1 /* 2 * Local APIC handling, local APIC timers 3 * 4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 5 * 6 * Fixes 7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8 * thanks to Eric Gilmore 9 * and Rolf G. Tews 10 * for testing these extensively. 11 * Maciej W. Rozycki : Various updates and fixes. 12 * Mikael Pettersson : Power Management for UP-APIC. 13 * Pavel Machek and 14 * Mikael Pettersson : PM converted to driver model. 15 */ 16 17 #include <linux/perf_event.h> 18 #include <linux/kernel_stat.h> 19 #include <linux/mc146818rtc.h> 20 #include <linux/acpi_pmtmr.h> 21 #include <linux/clockchips.h> 22 #include <linux/interrupt.h> 23 #include <linux/memblock.h> 24 #include <linux/ftrace.h> 25 #include <linux/ioport.h> 26 #include <linux/export.h> 27 #include <linux/syscore_ops.h> 28 #include <linux/delay.h> 29 #include <linux/timex.h> 30 #include <linux/i8253.h> 31 #include <linux/dmar.h> 32 #include <linux/init.h> 33 #include <linux/cpu.h> 34 #include <linux/dmi.h> 35 #include <linux/smp.h> 36 #include <linux/mm.h> 37 38 #include <asm/trace/irq_vectors.h> 39 #include <asm/irq_remapping.h> 40 #include <asm/perf_event.h> 41 #include <asm/x86_init.h> 42 #include <asm/pgalloc.h> 43 #include <linux/atomic.h> 44 #include <asm/mpspec.h> 45 #include <asm/i8259.h> 46 #include <asm/proto.h> 47 #include <asm/traps.h> 48 #include <asm/apic.h> 49 #include <asm/io_apic.h> 50 #include <asm/desc.h> 51 #include <asm/hpet.h> 52 #include <asm/mtrr.h> 53 #include <asm/time.h> 54 #include <asm/smp.h> 55 #include <asm/mce.h> 56 #include <asm/tsc.h> 57 #include <asm/hypervisor.h> 58 #include <asm/cpu_device_id.h> 59 #include <asm/intel-family.h> 60 #include <asm/irq_regs.h> 61 62 unsigned int num_processors; 63 64 unsigned disabled_cpus; 65 66 /* Processor that is doing the boot up */ 67 unsigned int boot_cpu_physical_apicid = -1U; 68 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); 69 70 u8 boot_cpu_apic_version; 71 72 /* 73 * The highest APIC ID seen during enumeration. 74 */ 75 static unsigned int max_physical_apicid; 76 77 /* 78 * Bitmask of physically existing CPUs: 79 */ 80 physid_mask_t phys_cpu_present_map; 81 82 /* 83 * Processor to be disabled specified by kernel parameter 84 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to 85 * avoid undefined behaviour caused by sending INIT from AP to BSP. 86 */ 87 static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID; 88 89 /* 90 * This variable controls which CPUs receive external NMIs. By default, 91 * external NMIs are delivered only to the BSP. 92 */ 93 static int apic_extnmi = APIC_EXTNMI_BSP; 94 95 /* 96 * Map cpu index to physical APIC ID 97 */ 98 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); 99 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); 100 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX); 101 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 102 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 103 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); 104 105 #ifdef CONFIG_X86_32 106 107 /* 108 * On x86_32, the mapping between cpu and logical apicid may vary 109 * depending on apic in use. The following early percpu variable is 110 * used for the mapping. This is where the behaviors of x86_64 and 32 111 * actually diverge. Let's keep it ugly for now. 112 */ 113 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); 114 115 /* Local APIC was disabled by the BIOS and enabled by the kernel */ 116 static int enabled_via_apicbase; 117 118 /* 119 * Handle interrupt mode configuration register (IMCR). 120 * This register controls whether the interrupt signals 121 * that reach the BSP come from the master PIC or from the 122 * local APIC. Before entering Symmetric I/O Mode, either 123 * the BIOS or the operating system must switch out of 124 * PIC Mode by changing the IMCR. 125 */ 126 static inline void imcr_pic_to_apic(void) 127 { 128 /* select IMCR register */ 129 outb(0x70, 0x22); 130 /* NMI and 8259 INTR go through APIC */ 131 outb(0x01, 0x23); 132 } 133 134 static inline void imcr_apic_to_pic(void) 135 { 136 /* select IMCR register */ 137 outb(0x70, 0x22); 138 /* NMI and 8259 INTR go directly to BSP */ 139 outb(0x00, 0x23); 140 } 141 #endif 142 143 /* 144 * Knob to control our willingness to enable the local APIC. 145 * 146 * +1=force-enable 147 */ 148 static int force_enable_local_apic __initdata; 149 150 /* 151 * APIC command line parameters 152 */ 153 static int __init parse_lapic(char *arg) 154 { 155 if (IS_ENABLED(CONFIG_X86_32) && !arg) 156 force_enable_local_apic = 1; 157 else if (arg && !strncmp(arg, "notscdeadline", 13)) 158 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 159 return 0; 160 } 161 early_param("lapic", parse_lapic); 162 163 #ifdef CONFIG_X86_64 164 static int apic_calibrate_pmtmr __initdata; 165 static __init int setup_apicpmtimer(char *s) 166 { 167 apic_calibrate_pmtmr = 1; 168 notsc_setup(NULL); 169 return 0; 170 } 171 __setup("apicpmtimer", setup_apicpmtimer); 172 #endif 173 174 unsigned long mp_lapic_addr; 175 int disable_apic; 176 /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 177 static int disable_apic_timer __initdata; 178 /* Local APIC timer works in C2 */ 179 int local_apic_timer_c2_ok; 180 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 181 182 /* 183 * Debug level, exported for io_apic.c 184 */ 185 unsigned int apic_verbosity; 186 187 int pic_mode; 188 189 /* Have we found an MP table */ 190 int smp_found_config; 191 192 static struct resource lapic_resource = { 193 .name = "Local APIC", 194 .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 195 }; 196 197 unsigned int lapic_timer_frequency = 0; 198 199 static void apic_pm_activate(void); 200 201 static unsigned long apic_phys; 202 203 /* 204 * Get the LAPIC version 205 */ 206 static inline int lapic_get_version(void) 207 { 208 return GET_APIC_VERSION(apic_read(APIC_LVR)); 209 } 210 211 /* 212 * Check, if the APIC is integrated or a separate chip 213 */ 214 static inline int lapic_is_integrated(void) 215 { 216 return APIC_INTEGRATED(lapic_get_version()); 217 } 218 219 /* 220 * Check, whether this is a modern or a first generation APIC 221 */ 222 static int modern_apic(void) 223 { 224 /* AMD systems use old APIC versions, so check the CPU */ 225 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 226 boot_cpu_data.x86 >= 0xf) 227 return 1; 228 229 /* Hygon systems use modern APIC */ 230 if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 231 return 1; 232 233 return lapic_get_version() >= 0x14; 234 } 235 236 /* 237 * right after this call apic become NOOP driven 238 * so apic->write/read doesn't do anything 239 */ 240 static void __init apic_disable(void) 241 { 242 pr_info("APIC: switched to apic NOOP\n"); 243 apic = &apic_noop; 244 } 245 246 void native_apic_wait_icr_idle(void) 247 { 248 while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 249 cpu_relax(); 250 } 251 252 u32 native_safe_apic_wait_icr_idle(void) 253 { 254 u32 send_status; 255 int timeout; 256 257 timeout = 0; 258 do { 259 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 260 if (!send_status) 261 break; 262 inc_irq_stat(icr_read_retry_count); 263 udelay(100); 264 } while (timeout++ < 1000); 265 266 return send_status; 267 } 268 269 void native_apic_icr_write(u32 low, u32 id) 270 { 271 unsigned long flags; 272 273 local_irq_save(flags); 274 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 275 apic_write(APIC_ICR, low); 276 local_irq_restore(flags); 277 } 278 279 u64 native_apic_icr_read(void) 280 { 281 u32 icr1, icr2; 282 283 icr2 = apic_read(APIC_ICR2); 284 icr1 = apic_read(APIC_ICR); 285 286 return icr1 | ((u64)icr2 << 32); 287 } 288 289 #ifdef CONFIG_X86_32 290 /** 291 * get_physical_broadcast - Get number of physical broadcast IDs 292 */ 293 int get_physical_broadcast(void) 294 { 295 return modern_apic() ? 0xff : 0xf; 296 } 297 #endif 298 299 /** 300 * lapic_get_maxlvt - get the maximum number of local vector table entries 301 */ 302 int lapic_get_maxlvt(void) 303 { 304 /* 305 * - we always have APIC integrated on 64bit mode 306 * - 82489DXs do not report # of LVT entries 307 */ 308 return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2; 309 } 310 311 /* 312 * Local APIC timer 313 */ 314 315 /* Clock divisor */ 316 #define APIC_DIVISOR 16 317 #define TSC_DIVISOR 8 318 319 /* 320 * This function sets up the local APIC timer, with a timeout of 321 * 'clocks' APIC bus clock. During calibration we actually call 322 * this function twice on the boot CPU, once with a bogus timeout 323 * value, second time for real. The other (noncalibrating) CPUs 324 * call this function only once, with the real, calibrated value. 325 * 326 * We do reads before writes even if unnecessary, to get around the 327 * P5 APIC double write bug. 328 */ 329 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 330 { 331 unsigned int lvtt_value, tmp_value; 332 333 lvtt_value = LOCAL_TIMER_VECTOR; 334 if (!oneshot) 335 lvtt_value |= APIC_LVT_TIMER_PERIODIC; 336 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 337 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; 338 339 if (!lapic_is_integrated()) 340 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 341 342 if (!irqen) 343 lvtt_value |= APIC_LVT_MASKED; 344 345 apic_write(APIC_LVTT, lvtt_value); 346 347 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { 348 /* 349 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, 350 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. 351 * According to Intel, MFENCE can do the serialization here. 352 */ 353 asm volatile("mfence" : : : "memory"); 354 355 printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); 356 return; 357 } 358 359 /* 360 * Divide PICLK by 16 361 */ 362 tmp_value = apic_read(APIC_TDCR); 363 apic_write(APIC_TDCR, 364 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 365 APIC_TDR_DIV_16); 366 367 if (!oneshot) 368 apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 369 } 370 371 /* 372 * Setup extended LVT, AMD specific 373 * 374 * Software should use the LVT offsets the BIOS provides. The offsets 375 * are determined by the subsystems using it like those for MCE 376 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 377 * are supported. Beginning with family 10h at least 4 offsets are 378 * available. 379 * 380 * Since the offsets must be consistent for all cores, we keep track 381 * of the LVT offsets in software and reserve the offset for the same 382 * vector also to be used on other cores. An offset is freed by 383 * setting the entry to APIC_EILVT_MASKED. 384 * 385 * If the BIOS is right, there should be no conflicts. Otherwise a 386 * "[Firmware Bug]: ..." error message is generated. However, if 387 * software does not properly determines the offsets, it is not 388 * necessarily a BIOS bug. 389 */ 390 391 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 392 393 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 394 { 395 return (old & APIC_EILVT_MASKED) 396 || (new == APIC_EILVT_MASKED) 397 || ((new & ~APIC_EILVT_MASKED) == old); 398 } 399 400 static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 401 { 402 unsigned int rsvd, vector; 403 404 if (offset >= APIC_EILVT_NR_MAX) 405 return ~0; 406 407 rsvd = atomic_read(&eilvt_offsets[offset]); 408 do { 409 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ 410 if (vector && !eilvt_entry_is_changeable(vector, new)) 411 /* may not change if vectors are different */ 412 return rsvd; 413 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 414 } while (rsvd != new); 415 416 rsvd &= ~APIC_EILVT_MASKED; 417 if (rsvd && rsvd != vector) 418 pr_info("LVT offset %d assigned for vector 0x%02x\n", 419 offset, rsvd); 420 421 return new; 422 } 423 424 /* 425 * If mask=1, the LVT entry does not generate interrupts while mask=0 426 * enables the vector. See also the BKDGs. Must be called with 427 * preemption disabled. 428 */ 429 430 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 431 { 432 unsigned long reg = APIC_EILVTn(offset); 433 unsigned int new, old, reserved; 434 435 new = (mask << 16) | (msg_type << 8) | vector; 436 old = apic_read(reg); 437 reserved = reserve_eilvt_offset(offset, new); 438 439 if (reserved != new) { 440 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 441 "vector 0x%x, but the register is already in use for " 442 "vector 0x%x on another cpu\n", 443 smp_processor_id(), reg, offset, new, reserved); 444 return -EINVAL; 445 } 446 447 if (!eilvt_entry_is_changeable(old, new)) { 448 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 449 "vector 0x%x, but the register is already in use for " 450 "vector 0x%x on this cpu\n", 451 smp_processor_id(), reg, offset, new, old); 452 return -EBUSY; 453 } 454 455 apic_write(reg, new); 456 457 return 0; 458 } 459 EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 460 461 /* 462 * Program the next event, relative to now 463 */ 464 static int lapic_next_event(unsigned long delta, 465 struct clock_event_device *evt) 466 { 467 apic_write(APIC_TMICT, delta); 468 return 0; 469 } 470 471 static int lapic_next_deadline(unsigned long delta, 472 struct clock_event_device *evt) 473 { 474 u64 tsc; 475 476 tsc = rdtsc(); 477 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); 478 return 0; 479 } 480 481 static int lapic_timer_shutdown(struct clock_event_device *evt) 482 { 483 unsigned int v; 484 485 /* Lapic used as dummy for broadcast ? */ 486 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 487 return 0; 488 489 v = apic_read(APIC_LVTT); 490 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 491 apic_write(APIC_LVTT, v); 492 apic_write(APIC_TMICT, 0); 493 return 0; 494 } 495 496 static inline int 497 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot) 498 { 499 /* Lapic used as dummy for broadcast ? */ 500 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 501 return 0; 502 503 __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1); 504 return 0; 505 } 506 507 static int lapic_timer_set_periodic(struct clock_event_device *evt) 508 { 509 return lapic_timer_set_periodic_oneshot(evt, false); 510 } 511 512 static int lapic_timer_set_oneshot(struct clock_event_device *evt) 513 { 514 return lapic_timer_set_periodic_oneshot(evt, true); 515 } 516 517 /* 518 * Local APIC timer broadcast function 519 */ 520 static void lapic_timer_broadcast(const struct cpumask *mask) 521 { 522 #ifdef CONFIG_SMP 523 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 524 #endif 525 } 526 527 528 /* 529 * The local apic timer can be used for any function which is CPU local. 530 */ 531 static struct clock_event_device lapic_clockevent = { 532 .name = "lapic", 533 .features = CLOCK_EVT_FEAT_PERIODIC | 534 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP 535 | CLOCK_EVT_FEAT_DUMMY, 536 .shift = 32, 537 .set_state_shutdown = lapic_timer_shutdown, 538 .set_state_periodic = lapic_timer_set_periodic, 539 .set_state_oneshot = lapic_timer_set_oneshot, 540 .set_state_oneshot_stopped = lapic_timer_shutdown, 541 .set_next_event = lapic_next_event, 542 .broadcast = lapic_timer_broadcast, 543 .rating = 100, 544 .irq = -1, 545 }; 546 static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 547 548 #define DEADLINE_MODEL_MATCH_FUNC(model, func) \ 549 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&func } 550 551 #define DEADLINE_MODEL_MATCH_REV(model, rev) \ 552 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)rev } 553 554 static u32 hsx_deadline_rev(void) 555 { 556 switch (boot_cpu_data.x86_stepping) { 557 case 0x02: return 0x3a; /* EP */ 558 case 0x04: return 0x0f; /* EX */ 559 } 560 561 return ~0U; 562 } 563 564 static u32 bdx_deadline_rev(void) 565 { 566 switch (boot_cpu_data.x86_stepping) { 567 case 0x02: return 0x00000011; 568 case 0x03: return 0x0700000e; 569 case 0x04: return 0x0f00000c; 570 case 0x05: return 0x0e000003; 571 } 572 573 return ~0U; 574 } 575 576 static u32 skx_deadline_rev(void) 577 { 578 switch (boot_cpu_data.x86_stepping) { 579 case 0x03: return 0x01000136; 580 case 0x04: return 0x02000014; 581 } 582 583 if (boot_cpu_data.x86_stepping > 4) 584 return 0; 585 586 return ~0U; 587 } 588 589 static const struct x86_cpu_id deadline_match[] = { 590 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X, hsx_deadline_rev), 591 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X, 0x0b000020), 592 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_XEON_D, bdx_deadline_rev), 593 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_SKYLAKE_X, skx_deadline_rev), 594 595 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_CORE, 0x22), 596 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_ULT, 0x20), 597 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_GT3E, 0x17), 598 599 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_CORE, 0x25), 600 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_GT3E, 0x17), 601 602 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE, 0xb2), 603 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP, 0xb2), 604 605 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE, 0x52), 606 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP, 0x52), 607 608 {}, 609 }; 610 611 static void apic_check_deadline_errata(void) 612 { 613 const struct x86_cpu_id *m; 614 u32 rev; 615 616 if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER) || 617 boot_cpu_has(X86_FEATURE_HYPERVISOR)) 618 return; 619 620 m = x86_match_cpu(deadline_match); 621 if (!m) 622 return; 623 624 /* 625 * Function pointers will have the MSB set due to address layout, 626 * immediate revisions will not. 627 */ 628 if ((long)m->driver_data < 0) 629 rev = ((u32 (*)(void))(m->driver_data))(); 630 else 631 rev = (u32)m->driver_data; 632 633 if (boot_cpu_data.microcode >= rev) 634 return; 635 636 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 637 pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; " 638 "please update microcode to version: 0x%x (or later)\n", rev); 639 } 640 641 /* 642 * Setup the local APIC timer for this CPU. Copy the initialized values 643 * of the boot CPU and register the clock event in the framework. 644 */ 645 static void setup_APIC_timer(void) 646 { 647 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 648 649 if (this_cpu_has(X86_FEATURE_ARAT)) { 650 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 651 /* Make LAPIC timer preferrable over percpu HPET */ 652 lapic_clockevent.rating = 150; 653 } 654 655 memcpy(levt, &lapic_clockevent, sizeof(*levt)); 656 levt->cpumask = cpumask_of(smp_processor_id()); 657 658 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 659 levt->name = "lapic-deadline"; 660 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | 661 CLOCK_EVT_FEAT_DUMMY); 662 levt->set_next_event = lapic_next_deadline; 663 clockevents_config_and_register(levt, 664 tsc_khz * (1000 / TSC_DIVISOR), 665 0xF, ~0UL); 666 } else 667 clockevents_register_device(levt); 668 } 669 670 /* 671 * Install the updated TSC frequency from recalibration at the TSC 672 * deadline clockevent devices. 673 */ 674 static void __lapic_update_tsc_freq(void *info) 675 { 676 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 677 678 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 679 return; 680 681 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR)); 682 } 683 684 void lapic_update_tsc_freq(void) 685 { 686 /* 687 * The clockevent device's ->mult and ->shift can both be 688 * changed. In order to avoid races, schedule the frequency 689 * update code on each CPU. 690 */ 691 on_each_cpu(__lapic_update_tsc_freq, NULL, 0); 692 } 693 694 /* 695 * In this functions we calibrate APIC bus clocks to the external timer. 696 * 697 * We want to do the calibration only once since we want to have local timer 698 * irqs syncron. CPUs connected by the same APIC bus have the very same bus 699 * frequency. 700 * 701 * This was previously done by reading the PIT/HPET and waiting for a wrap 702 * around to find out, that a tick has elapsed. I have a box, where the PIT 703 * readout is broken, so it never gets out of the wait loop again. This was 704 * also reported by others. 705 * 706 * Monitoring the jiffies value is inaccurate and the clockevents 707 * infrastructure allows us to do a simple substitution of the interrupt 708 * handler. 709 * 710 * The calibration routine also uses the pm_timer when possible, as the PIT 711 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 712 * back to normal later in the boot process). 713 */ 714 715 #define LAPIC_CAL_LOOPS (HZ/10) 716 717 static __initdata int lapic_cal_loops = -1; 718 static __initdata long lapic_cal_t1, lapic_cal_t2; 719 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 720 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 721 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 722 723 /* 724 * Temporary interrupt handler. 725 */ 726 static void __init lapic_cal_handler(struct clock_event_device *dev) 727 { 728 unsigned long long tsc = 0; 729 long tapic = apic_read(APIC_TMCCT); 730 unsigned long pm = acpi_pm_read_early(); 731 732 if (boot_cpu_has(X86_FEATURE_TSC)) 733 tsc = rdtsc(); 734 735 switch (lapic_cal_loops++) { 736 case 0: 737 lapic_cal_t1 = tapic; 738 lapic_cal_tsc1 = tsc; 739 lapic_cal_pm1 = pm; 740 lapic_cal_j1 = jiffies; 741 break; 742 743 case LAPIC_CAL_LOOPS: 744 lapic_cal_t2 = tapic; 745 lapic_cal_tsc2 = tsc; 746 if (pm < lapic_cal_pm1) 747 pm += ACPI_PM_OVRRUN; 748 lapic_cal_pm2 = pm; 749 lapic_cal_j2 = jiffies; 750 break; 751 } 752 } 753 754 static int __init 755 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 756 { 757 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 758 const long pm_thresh = pm_100ms / 100; 759 unsigned long mult; 760 u64 res; 761 762 #ifndef CONFIG_X86_PM_TIMER 763 return -1; 764 #endif 765 766 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 767 768 /* Check, if the PM timer is available */ 769 if (!deltapm) 770 return -1; 771 772 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 773 774 if (deltapm > (pm_100ms - pm_thresh) && 775 deltapm < (pm_100ms + pm_thresh)) { 776 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 777 return 0; 778 } 779 780 res = (((u64)deltapm) * mult) >> 22; 781 do_div(res, 1000000); 782 pr_warning("APIC calibration not consistent " 783 "with PM-Timer: %ldms instead of 100ms\n",(long)res); 784 785 /* Correct the lapic counter value */ 786 res = (((u64)(*delta)) * pm_100ms); 787 do_div(res, deltapm); 788 pr_info("APIC delta adjusted to PM-Timer: " 789 "%lu (%ld)\n", (unsigned long)res, *delta); 790 *delta = (long)res; 791 792 /* Correct the tsc counter value */ 793 if (boot_cpu_has(X86_FEATURE_TSC)) { 794 res = (((u64)(*deltatsc)) * pm_100ms); 795 do_div(res, deltapm); 796 apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 797 "PM-Timer: %lu (%ld)\n", 798 (unsigned long)res, *deltatsc); 799 *deltatsc = (long)res; 800 } 801 802 return 0; 803 } 804 805 static int __init calibrate_APIC_clock(void) 806 { 807 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 808 void (*real_handler)(struct clock_event_device *dev); 809 unsigned long deltaj; 810 long delta, deltatsc; 811 int pm_referenced = 0; 812 813 /** 814 * check if lapic timer has already been calibrated by platform 815 * specific routine, such as tsc calibration code. if so, we just fill 816 * in the clockevent structure and return. 817 */ 818 819 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 820 return 0; 821 } else if (lapic_timer_frequency) { 822 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", 823 lapic_timer_frequency); 824 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR, 825 TICK_NSEC, lapic_clockevent.shift); 826 lapic_clockevent.max_delta_ns = 827 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); 828 lapic_clockevent.max_delta_ticks = 0x7FFFFF; 829 lapic_clockevent.min_delta_ns = 830 clockevent_delta2ns(0xF, &lapic_clockevent); 831 lapic_clockevent.min_delta_ticks = 0xF; 832 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 833 return 0; 834 } 835 836 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 837 "calibrating APIC timer ...\n"); 838 839 local_irq_disable(); 840 841 /* Replace the global interrupt handler */ 842 real_handler = global_clock_event->event_handler; 843 global_clock_event->event_handler = lapic_cal_handler; 844 845 /* 846 * Setup the APIC counter to maximum. There is no way the lapic 847 * can underflow in the 100ms detection time frame 848 */ 849 __setup_APIC_LVTT(0xffffffff, 0, 0); 850 851 /* Let the interrupts run */ 852 local_irq_enable(); 853 854 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 855 cpu_relax(); 856 857 local_irq_disable(); 858 859 /* Restore the real event handler */ 860 global_clock_event->event_handler = real_handler; 861 862 /* Build delta t1-t2 as apic timer counts down */ 863 delta = lapic_cal_t1 - lapic_cal_t2; 864 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 865 866 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 867 868 /* we trust the PM based calibration if possible */ 869 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 870 &delta, &deltatsc); 871 872 /* Calculate the scaled math multiplication factor */ 873 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 874 lapic_clockevent.shift); 875 lapic_clockevent.max_delta_ns = 876 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 877 lapic_clockevent.max_delta_ticks = 0x7FFFFFFF; 878 lapic_clockevent.min_delta_ns = 879 clockevent_delta2ns(0xF, &lapic_clockevent); 880 lapic_clockevent.min_delta_ticks = 0xF; 881 882 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 883 884 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 885 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 886 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 887 lapic_timer_frequency); 888 889 if (boot_cpu_has(X86_FEATURE_TSC)) { 890 apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 891 "%ld.%04ld MHz.\n", 892 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 893 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 894 } 895 896 apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 897 "%u.%04u MHz.\n", 898 lapic_timer_frequency / (1000000 / HZ), 899 lapic_timer_frequency % (1000000 / HZ)); 900 901 /* 902 * Do a sanity check on the APIC calibration result 903 */ 904 if (lapic_timer_frequency < (1000000 / HZ)) { 905 local_irq_enable(); 906 pr_warning("APIC frequency too slow, disabling apic timer\n"); 907 return -1; 908 } 909 910 levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 911 912 /* 913 * PM timer calibration failed or not turned on 914 * so lets try APIC timer based calibration 915 */ 916 if (!pm_referenced) { 917 apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 918 919 /* 920 * Setup the apic timer manually 921 */ 922 levt->event_handler = lapic_cal_handler; 923 lapic_timer_set_periodic(levt); 924 lapic_cal_loops = -1; 925 926 /* Let the interrupts run */ 927 local_irq_enable(); 928 929 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 930 cpu_relax(); 931 932 /* Stop the lapic timer */ 933 local_irq_disable(); 934 lapic_timer_shutdown(levt); 935 936 /* Jiffies delta */ 937 deltaj = lapic_cal_j2 - lapic_cal_j1; 938 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 939 940 /* Check, if the jiffies result is consistent */ 941 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 942 apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 943 else 944 levt->features |= CLOCK_EVT_FEAT_DUMMY; 945 } 946 local_irq_enable(); 947 948 if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 949 pr_warning("APIC timer disabled due to verification failure\n"); 950 return -1; 951 } 952 953 return 0; 954 } 955 956 /* 957 * Setup the boot APIC 958 * 959 * Calibrate and verify the result. 960 */ 961 void __init setup_boot_APIC_clock(void) 962 { 963 /* 964 * The local apic timer can be disabled via the kernel 965 * commandline or from the CPU detection code. Register the lapic 966 * timer as a dummy clock event source on SMP systems, so the 967 * broadcast mechanism is used. On UP systems simply ignore it. 968 */ 969 if (disable_apic_timer) { 970 pr_info("Disabling APIC timer\n"); 971 /* No broadcast on UP ! */ 972 if (num_possible_cpus() > 1) { 973 lapic_clockevent.mult = 1; 974 setup_APIC_timer(); 975 } 976 return; 977 } 978 979 if (calibrate_APIC_clock()) { 980 /* No broadcast on UP ! */ 981 if (num_possible_cpus() > 1) 982 setup_APIC_timer(); 983 return; 984 } 985 986 /* 987 * If nmi_watchdog is set to IO_APIC, we need the 988 * PIT/HPET going. Otherwise register lapic as a dummy 989 * device. 990 */ 991 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 992 993 /* Setup the lapic or request the broadcast */ 994 setup_APIC_timer(); 995 amd_e400_c1e_apic_setup(); 996 } 997 998 void setup_secondary_APIC_clock(void) 999 { 1000 setup_APIC_timer(); 1001 amd_e400_c1e_apic_setup(); 1002 } 1003 1004 /* 1005 * The guts of the apic timer interrupt 1006 */ 1007 static void local_apic_timer_interrupt(void) 1008 { 1009 struct clock_event_device *evt = this_cpu_ptr(&lapic_events); 1010 1011 /* 1012 * Normally we should not be here till LAPIC has been initialized but 1013 * in some cases like kdump, its possible that there is a pending LAPIC 1014 * timer interrupt from previous kernel's context and is delivered in 1015 * new kernel the moment interrupts are enabled. 1016 * 1017 * Interrupts are enabled early and LAPIC is setup much later, hence 1018 * its possible that when we get here evt->event_handler is NULL. 1019 * Check for event_handler being NULL and discard the interrupt as 1020 * spurious. 1021 */ 1022 if (!evt->event_handler) { 1023 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", 1024 smp_processor_id()); 1025 /* Switch it off */ 1026 lapic_timer_shutdown(evt); 1027 return; 1028 } 1029 1030 /* 1031 * the NMI deadlock-detector uses this. 1032 */ 1033 inc_irq_stat(apic_timer_irqs); 1034 1035 evt->event_handler(evt); 1036 } 1037 1038 /* 1039 * Local APIC timer interrupt. This is the most natural way for doing 1040 * local interrupts, but local timer interrupts can be emulated by 1041 * broadcast interrupts too. [in case the hw doesn't support APIC timers] 1042 * 1043 * [ if a single-CPU system runs an SMP kernel then we call the local 1044 * interrupt as well. Thus we cannot inline the local irq ... ] 1045 */ 1046 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 1047 { 1048 struct pt_regs *old_regs = set_irq_regs(regs); 1049 1050 /* 1051 * NOTE! We'd better ACK the irq immediately, 1052 * because timer handling can be slow. 1053 * 1054 * update_process_times() expects us to have done irq_enter(). 1055 * Besides, if we don't timer interrupts ignore the global 1056 * interrupt lock, which is the WrongThing (tm) to do. 1057 */ 1058 entering_ack_irq(); 1059 trace_local_timer_entry(LOCAL_TIMER_VECTOR); 1060 local_apic_timer_interrupt(); 1061 trace_local_timer_exit(LOCAL_TIMER_VECTOR); 1062 exiting_irq(); 1063 1064 set_irq_regs(old_regs); 1065 } 1066 1067 int setup_profiling_timer(unsigned int multiplier) 1068 { 1069 return -EINVAL; 1070 } 1071 1072 /* 1073 * Local APIC start and shutdown 1074 */ 1075 1076 /** 1077 * clear_local_APIC - shutdown the local APIC 1078 * 1079 * This is called, when a CPU is disabled and before rebooting, so the state of 1080 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 1081 * leftovers during boot. 1082 */ 1083 void clear_local_APIC(void) 1084 { 1085 int maxlvt; 1086 u32 v; 1087 1088 /* APIC hasn't been mapped yet */ 1089 if (!x2apic_mode && !apic_phys) 1090 return; 1091 1092 maxlvt = lapic_get_maxlvt(); 1093 /* 1094 * Masking an LVT entry can trigger a local APIC error 1095 * if the vector is zero. Mask LVTERR first to prevent this. 1096 */ 1097 if (maxlvt >= 3) { 1098 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 1099 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 1100 } 1101 /* 1102 * Careful: we have to set masks only first to deassert 1103 * any level-triggered sources. 1104 */ 1105 v = apic_read(APIC_LVTT); 1106 apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 1107 v = apic_read(APIC_LVT0); 1108 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 1109 v = apic_read(APIC_LVT1); 1110 apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 1111 if (maxlvt >= 4) { 1112 v = apic_read(APIC_LVTPC); 1113 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 1114 } 1115 1116 /* lets not touch this if we didn't frob it */ 1117 #ifdef CONFIG_X86_THERMAL_VECTOR 1118 if (maxlvt >= 5) { 1119 v = apic_read(APIC_LVTTHMR); 1120 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 1121 } 1122 #endif 1123 #ifdef CONFIG_X86_MCE_INTEL 1124 if (maxlvt >= 6) { 1125 v = apic_read(APIC_LVTCMCI); 1126 if (!(v & APIC_LVT_MASKED)) 1127 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 1128 } 1129 #endif 1130 1131 /* 1132 * Clean APIC state for other OSs: 1133 */ 1134 apic_write(APIC_LVTT, APIC_LVT_MASKED); 1135 apic_write(APIC_LVT0, APIC_LVT_MASKED); 1136 apic_write(APIC_LVT1, APIC_LVT_MASKED); 1137 if (maxlvt >= 3) 1138 apic_write(APIC_LVTERR, APIC_LVT_MASKED); 1139 if (maxlvt >= 4) 1140 apic_write(APIC_LVTPC, APIC_LVT_MASKED); 1141 1142 /* Integrated APIC (!82489DX) ? */ 1143 if (lapic_is_integrated()) { 1144 if (maxlvt > 3) 1145 /* Clear ESR due to Pentium errata 3AP and 11AP */ 1146 apic_write(APIC_ESR, 0); 1147 apic_read(APIC_ESR); 1148 } 1149 } 1150 1151 /** 1152 * disable_local_APIC - clear and disable the local APIC 1153 */ 1154 void disable_local_APIC(void) 1155 { 1156 unsigned int value; 1157 1158 /* APIC hasn't been mapped yet */ 1159 if (!x2apic_mode && !apic_phys) 1160 return; 1161 1162 clear_local_APIC(); 1163 1164 /* 1165 * Disable APIC (implies clearing of registers 1166 * for 82489DX!). 1167 */ 1168 value = apic_read(APIC_SPIV); 1169 value &= ~APIC_SPIV_APIC_ENABLED; 1170 apic_write(APIC_SPIV, value); 1171 1172 #ifdef CONFIG_X86_32 1173 /* 1174 * When LAPIC was disabled by the BIOS and enabled by the kernel, 1175 * restore the disabled state. 1176 */ 1177 if (enabled_via_apicbase) { 1178 unsigned int l, h; 1179 1180 rdmsr(MSR_IA32_APICBASE, l, h); 1181 l &= ~MSR_IA32_APICBASE_ENABLE; 1182 wrmsr(MSR_IA32_APICBASE, l, h); 1183 } 1184 #endif 1185 } 1186 1187 /* 1188 * If Linux enabled the LAPIC against the BIOS default disable it down before 1189 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 1190 * not power-off. Additionally clear all LVT entries before disable_local_APIC 1191 * for the case where Linux didn't enable the LAPIC. 1192 */ 1193 void lapic_shutdown(void) 1194 { 1195 unsigned long flags; 1196 1197 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) 1198 return; 1199 1200 local_irq_save(flags); 1201 1202 #ifdef CONFIG_X86_32 1203 if (!enabled_via_apicbase) 1204 clear_local_APIC(); 1205 else 1206 #endif 1207 disable_local_APIC(); 1208 1209 1210 local_irq_restore(flags); 1211 } 1212 1213 /** 1214 * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1215 */ 1216 void __init sync_Arb_IDs(void) 1217 { 1218 /* 1219 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1220 * needed on AMD. 1221 */ 1222 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1223 return; 1224 1225 /* 1226 * Wait for idle. 1227 */ 1228 apic_wait_icr_idle(); 1229 1230 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1231 apic_write(APIC_ICR, APIC_DEST_ALLINC | 1232 APIC_INT_LEVELTRIG | APIC_DM_INIT); 1233 } 1234 1235 enum apic_intr_mode_id apic_intr_mode; 1236 1237 static int __init apic_intr_mode_select(void) 1238 { 1239 /* Check kernel option */ 1240 if (disable_apic) { 1241 pr_info("APIC disabled via kernel command line\n"); 1242 return APIC_PIC; 1243 } 1244 1245 /* Check BIOS */ 1246 #ifdef CONFIG_X86_64 1247 /* On 64-bit, the APIC must be integrated, Check local APIC only */ 1248 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1249 disable_apic = 1; 1250 pr_info("APIC disabled by BIOS\n"); 1251 return APIC_PIC; 1252 } 1253 #else 1254 /* On 32-bit, the APIC may be integrated APIC or 82489DX */ 1255 1256 /* Neither 82489DX nor integrated APIC ? */ 1257 if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) { 1258 disable_apic = 1; 1259 return APIC_PIC; 1260 } 1261 1262 /* If the BIOS pretends there is an integrated APIC ? */ 1263 if (!boot_cpu_has(X86_FEATURE_APIC) && 1264 APIC_INTEGRATED(boot_cpu_apic_version)) { 1265 disable_apic = 1; 1266 pr_err(FW_BUG "Local APIC %d not detected, force emulation\n", 1267 boot_cpu_physical_apicid); 1268 return APIC_PIC; 1269 } 1270 #endif 1271 1272 /* Check MP table or ACPI MADT configuration */ 1273 if (!smp_found_config) { 1274 disable_ioapic_support(); 1275 if (!acpi_lapic) { 1276 pr_info("APIC: ACPI MADT or MP tables are not detected\n"); 1277 return APIC_VIRTUAL_WIRE_NO_CONFIG; 1278 } 1279 return APIC_VIRTUAL_WIRE; 1280 } 1281 1282 #ifdef CONFIG_SMP 1283 /* If SMP should be disabled, then really disable it! */ 1284 if (!setup_max_cpus) { 1285 pr_info("APIC: SMP mode deactivated\n"); 1286 return APIC_SYMMETRIC_IO_NO_ROUTING; 1287 } 1288 1289 if (read_apic_id() != boot_cpu_physical_apicid) { 1290 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1291 read_apic_id(), boot_cpu_physical_apicid); 1292 /* Or can we switch back to PIC here? */ 1293 } 1294 #endif 1295 1296 return APIC_SYMMETRIC_IO; 1297 } 1298 1299 /* 1300 * An initial setup of the virtual wire mode. 1301 */ 1302 void __init init_bsp_APIC(void) 1303 { 1304 unsigned int value; 1305 1306 /* 1307 * Don't do the setup now if we have a SMP BIOS as the 1308 * through-I/O-APIC virtual wire mode might be active. 1309 */ 1310 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC)) 1311 return; 1312 1313 /* 1314 * Do not trust the local APIC being empty at bootup. 1315 */ 1316 clear_local_APIC(); 1317 1318 /* 1319 * Enable APIC. 1320 */ 1321 value = apic_read(APIC_SPIV); 1322 value &= ~APIC_VECTOR_MASK; 1323 value |= APIC_SPIV_APIC_ENABLED; 1324 1325 #ifdef CONFIG_X86_32 1326 /* This bit is reserved on P4/Xeon and should be cleared */ 1327 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1328 (boot_cpu_data.x86 == 15)) 1329 value &= ~APIC_SPIV_FOCUS_DISABLED; 1330 else 1331 #endif 1332 value |= APIC_SPIV_FOCUS_DISABLED; 1333 value |= SPURIOUS_APIC_VECTOR; 1334 apic_write(APIC_SPIV, value); 1335 1336 /* 1337 * Set up the virtual wire mode. 1338 */ 1339 apic_write(APIC_LVT0, APIC_DM_EXTINT); 1340 value = APIC_DM_NMI; 1341 if (!lapic_is_integrated()) /* 82489DX */ 1342 value |= APIC_LVT_LEVEL_TRIGGER; 1343 if (apic_extnmi == APIC_EXTNMI_NONE) 1344 value |= APIC_LVT_MASKED; 1345 apic_write(APIC_LVT1, value); 1346 } 1347 1348 /* Init the interrupt delivery mode for the BSP */ 1349 void __init apic_intr_mode_init(void) 1350 { 1351 bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT); 1352 1353 apic_intr_mode = apic_intr_mode_select(); 1354 1355 switch (apic_intr_mode) { 1356 case APIC_PIC: 1357 pr_info("APIC: Keep in PIC mode(8259)\n"); 1358 return; 1359 case APIC_VIRTUAL_WIRE: 1360 pr_info("APIC: Switch to virtual wire mode setup\n"); 1361 default_setup_apic_routing(); 1362 break; 1363 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1364 pr_info("APIC: Switch to virtual wire mode setup with no configuration\n"); 1365 upmode = true; 1366 default_setup_apic_routing(); 1367 break; 1368 case APIC_SYMMETRIC_IO: 1369 pr_info("APIC: Switch to symmetric I/O mode setup\n"); 1370 default_setup_apic_routing(); 1371 break; 1372 case APIC_SYMMETRIC_IO_NO_ROUTING: 1373 pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n"); 1374 break; 1375 } 1376 1377 apic_bsp_setup(upmode); 1378 } 1379 1380 static void lapic_setup_esr(void) 1381 { 1382 unsigned int oldvalue, value, maxlvt; 1383 1384 if (!lapic_is_integrated()) { 1385 pr_info("No ESR for 82489DX.\n"); 1386 return; 1387 } 1388 1389 if (apic->disable_esr) { 1390 /* 1391 * Something untraceable is creating bad interrupts on 1392 * secondary quads ... for the moment, just leave the 1393 * ESR disabled - we can't do anything useful with the 1394 * errors anyway - mbligh 1395 */ 1396 pr_info("Leaving ESR disabled.\n"); 1397 return; 1398 } 1399 1400 maxlvt = lapic_get_maxlvt(); 1401 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1402 apic_write(APIC_ESR, 0); 1403 oldvalue = apic_read(APIC_ESR); 1404 1405 /* enables sending errors */ 1406 value = ERROR_APIC_VECTOR; 1407 apic_write(APIC_LVTERR, value); 1408 1409 /* 1410 * spec says clear errors after enabling vector. 1411 */ 1412 if (maxlvt > 3) 1413 apic_write(APIC_ESR, 0); 1414 value = apic_read(APIC_ESR); 1415 if (value != oldvalue) 1416 apic_printk(APIC_VERBOSE, "ESR value before enabling " 1417 "vector: 0x%08x after: 0x%08x\n", 1418 oldvalue, value); 1419 } 1420 1421 static void apic_pending_intr_clear(void) 1422 { 1423 long long max_loops = cpu_khz ? cpu_khz : 1000000; 1424 unsigned long long tsc = 0, ntsc; 1425 unsigned int queued; 1426 unsigned long value; 1427 int i, j, acked = 0; 1428 1429 if (boot_cpu_has(X86_FEATURE_TSC)) 1430 tsc = rdtsc(); 1431 /* 1432 * After a crash, we no longer service the interrupts and a pending 1433 * interrupt from previous kernel might still have ISR bit set. 1434 * 1435 * Most probably by now CPU has serviced that pending interrupt and 1436 * it might not have done the ack_APIC_irq() because it thought, 1437 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1438 * does not clear the ISR bit and cpu thinks it has already serivced 1439 * the interrupt. Hence a vector might get locked. It was noticed 1440 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1441 */ 1442 do { 1443 queued = 0; 1444 for (i = APIC_ISR_NR - 1; i >= 0; i--) 1445 queued |= apic_read(APIC_IRR + i*0x10); 1446 1447 for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1448 value = apic_read(APIC_ISR + i*0x10); 1449 for_each_set_bit(j, &value, 32) { 1450 ack_APIC_irq(); 1451 acked++; 1452 } 1453 } 1454 if (acked > 256) { 1455 pr_err("LAPIC pending interrupts after %d EOI\n", acked); 1456 break; 1457 } 1458 if (queued) { 1459 if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) { 1460 ntsc = rdtsc(); 1461 max_loops = (cpu_khz << 10) - (ntsc - tsc); 1462 } else { 1463 max_loops--; 1464 } 1465 } 1466 } while (queued && max_loops > 0); 1467 WARN_ON(max_loops <= 0); 1468 } 1469 1470 /** 1471 * setup_local_APIC - setup the local APIC 1472 * 1473 * Used to setup local APIC while initializing BSP or bringing up APs. 1474 * Always called with preemption disabled. 1475 */ 1476 static void setup_local_APIC(void) 1477 { 1478 int cpu = smp_processor_id(); 1479 unsigned int value; 1480 #ifdef CONFIG_X86_32 1481 int logical_apicid, ldr_apicid; 1482 #endif 1483 1484 1485 if (disable_apic) { 1486 disable_ioapic_support(); 1487 return; 1488 } 1489 1490 #ifdef CONFIG_X86_32 1491 /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1492 if (lapic_is_integrated() && apic->disable_esr) { 1493 apic_write(APIC_ESR, 0); 1494 apic_write(APIC_ESR, 0); 1495 apic_write(APIC_ESR, 0); 1496 apic_write(APIC_ESR, 0); 1497 } 1498 #endif 1499 perf_events_lapic_init(); 1500 1501 /* 1502 * Double-check whether this APIC is really registered. 1503 * This is meaningless in clustered apic mode, so we skip it. 1504 */ 1505 BUG_ON(!apic->apic_id_registered()); 1506 1507 /* 1508 * Intel recommends to set DFR, LDR and TPR before enabling 1509 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1510 * document number 292116). So here it goes... 1511 */ 1512 apic->init_apic_ldr(); 1513 1514 #ifdef CONFIG_X86_32 1515 /* 1516 * APIC LDR is initialized. If logical_apicid mapping was 1517 * initialized during get_smp_config(), make sure it matches the 1518 * actual value. 1519 */ 1520 logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu); 1521 ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 1522 WARN_ON(logical_apicid != BAD_APICID && logical_apicid != ldr_apicid); 1523 /* always use the value from LDR */ 1524 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid; 1525 #endif 1526 1527 /* 1528 * Set Task Priority to 'accept all'. We never change this 1529 * later on. 1530 */ 1531 value = apic_read(APIC_TASKPRI); 1532 value &= ~APIC_TPRI_MASK; 1533 apic_write(APIC_TASKPRI, value); 1534 1535 apic_pending_intr_clear(); 1536 1537 /* 1538 * Now that we are all set up, enable the APIC 1539 */ 1540 value = apic_read(APIC_SPIV); 1541 value &= ~APIC_VECTOR_MASK; 1542 /* 1543 * Enable APIC 1544 */ 1545 value |= APIC_SPIV_APIC_ENABLED; 1546 1547 #ifdef CONFIG_X86_32 1548 /* 1549 * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1550 * certain networking cards. If high frequency interrupts are 1551 * happening on a particular IOAPIC pin, plus the IOAPIC routing 1552 * entry is masked/unmasked at a high rate as well then sooner or 1553 * later IOAPIC line gets 'stuck', no more interrupts are received 1554 * from the device. If focus CPU is disabled then the hang goes 1555 * away, oh well :-( 1556 * 1557 * [ This bug can be reproduced easily with a level-triggered 1558 * PCI Ne2000 networking cards and PII/PIII processors, dual 1559 * BX chipset. ] 1560 */ 1561 /* 1562 * Actually disabling the focus CPU check just makes the hang less 1563 * frequent as it makes the interrupt distributon model be more 1564 * like LRU than MRU (the short-term load is more even across CPUs). 1565 */ 1566 1567 /* 1568 * - enable focus processor (bit==0) 1569 * - 64bit mode always use processor focus 1570 * so no need to set it 1571 */ 1572 value &= ~APIC_SPIV_FOCUS_DISABLED; 1573 #endif 1574 1575 /* 1576 * Set spurious IRQ vector 1577 */ 1578 value |= SPURIOUS_APIC_VECTOR; 1579 apic_write(APIC_SPIV, value); 1580 1581 /* 1582 * Set up LVT0, LVT1: 1583 * 1584 * set up through-local-APIC on the boot CPU's LINT0. This is not 1585 * strictly necessary in pure symmetric-IO mode, but sometimes 1586 * we delegate interrupts to the 8259A. 1587 */ 1588 /* 1589 * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1590 */ 1591 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1592 if (!cpu && (pic_mode || !value || skip_ioapic_setup)) { 1593 value = APIC_DM_EXTINT; 1594 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1595 } else { 1596 value = APIC_DM_EXTINT | APIC_LVT_MASKED; 1597 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1598 } 1599 apic_write(APIC_LVT0, value); 1600 1601 /* 1602 * Only the BSP sees the LINT1 NMI signal by default. This can be 1603 * modified by apic_extnmi= boot option. 1604 */ 1605 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) || 1606 apic_extnmi == APIC_EXTNMI_ALL) 1607 value = APIC_DM_NMI; 1608 else 1609 value = APIC_DM_NMI | APIC_LVT_MASKED; 1610 1611 /* Is 82489DX ? */ 1612 if (!lapic_is_integrated()) 1613 value |= APIC_LVT_LEVEL_TRIGGER; 1614 apic_write(APIC_LVT1, value); 1615 1616 #ifdef CONFIG_X86_MCE_INTEL 1617 /* Recheck CMCI information after local APIC is up on CPU #0 */ 1618 if (!cpu) 1619 cmci_recheck(); 1620 #endif 1621 } 1622 1623 static void end_local_APIC_setup(void) 1624 { 1625 lapic_setup_esr(); 1626 1627 #ifdef CONFIG_X86_32 1628 { 1629 unsigned int value; 1630 /* Disable the local apic timer */ 1631 value = apic_read(APIC_LVTT); 1632 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1633 apic_write(APIC_LVTT, value); 1634 } 1635 #endif 1636 1637 apic_pm_activate(); 1638 } 1639 1640 /* 1641 * APIC setup function for application processors. Called from smpboot.c 1642 */ 1643 void apic_ap_setup(void) 1644 { 1645 setup_local_APIC(); 1646 end_local_APIC_setup(); 1647 } 1648 1649 #ifdef CONFIG_X86_X2APIC 1650 int x2apic_mode; 1651 1652 enum { 1653 X2APIC_OFF, 1654 X2APIC_ON, 1655 X2APIC_DISABLED, 1656 }; 1657 static int x2apic_state; 1658 1659 static void __x2apic_disable(void) 1660 { 1661 u64 msr; 1662 1663 if (!boot_cpu_has(X86_FEATURE_APIC)) 1664 return; 1665 1666 rdmsrl(MSR_IA32_APICBASE, msr); 1667 if (!(msr & X2APIC_ENABLE)) 1668 return; 1669 /* Disable xapic and x2apic first and then reenable xapic mode */ 1670 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); 1671 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); 1672 printk_once(KERN_INFO "x2apic disabled\n"); 1673 } 1674 1675 static void __x2apic_enable(void) 1676 { 1677 u64 msr; 1678 1679 rdmsrl(MSR_IA32_APICBASE, msr); 1680 if (msr & X2APIC_ENABLE) 1681 return; 1682 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); 1683 printk_once(KERN_INFO "x2apic enabled\n"); 1684 } 1685 1686 static int __init setup_nox2apic(char *str) 1687 { 1688 if (x2apic_enabled()) { 1689 int apicid = native_apic_msr_read(APIC_ID); 1690 1691 if (apicid >= 255) { 1692 pr_warning("Apicid: %08x, cannot enforce nox2apic\n", 1693 apicid); 1694 return 0; 1695 } 1696 pr_warning("x2apic already enabled.\n"); 1697 __x2apic_disable(); 1698 } 1699 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 1700 x2apic_state = X2APIC_DISABLED; 1701 x2apic_mode = 0; 1702 return 0; 1703 } 1704 early_param("nox2apic", setup_nox2apic); 1705 1706 /* Called from cpu_init() to enable x2apic on (secondary) cpus */ 1707 void x2apic_setup(void) 1708 { 1709 /* 1710 * If x2apic is not in ON state, disable it if already enabled 1711 * from BIOS. 1712 */ 1713 if (x2apic_state != X2APIC_ON) { 1714 __x2apic_disable(); 1715 return; 1716 } 1717 __x2apic_enable(); 1718 } 1719 1720 static __init void x2apic_disable(void) 1721 { 1722 u32 x2apic_id, state = x2apic_state; 1723 1724 x2apic_mode = 0; 1725 x2apic_state = X2APIC_DISABLED; 1726 1727 if (state != X2APIC_ON) 1728 return; 1729 1730 x2apic_id = read_apic_id(); 1731 if (x2apic_id >= 255) 1732 panic("Cannot disable x2apic, id: %08x\n", x2apic_id); 1733 1734 __x2apic_disable(); 1735 register_lapic_address(mp_lapic_addr); 1736 } 1737 1738 static __init void x2apic_enable(void) 1739 { 1740 if (x2apic_state != X2APIC_OFF) 1741 return; 1742 1743 x2apic_mode = 1; 1744 x2apic_state = X2APIC_ON; 1745 __x2apic_enable(); 1746 } 1747 1748 static __init void try_to_enable_x2apic(int remap_mode) 1749 { 1750 if (x2apic_state == X2APIC_DISABLED) 1751 return; 1752 1753 if (remap_mode != IRQ_REMAP_X2APIC_MODE) { 1754 /* IR is required if there is APIC ID > 255 even when running 1755 * under KVM 1756 */ 1757 if (max_physical_apicid > 255 || 1758 !x86_init.hyper.x2apic_available()) { 1759 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); 1760 x2apic_disable(); 1761 return; 1762 } 1763 1764 /* 1765 * without IR all CPUs can be addressed by IOAPIC/MSI 1766 * only in physical mode 1767 */ 1768 x2apic_phys = 1; 1769 } 1770 x2apic_enable(); 1771 } 1772 1773 void __init check_x2apic(void) 1774 { 1775 if (x2apic_enabled()) { 1776 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); 1777 x2apic_mode = 1; 1778 x2apic_state = X2APIC_ON; 1779 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) { 1780 x2apic_state = X2APIC_DISABLED; 1781 } 1782 } 1783 #else /* CONFIG_X86_X2APIC */ 1784 static int __init validate_x2apic(void) 1785 { 1786 if (!apic_is_x2apic_enabled()) 1787 return 0; 1788 /* 1789 * Checkme: Can we simply turn off x2apic here instead of panic? 1790 */ 1791 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n"); 1792 } 1793 early_initcall(validate_x2apic); 1794 1795 static inline void try_to_enable_x2apic(int remap_mode) { } 1796 static inline void __x2apic_enable(void) { } 1797 #endif /* !CONFIG_X86_X2APIC */ 1798 1799 void __init enable_IR_x2apic(void) 1800 { 1801 unsigned long flags; 1802 int ret, ir_stat; 1803 1804 if (skip_ioapic_setup) { 1805 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); 1806 return; 1807 } 1808 1809 ir_stat = irq_remapping_prepare(); 1810 if (ir_stat < 0 && !x2apic_supported()) 1811 return; 1812 1813 ret = save_ioapic_entries(); 1814 if (ret) { 1815 pr_info("Saving IO-APIC state failed: %d\n", ret); 1816 return; 1817 } 1818 1819 local_irq_save(flags); 1820 legacy_pic->mask_all(); 1821 mask_ioapic_entries(); 1822 1823 /* If irq_remapping_prepare() succeeded, try to enable it */ 1824 if (ir_stat >= 0) 1825 ir_stat = irq_remapping_enable(); 1826 /* ir_stat contains the remap mode or an error code */ 1827 try_to_enable_x2apic(ir_stat); 1828 1829 if (ir_stat < 0) 1830 restore_ioapic_entries(); 1831 legacy_pic->restore_mask(); 1832 local_irq_restore(flags); 1833 } 1834 1835 #ifdef CONFIG_X86_64 1836 /* 1837 * Detect and enable local APICs on non-SMP boards. 1838 * Original code written by Keir Fraser. 1839 * On AMD64 we trust the BIOS - if it says no APIC it is likely 1840 * not correctly set up (usually the APIC timer won't work etc.) 1841 */ 1842 static int __init detect_init_APIC(void) 1843 { 1844 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1845 pr_info("No local APIC present\n"); 1846 return -1; 1847 } 1848 1849 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1850 return 0; 1851 } 1852 #else 1853 1854 static int __init apic_verify(void) 1855 { 1856 u32 features, h, l; 1857 1858 /* 1859 * The APIC feature bit should now be enabled 1860 * in `cpuid' 1861 */ 1862 features = cpuid_edx(1); 1863 if (!(features & (1 << X86_FEATURE_APIC))) { 1864 pr_warning("Could not enable APIC!\n"); 1865 return -1; 1866 } 1867 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1868 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1869 1870 /* The BIOS may have set up the APIC at some other address */ 1871 if (boot_cpu_data.x86 >= 6) { 1872 rdmsr(MSR_IA32_APICBASE, l, h); 1873 if (l & MSR_IA32_APICBASE_ENABLE) 1874 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1875 } 1876 1877 pr_info("Found and enabled local APIC!\n"); 1878 return 0; 1879 } 1880 1881 int __init apic_force_enable(unsigned long addr) 1882 { 1883 u32 h, l; 1884 1885 if (disable_apic) 1886 return -1; 1887 1888 /* 1889 * Some BIOSes disable the local APIC in the APIC_BASE 1890 * MSR. This can only be done in software for Intel P6 or later 1891 * and AMD K7 (Model > 1) or later. 1892 */ 1893 if (boot_cpu_data.x86 >= 6) { 1894 rdmsr(MSR_IA32_APICBASE, l, h); 1895 if (!(l & MSR_IA32_APICBASE_ENABLE)) { 1896 pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 1897 l &= ~MSR_IA32_APICBASE_BASE; 1898 l |= MSR_IA32_APICBASE_ENABLE | addr; 1899 wrmsr(MSR_IA32_APICBASE, l, h); 1900 enabled_via_apicbase = 1; 1901 } 1902 } 1903 return apic_verify(); 1904 } 1905 1906 /* 1907 * Detect and initialize APIC 1908 */ 1909 static int __init detect_init_APIC(void) 1910 { 1911 /* Disabled by kernel option? */ 1912 if (disable_apic) 1913 return -1; 1914 1915 switch (boot_cpu_data.x86_vendor) { 1916 case X86_VENDOR_AMD: 1917 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1918 (boot_cpu_data.x86 >= 15)) 1919 break; 1920 goto no_apic; 1921 case X86_VENDOR_HYGON: 1922 break; 1923 case X86_VENDOR_INTEL: 1924 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1925 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC))) 1926 break; 1927 goto no_apic; 1928 default: 1929 goto no_apic; 1930 } 1931 1932 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1933 /* 1934 * Over-ride BIOS and try to enable the local APIC only if 1935 * "lapic" specified. 1936 */ 1937 if (!force_enable_local_apic) { 1938 pr_info("Local APIC disabled by BIOS -- " 1939 "you can enable it with \"lapic\"\n"); 1940 return -1; 1941 } 1942 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) 1943 return -1; 1944 } else { 1945 if (apic_verify()) 1946 return -1; 1947 } 1948 1949 apic_pm_activate(); 1950 1951 return 0; 1952 1953 no_apic: 1954 pr_info("No local APIC present or hardware disabled\n"); 1955 return -1; 1956 } 1957 #endif 1958 1959 /** 1960 * init_apic_mappings - initialize APIC mappings 1961 */ 1962 void __init init_apic_mappings(void) 1963 { 1964 unsigned int new_apicid; 1965 1966 apic_check_deadline_errata(); 1967 1968 if (x2apic_mode) { 1969 boot_cpu_physical_apicid = read_apic_id(); 1970 return; 1971 } 1972 1973 /* If no local APIC can be found return early */ 1974 if (!smp_found_config && detect_init_APIC()) { 1975 /* lets NOP'ify apic operations */ 1976 pr_info("APIC: disable apic facility\n"); 1977 apic_disable(); 1978 } else { 1979 apic_phys = mp_lapic_addr; 1980 1981 /* 1982 * If the system has ACPI MADT tables or MP info, the LAPIC 1983 * address is already registered. 1984 */ 1985 if (!acpi_lapic && !smp_found_config) 1986 register_lapic_address(apic_phys); 1987 } 1988 1989 /* 1990 * Fetch the APIC ID of the BSP in case we have a 1991 * default configuration (or the MP table is broken). 1992 */ 1993 new_apicid = read_apic_id(); 1994 if (boot_cpu_physical_apicid != new_apicid) { 1995 boot_cpu_physical_apicid = new_apicid; 1996 /* 1997 * yeah -- we lie about apic_version 1998 * in case if apic was disabled via boot option 1999 * but it's not a problem for SMP compiled kernel 2000 * since apic_intr_mode_select is prepared for such 2001 * a case and disable smp mode 2002 */ 2003 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 2004 } 2005 } 2006 2007 void __init register_lapic_address(unsigned long address) 2008 { 2009 mp_lapic_addr = address; 2010 2011 if (!x2apic_mode) { 2012 set_fixmap_nocache(FIX_APIC_BASE, address); 2013 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 2014 APIC_BASE, address); 2015 } 2016 if (boot_cpu_physical_apicid == -1U) { 2017 boot_cpu_physical_apicid = read_apic_id(); 2018 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 2019 } 2020 } 2021 2022 /* 2023 * Local APIC interrupts 2024 */ 2025 2026 /* 2027 * This interrupt should _never_ happen with our APIC/SMP architecture 2028 */ 2029 __visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs) 2030 { 2031 u8 vector = ~regs->orig_ax; 2032 u32 v; 2033 2034 entering_irq(); 2035 trace_spurious_apic_entry(vector); 2036 2037 /* 2038 * Check if this really is a spurious interrupt and ACK it 2039 * if it is a vectored one. Just in case... 2040 * Spurious interrupts should not be ACKed. 2041 */ 2042 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); 2043 if (v & (1 << (vector & 0x1f))) 2044 ack_APIC_irq(); 2045 2046 inc_irq_stat(irq_spurious_count); 2047 2048 /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 2049 pr_info("spurious APIC interrupt through vector %02x on CPU#%d, " 2050 "should never happen.\n", vector, smp_processor_id()); 2051 2052 trace_spurious_apic_exit(vector); 2053 exiting_irq(); 2054 } 2055 2056 /* 2057 * This interrupt should never happen with our APIC/SMP architecture 2058 */ 2059 __visible void __irq_entry smp_error_interrupt(struct pt_regs *regs) 2060 { 2061 static const char * const error_interrupt_reason[] = { 2062 "Send CS error", /* APIC Error Bit 0 */ 2063 "Receive CS error", /* APIC Error Bit 1 */ 2064 "Send accept error", /* APIC Error Bit 2 */ 2065 "Receive accept error", /* APIC Error Bit 3 */ 2066 "Redirectable IPI", /* APIC Error Bit 4 */ 2067 "Send illegal vector", /* APIC Error Bit 5 */ 2068 "Received illegal vector", /* APIC Error Bit 6 */ 2069 "Illegal register address", /* APIC Error Bit 7 */ 2070 }; 2071 u32 v, i = 0; 2072 2073 entering_irq(); 2074 trace_error_apic_entry(ERROR_APIC_VECTOR); 2075 2076 /* First tickle the hardware, only then report what went on. -- REW */ 2077 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ 2078 apic_write(APIC_ESR, 0); 2079 v = apic_read(APIC_ESR); 2080 ack_APIC_irq(); 2081 atomic_inc(&irq_err_count); 2082 2083 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", 2084 smp_processor_id(), v); 2085 2086 v &= 0xff; 2087 while (v) { 2088 if (v & 0x1) 2089 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); 2090 i++; 2091 v >>= 1; 2092 } 2093 2094 apic_printk(APIC_DEBUG, KERN_CONT "\n"); 2095 2096 trace_error_apic_exit(ERROR_APIC_VECTOR); 2097 exiting_irq(); 2098 } 2099 2100 /** 2101 * connect_bsp_APIC - attach the APIC to the interrupt system 2102 */ 2103 static void __init connect_bsp_APIC(void) 2104 { 2105 #ifdef CONFIG_X86_32 2106 if (pic_mode) { 2107 /* 2108 * Do not trust the local APIC being empty at bootup. 2109 */ 2110 clear_local_APIC(); 2111 /* 2112 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 2113 * local APIC to INT and NMI lines. 2114 */ 2115 apic_printk(APIC_VERBOSE, "leaving PIC mode, " 2116 "enabling APIC mode.\n"); 2117 imcr_pic_to_apic(); 2118 } 2119 #endif 2120 } 2121 2122 /** 2123 * disconnect_bsp_APIC - detach the APIC from the interrupt system 2124 * @virt_wire_setup: indicates, whether virtual wire mode is selected 2125 * 2126 * Virtual wire mode is necessary to deliver legacy interrupts even when the 2127 * APIC is disabled. 2128 */ 2129 void disconnect_bsp_APIC(int virt_wire_setup) 2130 { 2131 unsigned int value; 2132 2133 #ifdef CONFIG_X86_32 2134 if (pic_mode) { 2135 /* 2136 * Put the board back into PIC mode (has an effect only on 2137 * certain older boards). Note that APIC interrupts, including 2138 * IPIs, won't work beyond this point! The only exception are 2139 * INIT IPIs. 2140 */ 2141 apic_printk(APIC_VERBOSE, "disabling APIC mode, " 2142 "entering PIC mode.\n"); 2143 imcr_apic_to_pic(); 2144 return; 2145 } 2146 #endif 2147 2148 /* Go back to Virtual Wire compatibility mode */ 2149 2150 /* For the spurious interrupt use vector F, and enable it */ 2151 value = apic_read(APIC_SPIV); 2152 value &= ~APIC_VECTOR_MASK; 2153 value |= APIC_SPIV_APIC_ENABLED; 2154 value |= 0xf; 2155 apic_write(APIC_SPIV, value); 2156 2157 if (!virt_wire_setup) { 2158 /* 2159 * For LVT0 make it edge triggered, active high, 2160 * external and enabled 2161 */ 2162 value = apic_read(APIC_LVT0); 2163 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2164 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2165 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2166 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2167 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 2168 apic_write(APIC_LVT0, value); 2169 } else { 2170 /* Disable LVT0 */ 2171 apic_write(APIC_LVT0, APIC_LVT_MASKED); 2172 } 2173 2174 /* 2175 * For LVT1 make it edge triggered, active high, 2176 * nmi and enabled 2177 */ 2178 value = apic_read(APIC_LVT1); 2179 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2180 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2181 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2182 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2183 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 2184 apic_write(APIC_LVT1, value); 2185 } 2186 2187 /* 2188 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated 2189 * contiguously, it equals to current allocated max logical CPU ID plus 1. 2190 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range, 2191 * so the maximum of nr_logical_cpuids is nr_cpu_ids. 2192 * 2193 * NOTE: Reserve 0 for BSP. 2194 */ 2195 static int nr_logical_cpuids = 1; 2196 2197 /* 2198 * Used to store mapping between logical CPU IDs and APIC IDs. 2199 */ 2200 static int cpuid_to_apicid[] = { 2201 [0 ... NR_CPUS - 1] = -1, 2202 }; 2203 2204 #ifdef CONFIG_SMP 2205 /** 2206 * apic_id_is_primary_thread - Check whether APIC ID belongs to a primary thread 2207 * @id: APIC ID to check 2208 */ 2209 bool apic_id_is_primary_thread(unsigned int apicid) 2210 { 2211 u32 mask; 2212 2213 if (smp_num_siblings == 1) 2214 return true; 2215 /* Isolate the SMT bit(s) in the APICID and check for 0 */ 2216 mask = (1U << (fls(smp_num_siblings) - 1)) - 1; 2217 return !(apicid & mask); 2218 } 2219 #endif 2220 2221 /* 2222 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids 2223 * and cpuid_to_apicid[] synchronized. 2224 */ 2225 static int allocate_logical_cpuid(int apicid) 2226 { 2227 int i; 2228 2229 /* 2230 * cpuid <-> apicid mapping is persistent, so when a cpu is up, 2231 * check if the kernel has allocated a cpuid for it. 2232 */ 2233 for (i = 0; i < nr_logical_cpuids; i++) { 2234 if (cpuid_to_apicid[i] == apicid) 2235 return i; 2236 } 2237 2238 /* Allocate a new cpuid. */ 2239 if (nr_logical_cpuids >= nr_cpu_ids) { 2240 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. " 2241 "Processor %d/0x%x and the rest are ignored.\n", 2242 nr_cpu_ids, nr_logical_cpuids, apicid); 2243 return -EINVAL; 2244 } 2245 2246 cpuid_to_apicid[nr_logical_cpuids] = apicid; 2247 return nr_logical_cpuids++; 2248 } 2249 2250 int generic_processor_info(int apicid, int version) 2251 { 2252 int cpu, max = nr_cpu_ids; 2253 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, 2254 phys_cpu_present_map); 2255 2256 /* 2257 * boot_cpu_physical_apicid is designed to have the apicid 2258 * returned by read_apic_id(), i.e, the apicid of the 2259 * currently booting-up processor. However, on some platforms, 2260 * it is temporarily modified by the apicid reported as BSP 2261 * through MP table. Concretely: 2262 * 2263 * - arch/x86/kernel/mpparse.c: MP_processor_info() 2264 * - arch/x86/mm/amdtopology.c: amd_numa_init() 2265 * 2266 * This function is executed with the modified 2267 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel 2268 * parameter doesn't work to disable APs on kdump 2nd kernel. 2269 * 2270 * Since fixing handling of boot_cpu_physical_apicid requires 2271 * another discussion and tests on each platform, we leave it 2272 * for now and here we use read_apic_id() directly in this 2273 * function, generic_processor_info(). 2274 */ 2275 if (disabled_cpu_apicid != BAD_APICID && 2276 disabled_cpu_apicid != read_apic_id() && 2277 disabled_cpu_apicid == apicid) { 2278 int thiscpu = num_processors + disabled_cpus; 2279 2280 pr_warning("APIC: Disabling requested cpu." 2281 " Processor %d/0x%x ignored.\n", 2282 thiscpu, apicid); 2283 2284 disabled_cpus++; 2285 return -ENODEV; 2286 } 2287 2288 /* 2289 * If boot cpu has not been detected yet, then only allow upto 2290 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu 2291 */ 2292 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && 2293 apicid != boot_cpu_physical_apicid) { 2294 int thiscpu = max + disabled_cpus - 1; 2295 2296 pr_warning( 2297 "APIC: NR_CPUS/possible_cpus limit of %i almost" 2298 " reached. Keeping one slot for boot cpu." 2299 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2300 2301 disabled_cpus++; 2302 return -ENODEV; 2303 } 2304 2305 if (num_processors >= nr_cpu_ids) { 2306 int thiscpu = max + disabled_cpus; 2307 2308 pr_warning("APIC: NR_CPUS/possible_cpus limit of %i " 2309 "reached. Processor %d/0x%x ignored.\n", 2310 max, thiscpu, apicid); 2311 2312 disabled_cpus++; 2313 return -EINVAL; 2314 } 2315 2316 if (apicid == boot_cpu_physical_apicid) { 2317 /* 2318 * x86_bios_cpu_apicid is required to have processors listed 2319 * in same order as logical cpu numbers. Hence the first 2320 * entry is BSP, and so on. 2321 * boot_cpu_init() already hold bit 0 in cpu_present_mask 2322 * for BSP. 2323 */ 2324 cpu = 0; 2325 2326 /* Logical cpuid 0 is reserved for BSP. */ 2327 cpuid_to_apicid[0] = apicid; 2328 } else { 2329 cpu = allocate_logical_cpuid(apicid); 2330 if (cpu < 0) { 2331 disabled_cpus++; 2332 return -EINVAL; 2333 } 2334 } 2335 2336 /* 2337 * Validate version 2338 */ 2339 if (version == 0x0) { 2340 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", 2341 cpu, apicid); 2342 version = 0x10; 2343 } 2344 2345 if (version != boot_cpu_apic_version) { 2346 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", 2347 boot_cpu_apic_version, cpu, version); 2348 } 2349 2350 if (apicid > max_physical_apicid) 2351 max_physical_apicid = apicid; 2352 2353 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 2354 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 2355 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 2356 #endif 2357 #ifdef CONFIG_X86_32 2358 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 2359 apic->x86_32_early_logical_apicid(cpu); 2360 #endif 2361 set_cpu_possible(cpu, true); 2362 physid_set(apicid, phys_cpu_present_map); 2363 set_cpu_present(cpu, true); 2364 num_processors++; 2365 2366 return cpu; 2367 } 2368 2369 int hard_smp_processor_id(void) 2370 { 2371 return read_apic_id(); 2372 } 2373 2374 /* 2375 * Override the generic EOI implementation with an optimized version. 2376 * Only called during early boot when only one CPU is active and with 2377 * interrupts disabled, so we know this does not race with actual APIC driver 2378 * use. 2379 */ 2380 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) 2381 { 2382 struct apic **drv; 2383 2384 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { 2385 /* Should happen once for each apic */ 2386 WARN_ON((*drv)->eoi_write == eoi_write); 2387 (*drv)->native_eoi_write = (*drv)->eoi_write; 2388 (*drv)->eoi_write = eoi_write; 2389 } 2390 } 2391 2392 static void __init apic_bsp_up_setup(void) 2393 { 2394 #ifdef CONFIG_X86_64 2395 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid)); 2396 #else 2397 /* 2398 * Hack: In case of kdump, after a crash, kernel might be booting 2399 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 2400 * might be zero if read from MP tables. Get it from LAPIC. 2401 */ 2402 # ifdef CONFIG_CRASH_DUMP 2403 boot_cpu_physical_apicid = read_apic_id(); 2404 # endif 2405 #endif 2406 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 2407 } 2408 2409 /** 2410 * apic_bsp_setup - Setup function for local apic and io-apic 2411 * @upmode: Force UP mode (for APIC_init_uniprocessor) 2412 * 2413 * Returns: 2414 * apic_id of BSP APIC 2415 */ 2416 void __init apic_bsp_setup(bool upmode) 2417 { 2418 connect_bsp_APIC(); 2419 if (upmode) 2420 apic_bsp_up_setup(); 2421 setup_local_APIC(); 2422 2423 enable_IO_APIC(); 2424 end_local_APIC_setup(); 2425 irq_remap_enable_fault_handling(); 2426 setup_IO_APIC(); 2427 } 2428 2429 #ifdef CONFIG_UP_LATE_INIT 2430 void __init up_late_init(void) 2431 { 2432 if (apic_intr_mode == APIC_PIC) 2433 return; 2434 2435 /* Setup local timer */ 2436 x86_init.timers.setup_percpu_clockev(); 2437 } 2438 #endif 2439 2440 /* 2441 * Power management 2442 */ 2443 #ifdef CONFIG_PM 2444 2445 static struct { 2446 /* 2447 * 'active' is true if the local APIC was enabled by us and 2448 * not the BIOS; this signifies that we are also responsible 2449 * for disabling it before entering apm/acpi suspend 2450 */ 2451 int active; 2452 /* r/w apic fields */ 2453 unsigned int apic_id; 2454 unsigned int apic_taskpri; 2455 unsigned int apic_ldr; 2456 unsigned int apic_dfr; 2457 unsigned int apic_spiv; 2458 unsigned int apic_lvtt; 2459 unsigned int apic_lvtpc; 2460 unsigned int apic_lvt0; 2461 unsigned int apic_lvt1; 2462 unsigned int apic_lvterr; 2463 unsigned int apic_tmict; 2464 unsigned int apic_tdcr; 2465 unsigned int apic_thmr; 2466 unsigned int apic_cmci; 2467 } apic_pm_state; 2468 2469 static int lapic_suspend(void) 2470 { 2471 unsigned long flags; 2472 int maxlvt; 2473 2474 if (!apic_pm_state.active) 2475 return 0; 2476 2477 maxlvt = lapic_get_maxlvt(); 2478 2479 apic_pm_state.apic_id = apic_read(APIC_ID); 2480 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2481 apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2482 apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2483 apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2484 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2485 if (maxlvt >= 4) 2486 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2487 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2488 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2489 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2490 apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2491 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 2492 #ifdef CONFIG_X86_THERMAL_VECTOR 2493 if (maxlvt >= 5) 2494 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2495 #endif 2496 #ifdef CONFIG_X86_MCE_INTEL 2497 if (maxlvt >= 6) 2498 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI); 2499 #endif 2500 2501 local_irq_save(flags); 2502 disable_local_APIC(); 2503 2504 irq_remapping_disable(); 2505 2506 local_irq_restore(flags); 2507 return 0; 2508 } 2509 2510 static void lapic_resume(void) 2511 { 2512 unsigned int l, h; 2513 unsigned long flags; 2514 int maxlvt; 2515 2516 if (!apic_pm_state.active) 2517 return; 2518 2519 local_irq_save(flags); 2520 2521 /* 2522 * IO-APIC and PIC have their own resume routines. 2523 * We just mask them here to make sure the interrupt 2524 * subsystem is completely quiet while we enable x2apic 2525 * and interrupt-remapping. 2526 */ 2527 mask_ioapic_entries(); 2528 legacy_pic->mask_all(); 2529 2530 if (x2apic_mode) { 2531 __x2apic_enable(); 2532 } else { 2533 /* 2534 * Make sure the APICBASE points to the right address 2535 * 2536 * FIXME! This will be wrong if we ever support suspend on 2537 * SMP! We'll need to do this as part of the CPU restore! 2538 */ 2539 if (boot_cpu_data.x86 >= 6) { 2540 rdmsr(MSR_IA32_APICBASE, l, h); 2541 l &= ~MSR_IA32_APICBASE_BASE; 2542 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2543 wrmsr(MSR_IA32_APICBASE, l, h); 2544 } 2545 } 2546 2547 maxlvt = lapic_get_maxlvt(); 2548 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2549 apic_write(APIC_ID, apic_pm_state.apic_id); 2550 apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2551 apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2552 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2553 apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2554 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2555 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2556 #ifdef CONFIG_X86_THERMAL_VECTOR 2557 if (maxlvt >= 5) 2558 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2559 #endif 2560 #ifdef CONFIG_X86_MCE_INTEL 2561 if (maxlvt >= 6) 2562 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci); 2563 #endif 2564 if (maxlvt >= 4) 2565 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2566 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2567 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2568 apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2569 apic_write(APIC_ESR, 0); 2570 apic_read(APIC_ESR); 2571 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2572 apic_write(APIC_ESR, 0); 2573 apic_read(APIC_ESR); 2574 2575 irq_remapping_reenable(x2apic_mode); 2576 2577 local_irq_restore(flags); 2578 } 2579 2580 /* 2581 * This device has no shutdown method - fully functioning local APICs 2582 * are needed on every CPU up until machine_halt/restart/poweroff. 2583 */ 2584 2585 static struct syscore_ops lapic_syscore_ops = { 2586 .resume = lapic_resume, 2587 .suspend = lapic_suspend, 2588 }; 2589 2590 static void apic_pm_activate(void) 2591 { 2592 apic_pm_state.active = 1; 2593 } 2594 2595 static int __init init_lapic_sysfs(void) 2596 { 2597 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2598 if (boot_cpu_has(X86_FEATURE_APIC)) 2599 register_syscore_ops(&lapic_syscore_ops); 2600 2601 return 0; 2602 } 2603 2604 /* local apic needs to resume before other devices access its registers. */ 2605 core_initcall(init_lapic_sysfs); 2606 2607 #else /* CONFIG_PM */ 2608 2609 static void apic_pm_activate(void) { } 2610 2611 #endif /* CONFIG_PM */ 2612 2613 #ifdef CONFIG_X86_64 2614 2615 static int multi_checked; 2616 static int multi; 2617 2618 static int set_multi(const struct dmi_system_id *d) 2619 { 2620 if (multi) 2621 return 0; 2622 pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2623 multi = 1; 2624 return 0; 2625 } 2626 2627 static const struct dmi_system_id multi_dmi_table[] = { 2628 { 2629 .callback = set_multi, 2630 .ident = "IBM System Summit2", 2631 .matches = { 2632 DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2633 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2634 }, 2635 }, 2636 {} 2637 }; 2638 2639 static void dmi_check_multi(void) 2640 { 2641 if (multi_checked) 2642 return; 2643 2644 dmi_check_system(multi_dmi_table); 2645 multi_checked = 1; 2646 } 2647 2648 /* 2649 * apic_is_clustered_box() -- Check if we can expect good TSC 2650 * 2651 * Thus far, the major user of this is IBM's Summit2 series: 2652 * Clustered boxes may have unsynced TSC problems if they are 2653 * multi-chassis. 2654 * Use DMI to check them 2655 */ 2656 int apic_is_clustered_box(void) 2657 { 2658 dmi_check_multi(); 2659 return multi; 2660 } 2661 #endif 2662 2663 /* 2664 * APIC command line parameters 2665 */ 2666 static int __init setup_disableapic(char *arg) 2667 { 2668 disable_apic = 1; 2669 setup_clear_cpu_cap(X86_FEATURE_APIC); 2670 return 0; 2671 } 2672 early_param("disableapic", setup_disableapic); 2673 2674 /* same as disableapic, for compatibility */ 2675 static int __init setup_nolapic(char *arg) 2676 { 2677 return setup_disableapic(arg); 2678 } 2679 early_param("nolapic", setup_nolapic); 2680 2681 static int __init parse_lapic_timer_c2_ok(char *arg) 2682 { 2683 local_apic_timer_c2_ok = 1; 2684 return 0; 2685 } 2686 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2687 2688 static int __init parse_disable_apic_timer(char *arg) 2689 { 2690 disable_apic_timer = 1; 2691 return 0; 2692 } 2693 early_param("noapictimer", parse_disable_apic_timer); 2694 2695 static int __init parse_nolapic_timer(char *arg) 2696 { 2697 disable_apic_timer = 1; 2698 return 0; 2699 } 2700 early_param("nolapic_timer", parse_nolapic_timer); 2701 2702 static int __init apic_set_verbosity(char *arg) 2703 { 2704 if (!arg) { 2705 #ifdef CONFIG_X86_64 2706 skip_ioapic_setup = 0; 2707 return 0; 2708 #endif 2709 return -EINVAL; 2710 } 2711 2712 if (strcmp("debug", arg) == 0) 2713 apic_verbosity = APIC_DEBUG; 2714 else if (strcmp("verbose", arg) == 0) 2715 apic_verbosity = APIC_VERBOSE; 2716 #ifdef CONFIG_X86_64 2717 else { 2718 pr_warning("APIC Verbosity level %s not recognised" 2719 " use apic=verbose or apic=debug\n", arg); 2720 return -EINVAL; 2721 } 2722 #endif 2723 2724 return 0; 2725 } 2726 early_param("apic", apic_set_verbosity); 2727 2728 static int __init lapic_insert_resource(void) 2729 { 2730 if (!apic_phys) 2731 return -1; 2732 2733 /* Put local APIC into the resource map. */ 2734 lapic_resource.start = apic_phys; 2735 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2736 insert_resource(&iomem_resource, &lapic_resource); 2737 2738 return 0; 2739 } 2740 2741 /* 2742 * need call insert after e820__reserve_resources() 2743 * that is using request_resource 2744 */ 2745 late_initcall(lapic_insert_resource); 2746 2747 static int __init apic_set_disabled_cpu_apicid(char *arg) 2748 { 2749 if (!arg || !get_option(&arg, &disabled_cpu_apicid)) 2750 return -EINVAL; 2751 2752 return 0; 2753 } 2754 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); 2755 2756 static int __init apic_set_extnmi(char *arg) 2757 { 2758 if (!arg) 2759 return -EINVAL; 2760 2761 if (!strncmp("all", arg, 3)) 2762 apic_extnmi = APIC_EXTNMI_ALL; 2763 else if (!strncmp("none", arg, 4)) 2764 apic_extnmi = APIC_EXTNMI_NONE; 2765 else if (!strncmp("bsp", arg, 3)) 2766 apic_extnmi = APIC_EXTNMI_BSP; 2767 else { 2768 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg); 2769 return -EINVAL; 2770 } 2771 2772 return 0; 2773 } 2774 early_param("apic_extnmi", apic_set_extnmi); 2775