1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Local APIC handling, local APIC timers 4 * 5 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * 7 * Fixes 8 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 9 * thanks to Eric Gilmore 10 * and Rolf G. Tews 11 * for testing these extensively. 12 * Maciej W. Rozycki : Various updates and fixes. 13 * Mikael Pettersson : Power Management for UP-APIC. 14 * Pavel Machek and 15 * Mikael Pettersson : PM converted to driver model. 16 */ 17 18 #include <linux/perf_event.h> 19 #include <linux/kernel_stat.h> 20 #include <linux/mc146818rtc.h> 21 #include <linux/acpi_pmtmr.h> 22 #include <linux/clockchips.h> 23 #include <linux/interrupt.h> 24 #include <linux/memblock.h> 25 #include <linux/ftrace.h> 26 #include <linux/ioport.h> 27 #include <linux/export.h> 28 #include <linux/syscore_ops.h> 29 #include <linux/delay.h> 30 #include <linux/timex.h> 31 #include <linux/i8253.h> 32 #include <linux/dmar.h> 33 #include <linux/init.h> 34 #include <linux/cpu.h> 35 #include <linux/dmi.h> 36 #include <linux/smp.h> 37 #include <linux/mm.h> 38 39 #include <asm/trace/irq_vectors.h> 40 #include <asm/irq_remapping.h> 41 #include <asm/perf_event.h> 42 #include <asm/x86_init.h> 43 #include <linux/atomic.h> 44 #include <asm/mpspec.h> 45 #include <asm/i8259.h> 46 #include <asm/proto.h> 47 #include <asm/traps.h> 48 #include <asm/apic.h> 49 #include <asm/acpi.h> 50 #include <asm/io_apic.h> 51 #include <asm/desc.h> 52 #include <asm/hpet.h> 53 #include <asm/mtrr.h> 54 #include <asm/time.h> 55 #include <asm/smp.h> 56 #include <asm/mce.h> 57 #include <asm/tsc.h> 58 #include <asm/hypervisor.h> 59 #include <asm/cpu_device_id.h> 60 #include <asm/intel-family.h> 61 #include <asm/irq_regs.h> 62 63 unsigned int num_processors; 64 65 unsigned disabled_cpus; 66 67 /* Processor that is doing the boot up */ 68 unsigned int boot_cpu_physical_apicid __ro_after_init = -1U; 69 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); 70 71 u8 boot_cpu_apic_version __ro_after_init; 72 73 /* 74 * The highest APIC ID seen during enumeration. 75 */ 76 static unsigned int max_physical_apicid; 77 78 /* 79 * Bitmask of physically existing CPUs: 80 */ 81 physid_mask_t phys_cpu_present_map; 82 83 /* 84 * Processor to be disabled specified by kernel parameter 85 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to 86 * avoid undefined behaviour caused by sending INIT from AP to BSP. 87 */ 88 static unsigned int disabled_cpu_apicid __ro_after_init = BAD_APICID; 89 90 /* 91 * This variable controls which CPUs receive external NMIs. By default, 92 * external NMIs are delivered only to the BSP. 93 */ 94 static int apic_extnmi __ro_after_init = APIC_EXTNMI_BSP; 95 96 /* 97 * Hypervisor supports 15 bits of APIC ID in MSI Extended Destination ID 98 */ 99 static bool virt_ext_dest_id __ro_after_init; 100 101 /* 102 * Map cpu index to physical APIC ID 103 */ 104 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); 105 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); 106 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX); 107 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 108 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 109 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); 110 111 #ifdef CONFIG_X86_32 112 113 /* 114 * On x86_32, the mapping between cpu and logical apicid may vary 115 * depending on apic in use. The following early percpu variable is 116 * used for the mapping. This is where the behaviors of x86_64 and 32 117 * actually diverge. Let's keep it ugly for now. 118 */ 119 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); 120 121 /* Local APIC was disabled by the BIOS and enabled by the kernel */ 122 static int enabled_via_apicbase __ro_after_init; 123 124 /* 125 * Handle interrupt mode configuration register (IMCR). 126 * This register controls whether the interrupt signals 127 * that reach the BSP come from the master PIC or from the 128 * local APIC. Before entering Symmetric I/O Mode, either 129 * the BIOS or the operating system must switch out of 130 * PIC Mode by changing the IMCR. 131 */ 132 static inline void imcr_pic_to_apic(void) 133 { 134 /* select IMCR register */ 135 outb(0x70, 0x22); 136 /* NMI and 8259 INTR go through APIC */ 137 outb(0x01, 0x23); 138 } 139 140 static inline void imcr_apic_to_pic(void) 141 { 142 /* select IMCR register */ 143 outb(0x70, 0x22); 144 /* NMI and 8259 INTR go directly to BSP */ 145 outb(0x00, 0x23); 146 } 147 #endif 148 149 /* 150 * Knob to control our willingness to enable the local APIC. 151 * 152 * +1=force-enable 153 */ 154 static int force_enable_local_apic __initdata; 155 156 /* 157 * APIC command line parameters 158 */ 159 static int __init parse_lapic(char *arg) 160 { 161 if (IS_ENABLED(CONFIG_X86_32) && !arg) 162 force_enable_local_apic = 1; 163 else if (arg && !strncmp(arg, "notscdeadline", 13)) 164 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 165 return 0; 166 } 167 early_param("lapic", parse_lapic); 168 169 #ifdef CONFIG_X86_64 170 static int apic_calibrate_pmtmr __initdata; 171 static __init int setup_apicpmtimer(char *s) 172 { 173 apic_calibrate_pmtmr = 1; 174 notsc_setup(NULL); 175 return 0; 176 } 177 __setup("apicpmtimer", setup_apicpmtimer); 178 #endif 179 180 unsigned long mp_lapic_addr __ro_after_init; 181 int disable_apic __ro_after_init; 182 /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 183 static int disable_apic_timer __initdata; 184 /* Local APIC timer works in C2 */ 185 int local_apic_timer_c2_ok __ro_after_init; 186 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 187 188 /* 189 * Debug level, exported for io_apic.c 190 */ 191 int apic_verbosity __ro_after_init; 192 193 int pic_mode __ro_after_init; 194 195 /* Have we found an MP table */ 196 int smp_found_config __ro_after_init; 197 198 static struct resource lapic_resource = { 199 .name = "Local APIC", 200 .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 201 }; 202 203 unsigned int lapic_timer_period = 0; 204 205 static void apic_pm_activate(void); 206 207 static unsigned long apic_phys __ro_after_init; 208 209 /* 210 * Get the LAPIC version 211 */ 212 static inline int lapic_get_version(void) 213 { 214 return GET_APIC_VERSION(apic_read(APIC_LVR)); 215 } 216 217 /* 218 * Check, if the APIC is integrated or a separate chip 219 */ 220 static inline int lapic_is_integrated(void) 221 { 222 return APIC_INTEGRATED(lapic_get_version()); 223 } 224 225 /* 226 * Check, whether this is a modern or a first generation APIC 227 */ 228 static int modern_apic(void) 229 { 230 /* AMD systems use old APIC versions, so check the CPU */ 231 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 232 boot_cpu_data.x86 >= 0xf) 233 return 1; 234 235 /* Hygon systems use modern APIC */ 236 if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 237 return 1; 238 239 return lapic_get_version() >= 0x14; 240 } 241 242 /* 243 * right after this call apic become NOOP driven 244 * so apic->write/read doesn't do anything 245 */ 246 static void __init apic_disable(void) 247 { 248 pr_info("APIC: switched to apic NOOP\n"); 249 apic = &apic_noop; 250 } 251 252 void native_apic_wait_icr_idle(void) 253 { 254 while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 255 cpu_relax(); 256 } 257 258 u32 native_safe_apic_wait_icr_idle(void) 259 { 260 u32 send_status; 261 int timeout; 262 263 timeout = 0; 264 do { 265 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 266 if (!send_status) 267 break; 268 inc_irq_stat(icr_read_retry_count); 269 udelay(100); 270 } while (timeout++ < 1000); 271 272 return send_status; 273 } 274 275 void native_apic_icr_write(u32 low, u32 id) 276 { 277 unsigned long flags; 278 279 local_irq_save(flags); 280 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 281 apic_write(APIC_ICR, low); 282 local_irq_restore(flags); 283 } 284 285 u64 native_apic_icr_read(void) 286 { 287 u32 icr1, icr2; 288 289 icr2 = apic_read(APIC_ICR2); 290 icr1 = apic_read(APIC_ICR); 291 292 return icr1 | ((u64)icr2 << 32); 293 } 294 295 #ifdef CONFIG_X86_32 296 /** 297 * get_physical_broadcast - Get number of physical broadcast IDs 298 */ 299 int get_physical_broadcast(void) 300 { 301 return modern_apic() ? 0xff : 0xf; 302 } 303 #endif 304 305 /** 306 * lapic_get_maxlvt - get the maximum number of local vector table entries 307 */ 308 int lapic_get_maxlvt(void) 309 { 310 /* 311 * - we always have APIC integrated on 64bit mode 312 * - 82489DXs do not report # of LVT entries 313 */ 314 return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2; 315 } 316 317 /* 318 * Local APIC timer 319 */ 320 321 /* Clock divisor */ 322 #define APIC_DIVISOR 16 323 #define TSC_DIVISOR 8 324 325 /* 326 * This function sets up the local APIC timer, with a timeout of 327 * 'clocks' APIC bus clock. During calibration we actually call 328 * this function twice on the boot CPU, once with a bogus timeout 329 * value, second time for real. The other (noncalibrating) CPUs 330 * call this function only once, with the real, calibrated value. 331 * 332 * We do reads before writes even if unnecessary, to get around the 333 * P5 APIC double write bug. 334 */ 335 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 336 { 337 unsigned int lvtt_value, tmp_value; 338 339 lvtt_value = LOCAL_TIMER_VECTOR; 340 if (!oneshot) 341 lvtt_value |= APIC_LVT_TIMER_PERIODIC; 342 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 343 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; 344 345 if (!lapic_is_integrated()) 346 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 347 348 if (!irqen) 349 lvtt_value |= APIC_LVT_MASKED; 350 351 apic_write(APIC_LVTT, lvtt_value); 352 353 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { 354 /* 355 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, 356 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. 357 * According to Intel, MFENCE can do the serialization here. 358 */ 359 asm volatile("mfence" : : : "memory"); 360 return; 361 } 362 363 /* 364 * Divide PICLK by 16 365 */ 366 tmp_value = apic_read(APIC_TDCR); 367 apic_write(APIC_TDCR, 368 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 369 APIC_TDR_DIV_16); 370 371 if (!oneshot) 372 apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 373 } 374 375 /* 376 * Setup extended LVT, AMD specific 377 * 378 * Software should use the LVT offsets the BIOS provides. The offsets 379 * are determined by the subsystems using it like those for MCE 380 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 381 * are supported. Beginning with family 10h at least 4 offsets are 382 * available. 383 * 384 * Since the offsets must be consistent for all cores, we keep track 385 * of the LVT offsets in software and reserve the offset for the same 386 * vector also to be used on other cores. An offset is freed by 387 * setting the entry to APIC_EILVT_MASKED. 388 * 389 * If the BIOS is right, there should be no conflicts. Otherwise a 390 * "[Firmware Bug]: ..." error message is generated. However, if 391 * software does not properly determines the offsets, it is not 392 * necessarily a BIOS bug. 393 */ 394 395 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 396 397 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 398 { 399 return (old & APIC_EILVT_MASKED) 400 || (new == APIC_EILVT_MASKED) 401 || ((new & ~APIC_EILVT_MASKED) == old); 402 } 403 404 static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 405 { 406 unsigned int rsvd, vector; 407 408 if (offset >= APIC_EILVT_NR_MAX) 409 return ~0; 410 411 rsvd = atomic_read(&eilvt_offsets[offset]); 412 do { 413 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ 414 if (vector && !eilvt_entry_is_changeable(vector, new)) 415 /* may not change if vectors are different */ 416 return rsvd; 417 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 418 } while (rsvd != new); 419 420 rsvd &= ~APIC_EILVT_MASKED; 421 if (rsvd && rsvd != vector) 422 pr_info("LVT offset %d assigned for vector 0x%02x\n", 423 offset, rsvd); 424 425 return new; 426 } 427 428 /* 429 * If mask=1, the LVT entry does not generate interrupts while mask=0 430 * enables the vector. See also the BKDGs. Must be called with 431 * preemption disabled. 432 */ 433 434 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 435 { 436 unsigned long reg = APIC_EILVTn(offset); 437 unsigned int new, old, reserved; 438 439 new = (mask << 16) | (msg_type << 8) | vector; 440 old = apic_read(reg); 441 reserved = reserve_eilvt_offset(offset, new); 442 443 if (reserved != new) { 444 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 445 "vector 0x%x, but the register is already in use for " 446 "vector 0x%x on another cpu\n", 447 smp_processor_id(), reg, offset, new, reserved); 448 return -EINVAL; 449 } 450 451 if (!eilvt_entry_is_changeable(old, new)) { 452 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 453 "vector 0x%x, but the register is already in use for " 454 "vector 0x%x on this cpu\n", 455 smp_processor_id(), reg, offset, new, old); 456 return -EBUSY; 457 } 458 459 apic_write(reg, new); 460 461 return 0; 462 } 463 EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 464 465 /* 466 * Program the next event, relative to now 467 */ 468 static int lapic_next_event(unsigned long delta, 469 struct clock_event_device *evt) 470 { 471 apic_write(APIC_TMICT, delta); 472 return 0; 473 } 474 475 static int lapic_next_deadline(unsigned long delta, 476 struct clock_event_device *evt) 477 { 478 u64 tsc; 479 480 tsc = rdtsc(); 481 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); 482 return 0; 483 } 484 485 static int lapic_timer_shutdown(struct clock_event_device *evt) 486 { 487 unsigned int v; 488 489 /* Lapic used as dummy for broadcast ? */ 490 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 491 return 0; 492 493 v = apic_read(APIC_LVTT); 494 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 495 apic_write(APIC_LVTT, v); 496 apic_write(APIC_TMICT, 0); 497 return 0; 498 } 499 500 static inline int 501 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot) 502 { 503 /* Lapic used as dummy for broadcast ? */ 504 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 505 return 0; 506 507 __setup_APIC_LVTT(lapic_timer_period, oneshot, 1); 508 return 0; 509 } 510 511 static int lapic_timer_set_periodic(struct clock_event_device *evt) 512 { 513 return lapic_timer_set_periodic_oneshot(evt, false); 514 } 515 516 static int lapic_timer_set_oneshot(struct clock_event_device *evt) 517 { 518 return lapic_timer_set_periodic_oneshot(evt, true); 519 } 520 521 /* 522 * Local APIC timer broadcast function 523 */ 524 static void lapic_timer_broadcast(const struct cpumask *mask) 525 { 526 #ifdef CONFIG_SMP 527 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 528 #endif 529 } 530 531 532 /* 533 * The local apic timer can be used for any function which is CPU local. 534 */ 535 static struct clock_event_device lapic_clockevent = { 536 .name = "lapic", 537 .features = CLOCK_EVT_FEAT_PERIODIC | 538 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP 539 | CLOCK_EVT_FEAT_DUMMY, 540 .shift = 32, 541 .set_state_shutdown = lapic_timer_shutdown, 542 .set_state_periodic = lapic_timer_set_periodic, 543 .set_state_oneshot = lapic_timer_set_oneshot, 544 .set_state_oneshot_stopped = lapic_timer_shutdown, 545 .set_next_event = lapic_next_event, 546 .broadcast = lapic_timer_broadcast, 547 .rating = 100, 548 .irq = -1, 549 }; 550 static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 551 552 static const struct x86_cpu_id deadline_match[] __initconst = { 553 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(HASWELL_X, X86_STEPPINGS(0x2, 0x2), 0x3a), /* EP */ 554 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(HASWELL_X, X86_STEPPINGS(0x4, 0x4), 0x0f), /* EX */ 555 556 X86_MATCH_INTEL_FAM6_MODEL( BROADWELL_X, 0x0b000020), 557 558 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x2, 0x2), 0x00000011), 559 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x3, 0x3), 0x0700000e), 560 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x4, 0x4), 0x0f00000c), 561 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x5, 0x5), 0x0e000003), 562 563 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x3, 0x3), 0x01000136), 564 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x4, 0x4), 0x02000014), 565 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x5, 0xf), 0), 566 567 X86_MATCH_INTEL_FAM6_MODEL( HASWELL, 0x22), 568 X86_MATCH_INTEL_FAM6_MODEL( HASWELL_L, 0x20), 569 X86_MATCH_INTEL_FAM6_MODEL( HASWELL_G, 0x17), 570 571 X86_MATCH_INTEL_FAM6_MODEL( BROADWELL, 0x25), 572 X86_MATCH_INTEL_FAM6_MODEL( BROADWELL_G, 0x17), 573 574 X86_MATCH_INTEL_FAM6_MODEL( SKYLAKE_L, 0xb2), 575 X86_MATCH_INTEL_FAM6_MODEL( SKYLAKE, 0xb2), 576 577 X86_MATCH_INTEL_FAM6_MODEL( KABYLAKE_L, 0x52), 578 X86_MATCH_INTEL_FAM6_MODEL( KABYLAKE, 0x52), 579 580 {}, 581 }; 582 583 static __init bool apic_validate_deadline_timer(void) 584 { 585 const struct x86_cpu_id *m; 586 u32 rev; 587 588 if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 589 return false; 590 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) 591 return true; 592 593 m = x86_match_cpu(deadline_match); 594 if (!m) 595 return true; 596 597 rev = (u32)m->driver_data; 598 599 if (boot_cpu_data.microcode >= rev) 600 return true; 601 602 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 603 pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; " 604 "please update microcode to version: 0x%x (or later)\n", rev); 605 return false; 606 } 607 608 /* 609 * Setup the local APIC timer for this CPU. Copy the initialized values 610 * of the boot CPU and register the clock event in the framework. 611 */ 612 static void setup_APIC_timer(void) 613 { 614 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 615 616 if (this_cpu_has(X86_FEATURE_ARAT)) { 617 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 618 /* Make LAPIC timer preferrable over percpu HPET */ 619 lapic_clockevent.rating = 150; 620 } 621 622 memcpy(levt, &lapic_clockevent, sizeof(*levt)); 623 levt->cpumask = cpumask_of(smp_processor_id()); 624 625 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 626 levt->name = "lapic-deadline"; 627 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | 628 CLOCK_EVT_FEAT_DUMMY); 629 levt->set_next_event = lapic_next_deadline; 630 clockevents_config_and_register(levt, 631 tsc_khz * (1000 / TSC_DIVISOR), 632 0xF, ~0UL); 633 } else 634 clockevents_register_device(levt); 635 } 636 637 /* 638 * Install the updated TSC frequency from recalibration at the TSC 639 * deadline clockevent devices. 640 */ 641 static void __lapic_update_tsc_freq(void *info) 642 { 643 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 644 645 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 646 return; 647 648 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR)); 649 } 650 651 void lapic_update_tsc_freq(void) 652 { 653 /* 654 * The clockevent device's ->mult and ->shift can both be 655 * changed. In order to avoid races, schedule the frequency 656 * update code on each CPU. 657 */ 658 on_each_cpu(__lapic_update_tsc_freq, NULL, 0); 659 } 660 661 /* 662 * In this functions we calibrate APIC bus clocks to the external timer. 663 * 664 * We want to do the calibration only once since we want to have local timer 665 * irqs syncron. CPUs connected by the same APIC bus have the very same bus 666 * frequency. 667 * 668 * This was previously done by reading the PIT/HPET and waiting for a wrap 669 * around to find out, that a tick has elapsed. I have a box, where the PIT 670 * readout is broken, so it never gets out of the wait loop again. This was 671 * also reported by others. 672 * 673 * Monitoring the jiffies value is inaccurate and the clockevents 674 * infrastructure allows us to do a simple substitution of the interrupt 675 * handler. 676 * 677 * The calibration routine also uses the pm_timer when possible, as the PIT 678 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 679 * back to normal later in the boot process). 680 */ 681 682 #define LAPIC_CAL_LOOPS (HZ/10) 683 684 static __initdata int lapic_cal_loops = -1; 685 static __initdata long lapic_cal_t1, lapic_cal_t2; 686 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 687 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 688 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 689 690 /* 691 * Temporary interrupt handler and polled calibration function. 692 */ 693 static void __init lapic_cal_handler(struct clock_event_device *dev) 694 { 695 unsigned long long tsc = 0; 696 long tapic = apic_read(APIC_TMCCT); 697 unsigned long pm = acpi_pm_read_early(); 698 699 if (boot_cpu_has(X86_FEATURE_TSC)) 700 tsc = rdtsc(); 701 702 switch (lapic_cal_loops++) { 703 case 0: 704 lapic_cal_t1 = tapic; 705 lapic_cal_tsc1 = tsc; 706 lapic_cal_pm1 = pm; 707 lapic_cal_j1 = jiffies; 708 break; 709 710 case LAPIC_CAL_LOOPS: 711 lapic_cal_t2 = tapic; 712 lapic_cal_tsc2 = tsc; 713 if (pm < lapic_cal_pm1) 714 pm += ACPI_PM_OVRRUN; 715 lapic_cal_pm2 = pm; 716 lapic_cal_j2 = jiffies; 717 break; 718 } 719 } 720 721 static int __init 722 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 723 { 724 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 725 const long pm_thresh = pm_100ms / 100; 726 unsigned long mult; 727 u64 res; 728 729 #ifndef CONFIG_X86_PM_TIMER 730 return -1; 731 #endif 732 733 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 734 735 /* Check, if the PM timer is available */ 736 if (!deltapm) 737 return -1; 738 739 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 740 741 if (deltapm > (pm_100ms - pm_thresh) && 742 deltapm < (pm_100ms + pm_thresh)) { 743 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 744 return 0; 745 } 746 747 res = (((u64)deltapm) * mult) >> 22; 748 do_div(res, 1000000); 749 pr_warn("APIC calibration not consistent " 750 "with PM-Timer: %ldms instead of 100ms\n", (long)res); 751 752 /* Correct the lapic counter value */ 753 res = (((u64)(*delta)) * pm_100ms); 754 do_div(res, deltapm); 755 pr_info("APIC delta adjusted to PM-Timer: " 756 "%lu (%ld)\n", (unsigned long)res, *delta); 757 *delta = (long)res; 758 759 /* Correct the tsc counter value */ 760 if (boot_cpu_has(X86_FEATURE_TSC)) { 761 res = (((u64)(*deltatsc)) * pm_100ms); 762 do_div(res, deltapm); 763 apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 764 "PM-Timer: %lu (%ld)\n", 765 (unsigned long)res, *deltatsc); 766 *deltatsc = (long)res; 767 } 768 769 return 0; 770 } 771 772 static int __init lapic_init_clockevent(void) 773 { 774 if (!lapic_timer_period) 775 return -1; 776 777 /* Calculate the scaled math multiplication factor */ 778 lapic_clockevent.mult = div_sc(lapic_timer_period/APIC_DIVISOR, 779 TICK_NSEC, lapic_clockevent.shift); 780 lapic_clockevent.max_delta_ns = 781 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 782 lapic_clockevent.max_delta_ticks = 0x7FFFFFFF; 783 lapic_clockevent.min_delta_ns = 784 clockevent_delta2ns(0xF, &lapic_clockevent); 785 lapic_clockevent.min_delta_ticks = 0xF; 786 787 return 0; 788 } 789 790 bool __init apic_needs_pit(void) 791 { 792 /* 793 * If the frequencies are not known, PIT is required for both TSC 794 * and apic timer calibration. 795 */ 796 if (!tsc_khz || !cpu_khz) 797 return true; 798 799 /* Is there an APIC at all or is it disabled? */ 800 if (!boot_cpu_has(X86_FEATURE_APIC) || disable_apic) 801 return true; 802 803 /* 804 * If interrupt delivery mode is legacy PIC or virtual wire without 805 * configuration, the local APIC timer wont be set up. Make sure 806 * that the PIT is initialized. 807 */ 808 if (apic_intr_mode == APIC_PIC || 809 apic_intr_mode == APIC_VIRTUAL_WIRE_NO_CONFIG) 810 return true; 811 812 /* Virt guests may lack ARAT, but still have DEADLINE */ 813 if (!boot_cpu_has(X86_FEATURE_ARAT)) 814 return true; 815 816 /* Deadline timer is based on TSC so no further PIT action required */ 817 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 818 return false; 819 820 /* APIC timer disabled? */ 821 if (disable_apic_timer) 822 return true; 823 /* 824 * The APIC timer frequency is known already, no PIT calibration 825 * required. If unknown, let the PIT be initialized. 826 */ 827 return lapic_timer_period == 0; 828 } 829 830 static int __init calibrate_APIC_clock(void) 831 { 832 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 833 u64 tsc_perj = 0, tsc_start = 0; 834 unsigned long jif_start; 835 unsigned long deltaj; 836 long delta, deltatsc; 837 int pm_referenced = 0; 838 839 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 840 return 0; 841 842 /* 843 * Check if lapic timer has already been calibrated by platform 844 * specific routine, such as tsc calibration code. If so just fill 845 * in the clockevent structure and return. 846 */ 847 if (!lapic_init_clockevent()) { 848 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", 849 lapic_timer_period); 850 /* 851 * Direct calibration methods must have an always running 852 * local APIC timer, no need for broadcast timer. 853 */ 854 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 855 return 0; 856 } 857 858 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 859 "calibrating APIC timer ...\n"); 860 861 /* 862 * There are platforms w/o global clockevent devices. Instead of 863 * making the calibration conditional on that, use a polling based 864 * approach everywhere. 865 */ 866 local_irq_disable(); 867 868 /* 869 * Setup the APIC counter to maximum. There is no way the lapic 870 * can underflow in the 100ms detection time frame 871 */ 872 __setup_APIC_LVTT(0xffffffff, 0, 0); 873 874 /* 875 * Methods to terminate the calibration loop: 876 * 1) Global clockevent if available (jiffies) 877 * 2) TSC if available and frequency is known 878 */ 879 jif_start = READ_ONCE(jiffies); 880 881 if (tsc_khz) { 882 tsc_start = rdtsc(); 883 tsc_perj = div_u64((u64)tsc_khz * 1000, HZ); 884 } 885 886 /* 887 * Enable interrupts so the tick can fire, if a global 888 * clockevent device is available 889 */ 890 local_irq_enable(); 891 892 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) { 893 /* Wait for a tick to elapse */ 894 while (1) { 895 if (tsc_khz) { 896 u64 tsc_now = rdtsc(); 897 if ((tsc_now - tsc_start) >= tsc_perj) { 898 tsc_start += tsc_perj; 899 break; 900 } 901 } else { 902 unsigned long jif_now = READ_ONCE(jiffies); 903 904 if (time_after(jif_now, jif_start)) { 905 jif_start = jif_now; 906 break; 907 } 908 } 909 cpu_relax(); 910 } 911 912 /* Invoke the calibration routine */ 913 local_irq_disable(); 914 lapic_cal_handler(NULL); 915 local_irq_enable(); 916 } 917 918 local_irq_disable(); 919 920 /* Build delta t1-t2 as apic timer counts down */ 921 delta = lapic_cal_t1 - lapic_cal_t2; 922 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 923 924 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 925 926 /* we trust the PM based calibration if possible */ 927 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 928 &delta, &deltatsc); 929 930 lapic_timer_period = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 931 lapic_init_clockevent(); 932 933 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 934 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 935 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 936 lapic_timer_period); 937 938 if (boot_cpu_has(X86_FEATURE_TSC)) { 939 apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 940 "%ld.%04ld MHz.\n", 941 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 942 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 943 } 944 945 apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 946 "%u.%04u MHz.\n", 947 lapic_timer_period / (1000000 / HZ), 948 lapic_timer_period % (1000000 / HZ)); 949 950 /* 951 * Do a sanity check on the APIC calibration result 952 */ 953 if (lapic_timer_period < (1000000 / HZ)) { 954 local_irq_enable(); 955 pr_warn("APIC frequency too slow, disabling apic timer\n"); 956 return -1; 957 } 958 959 levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 960 961 /* 962 * PM timer calibration failed or not turned on so lets try APIC 963 * timer based calibration, if a global clockevent device is 964 * available. 965 */ 966 if (!pm_referenced && global_clock_event) { 967 apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 968 969 /* 970 * Setup the apic timer manually 971 */ 972 levt->event_handler = lapic_cal_handler; 973 lapic_timer_set_periodic(levt); 974 lapic_cal_loops = -1; 975 976 /* Let the interrupts run */ 977 local_irq_enable(); 978 979 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 980 cpu_relax(); 981 982 /* Stop the lapic timer */ 983 local_irq_disable(); 984 lapic_timer_shutdown(levt); 985 986 /* Jiffies delta */ 987 deltaj = lapic_cal_j2 - lapic_cal_j1; 988 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 989 990 /* Check, if the jiffies result is consistent */ 991 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 992 apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 993 else 994 levt->features |= CLOCK_EVT_FEAT_DUMMY; 995 } 996 local_irq_enable(); 997 998 if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 999 pr_warn("APIC timer disabled due to verification failure\n"); 1000 return -1; 1001 } 1002 1003 return 0; 1004 } 1005 1006 /* 1007 * Setup the boot APIC 1008 * 1009 * Calibrate and verify the result. 1010 */ 1011 void __init setup_boot_APIC_clock(void) 1012 { 1013 /* 1014 * The local apic timer can be disabled via the kernel 1015 * commandline or from the CPU detection code. Register the lapic 1016 * timer as a dummy clock event source on SMP systems, so the 1017 * broadcast mechanism is used. On UP systems simply ignore it. 1018 */ 1019 if (disable_apic_timer) { 1020 pr_info("Disabling APIC timer\n"); 1021 /* No broadcast on UP ! */ 1022 if (num_possible_cpus() > 1) { 1023 lapic_clockevent.mult = 1; 1024 setup_APIC_timer(); 1025 } 1026 return; 1027 } 1028 1029 if (calibrate_APIC_clock()) { 1030 /* No broadcast on UP ! */ 1031 if (num_possible_cpus() > 1) 1032 setup_APIC_timer(); 1033 return; 1034 } 1035 1036 /* 1037 * If nmi_watchdog is set to IO_APIC, we need the 1038 * PIT/HPET going. Otherwise register lapic as a dummy 1039 * device. 1040 */ 1041 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 1042 1043 /* Setup the lapic or request the broadcast */ 1044 setup_APIC_timer(); 1045 amd_e400_c1e_apic_setup(); 1046 } 1047 1048 void setup_secondary_APIC_clock(void) 1049 { 1050 setup_APIC_timer(); 1051 amd_e400_c1e_apic_setup(); 1052 } 1053 1054 /* 1055 * The guts of the apic timer interrupt 1056 */ 1057 static void local_apic_timer_interrupt(void) 1058 { 1059 struct clock_event_device *evt = this_cpu_ptr(&lapic_events); 1060 1061 /* 1062 * Normally we should not be here till LAPIC has been initialized but 1063 * in some cases like kdump, its possible that there is a pending LAPIC 1064 * timer interrupt from previous kernel's context and is delivered in 1065 * new kernel the moment interrupts are enabled. 1066 * 1067 * Interrupts are enabled early and LAPIC is setup much later, hence 1068 * its possible that when we get here evt->event_handler is NULL. 1069 * Check for event_handler being NULL and discard the interrupt as 1070 * spurious. 1071 */ 1072 if (!evt->event_handler) { 1073 pr_warn("Spurious LAPIC timer interrupt on cpu %d\n", 1074 smp_processor_id()); 1075 /* Switch it off */ 1076 lapic_timer_shutdown(evt); 1077 return; 1078 } 1079 1080 /* 1081 * the NMI deadlock-detector uses this. 1082 */ 1083 inc_irq_stat(apic_timer_irqs); 1084 1085 evt->event_handler(evt); 1086 } 1087 1088 /* 1089 * Local APIC timer interrupt. This is the most natural way for doing 1090 * local interrupts, but local timer interrupts can be emulated by 1091 * broadcast interrupts too. [in case the hw doesn't support APIC timers] 1092 * 1093 * [ if a single-CPU system runs an SMP kernel then we call the local 1094 * interrupt as well. Thus we cannot inline the local irq ... ] 1095 */ 1096 DEFINE_IDTENTRY_SYSVEC(sysvec_apic_timer_interrupt) 1097 { 1098 struct pt_regs *old_regs = set_irq_regs(regs); 1099 1100 ack_APIC_irq(); 1101 trace_local_timer_entry(LOCAL_TIMER_VECTOR); 1102 local_apic_timer_interrupt(); 1103 trace_local_timer_exit(LOCAL_TIMER_VECTOR); 1104 1105 set_irq_regs(old_regs); 1106 } 1107 1108 int setup_profiling_timer(unsigned int multiplier) 1109 { 1110 return -EINVAL; 1111 } 1112 1113 /* 1114 * Local APIC start and shutdown 1115 */ 1116 1117 /** 1118 * clear_local_APIC - shutdown the local APIC 1119 * 1120 * This is called, when a CPU is disabled and before rebooting, so the state of 1121 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 1122 * leftovers during boot. 1123 */ 1124 void clear_local_APIC(void) 1125 { 1126 int maxlvt; 1127 u32 v; 1128 1129 /* APIC hasn't been mapped yet */ 1130 if (!x2apic_mode && !apic_phys) 1131 return; 1132 1133 maxlvt = lapic_get_maxlvt(); 1134 /* 1135 * Masking an LVT entry can trigger a local APIC error 1136 * if the vector is zero. Mask LVTERR first to prevent this. 1137 */ 1138 if (maxlvt >= 3) { 1139 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 1140 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 1141 } 1142 /* 1143 * Careful: we have to set masks only first to deassert 1144 * any level-triggered sources. 1145 */ 1146 v = apic_read(APIC_LVTT); 1147 apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 1148 v = apic_read(APIC_LVT0); 1149 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 1150 v = apic_read(APIC_LVT1); 1151 apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 1152 if (maxlvt >= 4) { 1153 v = apic_read(APIC_LVTPC); 1154 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 1155 } 1156 1157 /* lets not touch this if we didn't frob it */ 1158 #ifdef CONFIG_X86_THERMAL_VECTOR 1159 if (maxlvt >= 5) { 1160 v = apic_read(APIC_LVTTHMR); 1161 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 1162 } 1163 #endif 1164 #ifdef CONFIG_X86_MCE_INTEL 1165 if (maxlvt >= 6) { 1166 v = apic_read(APIC_LVTCMCI); 1167 if (!(v & APIC_LVT_MASKED)) 1168 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 1169 } 1170 #endif 1171 1172 /* 1173 * Clean APIC state for other OSs: 1174 */ 1175 apic_write(APIC_LVTT, APIC_LVT_MASKED); 1176 apic_write(APIC_LVT0, APIC_LVT_MASKED); 1177 apic_write(APIC_LVT1, APIC_LVT_MASKED); 1178 if (maxlvt >= 3) 1179 apic_write(APIC_LVTERR, APIC_LVT_MASKED); 1180 if (maxlvt >= 4) 1181 apic_write(APIC_LVTPC, APIC_LVT_MASKED); 1182 1183 /* Integrated APIC (!82489DX) ? */ 1184 if (lapic_is_integrated()) { 1185 if (maxlvt > 3) 1186 /* Clear ESR due to Pentium errata 3AP and 11AP */ 1187 apic_write(APIC_ESR, 0); 1188 apic_read(APIC_ESR); 1189 } 1190 } 1191 1192 /** 1193 * apic_soft_disable - Clears and software disables the local APIC on hotplug 1194 * 1195 * Contrary to disable_local_APIC() this does not touch the enable bit in 1196 * MSR_IA32_APICBASE. Clearing that bit on systems based on the 3 wire APIC 1197 * bus would require a hardware reset as the APIC would lose track of bus 1198 * arbitration. On systems with FSB delivery APICBASE could be disabled, 1199 * but it has to be guaranteed that no interrupt is sent to the APIC while 1200 * in that state and it's not clear from the SDM whether it still responds 1201 * to INIT/SIPI messages. Stay on the safe side and use software disable. 1202 */ 1203 void apic_soft_disable(void) 1204 { 1205 u32 value; 1206 1207 clear_local_APIC(); 1208 1209 /* Soft disable APIC (implies clearing of registers for 82489DX!). */ 1210 value = apic_read(APIC_SPIV); 1211 value &= ~APIC_SPIV_APIC_ENABLED; 1212 apic_write(APIC_SPIV, value); 1213 } 1214 1215 /** 1216 * disable_local_APIC - clear and disable the local APIC 1217 */ 1218 void disable_local_APIC(void) 1219 { 1220 /* APIC hasn't been mapped yet */ 1221 if (!x2apic_mode && !apic_phys) 1222 return; 1223 1224 apic_soft_disable(); 1225 1226 #ifdef CONFIG_X86_32 1227 /* 1228 * When LAPIC was disabled by the BIOS and enabled by the kernel, 1229 * restore the disabled state. 1230 */ 1231 if (enabled_via_apicbase) { 1232 unsigned int l, h; 1233 1234 rdmsr(MSR_IA32_APICBASE, l, h); 1235 l &= ~MSR_IA32_APICBASE_ENABLE; 1236 wrmsr(MSR_IA32_APICBASE, l, h); 1237 } 1238 #endif 1239 } 1240 1241 /* 1242 * If Linux enabled the LAPIC against the BIOS default disable it down before 1243 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 1244 * not power-off. Additionally clear all LVT entries before disable_local_APIC 1245 * for the case where Linux didn't enable the LAPIC. 1246 */ 1247 void lapic_shutdown(void) 1248 { 1249 unsigned long flags; 1250 1251 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) 1252 return; 1253 1254 local_irq_save(flags); 1255 1256 #ifdef CONFIG_X86_32 1257 if (!enabled_via_apicbase) 1258 clear_local_APIC(); 1259 else 1260 #endif 1261 disable_local_APIC(); 1262 1263 1264 local_irq_restore(flags); 1265 } 1266 1267 /** 1268 * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1269 */ 1270 void __init sync_Arb_IDs(void) 1271 { 1272 /* 1273 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1274 * needed on AMD. 1275 */ 1276 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1277 return; 1278 1279 /* 1280 * Wait for idle. 1281 */ 1282 apic_wait_icr_idle(); 1283 1284 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1285 apic_write(APIC_ICR, APIC_DEST_ALLINC | 1286 APIC_INT_LEVELTRIG | APIC_DM_INIT); 1287 } 1288 1289 enum apic_intr_mode_id apic_intr_mode __ro_after_init; 1290 1291 static int __init __apic_intr_mode_select(void) 1292 { 1293 /* Check kernel option */ 1294 if (disable_apic) { 1295 pr_info("APIC disabled via kernel command line\n"); 1296 return APIC_PIC; 1297 } 1298 1299 /* Check BIOS */ 1300 #ifdef CONFIG_X86_64 1301 /* On 64-bit, the APIC must be integrated, Check local APIC only */ 1302 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1303 disable_apic = 1; 1304 pr_info("APIC disabled by BIOS\n"); 1305 return APIC_PIC; 1306 } 1307 #else 1308 /* On 32-bit, the APIC may be integrated APIC or 82489DX */ 1309 1310 /* Neither 82489DX nor integrated APIC ? */ 1311 if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) { 1312 disable_apic = 1; 1313 return APIC_PIC; 1314 } 1315 1316 /* If the BIOS pretends there is an integrated APIC ? */ 1317 if (!boot_cpu_has(X86_FEATURE_APIC) && 1318 APIC_INTEGRATED(boot_cpu_apic_version)) { 1319 disable_apic = 1; 1320 pr_err(FW_BUG "Local APIC %d not detected, force emulation\n", 1321 boot_cpu_physical_apicid); 1322 return APIC_PIC; 1323 } 1324 #endif 1325 1326 /* Check MP table or ACPI MADT configuration */ 1327 if (!smp_found_config) { 1328 disable_ioapic_support(); 1329 if (!acpi_lapic) { 1330 pr_info("APIC: ACPI MADT or MP tables are not detected\n"); 1331 return APIC_VIRTUAL_WIRE_NO_CONFIG; 1332 } 1333 return APIC_VIRTUAL_WIRE; 1334 } 1335 1336 #ifdef CONFIG_SMP 1337 /* If SMP should be disabled, then really disable it! */ 1338 if (!setup_max_cpus) { 1339 pr_info("APIC: SMP mode deactivated\n"); 1340 return APIC_SYMMETRIC_IO_NO_ROUTING; 1341 } 1342 1343 if (read_apic_id() != boot_cpu_physical_apicid) { 1344 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1345 read_apic_id(), boot_cpu_physical_apicid); 1346 /* Or can we switch back to PIC here? */ 1347 } 1348 #endif 1349 1350 return APIC_SYMMETRIC_IO; 1351 } 1352 1353 /* Select the interrupt delivery mode for the BSP */ 1354 void __init apic_intr_mode_select(void) 1355 { 1356 apic_intr_mode = __apic_intr_mode_select(); 1357 } 1358 1359 /* 1360 * An initial setup of the virtual wire mode. 1361 */ 1362 void __init init_bsp_APIC(void) 1363 { 1364 unsigned int value; 1365 1366 /* 1367 * Don't do the setup now if we have a SMP BIOS as the 1368 * through-I/O-APIC virtual wire mode might be active. 1369 */ 1370 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC)) 1371 return; 1372 1373 /* 1374 * Do not trust the local APIC being empty at bootup. 1375 */ 1376 clear_local_APIC(); 1377 1378 /* 1379 * Enable APIC. 1380 */ 1381 value = apic_read(APIC_SPIV); 1382 value &= ~APIC_VECTOR_MASK; 1383 value |= APIC_SPIV_APIC_ENABLED; 1384 1385 #ifdef CONFIG_X86_32 1386 /* This bit is reserved on P4/Xeon and should be cleared */ 1387 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1388 (boot_cpu_data.x86 == 15)) 1389 value &= ~APIC_SPIV_FOCUS_DISABLED; 1390 else 1391 #endif 1392 value |= APIC_SPIV_FOCUS_DISABLED; 1393 value |= SPURIOUS_APIC_VECTOR; 1394 apic_write(APIC_SPIV, value); 1395 1396 /* 1397 * Set up the virtual wire mode. 1398 */ 1399 apic_write(APIC_LVT0, APIC_DM_EXTINT); 1400 value = APIC_DM_NMI; 1401 if (!lapic_is_integrated()) /* 82489DX */ 1402 value |= APIC_LVT_LEVEL_TRIGGER; 1403 if (apic_extnmi == APIC_EXTNMI_NONE) 1404 value |= APIC_LVT_MASKED; 1405 apic_write(APIC_LVT1, value); 1406 } 1407 1408 static void __init apic_bsp_setup(bool upmode); 1409 1410 /* Init the interrupt delivery mode for the BSP */ 1411 void __init apic_intr_mode_init(void) 1412 { 1413 bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT); 1414 1415 switch (apic_intr_mode) { 1416 case APIC_PIC: 1417 pr_info("APIC: Keep in PIC mode(8259)\n"); 1418 return; 1419 case APIC_VIRTUAL_WIRE: 1420 pr_info("APIC: Switch to virtual wire mode setup\n"); 1421 default_setup_apic_routing(); 1422 break; 1423 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1424 pr_info("APIC: Switch to virtual wire mode setup with no configuration\n"); 1425 upmode = true; 1426 default_setup_apic_routing(); 1427 break; 1428 case APIC_SYMMETRIC_IO: 1429 pr_info("APIC: Switch to symmetric I/O mode setup\n"); 1430 default_setup_apic_routing(); 1431 break; 1432 case APIC_SYMMETRIC_IO_NO_ROUTING: 1433 pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n"); 1434 break; 1435 } 1436 1437 if (x86_platform.apic_post_init) 1438 x86_platform.apic_post_init(); 1439 1440 apic_bsp_setup(upmode); 1441 } 1442 1443 static void lapic_setup_esr(void) 1444 { 1445 unsigned int oldvalue, value, maxlvt; 1446 1447 if (!lapic_is_integrated()) { 1448 pr_info("No ESR for 82489DX.\n"); 1449 return; 1450 } 1451 1452 if (apic->disable_esr) { 1453 /* 1454 * Something untraceable is creating bad interrupts on 1455 * secondary quads ... for the moment, just leave the 1456 * ESR disabled - we can't do anything useful with the 1457 * errors anyway - mbligh 1458 */ 1459 pr_info("Leaving ESR disabled.\n"); 1460 return; 1461 } 1462 1463 maxlvt = lapic_get_maxlvt(); 1464 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1465 apic_write(APIC_ESR, 0); 1466 oldvalue = apic_read(APIC_ESR); 1467 1468 /* enables sending errors */ 1469 value = ERROR_APIC_VECTOR; 1470 apic_write(APIC_LVTERR, value); 1471 1472 /* 1473 * spec says clear errors after enabling vector. 1474 */ 1475 if (maxlvt > 3) 1476 apic_write(APIC_ESR, 0); 1477 value = apic_read(APIC_ESR); 1478 if (value != oldvalue) 1479 apic_printk(APIC_VERBOSE, "ESR value before enabling " 1480 "vector: 0x%08x after: 0x%08x\n", 1481 oldvalue, value); 1482 } 1483 1484 #define APIC_IR_REGS APIC_ISR_NR 1485 #define APIC_IR_BITS (APIC_IR_REGS * 32) 1486 #define APIC_IR_MAPSIZE (APIC_IR_BITS / BITS_PER_LONG) 1487 1488 union apic_ir { 1489 unsigned long map[APIC_IR_MAPSIZE]; 1490 u32 regs[APIC_IR_REGS]; 1491 }; 1492 1493 static bool apic_check_and_ack(union apic_ir *irr, union apic_ir *isr) 1494 { 1495 int i, bit; 1496 1497 /* Read the IRRs */ 1498 for (i = 0; i < APIC_IR_REGS; i++) 1499 irr->regs[i] = apic_read(APIC_IRR + i * 0x10); 1500 1501 /* Read the ISRs */ 1502 for (i = 0; i < APIC_IR_REGS; i++) 1503 isr->regs[i] = apic_read(APIC_ISR + i * 0x10); 1504 1505 /* 1506 * If the ISR map is not empty. ACK the APIC and run another round 1507 * to verify whether a pending IRR has been unblocked and turned 1508 * into a ISR. 1509 */ 1510 if (!bitmap_empty(isr->map, APIC_IR_BITS)) { 1511 /* 1512 * There can be multiple ISR bits set when a high priority 1513 * interrupt preempted a lower priority one. Issue an ACK 1514 * per set bit. 1515 */ 1516 for_each_set_bit(bit, isr->map, APIC_IR_BITS) 1517 ack_APIC_irq(); 1518 return true; 1519 } 1520 1521 return !bitmap_empty(irr->map, APIC_IR_BITS); 1522 } 1523 1524 /* 1525 * After a crash, we no longer service the interrupts and a pending 1526 * interrupt from previous kernel might still have ISR bit set. 1527 * 1528 * Most probably by now the CPU has serviced that pending interrupt and it 1529 * might not have done the ack_APIC_irq() because it thought, interrupt 1530 * came from i8259 as ExtInt. LAPIC did not get EOI so it does not clear 1531 * the ISR bit and cpu thinks it has already serivced the interrupt. Hence 1532 * a vector might get locked. It was noticed for timer irq (vector 1533 * 0x31). Issue an extra EOI to clear ISR. 1534 * 1535 * If there are pending IRR bits they turn into ISR bits after a higher 1536 * priority ISR bit has been acked. 1537 */ 1538 static void apic_pending_intr_clear(void) 1539 { 1540 union apic_ir irr, isr; 1541 unsigned int i; 1542 1543 /* 512 loops are way oversized and give the APIC a chance to obey. */ 1544 for (i = 0; i < 512; i++) { 1545 if (!apic_check_and_ack(&irr, &isr)) 1546 return; 1547 } 1548 /* Dump the IRR/ISR content if that failed */ 1549 pr_warn("APIC: Stale IRR: %256pb ISR: %256pb\n", irr.map, isr.map); 1550 } 1551 1552 /** 1553 * setup_local_APIC - setup the local APIC 1554 * 1555 * Used to setup local APIC while initializing BSP or bringing up APs. 1556 * Always called with preemption disabled. 1557 */ 1558 static void setup_local_APIC(void) 1559 { 1560 int cpu = smp_processor_id(); 1561 unsigned int value; 1562 1563 if (disable_apic) { 1564 disable_ioapic_support(); 1565 return; 1566 } 1567 1568 /* 1569 * If this comes from kexec/kcrash the APIC might be enabled in 1570 * SPIV. Soft disable it before doing further initialization. 1571 */ 1572 value = apic_read(APIC_SPIV); 1573 value &= ~APIC_SPIV_APIC_ENABLED; 1574 apic_write(APIC_SPIV, value); 1575 1576 #ifdef CONFIG_X86_32 1577 /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1578 if (lapic_is_integrated() && apic->disable_esr) { 1579 apic_write(APIC_ESR, 0); 1580 apic_write(APIC_ESR, 0); 1581 apic_write(APIC_ESR, 0); 1582 apic_write(APIC_ESR, 0); 1583 } 1584 #endif 1585 /* 1586 * Double-check whether this APIC is really registered. 1587 * This is meaningless in clustered apic mode, so we skip it. 1588 */ 1589 BUG_ON(!apic->apic_id_registered()); 1590 1591 /* 1592 * Intel recommends to set DFR, LDR and TPR before enabling 1593 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1594 * document number 292116). So here it goes... 1595 */ 1596 apic->init_apic_ldr(); 1597 1598 #ifdef CONFIG_X86_32 1599 if (apic->dest_mode_logical) { 1600 int logical_apicid, ldr_apicid; 1601 1602 /* 1603 * APIC LDR is initialized. If logical_apicid mapping was 1604 * initialized during get_smp_config(), make sure it matches 1605 * the actual value. 1606 */ 1607 logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu); 1608 ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 1609 if (logical_apicid != BAD_APICID) 1610 WARN_ON(logical_apicid != ldr_apicid); 1611 /* Always use the value from LDR. */ 1612 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid; 1613 } 1614 #endif 1615 1616 /* 1617 * Set Task Priority to 'accept all except vectors 0-31'. An APIC 1618 * vector in the 16-31 range could be delivered if TPR == 0, but we 1619 * would think it's an exception and terrible things will happen. We 1620 * never change this later on. 1621 */ 1622 value = apic_read(APIC_TASKPRI); 1623 value &= ~APIC_TPRI_MASK; 1624 value |= 0x10; 1625 apic_write(APIC_TASKPRI, value); 1626 1627 /* Clear eventually stale ISR/IRR bits */ 1628 apic_pending_intr_clear(); 1629 1630 /* 1631 * Now that we are all set up, enable the APIC 1632 */ 1633 value = apic_read(APIC_SPIV); 1634 value &= ~APIC_VECTOR_MASK; 1635 /* 1636 * Enable APIC 1637 */ 1638 value |= APIC_SPIV_APIC_ENABLED; 1639 1640 #ifdef CONFIG_X86_32 1641 /* 1642 * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1643 * certain networking cards. If high frequency interrupts are 1644 * happening on a particular IOAPIC pin, plus the IOAPIC routing 1645 * entry is masked/unmasked at a high rate as well then sooner or 1646 * later IOAPIC line gets 'stuck', no more interrupts are received 1647 * from the device. If focus CPU is disabled then the hang goes 1648 * away, oh well :-( 1649 * 1650 * [ This bug can be reproduced easily with a level-triggered 1651 * PCI Ne2000 networking cards and PII/PIII processors, dual 1652 * BX chipset. ] 1653 */ 1654 /* 1655 * Actually disabling the focus CPU check just makes the hang less 1656 * frequent as it makes the interrupt distributon model be more 1657 * like LRU than MRU (the short-term load is more even across CPUs). 1658 */ 1659 1660 /* 1661 * - enable focus processor (bit==0) 1662 * - 64bit mode always use processor focus 1663 * so no need to set it 1664 */ 1665 value &= ~APIC_SPIV_FOCUS_DISABLED; 1666 #endif 1667 1668 /* 1669 * Set spurious IRQ vector 1670 */ 1671 value |= SPURIOUS_APIC_VECTOR; 1672 apic_write(APIC_SPIV, value); 1673 1674 perf_events_lapic_init(); 1675 1676 /* 1677 * Set up LVT0, LVT1: 1678 * 1679 * set up through-local-APIC on the boot CPU's LINT0. This is not 1680 * strictly necessary in pure symmetric-IO mode, but sometimes 1681 * we delegate interrupts to the 8259A. 1682 */ 1683 /* 1684 * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1685 */ 1686 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1687 if (!cpu && (pic_mode || !value || skip_ioapic_setup)) { 1688 value = APIC_DM_EXTINT; 1689 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1690 } else { 1691 value = APIC_DM_EXTINT | APIC_LVT_MASKED; 1692 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1693 } 1694 apic_write(APIC_LVT0, value); 1695 1696 /* 1697 * Only the BSP sees the LINT1 NMI signal by default. This can be 1698 * modified by apic_extnmi= boot option. 1699 */ 1700 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) || 1701 apic_extnmi == APIC_EXTNMI_ALL) 1702 value = APIC_DM_NMI; 1703 else 1704 value = APIC_DM_NMI | APIC_LVT_MASKED; 1705 1706 /* Is 82489DX ? */ 1707 if (!lapic_is_integrated()) 1708 value |= APIC_LVT_LEVEL_TRIGGER; 1709 apic_write(APIC_LVT1, value); 1710 1711 #ifdef CONFIG_X86_MCE_INTEL 1712 /* Recheck CMCI information after local APIC is up on CPU #0 */ 1713 if (!cpu) 1714 cmci_recheck(); 1715 #endif 1716 } 1717 1718 static void end_local_APIC_setup(void) 1719 { 1720 lapic_setup_esr(); 1721 1722 #ifdef CONFIG_X86_32 1723 { 1724 unsigned int value; 1725 /* Disable the local apic timer */ 1726 value = apic_read(APIC_LVTT); 1727 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1728 apic_write(APIC_LVTT, value); 1729 } 1730 #endif 1731 1732 apic_pm_activate(); 1733 } 1734 1735 /* 1736 * APIC setup function for application processors. Called from smpboot.c 1737 */ 1738 void apic_ap_setup(void) 1739 { 1740 setup_local_APIC(); 1741 end_local_APIC_setup(); 1742 } 1743 1744 #ifdef CONFIG_X86_X2APIC 1745 int x2apic_mode; 1746 1747 enum { 1748 X2APIC_OFF, 1749 X2APIC_ON, 1750 X2APIC_DISABLED, 1751 }; 1752 static int x2apic_state; 1753 1754 static void __x2apic_disable(void) 1755 { 1756 u64 msr; 1757 1758 if (!boot_cpu_has(X86_FEATURE_APIC)) 1759 return; 1760 1761 rdmsrl(MSR_IA32_APICBASE, msr); 1762 if (!(msr & X2APIC_ENABLE)) 1763 return; 1764 /* Disable xapic and x2apic first and then reenable xapic mode */ 1765 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); 1766 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); 1767 printk_once(KERN_INFO "x2apic disabled\n"); 1768 } 1769 1770 static void __x2apic_enable(void) 1771 { 1772 u64 msr; 1773 1774 rdmsrl(MSR_IA32_APICBASE, msr); 1775 if (msr & X2APIC_ENABLE) 1776 return; 1777 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); 1778 printk_once(KERN_INFO "x2apic enabled\n"); 1779 } 1780 1781 static int __init setup_nox2apic(char *str) 1782 { 1783 if (x2apic_enabled()) { 1784 int apicid = native_apic_msr_read(APIC_ID); 1785 1786 if (apicid >= 255) { 1787 pr_warn("Apicid: %08x, cannot enforce nox2apic\n", 1788 apicid); 1789 return 0; 1790 } 1791 pr_warn("x2apic already enabled.\n"); 1792 __x2apic_disable(); 1793 } 1794 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 1795 x2apic_state = X2APIC_DISABLED; 1796 x2apic_mode = 0; 1797 return 0; 1798 } 1799 early_param("nox2apic", setup_nox2apic); 1800 1801 /* Called from cpu_init() to enable x2apic on (secondary) cpus */ 1802 void x2apic_setup(void) 1803 { 1804 /* 1805 * If x2apic is not in ON state, disable it if already enabled 1806 * from BIOS. 1807 */ 1808 if (x2apic_state != X2APIC_ON) { 1809 __x2apic_disable(); 1810 return; 1811 } 1812 __x2apic_enable(); 1813 } 1814 1815 static __init void x2apic_disable(void) 1816 { 1817 u32 x2apic_id, state = x2apic_state; 1818 1819 x2apic_mode = 0; 1820 x2apic_state = X2APIC_DISABLED; 1821 1822 if (state != X2APIC_ON) 1823 return; 1824 1825 x2apic_id = read_apic_id(); 1826 if (x2apic_id >= 255) 1827 panic("Cannot disable x2apic, id: %08x\n", x2apic_id); 1828 1829 __x2apic_disable(); 1830 register_lapic_address(mp_lapic_addr); 1831 } 1832 1833 static __init void x2apic_enable(void) 1834 { 1835 if (x2apic_state != X2APIC_OFF) 1836 return; 1837 1838 x2apic_mode = 1; 1839 x2apic_state = X2APIC_ON; 1840 __x2apic_enable(); 1841 } 1842 1843 static __init void try_to_enable_x2apic(int remap_mode) 1844 { 1845 if (x2apic_state == X2APIC_DISABLED) 1846 return; 1847 1848 if (remap_mode != IRQ_REMAP_X2APIC_MODE) { 1849 u32 apic_limit = 255; 1850 1851 /* 1852 * Using X2APIC without IR is not architecturally supported 1853 * on bare metal but may be supported in guests. 1854 */ 1855 if (!x86_init.hyper.x2apic_available()) { 1856 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); 1857 x2apic_disable(); 1858 return; 1859 } 1860 1861 /* 1862 * If the hypervisor supports extended destination ID in 1863 * MSI, that increases the maximum APIC ID that can be 1864 * used for non-remapped IRQ domains. 1865 */ 1866 if (x86_init.hyper.msi_ext_dest_id()) { 1867 virt_ext_dest_id = 1; 1868 apic_limit = 32767; 1869 } 1870 1871 /* 1872 * Without IR, all CPUs can be addressed by IOAPIC/MSI only 1873 * in physical mode, and CPUs with an APIC ID that cannnot 1874 * be addressed must not be brought online. 1875 */ 1876 x2apic_set_max_apicid(apic_limit); 1877 x2apic_phys = 1; 1878 } 1879 x2apic_enable(); 1880 } 1881 1882 void __init check_x2apic(void) 1883 { 1884 if (x2apic_enabled()) { 1885 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); 1886 x2apic_mode = 1; 1887 x2apic_state = X2APIC_ON; 1888 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) { 1889 x2apic_state = X2APIC_DISABLED; 1890 } 1891 } 1892 #else /* CONFIG_X86_X2APIC */ 1893 static int __init validate_x2apic(void) 1894 { 1895 if (!apic_is_x2apic_enabled()) 1896 return 0; 1897 /* 1898 * Checkme: Can we simply turn off x2apic here instead of panic? 1899 */ 1900 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n"); 1901 } 1902 early_initcall(validate_x2apic); 1903 1904 static inline void try_to_enable_x2apic(int remap_mode) { } 1905 static inline void __x2apic_enable(void) { } 1906 #endif /* !CONFIG_X86_X2APIC */ 1907 1908 void __init enable_IR_x2apic(void) 1909 { 1910 unsigned long flags; 1911 int ret, ir_stat; 1912 1913 if (skip_ioapic_setup) { 1914 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); 1915 return; 1916 } 1917 1918 ir_stat = irq_remapping_prepare(); 1919 if (ir_stat < 0 && !x2apic_supported()) 1920 return; 1921 1922 ret = save_ioapic_entries(); 1923 if (ret) { 1924 pr_info("Saving IO-APIC state failed: %d\n", ret); 1925 return; 1926 } 1927 1928 local_irq_save(flags); 1929 legacy_pic->mask_all(); 1930 mask_ioapic_entries(); 1931 1932 /* If irq_remapping_prepare() succeeded, try to enable it */ 1933 if (ir_stat >= 0) 1934 ir_stat = irq_remapping_enable(); 1935 /* ir_stat contains the remap mode or an error code */ 1936 try_to_enable_x2apic(ir_stat); 1937 1938 if (ir_stat < 0) 1939 restore_ioapic_entries(); 1940 legacy_pic->restore_mask(); 1941 local_irq_restore(flags); 1942 } 1943 1944 #ifdef CONFIG_X86_64 1945 /* 1946 * Detect and enable local APICs on non-SMP boards. 1947 * Original code written by Keir Fraser. 1948 * On AMD64 we trust the BIOS - if it says no APIC it is likely 1949 * not correctly set up (usually the APIC timer won't work etc.) 1950 */ 1951 static int __init detect_init_APIC(void) 1952 { 1953 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1954 pr_info("No local APIC present\n"); 1955 return -1; 1956 } 1957 1958 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1959 return 0; 1960 } 1961 #else 1962 1963 static int __init apic_verify(void) 1964 { 1965 u32 features, h, l; 1966 1967 /* 1968 * The APIC feature bit should now be enabled 1969 * in `cpuid' 1970 */ 1971 features = cpuid_edx(1); 1972 if (!(features & (1 << X86_FEATURE_APIC))) { 1973 pr_warn("Could not enable APIC!\n"); 1974 return -1; 1975 } 1976 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1977 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1978 1979 /* The BIOS may have set up the APIC at some other address */ 1980 if (boot_cpu_data.x86 >= 6) { 1981 rdmsr(MSR_IA32_APICBASE, l, h); 1982 if (l & MSR_IA32_APICBASE_ENABLE) 1983 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1984 } 1985 1986 pr_info("Found and enabled local APIC!\n"); 1987 return 0; 1988 } 1989 1990 int __init apic_force_enable(unsigned long addr) 1991 { 1992 u32 h, l; 1993 1994 if (disable_apic) 1995 return -1; 1996 1997 /* 1998 * Some BIOSes disable the local APIC in the APIC_BASE 1999 * MSR. This can only be done in software for Intel P6 or later 2000 * and AMD K7 (Model > 1) or later. 2001 */ 2002 if (boot_cpu_data.x86 >= 6) { 2003 rdmsr(MSR_IA32_APICBASE, l, h); 2004 if (!(l & MSR_IA32_APICBASE_ENABLE)) { 2005 pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 2006 l &= ~MSR_IA32_APICBASE_BASE; 2007 l |= MSR_IA32_APICBASE_ENABLE | addr; 2008 wrmsr(MSR_IA32_APICBASE, l, h); 2009 enabled_via_apicbase = 1; 2010 } 2011 } 2012 return apic_verify(); 2013 } 2014 2015 /* 2016 * Detect and initialize APIC 2017 */ 2018 static int __init detect_init_APIC(void) 2019 { 2020 /* Disabled by kernel option? */ 2021 if (disable_apic) 2022 return -1; 2023 2024 switch (boot_cpu_data.x86_vendor) { 2025 case X86_VENDOR_AMD: 2026 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 2027 (boot_cpu_data.x86 >= 15)) 2028 break; 2029 goto no_apic; 2030 case X86_VENDOR_HYGON: 2031 break; 2032 case X86_VENDOR_INTEL: 2033 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 2034 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC))) 2035 break; 2036 goto no_apic; 2037 default: 2038 goto no_apic; 2039 } 2040 2041 if (!boot_cpu_has(X86_FEATURE_APIC)) { 2042 /* 2043 * Over-ride BIOS and try to enable the local APIC only if 2044 * "lapic" specified. 2045 */ 2046 if (!force_enable_local_apic) { 2047 pr_info("Local APIC disabled by BIOS -- " 2048 "you can enable it with \"lapic\"\n"); 2049 return -1; 2050 } 2051 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) 2052 return -1; 2053 } else { 2054 if (apic_verify()) 2055 return -1; 2056 } 2057 2058 apic_pm_activate(); 2059 2060 return 0; 2061 2062 no_apic: 2063 pr_info("No local APIC present or hardware disabled\n"); 2064 return -1; 2065 } 2066 #endif 2067 2068 /** 2069 * init_apic_mappings - initialize APIC mappings 2070 */ 2071 void __init init_apic_mappings(void) 2072 { 2073 unsigned int new_apicid; 2074 2075 if (apic_validate_deadline_timer()) 2076 pr_info("TSC deadline timer available\n"); 2077 2078 if (x2apic_mode) { 2079 boot_cpu_physical_apicid = read_apic_id(); 2080 return; 2081 } 2082 2083 /* If no local APIC can be found return early */ 2084 if (!smp_found_config && detect_init_APIC()) { 2085 /* lets NOP'ify apic operations */ 2086 pr_info("APIC: disable apic facility\n"); 2087 apic_disable(); 2088 } else { 2089 apic_phys = mp_lapic_addr; 2090 2091 /* 2092 * If the system has ACPI MADT tables or MP info, the LAPIC 2093 * address is already registered. 2094 */ 2095 if (!acpi_lapic && !smp_found_config) 2096 register_lapic_address(apic_phys); 2097 } 2098 2099 /* 2100 * Fetch the APIC ID of the BSP in case we have a 2101 * default configuration (or the MP table is broken). 2102 */ 2103 new_apicid = read_apic_id(); 2104 if (boot_cpu_physical_apicid != new_apicid) { 2105 boot_cpu_physical_apicid = new_apicid; 2106 /* 2107 * yeah -- we lie about apic_version 2108 * in case if apic was disabled via boot option 2109 * but it's not a problem for SMP compiled kernel 2110 * since apic_intr_mode_select is prepared for such 2111 * a case and disable smp mode 2112 */ 2113 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 2114 } 2115 } 2116 2117 void __init register_lapic_address(unsigned long address) 2118 { 2119 mp_lapic_addr = address; 2120 2121 if (!x2apic_mode) { 2122 set_fixmap_nocache(FIX_APIC_BASE, address); 2123 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 2124 APIC_BASE, address); 2125 } 2126 if (boot_cpu_physical_apicid == -1U) { 2127 boot_cpu_physical_apicid = read_apic_id(); 2128 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 2129 } 2130 } 2131 2132 /* 2133 * Local APIC interrupts 2134 */ 2135 2136 /** 2137 * spurious_interrupt - Catch all for interrupts raised on unused vectors 2138 * @regs: Pointer to pt_regs on stack 2139 * @vector: The vector number 2140 * 2141 * This is invoked from ASM entry code to catch all interrupts which 2142 * trigger on an entry which is routed to the common_spurious idtentry 2143 * point. 2144 * 2145 * Also called from sysvec_spurious_apic_interrupt(). 2146 */ 2147 DEFINE_IDTENTRY_IRQ(spurious_interrupt) 2148 { 2149 u32 v; 2150 2151 trace_spurious_apic_entry(vector); 2152 2153 inc_irq_stat(irq_spurious_count); 2154 2155 /* 2156 * If this is a spurious interrupt then do not acknowledge 2157 */ 2158 if (vector == SPURIOUS_APIC_VECTOR) { 2159 /* See SDM vol 3 */ 2160 pr_info("Spurious APIC interrupt (vector 0xFF) on CPU#%d, should never happen.\n", 2161 smp_processor_id()); 2162 goto out; 2163 } 2164 2165 /* 2166 * If it is a vectored one, verify it's set in the ISR. If set, 2167 * acknowledge it. 2168 */ 2169 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); 2170 if (v & (1 << (vector & 0x1f))) { 2171 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Acked\n", 2172 vector, smp_processor_id()); 2173 ack_APIC_irq(); 2174 } else { 2175 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Not pending!\n", 2176 vector, smp_processor_id()); 2177 } 2178 out: 2179 trace_spurious_apic_exit(vector); 2180 } 2181 2182 DEFINE_IDTENTRY_SYSVEC(sysvec_spurious_apic_interrupt) 2183 { 2184 __spurious_interrupt(regs, SPURIOUS_APIC_VECTOR); 2185 } 2186 2187 /* 2188 * This interrupt should never happen with our APIC/SMP architecture 2189 */ 2190 DEFINE_IDTENTRY_SYSVEC(sysvec_error_interrupt) 2191 { 2192 static const char * const error_interrupt_reason[] = { 2193 "Send CS error", /* APIC Error Bit 0 */ 2194 "Receive CS error", /* APIC Error Bit 1 */ 2195 "Send accept error", /* APIC Error Bit 2 */ 2196 "Receive accept error", /* APIC Error Bit 3 */ 2197 "Redirectable IPI", /* APIC Error Bit 4 */ 2198 "Send illegal vector", /* APIC Error Bit 5 */ 2199 "Received illegal vector", /* APIC Error Bit 6 */ 2200 "Illegal register address", /* APIC Error Bit 7 */ 2201 }; 2202 u32 v, i = 0; 2203 2204 trace_error_apic_entry(ERROR_APIC_VECTOR); 2205 2206 /* First tickle the hardware, only then report what went on. -- REW */ 2207 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ 2208 apic_write(APIC_ESR, 0); 2209 v = apic_read(APIC_ESR); 2210 ack_APIC_irq(); 2211 atomic_inc(&irq_err_count); 2212 2213 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", 2214 smp_processor_id(), v); 2215 2216 v &= 0xff; 2217 while (v) { 2218 if (v & 0x1) 2219 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); 2220 i++; 2221 v >>= 1; 2222 } 2223 2224 apic_printk(APIC_DEBUG, KERN_CONT "\n"); 2225 2226 trace_error_apic_exit(ERROR_APIC_VECTOR); 2227 } 2228 2229 /** 2230 * connect_bsp_APIC - attach the APIC to the interrupt system 2231 */ 2232 static void __init connect_bsp_APIC(void) 2233 { 2234 #ifdef CONFIG_X86_32 2235 if (pic_mode) { 2236 /* 2237 * Do not trust the local APIC being empty at bootup. 2238 */ 2239 clear_local_APIC(); 2240 /* 2241 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 2242 * local APIC to INT and NMI lines. 2243 */ 2244 apic_printk(APIC_VERBOSE, "leaving PIC mode, " 2245 "enabling APIC mode.\n"); 2246 imcr_pic_to_apic(); 2247 } 2248 #endif 2249 } 2250 2251 /** 2252 * disconnect_bsp_APIC - detach the APIC from the interrupt system 2253 * @virt_wire_setup: indicates, whether virtual wire mode is selected 2254 * 2255 * Virtual wire mode is necessary to deliver legacy interrupts even when the 2256 * APIC is disabled. 2257 */ 2258 void disconnect_bsp_APIC(int virt_wire_setup) 2259 { 2260 unsigned int value; 2261 2262 #ifdef CONFIG_X86_32 2263 if (pic_mode) { 2264 /* 2265 * Put the board back into PIC mode (has an effect only on 2266 * certain older boards). Note that APIC interrupts, including 2267 * IPIs, won't work beyond this point! The only exception are 2268 * INIT IPIs. 2269 */ 2270 apic_printk(APIC_VERBOSE, "disabling APIC mode, " 2271 "entering PIC mode.\n"); 2272 imcr_apic_to_pic(); 2273 return; 2274 } 2275 #endif 2276 2277 /* Go back to Virtual Wire compatibility mode */ 2278 2279 /* For the spurious interrupt use vector F, and enable it */ 2280 value = apic_read(APIC_SPIV); 2281 value &= ~APIC_VECTOR_MASK; 2282 value |= APIC_SPIV_APIC_ENABLED; 2283 value |= 0xf; 2284 apic_write(APIC_SPIV, value); 2285 2286 if (!virt_wire_setup) { 2287 /* 2288 * For LVT0 make it edge triggered, active high, 2289 * external and enabled 2290 */ 2291 value = apic_read(APIC_LVT0); 2292 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2293 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2294 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2295 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2296 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 2297 apic_write(APIC_LVT0, value); 2298 } else { 2299 /* Disable LVT0 */ 2300 apic_write(APIC_LVT0, APIC_LVT_MASKED); 2301 } 2302 2303 /* 2304 * For LVT1 make it edge triggered, active high, 2305 * nmi and enabled 2306 */ 2307 value = apic_read(APIC_LVT1); 2308 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2309 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2310 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2311 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2312 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 2313 apic_write(APIC_LVT1, value); 2314 } 2315 2316 /* 2317 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated 2318 * contiguously, it equals to current allocated max logical CPU ID plus 1. 2319 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range, 2320 * so the maximum of nr_logical_cpuids is nr_cpu_ids. 2321 * 2322 * NOTE: Reserve 0 for BSP. 2323 */ 2324 static int nr_logical_cpuids = 1; 2325 2326 /* 2327 * Used to store mapping between logical CPU IDs and APIC IDs. 2328 */ 2329 static int cpuid_to_apicid[] = { 2330 [0 ... NR_CPUS - 1] = -1, 2331 }; 2332 2333 #ifdef CONFIG_SMP 2334 /** 2335 * apic_id_is_primary_thread - Check whether APIC ID belongs to a primary thread 2336 * @apicid: APIC ID to check 2337 */ 2338 bool apic_id_is_primary_thread(unsigned int apicid) 2339 { 2340 u32 mask; 2341 2342 if (smp_num_siblings == 1) 2343 return true; 2344 /* Isolate the SMT bit(s) in the APICID and check for 0 */ 2345 mask = (1U << (fls(smp_num_siblings) - 1)) - 1; 2346 return !(apicid & mask); 2347 } 2348 #endif 2349 2350 /* 2351 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids 2352 * and cpuid_to_apicid[] synchronized. 2353 */ 2354 static int allocate_logical_cpuid(int apicid) 2355 { 2356 int i; 2357 2358 /* 2359 * cpuid <-> apicid mapping is persistent, so when a cpu is up, 2360 * check if the kernel has allocated a cpuid for it. 2361 */ 2362 for (i = 0; i < nr_logical_cpuids; i++) { 2363 if (cpuid_to_apicid[i] == apicid) 2364 return i; 2365 } 2366 2367 /* Allocate a new cpuid. */ 2368 if (nr_logical_cpuids >= nr_cpu_ids) { 2369 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. " 2370 "Processor %d/0x%x and the rest are ignored.\n", 2371 nr_cpu_ids, nr_logical_cpuids, apicid); 2372 return -EINVAL; 2373 } 2374 2375 cpuid_to_apicid[nr_logical_cpuids] = apicid; 2376 return nr_logical_cpuids++; 2377 } 2378 2379 int generic_processor_info(int apicid, int version) 2380 { 2381 int cpu, max = nr_cpu_ids; 2382 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, 2383 phys_cpu_present_map); 2384 2385 /* 2386 * boot_cpu_physical_apicid is designed to have the apicid 2387 * returned by read_apic_id(), i.e, the apicid of the 2388 * currently booting-up processor. However, on some platforms, 2389 * it is temporarily modified by the apicid reported as BSP 2390 * through MP table. Concretely: 2391 * 2392 * - arch/x86/kernel/mpparse.c: MP_processor_info() 2393 * - arch/x86/mm/amdtopology.c: amd_numa_init() 2394 * 2395 * This function is executed with the modified 2396 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel 2397 * parameter doesn't work to disable APs on kdump 2nd kernel. 2398 * 2399 * Since fixing handling of boot_cpu_physical_apicid requires 2400 * another discussion and tests on each platform, we leave it 2401 * for now and here we use read_apic_id() directly in this 2402 * function, generic_processor_info(). 2403 */ 2404 if (disabled_cpu_apicid != BAD_APICID && 2405 disabled_cpu_apicid != read_apic_id() && 2406 disabled_cpu_apicid == apicid) { 2407 int thiscpu = num_processors + disabled_cpus; 2408 2409 pr_warn("APIC: Disabling requested cpu." 2410 " Processor %d/0x%x ignored.\n", thiscpu, apicid); 2411 2412 disabled_cpus++; 2413 return -ENODEV; 2414 } 2415 2416 /* 2417 * If boot cpu has not been detected yet, then only allow upto 2418 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu 2419 */ 2420 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && 2421 apicid != boot_cpu_physical_apicid) { 2422 int thiscpu = max + disabled_cpus - 1; 2423 2424 pr_warn("APIC: NR_CPUS/possible_cpus limit of %i almost" 2425 " reached. Keeping one slot for boot cpu." 2426 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2427 2428 disabled_cpus++; 2429 return -ENODEV; 2430 } 2431 2432 if (num_processors >= nr_cpu_ids) { 2433 int thiscpu = max + disabled_cpus; 2434 2435 pr_warn("APIC: NR_CPUS/possible_cpus limit of %i reached. " 2436 "Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2437 2438 disabled_cpus++; 2439 return -EINVAL; 2440 } 2441 2442 if (apicid == boot_cpu_physical_apicid) { 2443 /* 2444 * x86_bios_cpu_apicid is required to have processors listed 2445 * in same order as logical cpu numbers. Hence the first 2446 * entry is BSP, and so on. 2447 * boot_cpu_init() already hold bit 0 in cpu_present_mask 2448 * for BSP. 2449 */ 2450 cpu = 0; 2451 2452 /* Logical cpuid 0 is reserved for BSP. */ 2453 cpuid_to_apicid[0] = apicid; 2454 } else { 2455 cpu = allocate_logical_cpuid(apicid); 2456 if (cpu < 0) { 2457 disabled_cpus++; 2458 return -EINVAL; 2459 } 2460 } 2461 2462 /* 2463 * Validate version 2464 */ 2465 if (version == 0x0) { 2466 pr_warn("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", 2467 cpu, apicid); 2468 version = 0x10; 2469 } 2470 2471 if (version != boot_cpu_apic_version) { 2472 pr_warn("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", 2473 boot_cpu_apic_version, cpu, version); 2474 } 2475 2476 if (apicid > max_physical_apicid) 2477 max_physical_apicid = apicid; 2478 2479 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 2480 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 2481 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 2482 #endif 2483 #ifdef CONFIG_X86_32 2484 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 2485 apic->x86_32_early_logical_apicid(cpu); 2486 #endif 2487 set_cpu_possible(cpu, true); 2488 physid_set(apicid, phys_cpu_present_map); 2489 set_cpu_present(cpu, true); 2490 num_processors++; 2491 2492 return cpu; 2493 } 2494 2495 int hard_smp_processor_id(void) 2496 { 2497 return read_apic_id(); 2498 } 2499 2500 void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg, 2501 bool dmar) 2502 { 2503 memset(msg, 0, sizeof(*msg)); 2504 2505 msg->arch_addr_lo.base_address = X86_MSI_BASE_ADDRESS_LOW; 2506 msg->arch_addr_lo.dest_mode_logical = apic->dest_mode_logical; 2507 msg->arch_addr_lo.destid_0_7 = cfg->dest_apicid & 0xFF; 2508 2509 msg->arch_data.delivery_mode = APIC_DELIVERY_MODE_FIXED; 2510 msg->arch_data.vector = cfg->vector; 2511 2512 msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH; 2513 /* 2514 * Only the IOMMU itself can use the trick of putting destination 2515 * APIC ID into the high bits of the address. Anything else would 2516 * just be writing to memory if it tried that, and needs IR to 2517 * address APICs which can't be addressed in the normal 32-bit 2518 * address range at 0xFFExxxxx. That is typically just 8 bits, but 2519 * some hypervisors allow the extended destination ID field in bits 2520 * 5-11 to be used, giving support for 15 bits of APIC IDs in total. 2521 */ 2522 if (dmar) 2523 msg->arch_addr_hi.destid_8_31 = cfg->dest_apicid >> 8; 2524 else if (virt_ext_dest_id && cfg->dest_apicid < 0x8000) 2525 msg->arch_addr_lo.virt_destid_8_14 = cfg->dest_apicid >> 8; 2526 else 2527 WARN_ON_ONCE(cfg->dest_apicid > 0xFF); 2528 } 2529 2530 u32 x86_msi_msg_get_destid(struct msi_msg *msg, bool extid) 2531 { 2532 u32 dest = msg->arch_addr_lo.destid_0_7; 2533 2534 if (extid) 2535 dest |= msg->arch_addr_hi.destid_8_31 << 8; 2536 return dest; 2537 } 2538 EXPORT_SYMBOL_GPL(x86_msi_msg_get_destid); 2539 2540 /* 2541 * Override the generic EOI implementation with an optimized version. 2542 * Only called during early boot when only one CPU is active and with 2543 * interrupts disabled, so we know this does not race with actual APIC driver 2544 * use. 2545 */ 2546 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) 2547 { 2548 struct apic **drv; 2549 2550 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { 2551 /* Should happen once for each apic */ 2552 WARN_ON((*drv)->eoi_write == eoi_write); 2553 (*drv)->native_eoi_write = (*drv)->eoi_write; 2554 (*drv)->eoi_write = eoi_write; 2555 } 2556 } 2557 2558 static void __init apic_bsp_up_setup(void) 2559 { 2560 #ifdef CONFIG_X86_64 2561 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid)); 2562 #else 2563 /* 2564 * Hack: In case of kdump, after a crash, kernel might be booting 2565 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 2566 * might be zero if read from MP tables. Get it from LAPIC. 2567 */ 2568 # ifdef CONFIG_CRASH_DUMP 2569 boot_cpu_physical_apicid = read_apic_id(); 2570 # endif 2571 #endif 2572 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 2573 } 2574 2575 /** 2576 * apic_bsp_setup - Setup function for local apic and io-apic 2577 * @upmode: Force UP mode (for APIC_init_uniprocessor) 2578 */ 2579 static void __init apic_bsp_setup(bool upmode) 2580 { 2581 connect_bsp_APIC(); 2582 if (upmode) 2583 apic_bsp_up_setup(); 2584 setup_local_APIC(); 2585 2586 enable_IO_APIC(); 2587 end_local_APIC_setup(); 2588 irq_remap_enable_fault_handling(); 2589 setup_IO_APIC(); 2590 } 2591 2592 #ifdef CONFIG_UP_LATE_INIT 2593 void __init up_late_init(void) 2594 { 2595 if (apic_intr_mode == APIC_PIC) 2596 return; 2597 2598 /* Setup local timer */ 2599 x86_init.timers.setup_percpu_clockev(); 2600 } 2601 #endif 2602 2603 /* 2604 * Power management 2605 */ 2606 #ifdef CONFIG_PM 2607 2608 static struct { 2609 /* 2610 * 'active' is true if the local APIC was enabled by us and 2611 * not the BIOS; this signifies that we are also responsible 2612 * for disabling it before entering apm/acpi suspend 2613 */ 2614 int active; 2615 /* r/w apic fields */ 2616 unsigned int apic_id; 2617 unsigned int apic_taskpri; 2618 unsigned int apic_ldr; 2619 unsigned int apic_dfr; 2620 unsigned int apic_spiv; 2621 unsigned int apic_lvtt; 2622 unsigned int apic_lvtpc; 2623 unsigned int apic_lvt0; 2624 unsigned int apic_lvt1; 2625 unsigned int apic_lvterr; 2626 unsigned int apic_tmict; 2627 unsigned int apic_tdcr; 2628 unsigned int apic_thmr; 2629 unsigned int apic_cmci; 2630 } apic_pm_state; 2631 2632 static int lapic_suspend(void) 2633 { 2634 unsigned long flags; 2635 int maxlvt; 2636 2637 if (!apic_pm_state.active) 2638 return 0; 2639 2640 maxlvt = lapic_get_maxlvt(); 2641 2642 apic_pm_state.apic_id = apic_read(APIC_ID); 2643 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2644 apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2645 apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2646 apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2647 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2648 if (maxlvt >= 4) 2649 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2650 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2651 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2652 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2653 apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2654 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 2655 #ifdef CONFIG_X86_THERMAL_VECTOR 2656 if (maxlvt >= 5) 2657 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2658 #endif 2659 #ifdef CONFIG_X86_MCE_INTEL 2660 if (maxlvt >= 6) 2661 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI); 2662 #endif 2663 2664 local_irq_save(flags); 2665 2666 /* 2667 * Mask IOAPIC before disabling the local APIC to prevent stale IRR 2668 * entries on some implementations. 2669 */ 2670 mask_ioapic_entries(); 2671 2672 disable_local_APIC(); 2673 2674 irq_remapping_disable(); 2675 2676 local_irq_restore(flags); 2677 return 0; 2678 } 2679 2680 static void lapic_resume(void) 2681 { 2682 unsigned int l, h; 2683 unsigned long flags; 2684 int maxlvt; 2685 2686 if (!apic_pm_state.active) 2687 return; 2688 2689 local_irq_save(flags); 2690 2691 /* 2692 * IO-APIC and PIC have their own resume routines. 2693 * We just mask them here to make sure the interrupt 2694 * subsystem is completely quiet while we enable x2apic 2695 * and interrupt-remapping. 2696 */ 2697 mask_ioapic_entries(); 2698 legacy_pic->mask_all(); 2699 2700 if (x2apic_mode) { 2701 __x2apic_enable(); 2702 } else { 2703 /* 2704 * Make sure the APICBASE points to the right address 2705 * 2706 * FIXME! This will be wrong if we ever support suspend on 2707 * SMP! We'll need to do this as part of the CPU restore! 2708 */ 2709 if (boot_cpu_data.x86 >= 6) { 2710 rdmsr(MSR_IA32_APICBASE, l, h); 2711 l &= ~MSR_IA32_APICBASE_BASE; 2712 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2713 wrmsr(MSR_IA32_APICBASE, l, h); 2714 } 2715 } 2716 2717 maxlvt = lapic_get_maxlvt(); 2718 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2719 apic_write(APIC_ID, apic_pm_state.apic_id); 2720 apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2721 apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2722 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2723 apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2724 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2725 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2726 #ifdef CONFIG_X86_THERMAL_VECTOR 2727 if (maxlvt >= 5) 2728 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2729 #endif 2730 #ifdef CONFIG_X86_MCE_INTEL 2731 if (maxlvt >= 6) 2732 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci); 2733 #endif 2734 if (maxlvt >= 4) 2735 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2736 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2737 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2738 apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2739 apic_write(APIC_ESR, 0); 2740 apic_read(APIC_ESR); 2741 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2742 apic_write(APIC_ESR, 0); 2743 apic_read(APIC_ESR); 2744 2745 irq_remapping_reenable(x2apic_mode); 2746 2747 local_irq_restore(flags); 2748 } 2749 2750 /* 2751 * This device has no shutdown method - fully functioning local APICs 2752 * are needed on every CPU up until machine_halt/restart/poweroff. 2753 */ 2754 2755 static struct syscore_ops lapic_syscore_ops = { 2756 .resume = lapic_resume, 2757 .suspend = lapic_suspend, 2758 }; 2759 2760 static void apic_pm_activate(void) 2761 { 2762 apic_pm_state.active = 1; 2763 } 2764 2765 static int __init init_lapic_sysfs(void) 2766 { 2767 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2768 if (boot_cpu_has(X86_FEATURE_APIC)) 2769 register_syscore_ops(&lapic_syscore_ops); 2770 2771 return 0; 2772 } 2773 2774 /* local apic needs to resume before other devices access its registers. */ 2775 core_initcall(init_lapic_sysfs); 2776 2777 #else /* CONFIG_PM */ 2778 2779 static void apic_pm_activate(void) { } 2780 2781 #endif /* CONFIG_PM */ 2782 2783 #ifdef CONFIG_X86_64 2784 2785 static int multi_checked; 2786 static int multi; 2787 2788 static int set_multi(const struct dmi_system_id *d) 2789 { 2790 if (multi) 2791 return 0; 2792 pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2793 multi = 1; 2794 return 0; 2795 } 2796 2797 static const struct dmi_system_id multi_dmi_table[] = { 2798 { 2799 .callback = set_multi, 2800 .ident = "IBM System Summit2", 2801 .matches = { 2802 DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2803 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2804 }, 2805 }, 2806 {} 2807 }; 2808 2809 static void dmi_check_multi(void) 2810 { 2811 if (multi_checked) 2812 return; 2813 2814 dmi_check_system(multi_dmi_table); 2815 multi_checked = 1; 2816 } 2817 2818 /* 2819 * apic_is_clustered_box() -- Check if we can expect good TSC 2820 * 2821 * Thus far, the major user of this is IBM's Summit2 series: 2822 * Clustered boxes may have unsynced TSC problems if they are 2823 * multi-chassis. 2824 * Use DMI to check them 2825 */ 2826 int apic_is_clustered_box(void) 2827 { 2828 dmi_check_multi(); 2829 return multi; 2830 } 2831 #endif 2832 2833 /* 2834 * APIC command line parameters 2835 */ 2836 static int __init setup_disableapic(char *arg) 2837 { 2838 disable_apic = 1; 2839 setup_clear_cpu_cap(X86_FEATURE_APIC); 2840 return 0; 2841 } 2842 early_param("disableapic", setup_disableapic); 2843 2844 /* same as disableapic, for compatibility */ 2845 static int __init setup_nolapic(char *arg) 2846 { 2847 return setup_disableapic(arg); 2848 } 2849 early_param("nolapic", setup_nolapic); 2850 2851 static int __init parse_lapic_timer_c2_ok(char *arg) 2852 { 2853 local_apic_timer_c2_ok = 1; 2854 return 0; 2855 } 2856 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2857 2858 static int __init parse_disable_apic_timer(char *arg) 2859 { 2860 disable_apic_timer = 1; 2861 return 0; 2862 } 2863 early_param("noapictimer", parse_disable_apic_timer); 2864 2865 static int __init parse_nolapic_timer(char *arg) 2866 { 2867 disable_apic_timer = 1; 2868 return 0; 2869 } 2870 early_param("nolapic_timer", parse_nolapic_timer); 2871 2872 static int __init apic_set_verbosity(char *arg) 2873 { 2874 if (!arg) { 2875 #ifdef CONFIG_X86_64 2876 skip_ioapic_setup = 0; 2877 return 0; 2878 #endif 2879 return -EINVAL; 2880 } 2881 2882 if (strcmp("debug", arg) == 0) 2883 apic_verbosity = APIC_DEBUG; 2884 else if (strcmp("verbose", arg) == 0) 2885 apic_verbosity = APIC_VERBOSE; 2886 #ifdef CONFIG_X86_64 2887 else { 2888 pr_warn("APIC Verbosity level %s not recognised" 2889 " use apic=verbose or apic=debug\n", arg); 2890 return -EINVAL; 2891 } 2892 #endif 2893 2894 return 0; 2895 } 2896 early_param("apic", apic_set_verbosity); 2897 2898 static int __init lapic_insert_resource(void) 2899 { 2900 if (!apic_phys) 2901 return -1; 2902 2903 /* Put local APIC into the resource map. */ 2904 lapic_resource.start = apic_phys; 2905 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2906 insert_resource(&iomem_resource, &lapic_resource); 2907 2908 return 0; 2909 } 2910 2911 /* 2912 * need call insert after e820__reserve_resources() 2913 * that is using request_resource 2914 */ 2915 late_initcall(lapic_insert_resource); 2916 2917 static int __init apic_set_disabled_cpu_apicid(char *arg) 2918 { 2919 if (!arg || !get_option(&arg, &disabled_cpu_apicid)) 2920 return -EINVAL; 2921 2922 return 0; 2923 } 2924 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); 2925 2926 static int __init apic_set_extnmi(char *arg) 2927 { 2928 if (!arg) 2929 return -EINVAL; 2930 2931 if (!strncmp("all", arg, 3)) 2932 apic_extnmi = APIC_EXTNMI_ALL; 2933 else if (!strncmp("none", arg, 4)) 2934 apic_extnmi = APIC_EXTNMI_NONE; 2935 else if (!strncmp("bsp", arg, 3)) 2936 apic_extnmi = APIC_EXTNMI_BSP; 2937 else { 2938 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg); 2939 return -EINVAL; 2940 } 2941 2942 return 0; 2943 } 2944 early_param("apic_extnmi", apic_set_extnmi); 2945