1457c8996SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2f62bae50SIngo Molnar /* 3f62bae50SIngo Molnar * Local APIC handling, local APIC timers 4f62bae50SIngo Molnar * 5f62bae50SIngo Molnar * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6f62bae50SIngo Molnar * 7f62bae50SIngo Molnar * Fixes 8f62bae50SIngo Molnar * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 9f62bae50SIngo Molnar * thanks to Eric Gilmore 10f62bae50SIngo Molnar * and Rolf G. Tews 11f62bae50SIngo Molnar * for testing these extensively. 12f62bae50SIngo Molnar * Maciej W. Rozycki : Various updates and fixes. 13f62bae50SIngo Molnar * Mikael Pettersson : Power Management for UP-APIC. 14f62bae50SIngo Molnar * Pavel Machek and 15f62bae50SIngo Molnar * Mikael Pettersson : PM converted to driver model. 16f62bae50SIngo Molnar */ 17f62bae50SIngo Molnar 18cdd6c482SIngo Molnar #include <linux/perf_event.h> 19f62bae50SIngo Molnar #include <linux/kernel_stat.h> 20f62bae50SIngo Molnar #include <linux/mc146818rtc.h> 21f62bae50SIngo Molnar #include <linux/acpi_pmtmr.h> 22f62bae50SIngo Molnar #include <linux/clockchips.h> 23f62bae50SIngo Molnar #include <linux/interrupt.h> 2457c8a661SMike Rapoport #include <linux/memblock.h> 25f62bae50SIngo Molnar #include <linux/ftrace.h> 26f62bae50SIngo Molnar #include <linux/ioport.h> 27186f4360SPaul Gortmaker #include <linux/export.h> 28f3c6ea1bSRafael J. Wysocki #include <linux/syscore_ops.h> 29f62bae50SIngo Molnar #include <linux/delay.h> 30f62bae50SIngo Molnar #include <linux/timex.h> 31334955efSRalf Baechle #include <linux/i8253.h> 32f62bae50SIngo Molnar #include <linux/dmar.h> 33f62bae50SIngo Molnar #include <linux/init.h> 34f62bae50SIngo Molnar #include <linux/cpu.h> 35f62bae50SIngo Molnar #include <linux/dmi.h> 36f62bae50SIngo Molnar #include <linux/smp.h> 37f62bae50SIngo Molnar #include <linux/mm.h> 38f62bae50SIngo Molnar 3983ab8514SSteven Rostedt (Red Hat) #include <asm/trace/irq_vectors.h> 408a8f422dSSuresh Siddha #include <asm/irq_remapping.h> 41cdd6c482SIngo Molnar #include <asm/perf_event.h> 42736decacSThomas Gleixner #include <asm/x86_init.h> 43f62bae50SIngo Molnar #include <asm/pgalloc.h> 4460063497SArun Sharma #include <linux/atomic.h> 45f62bae50SIngo Molnar #include <asm/mpspec.h> 46f62bae50SIngo Molnar #include <asm/i8259.h> 47f62bae50SIngo Molnar #include <asm/proto.h> 48ad3bc25aSBorislav Petkov #include <asm/traps.h> 49f62bae50SIngo Molnar #include <asm/apic.h> 507167d08eSHenrik Kretzschmar #include <asm/io_apic.h> 51f62bae50SIngo Molnar #include <asm/desc.h> 52f62bae50SIngo Molnar #include <asm/hpet.h> 53f62bae50SIngo Molnar #include <asm/mtrr.h> 5416f871bcSRalf Baechle #include <asm/time.h> 55f62bae50SIngo Molnar #include <asm/smp.h> 56638bee71SH. Peter Anvin #include <asm/mce.h> 578c3ba8d0SKerstin Jonsson #include <asm/tsc.h> 582904ed8dSSheng Yang #include <asm/hypervisor.h> 59bd9240a1SPeter Zijlstra #include <asm/cpu_device_id.h> 60bd9240a1SPeter Zijlstra #include <asm/intel-family.h> 61447ae316SNicolai Stange #include <asm/irq_regs.h> 62f62bae50SIngo Molnar 63f62bae50SIngo Molnar unsigned int num_processors; 64f62bae50SIngo Molnar 65148f9bb8SPaul Gortmaker unsigned disabled_cpus; 66f62bae50SIngo Molnar 67f62bae50SIngo Molnar /* Processor that is doing the boot up */ 68f62bae50SIngo Molnar unsigned int boot_cpu_physical_apicid = -1U; 69cc08e04cSDavid Rientjes EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); 70f62bae50SIngo Molnar 71cff9ab2bSDenys Vlasenko u8 boot_cpu_apic_version; 72cff9ab2bSDenys Vlasenko 73f62bae50SIngo Molnar /* 74f62bae50SIngo Molnar * The highest APIC ID seen during enumeration. 75f62bae50SIngo Molnar */ 76a491cc90SJiang Liu static unsigned int max_physical_apicid; 77f62bae50SIngo Molnar 78f62bae50SIngo Molnar /* 79f62bae50SIngo Molnar * Bitmask of physically existing CPUs: 80f62bae50SIngo Molnar */ 81f62bae50SIngo Molnar physid_mask_t phys_cpu_present_map; 82f62bae50SIngo Molnar 83f62bae50SIngo Molnar /* 84151e0c7dSHATAYAMA Daisuke * Processor to be disabled specified by kernel parameter 85151e0c7dSHATAYAMA Daisuke * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to 86151e0c7dSHATAYAMA Daisuke * avoid undefined behaviour caused by sending INIT from AP to BSP. 87151e0c7dSHATAYAMA Daisuke */ 885b4d1dbcSH. Peter Anvin static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID; 89151e0c7dSHATAYAMA Daisuke 90151e0c7dSHATAYAMA Daisuke /* 91b7c4948eSHidehiro Kawai * This variable controls which CPUs receive external NMIs. By default, 92b7c4948eSHidehiro Kawai * external NMIs are delivered only to the BSP. 93b7c4948eSHidehiro Kawai */ 94b7c4948eSHidehiro Kawai static int apic_extnmi = APIC_EXTNMI_BSP; 95b7c4948eSHidehiro Kawai 96b7c4948eSHidehiro Kawai /* 97f62bae50SIngo Molnar * Map cpu index to physical APIC ID 98f62bae50SIngo Molnar */ 990816b0f0SVlad Zolotarov DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); 1000816b0f0SVlad Zolotarov DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); 1013e9e57faSVitaly Kuznetsov DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX); 102f62bae50SIngo Molnar EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 103f62bae50SIngo Molnar EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 1043e9e57faSVitaly Kuznetsov EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); 105f62bae50SIngo Molnar 106f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1074c321ff8STejun Heo 1084c321ff8STejun Heo /* 1094c321ff8STejun Heo * On x86_32, the mapping between cpu and logical apicid may vary 1104c321ff8STejun Heo * depending on apic in use. The following early percpu variable is 1114c321ff8STejun Heo * used for the mapping. This is where the behaviors of x86_64 and 32 1124c321ff8STejun Heo * actually diverge. Let's keep it ugly for now. 1134c321ff8STejun Heo */ 1140816b0f0SVlad Zolotarov DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); 1154c321ff8STejun Heo 116f62bae50SIngo Molnar /* Local APIC was disabled by the BIOS and enabled by the kernel */ 117f62bae50SIngo Molnar static int enabled_via_apicbase; 118f62bae50SIngo Molnar 119c0eaa453SCyrill Gorcunov /* 120c0eaa453SCyrill Gorcunov * Handle interrupt mode configuration register (IMCR). 121c0eaa453SCyrill Gorcunov * This register controls whether the interrupt signals 122c0eaa453SCyrill Gorcunov * that reach the BSP come from the master PIC or from the 123c0eaa453SCyrill Gorcunov * local APIC. Before entering Symmetric I/O Mode, either 124c0eaa453SCyrill Gorcunov * the BIOS or the operating system must switch out of 125c0eaa453SCyrill Gorcunov * PIC Mode by changing the IMCR. 126c0eaa453SCyrill Gorcunov */ 1275cda395fSAlexander van Heukelum static inline void imcr_pic_to_apic(void) 128c0eaa453SCyrill Gorcunov { 129c0eaa453SCyrill Gorcunov /* select IMCR register */ 130c0eaa453SCyrill Gorcunov outb(0x70, 0x22); 131c0eaa453SCyrill Gorcunov /* NMI and 8259 INTR go through APIC */ 132c0eaa453SCyrill Gorcunov outb(0x01, 0x23); 133c0eaa453SCyrill Gorcunov } 134c0eaa453SCyrill Gorcunov 1355cda395fSAlexander van Heukelum static inline void imcr_apic_to_pic(void) 136c0eaa453SCyrill Gorcunov { 137c0eaa453SCyrill Gorcunov /* select IMCR register */ 138c0eaa453SCyrill Gorcunov outb(0x70, 0x22); 139c0eaa453SCyrill Gorcunov /* NMI and 8259 INTR go directly to BSP */ 140c0eaa453SCyrill Gorcunov outb(0x00, 0x23); 141c0eaa453SCyrill Gorcunov } 142f62bae50SIngo Molnar #endif 143f62bae50SIngo Molnar 144279f1461SSuresh Siddha /* 145279f1461SSuresh Siddha * Knob to control our willingness to enable the local APIC. 146279f1461SSuresh Siddha * 147279f1461SSuresh Siddha * +1=force-enable 148279f1461SSuresh Siddha */ 149279f1461SSuresh Siddha static int force_enable_local_apic __initdata; 150dc9788f4SDavid Rientjes 151279f1461SSuresh Siddha /* 152279f1461SSuresh Siddha * APIC command line parameters 153279f1461SSuresh Siddha */ 154279f1461SSuresh Siddha static int __init parse_lapic(char *arg) 155279f1461SSuresh Siddha { 15697f2645fSMasahiro Yamada if (IS_ENABLED(CONFIG_X86_32) && !arg) 157279f1461SSuresh Siddha force_enable_local_apic = 1; 15827cf9298SMathias Krause else if (arg && !strncmp(arg, "notscdeadline", 13)) 159279f1461SSuresh Siddha setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 160279f1461SSuresh Siddha return 0; 161279f1461SSuresh Siddha } 162279f1461SSuresh Siddha early_param("lapic", parse_lapic); 163279f1461SSuresh Siddha 164f62bae50SIngo Molnar #ifdef CONFIG_X86_64 165f62bae50SIngo Molnar static int apic_calibrate_pmtmr __initdata; 166f62bae50SIngo Molnar static __init int setup_apicpmtimer(char *s) 167f62bae50SIngo Molnar { 168f62bae50SIngo Molnar apic_calibrate_pmtmr = 1; 169f62bae50SIngo Molnar notsc_setup(NULL); 170f62bae50SIngo Molnar return 0; 171f62bae50SIngo Molnar } 172f62bae50SIngo Molnar __setup("apicpmtimer", setup_apicpmtimer); 173f62bae50SIngo Molnar #endif 174f62bae50SIngo Molnar 175f62bae50SIngo Molnar unsigned long mp_lapic_addr; 176f62bae50SIngo Molnar int disable_apic; 177f62bae50SIngo Molnar /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 17825874a29SHenrik Kretzschmar static int disable_apic_timer __initdata; 179f62bae50SIngo Molnar /* Local APIC timer works in C2 */ 180f62bae50SIngo Molnar int local_apic_timer_c2_ok; 181f62bae50SIngo Molnar EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 182f62bae50SIngo Molnar 183f62bae50SIngo Molnar /* 184f62bae50SIngo Molnar * Debug level, exported for io_apic.c 185f62bae50SIngo Molnar */ 186ec633558SQian Cai int apic_verbosity; 187f62bae50SIngo Molnar 188f62bae50SIngo Molnar int pic_mode; 189f62bae50SIngo Molnar 190f62bae50SIngo Molnar /* Have we found an MP table */ 191f62bae50SIngo Molnar int smp_found_config; 192f62bae50SIngo Molnar 193f62bae50SIngo Molnar static struct resource lapic_resource = { 194f62bae50SIngo Molnar .name = "Local APIC", 195f62bae50SIngo Molnar .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 196f62bae50SIngo Molnar }; 197f62bae50SIngo Molnar 19852ae346bSDaniel Drake unsigned int lapic_timer_period = 0; 199f62bae50SIngo Molnar 200f62bae50SIngo Molnar static void apic_pm_activate(void); 201f62bae50SIngo Molnar 202f62bae50SIngo Molnar static unsigned long apic_phys; 203f62bae50SIngo Molnar 204f62bae50SIngo Molnar /* 205f62bae50SIngo Molnar * Get the LAPIC version 206f62bae50SIngo Molnar */ 207f62bae50SIngo Molnar static inline int lapic_get_version(void) 208f62bae50SIngo Molnar { 209f62bae50SIngo Molnar return GET_APIC_VERSION(apic_read(APIC_LVR)); 210f62bae50SIngo Molnar } 211f62bae50SIngo Molnar 212f62bae50SIngo Molnar /* 213f62bae50SIngo Molnar * Check, if the APIC is integrated or a separate chip 214f62bae50SIngo Molnar */ 215f62bae50SIngo Molnar static inline int lapic_is_integrated(void) 216f62bae50SIngo Molnar { 217f62bae50SIngo Molnar return APIC_INTEGRATED(lapic_get_version()); 218f62bae50SIngo Molnar } 219f62bae50SIngo Molnar 220f62bae50SIngo Molnar /* 221f62bae50SIngo Molnar * Check, whether this is a modern or a first generation APIC 222f62bae50SIngo Molnar */ 223f62bae50SIngo Molnar static int modern_apic(void) 224f62bae50SIngo Molnar { 225f62bae50SIngo Molnar /* AMD systems use old APIC versions, so check the CPU */ 226f62bae50SIngo Molnar if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 227f62bae50SIngo Molnar boot_cpu_data.x86 >= 0xf) 228f62bae50SIngo Molnar return 1; 229da33dfefSPu Wen 230da33dfefSPu Wen /* Hygon systems use modern APIC */ 231da33dfefSPu Wen if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 232da33dfefSPu Wen return 1; 233da33dfefSPu Wen 234f62bae50SIngo Molnar return lapic_get_version() >= 0x14; 235f62bae50SIngo Molnar } 236f62bae50SIngo Molnar 23708306ce6SCyrill Gorcunov /* 238a933c618SCyrill Gorcunov * right after this call apic become NOOP driven 239a933c618SCyrill Gorcunov * so apic->write/read doesn't do anything 24008306ce6SCyrill Gorcunov */ 24125874a29SHenrik Kretzschmar static void __init apic_disable(void) 24208306ce6SCyrill Gorcunov { 243f88f2b4fSCyrill Gorcunov pr_info("APIC: switched to apic NOOP\n"); 244a933c618SCyrill Gorcunov apic = &apic_noop; 24508306ce6SCyrill Gorcunov } 24608306ce6SCyrill Gorcunov 247f62bae50SIngo Molnar void native_apic_wait_icr_idle(void) 248f62bae50SIngo Molnar { 249f62bae50SIngo Molnar while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 250f62bae50SIngo Molnar cpu_relax(); 251f62bae50SIngo Molnar } 252f62bae50SIngo Molnar 253f62bae50SIngo Molnar u32 native_safe_apic_wait_icr_idle(void) 254f62bae50SIngo Molnar { 255f62bae50SIngo Molnar u32 send_status; 256f62bae50SIngo Molnar int timeout; 257f62bae50SIngo Molnar 258f62bae50SIngo Molnar timeout = 0; 259f62bae50SIngo Molnar do { 260f62bae50SIngo Molnar send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 261f62bae50SIngo Molnar if (!send_status) 262f62bae50SIngo Molnar break; 263b49d7d87SFernando Luis Vazquez Cao inc_irq_stat(icr_read_retry_count); 264f62bae50SIngo Molnar udelay(100); 265f62bae50SIngo Molnar } while (timeout++ < 1000); 266f62bae50SIngo Molnar 267f62bae50SIngo Molnar return send_status; 268f62bae50SIngo Molnar } 269f62bae50SIngo Molnar 270f62bae50SIngo Molnar void native_apic_icr_write(u32 low, u32 id) 271f62bae50SIngo Molnar { 272ea7bdc65SJan Kiszka unsigned long flags; 273ea7bdc65SJan Kiszka 274ea7bdc65SJan Kiszka local_irq_save(flags); 275f62bae50SIngo Molnar apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 276f62bae50SIngo Molnar apic_write(APIC_ICR, low); 277ea7bdc65SJan Kiszka local_irq_restore(flags); 278f62bae50SIngo Molnar } 279f62bae50SIngo Molnar 280f62bae50SIngo Molnar u64 native_apic_icr_read(void) 281f62bae50SIngo Molnar { 282f62bae50SIngo Molnar u32 icr1, icr2; 283f62bae50SIngo Molnar 284f62bae50SIngo Molnar icr2 = apic_read(APIC_ICR2); 285f62bae50SIngo Molnar icr1 = apic_read(APIC_ICR); 286f62bae50SIngo Molnar 287f62bae50SIngo Molnar return icr1 | ((u64)icr2 << 32); 288f62bae50SIngo Molnar } 289f62bae50SIngo Molnar 290f62bae50SIngo Molnar #ifdef CONFIG_X86_32 291f62bae50SIngo Molnar /** 292f62bae50SIngo Molnar * get_physical_broadcast - Get number of physical broadcast IDs 293f62bae50SIngo Molnar */ 294f62bae50SIngo Molnar int get_physical_broadcast(void) 295f62bae50SIngo Molnar { 296f62bae50SIngo Molnar return modern_apic() ? 0xff : 0xf; 297f62bae50SIngo Molnar } 298f62bae50SIngo Molnar #endif 299f62bae50SIngo Molnar 300f62bae50SIngo Molnar /** 301f62bae50SIngo Molnar * lapic_get_maxlvt - get the maximum number of local vector table entries 302f62bae50SIngo Molnar */ 303f62bae50SIngo Molnar int lapic_get_maxlvt(void) 304f62bae50SIngo Molnar { 305f62bae50SIngo Molnar /* 306f62bae50SIngo Molnar * - we always have APIC integrated on 64bit mode 307f62bae50SIngo Molnar * - 82489DXs do not report # of LVT entries 308f62bae50SIngo Molnar */ 309ae41a2a4SDou Liyang return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2; 310f62bae50SIngo Molnar } 311f62bae50SIngo Molnar 312f62bae50SIngo Molnar /* 313f62bae50SIngo Molnar * Local APIC timer 314f62bae50SIngo Molnar */ 315f62bae50SIngo Molnar 316f62bae50SIngo Molnar /* Clock divisor */ 317f62bae50SIngo Molnar #define APIC_DIVISOR 16 3181a9e4c56SNicolai Stange #define TSC_DIVISOR 8 319f62bae50SIngo Molnar 320f62bae50SIngo Molnar /* 321f62bae50SIngo Molnar * This function sets up the local APIC timer, with a timeout of 322f62bae50SIngo Molnar * 'clocks' APIC bus clock. During calibration we actually call 323f62bae50SIngo Molnar * this function twice on the boot CPU, once with a bogus timeout 324f62bae50SIngo Molnar * value, second time for real. The other (noncalibrating) CPUs 325f62bae50SIngo Molnar * call this function only once, with the real, calibrated value. 326f62bae50SIngo Molnar * 327f62bae50SIngo Molnar * We do reads before writes even if unnecessary, to get around the 328f62bae50SIngo Molnar * P5 APIC double write bug. 329f62bae50SIngo Molnar */ 330f62bae50SIngo Molnar static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 331f62bae50SIngo Molnar { 332f62bae50SIngo Molnar unsigned int lvtt_value, tmp_value; 333f62bae50SIngo Molnar 334f62bae50SIngo Molnar lvtt_value = LOCAL_TIMER_VECTOR; 335f62bae50SIngo Molnar if (!oneshot) 336f62bae50SIngo Molnar lvtt_value |= APIC_LVT_TIMER_PERIODIC; 337279f1461SSuresh Siddha else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 338279f1461SSuresh Siddha lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; 339279f1461SSuresh Siddha 340f62bae50SIngo Molnar if (!lapic_is_integrated()) 341f62bae50SIngo Molnar lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 342f62bae50SIngo Molnar 343f62bae50SIngo Molnar if (!irqen) 344f62bae50SIngo Molnar lvtt_value |= APIC_LVT_MASKED; 345f62bae50SIngo Molnar 346f62bae50SIngo Molnar apic_write(APIC_LVTT, lvtt_value); 347f62bae50SIngo Molnar 348279f1461SSuresh Siddha if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { 3495d7c631dSShaohua Li /* 3505d7c631dSShaohua Li * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, 3515d7c631dSShaohua Li * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. 3525d7c631dSShaohua Li * According to Intel, MFENCE can do the serialization here. 3535d7c631dSShaohua Li */ 3545d7c631dSShaohua Li asm volatile("mfence" : : : "memory"); 3555d7c631dSShaohua Li 356279f1461SSuresh Siddha printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); 357279f1461SSuresh Siddha return; 358279f1461SSuresh Siddha } 359279f1461SSuresh Siddha 360f62bae50SIngo Molnar /* 361f62bae50SIngo Molnar * Divide PICLK by 16 362f62bae50SIngo Molnar */ 363f62bae50SIngo Molnar tmp_value = apic_read(APIC_TDCR); 364f62bae50SIngo Molnar apic_write(APIC_TDCR, 365f62bae50SIngo Molnar (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 366f62bae50SIngo Molnar APIC_TDR_DIV_16); 367f62bae50SIngo Molnar 368f62bae50SIngo Molnar if (!oneshot) 369f62bae50SIngo Molnar apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 370f62bae50SIngo Molnar } 371f62bae50SIngo Molnar 372f62bae50SIngo Molnar /* 373a68c439bSRobert Richter * Setup extended LVT, AMD specific 374f62bae50SIngo Molnar * 375a68c439bSRobert Richter * Software should use the LVT offsets the BIOS provides. The offsets 376a68c439bSRobert Richter * are determined by the subsystems using it like those for MCE 377a68c439bSRobert Richter * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 378a68c439bSRobert Richter * are supported. Beginning with family 10h at least 4 offsets are 379a68c439bSRobert Richter * available. 380f62bae50SIngo Molnar * 381a68c439bSRobert Richter * Since the offsets must be consistent for all cores, we keep track 382a68c439bSRobert Richter * of the LVT offsets in software and reserve the offset for the same 383a68c439bSRobert Richter * vector also to be used on other cores. An offset is freed by 384a68c439bSRobert Richter * setting the entry to APIC_EILVT_MASKED. 385a68c439bSRobert Richter * 386a68c439bSRobert Richter * If the BIOS is right, there should be no conflicts. Otherwise a 387a68c439bSRobert Richter * "[Firmware Bug]: ..." error message is generated. However, if 388a68c439bSRobert Richter * software does not properly determines the offsets, it is not 389a68c439bSRobert Richter * necessarily a BIOS bug. 390f62bae50SIngo Molnar */ 391f62bae50SIngo Molnar 392a68c439bSRobert Richter static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 393f62bae50SIngo Molnar 394a68c439bSRobert Richter static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 395a68c439bSRobert Richter { 396a68c439bSRobert Richter return (old & APIC_EILVT_MASKED) 397a68c439bSRobert Richter || (new == APIC_EILVT_MASKED) 398a68c439bSRobert Richter || ((new & ~APIC_EILVT_MASKED) == old); 399a68c439bSRobert Richter } 400a68c439bSRobert Richter 401a68c439bSRobert Richter static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 402a68c439bSRobert Richter { 4038abc3122SRobert Richter unsigned int rsvd, vector; 404a68c439bSRobert Richter 405a68c439bSRobert Richter if (offset >= APIC_EILVT_NR_MAX) 406a68c439bSRobert Richter return ~0; 407a68c439bSRobert Richter 4088abc3122SRobert Richter rsvd = atomic_read(&eilvt_offsets[offset]); 409a68c439bSRobert Richter do { 4108abc3122SRobert Richter vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ 4118abc3122SRobert Richter if (vector && !eilvt_entry_is_changeable(vector, new)) 412a68c439bSRobert Richter /* may not change if vectors are different */ 413a68c439bSRobert Richter return rsvd; 414a68c439bSRobert Richter rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 415a68c439bSRobert Richter } while (rsvd != new); 416a68c439bSRobert Richter 4178abc3122SRobert Richter rsvd &= ~APIC_EILVT_MASKED; 4188abc3122SRobert Richter if (rsvd && rsvd != vector) 4198abc3122SRobert Richter pr_info("LVT offset %d assigned for vector 0x%02x\n", 4208abc3122SRobert Richter offset, rsvd); 4218abc3122SRobert Richter 422a68c439bSRobert Richter return new; 423a68c439bSRobert Richter } 424a68c439bSRobert Richter 425a68c439bSRobert Richter /* 426a68c439bSRobert Richter * If mask=1, the LVT entry does not generate interrupts while mask=0 427cbf74ceaSRobert Richter * enables the vector. See also the BKDGs. Must be called with 428cbf74ceaSRobert Richter * preemption disabled. 429a68c439bSRobert Richter */ 430a68c439bSRobert Richter 43127afdf20SRobert Richter int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 432a68c439bSRobert Richter { 433a68c439bSRobert Richter unsigned long reg = APIC_EILVTn(offset); 434a68c439bSRobert Richter unsigned int new, old, reserved; 435a68c439bSRobert Richter 436a68c439bSRobert Richter new = (mask << 16) | (msg_type << 8) | vector; 437a68c439bSRobert Richter old = apic_read(reg); 438a68c439bSRobert Richter reserved = reserve_eilvt_offset(offset, new); 439a68c439bSRobert Richter 440a68c439bSRobert Richter if (reserved != new) { 441eb48c9cbSRobert Richter pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 442eb48c9cbSRobert Richter "vector 0x%x, but the register is already in use for " 443eb48c9cbSRobert Richter "vector 0x%x on another cpu\n", 444eb48c9cbSRobert Richter smp_processor_id(), reg, offset, new, reserved); 445a68c439bSRobert Richter return -EINVAL; 446a68c439bSRobert Richter } 447a68c439bSRobert Richter 448a68c439bSRobert Richter if (!eilvt_entry_is_changeable(old, new)) { 449eb48c9cbSRobert Richter pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 450eb48c9cbSRobert Richter "vector 0x%x, but the register is already in use for " 451eb48c9cbSRobert Richter "vector 0x%x on this cpu\n", 452eb48c9cbSRobert Richter smp_processor_id(), reg, offset, new, old); 453a68c439bSRobert Richter return -EBUSY; 454a68c439bSRobert Richter } 455a68c439bSRobert Richter 456a68c439bSRobert Richter apic_write(reg, new); 457a68c439bSRobert Richter 458a68c439bSRobert Richter return 0; 459f62bae50SIngo Molnar } 46027afdf20SRobert Richter EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 461f62bae50SIngo Molnar 462f62bae50SIngo Molnar /* 463f62bae50SIngo Molnar * Program the next event, relative to now 464f62bae50SIngo Molnar */ 465f62bae50SIngo Molnar static int lapic_next_event(unsigned long delta, 466f62bae50SIngo Molnar struct clock_event_device *evt) 467f62bae50SIngo Molnar { 468f62bae50SIngo Molnar apic_write(APIC_TMICT, delta); 469f62bae50SIngo Molnar return 0; 470f62bae50SIngo Molnar } 471f62bae50SIngo Molnar 472279f1461SSuresh Siddha static int lapic_next_deadline(unsigned long delta, 473279f1461SSuresh Siddha struct clock_event_device *evt) 474279f1461SSuresh Siddha { 475279f1461SSuresh Siddha u64 tsc; 476279f1461SSuresh Siddha 4774ea1636bSAndy Lutomirski tsc = rdtsc(); 478279f1461SSuresh Siddha wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); 479279f1461SSuresh Siddha return 0; 480279f1461SSuresh Siddha } 481279f1461SSuresh Siddha 482b23d8e52SViresh Kumar static int lapic_timer_shutdown(struct clock_event_device *evt) 483f62bae50SIngo Molnar { 484f62bae50SIngo Molnar unsigned int v; 485f62bae50SIngo Molnar 486f62bae50SIngo Molnar /* Lapic used as dummy for broadcast ? */ 487f62bae50SIngo Molnar if (evt->features & CLOCK_EVT_FEAT_DUMMY) 488b23d8e52SViresh Kumar return 0; 489f62bae50SIngo Molnar 490f62bae50SIngo Molnar v = apic_read(APIC_LVTT); 491f62bae50SIngo Molnar v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 492f62bae50SIngo Molnar apic_write(APIC_LVTT, v); 4936f9b4100SAndreas Herrmann apic_write(APIC_TMICT, 0); 494b23d8e52SViresh Kumar return 0; 495f62bae50SIngo Molnar } 496f62bae50SIngo Molnar 497b23d8e52SViresh Kumar static inline int 498b23d8e52SViresh Kumar lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot) 499b23d8e52SViresh Kumar { 500b23d8e52SViresh Kumar /* Lapic used as dummy for broadcast ? */ 501b23d8e52SViresh Kumar if (evt->features & CLOCK_EVT_FEAT_DUMMY) 502b23d8e52SViresh Kumar return 0; 503b23d8e52SViresh Kumar 50452ae346bSDaniel Drake __setup_APIC_LVTT(lapic_timer_period, oneshot, 1); 505b23d8e52SViresh Kumar return 0; 506b23d8e52SViresh Kumar } 507b23d8e52SViresh Kumar 508b23d8e52SViresh Kumar static int lapic_timer_set_periodic(struct clock_event_device *evt) 509b23d8e52SViresh Kumar { 510b23d8e52SViresh Kumar return lapic_timer_set_periodic_oneshot(evt, false); 511b23d8e52SViresh Kumar } 512b23d8e52SViresh Kumar 513b23d8e52SViresh Kumar static int lapic_timer_set_oneshot(struct clock_event_device *evt) 514b23d8e52SViresh Kumar { 515b23d8e52SViresh Kumar return lapic_timer_set_periodic_oneshot(evt, true); 516f62bae50SIngo Molnar } 517f62bae50SIngo Molnar 518f62bae50SIngo Molnar /* 519f62bae50SIngo Molnar * Local APIC timer broadcast function 520f62bae50SIngo Molnar */ 521f62bae50SIngo Molnar static void lapic_timer_broadcast(const struct cpumask *mask) 522f62bae50SIngo Molnar { 523f62bae50SIngo Molnar #ifdef CONFIG_SMP 524f62bae50SIngo Molnar apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 525f62bae50SIngo Molnar #endif 526f62bae50SIngo Molnar } 527f62bae50SIngo Molnar 52825874a29SHenrik Kretzschmar 52925874a29SHenrik Kretzschmar /* 53025874a29SHenrik Kretzschmar * The local apic timer can be used for any function which is CPU local. 53125874a29SHenrik Kretzschmar */ 53225874a29SHenrik Kretzschmar static struct clock_event_device lapic_clockevent = { 53325874a29SHenrik Kretzschmar .name = "lapic", 534b23d8e52SViresh Kumar .features = CLOCK_EVT_FEAT_PERIODIC | 535b23d8e52SViresh Kumar CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP 536b23d8e52SViresh Kumar | CLOCK_EVT_FEAT_DUMMY, 53725874a29SHenrik Kretzschmar .shift = 32, 538b23d8e52SViresh Kumar .set_state_shutdown = lapic_timer_shutdown, 539b23d8e52SViresh Kumar .set_state_periodic = lapic_timer_set_periodic, 540b23d8e52SViresh Kumar .set_state_oneshot = lapic_timer_set_oneshot, 541914122c3SFrederic Weisbecker .set_state_oneshot_stopped = lapic_timer_shutdown, 54225874a29SHenrik Kretzschmar .set_next_event = lapic_next_event, 54325874a29SHenrik Kretzschmar .broadcast = lapic_timer_broadcast, 54425874a29SHenrik Kretzschmar .rating = 100, 54525874a29SHenrik Kretzschmar .irq = -1, 54625874a29SHenrik Kretzschmar }; 54725874a29SHenrik Kretzschmar static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 54825874a29SHenrik Kretzschmar 549bd9240a1SPeter Zijlstra #define DEADLINE_MODEL_MATCH_FUNC(model, func) \ 550bd9240a1SPeter Zijlstra { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&func } 551bd9240a1SPeter Zijlstra 552bd9240a1SPeter Zijlstra #define DEADLINE_MODEL_MATCH_REV(model, rev) \ 553bd9240a1SPeter Zijlstra { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)rev } 554bd9240a1SPeter Zijlstra 555bd9240a1SPeter Zijlstra static u32 hsx_deadline_rev(void) 556bd9240a1SPeter Zijlstra { 557b399151cSJia Zhang switch (boot_cpu_data.x86_stepping) { 558bd9240a1SPeter Zijlstra case 0x02: return 0x3a; /* EP */ 559bd9240a1SPeter Zijlstra case 0x04: return 0x0f; /* EX */ 560bd9240a1SPeter Zijlstra } 561bd9240a1SPeter Zijlstra 562bd9240a1SPeter Zijlstra return ~0U; 563bd9240a1SPeter Zijlstra } 564bd9240a1SPeter Zijlstra 565bd9240a1SPeter Zijlstra static u32 bdx_deadline_rev(void) 566bd9240a1SPeter Zijlstra { 567b399151cSJia Zhang switch (boot_cpu_data.x86_stepping) { 568bd9240a1SPeter Zijlstra case 0x02: return 0x00000011; 569bd9240a1SPeter Zijlstra case 0x03: return 0x0700000e; 570bd9240a1SPeter Zijlstra case 0x04: return 0x0f00000c; 571bd9240a1SPeter Zijlstra case 0x05: return 0x0e000003; 572bd9240a1SPeter Zijlstra } 573bd9240a1SPeter Zijlstra 574bd9240a1SPeter Zijlstra return ~0U; 575bd9240a1SPeter Zijlstra } 576bd9240a1SPeter Zijlstra 577616dd587SLen Brown static u32 skx_deadline_rev(void) 578616dd587SLen Brown { 579b399151cSJia Zhang switch (boot_cpu_data.x86_stepping) { 580616dd587SLen Brown case 0x03: return 0x01000136; 581616dd587SLen Brown case 0x04: return 0x02000014; 582616dd587SLen Brown } 583616dd587SLen Brown 584d9e6dbcfSLen Brown if (boot_cpu_data.x86_stepping > 4) 585d9e6dbcfSLen Brown return 0; 586d9e6dbcfSLen Brown 587616dd587SLen Brown return ~0U; 588616dd587SLen Brown } 589616dd587SLen Brown 590bd9240a1SPeter Zijlstra static const struct x86_cpu_id deadline_match[] = { 591bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X, hsx_deadline_rev), 592bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X, 0x0b000020), 593bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_XEON_D, bdx_deadline_rev), 594616dd587SLen Brown DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_SKYLAKE_X, skx_deadline_rev), 595bd9240a1SPeter Zijlstra 596bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_CORE, 0x22), 597bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_ULT, 0x20), 598bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_GT3E, 0x17), 599bd9240a1SPeter Zijlstra 600bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_CORE, 0x25), 601bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_GT3E, 0x17), 602bd9240a1SPeter Zijlstra 603bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE, 0xb2), 604bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP, 0xb2), 605bd9240a1SPeter Zijlstra 606bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE, 0x52), 607bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP, 0x52), 608bd9240a1SPeter Zijlstra 609bd9240a1SPeter Zijlstra {}, 610bd9240a1SPeter Zijlstra }; 611bd9240a1SPeter Zijlstra 612bd9240a1SPeter Zijlstra static void apic_check_deadline_errata(void) 613bd9240a1SPeter Zijlstra { 614594a30fbSHans de Goede const struct x86_cpu_id *m; 615bd9240a1SPeter Zijlstra u32 rev; 616bd9240a1SPeter Zijlstra 617cc6afe22SPaolo Bonzini if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER) || 618cc6afe22SPaolo Bonzini boot_cpu_has(X86_FEATURE_HYPERVISOR)) 619594a30fbSHans de Goede return; 620594a30fbSHans de Goede 621594a30fbSHans de Goede m = x86_match_cpu(deadline_match); 622bd9240a1SPeter Zijlstra if (!m) 623bd9240a1SPeter Zijlstra return; 624bd9240a1SPeter Zijlstra 625bd9240a1SPeter Zijlstra /* 626bd9240a1SPeter Zijlstra * Function pointers will have the MSB set due to address layout, 627bd9240a1SPeter Zijlstra * immediate revisions will not. 628bd9240a1SPeter Zijlstra */ 629bd9240a1SPeter Zijlstra if ((long)m->driver_data < 0) 630bd9240a1SPeter Zijlstra rev = ((u32 (*)(void))(m->driver_data))(); 631bd9240a1SPeter Zijlstra else 632bd9240a1SPeter Zijlstra rev = (u32)m->driver_data; 633bd9240a1SPeter Zijlstra 634bd9240a1SPeter Zijlstra if (boot_cpu_data.microcode >= rev) 635bd9240a1SPeter Zijlstra return; 636bd9240a1SPeter Zijlstra 637bd9240a1SPeter Zijlstra setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 638bd9240a1SPeter Zijlstra pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; " 639bd9240a1SPeter Zijlstra "please update microcode to version: 0x%x (or later)\n", rev); 640bd9240a1SPeter Zijlstra } 641bd9240a1SPeter Zijlstra 642f62bae50SIngo Molnar /* 643421f91d2SUwe Kleine-König * Setup the local APIC timer for this CPU. Copy the initialized values 644f62bae50SIngo Molnar * of the boot CPU and register the clock event in the framework. 645f62bae50SIngo Molnar */ 646148f9bb8SPaul Gortmaker static void setup_APIC_timer(void) 647f62bae50SIngo Molnar { 64889cbc767SChristoph Lameter struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 649f62bae50SIngo Molnar 650349c004eSChristoph Lameter if (this_cpu_has(X86_FEATURE_ARAT)) { 651db954b58SVenkatesh Pallipadi lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 652db954b58SVenkatesh Pallipadi /* Make LAPIC timer preferrable over percpu HPET */ 653db954b58SVenkatesh Pallipadi lapic_clockevent.rating = 150; 654db954b58SVenkatesh Pallipadi } 655db954b58SVenkatesh Pallipadi 656f62bae50SIngo Molnar memcpy(levt, &lapic_clockevent, sizeof(*levt)); 657f62bae50SIngo Molnar levt->cpumask = cpumask_of(smp_processor_id()); 658f62bae50SIngo Molnar 659279f1461SSuresh Siddha if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 660c6e9f42bSPeter Zijlstra levt->name = "lapic-deadline"; 661279f1461SSuresh Siddha levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | 662279f1461SSuresh Siddha CLOCK_EVT_FEAT_DUMMY); 663279f1461SSuresh Siddha levt->set_next_event = lapic_next_deadline; 664279f1461SSuresh Siddha clockevents_config_and_register(levt, 6651a9e4c56SNicolai Stange tsc_khz * (1000 / TSC_DIVISOR), 666279f1461SSuresh Siddha 0xF, ~0UL); 667279f1461SSuresh Siddha } else 668f62bae50SIngo Molnar clockevents_register_device(levt); 669f62bae50SIngo Molnar } 670f62bae50SIngo Molnar 671f62bae50SIngo Molnar /* 6726731b0d6SNicolai Stange * Install the updated TSC frequency from recalibration at the TSC 6736731b0d6SNicolai Stange * deadline clockevent devices. 6746731b0d6SNicolai Stange */ 6756731b0d6SNicolai Stange static void __lapic_update_tsc_freq(void *info) 6766731b0d6SNicolai Stange { 6776731b0d6SNicolai Stange struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 6786731b0d6SNicolai Stange 6796731b0d6SNicolai Stange if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 6806731b0d6SNicolai Stange return; 6816731b0d6SNicolai Stange 6826731b0d6SNicolai Stange clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR)); 6836731b0d6SNicolai Stange } 6846731b0d6SNicolai Stange 6856731b0d6SNicolai Stange void lapic_update_tsc_freq(void) 6866731b0d6SNicolai Stange { 6876731b0d6SNicolai Stange /* 6886731b0d6SNicolai Stange * The clockevent device's ->mult and ->shift can both be 6896731b0d6SNicolai Stange * changed. In order to avoid races, schedule the frequency 6906731b0d6SNicolai Stange * update code on each CPU. 6916731b0d6SNicolai Stange */ 6926731b0d6SNicolai Stange on_each_cpu(__lapic_update_tsc_freq, NULL, 0); 6936731b0d6SNicolai Stange } 6946731b0d6SNicolai Stange 6956731b0d6SNicolai Stange /* 696f62bae50SIngo Molnar * In this functions we calibrate APIC bus clocks to the external timer. 697f62bae50SIngo Molnar * 698f62bae50SIngo Molnar * We want to do the calibration only once since we want to have local timer 699f62bae50SIngo Molnar * irqs syncron. CPUs connected by the same APIC bus have the very same bus 700f62bae50SIngo Molnar * frequency. 701f62bae50SIngo Molnar * 702f62bae50SIngo Molnar * This was previously done by reading the PIT/HPET and waiting for a wrap 703f62bae50SIngo Molnar * around to find out, that a tick has elapsed. I have a box, where the PIT 704f62bae50SIngo Molnar * readout is broken, so it never gets out of the wait loop again. This was 705f62bae50SIngo Molnar * also reported by others. 706f62bae50SIngo Molnar * 707f62bae50SIngo Molnar * Monitoring the jiffies value is inaccurate and the clockevents 708f62bae50SIngo Molnar * infrastructure allows us to do a simple substitution of the interrupt 709f62bae50SIngo Molnar * handler. 710f62bae50SIngo Molnar * 711f62bae50SIngo Molnar * The calibration routine also uses the pm_timer when possible, as the PIT 712f62bae50SIngo Molnar * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 713f62bae50SIngo Molnar * back to normal later in the boot process). 714f62bae50SIngo Molnar */ 715f62bae50SIngo Molnar 716f62bae50SIngo Molnar #define LAPIC_CAL_LOOPS (HZ/10) 717f62bae50SIngo Molnar 718f62bae50SIngo Molnar static __initdata int lapic_cal_loops = -1; 719f62bae50SIngo Molnar static __initdata long lapic_cal_t1, lapic_cal_t2; 720f62bae50SIngo Molnar static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 721f62bae50SIngo Molnar static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 722f62bae50SIngo Molnar static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 723f62bae50SIngo Molnar 724f62bae50SIngo Molnar /* 725f62bae50SIngo Molnar * Temporary interrupt handler. 726f62bae50SIngo Molnar */ 727f62bae50SIngo Molnar static void __init lapic_cal_handler(struct clock_event_device *dev) 728f62bae50SIngo Molnar { 729f62bae50SIngo Molnar unsigned long long tsc = 0; 730f62bae50SIngo Molnar long tapic = apic_read(APIC_TMCCT); 731f62bae50SIngo Molnar unsigned long pm = acpi_pm_read_early(); 732f62bae50SIngo Molnar 73359e21e3dSBorislav Petkov if (boot_cpu_has(X86_FEATURE_TSC)) 7344ea1636bSAndy Lutomirski tsc = rdtsc(); 735f62bae50SIngo Molnar 736f62bae50SIngo Molnar switch (lapic_cal_loops++) { 737f62bae50SIngo Molnar case 0: 738f62bae50SIngo Molnar lapic_cal_t1 = tapic; 739f62bae50SIngo Molnar lapic_cal_tsc1 = tsc; 740f62bae50SIngo Molnar lapic_cal_pm1 = pm; 741f62bae50SIngo Molnar lapic_cal_j1 = jiffies; 742f62bae50SIngo Molnar break; 743f62bae50SIngo Molnar 744f62bae50SIngo Molnar case LAPIC_CAL_LOOPS: 745f62bae50SIngo Molnar lapic_cal_t2 = tapic; 746f62bae50SIngo Molnar lapic_cal_tsc2 = tsc; 747f62bae50SIngo Molnar if (pm < lapic_cal_pm1) 748f62bae50SIngo Molnar pm += ACPI_PM_OVRRUN; 749f62bae50SIngo Molnar lapic_cal_pm2 = pm; 750f62bae50SIngo Molnar lapic_cal_j2 = jiffies; 751f62bae50SIngo Molnar break; 752f62bae50SIngo Molnar } 753f62bae50SIngo Molnar } 754f62bae50SIngo Molnar 755f62bae50SIngo Molnar static int __init 756f62bae50SIngo Molnar calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 757f62bae50SIngo Molnar { 758f62bae50SIngo Molnar const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 759f62bae50SIngo Molnar const long pm_thresh = pm_100ms / 100; 760f62bae50SIngo Molnar unsigned long mult; 761f62bae50SIngo Molnar u64 res; 762f62bae50SIngo Molnar 763f62bae50SIngo Molnar #ifndef CONFIG_X86_PM_TIMER 764f62bae50SIngo Molnar return -1; 765f62bae50SIngo Molnar #endif 766f62bae50SIngo Molnar 767f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 768f62bae50SIngo Molnar 769f62bae50SIngo Molnar /* Check, if the PM timer is available */ 770f62bae50SIngo Molnar if (!deltapm) 771f62bae50SIngo Molnar return -1; 772f62bae50SIngo Molnar 773f62bae50SIngo Molnar mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 774f62bae50SIngo Molnar 775f62bae50SIngo Molnar if (deltapm > (pm_100ms - pm_thresh) && 776f62bae50SIngo Molnar deltapm < (pm_100ms + pm_thresh)) { 777f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 778f62bae50SIngo Molnar return 0; 779f62bae50SIngo Molnar } 780f62bae50SIngo Molnar 781f62bae50SIngo Molnar res = (((u64)deltapm) * mult) >> 22; 782f62bae50SIngo Molnar do_div(res, 1000000); 783f62bae50SIngo Molnar pr_warning("APIC calibration not consistent " 784f62bae50SIngo Molnar "with PM-Timer: %ldms instead of 100ms\n",(long)res); 785f62bae50SIngo Molnar 786f62bae50SIngo Molnar /* Correct the lapic counter value */ 787f62bae50SIngo Molnar res = (((u64)(*delta)) * pm_100ms); 788f62bae50SIngo Molnar do_div(res, deltapm); 789f62bae50SIngo Molnar pr_info("APIC delta adjusted to PM-Timer: " 790f62bae50SIngo Molnar "%lu (%ld)\n", (unsigned long)res, *delta); 791f62bae50SIngo Molnar *delta = (long)res; 792f62bae50SIngo Molnar 793f62bae50SIngo Molnar /* Correct the tsc counter value */ 79459e21e3dSBorislav Petkov if (boot_cpu_has(X86_FEATURE_TSC)) { 795f62bae50SIngo Molnar res = (((u64)(*deltatsc)) * pm_100ms); 796f62bae50SIngo Molnar do_div(res, deltapm); 797f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 798f62bae50SIngo Molnar "PM-Timer: %lu (%ld)\n", 799f62bae50SIngo Molnar (unsigned long)res, *deltatsc); 800f62bae50SIngo Molnar *deltatsc = (long)res; 801f62bae50SIngo Molnar } 802f62bae50SIngo Molnar 803f62bae50SIngo Molnar return 0; 804f62bae50SIngo Molnar } 805f62bae50SIngo Molnar 8066eb4f082SJacob Pan static int __init lapic_init_clockevent(void) 8076eb4f082SJacob Pan { 80852ae346bSDaniel Drake if (!lapic_timer_period) 8096eb4f082SJacob Pan return -1; 8106eb4f082SJacob Pan 8116eb4f082SJacob Pan /* Calculate the scaled math multiplication factor */ 81252ae346bSDaniel Drake lapic_clockevent.mult = div_sc(lapic_timer_period/APIC_DIVISOR, 8136eb4f082SJacob Pan TICK_NSEC, lapic_clockevent.shift); 8146eb4f082SJacob Pan lapic_clockevent.max_delta_ns = 8156eb4f082SJacob Pan clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 8166eb4f082SJacob Pan lapic_clockevent.max_delta_ticks = 0x7FFFFFFF; 8176eb4f082SJacob Pan lapic_clockevent.min_delta_ns = 8186eb4f082SJacob Pan clockevent_delta2ns(0xF, &lapic_clockevent); 8196eb4f082SJacob Pan lapic_clockevent.min_delta_ticks = 0xF; 8206eb4f082SJacob Pan 8216eb4f082SJacob Pan return 0; 8226eb4f082SJacob Pan } 8236eb4f082SJacob Pan 824c8c40767SThomas Gleixner bool __init apic_needs_pit(void) 825c8c40767SThomas Gleixner { 826c8c40767SThomas Gleixner /* 827c8c40767SThomas Gleixner * If the frequencies are not known, PIT is required for both TSC 828c8c40767SThomas Gleixner * and apic timer calibration. 829c8c40767SThomas Gleixner */ 830c8c40767SThomas Gleixner if (!tsc_khz || !cpu_khz) 831c8c40767SThomas Gleixner return true; 832c8c40767SThomas Gleixner 833c8c40767SThomas Gleixner /* Is there an APIC at all? */ 834c8c40767SThomas Gleixner if (!boot_cpu_has(X86_FEATURE_APIC)) 835c8c40767SThomas Gleixner return true; 836c8c40767SThomas Gleixner 837c8c40767SThomas Gleixner /* Deadline timer is based on TSC so no further PIT action required */ 838c8c40767SThomas Gleixner if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 839c8c40767SThomas Gleixner return false; 840c8c40767SThomas Gleixner 841c8c40767SThomas Gleixner /* APIC timer disabled? */ 842c8c40767SThomas Gleixner if (disable_apic_timer) 843c8c40767SThomas Gleixner return true; 844c8c40767SThomas Gleixner /* 845c8c40767SThomas Gleixner * The APIC timer frequency is known already, no PIT calibration 846c8c40767SThomas Gleixner * required. If unknown, let the PIT be initialized. 847c8c40767SThomas Gleixner */ 848c8c40767SThomas Gleixner return lapic_timer_period == 0; 849c8c40767SThomas Gleixner } 850c8c40767SThomas Gleixner 851f62bae50SIngo Molnar static int __init calibrate_APIC_clock(void) 852f62bae50SIngo Molnar { 85389cbc767SChristoph Lameter struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 854f62bae50SIngo Molnar void (*real_handler)(struct clock_event_device *dev); 855f62bae50SIngo Molnar unsigned long deltaj; 856f62bae50SIngo Molnar long delta, deltatsc; 857f62bae50SIngo Molnar int pm_referenced = 0; 858f62bae50SIngo Molnar 8596eb4f082SJacob Pan if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 8606eb4f082SJacob Pan return 0; 8616eb4f082SJacob Pan 8626eb4f082SJacob Pan /* 8636eb4f082SJacob Pan * Check if lapic timer has already been calibrated by platform 8646eb4f082SJacob Pan * specific routine, such as tsc calibration code. If so just fill 8651ade93efSJacob Pan * in the clockevent structure and return. 8661ade93efSJacob Pan */ 8676eb4f082SJacob Pan if (!lapic_init_clockevent()) { 8681ade93efSJacob Pan apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", 86952ae346bSDaniel Drake lapic_timer_period); 8706eb4f082SJacob Pan /* 8716eb4f082SJacob Pan * Direct calibration methods must have an always running 8726eb4f082SJacob Pan * local APIC timer, no need for broadcast timer. 8736eb4f082SJacob Pan */ 8741ade93efSJacob Pan lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 8751ade93efSJacob Pan return 0; 8761ade93efSJacob Pan } 8771ade93efSJacob Pan 878279f1461SSuresh Siddha apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 879279f1461SSuresh Siddha "calibrating APIC timer ...\n"); 880279f1461SSuresh Siddha 881f62bae50SIngo Molnar local_irq_disable(); 882f62bae50SIngo Molnar 883f62bae50SIngo Molnar /* Replace the global interrupt handler */ 884f62bae50SIngo Molnar real_handler = global_clock_event->event_handler; 885f62bae50SIngo Molnar global_clock_event->event_handler = lapic_cal_handler; 886f62bae50SIngo Molnar 887f62bae50SIngo Molnar /* 888f62bae50SIngo Molnar * Setup the APIC counter to maximum. There is no way the lapic 889f62bae50SIngo Molnar * can underflow in the 100ms detection time frame 890f62bae50SIngo Molnar */ 891f62bae50SIngo Molnar __setup_APIC_LVTT(0xffffffff, 0, 0); 892f62bae50SIngo Molnar 893f62bae50SIngo Molnar /* Let the interrupts run */ 894f62bae50SIngo Molnar local_irq_enable(); 895f62bae50SIngo Molnar 896f62bae50SIngo Molnar while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 897f62bae50SIngo Molnar cpu_relax(); 898f62bae50SIngo Molnar 899f62bae50SIngo Molnar local_irq_disable(); 900f62bae50SIngo Molnar 901f62bae50SIngo Molnar /* Restore the real event handler */ 902f62bae50SIngo Molnar global_clock_event->event_handler = real_handler; 903f62bae50SIngo Molnar 904f62bae50SIngo Molnar /* Build delta t1-t2 as apic timer counts down */ 905f62bae50SIngo Molnar delta = lapic_cal_t1 - lapic_cal_t2; 906f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 907f62bae50SIngo Molnar 908f62bae50SIngo Molnar deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 909f62bae50SIngo Molnar 910f62bae50SIngo Molnar /* we trust the PM based calibration if possible */ 911f62bae50SIngo Molnar pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 912f62bae50SIngo Molnar &delta, &deltatsc); 913f62bae50SIngo Molnar 91452ae346bSDaniel Drake lapic_timer_period = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 9156eb4f082SJacob Pan lapic_init_clockevent(); 916f62bae50SIngo Molnar 917f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 918411462f6SThomas Gleixner apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 919f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 92052ae346bSDaniel Drake lapic_timer_period); 921f62bae50SIngo Molnar 92259e21e3dSBorislav Petkov if (boot_cpu_has(X86_FEATURE_TSC)) { 923f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 924f62bae50SIngo Molnar "%ld.%04ld MHz.\n", 925f62bae50SIngo Molnar (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 926f62bae50SIngo Molnar (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 927f62bae50SIngo Molnar } 928f62bae50SIngo Molnar 929f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 930f62bae50SIngo Molnar "%u.%04u MHz.\n", 93152ae346bSDaniel Drake lapic_timer_period / (1000000 / HZ), 93252ae346bSDaniel Drake lapic_timer_period % (1000000 / HZ)); 933f62bae50SIngo Molnar 934f62bae50SIngo Molnar /* 935f62bae50SIngo Molnar * Do a sanity check on the APIC calibration result 936f62bae50SIngo Molnar */ 93752ae346bSDaniel Drake if (lapic_timer_period < (1000000 / HZ)) { 938f62bae50SIngo Molnar local_irq_enable(); 939f62bae50SIngo Molnar pr_warning("APIC frequency too slow, disabling apic timer\n"); 940f62bae50SIngo Molnar return -1; 941f62bae50SIngo Molnar } 942f62bae50SIngo Molnar 943f62bae50SIngo Molnar levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 944f62bae50SIngo Molnar 945f62bae50SIngo Molnar /* 946f62bae50SIngo Molnar * PM timer calibration failed or not turned on 947f62bae50SIngo Molnar * so lets try APIC timer based calibration 948f62bae50SIngo Molnar */ 949f62bae50SIngo Molnar if (!pm_referenced) { 950f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 951f62bae50SIngo Molnar 952f62bae50SIngo Molnar /* 953f62bae50SIngo Molnar * Setup the apic timer manually 954f62bae50SIngo Molnar */ 955f62bae50SIngo Molnar levt->event_handler = lapic_cal_handler; 956b23d8e52SViresh Kumar lapic_timer_set_periodic(levt); 957f62bae50SIngo Molnar lapic_cal_loops = -1; 958f62bae50SIngo Molnar 959f62bae50SIngo Molnar /* Let the interrupts run */ 960f62bae50SIngo Molnar local_irq_enable(); 961f62bae50SIngo Molnar 962f62bae50SIngo Molnar while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 963f62bae50SIngo Molnar cpu_relax(); 964f62bae50SIngo Molnar 965f62bae50SIngo Molnar /* Stop the lapic timer */ 966c948c260SThomas Gleixner local_irq_disable(); 967b23d8e52SViresh Kumar lapic_timer_shutdown(levt); 968f62bae50SIngo Molnar 969f62bae50SIngo Molnar /* Jiffies delta */ 970f62bae50SIngo Molnar deltaj = lapic_cal_j2 - lapic_cal_j1; 971f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 972f62bae50SIngo Molnar 973f62bae50SIngo Molnar /* Check, if the jiffies result is consistent */ 974f62bae50SIngo Molnar if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 975f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 976f62bae50SIngo Molnar else 977f62bae50SIngo Molnar levt->features |= CLOCK_EVT_FEAT_DUMMY; 978c948c260SThomas Gleixner } 979f62bae50SIngo Molnar local_irq_enable(); 980f62bae50SIngo Molnar 981f62bae50SIngo Molnar if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 982f62bae50SIngo Molnar pr_warning("APIC timer disabled due to verification failure\n"); 983f62bae50SIngo Molnar return -1; 984f62bae50SIngo Molnar } 985f62bae50SIngo Molnar 986f62bae50SIngo Molnar return 0; 987f62bae50SIngo Molnar } 988f62bae50SIngo Molnar 989f62bae50SIngo Molnar /* 990f62bae50SIngo Molnar * Setup the boot APIC 991f62bae50SIngo Molnar * 992f62bae50SIngo Molnar * Calibrate and verify the result. 993f62bae50SIngo Molnar */ 994f62bae50SIngo Molnar void __init setup_boot_APIC_clock(void) 995f62bae50SIngo Molnar { 996f62bae50SIngo Molnar /* 997f62bae50SIngo Molnar * The local apic timer can be disabled via the kernel 998f62bae50SIngo Molnar * commandline or from the CPU detection code. Register the lapic 999f62bae50SIngo Molnar * timer as a dummy clock event source on SMP systems, so the 1000f62bae50SIngo Molnar * broadcast mechanism is used. On UP systems simply ignore it. 1001f62bae50SIngo Molnar */ 1002f62bae50SIngo Molnar if (disable_apic_timer) { 1003f62bae50SIngo Molnar pr_info("Disabling APIC timer\n"); 1004f62bae50SIngo Molnar /* No broadcast on UP ! */ 1005f62bae50SIngo Molnar if (num_possible_cpus() > 1) { 1006f62bae50SIngo Molnar lapic_clockevent.mult = 1; 1007f62bae50SIngo Molnar setup_APIC_timer(); 1008f62bae50SIngo Molnar } 1009f62bae50SIngo Molnar return; 1010f62bae50SIngo Molnar } 1011f62bae50SIngo Molnar 1012f62bae50SIngo Molnar if (calibrate_APIC_clock()) { 1013f62bae50SIngo Molnar /* No broadcast on UP ! */ 1014f62bae50SIngo Molnar if (num_possible_cpus() > 1) 1015f62bae50SIngo Molnar setup_APIC_timer(); 1016f62bae50SIngo Molnar return; 1017f62bae50SIngo Molnar } 1018f62bae50SIngo Molnar 1019f62bae50SIngo Molnar /* 1020f62bae50SIngo Molnar * If nmi_watchdog is set to IO_APIC, we need the 1021f62bae50SIngo Molnar * PIT/HPET going. Otherwise register lapic as a dummy 1022f62bae50SIngo Molnar * device. 1023f62bae50SIngo Molnar */ 1024f62bae50SIngo Molnar lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 1025f62bae50SIngo Molnar 1026f62bae50SIngo Molnar /* Setup the lapic or request the broadcast */ 1027f62bae50SIngo Molnar setup_APIC_timer(); 102807c94a38SBorislav Petkov amd_e400_c1e_apic_setup(); 1029f62bae50SIngo Molnar } 1030f62bae50SIngo Molnar 1031148f9bb8SPaul Gortmaker void setup_secondary_APIC_clock(void) 1032f62bae50SIngo Molnar { 1033f62bae50SIngo Molnar setup_APIC_timer(); 103407c94a38SBorislav Petkov amd_e400_c1e_apic_setup(); 1035f62bae50SIngo Molnar } 1036f62bae50SIngo Molnar 1037f62bae50SIngo Molnar /* 1038f62bae50SIngo Molnar * The guts of the apic timer interrupt 1039f62bae50SIngo Molnar */ 1040f62bae50SIngo Molnar static void local_apic_timer_interrupt(void) 1041f62bae50SIngo Molnar { 10423bec6defSThomas Gleixner struct clock_event_device *evt = this_cpu_ptr(&lapic_events); 1043f62bae50SIngo Molnar 1044f62bae50SIngo Molnar /* 1045f62bae50SIngo Molnar * Normally we should not be here till LAPIC has been initialized but 1046f62bae50SIngo Molnar * in some cases like kdump, its possible that there is a pending LAPIC 1047f62bae50SIngo Molnar * timer interrupt from previous kernel's context and is delivered in 1048f62bae50SIngo Molnar * new kernel the moment interrupts are enabled. 1049f62bae50SIngo Molnar * 1050f62bae50SIngo Molnar * Interrupts are enabled early and LAPIC is setup much later, hence 1051f62bae50SIngo Molnar * its possible that when we get here evt->event_handler is NULL. 1052f62bae50SIngo Molnar * Check for event_handler being NULL and discard the interrupt as 1053f62bae50SIngo Molnar * spurious. 1054f62bae50SIngo Molnar */ 1055f62bae50SIngo Molnar if (!evt->event_handler) { 10563bec6defSThomas Gleixner pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", 10573bec6defSThomas Gleixner smp_processor_id()); 1058f62bae50SIngo Molnar /* Switch it off */ 1059b23d8e52SViresh Kumar lapic_timer_shutdown(evt); 1060f62bae50SIngo Molnar return; 1061f62bae50SIngo Molnar } 1062f62bae50SIngo Molnar 1063f62bae50SIngo Molnar /* 1064f62bae50SIngo Molnar * the NMI deadlock-detector uses this. 1065f62bae50SIngo Molnar */ 1066f62bae50SIngo Molnar inc_irq_stat(apic_timer_irqs); 1067f62bae50SIngo Molnar 1068f62bae50SIngo Molnar evt->event_handler(evt); 1069f62bae50SIngo Molnar } 1070f62bae50SIngo Molnar 1071f62bae50SIngo Molnar /* 1072f62bae50SIngo Molnar * Local APIC timer interrupt. This is the most natural way for doing 1073f62bae50SIngo Molnar * local interrupts, but local timer interrupts can be emulated by 1074f62bae50SIngo Molnar * broadcast interrupts too. [in case the hw doesn't support APIC timers] 1075f62bae50SIngo Molnar * 1076f62bae50SIngo Molnar * [ if a single-CPU system runs an SMP kernel then we call the local 1077f62bae50SIngo Molnar * interrupt as well. Thus we cannot inline the local irq ... ] 1078f62bae50SIngo Molnar */ 10791d9090e2SAndi Kleen __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 1080f62bae50SIngo Molnar { 1081f62bae50SIngo Molnar struct pt_regs *old_regs = set_irq_regs(regs); 1082f62bae50SIngo Molnar 1083f62bae50SIngo Molnar /* 1084f62bae50SIngo Molnar * NOTE! We'd better ACK the irq immediately, 1085f62bae50SIngo Molnar * because timer handling can be slow. 1086eddc0e92SSeiji Aguchi * 1087f62bae50SIngo Molnar * update_process_times() expects us to have done irq_enter(). 1088f62bae50SIngo Molnar * Besides, if we don't timer interrupts ignore the global 1089f62bae50SIngo Molnar * interrupt lock, which is the WrongThing (tm) to do. 1090f62bae50SIngo Molnar */ 1091eddc0e92SSeiji Aguchi entering_ack_irq(); 1092cf910e83SSeiji Aguchi trace_local_timer_entry(LOCAL_TIMER_VECTOR); 1093cf910e83SSeiji Aguchi local_apic_timer_interrupt(); 1094cf910e83SSeiji Aguchi trace_local_timer_exit(LOCAL_TIMER_VECTOR); 1095cf910e83SSeiji Aguchi exiting_irq(); 1096f62bae50SIngo Molnar 1097f62bae50SIngo Molnar set_irq_regs(old_regs); 1098f62bae50SIngo Molnar } 1099f62bae50SIngo Molnar 1100f62bae50SIngo Molnar int setup_profiling_timer(unsigned int multiplier) 1101f62bae50SIngo Molnar { 1102f62bae50SIngo Molnar return -EINVAL; 1103f62bae50SIngo Molnar } 1104f62bae50SIngo Molnar 1105f62bae50SIngo Molnar /* 1106f62bae50SIngo Molnar * Local APIC start and shutdown 1107f62bae50SIngo Molnar */ 1108f62bae50SIngo Molnar 1109f62bae50SIngo Molnar /** 1110f62bae50SIngo Molnar * clear_local_APIC - shutdown the local APIC 1111f62bae50SIngo Molnar * 1112f62bae50SIngo Molnar * This is called, when a CPU is disabled and before rebooting, so the state of 1113f62bae50SIngo Molnar * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 1114f62bae50SIngo Molnar * leftovers during boot. 1115f62bae50SIngo Molnar */ 1116f62bae50SIngo Molnar void clear_local_APIC(void) 1117f62bae50SIngo Molnar { 1118f62bae50SIngo Molnar int maxlvt; 1119f62bae50SIngo Molnar u32 v; 1120f62bae50SIngo Molnar 1121f62bae50SIngo Molnar /* APIC hasn't been mapped yet */ 1122fc1edaf9SSuresh Siddha if (!x2apic_mode && !apic_phys) 1123f62bae50SIngo Molnar return; 1124f62bae50SIngo Molnar 1125f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 1126f62bae50SIngo Molnar /* 1127f62bae50SIngo Molnar * Masking an LVT entry can trigger a local APIC error 1128f62bae50SIngo Molnar * if the vector is zero. Mask LVTERR first to prevent this. 1129f62bae50SIngo Molnar */ 1130f62bae50SIngo Molnar if (maxlvt >= 3) { 1131f62bae50SIngo Molnar v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 1132f62bae50SIngo Molnar apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 1133f62bae50SIngo Molnar } 1134f62bae50SIngo Molnar /* 1135f62bae50SIngo Molnar * Careful: we have to set masks only first to deassert 1136f62bae50SIngo Molnar * any level-triggered sources. 1137f62bae50SIngo Molnar */ 1138f62bae50SIngo Molnar v = apic_read(APIC_LVTT); 1139f62bae50SIngo Molnar apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 1140f62bae50SIngo Molnar v = apic_read(APIC_LVT0); 1141f62bae50SIngo Molnar apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 1142f62bae50SIngo Molnar v = apic_read(APIC_LVT1); 1143f62bae50SIngo Molnar apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 1144f62bae50SIngo Molnar if (maxlvt >= 4) { 1145f62bae50SIngo Molnar v = apic_read(APIC_LVTPC); 1146f62bae50SIngo Molnar apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 1147f62bae50SIngo Molnar } 1148f62bae50SIngo Molnar 1149f62bae50SIngo Molnar /* lets not touch this if we didn't frob it */ 11504efc0670SAndi Kleen #ifdef CONFIG_X86_THERMAL_VECTOR 1151f62bae50SIngo Molnar if (maxlvt >= 5) { 1152f62bae50SIngo Molnar v = apic_read(APIC_LVTTHMR); 1153f62bae50SIngo Molnar apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 1154f62bae50SIngo Molnar } 1155f62bae50SIngo Molnar #endif 1156638bee71SH. Peter Anvin #ifdef CONFIG_X86_MCE_INTEL 1157638bee71SH. Peter Anvin if (maxlvt >= 6) { 1158638bee71SH. Peter Anvin v = apic_read(APIC_LVTCMCI); 1159638bee71SH. Peter Anvin if (!(v & APIC_LVT_MASKED)) 1160638bee71SH. Peter Anvin apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 1161638bee71SH. Peter Anvin } 1162638bee71SH. Peter Anvin #endif 1163638bee71SH. Peter Anvin 1164f62bae50SIngo Molnar /* 1165f62bae50SIngo Molnar * Clean APIC state for other OSs: 1166f62bae50SIngo Molnar */ 1167f62bae50SIngo Molnar apic_write(APIC_LVTT, APIC_LVT_MASKED); 1168f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_LVT_MASKED); 1169f62bae50SIngo Molnar apic_write(APIC_LVT1, APIC_LVT_MASKED); 1170f62bae50SIngo Molnar if (maxlvt >= 3) 1171f62bae50SIngo Molnar apic_write(APIC_LVTERR, APIC_LVT_MASKED); 1172f62bae50SIngo Molnar if (maxlvt >= 4) 1173f62bae50SIngo Molnar apic_write(APIC_LVTPC, APIC_LVT_MASKED); 1174f62bae50SIngo Molnar 1175f62bae50SIngo Molnar /* Integrated APIC (!82489DX) ? */ 1176f62bae50SIngo Molnar if (lapic_is_integrated()) { 1177f62bae50SIngo Molnar if (maxlvt > 3) 1178f62bae50SIngo Molnar /* Clear ESR due to Pentium errata 3AP and 11AP */ 1179f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1180f62bae50SIngo Molnar apic_read(APIC_ESR); 1181f62bae50SIngo Molnar } 1182f62bae50SIngo Molnar } 1183f62bae50SIngo Molnar 1184f62bae50SIngo Molnar /** 1185f62bae50SIngo Molnar * disable_local_APIC - clear and disable the local APIC 1186f62bae50SIngo Molnar */ 1187f62bae50SIngo Molnar void disable_local_APIC(void) 1188f62bae50SIngo Molnar { 1189f62bae50SIngo Molnar unsigned int value; 1190f62bae50SIngo Molnar 1191f62bae50SIngo Molnar /* APIC hasn't been mapped yet */ 1192fd19dce7SYinghai Lu if (!x2apic_mode && !apic_phys) 1193f62bae50SIngo Molnar return; 1194f62bae50SIngo Molnar 1195f62bae50SIngo Molnar clear_local_APIC(); 1196f62bae50SIngo Molnar 1197f62bae50SIngo Molnar /* 1198f62bae50SIngo Molnar * Disable APIC (implies clearing of registers 1199f62bae50SIngo Molnar * for 82489DX!). 1200f62bae50SIngo Molnar */ 1201f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 1202f62bae50SIngo Molnar value &= ~APIC_SPIV_APIC_ENABLED; 1203f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 1204f62bae50SIngo Molnar 1205f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1206f62bae50SIngo Molnar /* 1207f62bae50SIngo Molnar * When LAPIC was disabled by the BIOS and enabled by the kernel, 1208f62bae50SIngo Molnar * restore the disabled state. 1209f62bae50SIngo Molnar */ 1210f62bae50SIngo Molnar if (enabled_via_apicbase) { 1211f62bae50SIngo Molnar unsigned int l, h; 1212f62bae50SIngo Molnar 1213f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, l, h); 1214f62bae50SIngo Molnar l &= ~MSR_IA32_APICBASE_ENABLE; 1215f62bae50SIngo Molnar wrmsr(MSR_IA32_APICBASE, l, h); 1216f62bae50SIngo Molnar } 1217f62bae50SIngo Molnar #endif 1218f62bae50SIngo Molnar } 1219f62bae50SIngo Molnar 1220f62bae50SIngo Molnar /* 1221f62bae50SIngo Molnar * If Linux enabled the LAPIC against the BIOS default disable it down before 1222f62bae50SIngo Molnar * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 1223f62bae50SIngo Molnar * not power-off. Additionally clear all LVT entries before disable_local_APIC 1224f62bae50SIngo Molnar * for the case where Linux didn't enable the LAPIC. 1225f62bae50SIngo Molnar */ 1226f62bae50SIngo Molnar void lapic_shutdown(void) 1227f62bae50SIngo Molnar { 1228f62bae50SIngo Molnar unsigned long flags; 1229f62bae50SIngo Molnar 123093984fbdSBorislav Petkov if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) 1231f62bae50SIngo Molnar return; 1232f62bae50SIngo Molnar 1233f62bae50SIngo Molnar local_irq_save(flags); 1234f62bae50SIngo Molnar 1235f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1236f62bae50SIngo Molnar if (!enabled_via_apicbase) 1237f62bae50SIngo Molnar clear_local_APIC(); 1238f62bae50SIngo Molnar else 1239f62bae50SIngo Molnar #endif 1240f62bae50SIngo Molnar disable_local_APIC(); 1241f62bae50SIngo Molnar 1242f62bae50SIngo Molnar 1243f62bae50SIngo Molnar local_irq_restore(flags); 1244f62bae50SIngo Molnar } 1245f62bae50SIngo Molnar 1246f62bae50SIngo Molnar /** 1247f62bae50SIngo Molnar * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1248f62bae50SIngo Molnar */ 1249f62bae50SIngo Molnar void __init sync_Arb_IDs(void) 1250f62bae50SIngo Molnar { 1251f62bae50SIngo Molnar /* 1252f62bae50SIngo Molnar * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1253f62bae50SIngo Molnar * needed on AMD. 1254f62bae50SIngo Molnar */ 1255f62bae50SIngo Molnar if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1256f62bae50SIngo Molnar return; 1257f62bae50SIngo Molnar 1258f62bae50SIngo Molnar /* 1259f62bae50SIngo Molnar * Wait for idle. 1260f62bae50SIngo Molnar */ 1261f62bae50SIngo Molnar apic_wait_icr_idle(); 1262f62bae50SIngo Molnar 1263f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1264f62bae50SIngo Molnar apic_write(APIC_ICR, APIC_DEST_ALLINC | 1265f62bae50SIngo Molnar APIC_INT_LEVELTRIG | APIC_DM_INIT); 1266f62bae50SIngo Molnar } 1267f62bae50SIngo Molnar 12684f45ed9fSDou Liyang enum apic_intr_mode_id apic_intr_mode; 12690114a8e8SDou Liyang 12700114a8e8SDou Liyang static int __init apic_intr_mode_select(void) 1271f62bae50SIngo Molnar { 12720114a8e8SDou Liyang /* Check kernel option */ 12730114a8e8SDou Liyang if (disable_apic) { 12740114a8e8SDou Liyang pr_info("APIC disabled via kernel command line\n"); 12750114a8e8SDou Liyang return APIC_PIC; 12760114a8e8SDou Liyang } 1277f62bae50SIngo Molnar 12780114a8e8SDou Liyang /* Check BIOS */ 12790114a8e8SDou Liyang #ifdef CONFIG_X86_64 12800114a8e8SDou Liyang /* On 64-bit, the APIC must be integrated, Check local APIC only */ 12810114a8e8SDou Liyang if (!boot_cpu_has(X86_FEATURE_APIC)) { 12820114a8e8SDou Liyang disable_apic = 1; 12830114a8e8SDou Liyang pr_info("APIC disabled by BIOS\n"); 12840114a8e8SDou Liyang return APIC_PIC; 12850114a8e8SDou Liyang } 12860114a8e8SDou Liyang #else 12870114a8e8SDou Liyang /* On 32-bit, the APIC may be integrated APIC or 82489DX */ 1288f62bae50SIngo Molnar 12890114a8e8SDou Liyang /* Neither 82489DX nor integrated APIC ? */ 12900114a8e8SDou Liyang if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) { 12910114a8e8SDou Liyang disable_apic = 1; 12920114a8e8SDou Liyang return APIC_PIC; 12930114a8e8SDou Liyang } 1294f62bae50SIngo Molnar 12950114a8e8SDou Liyang /* If the BIOS pretends there is an integrated APIC ? */ 12960114a8e8SDou Liyang if (!boot_cpu_has(X86_FEATURE_APIC) && 12970114a8e8SDou Liyang APIC_INTEGRATED(boot_cpu_apic_version)) { 12980114a8e8SDou Liyang disable_apic = 1; 12990114a8e8SDou Liyang pr_err(FW_BUG "Local APIC %d not detected, force emulation\n", 13000114a8e8SDou Liyang boot_cpu_physical_apicid); 13010114a8e8SDou Liyang return APIC_PIC; 13020114a8e8SDou Liyang } 1303f62bae50SIngo Molnar #endif 1304f62bae50SIngo Molnar 13050114a8e8SDou Liyang /* Check MP table or ACPI MADT configuration */ 13060114a8e8SDou Liyang if (!smp_found_config) { 13070114a8e8SDou Liyang disable_ioapic_support(); 13083e730dadSDou Liyang if (!acpi_lapic) { 13090114a8e8SDou Liyang pr_info("APIC: ACPI MADT or MP tables are not detected\n"); 13103e730dadSDou Liyang return APIC_VIRTUAL_WIRE_NO_CONFIG; 13113e730dadSDou Liyang } 13120114a8e8SDou Liyang return APIC_VIRTUAL_WIRE; 13130114a8e8SDou Liyang } 13140114a8e8SDou Liyang 13153e730dadSDou Liyang #ifdef CONFIG_SMP 13163e730dadSDou Liyang /* If SMP should be disabled, then really disable it! */ 13173e730dadSDou Liyang if (!setup_max_cpus) { 13183e730dadSDou Liyang pr_info("APIC: SMP mode deactivated\n"); 13193e730dadSDou Liyang return APIC_SYMMETRIC_IO_NO_ROUTING; 13203e730dadSDou Liyang } 13213e730dadSDou Liyang 13223e730dadSDou Liyang if (read_apic_id() != boot_cpu_physical_apicid) { 13233e730dadSDou Liyang panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 13243e730dadSDou Liyang read_apic_id(), boot_cpu_physical_apicid); 13253e730dadSDou Liyang /* Or can we switch back to PIC here? */ 13263e730dadSDou Liyang } 13273e730dadSDou Liyang #endif 13283e730dadSDou Liyang 13290114a8e8SDou Liyang return APIC_SYMMETRIC_IO; 13300114a8e8SDou Liyang } 13310114a8e8SDou Liyang 1332fc90ccfdSVille Syrjälä /* 1333fc90ccfdSVille Syrjälä * An initial setup of the virtual wire mode. 1334fc90ccfdSVille Syrjälä */ 1335fc90ccfdSVille Syrjälä void __init init_bsp_APIC(void) 1336fc90ccfdSVille Syrjälä { 1337fc90ccfdSVille Syrjälä unsigned int value; 1338fc90ccfdSVille Syrjälä 1339fc90ccfdSVille Syrjälä /* 1340fc90ccfdSVille Syrjälä * Don't do the setup now if we have a SMP BIOS as the 1341fc90ccfdSVille Syrjälä * through-I/O-APIC virtual wire mode might be active. 1342fc90ccfdSVille Syrjälä */ 1343fc90ccfdSVille Syrjälä if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC)) 1344fc90ccfdSVille Syrjälä return; 1345fc90ccfdSVille Syrjälä 1346fc90ccfdSVille Syrjälä /* 1347fc90ccfdSVille Syrjälä * Do not trust the local APIC being empty at bootup. 1348fc90ccfdSVille Syrjälä */ 1349fc90ccfdSVille Syrjälä clear_local_APIC(); 1350fc90ccfdSVille Syrjälä 1351fc90ccfdSVille Syrjälä /* 1352fc90ccfdSVille Syrjälä * Enable APIC. 1353fc90ccfdSVille Syrjälä */ 1354fc90ccfdSVille Syrjälä value = apic_read(APIC_SPIV); 1355fc90ccfdSVille Syrjälä value &= ~APIC_VECTOR_MASK; 1356fc90ccfdSVille Syrjälä value |= APIC_SPIV_APIC_ENABLED; 1357fc90ccfdSVille Syrjälä 1358fc90ccfdSVille Syrjälä #ifdef CONFIG_X86_32 1359fc90ccfdSVille Syrjälä /* This bit is reserved on P4/Xeon and should be cleared */ 1360fc90ccfdSVille Syrjälä if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1361fc90ccfdSVille Syrjälä (boot_cpu_data.x86 == 15)) 1362fc90ccfdSVille Syrjälä value &= ~APIC_SPIV_FOCUS_DISABLED; 1363fc90ccfdSVille Syrjälä else 1364fc90ccfdSVille Syrjälä #endif 1365fc90ccfdSVille Syrjälä value |= APIC_SPIV_FOCUS_DISABLED; 1366fc90ccfdSVille Syrjälä value |= SPURIOUS_APIC_VECTOR; 1367fc90ccfdSVille Syrjälä apic_write(APIC_SPIV, value); 1368fc90ccfdSVille Syrjälä 1369fc90ccfdSVille Syrjälä /* 1370fc90ccfdSVille Syrjälä * Set up the virtual wire mode. 1371fc90ccfdSVille Syrjälä */ 1372fc90ccfdSVille Syrjälä apic_write(APIC_LVT0, APIC_DM_EXTINT); 1373fc90ccfdSVille Syrjälä value = APIC_DM_NMI; 1374fc90ccfdSVille Syrjälä if (!lapic_is_integrated()) /* 82489DX */ 1375fc90ccfdSVille Syrjälä value |= APIC_LVT_LEVEL_TRIGGER; 1376fc90ccfdSVille Syrjälä if (apic_extnmi == APIC_EXTNMI_NONE) 1377fc90ccfdSVille Syrjälä value |= APIC_LVT_MASKED; 1378fc90ccfdSVille Syrjälä apic_write(APIC_LVT1, value); 1379fc90ccfdSVille Syrjälä } 1380fc90ccfdSVille Syrjälä 1381748b170cSThomas Gleixner static void __init apic_bsp_setup(bool upmode); 1382748b170cSThomas Gleixner 13834b1669e8SDou Liyang /* Init the interrupt delivery mode for the BSP */ 13844b1669e8SDou Liyang void __init apic_intr_mode_init(void) 13854b1669e8SDou Liyang { 13860c759131SDou Liyang bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT); 13873e730dadSDou Liyang 13884f45ed9fSDou Liyang apic_intr_mode = apic_intr_mode_select(); 13894f45ed9fSDou Liyang 13904f45ed9fSDou Liyang switch (apic_intr_mode) { 13914b1669e8SDou Liyang case APIC_PIC: 13924b1669e8SDou Liyang pr_info("APIC: Keep in PIC mode(8259)\n"); 13934b1669e8SDou Liyang return; 13944b1669e8SDou Liyang case APIC_VIRTUAL_WIRE: 13954b1669e8SDou Liyang pr_info("APIC: Switch to virtual wire mode setup\n"); 13963e730dadSDou Liyang default_setup_apic_routing(); 13973e730dadSDou Liyang break; 13983e730dadSDou Liyang case APIC_VIRTUAL_WIRE_NO_CONFIG: 13993e730dadSDou Liyang pr_info("APIC: Switch to virtual wire mode setup with no configuration\n"); 14003e730dadSDou Liyang upmode = true; 14013e730dadSDou Liyang default_setup_apic_routing(); 14023e730dadSDou Liyang break; 14034b1669e8SDou Liyang case APIC_SYMMETRIC_IO: 140479761ce8SColin Ian King pr_info("APIC: Switch to symmetric I/O mode setup\n"); 14053e730dadSDou Liyang default_setup_apic_routing(); 14063e730dadSDou Liyang break; 14073e730dadSDou Liyang case APIC_SYMMETRIC_IO_NO_ROUTING: 140879761ce8SColin Ian King pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n"); 14093e730dadSDou Liyang break; 14104b1669e8SDou Liyang } 14113e730dadSDou Liyang 14123e730dadSDou Liyang apic_bsp_setup(upmode); 1413f62bae50SIngo Molnar } 1414f62bae50SIngo Molnar 1415148f9bb8SPaul Gortmaker static void lapic_setup_esr(void) 1416f62bae50SIngo Molnar { 1417f62bae50SIngo Molnar unsigned int oldvalue, value, maxlvt; 1418f62bae50SIngo Molnar 1419f62bae50SIngo Molnar if (!lapic_is_integrated()) { 1420f62bae50SIngo Molnar pr_info("No ESR for 82489DX.\n"); 1421f62bae50SIngo Molnar return; 1422f62bae50SIngo Molnar } 1423f62bae50SIngo Molnar 1424f62bae50SIngo Molnar if (apic->disable_esr) { 1425f62bae50SIngo Molnar /* 1426f62bae50SIngo Molnar * Something untraceable is creating bad interrupts on 1427f62bae50SIngo Molnar * secondary quads ... for the moment, just leave the 1428f62bae50SIngo Molnar * ESR disabled - we can't do anything useful with the 1429f62bae50SIngo Molnar * errors anyway - mbligh 1430f62bae50SIngo Molnar */ 1431f62bae50SIngo Molnar pr_info("Leaving ESR disabled.\n"); 1432f62bae50SIngo Molnar return; 1433f62bae50SIngo Molnar } 1434f62bae50SIngo Molnar 1435f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 1436f62bae50SIngo Molnar if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1437f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1438f62bae50SIngo Molnar oldvalue = apic_read(APIC_ESR); 1439f62bae50SIngo Molnar 1440f62bae50SIngo Molnar /* enables sending errors */ 1441f62bae50SIngo Molnar value = ERROR_APIC_VECTOR; 1442f62bae50SIngo Molnar apic_write(APIC_LVTERR, value); 1443f62bae50SIngo Molnar 1444f62bae50SIngo Molnar /* 1445f62bae50SIngo Molnar * spec says clear errors after enabling vector. 1446f62bae50SIngo Molnar */ 1447f62bae50SIngo Molnar if (maxlvt > 3) 1448f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1449f62bae50SIngo Molnar value = apic_read(APIC_ESR); 1450f62bae50SIngo Molnar if (value != oldvalue) 1451f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "ESR value before enabling " 1452f62bae50SIngo Molnar "vector: 0x%08x after: 0x%08x\n", 1453f62bae50SIngo Molnar oldvalue, value); 1454f62bae50SIngo Molnar } 1455f62bae50SIngo Molnar 14569b217f33SDou Liyang static void apic_pending_intr_clear(void) 14579b217f33SDou Liyang { 14589b217f33SDou Liyang long long max_loops = cpu_khz ? cpu_khz : 1000000; 14599b217f33SDou Liyang unsigned long long tsc = 0, ntsc; 14603ea9e7aeSDou Liyang unsigned int queued; 14613ea9e7aeSDou Liyang unsigned long value; 14629b217f33SDou Liyang int i, j, acked = 0; 14639b217f33SDou Liyang 14649b217f33SDou Liyang if (boot_cpu_has(X86_FEATURE_TSC)) 14659b217f33SDou Liyang tsc = rdtsc(); 14669b217f33SDou Liyang /* 14679b217f33SDou Liyang * After a crash, we no longer service the interrupts and a pending 14689b217f33SDou Liyang * interrupt from previous kernel might still have ISR bit set. 14699b217f33SDou Liyang * 14709b217f33SDou Liyang * Most probably by now CPU has serviced that pending interrupt and 14719b217f33SDou Liyang * it might not have done the ack_APIC_irq() because it thought, 14729b217f33SDou Liyang * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 14739b217f33SDou Liyang * does not clear the ISR bit and cpu thinks it has already serivced 14749b217f33SDou Liyang * the interrupt. Hence a vector might get locked. It was noticed 14759b217f33SDou Liyang * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 14769b217f33SDou Liyang */ 14779b217f33SDou Liyang do { 14789b217f33SDou Liyang queued = 0; 14799b217f33SDou Liyang for (i = APIC_ISR_NR - 1; i >= 0; i--) 14809b217f33SDou Liyang queued |= apic_read(APIC_IRR + i*0x10); 14819b217f33SDou Liyang 14829b217f33SDou Liyang for (i = APIC_ISR_NR - 1; i >= 0; i--) { 14839b217f33SDou Liyang value = apic_read(APIC_ISR + i*0x10); 14843ea9e7aeSDou Liyang for_each_set_bit(j, &value, 32) { 14859b217f33SDou Liyang ack_APIC_irq(); 14869b217f33SDou Liyang acked++; 14879b217f33SDou Liyang } 14889b217f33SDou Liyang } 14899b217f33SDou Liyang if (acked > 256) { 14903ea9e7aeSDou Liyang pr_err("LAPIC pending interrupts after %d EOI\n", acked); 14919b217f33SDou Liyang break; 14929b217f33SDou Liyang } 14939b217f33SDou Liyang if (queued) { 14949b217f33SDou Liyang if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) { 14959b217f33SDou Liyang ntsc = rdtsc(); 1496ea136a11SColin Ian King max_loops = (long long)cpu_khz << 10; 1497ea136a11SColin Ian King max_loops -= ntsc - tsc; 14983ea9e7aeSDou Liyang } else { 14999b217f33SDou Liyang max_loops--; 15009b217f33SDou Liyang } 15013ea9e7aeSDou Liyang } 15029b217f33SDou Liyang } while (queued && max_loops > 0); 15039b217f33SDou Liyang WARN_ON(max_loops <= 0); 15049b217f33SDou Liyang } 15059b217f33SDou Liyang 1506f62bae50SIngo Molnar /** 1507f62bae50SIngo Molnar * setup_local_APIC - setup the local APIC 15080aa002feSTejun Heo * 1509543113d2SDou Liyang * Used to setup local APIC while initializing BSP or bringing up APs. 15100aa002feSTejun Heo * Always called with preemption disabled. 1511f62bae50SIngo Molnar */ 1512b753a2b7SDou Liyang static void setup_local_APIC(void) 1513f62bae50SIngo Molnar { 15140aa002feSTejun Heo int cpu = smp_processor_id(); 15159b217f33SDou Liyang unsigned int value; 15169b217f33SDou Liyang #ifdef CONFIG_X86_32 15178f156168SDou Liyang int logical_apicid, ldr_apicid; 15189b217f33SDou Liyang #endif 15198c3ba8d0SKerstin Jonsson 1520f62bae50SIngo Molnar 1521f62bae50SIngo Molnar if (disable_apic) { 15227167d08eSHenrik Kretzschmar disable_ioapic_support(); 1523f62bae50SIngo Molnar return; 1524f62bae50SIngo Molnar } 1525f62bae50SIngo Molnar 1526f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1527f62bae50SIngo Molnar /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1528f62bae50SIngo Molnar if (lapic_is_integrated() && apic->disable_esr) { 1529f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1530f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1531f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1532f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1533f62bae50SIngo Molnar } 1534f62bae50SIngo Molnar #endif 1535cdd6c482SIngo Molnar perf_events_lapic_init(); 1536f62bae50SIngo Molnar 1537f62bae50SIngo Molnar /* 1538f62bae50SIngo Molnar * Double-check whether this APIC is really registered. 1539f62bae50SIngo Molnar * This is meaningless in clustered apic mode, so we skip it. 1540f62bae50SIngo Molnar */ 1541c2777f98SDaniel Walker BUG_ON(!apic->apic_id_registered()); 1542f62bae50SIngo Molnar 1543f62bae50SIngo Molnar /* 1544f62bae50SIngo Molnar * Intel recommends to set DFR, LDR and TPR before enabling 1545f62bae50SIngo Molnar * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1546f62bae50SIngo Molnar * document number 292116). So here it goes... 1547f62bae50SIngo Molnar */ 1548f62bae50SIngo Molnar apic->init_apic_ldr(); 1549f62bae50SIngo Molnar 15506f802c4bSTejun Heo #ifdef CONFIG_X86_32 15516f802c4bSTejun Heo /* 1552acb8bc09STejun Heo * APIC LDR is initialized. If logical_apicid mapping was 1553acb8bc09STejun Heo * initialized during get_smp_config(), make sure it matches the 1554acb8bc09STejun Heo * actual value. 15556f802c4bSTejun Heo */ 15568f156168SDou Liyang logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu); 15578f156168SDou Liyang ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 15588f156168SDou Liyang WARN_ON(logical_apicid != BAD_APICID && logical_apicid != ldr_apicid); 1559acb8bc09STejun Heo /* always use the value from LDR */ 15608f156168SDou Liyang early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid; 15616f802c4bSTejun Heo #endif 15626f802c4bSTejun Heo 1563f62bae50SIngo Molnar /* 1564f62bae50SIngo Molnar * Set Task Priority to 'accept all'. We never change this 1565f62bae50SIngo Molnar * later on. 1566f62bae50SIngo Molnar */ 1567f62bae50SIngo Molnar value = apic_read(APIC_TASKPRI); 1568f62bae50SIngo Molnar value &= ~APIC_TPRI_MASK; 1569f62bae50SIngo Molnar apic_write(APIC_TASKPRI, value); 1570f62bae50SIngo Molnar 15719b217f33SDou Liyang apic_pending_intr_clear(); 1572f62bae50SIngo Molnar 1573f62bae50SIngo Molnar /* 1574f62bae50SIngo Molnar * Now that we are all set up, enable the APIC 1575f62bae50SIngo Molnar */ 1576f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 1577f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 1578f62bae50SIngo Molnar /* 1579f62bae50SIngo Molnar * Enable APIC 1580f62bae50SIngo Molnar */ 1581f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 1582f62bae50SIngo Molnar 1583f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1584f62bae50SIngo Molnar /* 1585f62bae50SIngo Molnar * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1586f62bae50SIngo Molnar * certain networking cards. If high frequency interrupts are 1587f62bae50SIngo Molnar * happening on a particular IOAPIC pin, plus the IOAPIC routing 1588f62bae50SIngo Molnar * entry is masked/unmasked at a high rate as well then sooner or 1589f62bae50SIngo Molnar * later IOAPIC line gets 'stuck', no more interrupts are received 1590f62bae50SIngo Molnar * from the device. If focus CPU is disabled then the hang goes 1591f62bae50SIngo Molnar * away, oh well :-( 1592f62bae50SIngo Molnar * 1593f62bae50SIngo Molnar * [ This bug can be reproduced easily with a level-triggered 1594f62bae50SIngo Molnar * PCI Ne2000 networking cards and PII/PIII processors, dual 1595f62bae50SIngo Molnar * BX chipset. ] 1596f62bae50SIngo Molnar */ 1597f62bae50SIngo Molnar /* 1598f62bae50SIngo Molnar * Actually disabling the focus CPU check just makes the hang less 1599f62bae50SIngo Molnar * frequent as it makes the interrupt distributon model be more 1600f62bae50SIngo Molnar * like LRU than MRU (the short-term load is more even across CPUs). 1601f62bae50SIngo Molnar */ 1602f62bae50SIngo Molnar 1603f62bae50SIngo Molnar /* 1604f62bae50SIngo Molnar * - enable focus processor (bit==0) 1605f62bae50SIngo Molnar * - 64bit mode always use processor focus 1606f62bae50SIngo Molnar * so no need to set it 1607f62bae50SIngo Molnar */ 1608f62bae50SIngo Molnar value &= ~APIC_SPIV_FOCUS_DISABLED; 1609f62bae50SIngo Molnar #endif 1610f62bae50SIngo Molnar 1611f62bae50SIngo Molnar /* 1612f62bae50SIngo Molnar * Set spurious IRQ vector 1613f62bae50SIngo Molnar */ 1614f62bae50SIngo Molnar value |= SPURIOUS_APIC_VECTOR; 1615f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 1616f62bae50SIngo Molnar 1617f62bae50SIngo Molnar /* 1618f62bae50SIngo Molnar * Set up LVT0, LVT1: 1619f62bae50SIngo Molnar * 1620a1652bb8SJean Delvare * set up through-local-APIC on the boot CPU's LINT0. This is not 1621f62bae50SIngo Molnar * strictly necessary in pure symmetric-IO mode, but sometimes 1622f62bae50SIngo Molnar * we delegate interrupts to the 8259A. 1623f62bae50SIngo Molnar */ 1624f62bae50SIngo Molnar /* 1625f62bae50SIngo Molnar * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1626f62bae50SIngo Molnar */ 1627f62bae50SIngo Molnar value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1628bee3204eSBaoquan He if (!cpu && (pic_mode || !value || skip_ioapic_setup)) { 1629f62bae50SIngo Molnar value = APIC_DM_EXTINT; 16300aa002feSTejun Heo apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1631f62bae50SIngo Molnar } else { 1632f62bae50SIngo Molnar value = APIC_DM_EXTINT | APIC_LVT_MASKED; 16330aa002feSTejun Heo apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1634f62bae50SIngo Molnar } 1635f62bae50SIngo Molnar apic_write(APIC_LVT0, value); 1636f62bae50SIngo Molnar 1637f62bae50SIngo Molnar /* 1638b7c4948eSHidehiro Kawai * Only the BSP sees the LINT1 NMI signal by default. This can be 1639b7c4948eSHidehiro Kawai * modified by apic_extnmi= boot option. 1640f62bae50SIngo Molnar */ 1641b7c4948eSHidehiro Kawai if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) || 1642b7c4948eSHidehiro Kawai apic_extnmi == APIC_EXTNMI_ALL) 1643f62bae50SIngo Molnar value = APIC_DM_NMI; 1644f62bae50SIngo Molnar else 1645f62bae50SIngo Molnar value = APIC_DM_NMI | APIC_LVT_MASKED; 1646ae41a2a4SDou Liyang 1647ae41a2a4SDou Liyang /* Is 82489DX ? */ 1648ae41a2a4SDou Liyang if (!lapic_is_integrated()) 1649f62bae50SIngo Molnar value |= APIC_LVT_LEVEL_TRIGGER; 1650f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 1651f62bae50SIngo Molnar 1652638bee71SH. Peter Anvin #ifdef CONFIG_X86_MCE_INTEL 1653638bee71SH. Peter Anvin /* Recheck CMCI information after local APIC is up on CPU #0 */ 16540aa002feSTejun Heo if (!cpu) 1655638bee71SH. Peter Anvin cmci_recheck(); 1656638bee71SH. Peter Anvin #endif 1657f62bae50SIngo Molnar } 1658f62bae50SIngo Molnar 165905f7e46dSThomas Gleixner static void end_local_APIC_setup(void) 1660f62bae50SIngo Molnar { 1661f62bae50SIngo Molnar lapic_setup_esr(); 1662f62bae50SIngo Molnar 1663f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1664f62bae50SIngo Molnar { 1665f62bae50SIngo Molnar unsigned int value; 1666f62bae50SIngo Molnar /* Disable the local apic timer */ 1667f62bae50SIngo Molnar value = apic_read(APIC_LVTT); 1668f62bae50SIngo Molnar value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1669f62bae50SIngo Molnar apic_write(APIC_LVTT, value); 1670f62bae50SIngo Molnar } 1671f62bae50SIngo Molnar #endif 1672f62bae50SIngo Molnar 1673f62bae50SIngo Molnar apic_pm_activate(); 16742fb270f3SJan Beulich } 16752fb270f3SJan Beulich 16767f7fbf45SKenji Kaneshige /* 167705f7e46dSThomas Gleixner * APIC setup function for application processors. Called from smpboot.c 16787f7fbf45SKenji Kaneshige */ 167905f7e46dSThomas Gleixner void apic_ap_setup(void) 168005f7e46dSThomas Gleixner { 168105f7e46dSThomas Gleixner setup_local_APIC(); 168205f7e46dSThomas Gleixner end_local_APIC_setup(); 1683f62bae50SIngo Molnar } 1684f62bae50SIngo Molnar 1685f62bae50SIngo Molnar #ifdef CONFIG_X86_X2APIC 1686bfb05070SThomas Gleixner int x2apic_mode; 168712e189d3SThomas Gleixner 168812e189d3SThomas Gleixner enum { 168912e189d3SThomas Gleixner X2APIC_OFF, 169012e189d3SThomas Gleixner X2APIC_ON, 169112e189d3SThomas Gleixner X2APIC_DISABLED, 169212e189d3SThomas Gleixner }; 169312e189d3SThomas Gleixner static int x2apic_state; 169412e189d3SThomas Gleixner 1695d786ad32SDenys Vlasenko static void __x2apic_disable(void) 169644e25ff9SThomas Gleixner { 169744e25ff9SThomas Gleixner u64 msr; 169844e25ff9SThomas Gleixner 169993984fbdSBorislav Petkov if (!boot_cpu_has(X86_FEATURE_APIC)) 1700659006bfSThomas Gleixner return; 1701659006bfSThomas Gleixner 170244e25ff9SThomas Gleixner rdmsrl(MSR_IA32_APICBASE, msr); 170344e25ff9SThomas Gleixner if (!(msr & X2APIC_ENABLE)) 170444e25ff9SThomas Gleixner return; 170544e25ff9SThomas Gleixner /* Disable xapic and x2apic first and then reenable xapic mode */ 170644e25ff9SThomas Gleixner wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); 170744e25ff9SThomas Gleixner wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); 170844e25ff9SThomas Gleixner printk_once(KERN_INFO "x2apic disabled\n"); 170944e25ff9SThomas Gleixner } 171044e25ff9SThomas Gleixner 1711d786ad32SDenys Vlasenko static void __x2apic_enable(void) 1712659006bfSThomas Gleixner { 1713659006bfSThomas Gleixner u64 msr; 1714659006bfSThomas Gleixner 1715659006bfSThomas Gleixner rdmsrl(MSR_IA32_APICBASE, msr); 1716659006bfSThomas Gleixner if (msr & X2APIC_ENABLE) 1717659006bfSThomas Gleixner return; 1718659006bfSThomas Gleixner wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); 1719659006bfSThomas Gleixner printk_once(KERN_INFO "x2apic enabled\n"); 1720659006bfSThomas Gleixner } 1721659006bfSThomas Gleixner 1722bfb05070SThomas Gleixner static int __init setup_nox2apic(char *str) 1723bfb05070SThomas Gleixner { 1724bfb05070SThomas Gleixner if (x2apic_enabled()) { 1725bfb05070SThomas Gleixner int apicid = native_apic_msr_read(APIC_ID); 1726bfb05070SThomas Gleixner 1727bfb05070SThomas Gleixner if (apicid >= 255) { 1728bfb05070SThomas Gleixner pr_warning("Apicid: %08x, cannot enforce nox2apic\n", 1729bfb05070SThomas Gleixner apicid); 1730bfb05070SThomas Gleixner return 0; 1731bfb05070SThomas Gleixner } 173244e25ff9SThomas Gleixner pr_warning("x2apic already enabled.\n"); 173344e25ff9SThomas Gleixner __x2apic_disable(); 173444e25ff9SThomas Gleixner } 1735bfb05070SThomas Gleixner setup_clear_cpu_cap(X86_FEATURE_X2APIC); 173612e189d3SThomas Gleixner x2apic_state = X2APIC_DISABLED; 173744e25ff9SThomas Gleixner x2apic_mode = 0; 1738bfb05070SThomas Gleixner return 0; 1739bfb05070SThomas Gleixner } 1740bfb05070SThomas Gleixner early_param("nox2apic", setup_nox2apic); 1741bfb05070SThomas Gleixner 1742659006bfSThomas Gleixner /* Called from cpu_init() to enable x2apic on (secondary) cpus */ 1743659006bfSThomas Gleixner void x2apic_setup(void) 1744659006bfSThomas Gleixner { 1745659006bfSThomas Gleixner /* 1746659006bfSThomas Gleixner * If x2apic is not in ON state, disable it if already enabled 1747659006bfSThomas Gleixner * from BIOS. 1748659006bfSThomas Gleixner */ 1749659006bfSThomas Gleixner if (x2apic_state != X2APIC_ON) { 1750659006bfSThomas Gleixner __x2apic_disable(); 1751659006bfSThomas Gleixner return; 1752659006bfSThomas Gleixner } 1753659006bfSThomas Gleixner __x2apic_enable(); 1754659006bfSThomas Gleixner } 1755659006bfSThomas Gleixner 175644e25ff9SThomas Gleixner static __init void x2apic_disable(void) 1757fb209bd8SYinghai Lu { 1758a57e456aSThomas Gleixner u32 x2apic_id, state = x2apic_state; 1759fb209bd8SYinghai Lu 1760a57e456aSThomas Gleixner x2apic_mode = 0; 1761a57e456aSThomas Gleixner x2apic_state = X2APIC_DISABLED; 1762a57e456aSThomas Gleixner 1763a57e456aSThomas Gleixner if (state != X2APIC_ON) 1764a57e456aSThomas Gleixner return; 1765fb209bd8SYinghai Lu 17666d2d49d2SThomas Gleixner x2apic_id = read_apic_id(); 1767fb209bd8SYinghai Lu if (x2apic_id >= 255) 1768fb209bd8SYinghai Lu panic("Cannot disable x2apic, id: %08x\n", x2apic_id); 1769fb209bd8SYinghai Lu 177044e25ff9SThomas Gleixner __x2apic_disable(); 1771fb209bd8SYinghai Lu register_lapic_address(mp_lapic_addr); 1772fb209bd8SYinghai Lu } 1773fb209bd8SYinghai Lu 1774659006bfSThomas Gleixner static __init void x2apic_enable(void) 1775f62bae50SIngo Molnar { 1776659006bfSThomas Gleixner if (x2apic_state != X2APIC_OFF) 1777f62bae50SIngo Molnar return; 1778f62bae50SIngo Molnar 1779659006bfSThomas Gleixner x2apic_mode = 1; 178012e189d3SThomas Gleixner x2apic_state = X2APIC_ON; 1781659006bfSThomas Gleixner __x2apic_enable(); 1782f62bae50SIngo Molnar } 1783d524165cSThomas Gleixner 178462e61633SThomas Gleixner static __init void try_to_enable_x2apic(int remap_mode) 178507806c50SJiang Liu { 1786659006bfSThomas Gleixner if (x2apic_state == X2APIC_DISABLED) 178707806c50SJiang Liu return; 178807806c50SJiang Liu 178962e61633SThomas Gleixner if (remap_mode != IRQ_REMAP_X2APIC_MODE) { 179007806c50SJiang Liu /* IR is required if there is APIC ID > 255 even when running 179107806c50SJiang Liu * under KVM 179207806c50SJiang Liu */ 179307806c50SJiang Liu if (max_physical_apicid > 255 || 1794f72e38e8SJuergen Gross !x86_init.hyper.x2apic_available()) { 179562e61633SThomas Gleixner pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); 179644e25ff9SThomas Gleixner x2apic_disable(); 179707806c50SJiang Liu return; 179807806c50SJiang Liu } 179907806c50SJiang Liu 180007806c50SJiang Liu /* 180107806c50SJiang Liu * without IR all CPUs can be addressed by IOAPIC/MSI 180207806c50SJiang Liu * only in physical mode 180307806c50SJiang Liu */ 180455eae7deSThomas Gleixner x2apic_phys = 1; 180507806c50SJiang Liu } 1806659006bfSThomas Gleixner x2apic_enable(); 180755eae7deSThomas Gleixner } 180855eae7deSThomas Gleixner 180955eae7deSThomas Gleixner void __init check_x2apic(void) 181055eae7deSThomas Gleixner { 181155eae7deSThomas Gleixner if (x2apic_enabled()) { 181255eae7deSThomas Gleixner pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); 181355eae7deSThomas Gleixner x2apic_mode = 1; 181412e189d3SThomas Gleixner x2apic_state = X2APIC_ON; 181562436a4dSBorislav Petkov } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) { 181612e189d3SThomas Gleixner x2apic_state = X2APIC_DISABLED; 181755eae7deSThomas Gleixner } 181855eae7deSThomas Gleixner } 181955eae7deSThomas Gleixner #else /* CONFIG_X86_X2APIC */ 182055eae7deSThomas Gleixner static int __init validate_x2apic(void) 182155eae7deSThomas Gleixner { 182255eae7deSThomas Gleixner if (!apic_is_x2apic_enabled()) 182355eae7deSThomas Gleixner return 0; 182455eae7deSThomas Gleixner /* 182555eae7deSThomas Gleixner * Checkme: Can we simply turn off x2apic here instead of panic? 182655eae7deSThomas Gleixner */ 182755eae7deSThomas Gleixner panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n"); 182855eae7deSThomas Gleixner } 182955eae7deSThomas Gleixner early_initcall(validate_x2apic); 183055eae7deSThomas Gleixner 183162e61633SThomas Gleixner static inline void try_to_enable_x2apic(int remap_mode) { } 1832659006bfSThomas Gleixner static inline void __x2apic_enable(void) { } 183355eae7deSThomas Gleixner #endif /* !CONFIG_X86_X2APIC */ 183455eae7deSThomas Gleixner 1835ce69a784SGleb Natapov void __init enable_IR_x2apic(void) 1836ce69a784SGleb Natapov { 1837ce69a784SGleb Natapov unsigned long flags; 183807806c50SJiang Liu int ret, ir_stat; 1839b7f42ab2SYinghai Lu 184011277aabSDou Liyang if (skip_ioapic_setup) { 184111277aabSDou Liyang pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); 18422e63ad4bSWanpeng Li return; 184311277aabSDou Liyang } 18442e63ad4bSWanpeng Li 184507806c50SJiang Liu ir_stat = irq_remapping_prepare(); 184607806c50SJiang Liu if (ir_stat < 0 && !x2apic_supported()) 1847e670761fSYinghai Lu return; 1848ce69a784SGleb Natapov 184931dce14aSSuresh Siddha ret = save_ioapic_entries(); 1850f62bae50SIngo Molnar if (ret) { 1851f62bae50SIngo Molnar pr_info("Saving IO-APIC state failed: %d\n", ret); 1852fb209bd8SYinghai Lu return; 1853f62bae50SIngo Molnar } 1854f62bae50SIngo Molnar 185505c3dc2cSSuresh Siddha local_irq_save(flags); 1856b81bb373SJacob Pan legacy_pic->mask_all(); 185731dce14aSSuresh Siddha mask_ioapic_entries(); 185805c3dc2cSSuresh Siddha 18596a6256f9SAdam Buchbinder /* If irq_remapping_prepare() succeeded, try to enable it */ 186007806c50SJiang Liu if (ir_stat >= 0) 186111277aabSDou Liyang ir_stat = irq_remapping_enable(); 186207806c50SJiang Liu /* ir_stat contains the remap mode or an error code */ 186307806c50SJiang Liu try_to_enable_x2apic(ir_stat); 1864a31bc327SYinghai Lu 186507806c50SJiang Liu if (ir_stat < 0) 186631dce14aSSuresh Siddha restore_ioapic_entries(); 1867b81bb373SJacob Pan legacy_pic->restore_mask(); 1868f62bae50SIngo Molnar local_irq_restore(flags); 1869f62bae50SIngo Molnar } 187093758238SWeidong Han 1871f62bae50SIngo Molnar #ifdef CONFIG_X86_64 1872f62bae50SIngo Molnar /* 1873f62bae50SIngo Molnar * Detect and enable local APICs on non-SMP boards. 1874f62bae50SIngo Molnar * Original code written by Keir Fraser. 1875f62bae50SIngo Molnar * On AMD64 we trust the BIOS - if it says no APIC it is likely 1876f62bae50SIngo Molnar * not correctly set up (usually the APIC timer won't work etc.) 1877f62bae50SIngo Molnar */ 1878f62bae50SIngo Molnar static int __init detect_init_APIC(void) 1879f62bae50SIngo Molnar { 188093984fbdSBorislav Petkov if (!boot_cpu_has(X86_FEATURE_APIC)) { 1881f62bae50SIngo Molnar pr_info("No local APIC present\n"); 1882f62bae50SIngo Molnar return -1; 1883f62bae50SIngo Molnar } 1884f62bae50SIngo Molnar 1885f62bae50SIngo Molnar mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1886f62bae50SIngo Molnar return 0; 1887f62bae50SIngo Molnar } 1888f62bae50SIngo Molnar #else 18895a7ae78fSThomas Gleixner 189025874a29SHenrik Kretzschmar static int __init apic_verify(void) 18915a7ae78fSThomas Gleixner { 18925a7ae78fSThomas Gleixner u32 features, h, l; 18935a7ae78fSThomas Gleixner 18945a7ae78fSThomas Gleixner /* 18955a7ae78fSThomas Gleixner * The APIC feature bit should now be enabled 18965a7ae78fSThomas Gleixner * in `cpuid' 18975a7ae78fSThomas Gleixner */ 18985a7ae78fSThomas Gleixner features = cpuid_edx(1); 18995a7ae78fSThomas Gleixner if (!(features & (1 << X86_FEATURE_APIC))) { 19005a7ae78fSThomas Gleixner pr_warning("Could not enable APIC!\n"); 19015a7ae78fSThomas Gleixner return -1; 19025a7ae78fSThomas Gleixner } 19035a7ae78fSThomas Gleixner set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 19045a7ae78fSThomas Gleixner mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 19055a7ae78fSThomas Gleixner 19065a7ae78fSThomas Gleixner /* The BIOS may have set up the APIC at some other address */ 1907cbf2829bSBryan O'Donoghue if (boot_cpu_data.x86 >= 6) { 19085a7ae78fSThomas Gleixner rdmsr(MSR_IA32_APICBASE, l, h); 19095a7ae78fSThomas Gleixner if (l & MSR_IA32_APICBASE_ENABLE) 19105a7ae78fSThomas Gleixner mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1911cbf2829bSBryan O'Donoghue } 19125a7ae78fSThomas Gleixner 19135a7ae78fSThomas Gleixner pr_info("Found and enabled local APIC!\n"); 19145a7ae78fSThomas Gleixner return 0; 19155a7ae78fSThomas Gleixner } 19165a7ae78fSThomas Gleixner 191725874a29SHenrik Kretzschmar int __init apic_force_enable(unsigned long addr) 19185a7ae78fSThomas Gleixner { 19195a7ae78fSThomas Gleixner u32 h, l; 19205a7ae78fSThomas Gleixner 19215a7ae78fSThomas Gleixner if (disable_apic) 19225a7ae78fSThomas Gleixner return -1; 19235a7ae78fSThomas Gleixner 19245a7ae78fSThomas Gleixner /* 19255a7ae78fSThomas Gleixner * Some BIOSes disable the local APIC in the APIC_BASE 19265a7ae78fSThomas Gleixner * MSR. This can only be done in software for Intel P6 or later 19275a7ae78fSThomas Gleixner * and AMD K7 (Model > 1) or later. 19285a7ae78fSThomas Gleixner */ 1929cbf2829bSBryan O'Donoghue if (boot_cpu_data.x86 >= 6) { 19305a7ae78fSThomas Gleixner rdmsr(MSR_IA32_APICBASE, l, h); 19315a7ae78fSThomas Gleixner if (!(l & MSR_IA32_APICBASE_ENABLE)) { 19325a7ae78fSThomas Gleixner pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 19335a7ae78fSThomas Gleixner l &= ~MSR_IA32_APICBASE_BASE; 1934a906fdaaSThomas Gleixner l |= MSR_IA32_APICBASE_ENABLE | addr; 19355a7ae78fSThomas Gleixner wrmsr(MSR_IA32_APICBASE, l, h); 19365a7ae78fSThomas Gleixner enabled_via_apicbase = 1; 19375a7ae78fSThomas Gleixner } 1938cbf2829bSBryan O'Donoghue } 19395a7ae78fSThomas Gleixner return apic_verify(); 19405a7ae78fSThomas Gleixner } 19415a7ae78fSThomas Gleixner 1942f62bae50SIngo Molnar /* 1943f62bae50SIngo Molnar * Detect and initialize APIC 1944f62bae50SIngo Molnar */ 1945f62bae50SIngo Molnar static int __init detect_init_APIC(void) 1946f62bae50SIngo Molnar { 1947f62bae50SIngo Molnar /* Disabled by kernel option? */ 1948f62bae50SIngo Molnar if (disable_apic) 1949f62bae50SIngo Molnar return -1; 1950f62bae50SIngo Molnar 1951f62bae50SIngo Molnar switch (boot_cpu_data.x86_vendor) { 1952f62bae50SIngo Molnar case X86_VENDOR_AMD: 1953f62bae50SIngo Molnar if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1954f62bae50SIngo Molnar (boot_cpu_data.x86 >= 15)) 1955f62bae50SIngo Molnar break; 1956f62bae50SIngo Molnar goto no_apic; 1957da33dfefSPu Wen case X86_VENDOR_HYGON: 1958da33dfefSPu Wen break; 1959f62bae50SIngo Molnar case X86_VENDOR_INTEL: 1960f62bae50SIngo Molnar if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 196193984fbdSBorislav Petkov (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC))) 1962f62bae50SIngo Molnar break; 1963f62bae50SIngo Molnar goto no_apic; 1964f62bae50SIngo Molnar default: 1965f62bae50SIngo Molnar goto no_apic; 1966f62bae50SIngo Molnar } 1967f62bae50SIngo Molnar 196893984fbdSBorislav Petkov if (!boot_cpu_has(X86_FEATURE_APIC)) { 1969f62bae50SIngo Molnar /* 1970f62bae50SIngo Molnar * Over-ride BIOS and try to enable the local APIC only if 1971f62bae50SIngo Molnar * "lapic" specified. 1972f62bae50SIngo Molnar */ 1973f62bae50SIngo Molnar if (!force_enable_local_apic) { 1974f62bae50SIngo Molnar pr_info("Local APIC disabled by BIOS -- " 1975f62bae50SIngo Molnar "you can enable it with \"lapic\"\n"); 1976f62bae50SIngo Molnar return -1; 1977f62bae50SIngo Molnar } 1978a906fdaaSThomas Gleixner if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) 19795a7ae78fSThomas Gleixner return -1; 19805a7ae78fSThomas Gleixner } else { 19815a7ae78fSThomas Gleixner if (apic_verify()) 1982f62bae50SIngo Molnar return -1; 1983f62bae50SIngo Molnar } 1984f62bae50SIngo Molnar 1985f62bae50SIngo Molnar apic_pm_activate(); 1986f62bae50SIngo Molnar 1987f62bae50SIngo Molnar return 0; 1988f62bae50SIngo Molnar 1989f62bae50SIngo Molnar no_apic: 1990f62bae50SIngo Molnar pr_info("No local APIC present or hardware disabled\n"); 1991f62bae50SIngo Molnar return -1; 1992f62bae50SIngo Molnar } 1993f62bae50SIngo Molnar #endif 1994f62bae50SIngo Molnar 1995f62bae50SIngo Molnar /** 1996f62bae50SIngo Molnar * init_apic_mappings - initialize APIC mappings 1997f62bae50SIngo Molnar */ 1998f62bae50SIngo Molnar void __init init_apic_mappings(void) 1999f62bae50SIngo Molnar { 20004401da61SYinghai Lu unsigned int new_apicid; 20014401da61SYinghai Lu 2002bd9240a1SPeter Zijlstra apic_check_deadline_errata(); 2003bd9240a1SPeter Zijlstra 2004fc1edaf9SSuresh Siddha if (x2apic_mode) { 2005f62bae50SIngo Molnar boot_cpu_physical_apicid = read_apic_id(); 2006f62bae50SIngo Molnar return; 2007f62bae50SIngo Molnar } 2008f62bae50SIngo Molnar 20094797f6b0SYinghai Lu /* If no local APIC can be found return early */ 2010f62bae50SIngo Molnar if (!smp_found_config && detect_init_APIC()) { 20114797f6b0SYinghai Lu /* lets NOP'ify apic operations */ 20124797f6b0SYinghai Lu pr_info("APIC: disable apic facility\n"); 20134797f6b0SYinghai Lu apic_disable(); 20144797f6b0SYinghai Lu } else { 2015f62bae50SIngo Molnar apic_phys = mp_lapic_addr; 2016f62bae50SIngo Molnar 20174401da61SYinghai Lu /* 20185ba039a5SDou Liyang * If the system has ACPI MADT tables or MP info, the LAPIC 20195ba039a5SDou Liyang * address is already registered. 20204401da61SYinghai Lu */ 20215989cd6aSEric W. Biederman if (!acpi_lapic && !smp_found_config) 2022326a2e6bSYinghai Lu register_lapic_address(apic_phys); 2023cec6be6dSCyrill Gorcunov } 2024f62bae50SIngo Molnar 2025f62bae50SIngo Molnar /* 2026f62bae50SIngo Molnar * Fetch the APIC ID of the BSP in case we have a 2027f62bae50SIngo Molnar * default configuration (or the MP table is broken). 2028f62bae50SIngo Molnar */ 20294401da61SYinghai Lu new_apicid = read_apic_id(); 20304401da61SYinghai Lu if (boot_cpu_physical_apicid != new_apicid) { 20314401da61SYinghai Lu boot_cpu_physical_apicid = new_apicid; 2032103428e5SCyrill Gorcunov /* 2033103428e5SCyrill Gorcunov * yeah -- we lie about apic_version 2034103428e5SCyrill Gorcunov * in case if apic was disabled via boot option 2035103428e5SCyrill Gorcunov * but it's not a problem for SMP compiled kernel 20364f45ed9fSDou Liyang * since apic_intr_mode_select is prepared for such 20374f45ed9fSDou Liyang * a case and disable smp mode 2038103428e5SCyrill Gorcunov */ 2039cff9ab2bSDenys Vlasenko boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 204008306ce6SCyrill Gorcunov } 2041f62bae50SIngo Molnar } 2042f62bae50SIngo Molnar 2043c0104d38SYinghai Lu void __init register_lapic_address(unsigned long address) 2044c0104d38SYinghai Lu { 2045c0104d38SYinghai Lu mp_lapic_addr = address; 2046c0104d38SYinghai Lu 20470450193bSYinghai Lu if (!x2apic_mode) { 2048c0104d38SYinghai Lu set_fixmap_nocache(FIX_APIC_BASE, address); 2049f1157141SYinghai Lu apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 20506de42119SBaoquan He APIC_BASE, address); 20510450193bSYinghai Lu } 2052c0104d38SYinghai Lu if (boot_cpu_physical_apicid == -1U) { 2053c0104d38SYinghai Lu boot_cpu_physical_apicid = read_apic_id(); 2054cff9ab2bSDenys Vlasenko boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 2055c0104d38SYinghai Lu } 2056c0104d38SYinghai Lu } 2057c0104d38SYinghai Lu 2058f62bae50SIngo Molnar /* 2059f62bae50SIngo Molnar * Local APIC interrupts 2060f62bae50SIngo Molnar */ 2061f62bae50SIngo Molnar 2062f62bae50SIngo Molnar /* 2063f62bae50SIngo Molnar * This interrupt should _never_ happen with our APIC/SMP architecture 2064f62bae50SIngo Molnar */ 206561069de7SThomas Gleixner __visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs) 2066f62bae50SIngo Molnar { 206761069de7SThomas Gleixner u8 vector = ~regs->orig_ax; 2068f62bae50SIngo Molnar u32 v; 2069f62bae50SIngo Molnar 207061069de7SThomas Gleixner entering_irq(); 207161069de7SThomas Gleixner trace_spurious_apic_entry(vector); 207261069de7SThomas Gleixner 2073f62bae50SIngo Molnar inc_irq_stat(irq_spurious_count); 2074f62bae50SIngo Molnar 2075f8a8fe61SThomas Gleixner /* 2076f8a8fe61SThomas Gleixner * If this is a spurious interrupt then do not acknowledge 2077f8a8fe61SThomas Gleixner */ 2078f8a8fe61SThomas Gleixner if (vector == SPURIOUS_APIC_VECTOR) { 2079f8a8fe61SThomas Gleixner /* See SDM vol 3 */ 2080f8a8fe61SThomas Gleixner pr_info("Spurious APIC interrupt (vector 0xFF) on CPU#%d, should never happen.\n", 2081f8a8fe61SThomas Gleixner smp_processor_id()); 2082f8a8fe61SThomas Gleixner goto out; 2083f8a8fe61SThomas Gleixner } 2084eddc0e92SSeiji Aguchi 2085f8a8fe61SThomas Gleixner /* 2086f8a8fe61SThomas Gleixner * If it is a vectored one, verify it's set in the ISR. If set, 2087f8a8fe61SThomas Gleixner * acknowledge it. 2088f8a8fe61SThomas Gleixner */ 2089f8a8fe61SThomas Gleixner v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); 2090f8a8fe61SThomas Gleixner if (v & (1 << (vector & 0x1f))) { 2091f8a8fe61SThomas Gleixner pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Acked\n", 2092f8a8fe61SThomas Gleixner vector, smp_processor_id()); 2093f8a8fe61SThomas Gleixner ack_APIC_irq(); 2094f8a8fe61SThomas Gleixner } else { 2095f8a8fe61SThomas Gleixner pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Not pending!\n", 2096f8a8fe61SThomas Gleixner vector, smp_processor_id()); 2097f8a8fe61SThomas Gleixner } 2098f8a8fe61SThomas Gleixner out: 20992414e021SJan Beulich trace_spurious_apic_exit(vector); 2100cf910e83SSeiji Aguchi exiting_irq(); 2101f62bae50SIngo Molnar } 2102f62bae50SIngo Molnar 2103f62bae50SIngo Molnar /* 2104f62bae50SIngo Molnar * This interrupt should never happen with our APIC/SMP architecture 2105f62bae50SIngo Molnar */ 210661069de7SThomas Gleixner __visible void __irq_entry smp_error_interrupt(struct pt_regs *regs) 2107f62bae50SIngo Molnar { 21082b398bd9SYouquan Song static const char * const error_interrupt_reason[] = { 21092b398bd9SYouquan Song "Send CS error", /* APIC Error Bit 0 */ 21102b398bd9SYouquan Song "Receive CS error", /* APIC Error Bit 1 */ 21112b398bd9SYouquan Song "Send accept error", /* APIC Error Bit 2 */ 21122b398bd9SYouquan Song "Receive accept error", /* APIC Error Bit 3 */ 21132b398bd9SYouquan Song "Redirectable IPI", /* APIC Error Bit 4 */ 21142b398bd9SYouquan Song "Send illegal vector", /* APIC Error Bit 5 */ 21152b398bd9SYouquan Song "Received illegal vector", /* APIC Error Bit 6 */ 21162b398bd9SYouquan Song "Illegal register address", /* APIC Error Bit 7 */ 21172b398bd9SYouquan Song }; 211861069de7SThomas Gleixner u32 v, i = 0; 211961069de7SThomas Gleixner 212061069de7SThomas Gleixner entering_irq(); 212161069de7SThomas Gleixner trace_error_apic_entry(ERROR_APIC_VECTOR); 2122f62bae50SIngo Molnar 2123f62bae50SIngo Molnar /* First tickle the hardware, only then report what went on. -- REW */ 2124023de4a0SMaciej W. Rozycki if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ 2125f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 212660283df7SRichard Weinberger v = apic_read(APIC_ESR); 2127f62bae50SIngo Molnar ack_APIC_irq(); 2128f62bae50SIngo Molnar atomic_inc(&irq_err_count); 2129f62bae50SIngo Molnar 213060283df7SRichard Weinberger apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", 213160283df7SRichard Weinberger smp_processor_id(), v); 21322b398bd9SYouquan Song 213360283df7SRichard Weinberger v &= 0xff; 213460283df7SRichard Weinberger while (v) { 213560283df7SRichard Weinberger if (v & 0x1) 21362b398bd9SYouquan Song apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); 21372b398bd9SYouquan Song i++; 213860283df7SRichard Weinberger v >>= 1; 21394b8073e4SPeter Senna Tschudin } 21402b398bd9SYouquan Song 21412b398bd9SYouquan Song apic_printk(APIC_DEBUG, KERN_CONT "\n"); 21422b398bd9SYouquan Song 2143cf910e83SSeiji Aguchi trace_error_apic_exit(ERROR_APIC_VECTOR); 2144cf910e83SSeiji Aguchi exiting_irq(); 2145f62bae50SIngo Molnar } 2146f62bae50SIngo Molnar 2147f62bae50SIngo Molnar /** 2148f62bae50SIngo Molnar * connect_bsp_APIC - attach the APIC to the interrupt system 2149f62bae50SIngo Molnar */ 215005f7e46dSThomas Gleixner static void __init connect_bsp_APIC(void) 2151f62bae50SIngo Molnar { 2152f62bae50SIngo Molnar #ifdef CONFIG_X86_32 2153f62bae50SIngo Molnar if (pic_mode) { 2154f62bae50SIngo Molnar /* 2155f62bae50SIngo Molnar * Do not trust the local APIC being empty at bootup. 2156f62bae50SIngo Molnar */ 2157f62bae50SIngo Molnar clear_local_APIC(); 2158f62bae50SIngo Molnar /* 2159f62bae50SIngo Molnar * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 2160f62bae50SIngo Molnar * local APIC to INT and NMI lines. 2161f62bae50SIngo Molnar */ 2162f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "leaving PIC mode, " 2163f62bae50SIngo Molnar "enabling APIC mode.\n"); 2164c0eaa453SCyrill Gorcunov imcr_pic_to_apic(); 2165f62bae50SIngo Molnar } 2166f62bae50SIngo Molnar #endif 2167f62bae50SIngo Molnar } 2168f62bae50SIngo Molnar 2169f62bae50SIngo Molnar /** 2170f62bae50SIngo Molnar * disconnect_bsp_APIC - detach the APIC from the interrupt system 2171f62bae50SIngo Molnar * @virt_wire_setup: indicates, whether virtual wire mode is selected 2172f62bae50SIngo Molnar * 2173f62bae50SIngo Molnar * Virtual wire mode is necessary to deliver legacy interrupts even when the 2174f62bae50SIngo Molnar * APIC is disabled. 2175f62bae50SIngo Molnar */ 2176f62bae50SIngo Molnar void disconnect_bsp_APIC(int virt_wire_setup) 2177f62bae50SIngo Molnar { 2178f62bae50SIngo Molnar unsigned int value; 2179f62bae50SIngo Molnar 2180f62bae50SIngo Molnar #ifdef CONFIG_X86_32 2181f62bae50SIngo Molnar if (pic_mode) { 2182f62bae50SIngo Molnar /* 2183f62bae50SIngo Molnar * Put the board back into PIC mode (has an effect only on 2184f62bae50SIngo Molnar * certain older boards). Note that APIC interrupts, including 2185f62bae50SIngo Molnar * IPIs, won't work beyond this point! The only exception are 2186f62bae50SIngo Molnar * INIT IPIs. 2187f62bae50SIngo Molnar */ 2188f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "disabling APIC mode, " 2189f62bae50SIngo Molnar "entering PIC mode.\n"); 2190c0eaa453SCyrill Gorcunov imcr_apic_to_pic(); 2191f62bae50SIngo Molnar return; 2192f62bae50SIngo Molnar } 2193f62bae50SIngo Molnar #endif 2194f62bae50SIngo Molnar 2195f62bae50SIngo Molnar /* Go back to Virtual Wire compatibility mode */ 2196f62bae50SIngo Molnar 2197f62bae50SIngo Molnar /* For the spurious interrupt use vector F, and enable it */ 2198f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 2199f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 2200f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 2201f62bae50SIngo Molnar value |= 0xf; 2202f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 2203f62bae50SIngo Molnar 2204f62bae50SIngo Molnar if (!virt_wire_setup) { 2205f62bae50SIngo Molnar /* 2206f62bae50SIngo Molnar * For LVT0 make it edge triggered, active high, 2207f62bae50SIngo Molnar * external and enabled 2208f62bae50SIngo Molnar */ 2209f62bae50SIngo Molnar value = apic_read(APIC_LVT0); 2210f62bae50SIngo Molnar value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2211f62bae50SIngo Molnar APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2212f62bae50SIngo Molnar APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2213f62bae50SIngo Molnar value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2214f62bae50SIngo Molnar value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 2215f62bae50SIngo Molnar apic_write(APIC_LVT0, value); 2216f62bae50SIngo Molnar } else { 2217f62bae50SIngo Molnar /* Disable LVT0 */ 2218f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_LVT_MASKED); 2219f62bae50SIngo Molnar } 2220f62bae50SIngo Molnar 2221f62bae50SIngo Molnar /* 2222f62bae50SIngo Molnar * For LVT1 make it edge triggered, active high, 2223f62bae50SIngo Molnar * nmi and enabled 2224f62bae50SIngo Molnar */ 2225f62bae50SIngo Molnar value = apic_read(APIC_LVT1); 2226f62bae50SIngo Molnar value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2227f62bae50SIngo Molnar APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2228f62bae50SIngo Molnar APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2229f62bae50SIngo Molnar value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2230f62bae50SIngo Molnar value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 2231f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 2232f62bae50SIngo Molnar } 2233f62bae50SIngo Molnar 22348f54969dSGu Zheng /* 22358f54969dSGu Zheng * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated 22368f54969dSGu Zheng * contiguously, it equals to current allocated max logical CPU ID plus 1. 223712bf98b9SDou Liyang * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range, 223812bf98b9SDou Liyang * so the maximum of nr_logical_cpuids is nr_cpu_ids. 22398f54969dSGu Zheng * 22408f54969dSGu Zheng * NOTE: Reserve 0 for BSP. 22418f54969dSGu Zheng */ 22428f54969dSGu Zheng static int nr_logical_cpuids = 1; 22438f54969dSGu Zheng 22448f54969dSGu Zheng /* 22458f54969dSGu Zheng * Used to store mapping between logical CPU IDs and APIC IDs. 22468f54969dSGu Zheng */ 22478f54969dSGu Zheng static int cpuid_to_apicid[] = { 22488f54969dSGu Zheng [0 ... NR_CPUS - 1] = -1, 22498f54969dSGu Zheng }; 22508f54969dSGu Zheng 2251d0055f35SVlastimil Babka #ifdef CONFIG_SMP 22526a4d2657SThomas Gleixner /** 22536a4d2657SThomas Gleixner * apic_id_is_primary_thread - Check whether APIC ID belongs to a primary thread 22546a4d2657SThomas Gleixner * @id: APIC ID to check 22556a4d2657SThomas Gleixner */ 22566a4d2657SThomas Gleixner bool apic_id_is_primary_thread(unsigned int apicid) 22576a4d2657SThomas Gleixner { 22586a4d2657SThomas Gleixner u32 mask; 22596a4d2657SThomas Gleixner 22606a4d2657SThomas Gleixner if (smp_num_siblings == 1) 22616a4d2657SThomas Gleixner return true; 22626a4d2657SThomas Gleixner /* Isolate the SMT bit(s) in the APICID and check for 0 */ 22636a4d2657SThomas Gleixner mask = (1U << (fls(smp_num_siblings) - 1)) - 1; 22646a4d2657SThomas Gleixner return !(apicid & mask); 22656a4d2657SThomas Gleixner } 2266d0055f35SVlastimil Babka #endif 22676a4d2657SThomas Gleixner 22688f54969dSGu Zheng /* 22698f54969dSGu Zheng * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids 22708f54969dSGu Zheng * and cpuid_to_apicid[] synchronized. 22718f54969dSGu Zheng */ 22728f54969dSGu Zheng static int allocate_logical_cpuid(int apicid) 22738f54969dSGu Zheng { 22748f54969dSGu Zheng int i; 22758f54969dSGu Zheng 22768f54969dSGu Zheng /* 22778f54969dSGu Zheng * cpuid <-> apicid mapping is persistent, so when a cpu is up, 22788f54969dSGu Zheng * check if the kernel has allocated a cpuid for it. 22798f54969dSGu Zheng */ 22808f54969dSGu Zheng for (i = 0; i < nr_logical_cpuids; i++) { 22818f54969dSGu Zheng if (cpuid_to_apicid[i] == apicid) 22828f54969dSGu Zheng return i; 22838f54969dSGu Zheng } 22848f54969dSGu Zheng 22858f54969dSGu Zheng /* Allocate a new cpuid. */ 22868f54969dSGu Zheng if (nr_logical_cpuids >= nr_cpu_ids) { 22879b130ad5SAlexey Dobriyan WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. " 22888f54969dSGu Zheng "Processor %d/0x%x and the rest are ignored.\n", 2289bb3f0a52SDou Liyang nr_cpu_ids, nr_logical_cpuids, apicid); 2290bb3f0a52SDou Liyang return -EINVAL; 22918f54969dSGu Zheng } 22928f54969dSGu Zheng 22938f54969dSGu Zheng cpuid_to_apicid[nr_logical_cpuids] = apicid; 22948f54969dSGu Zheng return nr_logical_cpuids++; 22958f54969dSGu Zheng } 22968f54969dSGu Zheng 22972b85b3d2SDou Liyang int generic_processor_info(int apicid, int version) 2298f62bae50SIngo Molnar { 229914cb6dcfSVivek Goyal int cpu, max = nr_cpu_ids; 230014cb6dcfSVivek Goyal bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, 230114cb6dcfSVivek Goyal phys_cpu_present_map); 230214cb6dcfSVivek Goyal 230314cb6dcfSVivek Goyal /* 2304151e0c7dSHATAYAMA Daisuke * boot_cpu_physical_apicid is designed to have the apicid 2305151e0c7dSHATAYAMA Daisuke * returned by read_apic_id(), i.e, the apicid of the 2306151e0c7dSHATAYAMA Daisuke * currently booting-up processor. However, on some platforms, 23075b4d1dbcSH. Peter Anvin * it is temporarily modified by the apicid reported as BSP 2308151e0c7dSHATAYAMA Daisuke * through MP table. Concretely: 2309151e0c7dSHATAYAMA Daisuke * 2310151e0c7dSHATAYAMA Daisuke * - arch/x86/kernel/mpparse.c: MP_processor_info() 2311151e0c7dSHATAYAMA Daisuke * - arch/x86/mm/amdtopology.c: amd_numa_init() 2312151e0c7dSHATAYAMA Daisuke * 2313151e0c7dSHATAYAMA Daisuke * This function is executed with the modified 2314151e0c7dSHATAYAMA Daisuke * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel 2315151e0c7dSHATAYAMA Daisuke * parameter doesn't work to disable APs on kdump 2nd kernel. 2316151e0c7dSHATAYAMA Daisuke * 2317151e0c7dSHATAYAMA Daisuke * Since fixing handling of boot_cpu_physical_apicid requires 2318151e0c7dSHATAYAMA Daisuke * another discussion and tests on each platform, we leave it 2319151e0c7dSHATAYAMA Daisuke * for now and here we use read_apic_id() directly in this 2320e2329b42SDou Liyang * function, generic_processor_info(). 2321151e0c7dSHATAYAMA Daisuke */ 2322151e0c7dSHATAYAMA Daisuke if (disabled_cpu_apicid != BAD_APICID && 2323151e0c7dSHATAYAMA Daisuke disabled_cpu_apicid != read_apic_id() && 2324151e0c7dSHATAYAMA Daisuke disabled_cpu_apicid == apicid) { 2325151e0c7dSHATAYAMA Daisuke int thiscpu = num_processors + disabled_cpus; 2326151e0c7dSHATAYAMA Daisuke 23275b4d1dbcSH. Peter Anvin pr_warning("APIC: Disabling requested cpu." 2328151e0c7dSHATAYAMA Daisuke " Processor %d/0x%x ignored.\n", 2329151e0c7dSHATAYAMA Daisuke thiscpu, apicid); 2330151e0c7dSHATAYAMA Daisuke 2331151e0c7dSHATAYAMA Daisuke disabled_cpus++; 2332151e0c7dSHATAYAMA Daisuke return -ENODEV; 2333151e0c7dSHATAYAMA Daisuke } 2334151e0c7dSHATAYAMA Daisuke 2335151e0c7dSHATAYAMA Daisuke /* 233614cb6dcfSVivek Goyal * If boot cpu has not been detected yet, then only allow upto 233714cb6dcfSVivek Goyal * nr_cpu_ids - 1 processors and keep one slot free for boot cpu 233814cb6dcfSVivek Goyal */ 233914cb6dcfSVivek Goyal if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && 234014cb6dcfSVivek Goyal apicid != boot_cpu_physical_apicid) { 234114cb6dcfSVivek Goyal int thiscpu = max + disabled_cpus - 1; 234214cb6dcfSVivek Goyal 234314cb6dcfSVivek Goyal pr_warning( 23443c8fad91SClaudio Fontana "APIC: NR_CPUS/possible_cpus limit of %i almost" 234514cb6dcfSVivek Goyal " reached. Keeping one slot for boot cpu." 234614cb6dcfSVivek Goyal " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 234714cb6dcfSVivek Goyal 234814cb6dcfSVivek Goyal disabled_cpus++; 23497e1f85f9SJiang Liu return -ENODEV; 235014cb6dcfSVivek Goyal } 2351f62bae50SIngo Molnar 2352f62bae50SIngo Molnar if (num_processors >= nr_cpu_ids) { 2353f62bae50SIngo Molnar int thiscpu = max + disabled_cpus; 2354f62bae50SIngo Molnar 2355df610d67SThomas Gleixner pr_warning("APIC: NR_CPUS/possible_cpus limit of %i " 2356df610d67SThomas Gleixner "reached. Processor %d/0x%x ignored.\n", 2357df610d67SThomas Gleixner max, thiscpu, apicid); 2358f62bae50SIngo Molnar 2359f62bae50SIngo Molnar disabled_cpus++; 23607e1f85f9SJiang Liu return -EINVAL; 2361f62bae50SIngo Molnar } 2362f62bae50SIngo Molnar 2363f62bae50SIngo Molnar if (apicid == boot_cpu_physical_apicid) { 2364f62bae50SIngo Molnar /* 2365f62bae50SIngo Molnar * x86_bios_cpu_apicid is required to have processors listed 2366f62bae50SIngo Molnar * in same order as logical cpu numbers. Hence the first 2367f62bae50SIngo Molnar * entry is BSP, and so on. 2368e5fea868SYinghai Lu * boot_cpu_init() already hold bit 0 in cpu_present_mask 2369e5fea868SYinghai Lu * for BSP. 2370f62bae50SIngo Molnar */ 2371f62bae50SIngo Molnar cpu = 0; 23728f54969dSGu Zheng 23738f54969dSGu Zheng /* Logical cpuid 0 is reserved for BSP. */ 23748f54969dSGu Zheng cpuid_to_apicid[0] = apicid; 23758f54969dSGu Zheng } else { 23768f54969dSGu Zheng cpu = allocate_logical_cpuid(apicid); 23778f54969dSGu Zheng if (cpu < 0) { 23788f54969dSGu Zheng disabled_cpus++; 23798f54969dSGu Zheng return -EINVAL; 23808f54969dSGu Zheng } 23818f54969dSGu Zheng } 2382e5fea868SYinghai Lu 2383e5fea868SYinghai Lu /* 2384e5fea868SYinghai Lu * Validate version 2385e5fea868SYinghai Lu */ 2386e5fea868SYinghai Lu if (version == 0x0) { 2387e5fea868SYinghai Lu pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", 2388e5fea868SYinghai Lu cpu, apicid); 2389e5fea868SYinghai Lu version = 0x10; 2390f62bae50SIngo Molnar } 2391e5fea868SYinghai Lu 2392cff9ab2bSDenys Vlasenko if (version != boot_cpu_apic_version) { 2393e5fea868SYinghai Lu pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", 2394cff9ab2bSDenys Vlasenko boot_cpu_apic_version, cpu, version); 2395e5fea868SYinghai Lu } 2396e5fea868SYinghai Lu 2397f62bae50SIngo Molnar if (apicid > max_physical_apicid) 2398f62bae50SIngo Molnar max_physical_apicid = apicid; 2399f62bae50SIngo Molnar 2400f62bae50SIngo Molnar #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 2401f62bae50SIngo Molnar early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 2402f62bae50SIngo Molnar early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 2403f62bae50SIngo Molnar #endif 2404acb8bc09STejun Heo #ifdef CONFIG_X86_32 2405acb8bc09STejun Heo early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 2406acb8bc09STejun Heo apic->x86_32_early_logical_apicid(cpu); 2407acb8bc09STejun Heo #endif 2408f62bae50SIngo Molnar set_cpu_possible(cpu, true); 2409f7c28833SGu Zheng physid_set(apicid, phys_cpu_present_map); 2410f62bae50SIngo Molnar set_cpu_present(cpu, true); 24112b85b3d2SDou Liyang num_processors++; 24127e1f85f9SJiang Liu 24137e1f85f9SJiang Liu return cpu; 2414f62bae50SIngo Molnar } 2415f62bae50SIngo Molnar 2416f62bae50SIngo Molnar int hard_smp_processor_id(void) 2417f62bae50SIngo Molnar { 2418f62bae50SIngo Molnar return read_apic_id(); 2419f62bae50SIngo Molnar } 2420f62bae50SIngo Molnar 2421f62bae50SIngo Molnar /* 24221551df64SMichael S. Tsirkin * Override the generic EOI implementation with an optimized version. 24231551df64SMichael S. Tsirkin * Only called during early boot when only one CPU is active and with 24241551df64SMichael S. Tsirkin * interrupts disabled, so we know this does not race with actual APIC driver 24251551df64SMichael S. Tsirkin * use. 24261551df64SMichael S. Tsirkin */ 24271551df64SMichael S. Tsirkin void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) 24281551df64SMichael S. Tsirkin { 24291551df64SMichael S. Tsirkin struct apic **drv; 24301551df64SMichael S. Tsirkin 24311551df64SMichael S. Tsirkin for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { 24321551df64SMichael S. Tsirkin /* Should happen once for each apic */ 24331551df64SMichael S. Tsirkin WARN_ON((*drv)->eoi_write == eoi_write); 24348ca22552SWanpeng Li (*drv)->native_eoi_write = (*drv)->eoi_write; 24351551df64SMichael S. Tsirkin (*drv)->eoi_write = eoi_write; 24361551df64SMichael S. Tsirkin } 24371551df64SMichael S. Tsirkin } 24381551df64SMichael S. Tsirkin 2439374aab33SThomas Gleixner static void __init apic_bsp_up_setup(void) 244005f7e46dSThomas Gleixner { 2441374aab33SThomas Gleixner #ifdef CONFIG_X86_64 24425d64d209SDou Liyang apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid)); 2443374aab33SThomas Gleixner #else 244405f7e46dSThomas Gleixner /* 2445374aab33SThomas Gleixner * Hack: In case of kdump, after a crash, kernel might be booting 2446374aab33SThomas Gleixner * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 2447374aab33SThomas Gleixner * might be zero if read from MP tables. Get it from LAPIC. 244805f7e46dSThomas Gleixner */ 2449374aab33SThomas Gleixner # ifdef CONFIG_CRASH_DUMP 2450374aab33SThomas Gleixner boot_cpu_physical_apicid = read_apic_id(); 2451374aab33SThomas Gleixner # endif 2452374aab33SThomas Gleixner #endif 2453374aab33SThomas Gleixner physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 245405f7e46dSThomas Gleixner } 245505f7e46dSThomas Gleixner 245605f7e46dSThomas Gleixner /** 245705f7e46dSThomas Gleixner * apic_bsp_setup - Setup function for local apic and io-apic 2458374aab33SThomas Gleixner * @upmode: Force UP mode (for APIC_init_uniprocessor) 245905f7e46dSThomas Gleixner */ 2460748b170cSThomas Gleixner static void __init apic_bsp_setup(bool upmode) 246105f7e46dSThomas Gleixner { 246205f7e46dSThomas Gleixner connect_bsp_APIC(); 2463374aab33SThomas Gleixner if (upmode) 2464374aab33SThomas Gleixner apic_bsp_up_setup(); 246505f7e46dSThomas Gleixner setup_local_APIC(); 246605f7e46dSThomas Gleixner 246705f7e46dSThomas Gleixner enable_IO_APIC(); 2468374aab33SThomas Gleixner end_local_APIC_setup(); 2469374aab33SThomas Gleixner irq_remap_enable_fault_handling(); 247005f7e46dSThomas Gleixner setup_IO_APIC(); 2471e714a91fSThomas Gleixner } 2472e714a91fSThomas Gleixner 247330b8b006SThomas Gleixner #ifdef CONFIG_UP_LATE_INIT 247430b8b006SThomas Gleixner void __init up_late_init(void) 247530b8b006SThomas Gleixner { 24760c759131SDou Liyang if (apic_intr_mode == APIC_PIC) 24770c759131SDou Liyang return; 24780c759131SDou Liyang 24790c759131SDou Liyang /* Setup local timer */ 24800c759131SDou Liyang x86_init.timers.setup_percpu_clockev(); 248130b8b006SThomas Gleixner } 248230b8b006SThomas Gleixner #endif 248330b8b006SThomas Gleixner 2484e714a91fSThomas Gleixner /* 2485f62bae50SIngo Molnar * Power management 2486f62bae50SIngo Molnar */ 2487f62bae50SIngo Molnar #ifdef CONFIG_PM 2488f62bae50SIngo Molnar 2489f62bae50SIngo Molnar static struct { 2490f62bae50SIngo Molnar /* 2491f62bae50SIngo Molnar * 'active' is true if the local APIC was enabled by us and 2492f62bae50SIngo Molnar * not the BIOS; this signifies that we are also responsible 2493f62bae50SIngo Molnar * for disabling it before entering apm/acpi suspend 2494f62bae50SIngo Molnar */ 2495f62bae50SIngo Molnar int active; 2496f62bae50SIngo Molnar /* r/w apic fields */ 2497f62bae50SIngo Molnar unsigned int apic_id; 2498f62bae50SIngo Molnar unsigned int apic_taskpri; 2499f62bae50SIngo Molnar unsigned int apic_ldr; 2500f62bae50SIngo Molnar unsigned int apic_dfr; 2501f62bae50SIngo Molnar unsigned int apic_spiv; 2502f62bae50SIngo Molnar unsigned int apic_lvtt; 2503f62bae50SIngo Molnar unsigned int apic_lvtpc; 2504f62bae50SIngo Molnar unsigned int apic_lvt0; 2505f62bae50SIngo Molnar unsigned int apic_lvt1; 2506f62bae50SIngo Molnar unsigned int apic_lvterr; 2507f62bae50SIngo Molnar unsigned int apic_tmict; 2508f62bae50SIngo Molnar unsigned int apic_tdcr; 2509f62bae50SIngo Molnar unsigned int apic_thmr; 251042baa258SJuergen Gross unsigned int apic_cmci; 2511f62bae50SIngo Molnar } apic_pm_state; 2512f62bae50SIngo Molnar 2513f3c6ea1bSRafael J. Wysocki static int lapic_suspend(void) 2514f62bae50SIngo Molnar { 2515f62bae50SIngo Molnar unsigned long flags; 2516f62bae50SIngo Molnar int maxlvt; 2517f62bae50SIngo Molnar 2518f62bae50SIngo Molnar if (!apic_pm_state.active) 2519f62bae50SIngo Molnar return 0; 2520f62bae50SIngo Molnar 2521f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 2522f62bae50SIngo Molnar 2523f62bae50SIngo Molnar apic_pm_state.apic_id = apic_read(APIC_ID); 2524f62bae50SIngo Molnar apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2525f62bae50SIngo Molnar apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2526f62bae50SIngo Molnar apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2527f62bae50SIngo Molnar apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2528f62bae50SIngo Molnar apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2529f62bae50SIngo Molnar if (maxlvt >= 4) 2530f62bae50SIngo Molnar apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2531f62bae50SIngo Molnar apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2532f62bae50SIngo Molnar apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2533f62bae50SIngo Molnar apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2534f62bae50SIngo Molnar apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2535f62bae50SIngo Molnar apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 25364efc0670SAndi Kleen #ifdef CONFIG_X86_THERMAL_VECTOR 2537f62bae50SIngo Molnar if (maxlvt >= 5) 2538f62bae50SIngo Molnar apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2539f62bae50SIngo Molnar #endif 254042baa258SJuergen Gross #ifdef CONFIG_X86_MCE_INTEL 254142baa258SJuergen Gross if (maxlvt >= 6) 254242baa258SJuergen Gross apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI); 254342baa258SJuergen Gross #endif 2544f62bae50SIngo Molnar 2545f62bae50SIngo Molnar local_irq_save(flags); 2546f62bae50SIngo Molnar disable_local_APIC(); 2547fc1edaf9SSuresh Siddha 254895a02e97SSuresh Siddha irq_remapping_disable(); 2549fc1edaf9SSuresh Siddha 2550f62bae50SIngo Molnar local_irq_restore(flags); 2551f62bae50SIngo Molnar return 0; 2552f62bae50SIngo Molnar } 2553f62bae50SIngo Molnar 2554f3c6ea1bSRafael J. Wysocki static void lapic_resume(void) 2555f62bae50SIngo Molnar { 2556f62bae50SIngo Molnar unsigned int l, h; 2557f62bae50SIngo Molnar unsigned long flags; 255831dce14aSSuresh Siddha int maxlvt; 2559b24696bcSFenghua Yu 2560f62bae50SIngo Molnar if (!apic_pm_state.active) 2561f3c6ea1bSRafael J. Wysocki return; 2562f62bae50SIngo Molnar 2563b24696bcSFenghua Yu local_irq_save(flags); 2564336224baSJoerg Roedel 256531dce14aSSuresh Siddha /* 256631dce14aSSuresh Siddha * IO-APIC and PIC have their own resume routines. 256731dce14aSSuresh Siddha * We just mask them here to make sure the interrupt 256831dce14aSSuresh Siddha * subsystem is completely quiet while we enable x2apic 256931dce14aSSuresh Siddha * and interrupt-remapping. 257031dce14aSSuresh Siddha */ 257131dce14aSSuresh Siddha mask_ioapic_entries(); 2572b81bb373SJacob Pan legacy_pic->mask_all(); 2573f62bae50SIngo Molnar 2574659006bfSThomas Gleixner if (x2apic_mode) { 2575659006bfSThomas Gleixner __x2apic_enable(); 2576659006bfSThomas Gleixner } else { 2577f62bae50SIngo Molnar /* 2578f62bae50SIngo Molnar * Make sure the APICBASE points to the right address 2579f62bae50SIngo Molnar * 2580f62bae50SIngo Molnar * FIXME! This will be wrong if we ever support suspend on 2581f62bae50SIngo Molnar * SMP! We'll need to do this as part of the CPU restore! 2582f62bae50SIngo Molnar */ 2583cbf2829bSBryan O'Donoghue if (boot_cpu_data.x86 >= 6) { 2584f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, l, h); 2585f62bae50SIngo Molnar l &= ~MSR_IA32_APICBASE_BASE; 2586f62bae50SIngo Molnar l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2587f62bae50SIngo Molnar wrmsr(MSR_IA32_APICBASE, l, h); 2588f62bae50SIngo Molnar } 2589cbf2829bSBryan O'Donoghue } 2590f62bae50SIngo Molnar 2591b24696bcSFenghua Yu maxlvt = lapic_get_maxlvt(); 2592f62bae50SIngo Molnar apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2593f62bae50SIngo Molnar apic_write(APIC_ID, apic_pm_state.apic_id); 2594f62bae50SIngo Molnar apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2595f62bae50SIngo Molnar apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2596f62bae50SIngo Molnar apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2597f62bae50SIngo Molnar apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2598f62bae50SIngo Molnar apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2599f62bae50SIngo Molnar apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 260042baa258SJuergen Gross #ifdef CONFIG_X86_THERMAL_VECTOR 2601f62bae50SIngo Molnar if (maxlvt >= 5) 2602f62bae50SIngo Molnar apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2603f62bae50SIngo Molnar #endif 260442baa258SJuergen Gross #ifdef CONFIG_X86_MCE_INTEL 260542baa258SJuergen Gross if (maxlvt >= 6) 260642baa258SJuergen Gross apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci); 260742baa258SJuergen Gross #endif 2608f62bae50SIngo Molnar if (maxlvt >= 4) 2609f62bae50SIngo Molnar apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2610f62bae50SIngo Molnar apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2611f62bae50SIngo Molnar apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2612f62bae50SIngo Molnar apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2613f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 2614f62bae50SIngo Molnar apic_read(APIC_ESR); 2615f62bae50SIngo Molnar apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2616f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 2617f62bae50SIngo Molnar apic_read(APIC_ESR); 2618f62bae50SIngo Molnar 261995a02e97SSuresh Siddha irq_remapping_reenable(x2apic_mode); 262031dce14aSSuresh Siddha 2621f62bae50SIngo Molnar local_irq_restore(flags); 2622f62bae50SIngo Molnar } 2623f62bae50SIngo Molnar 2624f62bae50SIngo Molnar /* 2625f62bae50SIngo Molnar * This device has no shutdown method - fully functioning local APICs 2626f62bae50SIngo Molnar * are needed on every CPU up until machine_halt/restart/poweroff. 2627f62bae50SIngo Molnar */ 2628f62bae50SIngo Molnar 2629f3c6ea1bSRafael J. Wysocki static struct syscore_ops lapic_syscore_ops = { 2630f62bae50SIngo Molnar .resume = lapic_resume, 2631f62bae50SIngo Molnar .suspend = lapic_suspend, 2632f62bae50SIngo Molnar }; 2633f62bae50SIngo Molnar 2634148f9bb8SPaul Gortmaker static void apic_pm_activate(void) 2635f62bae50SIngo Molnar { 2636f62bae50SIngo Molnar apic_pm_state.active = 1; 2637f62bae50SIngo Molnar } 2638f62bae50SIngo Molnar 2639f62bae50SIngo Molnar static int __init init_lapic_sysfs(void) 2640f62bae50SIngo Molnar { 2641f62bae50SIngo Molnar /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 264293984fbdSBorislav Petkov if (boot_cpu_has(X86_FEATURE_APIC)) 2643f3c6ea1bSRafael J. Wysocki register_syscore_ops(&lapic_syscore_ops); 2644f62bae50SIngo Molnar 2645f3c6ea1bSRafael J. Wysocki return 0; 2646f62bae50SIngo Molnar } 2647b24696bcSFenghua Yu 2648b24696bcSFenghua Yu /* local apic needs to resume before other devices access its registers. */ 2649b24696bcSFenghua Yu core_initcall(init_lapic_sysfs); 2650f62bae50SIngo Molnar 2651f62bae50SIngo Molnar #else /* CONFIG_PM */ 2652f62bae50SIngo Molnar 2653f62bae50SIngo Molnar static void apic_pm_activate(void) { } 2654f62bae50SIngo Molnar 2655f62bae50SIngo Molnar #endif /* CONFIG_PM */ 2656f62bae50SIngo Molnar 2657f62bae50SIngo Molnar #ifdef CONFIG_X86_64 2658e0e42142SYinghai Lu 2659148f9bb8SPaul Gortmaker static int multi_checked; 2660148f9bb8SPaul Gortmaker static int multi; 2661e0e42142SYinghai Lu 2662148f9bb8SPaul Gortmaker static int set_multi(const struct dmi_system_id *d) 2663e0e42142SYinghai Lu { 2664e0e42142SYinghai Lu if (multi) 2665e0e42142SYinghai Lu return 0; 26666f0aced6SCyrill Gorcunov pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2667e0e42142SYinghai Lu multi = 1; 2668e0e42142SYinghai Lu return 0; 2669e0e42142SYinghai Lu } 2670e0e42142SYinghai Lu 2671148f9bb8SPaul Gortmaker static const struct dmi_system_id multi_dmi_table[] = { 2672e0e42142SYinghai Lu { 2673e0e42142SYinghai Lu .callback = set_multi, 2674e0e42142SYinghai Lu .ident = "IBM System Summit2", 2675e0e42142SYinghai Lu .matches = { 2676e0e42142SYinghai Lu DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2677e0e42142SYinghai Lu DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2678e0e42142SYinghai Lu }, 2679e0e42142SYinghai Lu }, 2680e0e42142SYinghai Lu {} 2681e0e42142SYinghai Lu }; 2682e0e42142SYinghai Lu 2683148f9bb8SPaul Gortmaker static void dmi_check_multi(void) 2684e0e42142SYinghai Lu { 2685e0e42142SYinghai Lu if (multi_checked) 2686e0e42142SYinghai Lu return; 2687e0e42142SYinghai Lu 2688e0e42142SYinghai Lu dmi_check_system(multi_dmi_table); 2689e0e42142SYinghai Lu multi_checked = 1; 2690e0e42142SYinghai Lu } 2691f62bae50SIngo Molnar 2692f62bae50SIngo Molnar /* 2693e0e42142SYinghai Lu * apic_is_clustered_box() -- Check if we can expect good TSC 2694e0e42142SYinghai Lu * 2695e0e42142SYinghai Lu * Thus far, the major user of this is IBM's Summit2 series: 2696e0e42142SYinghai Lu * Clustered boxes may have unsynced TSC problems if they are 2697e0e42142SYinghai Lu * multi-chassis. 2698e0e42142SYinghai Lu * Use DMI to check them 2699f62bae50SIngo Molnar */ 2700148f9bb8SPaul Gortmaker int apic_is_clustered_box(void) 2701e0e42142SYinghai Lu { 2702e0e42142SYinghai Lu dmi_check_multi(); 2703411cf9eeSOren Twaig return multi; 2704f62bae50SIngo Molnar } 2705f62bae50SIngo Molnar #endif 2706f62bae50SIngo Molnar 2707f62bae50SIngo Molnar /* 2708f62bae50SIngo Molnar * APIC command line parameters 2709f62bae50SIngo Molnar */ 2710f62bae50SIngo Molnar static int __init setup_disableapic(char *arg) 2711f62bae50SIngo Molnar { 2712f62bae50SIngo Molnar disable_apic = 1; 2713f62bae50SIngo Molnar setup_clear_cpu_cap(X86_FEATURE_APIC); 2714f62bae50SIngo Molnar return 0; 2715f62bae50SIngo Molnar } 2716f62bae50SIngo Molnar early_param("disableapic", setup_disableapic); 2717f62bae50SIngo Molnar 2718f62bae50SIngo Molnar /* same as disableapic, for compatibility */ 2719f62bae50SIngo Molnar static int __init setup_nolapic(char *arg) 2720f62bae50SIngo Molnar { 2721f62bae50SIngo Molnar return setup_disableapic(arg); 2722f62bae50SIngo Molnar } 2723f62bae50SIngo Molnar early_param("nolapic", setup_nolapic); 2724f62bae50SIngo Molnar 2725f62bae50SIngo Molnar static int __init parse_lapic_timer_c2_ok(char *arg) 2726f62bae50SIngo Molnar { 2727f62bae50SIngo Molnar local_apic_timer_c2_ok = 1; 2728f62bae50SIngo Molnar return 0; 2729f62bae50SIngo Molnar } 2730f62bae50SIngo Molnar early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2731f62bae50SIngo Molnar 2732f62bae50SIngo Molnar static int __init parse_disable_apic_timer(char *arg) 2733f62bae50SIngo Molnar { 2734f62bae50SIngo Molnar disable_apic_timer = 1; 2735f62bae50SIngo Molnar return 0; 2736f62bae50SIngo Molnar } 2737f62bae50SIngo Molnar early_param("noapictimer", parse_disable_apic_timer); 2738f62bae50SIngo Molnar 2739f62bae50SIngo Molnar static int __init parse_nolapic_timer(char *arg) 2740f62bae50SIngo Molnar { 2741f62bae50SIngo Molnar disable_apic_timer = 1; 2742f62bae50SIngo Molnar return 0; 2743f62bae50SIngo Molnar } 2744f62bae50SIngo Molnar early_param("nolapic_timer", parse_nolapic_timer); 2745f62bae50SIngo Molnar 2746f62bae50SIngo Molnar static int __init apic_set_verbosity(char *arg) 2747f62bae50SIngo Molnar { 2748f62bae50SIngo Molnar if (!arg) { 2749f62bae50SIngo Molnar #ifdef CONFIG_X86_64 2750f62bae50SIngo Molnar skip_ioapic_setup = 0; 2751f62bae50SIngo Molnar return 0; 2752f62bae50SIngo Molnar #endif 2753f62bae50SIngo Molnar return -EINVAL; 2754f62bae50SIngo Molnar } 2755f62bae50SIngo Molnar 2756f62bae50SIngo Molnar if (strcmp("debug", arg) == 0) 2757f62bae50SIngo Molnar apic_verbosity = APIC_DEBUG; 2758f62bae50SIngo Molnar else if (strcmp("verbose", arg) == 0) 2759f62bae50SIngo Molnar apic_verbosity = APIC_VERBOSE; 27604fcab669SDou Liyang #ifdef CONFIG_X86_64 2761f62bae50SIngo Molnar else { 2762f62bae50SIngo Molnar pr_warning("APIC Verbosity level %s not recognised" 2763f62bae50SIngo Molnar " use apic=verbose or apic=debug\n", arg); 2764f62bae50SIngo Molnar return -EINVAL; 2765f62bae50SIngo Molnar } 27664fcab669SDou Liyang #endif 2767f62bae50SIngo Molnar 2768f62bae50SIngo Molnar return 0; 2769f62bae50SIngo Molnar } 2770f62bae50SIngo Molnar early_param("apic", apic_set_verbosity); 2771f62bae50SIngo Molnar 2772f62bae50SIngo Molnar static int __init lapic_insert_resource(void) 2773f62bae50SIngo Molnar { 2774f62bae50SIngo Molnar if (!apic_phys) 2775f62bae50SIngo Molnar return -1; 2776f62bae50SIngo Molnar 2777f62bae50SIngo Molnar /* Put local APIC into the resource map. */ 2778f62bae50SIngo Molnar lapic_resource.start = apic_phys; 2779f62bae50SIngo Molnar lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2780f62bae50SIngo Molnar insert_resource(&iomem_resource, &lapic_resource); 2781f62bae50SIngo Molnar 2782f62bae50SIngo Molnar return 0; 2783f62bae50SIngo Molnar } 2784f62bae50SIngo Molnar 2785f62bae50SIngo Molnar /* 27861506c8dcSIngo Molnar * need call insert after e820__reserve_resources() 2787f62bae50SIngo Molnar * that is using request_resource 2788f62bae50SIngo Molnar */ 2789f62bae50SIngo Molnar late_initcall(lapic_insert_resource); 2790151e0c7dSHATAYAMA Daisuke 2791151e0c7dSHATAYAMA Daisuke static int __init apic_set_disabled_cpu_apicid(char *arg) 2792151e0c7dSHATAYAMA Daisuke { 2793151e0c7dSHATAYAMA Daisuke if (!arg || !get_option(&arg, &disabled_cpu_apicid)) 2794151e0c7dSHATAYAMA Daisuke return -EINVAL; 2795151e0c7dSHATAYAMA Daisuke 2796151e0c7dSHATAYAMA Daisuke return 0; 2797151e0c7dSHATAYAMA Daisuke } 2798151e0c7dSHATAYAMA Daisuke early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); 2799b7c4948eSHidehiro Kawai 2800b7c4948eSHidehiro Kawai static int __init apic_set_extnmi(char *arg) 2801b7c4948eSHidehiro Kawai { 2802b7c4948eSHidehiro Kawai if (!arg) 2803b7c4948eSHidehiro Kawai return -EINVAL; 2804b7c4948eSHidehiro Kawai 2805b7c4948eSHidehiro Kawai if (!strncmp("all", arg, 3)) 2806b7c4948eSHidehiro Kawai apic_extnmi = APIC_EXTNMI_ALL; 2807b7c4948eSHidehiro Kawai else if (!strncmp("none", arg, 4)) 2808b7c4948eSHidehiro Kawai apic_extnmi = APIC_EXTNMI_NONE; 2809b7c4948eSHidehiro Kawai else if (!strncmp("bsp", arg, 3)) 2810b7c4948eSHidehiro Kawai apic_extnmi = APIC_EXTNMI_BSP; 2811b7c4948eSHidehiro Kawai else { 2812b7c4948eSHidehiro Kawai pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg); 2813b7c4948eSHidehiro Kawai return -EINVAL; 2814b7c4948eSHidehiro Kawai } 2815b7c4948eSHidehiro Kawai 2816b7c4948eSHidehiro Kawai return 0; 2817b7c4948eSHidehiro Kawai } 2818b7c4948eSHidehiro Kawai early_param("apic_extnmi", apic_set_extnmi); 2819