1f62bae50SIngo Molnar /* 2f62bae50SIngo Molnar * Local APIC handling, local APIC timers 3f62bae50SIngo Molnar * 4f62bae50SIngo Molnar * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 5f62bae50SIngo Molnar * 6f62bae50SIngo Molnar * Fixes 7f62bae50SIngo Molnar * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8f62bae50SIngo Molnar * thanks to Eric Gilmore 9f62bae50SIngo Molnar * and Rolf G. Tews 10f62bae50SIngo Molnar * for testing these extensively. 11f62bae50SIngo Molnar * Maciej W. Rozycki : Various updates and fixes. 12f62bae50SIngo Molnar * Mikael Pettersson : Power Management for UP-APIC. 13f62bae50SIngo Molnar * Pavel Machek and 14f62bae50SIngo Molnar * Mikael Pettersson : PM converted to driver model. 15f62bae50SIngo Molnar */ 16f62bae50SIngo Molnar 17cdd6c482SIngo Molnar #include <linux/perf_event.h> 18f62bae50SIngo Molnar #include <linux/kernel_stat.h> 19f62bae50SIngo Molnar #include <linux/mc146818rtc.h> 20f62bae50SIngo Molnar #include <linux/acpi_pmtmr.h> 21f62bae50SIngo Molnar #include <linux/clockchips.h> 22f62bae50SIngo Molnar #include <linux/interrupt.h> 23f62bae50SIngo Molnar #include <linux/bootmem.h> 24f62bae50SIngo Molnar #include <linux/ftrace.h> 25f62bae50SIngo Molnar #include <linux/ioport.h> 26186f4360SPaul Gortmaker #include <linux/export.h> 27f3c6ea1bSRafael J. Wysocki #include <linux/syscore_ops.h> 28f62bae50SIngo Molnar #include <linux/delay.h> 29f62bae50SIngo Molnar #include <linux/timex.h> 30334955efSRalf Baechle #include <linux/i8253.h> 31f62bae50SIngo Molnar #include <linux/dmar.h> 32f62bae50SIngo Molnar #include <linux/init.h> 33f62bae50SIngo Molnar #include <linux/cpu.h> 34f62bae50SIngo Molnar #include <linux/dmi.h> 35f62bae50SIngo Molnar #include <linux/smp.h> 36f62bae50SIngo Molnar #include <linux/mm.h> 37f62bae50SIngo Molnar 3883ab8514SSteven Rostedt (Red Hat) #include <asm/trace/irq_vectors.h> 398a8f422dSSuresh Siddha #include <asm/irq_remapping.h> 40cdd6c482SIngo Molnar #include <asm/perf_event.h> 41736decacSThomas Gleixner #include <asm/x86_init.h> 42f62bae50SIngo Molnar #include <asm/pgalloc.h> 4360063497SArun Sharma #include <linux/atomic.h> 44f62bae50SIngo Molnar #include <asm/mpspec.h> 45f62bae50SIngo Molnar #include <asm/i8259.h> 46f62bae50SIngo Molnar #include <asm/proto.h> 47f62bae50SIngo Molnar #include <asm/apic.h> 487167d08eSHenrik Kretzschmar #include <asm/io_apic.h> 49f62bae50SIngo Molnar #include <asm/desc.h> 50f62bae50SIngo Molnar #include <asm/hpet.h> 51f62bae50SIngo Molnar #include <asm/mtrr.h> 5216f871bcSRalf Baechle #include <asm/time.h> 53f62bae50SIngo Molnar #include <asm/smp.h> 54638bee71SH. Peter Anvin #include <asm/mce.h> 558c3ba8d0SKerstin Jonsson #include <asm/tsc.h> 562904ed8dSSheng Yang #include <asm/hypervisor.h> 57bd9240a1SPeter Zijlstra #include <asm/cpu_device_id.h> 58bd9240a1SPeter Zijlstra #include <asm/intel-family.h> 59f62bae50SIngo Molnar 60f62bae50SIngo Molnar unsigned int num_processors; 61f62bae50SIngo Molnar 62148f9bb8SPaul Gortmaker unsigned disabled_cpus; 63f62bae50SIngo Molnar 64f62bae50SIngo Molnar /* Processor that is doing the boot up */ 65f62bae50SIngo Molnar unsigned int boot_cpu_physical_apicid = -1U; 66cc08e04cSDavid Rientjes EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); 67f62bae50SIngo Molnar 68cff9ab2bSDenys Vlasenko u8 boot_cpu_apic_version; 69cff9ab2bSDenys Vlasenko 70f62bae50SIngo Molnar /* 71f62bae50SIngo Molnar * The highest APIC ID seen during enumeration. 72f62bae50SIngo Molnar */ 73a491cc90SJiang Liu static unsigned int max_physical_apicid; 74f62bae50SIngo Molnar 75f62bae50SIngo Molnar /* 76f62bae50SIngo Molnar * Bitmask of physically existing CPUs: 77f62bae50SIngo Molnar */ 78f62bae50SIngo Molnar physid_mask_t phys_cpu_present_map; 79f62bae50SIngo Molnar 80f62bae50SIngo Molnar /* 81151e0c7dSHATAYAMA Daisuke * Processor to be disabled specified by kernel parameter 82151e0c7dSHATAYAMA Daisuke * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to 83151e0c7dSHATAYAMA Daisuke * avoid undefined behaviour caused by sending INIT from AP to BSP. 84151e0c7dSHATAYAMA Daisuke */ 855b4d1dbcSH. Peter Anvin static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID; 86151e0c7dSHATAYAMA Daisuke 87151e0c7dSHATAYAMA Daisuke /* 88b7c4948eSHidehiro Kawai * This variable controls which CPUs receive external NMIs. By default, 89b7c4948eSHidehiro Kawai * external NMIs are delivered only to the BSP. 90b7c4948eSHidehiro Kawai */ 91b7c4948eSHidehiro Kawai static int apic_extnmi = APIC_EXTNMI_BSP; 92b7c4948eSHidehiro Kawai 93b7c4948eSHidehiro Kawai /* 94f62bae50SIngo Molnar * Map cpu index to physical APIC ID 95f62bae50SIngo Molnar */ 960816b0f0SVlad Zolotarov DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); 970816b0f0SVlad Zolotarov DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); 983e9e57faSVitaly Kuznetsov DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX); 99f62bae50SIngo Molnar EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 100f62bae50SIngo Molnar EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 1013e9e57faSVitaly Kuznetsov EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); 102f62bae50SIngo Molnar 103f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1044c321ff8STejun Heo 1054c321ff8STejun Heo /* 1064c321ff8STejun Heo * On x86_32, the mapping between cpu and logical apicid may vary 1074c321ff8STejun Heo * depending on apic in use. The following early percpu variable is 1084c321ff8STejun Heo * used for the mapping. This is where the behaviors of x86_64 and 32 1094c321ff8STejun Heo * actually diverge. Let's keep it ugly for now. 1104c321ff8STejun Heo */ 1110816b0f0SVlad Zolotarov DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); 1124c321ff8STejun Heo 113f62bae50SIngo Molnar /* Local APIC was disabled by the BIOS and enabled by the kernel */ 114f62bae50SIngo Molnar static int enabled_via_apicbase; 115f62bae50SIngo Molnar 116c0eaa453SCyrill Gorcunov /* 117c0eaa453SCyrill Gorcunov * Handle interrupt mode configuration register (IMCR). 118c0eaa453SCyrill Gorcunov * This register controls whether the interrupt signals 119c0eaa453SCyrill Gorcunov * that reach the BSP come from the master PIC or from the 120c0eaa453SCyrill Gorcunov * local APIC. Before entering Symmetric I/O Mode, either 121c0eaa453SCyrill Gorcunov * the BIOS or the operating system must switch out of 122c0eaa453SCyrill Gorcunov * PIC Mode by changing the IMCR. 123c0eaa453SCyrill Gorcunov */ 1245cda395fSAlexander van Heukelum static inline void imcr_pic_to_apic(void) 125c0eaa453SCyrill Gorcunov { 126c0eaa453SCyrill Gorcunov /* select IMCR register */ 127c0eaa453SCyrill Gorcunov outb(0x70, 0x22); 128c0eaa453SCyrill Gorcunov /* NMI and 8259 INTR go through APIC */ 129c0eaa453SCyrill Gorcunov outb(0x01, 0x23); 130c0eaa453SCyrill Gorcunov } 131c0eaa453SCyrill Gorcunov 1325cda395fSAlexander van Heukelum static inline void imcr_apic_to_pic(void) 133c0eaa453SCyrill Gorcunov { 134c0eaa453SCyrill Gorcunov /* select IMCR register */ 135c0eaa453SCyrill Gorcunov outb(0x70, 0x22); 136c0eaa453SCyrill Gorcunov /* NMI and 8259 INTR go directly to BSP */ 137c0eaa453SCyrill Gorcunov outb(0x00, 0x23); 138c0eaa453SCyrill Gorcunov } 139f62bae50SIngo Molnar #endif 140f62bae50SIngo Molnar 141279f1461SSuresh Siddha /* 142279f1461SSuresh Siddha * Knob to control our willingness to enable the local APIC. 143279f1461SSuresh Siddha * 144279f1461SSuresh Siddha * +1=force-enable 145279f1461SSuresh Siddha */ 146279f1461SSuresh Siddha static int force_enable_local_apic __initdata; 147dc9788f4SDavid Rientjes 148279f1461SSuresh Siddha /* 149279f1461SSuresh Siddha * APIC command line parameters 150279f1461SSuresh Siddha */ 151279f1461SSuresh Siddha static int __init parse_lapic(char *arg) 152279f1461SSuresh Siddha { 15397f2645fSMasahiro Yamada if (IS_ENABLED(CONFIG_X86_32) && !arg) 154279f1461SSuresh Siddha force_enable_local_apic = 1; 15527cf9298SMathias Krause else if (arg && !strncmp(arg, "notscdeadline", 13)) 156279f1461SSuresh Siddha setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 157279f1461SSuresh Siddha return 0; 158279f1461SSuresh Siddha } 159279f1461SSuresh Siddha early_param("lapic", parse_lapic); 160279f1461SSuresh Siddha 161f62bae50SIngo Molnar #ifdef CONFIG_X86_64 162f62bae50SIngo Molnar static int apic_calibrate_pmtmr __initdata; 163f62bae50SIngo Molnar static __init int setup_apicpmtimer(char *s) 164f62bae50SIngo Molnar { 165f62bae50SIngo Molnar apic_calibrate_pmtmr = 1; 166f62bae50SIngo Molnar notsc_setup(NULL); 167f62bae50SIngo Molnar return 0; 168f62bae50SIngo Molnar } 169f62bae50SIngo Molnar __setup("apicpmtimer", setup_apicpmtimer); 170f62bae50SIngo Molnar #endif 171f62bae50SIngo Molnar 172f62bae50SIngo Molnar unsigned long mp_lapic_addr; 173f62bae50SIngo Molnar int disable_apic; 174f62bae50SIngo Molnar /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 17525874a29SHenrik Kretzschmar static int disable_apic_timer __initdata; 176f62bae50SIngo Molnar /* Local APIC timer works in C2 */ 177f62bae50SIngo Molnar int local_apic_timer_c2_ok; 178f62bae50SIngo Molnar EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 179f62bae50SIngo Molnar 180f62bae50SIngo Molnar /* 181f62bae50SIngo Molnar * Debug level, exported for io_apic.c 182f62bae50SIngo Molnar */ 183f62bae50SIngo Molnar unsigned int apic_verbosity; 184f62bae50SIngo Molnar 185f62bae50SIngo Molnar int pic_mode; 186f62bae50SIngo Molnar 187f62bae50SIngo Molnar /* Have we found an MP table */ 188f62bae50SIngo Molnar int smp_found_config; 189f62bae50SIngo Molnar 190f62bae50SIngo Molnar static struct resource lapic_resource = { 191f62bae50SIngo Molnar .name = "Local APIC", 192f62bae50SIngo Molnar .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 193f62bae50SIngo Molnar }; 194f62bae50SIngo Molnar 1951ade93efSJacob Pan unsigned int lapic_timer_frequency = 0; 196f62bae50SIngo Molnar 197f62bae50SIngo Molnar static void apic_pm_activate(void); 198f62bae50SIngo Molnar 199f62bae50SIngo Molnar static unsigned long apic_phys; 200f62bae50SIngo Molnar 201f62bae50SIngo Molnar /* 202f62bae50SIngo Molnar * Get the LAPIC version 203f62bae50SIngo Molnar */ 204f62bae50SIngo Molnar static inline int lapic_get_version(void) 205f62bae50SIngo Molnar { 206f62bae50SIngo Molnar return GET_APIC_VERSION(apic_read(APIC_LVR)); 207f62bae50SIngo Molnar } 208f62bae50SIngo Molnar 209f62bae50SIngo Molnar /* 210f62bae50SIngo Molnar * Check, if the APIC is integrated or a separate chip 211f62bae50SIngo Molnar */ 212f62bae50SIngo Molnar static inline int lapic_is_integrated(void) 213f62bae50SIngo Molnar { 214f62bae50SIngo Molnar return APIC_INTEGRATED(lapic_get_version()); 215f62bae50SIngo Molnar } 216f62bae50SIngo Molnar 217f62bae50SIngo Molnar /* 218f62bae50SIngo Molnar * Check, whether this is a modern or a first generation APIC 219f62bae50SIngo Molnar */ 220f62bae50SIngo Molnar static int modern_apic(void) 221f62bae50SIngo Molnar { 222f62bae50SIngo Molnar /* AMD systems use old APIC versions, so check the CPU */ 223f62bae50SIngo Molnar if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 224f62bae50SIngo Molnar boot_cpu_data.x86 >= 0xf) 225f62bae50SIngo Molnar return 1; 226f62bae50SIngo Molnar return lapic_get_version() >= 0x14; 227f62bae50SIngo Molnar } 228f62bae50SIngo Molnar 22908306ce6SCyrill Gorcunov /* 230a933c618SCyrill Gorcunov * right after this call apic become NOOP driven 231a933c618SCyrill Gorcunov * so apic->write/read doesn't do anything 23208306ce6SCyrill Gorcunov */ 23325874a29SHenrik Kretzschmar static void __init apic_disable(void) 23408306ce6SCyrill Gorcunov { 235f88f2b4fSCyrill Gorcunov pr_info("APIC: switched to apic NOOP\n"); 236a933c618SCyrill Gorcunov apic = &apic_noop; 23708306ce6SCyrill Gorcunov } 23808306ce6SCyrill Gorcunov 239f62bae50SIngo Molnar void native_apic_wait_icr_idle(void) 240f62bae50SIngo Molnar { 241f62bae50SIngo Molnar while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 242f62bae50SIngo Molnar cpu_relax(); 243f62bae50SIngo Molnar } 244f62bae50SIngo Molnar 245f62bae50SIngo Molnar u32 native_safe_apic_wait_icr_idle(void) 246f62bae50SIngo Molnar { 247f62bae50SIngo Molnar u32 send_status; 248f62bae50SIngo Molnar int timeout; 249f62bae50SIngo Molnar 250f62bae50SIngo Molnar timeout = 0; 251f62bae50SIngo Molnar do { 252f62bae50SIngo Molnar send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 253f62bae50SIngo Molnar if (!send_status) 254f62bae50SIngo Molnar break; 255b49d7d87SFernando Luis Vazquez Cao inc_irq_stat(icr_read_retry_count); 256f62bae50SIngo Molnar udelay(100); 257f62bae50SIngo Molnar } while (timeout++ < 1000); 258f62bae50SIngo Molnar 259f62bae50SIngo Molnar return send_status; 260f62bae50SIngo Molnar } 261f62bae50SIngo Molnar 262f62bae50SIngo Molnar void native_apic_icr_write(u32 low, u32 id) 263f62bae50SIngo Molnar { 264ea7bdc65SJan Kiszka unsigned long flags; 265ea7bdc65SJan Kiszka 266ea7bdc65SJan Kiszka local_irq_save(flags); 267f62bae50SIngo Molnar apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 268f62bae50SIngo Molnar apic_write(APIC_ICR, low); 269ea7bdc65SJan Kiszka local_irq_restore(flags); 270f62bae50SIngo Molnar } 271f62bae50SIngo Molnar 272f62bae50SIngo Molnar u64 native_apic_icr_read(void) 273f62bae50SIngo Molnar { 274f62bae50SIngo Molnar u32 icr1, icr2; 275f62bae50SIngo Molnar 276f62bae50SIngo Molnar icr2 = apic_read(APIC_ICR2); 277f62bae50SIngo Molnar icr1 = apic_read(APIC_ICR); 278f62bae50SIngo Molnar 279f62bae50SIngo Molnar return icr1 | ((u64)icr2 << 32); 280f62bae50SIngo Molnar } 281f62bae50SIngo Molnar 282f62bae50SIngo Molnar #ifdef CONFIG_X86_32 283f62bae50SIngo Molnar /** 284f62bae50SIngo Molnar * get_physical_broadcast - Get number of physical broadcast IDs 285f62bae50SIngo Molnar */ 286f62bae50SIngo Molnar int get_physical_broadcast(void) 287f62bae50SIngo Molnar { 288f62bae50SIngo Molnar return modern_apic() ? 0xff : 0xf; 289f62bae50SIngo Molnar } 290f62bae50SIngo Molnar #endif 291f62bae50SIngo Molnar 292f62bae50SIngo Molnar /** 293f62bae50SIngo Molnar * lapic_get_maxlvt - get the maximum number of local vector table entries 294f62bae50SIngo Molnar */ 295f62bae50SIngo Molnar int lapic_get_maxlvt(void) 296f62bae50SIngo Molnar { 297f62bae50SIngo Molnar /* 298f62bae50SIngo Molnar * - we always have APIC integrated on 64bit mode 299f62bae50SIngo Molnar * - 82489DXs do not report # of LVT entries 300f62bae50SIngo Molnar */ 301ae41a2a4SDou Liyang return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2; 302f62bae50SIngo Molnar } 303f62bae50SIngo Molnar 304f62bae50SIngo Molnar /* 305f62bae50SIngo Molnar * Local APIC timer 306f62bae50SIngo Molnar */ 307f62bae50SIngo Molnar 308f62bae50SIngo Molnar /* Clock divisor */ 309f62bae50SIngo Molnar #define APIC_DIVISOR 16 3101a9e4c56SNicolai Stange #define TSC_DIVISOR 8 311f62bae50SIngo Molnar 312f62bae50SIngo Molnar /* 313f62bae50SIngo Molnar * This function sets up the local APIC timer, with a timeout of 314f62bae50SIngo Molnar * 'clocks' APIC bus clock. During calibration we actually call 315f62bae50SIngo Molnar * this function twice on the boot CPU, once with a bogus timeout 316f62bae50SIngo Molnar * value, second time for real. The other (noncalibrating) CPUs 317f62bae50SIngo Molnar * call this function only once, with the real, calibrated value. 318f62bae50SIngo Molnar * 319f62bae50SIngo Molnar * We do reads before writes even if unnecessary, to get around the 320f62bae50SIngo Molnar * P5 APIC double write bug. 321f62bae50SIngo Molnar */ 322f62bae50SIngo Molnar static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 323f62bae50SIngo Molnar { 324f62bae50SIngo Molnar unsigned int lvtt_value, tmp_value; 325f62bae50SIngo Molnar 326f62bae50SIngo Molnar lvtt_value = LOCAL_TIMER_VECTOR; 327f62bae50SIngo Molnar if (!oneshot) 328f62bae50SIngo Molnar lvtt_value |= APIC_LVT_TIMER_PERIODIC; 329279f1461SSuresh Siddha else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 330279f1461SSuresh Siddha lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; 331279f1461SSuresh Siddha 332f62bae50SIngo Molnar if (!lapic_is_integrated()) 333f62bae50SIngo Molnar lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 334f62bae50SIngo Molnar 335f62bae50SIngo Molnar if (!irqen) 336f62bae50SIngo Molnar lvtt_value |= APIC_LVT_MASKED; 337f62bae50SIngo Molnar 338f62bae50SIngo Molnar apic_write(APIC_LVTT, lvtt_value); 339f62bae50SIngo Molnar 340279f1461SSuresh Siddha if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { 3415d7c631dSShaohua Li /* 3425d7c631dSShaohua Li * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, 3435d7c631dSShaohua Li * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. 3445d7c631dSShaohua Li * According to Intel, MFENCE can do the serialization here. 3455d7c631dSShaohua Li */ 3465d7c631dSShaohua Li asm volatile("mfence" : : : "memory"); 3475d7c631dSShaohua Li 348279f1461SSuresh Siddha printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); 349279f1461SSuresh Siddha return; 350279f1461SSuresh Siddha } 351279f1461SSuresh Siddha 352f62bae50SIngo Molnar /* 353f62bae50SIngo Molnar * Divide PICLK by 16 354f62bae50SIngo Molnar */ 355f62bae50SIngo Molnar tmp_value = apic_read(APIC_TDCR); 356f62bae50SIngo Molnar apic_write(APIC_TDCR, 357f62bae50SIngo Molnar (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 358f62bae50SIngo Molnar APIC_TDR_DIV_16); 359f62bae50SIngo Molnar 360f62bae50SIngo Molnar if (!oneshot) 361f62bae50SIngo Molnar apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 362f62bae50SIngo Molnar } 363f62bae50SIngo Molnar 364f62bae50SIngo Molnar /* 365a68c439bSRobert Richter * Setup extended LVT, AMD specific 366f62bae50SIngo Molnar * 367a68c439bSRobert Richter * Software should use the LVT offsets the BIOS provides. The offsets 368a68c439bSRobert Richter * are determined by the subsystems using it like those for MCE 369a68c439bSRobert Richter * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 370a68c439bSRobert Richter * are supported. Beginning with family 10h at least 4 offsets are 371a68c439bSRobert Richter * available. 372f62bae50SIngo Molnar * 373a68c439bSRobert Richter * Since the offsets must be consistent for all cores, we keep track 374a68c439bSRobert Richter * of the LVT offsets in software and reserve the offset for the same 375a68c439bSRobert Richter * vector also to be used on other cores. An offset is freed by 376a68c439bSRobert Richter * setting the entry to APIC_EILVT_MASKED. 377a68c439bSRobert Richter * 378a68c439bSRobert Richter * If the BIOS is right, there should be no conflicts. Otherwise a 379a68c439bSRobert Richter * "[Firmware Bug]: ..." error message is generated. However, if 380a68c439bSRobert Richter * software does not properly determines the offsets, it is not 381a68c439bSRobert Richter * necessarily a BIOS bug. 382f62bae50SIngo Molnar */ 383f62bae50SIngo Molnar 384a68c439bSRobert Richter static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 385f62bae50SIngo Molnar 386a68c439bSRobert Richter static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 387a68c439bSRobert Richter { 388a68c439bSRobert Richter return (old & APIC_EILVT_MASKED) 389a68c439bSRobert Richter || (new == APIC_EILVT_MASKED) 390a68c439bSRobert Richter || ((new & ~APIC_EILVT_MASKED) == old); 391a68c439bSRobert Richter } 392a68c439bSRobert Richter 393a68c439bSRobert Richter static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 394a68c439bSRobert Richter { 3958abc3122SRobert Richter unsigned int rsvd, vector; 396a68c439bSRobert Richter 397a68c439bSRobert Richter if (offset >= APIC_EILVT_NR_MAX) 398a68c439bSRobert Richter return ~0; 399a68c439bSRobert Richter 4008abc3122SRobert Richter rsvd = atomic_read(&eilvt_offsets[offset]); 401a68c439bSRobert Richter do { 4028abc3122SRobert Richter vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ 4038abc3122SRobert Richter if (vector && !eilvt_entry_is_changeable(vector, new)) 404a68c439bSRobert Richter /* may not change if vectors are different */ 405a68c439bSRobert Richter return rsvd; 406a68c439bSRobert Richter rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 407a68c439bSRobert Richter } while (rsvd != new); 408a68c439bSRobert Richter 4098abc3122SRobert Richter rsvd &= ~APIC_EILVT_MASKED; 4108abc3122SRobert Richter if (rsvd && rsvd != vector) 4118abc3122SRobert Richter pr_info("LVT offset %d assigned for vector 0x%02x\n", 4128abc3122SRobert Richter offset, rsvd); 4138abc3122SRobert Richter 414a68c439bSRobert Richter return new; 415a68c439bSRobert Richter } 416a68c439bSRobert Richter 417a68c439bSRobert Richter /* 418a68c439bSRobert Richter * If mask=1, the LVT entry does not generate interrupts while mask=0 419cbf74ceaSRobert Richter * enables the vector. See also the BKDGs. Must be called with 420cbf74ceaSRobert Richter * preemption disabled. 421a68c439bSRobert Richter */ 422a68c439bSRobert Richter 42327afdf20SRobert Richter int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 424a68c439bSRobert Richter { 425a68c439bSRobert Richter unsigned long reg = APIC_EILVTn(offset); 426a68c439bSRobert Richter unsigned int new, old, reserved; 427a68c439bSRobert Richter 428a68c439bSRobert Richter new = (mask << 16) | (msg_type << 8) | vector; 429a68c439bSRobert Richter old = apic_read(reg); 430a68c439bSRobert Richter reserved = reserve_eilvt_offset(offset, new); 431a68c439bSRobert Richter 432a68c439bSRobert Richter if (reserved != new) { 433eb48c9cbSRobert Richter pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 434eb48c9cbSRobert Richter "vector 0x%x, but the register is already in use for " 435eb48c9cbSRobert Richter "vector 0x%x on another cpu\n", 436eb48c9cbSRobert Richter smp_processor_id(), reg, offset, new, reserved); 437a68c439bSRobert Richter return -EINVAL; 438a68c439bSRobert Richter } 439a68c439bSRobert Richter 440a68c439bSRobert Richter if (!eilvt_entry_is_changeable(old, new)) { 441eb48c9cbSRobert Richter pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 442eb48c9cbSRobert Richter "vector 0x%x, but the register is already in use for " 443eb48c9cbSRobert Richter "vector 0x%x on this cpu\n", 444eb48c9cbSRobert Richter smp_processor_id(), reg, offset, new, old); 445a68c439bSRobert Richter return -EBUSY; 446a68c439bSRobert Richter } 447a68c439bSRobert Richter 448a68c439bSRobert Richter apic_write(reg, new); 449a68c439bSRobert Richter 450a68c439bSRobert Richter return 0; 451f62bae50SIngo Molnar } 45227afdf20SRobert Richter EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 453f62bae50SIngo Molnar 454f62bae50SIngo Molnar /* 455f62bae50SIngo Molnar * Program the next event, relative to now 456f62bae50SIngo Molnar */ 457f62bae50SIngo Molnar static int lapic_next_event(unsigned long delta, 458f62bae50SIngo Molnar struct clock_event_device *evt) 459f62bae50SIngo Molnar { 460f62bae50SIngo Molnar apic_write(APIC_TMICT, delta); 461f62bae50SIngo Molnar return 0; 462f62bae50SIngo Molnar } 463f62bae50SIngo Molnar 464279f1461SSuresh Siddha static int lapic_next_deadline(unsigned long delta, 465279f1461SSuresh Siddha struct clock_event_device *evt) 466279f1461SSuresh Siddha { 467279f1461SSuresh Siddha u64 tsc; 468279f1461SSuresh Siddha 4694ea1636bSAndy Lutomirski tsc = rdtsc(); 470279f1461SSuresh Siddha wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); 471279f1461SSuresh Siddha return 0; 472279f1461SSuresh Siddha } 473279f1461SSuresh Siddha 474b23d8e52SViresh Kumar static int lapic_timer_shutdown(struct clock_event_device *evt) 475f62bae50SIngo Molnar { 476f62bae50SIngo Molnar unsigned int v; 477f62bae50SIngo Molnar 478f62bae50SIngo Molnar /* Lapic used as dummy for broadcast ? */ 479f62bae50SIngo Molnar if (evt->features & CLOCK_EVT_FEAT_DUMMY) 480b23d8e52SViresh Kumar return 0; 481f62bae50SIngo Molnar 482f62bae50SIngo Molnar v = apic_read(APIC_LVTT); 483f62bae50SIngo Molnar v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 484f62bae50SIngo Molnar apic_write(APIC_LVTT, v); 4856f9b4100SAndreas Herrmann apic_write(APIC_TMICT, 0); 486b23d8e52SViresh Kumar return 0; 487f62bae50SIngo Molnar } 488f62bae50SIngo Molnar 489b23d8e52SViresh Kumar static inline int 490b23d8e52SViresh Kumar lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot) 491b23d8e52SViresh Kumar { 492b23d8e52SViresh Kumar /* Lapic used as dummy for broadcast ? */ 493b23d8e52SViresh Kumar if (evt->features & CLOCK_EVT_FEAT_DUMMY) 494b23d8e52SViresh Kumar return 0; 495b23d8e52SViresh Kumar 496b23d8e52SViresh Kumar __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1); 497b23d8e52SViresh Kumar return 0; 498b23d8e52SViresh Kumar } 499b23d8e52SViresh Kumar 500b23d8e52SViresh Kumar static int lapic_timer_set_periodic(struct clock_event_device *evt) 501b23d8e52SViresh Kumar { 502b23d8e52SViresh Kumar return lapic_timer_set_periodic_oneshot(evt, false); 503b23d8e52SViresh Kumar } 504b23d8e52SViresh Kumar 505b23d8e52SViresh Kumar static int lapic_timer_set_oneshot(struct clock_event_device *evt) 506b23d8e52SViresh Kumar { 507b23d8e52SViresh Kumar return lapic_timer_set_periodic_oneshot(evt, true); 508f62bae50SIngo Molnar } 509f62bae50SIngo Molnar 510f62bae50SIngo Molnar /* 511f62bae50SIngo Molnar * Local APIC timer broadcast function 512f62bae50SIngo Molnar */ 513f62bae50SIngo Molnar static void lapic_timer_broadcast(const struct cpumask *mask) 514f62bae50SIngo Molnar { 515f62bae50SIngo Molnar #ifdef CONFIG_SMP 516f62bae50SIngo Molnar apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 517f62bae50SIngo Molnar #endif 518f62bae50SIngo Molnar } 519f62bae50SIngo Molnar 52025874a29SHenrik Kretzschmar 52125874a29SHenrik Kretzschmar /* 52225874a29SHenrik Kretzschmar * The local apic timer can be used for any function which is CPU local. 52325874a29SHenrik Kretzschmar */ 52425874a29SHenrik Kretzschmar static struct clock_event_device lapic_clockevent = { 52525874a29SHenrik Kretzschmar .name = "lapic", 526b23d8e52SViresh Kumar .features = CLOCK_EVT_FEAT_PERIODIC | 527b23d8e52SViresh Kumar CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP 528b23d8e52SViresh Kumar | CLOCK_EVT_FEAT_DUMMY, 52925874a29SHenrik Kretzschmar .shift = 32, 530b23d8e52SViresh Kumar .set_state_shutdown = lapic_timer_shutdown, 531b23d8e52SViresh Kumar .set_state_periodic = lapic_timer_set_periodic, 532b23d8e52SViresh Kumar .set_state_oneshot = lapic_timer_set_oneshot, 533914122c3SFrederic Weisbecker .set_state_oneshot_stopped = lapic_timer_shutdown, 53425874a29SHenrik Kretzschmar .set_next_event = lapic_next_event, 53525874a29SHenrik Kretzschmar .broadcast = lapic_timer_broadcast, 53625874a29SHenrik Kretzschmar .rating = 100, 53725874a29SHenrik Kretzschmar .irq = -1, 53825874a29SHenrik Kretzschmar }; 53925874a29SHenrik Kretzschmar static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 54025874a29SHenrik Kretzschmar 541bd9240a1SPeter Zijlstra #define DEADLINE_MODEL_MATCH_FUNC(model, func) \ 542bd9240a1SPeter Zijlstra { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&func } 543bd9240a1SPeter Zijlstra 544bd9240a1SPeter Zijlstra #define DEADLINE_MODEL_MATCH_REV(model, rev) \ 545bd9240a1SPeter Zijlstra { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)rev } 546bd9240a1SPeter Zijlstra 547bd9240a1SPeter Zijlstra static u32 hsx_deadline_rev(void) 548bd9240a1SPeter Zijlstra { 549b399151cSJia Zhang switch (boot_cpu_data.x86_stepping) { 550bd9240a1SPeter Zijlstra case 0x02: return 0x3a; /* EP */ 551bd9240a1SPeter Zijlstra case 0x04: return 0x0f; /* EX */ 552bd9240a1SPeter Zijlstra } 553bd9240a1SPeter Zijlstra 554bd9240a1SPeter Zijlstra return ~0U; 555bd9240a1SPeter Zijlstra } 556bd9240a1SPeter Zijlstra 557bd9240a1SPeter Zijlstra static u32 bdx_deadline_rev(void) 558bd9240a1SPeter Zijlstra { 559b399151cSJia Zhang switch (boot_cpu_data.x86_stepping) { 560bd9240a1SPeter Zijlstra case 0x02: return 0x00000011; 561bd9240a1SPeter Zijlstra case 0x03: return 0x0700000e; 562bd9240a1SPeter Zijlstra case 0x04: return 0x0f00000c; 563bd9240a1SPeter Zijlstra case 0x05: return 0x0e000003; 564bd9240a1SPeter Zijlstra } 565bd9240a1SPeter Zijlstra 566bd9240a1SPeter Zijlstra return ~0U; 567bd9240a1SPeter Zijlstra } 568bd9240a1SPeter Zijlstra 569616dd587SLen Brown static u32 skx_deadline_rev(void) 570616dd587SLen Brown { 571b399151cSJia Zhang switch (boot_cpu_data.x86_stepping) { 572616dd587SLen Brown case 0x03: return 0x01000136; 573616dd587SLen Brown case 0x04: return 0x02000014; 574616dd587SLen Brown } 575616dd587SLen Brown 576d9e6dbcfSLen Brown if (boot_cpu_data.x86_stepping > 4) 577d9e6dbcfSLen Brown return 0; 578d9e6dbcfSLen Brown 579616dd587SLen Brown return ~0U; 580616dd587SLen Brown } 581616dd587SLen Brown 582bd9240a1SPeter Zijlstra static const struct x86_cpu_id deadline_match[] = { 583bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X, hsx_deadline_rev), 584bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X, 0x0b000020), 585bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_XEON_D, bdx_deadline_rev), 586616dd587SLen Brown DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_SKYLAKE_X, skx_deadline_rev), 587bd9240a1SPeter Zijlstra 588bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_CORE, 0x22), 589bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_ULT, 0x20), 590bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_GT3E, 0x17), 591bd9240a1SPeter Zijlstra 592bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_CORE, 0x25), 593bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_GT3E, 0x17), 594bd9240a1SPeter Zijlstra 595bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE, 0xb2), 596bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP, 0xb2), 597bd9240a1SPeter Zijlstra 598bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE, 0x52), 599bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP, 0x52), 600bd9240a1SPeter Zijlstra 601bd9240a1SPeter Zijlstra {}, 602bd9240a1SPeter Zijlstra }; 603bd9240a1SPeter Zijlstra 604bd9240a1SPeter Zijlstra static void apic_check_deadline_errata(void) 605bd9240a1SPeter Zijlstra { 606594a30fbSHans de Goede const struct x86_cpu_id *m; 607bd9240a1SPeter Zijlstra u32 rev; 608bd9240a1SPeter Zijlstra 609cc6afe22SPaolo Bonzini if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER) || 610cc6afe22SPaolo Bonzini boot_cpu_has(X86_FEATURE_HYPERVISOR)) 611594a30fbSHans de Goede return; 612594a30fbSHans de Goede 613594a30fbSHans de Goede m = x86_match_cpu(deadline_match); 614bd9240a1SPeter Zijlstra if (!m) 615bd9240a1SPeter Zijlstra return; 616bd9240a1SPeter Zijlstra 617bd9240a1SPeter Zijlstra /* 618bd9240a1SPeter Zijlstra * Function pointers will have the MSB set due to address layout, 619bd9240a1SPeter Zijlstra * immediate revisions will not. 620bd9240a1SPeter Zijlstra */ 621bd9240a1SPeter Zijlstra if ((long)m->driver_data < 0) 622bd9240a1SPeter Zijlstra rev = ((u32 (*)(void))(m->driver_data))(); 623bd9240a1SPeter Zijlstra else 624bd9240a1SPeter Zijlstra rev = (u32)m->driver_data; 625bd9240a1SPeter Zijlstra 626bd9240a1SPeter Zijlstra if (boot_cpu_data.microcode >= rev) 627bd9240a1SPeter Zijlstra return; 628bd9240a1SPeter Zijlstra 629bd9240a1SPeter Zijlstra setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 630bd9240a1SPeter Zijlstra pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; " 631bd9240a1SPeter Zijlstra "please update microcode to version: 0x%x (or later)\n", rev); 632bd9240a1SPeter Zijlstra } 633bd9240a1SPeter Zijlstra 634f62bae50SIngo Molnar /* 635421f91d2SUwe Kleine-König * Setup the local APIC timer for this CPU. Copy the initialized values 636f62bae50SIngo Molnar * of the boot CPU and register the clock event in the framework. 637f62bae50SIngo Molnar */ 638148f9bb8SPaul Gortmaker static void setup_APIC_timer(void) 639f62bae50SIngo Molnar { 64089cbc767SChristoph Lameter struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 641f62bae50SIngo Molnar 642349c004eSChristoph Lameter if (this_cpu_has(X86_FEATURE_ARAT)) { 643db954b58SVenkatesh Pallipadi lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 644db954b58SVenkatesh Pallipadi /* Make LAPIC timer preferrable over percpu HPET */ 645db954b58SVenkatesh Pallipadi lapic_clockevent.rating = 150; 646db954b58SVenkatesh Pallipadi } 647db954b58SVenkatesh Pallipadi 648f62bae50SIngo Molnar memcpy(levt, &lapic_clockevent, sizeof(*levt)); 649f62bae50SIngo Molnar levt->cpumask = cpumask_of(smp_processor_id()); 650f62bae50SIngo Molnar 651279f1461SSuresh Siddha if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 652c6e9f42bSPeter Zijlstra levt->name = "lapic-deadline"; 653279f1461SSuresh Siddha levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | 654279f1461SSuresh Siddha CLOCK_EVT_FEAT_DUMMY); 655279f1461SSuresh Siddha levt->set_next_event = lapic_next_deadline; 656279f1461SSuresh Siddha clockevents_config_and_register(levt, 6571a9e4c56SNicolai Stange tsc_khz * (1000 / TSC_DIVISOR), 658279f1461SSuresh Siddha 0xF, ~0UL); 659279f1461SSuresh Siddha } else 660f62bae50SIngo Molnar clockevents_register_device(levt); 661f62bae50SIngo Molnar } 662f62bae50SIngo Molnar 663f62bae50SIngo Molnar /* 6646731b0d6SNicolai Stange * Install the updated TSC frequency from recalibration at the TSC 6656731b0d6SNicolai Stange * deadline clockevent devices. 6666731b0d6SNicolai Stange */ 6676731b0d6SNicolai Stange static void __lapic_update_tsc_freq(void *info) 6686731b0d6SNicolai Stange { 6696731b0d6SNicolai Stange struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 6706731b0d6SNicolai Stange 6716731b0d6SNicolai Stange if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 6726731b0d6SNicolai Stange return; 6736731b0d6SNicolai Stange 6746731b0d6SNicolai Stange clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR)); 6756731b0d6SNicolai Stange } 6766731b0d6SNicolai Stange 6776731b0d6SNicolai Stange void lapic_update_tsc_freq(void) 6786731b0d6SNicolai Stange { 6796731b0d6SNicolai Stange /* 6806731b0d6SNicolai Stange * The clockevent device's ->mult and ->shift can both be 6816731b0d6SNicolai Stange * changed. In order to avoid races, schedule the frequency 6826731b0d6SNicolai Stange * update code on each CPU. 6836731b0d6SNicolai Stange */ 6846731b0d6SNicolai Stange on_each_cpu(__lapic_update_tsc_freq, NULL, 0); 6856731b0d6SNicolai Stange } 6866731b0d6SNicolai Stange 6876731b0d6SNicolai Stange /* 688f62bae50SIngo Molnar * In this functions we calibrate APIC bus clocks to the external timer. 689f62bae50SIngo Molnar * 690f62bae50SIngo Molnar * We want to do the calibration only once since we want to have local timer 691f62bae50SIngo Molnar * irqs syncron. CPUs connected by the same APIC bus have the very same bus 692f62bae50SIngo Molnar * frequency. 693f62bae50SIngo Molnar * 694f62bae50SIngo Molnar * This was previously done by reading the PIT/HPET and waiting for a wrap 695f62bae50SIngo Molnar * around to find out, that a tick has elapsed. I have a box, where the PIT 696f62bae50SIngo Molnar * readout is broken, so it never gets out of the wait loop again. This was 697f62bae50SIngo Molnar * also reported by others. 698f62bae50SIngo Molnar * 699f62bae50SIngo Molnar * Monitoring the jiffies value is inaccurate and the clockevents 700f62bae50SIngo Molnar * infrastructure allows us to do a simple substitution of the interrupt 701f62bae50SIngo Molnar * handler. 702f62bae50SIngo Molnar * 703f62bae50SIngo Molnar * The calibration routine also uses the pm_timer when possible, as the PIT 704f62bae50SIngo Molnar * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 705f62bae50SIngo Molnar * back to normal later in the boot process). 706f62bae50SIngo Molnar */ 707f62bae50SIngo Molnar 708f62bae50SIngo Molnar #define LAPIC_CAL_LOOPS (HZ/10) 709f62bae50SIngo Molnar 710f62bae50SIngo Molnar static __initdata int lapic_cal_loops = -1; 711f62bae50SIngo Molnar static __initdata long lapic_cal_t1, lapic_cal_t2; 712f62bae50SIngo Molnar static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 713f62bae50SIngo Molnar static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 714f62bae50SIngo Molnar static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 715f62bae50SIngo Molnar 716f62bae50SIngo Molnar /* 717f62bae50SIngo Molnar * Temporary interrupt handler. 718f62bae50SIngo Molnar */ 719f62bae50SIngo Molnar static void __init lapic_cal_handler(struct clock_event_device *dev) 720f62bae50SIngo Molnar { 721f62bae50SIngo Molnar unsigned long long tsc = 0; 722f62bae50SIngo Molnar long tapic = apic_read(APIC_TMCCT); 723f62bae50SIngo Molnar unsigned long pm = acpi_pm_read_early(); 724f62bae50SIngo Molnar 72559e21e3dSBorislav Petkov if (boot_cpu_has(X86_FEATURE_TSC)) 7264ea1636bSAndy Lutomirski tsc = rdtsc(); 727f62bae50SIngo Molnar 728f62bae50SIngo Molnar switch (lapic_cal_loops++) { 729f62bae50SIngo Molnar case 0: 730f62bae50SIngo Molnar lapic_cal_t1 = tapic; 731f62bae50SIngo Molnar lapic_cal_tsc1 = tsc; 732f62bae50SIngo Molnar lapic_cal_pm1 = pm; 733f62bae50SIngo Molnar lapic_cal_j1 = jiffies; 734f62bae50SIngo Molnar break; 735f62bae50SIngo Molnar 736f62bae50SIngo Molnar case LAPIC_CAL_LOOPS: 737f62bae50SIngo Molnar lapic_cal_t2 = tapic; 738f62bae50SIngo Molnar lapic_cal_tsc2 = tsc; 739f62bae50SIngo Molnar if (pm < lapic_cal_pm1) 740f62bae50SIngo Molnar pm += ACPI_PM_OVRRUN; 741f62bae50SIngo Molnar lapic_cal_pm2 = pm; 742f62bae50SIngo Molnar lapic_cal_j2 = jiffies; 743f62bae50SIngo Molnar break; 744f62bae50SIngo Molnar } 745f62bae50SIngo Molnar } 746f62bae50SIngo Molnar 747f62bae50SIngo Molnar static int __init 748f62bae50SIngo Molnar calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 749f62bae50SIngo Molnar { 750f62bae50SIngo Molnar const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 751f62bae50SIngo Molnar const long pm_thresh = pm_100ms / 100; 752f62bae50SIngo Molnar unsigned long mult; 753f62bae50SIngo Molnar u64 res; 754f62bae50SIngo Molnar 755f62bae50SIngo Molnar #ifndef CONFIG_X86_PM_TIMER 756f62bae50SIngo Molnar return -1; 757f62bae50SIngo Molnar #endif 758f62bae50SIngo Molnar 759f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 760f62bae50SIngo Molnar 761f62bae50SIngo Molnar /* Check, if the PM timer is available */ 762f62bae50SIngo Molnar if (!deltapm) 763f62bae50SIngo Molnar return -1; 764f62bae50SIngo Molnar 765f62bae50SIngo Molnar mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 766f62bae50SIngo Molnar 767f62bae50SIngo Molnar if (deltapm > (pm_100ms - pm_thresh) && 768f62bae50SIngo Molnar deltapm < (pm_100ms + pm_thresh)) { 769f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 770f62bae50SIngo Molnar return 0; 771f62bae50SIngo Molnar } 772f62bae50SIngo Molnar 773f62bae50SIngo Molnar res = (((u64)deltapm) * mult) >> 22; 774f62bae50SIngo Molnar do_div(res, 1000000); 775f62bae50SIngo Molnar pr_warning("APIC calibration not consistent " 776f62bae50SIngo Molnar "with PM-Timer: %ldms instead of 100ms\n",(long)res); 777f62bae50SIngo Molnar 778f62bae50SIngo Molnar /* Correct the lapic counter value */ 779f62bae50SIngo Molnar res = (((u64)(*delta)) * pm_100ms); 780f62bae50SIngo Molnar do_div(res, deltapm); 781f62bae50SIngo Molnar pr_info("APIC delta adjusted to PM-Timer: " 782f62bae50SIngo Molnar "%lu (%ld)\n", (unsigned long)res, *delta); 783f62bae50SIngo Molnar *delta = (long)res; 784f62bae50SIngo Molnar 785f62bae50SIngo Molnar /* Correct the tsc counter value */ 78659e21e3dSBorislav Petkov if (boot_cpu_has(X86_FEATURE_TSC)) { 787f62bae50SIngo Molnar res = (((u64)(*deltatsc)) * pm_100ms); 788f62bae50SIngo Molnar do_div(res, deltapm); 789f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 790f62bae50SIngo Molnar "PM-Timer: %lu (%ld)\n", 791f62bae50SIngo Molnar (unsigned long)res, *deltatsc); 792f62bae50SIngo Molnar *deltatsc = (long)res; 793f62bae50SIngo Molnar } 794f62bae50SIngo Molnar 795f62bae50SIngo Molnar return 0; 796f62bae50SIngo Molnar } 797f62bae50SIngo Molnar 798f62bae50SIngo Molnar static int __init calibrate_APIC_clock(void) 799f62bae50SIngo Molnar { 80089cbc767SChristoph Lameter struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 801f62bae50SIngo Molnar void (*real_handler)(struct clock_event_device *dev); 802f62bae50SIngo Molnar unsigned long deltaj; 803f62bae50SIngo Molnar long delta, deltatsc; 804f62bae50SIngo Molnar int pm_referenced = 0; 805f62bae50SIngo Molnar 8061ade93efSJacob Pan /** 8071ade93efSJacob Pan * check if lapic timer has already been calibrated by platform 8081ade93efSJacob Pan * specific routine, such as tsc calibration code. if so, we just fill 8091ade93efSJacob Pan * in the clockevent structure and return. 8101ade93efSJacob Pan */ 8111ade93efSJacob Pan 812279f1461SSuresh Siddha if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 813279f1461SSuresh Siddha return 0; 814279f1461SSuresh Siddha } else if (lapic_timer_frequency) { 8151ade93efSJacob Pan apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", 8161ade93efSJacob Pan lapic_timer_frequency); 8171ade93efSJacob Pan lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR, 8181ade93efSJacob Pan TICK_NSEC, lapic_clockevent.shift); 8191ade93efSJacob Pan lapic_clockevent.max_delta_ns = 8201ade93efSJacob Pan clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); 821747d04b3SNicolai Stange lapic_clockevent.max_delta_ticks = 0x7FFFFF; 8221ade93efSJacob Pan lapic_clockevent.min_delta_ns = 8231ade93efSJacob Pan clockevent_delta2ns(0xF, &lapic_clockevent); 824747d04b3SNicolai Stange lapic_clockevent.min_delta_ticks = 0xF; 8251ade93efSJacob Pan lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 8261ade93efSJacob Pan return 0; 8271ade93efSJacob Pan } 8281ade93efSJacob Pan 829279f1461SSuresh Siddha apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 830279f1461SSuresh Siddha "calibrating APIC timer ...\n"); 831279f1461SSuresh Siddha 832f62bae50SIngo Molnar local_irq_disable(); 833f62bae50SIngo Molnar 834f62bae50SIngo Molnar /* Replace the global interrupt handler */ 835f62bae50SIngo Molnar real_handler = global_clock_event->event_handler; 836f62bae50SIngo Molnar global_clock_event->event_handler = lapic_cal_handler; 837f62bae50SIngo Molnar 838f62bae50SIngo Molnar /* 839f62bae50SIngo Molnar * Setup the APIC counter to maximum. There is no way the lapic 840f62bae50SIngo Molnar * can underflow in the 100ms detection time frame 841f62bae50SIngo Molnar */ 842f62bae50SIngo Molnar __setup_APIC_LVTT(0xffffffff, 0, 0); 843f62bae50SIngo Molnar 844f62bae50SIngo Molnar /* Let the interrupts run */ 845f62bae50SIngo Molnar local_irq_enable(); 846f62bae50SIngo Molnar 847f62bae50SIngo Molnar while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 848f62bae50SIngo Molnar cpu_relax(); 849f62bae50SIngo Molnar 850f62bae50SIngo Molnar local_irq_disable(); 851f62bae50SIngo Molnar 852f62bae50SIngo Molnar /* Restore the real event handler */ 853f62bae50SIngo Molnar global_clock_event->event_handler = real_handler; 854f62bae50SIngo Molnar 855f62bae50SIngo Molnar /* Build delta t1-t2 as apic timer counts down */ 856f62bae50SIngo Molnar delta = lapic_cal_t1 - lapic_cal_t2; 857f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 858f62bae50SIngo Molnar 859f62bae50SIngo Molnar deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 860f62bae50SIngo Molnar 861f62bae50SIngo Molnar /* we trust the PM based calibration if possible */ 862f62bae50SIngo Molnar pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 863f62bae50SIngo Molnar &delta, &deltatsc); 864f62bae50SIngo Molnar 865f62bae50SIngo Molnar /* Calculate the scaled math multiplication factor */ 866f62bae50SIngo Molnar lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 867f62bae50SIngo Molnar lapic_clockevent.shift); 868f62bae50SIngo Molnar lapic_clockevent.max_delta_ns = 8694aed89d6SPierre Tardy clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 870747d04b3SNicolai Stange lapic_clockevent.max_delta_ticks = 0x7FFFFFFF; 871f62bae50SIngo Molnar lapic_clockevent.min_delta_ns = 872f62bae50SIngo Molnar clockevent_delta2ns(0xF, &lapic_clockevent); 873747d04b3SNicolai Stange lapic_clockevent.min_delta_ticks = 0xF; 874f62bae50SIngo Molnar 8751ade93efSJacob Pan lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 876f62bae50SIngo Molnar 877f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 878411462f6SThomas Gleixner apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 879f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 8801ade93efSJacob Pan lapic_timer_frequency); 881f62bae50SIngo Molnar 88259e21e3dSBorislav Petkov if (boot_cpu_has(X86_FEATURE_TSC)) { 883f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 884f62bae50SIngo Molnar "%ld.%04ld MHz.\n", 885f62bae50SIngo Molnar (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 886f62bae50SIngo Molnar (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 887f62bae50SIngo Molnar } 888f62bae50SIngo Molnar 889f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 890f62bae50SIngo Molnar "%u.%04u MHz.\n", 8911ade93efSJacob Pan lapic_timer_frequency / (1000000 / HZ), 8921ade93efSJacob Pan lapic_timer_frequency % (1000000 / HZ)); 893f62bae50SIngo Molnar 894f62bae50SIngo Molnar /* 895f62bae50SIngo Molnar * Do a sanity check on the APIC calibration result 896f62bae50SIngo Molnar */ 8971ade93efSJacob Pan if (lapic_timer_frequency < (1000000 / HZ)) { 898f62bae50SIngo Molnar local_irq_enable(); 899f62bae50SIngo Molnar pr_warning("APIC frequency too slow, disabling apic timer\n"); 900f62bae50SIngo Molnar return -1; 901f62bae50SIngo Molnar } 902f62bae50SIngo Molnar 903f62bae50SIngo Molnar levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 904f62bae50SIngo Molnar 905f62bae50SIngo Molnar /* 906f62bae50SIngo Molnar * PM timer calibration failed or not turned on 907f62bae50SIngo Molnar * so lets try APIC timer based calibration 908f62bae50SIngo Molnar */ 909f62bae50SIngo Molnar if (!pm_referenced) { 910f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 911f62bae50SIngo Molnar 912f62bae50SIngo Molnar /* 913f62bae50SIngo Molnar * Setup the apic timer manually 914f62bae50SIngo Molnar */ 915f62bae50SIngo Molnar levt->event_handler = lapic_cal_handler; 916b23d8e52SViresh Kumar lapic_timer_set_periodic(levt); 917f62bae50SIngo Molnar lapic_cal_loops = -1; 918f62bae50SIngo Molnar 919f62bae50SIngo Molnar /* Let the interrupts run */ 920f62bae50SIngo Molnar local_irq_enable(); 921f62bae50SIngo Molnar 922f62bae50SIngo Molnar while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 923f62bae50SIngo Molnar cpu_relax(); 924f62bae50SIngo Molnar 925f62bae50SIngo Molnar /* Stop the lapic timer */ 926c948c260SThomas Gleixner local_irq_disable(); 927b23d8e52SViresh Kumar lapic_timer_shutdown(levt); 928f62bae50SIngo Molnar 929f62bae50SIngo Molnar /* Jiffies delta */ 930f62bae50SIngo Molnar deltaj = lapic_cal_j2 - lapic_cal_j1; 931f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 932f62bae50SIngo Molnar 933f62bae50SIngo Molnar /* Check, if the jiffies result is consistent */ 934f62bae50SIngo Molnar if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 935f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 936f62bae50SIngo Molnar else 937f62bae50SIngo Molnar levt->features |= CLOCK_EVT_FEAT_DUMMY; 938c948c260SThomas Gleixner } 939f62bae50SIngo Molnar local_irq_enable(); 940f62bae50SIngo Molnar 941f62bae50SIngo Molnar if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 942f62bae50SIngo Molnar pr_warning("APIC timer disabled due to verification failure\n"); 943f62bae50SIngo Molnar return -1; 944f62bae50SIngo Molnar } 945f62bae50SIngo Molnar 946f62bae50SIngo Molnar return 0; 947f62bae50SIngo Molnar } 948f62bae50SIngo Molnar 949f62bae50SIngo Molnar /* 950f62bae50SIngo Molnar * Setup the boot APIC 951f62bae50SIngo Molnar * 952f62bae50SIngo Molnar * Calibrate and verify the result. 953f62bae50SIngo Molnar */ 954f62bae50SIngo Molnar void __init setup_boot_APIC_clock(void) 955f62bae50SIngo Molnar { 956f62bae50SIngo Molnar /* 957f62bae50SIngo Molnar * The local apic timer can be disabled via the kernel 958f62bae50SIngo Molnar * commandline or from the CPU detection code. Register the lapic 959f62bae50SIngo Molnar * timer as a dummy clock event source on SMP systems, so the 960f62bae50SIngo Molnar * broadcast mechanism is used. On UP systems simply ignore it. 961f62bae50SIngo Molnar */ 962f62bae50SIngo Molnar if (disable_apic_timer) { 963f62bae50SIngo Molnar pr_info("Disabling APIC timer\n"); 964f62bae50SIngo Molnar /* No broadcast on UP ! */ 965f62bae50SIngo Molnar if (num_possible_cpus() > 1) { 966f62bae50SIngo Molnar lapic_clockevent.mult = 1; 967f62bae50SIngo Molnar setup_APIC_timer(); 968f62bae50SIngo Molnar } 969f62bae50SIngo Molnar return; 970f62bae50SIngo Molnar } 971f62bae50SIngo Molnar 972f62bae50SIngo Molnar if (calibrate_APIC_clock()) { 973f62bae50SIngo Molnar /* No broadcast on UP ! */ 974f62bae50SIngo Molnar if (num_possible_cpus() > 1) 975f62bae50SIngo Molnar setup_APIC_timer(); 976f62bae50SIngo Molnar return; 977f62bae50SIngo Molnar } 978f62bae50SIngo Molnar 979f62bae50SIngo Molnar /* 980f62bae50SIngo Molnar * If nmi_watchdog is set to IO_APIC, we need the 981f62bae50SIngo Molnar * PIT/HPET going. Otherwise register lapic as a dummy 982f62bae50SIngo Molnar * device. 983f62bae50SIngo Molnar */ 984f62bae50SIngo Molnar lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 985f62bae50SIngo Molnar 986f62bae50SIngo Molnar /* Setup the lapic or request the broadcast */ 987f62bae50SIngo Molnar setup_APIC_timer(); 98807c94a38SBorislav Petkov amd_e400_c1e_apic_setup(); 989f62bae50SIngo Molnar } 990f62bae50SIngo Molnar 991148f9bb8SPaul Gortmaker void setup_secondary_APIC_clock(void) 992f62bae50SIngo Molnar { 993f62bae50SIngo Molnar setup_APIC_timer(); 99407c94a38SBorislav Petkov amd_e400_c1e_apic_setup(); 995f62bae50SIngo Molnar } 996f62bae50SIngo Molnar 997f62bae50SIngo Molnar /* 998f62bae50SIngo Molnar * The guts of the apic timer interrupt 999f62bae50SIngo Molnar */ 1000f62bae50SIngo Molnar static void local_apic_timer_interrupt(void) 1001f62bae50SIngo Molnar { 10023bec6defSThomas Gleixner struct clock_event_device *evt = this_cpu_ptr(&lapic_events); 1003f62bae50SIngo Molnar 1004f62bae50SIngo Molnar /* 1005f62bae50SIngo Molnar * Normally we should not be here till LAPIC has been initialized but 1006f62bae50SIngo Molnar * in some cases like kdump, its possible that there is a pending LAPIC 1007f62bae50SIngo Molnar * timer interrupt from previous kernel's context and is delivered in 1008f62bae50SIngo Molnar * new kernel the moment interrupts are enabled. 1009f62bae50SIngo Molnar * 1010f62bae50SIngo Molnar * Interrupts are enabled early and LAPIC is setup much later, hence 1011f62bae50SIngo Molnar * its possible that when we get here evt->event_handler is NULL. 1012f62bae50SIngo Molnar * Check for event_handler being NULL and discard the interrupt as 1013f62bae50SIngo Molnar * spurious. 1014f62bae50SIngo Molnar */ 1015f62bae50SIngo Molnar if (!evt->event_handler) { 10163bec6defSThomas Gleixner pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", 10173bec6defSThomas Gleixner smp_processor_id()); 1018f62bae50SIngo Molnar /* Switch it off */ 1019b23d8e52SViresh Kumar lapic_timer_shutdown(evt); 1020f62bae50SIngo Molnar return; 1021f62bae50SIngo Molnar } 1022f62bae50SIngo Molnar 1023f62bae50SIngo Molnar /* 1024f62bae50SIngo Molnar * the NMI deadlock-detector uses this. 1025f62bae50SIngo Molnar */ 1026f62bae50SIngo Molnar inc_irq_stat(apic_timer_irqs); 1027f62bae50SIngo Molnar 1028f62bae50SIngo Molnar evt->event_handler(evt); 1029f62bae50SIngo Molnar } 1030f62bae50SIngo Molnar 1031f62bae50SIngo Molnar /* 1032f62bae50SIngo Molnar * Local APIC timer interrupt. This is the most natural way for doing 1033f62bae50SIngo Molnar * local interrupts, but local timer interrupts can be emulated by 1034f62bae50SIngo Molnar * broadcast interrupts too. [in case the hw doesn't support APIC timers] 1035f62bae50SIngo Molnar * 1036f62bae50SIngo Molnar * [ if a single-CPU system runs an SMP kernel then we call the local 1037f62bae50SIngo Molnar * interrupt as well. Thus we cannot inline the local irq ... ] 1038f62bae50SIngo Molnar */ 10391d9090e2SAndi Kleen __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 1040f62bae50SIngo Molnar { 1041f62bae50SIngo Molnar struct pt_regs *old_regs = set_irq_regs(regs); 1042f62bae50SIngo Molnar 1043f62bae50SIngo Molnar /* 1044f62bae50SIngo Molnar * NOTE! We'd better ACK the irq immediately, 1045f62bae50SIngo Molnar * because timer handling can be slow. 1046eddc0e92SSeiji Aguchi * 1047f62bae50SIngo Molnar * update_process_times() expects us to have done irq_enter(). 1048f62bae50SIngo Molnar * Besides, if we don't timer interrupts ignore the global 1049f62bae50SIngo Molnar * interrupt lock, which is the WrongThing (tm) to do. 1050f62bae50SIngo Molnar */ 1051eddc0e92SSeiji Aguchi entering_ack_irq(); 1052cf910e83SSeiji Aguchi trace_local_timer_entry(LOCAL_TIMER_VECTOR); 1053cf910e83SSeiji Aguchi local_apic_timer_interrupt(); 1054cf910e83SSeiji Aguchi trace_local_timer_exit(LOCAL_TIMER_VECTOR); 1055cf910e83SSeiji Aguchi exiting_irq(); 1056f62bae50SIngo Molnar 1057f62bae50SIngo Molnar set_irq_regs(old_regs); 1058f62bae50SIngo Molnar } 1059f62bae50SIngo Molnar 1060f62bae50SIngo Molnar int setup_profiling_timer(unsigned int multiplier) 1061f62bae50SIngo Molnar { 1062f62bae50SIngo Molnar return -EINVAL; 1063f62bae50SIngo Molnar } 1064f62bae50SIngo Molnar 1065f62bae50SIngo Molnar /* 1066f62bae50SIngo Molnar * Local APIC start and shutdown 1067f62bae50SIngo Molnar */ 1068f62bae50SIngo Molnar 1069f62bae50SIngo Molnar /** 1070f62bae50SIngo Molnar * clear_local_APIC - shutdown the local APIC 1071f62bae50SIngo Molnar * 1072f62bae50SIngo Molnar * This is called, when a CPU is disabled and before rebooting, so the state of 1073f62bae50SIngo Molnar * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 1074f62bae50SIngo Molnar * leftovers during boot. 1075f62bae50SIngo Molnar */ 1076f62bae50SIngo Molnar void clear_local_APIC(void) 1077f62bae50SIngo Molnar { 1078f62bae50SIngo Molnar int maxlvt; 1079f62bae50SIngo Molnar u32 v; 1080f62bae50SIngo Molnar 1081f62bae50SIngo Molnar /* APIC hasn't been mapped yet */ 1082fc1edaf9SSuresh Siddha if (!x2apic_mode && !apic_phys) 1083f62bae50SIngo Molnar return; 1084f62bae50SIngo Molnar 1085f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 1086f62bae50SIngo Molnar /* 1087f62bae50SIngo Molnar * Masking an LVT entry can trigger a local APIC error 1088f62bae50SIngo Molnar * if the vector is zero. Mask LVTERR first to prevent this. 1089f62bae50SIngo Molnar */ 1090f62bae50SIngo Molnar if (maxlvt >= 3) { 1091f62bae50SIngo Molnar v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 1092f62bae50SIngo Molnar apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 1093f62bae50SIngo Molnar } 1094f62bae50SIngo Molnar /* 1095f62bae50SIngo Molnar * Careful: we have to set masks only first to deassert 1096f62bae50SIngo Molnar * any level-triggered sources. 1097f62bae50SIngo Molnar */ 1098f62bae50SIngo Molnar v = apic_read(APIC_LVTT); 1099f62bae50SIngo Molnar apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 1100f62bae50SIngo Molnar v = apic_read(APIC_LVT0); 1101f62bae50SIngo Molnar apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 1102f62bae50SIngo Molnar v = apic_read(APIC_LVT1); 1103f62bae50SIngo Molnar apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 1104f62bae50SIngo Molnar if (maxlvt >= 4) { 1105f62bae50SIngo Molnar v = apic_read(APIC_LVTPC); 1106f62bae50SIngo Molnar apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 1107f62bae50SIngo Molnar } 1108f62bae50SIngo Molnar 1109f62bae50SIngo Molnar /* lets not touch this if we didn't frob it */ 11104efc0670SAndi Kleen #ifdef CONFIG_X86_THERMAL_VECTOR 1111f62bae50SIngo Molnar if (maxlvt >= 5) { 1112f62bae50SIngo Molnar v = apic_read(APIC_LVTTHMR); 1113f62bae50SIngo Molnar apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 1114f62bae50SIngo Molnar } 1115f62bae50SIngo Molnar #endif 1116638bee71SH. Peter Anvin #ifdef CONFIG_X86_MCE_INTEL 1117638bee71SH. Peter Anvin if (maxlvt >= 6) { 1118638bee71SH. Peter Anvin v = apic_read(APIC_LVTCMCI); 1119638bee71SH. Peter Anvin if (!(v & APIC_LVT_MASKED)) 1120638bee71SH. Peter Anvin apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 1121638bee71SH. Peter Anvin } 1122638bee71SH. Peter Anvin #endif 1123638bee71SH. Peter Anvin 1124f62bae50SIngo Molnar /* 1125f62bae50SIngo Molnar * Clean APIC state for other OSs: 1126f62bae50SIngo Molnar */ 1127f62bae50SIngo Molnar apic_write(APIC_LVTT, APIC_LVT_MASKED); 1128f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_LVT_MASKED); 1129f62bae50SIngo Molnar apic_write(APIC_LVT1, APIC_LVT_MASKED); 1130f62bae50SIngo Molnar if (maxlvt >= 3) 1131f62bae50SIngo Molnar apic_write(APIC_LVTERR, APIC_LVT_MASKED); 1132f62bae50SIngo Molnar if (maxlvt >= 4) 1133f62bae50SIngo Molnar apic_write(APIC_LVTPC, APIC_LVT_MASKED); 1134f62bae50SIngo Molnar 1135f62bae50SIngo Molnar /* Integrated APIC (!82489DX) ? */ 1136f62bae50SIngo Molnar if (lapic_is_integrated()) { 1137f62bae50SIngo Molnar if (maxlvt > 3) 1138f62bae50SIngo Molnar /* Clear ESR due to Pentium errata 3AP and 11AP */ 1139f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1140f62bae50SIngo Molnar apic_read(APIC_ESR); 1141f62bae50SIngo Molnar } 1142f62bae50SIngo Molnar } 1143f62bae50SIngo Molnar 1144f62bae50SIngo Molnar /** 1145f62bae50SIngo Molnar * disable_local_APIC - clear and disable the local APIC 1146f62bae50SIngo Molnar */ 1147f62bae50SIngo Molnar void disable_local_APIC(void) 1148f62bae50SIngo Molnar { 1149f62bae50SIngo Molnar unsigned int value; 1150f62bae50SIngo Molnar 1151f62bae50SIngo Molnar /* APIC hasn't been mapped yet */ 1152fd19dce7SYinghai Lu if (!x2apic_mode && !apic_phys) 1153f62bae50SIngo Molnar return; 1154f62bae50SIngo Molnar 1155f62bae50SIngo Molnar clear_local_APIC(); 1156f62bae50SIngo Molnar 1157f62bae50SIngo Molnar /* 1158f62bae50SIngo Molnar * Disable APIC (implies clearing of registers 1159f62bae50SIngo Molnar * for 82489DX!). 1160f62bae50SIngo Molnar */ 1161f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 1162f62bae50SIngo Molnar value &= ~APIC_SPIV_APIC_ENABLED; 1163f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 1164f62bae50SIngo Molnar 1165f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1166f62bae50SIngo Molnar /* 1167f62bae50SIngo Molnar * When LAPIC was disabled by the BIOS and enabled by the kernel, 1168f62bae50SIngo Molnar * restore the disabled state. 1169f62bae50SIngo Molnar */ 1170f62bae50SIngo Molnar if (enabled_via_apicbase) { 1171f62bae50SIngo Molnar unsigned int l, h; 1172f62bae50SIngo Molnar 1173f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, l, h); 1174f62bae50SIngo Molnar l &= ~MSR_IA32_APICBASE_ENABLE; 1175f62bae50SIngo Molnar wrmsr(MSR_IA32_APICBASE, l, h); 1176f62bae50SIngo Molnar } 1177f62bae50SIngo Molnar #endif 1178f62bae50SIngo Molnar } 1179f62bae50SIngo Molnar 1180f62bae50SIngo Molnar /* 1181f62bae50SIngo Molnar * If Linux enabled the LAPIC against the BIOS default disable it down before 1182f62bae50SIngo Molnar * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 1183f62bae50SIngo Molnar * not power-off. Additionally clear all LVT entries before disable_local_APIC 1184f62bae50SIngo Molnar * for the case where Linux didn't enable the LAPIC. 1185f62bae50SIngo Molnar */ 1186f62bae50SIngo Molnar void lapic_shutdown(void) 1187f62bae50SIngo Molnar { 1188f62bae50SIngo Molnar unsigned long flags; 1189f62bae50SIngo Molnar 119093984fbdSBorislav Petkov if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) 1191f62bae50SIngo Molnar return; 1192f62bae50SIngo Molnar 1193f62bae50SIngo Molnar local_irq_save(flags); 1194f62bae50SIngo Molnar 1195f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1196f62bae50SIngo Molnar if (!enabled_via_apicbase) 1197f62bae50SIngo Molnar clear_local_APIC(); 1198f62bae50SIngo Molnar else 1199f62bae50SIngo Molnar #endif 1200f62bae50SIngo Molnar disable_local_APIC(); 1201f62bae50SIngo Molnar 1202f62bae50SIngo Molnar 1203f62bae50SIngo Molnar local_irq_restore(flags); 1204f62bae50SIngo Molnar } 1205f62bae50SIngo Molnar 1206f62bae50SIngo Molnar /** 1207f62bae50SIngo Molnar * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1208f62bae50SIngo Molnar */ 1209f62bae50SIngo Molnar void __init sync_Arb_IDs(void) 1210f62bae50SIngo Molnar { 1211f62bae50SIngo Molnar /* 1212f62bae50SIngo Molnar * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1213f62bae50SIngo Molnar * needed on AMD. 1214f62bae50SIngo Molnar */ 1215f62bae50SIngo Molnar if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1216f62bae50SIngo Molnar return; 1217f62bae50SIngo Molnar 1218f62bae50SIngo Molnar /* 1219f62bae50SIngo Molnar * Wait for idle. 1220f62bae50SIngo Molnar */ 1221f62bae50SIngo Molnar apic_wait_icr_idle(); 1222f62bae50SIngo Molnar 1223f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1224f62bae50SIngo Molnar apic_write(APIC_ICR, APIC_DEST_ALLINC | 1225f62bae50SIngo Molnar APIC_INT_LEVELTRIG | APIC_DM_INIT); 1226f62bae50SIngo Molnar } 1227f62bae50SIngo Molnar 12284f45ed9fSDou Liyang enum apic_intr_mode_id apic_intr_mode; 12290114a8e8SDou Liyang 12300114a8e8SDou Liyang static int __init apic_intr_mode_select(void) 1231f62bae50SIngo Molnar { 12320114a8e8SDou Liyang /* Check kernel option */ 12330114a8e8SDou Liyang if (disable_apic) { 12340114a8e8SDou Liyang pr_info("APIC disabled via kernel command line\n"); 12350114a8e8SDou Liyang return APIC_PIC; 12360114a8e8SDou Liyang } 1237f62bae50SIngo Molnar 12380114a8e8SDou Liyang /* Check BIOS */ 12390114a8e8SDou Liyang #ifdef CONFIG_X86_64 12400114a8e8SDou Liyang /* On 64-bit, the APIC must be integrated, Check local APIC only */ 12410114a8e8SDou Liyang if (!boot_cpu_has(X86_FEATURE_APIC)) { 12420114a8e8SDou Liyang disable_apic = 1; 12430114a8e8SDou Liyang pr_info("APIC disabled by BIOS\n"); 12440114a8e8SDou Liyang return APIC_PIC; 12450114a8e8SDou Liyang } 12460114a8e8SDou Liyang #else 12470114a8e8SDou Liyang /* On 32-bit, the APIC may be integrated APIC or 82489DX */ 1248f62bae50SIngo Molnar 12490114a8e8SDou Liyang /* Neither 82489DX nor integrated APIC ? */ 12500114a8e8SDou Liyang if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) { 12510114a8e8SDou Liyang disable_apic = 1; 12520114a8e8SDou Liyang return APIC_PIC; 12530114a8e8SDou Liyang } 1254f62bae50SIngo Molnar 12550114a8e8SDou Liyang /* If the BIOS pretends there is an integrated APIC ? */ 12560114a8e8SDou Liyang if (!boot_cpu_has(X86_FEATURE_APIC) && 12570114a8e8SDou Liyang APIC_INTEGRATED(boot_cpu_apic_version)) { 12580114a8e8SDou Liyang disable_apic = 1; 12590114a8e8SDou Liyang pr_err(FW_BUG "Local APIC %d not detected, force emulation\n", 12600114a8e8SDou Liyang boot_cpu_physical_apicid); 12610114a8e8SDou Liyang return APIC_PIC; 12620114a8e8SDou Liyang } 1263f62bae50SIngo Molnar #endif 1264f62bae50SIngo Molnar 12650114a8e8SDou Liyang /* Check MP table or ACPI MADT configuration */ 12660114a8e8SDou Liyang if (!smp_found_config) { 12670114a8e8SDou Liyang disable_ioapic_support(); 12683e730dadSDou Liyang if (!acpi_lapic) { 12690114a8e8SDou Liyang pr_info("APIC: ACPI MADT or MP tables are not detected\n"); 12703e730dadSDou Liyang return APIC_VIRTUAL_WIRE_NO_CONFIG; 12713e730dadSDou Liyang } 12720114a8e8SDou Liyang return APIC_VIRTUAL_WIRE; 12730114a8e8SDou Liyang } 12740114a8e8SDou Liyang 12753e730dadSDou Liyang #ifdef CONFIG_SMP 12763e730dadSDou Liyang /* If SMP should be disabled, then really disable it! */ 12773e730dadSDou Liyang if (!setup_max_cpus) { 12783e730dadSDou Liyang pr_info("APIC: SMP mode deactivated\n"); 12793e730dadSDou Liyang return APIC_SYMMETRIC_IO_NO_ROUTING; 12803e730dadSDou Liyang } 12813e730dadSDou Liyang 12823e730dadSDou Liyang if (read_apic_id() != boot_cpu_physical_apicid) { 12833e730dadSDou Liyang panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 12843e730dadSDou Liyang read_apic_id(), boot_cpu_physical_apicid); 12853e730dadSDou Liyang /* Or can we switch back to PIC here? */ 12863e730dadSDou Liyang } 12873e730dadSDou Liyang #endif 12883e730dadSDou Liyang 12890114a8e8SDou Liyang return APIC_SYMMETRIC_IO; 12900114a8e8SDou Liyang } 12910114a8e8SDou Liyang 1292fc90ccfdSVille Syrjälä /* 1293fc90ccfdSVille Syrjälä * An initial setup of the virtual wire mode. 1294fc90ccfdSVille Syrjälä */ 1295fc90ccfdSVille Syrjälä void __init init_bsp_APIC(void) 1296fc90ccfdSVille Syrjälä { 1297fc90ccfdSVille Syrjälä unsigned int value; 1298fc90ccfdSVille Syrjälä 1299fc90ccfdSVille Syrjälä /* 1300fc90ccfdSVille Syrjälä * Don't do the setup now if we have a SMP BIOS as the 1301fc90ccfdSVille Syrjälä * through-I/O-APIC virtual wire mode might be active. 1302fc90ccfdSVille Syrjälä */ 1303fc90ccfdSVille Syrjälä if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC)) 1304fc90ccfdSVille Syrjälä return; 1305fc90ccfdSVille Syrjälä 1306fc90ccfdSVille Syrjälä /* 1307fc90ccfdSVille Syrjälä * Do not trust the local APIC being empty at bootup. 1308fc90ccfdSVille Syrjälä */ 1309fc90ccfdSVille Syrjälä clear_local_APIC(); 1310fc90ccfdSVille Syrjälä 1311fc90ccfdSVille Syrjälä /* 1312fc90ccfdSVille Syrjälä * Enable APIC. 1313fc90ccfdSVille Syrjälä */ 1314fc90ccfdSVille Syrjälä value = apic_read(APIC_SPIV); 1315fc90ccfdSVille Syrjälä value &= ~APIC_VECTOR_MASK; 1316fc90ccfdSVille Syrjälä value |= APIC_SPIV_APIC_ENABLED; 1317fc90ccfdSVille Syrjälä 1318fc90ccfdSVille Syrjälä #ifdef CONFIG_X86_32 1319fc90ccfdSVille Syrjälä /* This bit is reserved on P4/Xeon and should be cleared */ 1320fc90ccfdSVille Syrjälä if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1321fc90ccfdSVille Syrjälä (boot_cpu_data.x86 == 15)) 1322fc90ccfdSVille Syrjälä value &= ~APIC_SPIV_FOCUS_DISABLED; 1323fc90ccfdSVille Syrjälä else 1324fc90ccfdSVille Syrjälä #endif 1325fc90ccfdSVille Syrjälä value |= APIC_SPIV_FOCUS_DISABLED; 1326fc90ccfdSVille Syrjälä value |= SPURIOUS_APIC_VECTOR; 1327fc90ccfdSVille Syrjälä apic_write(APIC_SPIV, value); 1328fc90ccfdSVille Syrjälä 1329fc90ccfdSVille Syrjälä /* 1330fc90ccfdSVille Syrjälä * Set up the virtual wire mode. 1331fc90ccfdSVille Syrjälä */ 1332fc90ccfdSVille Syrjälä apic_write(APIC_LVT0, APIC_DM_EXTINT); 1333fc90ccfdSVille Syrjälä value = APIC_DM_NMI; 1334fc90ccfdSVille Syrjälä if (!lapic_is_integrated()) /* 82489DX */ 1335fc90ccfdSVille Syrjälä value |= APIC_LVT_LEVEL_TRIGGER; 1336fc90ccfdSVille Syrjälä if (apic_extnmi == APIC_EXTNMI_NONE) 1337fc90ccfdSVille Syrjälä value |= APIC_LVT_MASKED; 1338fc90ccfdSVille Syrjälä apic_write(APIC_LVT1, value); 1339fc90ccfdSVille Syrjälä } 1340fc90ccfdSVille Syrjälä 13414b1669e8SDou Liyang /* Init the interrupt delivery mode for the BSP */ 13424b1669e8SDou Liyang void __init apic_intr_mode_init(void) 13434b1669e8SDou Liyang { 13440c759131SDou Liyang bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT); 13453e730dadSDou Liyang 13464f45ed9fSDou Liyang apic_intr_mode = apic_intr_mode_select(); 13474f45ed9fSDou Liyang 13484f45ed9fSDou Liyang switch (apic_intr_mode) { 13494b1669e8SDou Liyang case APIC_PIC: 13504b1669e8SDou Liyang pr_info("APIC: Keep in PIC mode(8259)\n"); 13514b1669e8SDou Liyang return; 13524b1669e8SDou Liyang case APIC_VIRTUAL_WIRE: 13534b1669e8SDou Liyang pr_info("APIC: Switch to virtual wire mode setup\n"); 13543e730dadSDou Liyang default_setup_apic_routing(); 13553e730dadSDou Liyang break; 13563e730dadSDou Liyang case APIC_VIRTUAL_WIRE_NO_CONFIG: 13573e730dadSDou Liyang pr_info("APIC: Switch to virtual wire mode setup with no configuration\n"); 13583e730dadSDou Liyang upmode = true; 13593e730dadSDou Liyang default_setup_apic_routing(); 13603e730dadSDou Liyang break; 13614b1669e8SDou Liyang case APIC_SYMMETRIC_IO: 136279761ce8SColin Ian King pr_info("APIC: Switch to symmetric I/O mode setup\n"); 13633e730dadSDou Liyang default_setup_apic_routing(); 13643e730dadSDou Liyang break; 13653e730dadSDou Liyang case APIC_SYMMETRIC_IO_NO_ROUTING: 136679761ce8SColin Ian King pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n"); 13673e730dadSDou Liyang break; 13684b1669e8SDou Liyang } 13693e730dadSDou Liyang 13703e730dadSDou Liyang apic_bsp_setup(upmode); 1371f62bae50SIngo Molnar } 1372f62bae50SIngo Molnar 1373148f9bb8SPaul Gortmaker static void lapic_setup_esr(void) 1374f62bae50SIngo Molnar { 1375f62bae50SIngo Molnar unsigned int oldvalue, value, maxlvt; 1376f62bae50SIngo Molnar 1377f62bae50SIngo Molnar if (!lapic_is_integrated()) { 1378f62bae50SIngo Molnar pr_info("No ESR for 82489DX.\n"); 1379f62bae50SIngo Molnar return; 1380f62bae50SIngo Molnar } 1381f62bae50SIngo Molnar 1382f62bae50SIngo Molnar if (apic->disable_esr) { 1383f62bae50SIngo Molnar /* 1384f62bae50SIngo Molnar * Something untraceable is creating bad interrupts on 1385f62bae50SIngo Molnar * secondary quads ... for the moment, just leave the 1386f62bae50SIngo Molnar * ESR disabled - we can't do anything useful with the 1387f62bae50SIngo Molnar * errors anyway - mbligh 1388f62bae50SIngo Molnar */ 1389f62bae50SIngo Molnar pr_info("Leaving ESR disabled.\n"); 1390f62bae50SIngo Molnar return; 1391f62bae50SIngo Molnar } 1392f62bae50SIngo Molnar 1393f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 1394f62bae50SIngo Molnar if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1395f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1396f62bae50SIngo Molnar oldvalue = apic_read(APIC_ESR); 1397f62bae50SIngo Molnar 1398f62bae50SIngo Molnar /* enables sending errors */ 1399f62bae50SIngo Molnar value = ERROR_APIC_VECTOR; 1400f62bae50SIngo Molnar apic_write(APIC_LVTERR, value); 1401f62bae50SIngo Molnar 1402f62bae50SIngo Molnar /* 1403f62bae50SIngo Molnar * spec says clear errors after enabling vector. 1404f62bae50SIngo Molnar */ 1405f62bae50SIngo Molnar if (maxlvt > 3) 1406f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1407f62bae50SIngo Molnar value = apic_read(APIC_ESR); 1408f62bae50SIngo Molnar if (value != oldvalue) 1409f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "ESR value before enabling " 1410f62bae50SIngo Molnar "vector: 0x%08x after: 0x%08x\n", 1411f62bae50SIngo Molnar oldvalue, value); 1412f62bae50SIngo Molnar } 1413f62bae50SIngo Molnar 14149b217f33SDou Liyang static void apic_pending_intr_clear(void) 14159b217f33SDou Liyang { 14169b217f33SDou Liyang long long max_loops = cpu_khz ? cpu_khz : 1000000; 14179b217f33SDou Liyang unsigned long long tsc = 0, ntsc; 14183ea9e7aeSDou Liyang unsigned int queued; 14193ea9e7aeSDou Liyang unsigned long value; 14209b217f33SDou Liyang int i, j, acked = 0; 14219b217f33SDou Liyang 14229b217f33SDou Liyang if (boot_cpu_has(X86_FEATURE_TSC)) 14239b217f33SDou Liyang tsc = rdtsc(); 14249b217f33SDou Liyang /* 14259b217f33SDou Liyang * After a crash, we no longer service the interrupts and a pending 14269b217f33SDou Liyang * interrupt from previous kernel might still have ISR bit set. 14279b217f33SDou Liyang * 14289b217f33SDou Liyang * Most probably by now CPU has serviced that pending interrupt and 14299b217f33SDou Liyang * it might not have done the ack_APIC_irq() because it thought, 14309b217f33SDou Liyang * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 14319b217f33SDou Liyang * does not clear the ISR bit and cpu thinks it has already serivced 14329b217f33SDou Liyang * the interrupt. Hence a vector might get locked. It was noticed 14339b217f33SDou Liyang * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 14349b217f33SDou Liyang */ 14359b217f33SDou Liyang do { 14369b217f33SDou Liyang queued = 0; 14379b217f33SDou Liyang for (i = APIC_ISR_NR - 1; i >= 0; i--) 14389b217f33SDou Liyang queued |= apic_read(APIC_IRR + i*0x10); 14399b217f33SDou Liyang 14409b217f33SDou Liyang for (i = APIC_ISR_NR - 1; i >= 0; i--) { 14419b217f33SDou Liyang value = apic_read(APIC_ISR + i*0x10); 14423ea9e7aeSDou Liyang for_each_set_bit(j, &value, 32) { 14439b217f33SDou Liyang ack_APIC_irq(); 14449b217f33SDou Liyang acked++; 14459b217f33SDou Liyang } 14469b217f33SDou Liyang } 14479b217f33SDou Liyang if (acked > 256) { 14483ea9e7aeSDou Liyang pr_err("LAPIC pending interrupts after %d EOI\n", acked); 14499b217f33SDou Liyang break; 14509b217f33SDou Liyang } 14519b217f33SDou Liyang if (queued) { 14529b217f33SDou Liyang if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) { 14539b217f33SDou Liyang ntsc = rdtsc(); 14549b217f33SDou Liyang max_loops = (cpu_khz << 10) - (ntsc - tsc); 14553ea9e7aeSDou Liyang } else { 14569b217f33SDou Liyang max_loops--; 14579b217f33SDou Liyang } 14583ea9e7aeSDou Liyang } 14599b217f33SDou Liyang } while (queued && max_loops > 0); 14609b217f33SDou Liyang WARN_ON(max_loops <= 0); 14619b217f33SDou Liyang } 14629b217f33SDou Liyang 1463f62bae50SIngo Molnar /** 1464f62bae50SIngo Molnar * setup_local_APIC - setup the local APIC 14650aa002feSTejun Heo * 1466543113d2SDou Liyang * Used to setup local APIC while initializing BSP or bringing up APs. 14670aa002feSTejun Heo * Always called with preemption disabled. 1468f62bae50SIngo Molnar */ 1469b753a2b7SDou Liyang static void setup_local_APIC(void) 1470f62bae50SIngo Molnar { 14710aa002feSTejun Heo int cpu = smp_processor_id(); 14729b217f33SDou Liyang unsigned int value; 14739b217f33SDou Liyang #ifdef CONFIG_X86_32 14748f156168SDou Liyang int logical_apicid, ldr_apicid; 14759b217f33SDou Liyang #endif 14768c3ba8d0SKerstin Jonsson 1477f62bae50SIngo Molnar 1478f62bae50SIngo Molnar if (disable_apic) { 14797167d08eSHenrik Kretzschmar disable_ioapic_support(); 1480f62bae50SIngo Molnar return; 1481f62bae50SIngo Molnar } 1482f62bae50SIngo Molnar 1483f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1484f62bae50SIngo Molnar /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1485f62bae50SIngo Molnar if (lapic_is_integrated() && apic->disable_esr) { 1486f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1487f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1488f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1489f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1490f62bae50SIngo Molnar } 1491f62bae50SIngo Molnar #endif 1492cdd6c482SIngo Molnar perf_events_lapic_init(); 1493f62bae50SIngo Molnar 1494f62bae50SIngo Molnar /* 1495f62bae50SIngo Molnar * Double-check whether this APIC is really registered. 1496f62bae50SIngo Molnar * This is meaningless in clustered apic mode, so we skip it. 1497f62bae50SIngo Molnar */ 1498c2777f98SDaniel Walker BUG_ON(!apic->apic_id_registered()); 1499f62bae50SIngo Molnar 1500f62bae50SIngo Molnar /* 1501f62bae50SIngo Molnar * Intel recommends to set DFR, LDR and TPR before enabling 1502f62bae50SIngo Molnar * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1503f62bae50SIngo Molnar * document number 292116). So here it goes... 1504f62bae50SIngo Molnar */ 1505f62bae50SIngo Molnar apic->init_apic_ldr(); 1506f62bae50SIngo Molnar 15076f802c4bSTejun Heo #ifdef CONFIG_X86_32 15086f802c4bSTejun Heo /* 1509acb8bc09STejun Heo * APIC LDR is initialized. If logical_apicid mapping was 1510acb8bc09STejun Heo * initialized during get_smp_config(), make sure it matches the 1511acb8bc09STejun Heo * actual value. 15126f802c4bSTejun Heo */ 15138f156168SDou Liyang logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu); 15148f156168SDou Liyang ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 15158f156168SDou Liyang WARN_ON(logical_apicid != BAD_APICID && logical_apicid != ldr_apicid); 1516acb8bc09STejun Heo /* always use the value from LDR */ 15178f156168SDou Liyang early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid; 15186f802c4bSTejun Heo #endif 15196f802c4bSTejun Heo 1520f62bae50SIngo Molnar /* 1521f62bae50SIngo Molnar * Set Task Priority to 'accept all'. We never change this 1522f62bae50SIngo Molnar * later on. 1523f62bae50SIngo Molnar */ 1524f62bae50SIngo Molnar value = apic_read(APIC_TASKPRI); 1525f62bae50SIngo Molnar value &= ~APIC_TPRI_MASK; 1526f62bae50SIngo Molnar apic_write(APIC_TASKPRI, value); 1527f62bae50SIngo Molnar 15289b217f33SDou Liyang apic_pending_intr_clear(); 1529f62bae50SIngo Molnar 1530f62bae50SIngo Molnar /* 1531f62bae50SIngo Molnar * Now that we are all set up, enable the APIC 1532f62bae50SIngo Molnar */ 1533f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 1534f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 1535f62bae50SIngo Molnar /* 1536f62bae50SIngo Molnar * Enable APIC 1537f62bae50SIngo Molnar */ 1538f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 1539f62bae50SIngo Molnar 1540f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1541f62bae50SIngo Molnar /* 1542f62bae50SIngo Molnar * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1543f62bae50SIngo Molnar * certain networking cards. If high frequency interrupts are 1544f62bae50SIngo Molnar * happening on a particular IOAPIC pin, plus the IOAPIC routing 1545f62bae50SIngo Molnar * entry is masked/unmasked at a high rate as well then sooner or 1546f62bae50SIngo Molnar * later IOAPIC line gets 'stuck', no more interrupts are received 1547f62bae50SIngo Molnar * from the device. If focus CPU is disabled then the hang goes 1548f62bae50SIngo Molnar * away, oh well :-( 1549f62bae50SIngo Molnar * 1550f62bae50SIngo Molnar * [ This bug can be reproduced easily with a level-triggered 1551f62bae50SIngo Molnar * PCI Ne2000 networking cards and PII/PIII processors, dual 1552f62bae50SIngo Molnar * BX chipset. ] 1553f62bae50SIngo Molnar */ 1554f62bae50SIngo Molnar /* 1555f62bae50SIngo Molnar * Actually disabling the focus CPU check just makes the hang less 1556f62bae50SIngo Molnar * frequent as it makes the interrupt distributon model be more 1557f62bae50SIngo Molnar * like LRU than MRU (the short-term load is more even across CPUs). 1558f62bae50SIngo Molnar */ 1559f62bae50SIngo Molnar 1560f62bae50SIngo Molnar /* 1561f62bae50SIngo Molnar * - enable focus processor (bit==0) 1562f62bae50SIngo Molnar * - 64bit mode always use processor focus 1563f62bae50SIngo Molnar * so no need to set it 1564f62bae50SIngo Molnar */ 1565f62bae50SIngo Molnar value &= ~APIC_SPIV_FOCUS_DISABLED; 1566f62bae50SIngo Molnar #endif 1567f62bae50SIngo Molnar 1568f62bae50SIngo Molnar /* 1569f62bae50SIngo Molnar * Set spurious IRQ vector 1570f62bae50SIngo Molnar */ 1571f62bae50SIngo Molnar value |= SPURIOUS_APIC_VECTOR; 1572f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 1573f62bae50SIngo Molnar 1574f62bae50SIngo Molnar /* 1575f62bae50SIngo Molnar * Set up LVT0, LVT1: 1576f62bae50SIngo Molnar * 1577a1652bb8SJean Delvare * set up through-local-APIC on the boot CPU's LINT0. This is not 1578f62bae50SIngo Molnar * strictly necessary in pure symmetric-IO mode, but sometimes 1579f62bae50SIngo Molnar * we delegate interrupts to the 8259A. 1580f62bae50SIngo Molnar */ 1581f62bae50SIngo Molnar /* 1582f62bae50SIngo Molnar * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1583f62bae50SIngo Molnar */ 1584f62bae50SIngo Molnar value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1585bee3204eSBaoquan He if (!cpu && (pic_mode || !value || skip_ioapic_setup)) { 1586f62bae50SIngo Molnar value = APIC_DM_EXTINT; 15870aa002feSTejun Heo apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1588f62bae50SIngo Molnar } else { 1589f62bae50SIngo Molnar value = APIC_DM_EXTINT | APIC_LVT_MASKED; 15900aa002feSTejun Heo apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1591f62bae50SIngo Molnar } 1592f62bae50SIngo Molnar apic_write(APIC_LVT0, value); 1593f62bae50SIngo Molnar 1594f62bae50SIngo Molnar /* 1595b7c4948eSHidehiro Kawai * Only the BSP sees the LINT1 NMI signal by default. This can be 1596b7c4948eSHidehiro Kawai * modified by apic_extnmi= boot option. 1597f62bae50SIngo Molnar */ 1598b7c4948eSHidehiro Kawai if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) || 1599b7c4948eSHidehiro Kawai apic_extnmi == APIC_EXTNMI_ALL) 1600f62bae50SIngo Molnar value = APIC_DM_NMI; 1601f62bae50SIngo Molnar else 1602f62bae50SIngo Molnar value = APIC_DM_NMI | APIC_LVT_MASKED; 1603ae41a2a4SDou Liyang 1604ae41a2a4SDou Liyang /* Is 82489DX ? */ 1605ae41a2a4SDou Liyang if (!lapic_is_integrated()) 1606f62bae50SIngo Molnar value |= APIC_LVT_LEVEL_TRIGGER; 1607f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 1608f62bae50SIngo Molnar 1609638bee71SH. Peter Anvin #ifdef CONFIG_X86_MCE_INTEL 1610638bee71SH. Peter Anvin /* Recheck CMCI information after local APIC is up on CPU #0 */ 16110aa002feSTejun Heo if (!cpu) 1612638bee71SH. Peter Anvin cmci_recheck(); 1613638bee71SH. Peter Anvin #endif 1614f62bae50SIngo Molnar } 1615f62bae50SIngo Molnar 161605f7e46dSThomas Gleixner static void end_local_APIC_setup(void) 1617f62bae50SIngo Molnar { 1618f62bae50SIngo Molnar lapic_setup_esr(); 1619f62bae50SIngo Molnar 1620f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1621f62bae50SIngo Molnar { 1622f62bae50SIngo Molnar unsigned int value; 1623f62bae50SIngo Molnar /* Disable the local apic timer */ 1624f62bae50SIngo Molnar value = apic_read(APIC_LVTT); 1625f62bae50SIngo Molnar value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1626f62bae50SIngo Molnar apic_write(APIC_LVTT, value); 1627f62bae50SIngo Molnar } 1628f62bae50SIngo Molnar #endif 1629f62bae50SIngo Molnar 1630f62bae50SIngo Molnar apic_pm_activate(); 16312fb270f3SJan Beulich } 16322fb270f3SJan Beulich 16337f7fbf45SKenji Kaneshige /* 163405f7e46dSThomas Gleixner * APIC setup function for application processors. Called from smpboot.c 16357f7fbf45SKenji Kaneshige */ 163605f7e46dSThomas Gleixner void apic_ap_setup(void) 163705f7e46dSThomas Gleixner { 163805f7e46dSThomas Gleixner setup_local_APIC(); 163905f7e46dSThomas Gleixner end_local_APIC_setup(); 1640f62bae50SIngo Molnar } 1641f62bae50SIngo Molnar 1642f62bae50SIngo Molnar #ifdef CONFIG_X86_X2APIC 1643bfb05070SThomas Gleixner int x2apic_mode; 164412e189d3SThomas Gleixner 164512e189d3SThomas Gleixner enum { 164612e189d3SThomas Gleixner X2APIC_OFF, 164712e189d3SThomas Gleixner X2APIC_ON, 164812e189d3SThomas Gleixner X2APIC_DISABLED, 164912e189d3SThomas Gleixner }; 165012e189d3SThomas Gleixner static int x2apic_state; 165112e189d3SThomas Gleixner 1652d786ad32SDenys Vlasenko static void __x2apic_disable(void) 165344e25ff9SThomas Gleixner { 165444e25ff9SThomas Gleixner u64 msr; 165544e25ff9SThomas Gleixner 165693984fbdSBorislav Petkov if (!boot_cpu_has(X86_FEATURE_APIC)) 1657659006bfSThomas Gleixner return; 1658659006bfSThomas Gleixner 165944e25ff9SThomas Gleixner rdmsrl(MSR_IA32_APICBASE, msr); 166044e25ff9SThomas Gleixner if (!(msr & X2APIC_ENABLE)) 166144e25ff9SThomas Gleixner return; 166244e25ff9SThomas Gleixner /* Disable xapic and x2apic first and then reenable xapic mode */ 166344e25ff9SThomas Gleixner wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); 166444e25ff9SThomas Gleixner wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); 166544e25ff9SThomas Gleixner printk_once(KERN_INFO "x2apic disabled\n"); 166644e25ff9SThomas Gleixner } 166744e25ff9SThomas Gleixner 1668d786ad32SDenys Vlasenko static void __x2apic_enable(void) 1669659006bfSThomas Gleixner { 1670659006bfSThomas Gleixner u64 msr; 1671659006bfSThomas Gleixner 1672659006bfSThomas Gleixner rdmsrl(MSR_IA32_APICBASE, msr); 1673659006bfSThomas Gleixner if (msr & X2APIC_ENABLE) 1674659006bfSThomas Gleixner return; 1675659006bfSThomas Gleixner wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); 1676659006bfSThomas Gleixner printk_once(KERN_INFO "x2apic enabled\n"); 1677659006bfSThomas Gleixner } 1678659006bfSThomas Gleixner 1679bfb05070SThomas Gleixner static int __init setup_nox2apic(char *str) 1680bfb05070SThomas Gleixner { 1681bfb05070SThomas Gleixner if (x2apic_enabled()) { 1682bfb05070SThomas Gleixner int apicid = native_apic_msr_read(APIC_ID); 1683bfb05070SThomas Gleixner 1684bfb05070SThomas Gleixner if (apicid >= 255) { 1685bfb05070SThomas Gleixner pr_warning("Apicid: %08x, cannot enforce nox2apic\n", 1686bfb05070SThomas Gleixner apicid); 1687bfb05070SThomas Gleixner return 0; 1688bfb05070SThomas Gleixner } 168944e25ff9SThomas Gleixner pr_warning("x2apic already enabled.\n"); 169044e25ff9SThomas Gleixner __x2apic_disable(); 169144e25ff9SThomas Gleixner } 1692bfb05070SThomas Gleixner setup_clear_cpu_cap(X86_FEATURE_X2APIC); 169312e189d3SThomas Gleixner x2apic_state = X2APIC_DISABLED; 169444e25ff9SThomas Gleixner x2apic_mode = 0; 1695bfb05070SThomas Gleixner return 0; 1696bfb05070SThomas Gleixner } 1697bfb05070SThomas Gleixner early_param("nox2apic", setup_nox2apic); 1698bfb05070SThomas Gleixner 1699659006bfSThomas Gleixner /* Called from cpu_init() to enable x2apic on (secondary) cpus */ 1700659006bfSThomas Gleixner void x2apic_setup(void) 1701659006bfSThomas Gleixner { 1702659006bfSThomas Gleixner /* 1703659006bfSThomas Gleixner * If x2apic is not in ON state, disable it if already enabled 1704659006bfSThomas Gleixner * from BIOS. 1705659006bfSThomas Gleixner */ 1706659006bfSThomas Gleixner if (x2apic_state != X2APIC_ON) { 1707659006bfSThomas Gleixner __x2apic_disable(); 1708659006bfSThomas Gleixner return; 1709659006bfSThomas Gleixner } 1710659006bfSThomas Gleixner __x2apic_enable(); 1711659006bfSThomas Gleixner } 1712659006bfSThomas Gleixner 171344e25ff9SThomas Gleixner static __init void x2apic_disable(void) 1714fb209bd8SYinghai Lu { 1715a57e456aSThomas Gleixner u32 x2apic_id, state = x2apic_state; 1716fb209bd8SYinghai Lu 1717a57e456aSThomas Gleixner x2apic_mode = 0; 1718a57e456aSThomas Gleixner x2apic_state = X2APIC_DISABLED; 1719a57e456aSThomas Gleixner 1720a57e456aSThomas Gleixner if (state != X2APIC_ON) 1721a57e456aSThomas Gleixner return; 1722fb209bd8SYinghai Lu 17236d2d49d2SThomas Gleixner x2apic_id = read_apic_id(); 1724fb209bd8SYinghai Lu if (x2apic_id >= 255) 1725fb209bd8SYinghai Lu panic("Cannot disable x2apic, id: %08x\n", x2apic_id); 1726fb209bd8SYinghai Lu 172744e25ff9SThomas Gleixner __x2apic_disable(); 1728fb209bd8SYinghai Lu register_lapic_address(mp_lapic_addr); 1729fb209bd8SYinghai Lu } 1730fb209bd8SYinghai Lu 1731659006bfSThomas Gleixner static __init void x2apic_enable(void) 1732f62bae50SIngo Molnar { 1733659006bfSThomas Gleixner if (x2apic_state != X2APIC_OFF) 1734f62bae50SIngo Molnar return; 1735f62bae50SIngo Molnar 1736659006bfSThomas Gleixner x2apic_mode = 1; 173712e189d3SThomas Gleixner x2apic_state = X2APIC_ON; 1738659006bfSThomas Gleixner __x2apic_enable(); 1739f62bae50SIngo Molnar } 1740d524165cSThomas Gleixner 174162e61633SThomas Gleixner static __init void try_to_enable_x2apic(int remap_mode) 174207806c50SJiang Liu { 1743659006bfSThomas Gleixner if (x2apic_state == X2APIC_DISABLED) 174407806c50SJiang Liu return; 174507806c50SJiang Liu 174662e61633SThomas Gleixner if (remap_mode != IRQ_REMAP_X2APIC_MODE) { 174707806c50SJiang Liu /* IR is required if there is APIC ID > 255 even when running 174807806c50SJiang Liu * under KVM 174907806c50SJiang Liu */ 175007806c50SJiang Liu if (max_physical_apicid > 255 || 1751f72e38e8SJuergen Gross !x86_init.hyper.x2apic_available()) { 175262e61633SThomas Gleixner pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); 175344e25ff9SThomas Gleixner x2apic_disable(); 175407806c50SJiang Liu return; 175507806c50SJiang Liu } 175607806c50SJiang Liu 175707806c50SJiang Liu /* 175807806c50SJiang Liu * without IR all CPUs can be addressed by IOAPIC/MSI 175907806c50SJiang Liu * only in physical mode 176007806c50SJiang Liu */ 176155eae7deSThomas Gleixner x2apic_phys = 1; 176207806c50SJiang Liu } 1763659006bfSThomas Gleixner x2apic_enable(); 176455eae7deSThomas Gleixner } 176555eae7deSThomas Gleixner 176655eae7deSThomas Gleixner void __init check_x2apic(void) 176755eae7deSThomas Gleixner { 176855eae7deSThomas Gleixner if (x2apic_enabled()) { 176955eae7deSThomas Gleixner pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); 177055eae7deSThomas Gleixner x2apic_mode = 1; 177112e189d3SThomas Gleixner x2apic_state = X2APIC_ON; 177262436a4dSBorislav Petkov } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) { 177312e189d3SThomas Gleixner x2apic_state = X2APIC_DISABLED; 177455eae7deSThomas Gleixner } 177555eae7deSThomas Gleixner } 177655eae7deSThomas Gleixner #else /* CONFIG_X86_X2APIC */ 177755eae7deSThomas Gleixner static int __init validate_x2apic(void) 177855eae7deSThomas Gleixner { 177955eae7deSThomas Gleixner if (!apic_is_x2apic_enabled()) 178055eae7deSThomas Gleixner return 0; 178155eae7deSThomas Gleixner /* 178255eae7deSThomas Gleixner * Checkme: Can we simply turn off x2apic here instead of panic? 178355eae7deSThomas Gleixner */ 178455eae7deSThomas Gleixner panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n"); 178555eae7deSThomas Gleixner } 178655eae7deSThomas Gleixner early_initcall(validate_x2apic); 178755eae7deSThomas Gleixner 178862e61633SThomas Gleixner static inline void try_to_enable_x2apic(int remap_mode) { } 1789659006bfSThomas Gleixner static inline void __x2apic_enable(void) { } 179055eae7deSThomas Gleixner #endif /* !CONFIG_X86_X2APIC */ 179155eae7deSThomas Gleixner 1792ce69a784SGleb Natapov void __init enable_IR_x2apic(void) 1793ce69a784SGleb Natapov { 1794ce69a784SGleb Natapov unsigned long flags; 179507806c50SJiang Liu int ret, ir_stat; 1796b7f42ab2SYinghai Lu 179711277aabSDou Liyang if (skip_ioapic_setup) { 179811277aabSDou Liyang pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); 17992e63ad4bSWanpeng Li return; 180011277aabSDou Liyang } 18012e63ad4bSWanpeng Li 180207806c50SJiang Liu ir_stat = irq_remapping_prepare(); 180307806c50SJiang Liu if (ir_stat < 0 && !x2apic_supported()) 1804e670761fSYinghai Lu return; 1805ce69a784SGleb Natapov 180631dce14aSSuresh Siddha ret = save_ioapic_entries(); 1807f62bae50SIngo Molnar if (ret) { 1808f62bae50SIngo Molnar pr_info("Saving IO-APIC state failed: %d\n", ret); 1809fb209bd8SYinghai Lu return; 1810f62bae50SIngo Molnar } 1811f62bae50SIngo Molnar 181205c3dc2cSSuresh Siddha local_irq_save(flags); 1813b81bb373SJacob Pan legacy_pic->mask_all(); 181431dce14aSSuresh Siddha mask_ioapic_entries(); 181505c3dc2cSSuresh Siddha 18166a6256f9SAdam Buchbinder /* If irq_remapping_prepare() succeeded, try to enable it */ 181707806c50SJiang Liu if (ir_stat >= 0) 181811277aabSDou Liyang ir_stat = irq_remapping_enable(); 181907806c50SJiang Liu /* ir_stat contains the remap mode or an error code */ 182007806c50SJiang Liu try_to_enable_x2apic(ir_stat); 1821a31bc327SYinghai Lu 182207806c50SJiang Liu if (ir_stat < 0) 182331dce14aSSuresh Siddha restore_ioapic_entries(); 1824b81bb373SJacob Pan legacy_pic->restore_mask(); 1825f62bae50SIngo Molnar local_irq_restore(flags); 1826f62bae50SIngo Molnar } 182793758238SWeidong Han 1828f62bae50SIngo Molnar #ifdef CONFIG_X86_64 1829f62bae50SIngo Molnar /* 1830f62bae50SIngo Molnar * Detect and enable local APICs on non-SMP boards. 1831f62bae50SIngo Molnar * Original code written by Keir Fraser. 1832f62bae50SIngo Molnar * On AMD64 we trust the BIOS - if it says no APIC it is likely 1833f62bae50SIngo Molnar * not correctly set up (usually the APIC timer won't work etc.) 1834f62bae50SIngo Molnar */ 1835f62bae50SIngo Molnar static int __init detect_init_APIC(void) 1836f62bae50SIngo Molnar { 183793984fbdSBorislav Petkov if (!boot_cpu_has(X86_FEATURE_APIC)) { 1838f62bae50SIngo Molnar pr_info("No local APIC present\n"); 1839f62bae50SIngo Molnar return -1; 1840f62bae50SIngo Molnar } 1841f62bae50SIngo Molnar 1842f62bae50SIngo Molnar mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1843f62bae50SIngo Molnar return 0; 1844f62bae50SIngo Molnar } 1845f62bae50SIngo Molnar #else 18465a7ae78fSThomas Gleixner 184725874a29SHenrik Kretzschmar static int __init apic_verify(void) 18485a7ae78fSThomas Gleixner { 18495a7ae78fSThomas Gleixner u32 features, h, l; 18505a7ae78fSThomas Gleixner 18515a7ae78fSThomas Gleixner /* 18525a7ae78fSThomas Gleixner * The APIC feature bit should now be enabled 18535a7ae78fSThomas Gleixner * in `cpuid' 18545a7ae78fSThomas Gleixner */ 18555a7ae78fSThomas Gleixner features = cpuid_edx(1); 18565a7ae78fSThomas Gleixner if (!(features & (1 << X86_FEATURE_APIC))) { 18575a7ae78fSThomas Gleixner pr_warning("Could not enable APIC!\n"); 18585a7ae78fSThomas Gleixner return -1; 18595a7ae78fSThomas Gleixner } 18605a7ae78fSThomas Gleixner set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 18615a7ae78fSThomas Gleixner mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 18625a7ae78fSThomas Gleixner 18635a7ae78fSThomas Gleixner /* The BIOS may have set up the APIC at some other address */ 1864cbf2829bSBryan O'Donoghue if (boot_cpu_data.x86 >= 6) { 18655a7ae78fSThomas Gleixner rdmsr(MSR_IA32_APICBASE, l, h); 18665a7ae78fSThomas Gleixner if (l & MSR_IA32_APICBASE_ENABLE) 18675a7ae78fSThomas Gleixner mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1868cbf2829bSBryan O'Donoghue } 18695a7ae78fSThomas Gleixner 18705a7ae78fSThomas Gleixner pr_info("Found and enabled local APIC!\n"); 18715a7ae78fSThomas Gleixner return 0; 18725a7ae78fSThomas Gleixner } 18735a7ae78fSThomas Gleixner 187425874a29SHenrik Kretzschmar int __init apic_force_enable(unsigned long addr) 18755a7ae78fSThomas Gleixner { 18765a7ae78fSThomas Gleixner u32 h, l; 18775a7ae78fSThomas Gleixner 18785a7ae78fSThomas Gleixner if (disable_apic) 18795a7ae78fSThomas Gleixner return -1; 18805a7ae78fSThomas Gleixner 18815a7ae78fSThomas Gleixner /* 18825a7ae78fSThomas Gleixner * Some BIOSes disable the local APIC in the APIC_BASE 18835a7ae78fSThomas Gleixner * MSR. This can only be done in software for Intel P6 or later 18845a7ae78fSThomas Gleixner * and AMD K7 (Model > 1) or later. 18855a7ae78fSThomas Gleixner */ 1886cbf2829bSBryan O'Donoghue if (boot_cpu_data.x86 >= 6) { 18875a7ae78fSThomas Gleixner rdmsr(MSR_IA32_APICBASE, l, h); 18885a7ae78fSThomas Gleixner if (!(l & MSR_IA32_APICBASE_ENABLE)) { 18895a7ae78fSThomas Gleixner pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 18905a7ae78fSThomas Gleixner l &= ~MSR_IA32_APICBASE_BASE; 1891a906fdaaSThomas Gleixner l |= MSR_IA32_APICBASE_ENABLE | addr; 18925a7ae78fSThomas Gleixner wrmsr(MSR_IA32_APICBASE, l, h); 18935a7ae78fSThomas Gleixner enabled_via_apicbase = 1; 18945a7ae78fSThomas Gleixner } 1895cbf2829bSBryan O'Donoghue } 18965a7ae78fSThomas Gleixner return apic_verify(); 18975a7ae78fSThomas Gleixner } 18985a7ae78fSThomas Gleixner 1899f62bae50SIngo Molnar /* 1900f62bae50SIngo Molnar * Detect and initialize APIC 1901f62bae50SIngo Molnar */ 1902f62bae50SIngo Molnar static int __init detect_init_APIC(void) 1903f62bae50SIngo Molnar { 1904f62bae50SIngo Molnar /* Disabled by kernel option? */ 1905f62bae50SIngo Molnar if (disable_apic) 1906f62bae50SIngo Molnar return -1; 1907f62bae50SIngo Molnar 1908f62bae50SIngo Molnar switch (boot_cpu_data.x86_vendor) { 1909f62bae50SIngo Molnar case X86_VENDOR_AMD: 1910f62bae50SIngo Molnar if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1911f62bae50SIngo Molnar (boot_cpu_data.x86 >= 15)) 1912f62bae50SIngo Molnar break; 1913f62bae50SIngo Molnar goto no_apic; 1914f62bae50SIngo Molnar case X86_VENDOR_INTEL: 1915f62bae50SIngo Molnar if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 191693984fbdSBorislav Petkov (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC))) 1917f62bae50SIngo Molnar break; 1918f62bae50SIngo Molnar goto no_apic; 1919f62bae50SIngo Molnar default: 1920f62bae50SIngo Molnar goto no_apic; 1921f62bae50SIngo Molnar } 1922f62bae50SIngo Molnar 192393984fbdSBorislav Petkov if (!boot_cpu_has(X86_FEATURE_APIC)) { 1924f62bae50SIngo Molnar /* 1925f62bae50SIngo Molnar * Over-ride BIOS and try to enable the local APIC only if 1926f62bae50SIngo Molnar * "lapic" specified. 1927f62bae50SIngo Molnar */ 1928f62bae50SIngo Molnar if (!force_enable_local_apic) { 1929f62bae50SIngo Molnar pr_info("Local APIC disabled by BIOS -- " 1930f62bae50SIngo Molnar "you can enable it with \"lapic\"\n"); 1931f62bae50SIngo Molnar return -1; 1932f62bae50SIngo Molnar } 1933a906fdaaSThomas Gleixner if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) 19345a7ae78fSThomas Gleixner return -1; 19355a7ae78fSThomas Gleixner } else { 19365a7ae78fSThomas Gleixner if (apic_verify()) 1937f62bae50SIngo Molnar return -1; 1938f62bae50SIngo Molnar } 1939f62bae50SIngo Molnar 1940f62bae50SIngo Molnar apic_pm_activate(); 1941f62bae50SIngo Molnar 1942f62bae50SIngo Molnar return 0; 1943f62bae50SIngo Molnar 1944f62bae50SIngo Molnar no_apic: 1945f62bae50SIngo Molnar pr_info("No local APIC present or hardware disabled\n"); 1946f62bae50SIngo Molnar return -1; 1947f62bae50SIngo Molnar } 1948f62bae50SIngo Molnar #endif 1949f62bae50SIngo Molnar 1950f62bae50SIngo Molnar /** 1951f62bae50SIngo Molnar * init_apic_mappings - initialize APIC mappings 1952f62bae50SIngo Molnar */ 1953f62bae50SIngo Molnar void __init init_apic_mappings(void) 1954f62bae50SIngo Molnar { 19554401da61SYinghai Lu unsigned int new_apicid; 19564401da61SYinghai Lu 1957bd9240a1SPeter Zijlstra apic_check_deadline_errata(); 1958bd9240a1SPeter Zijlstra 1959fc1edaf9SSuresh Siddha if (x2apic_mode) { 1960f62bae50SIngo Molnar boot_cpu_physical_apicid = read_apic_id(); 1961f62bae50SIngo Molnar return; 1962f62bae50SIngo Molnar } 1963f62bae50SIngo Molnar 19644797f6b0SYinghai Lu /* If no local APIC can be found return early */ 1965f62bae50SIngo Molnar if (!smp_found_config && detect_init_APIC()) { 19664797f6b0SYinghai Lu /* lets NOP'ify apic operations */ 19674797f6b0SYinghai Lu pr_info("APIC: disable apic facility\n"); 19684797f6b0SYinghai Lu apic_disable(); 19694797f6b0SYinghai Lu } else { 1970f62bae50SIngo Molnar apic_phys = mp_lapic_addr; 1971f62bae50SIngo Molnar 19724401da61SYinghai Lu /* 19735ba039a5SDou Liyang * If the system has ACPI MADT tables or MP info, the LAPIC 19745ba039a5SDou Liyang * address is already registered. 19754401da61SYinghai Lu */ 19765989cd6aSEric W. Biederman if (!acpi_lapic && !smp_found_config) 1977326a2e6bSYinghai Lu register_lapic_address(apic_phys); 1978cec6be6dSCyrill Gorcunov } 1979f62bae50SIngo Molnar 1980f62bae50SIngo Molnar /* 1981f62bae50SIngo Molnar * Fetch the APIC ID of the BSP in case we have a 1982f62bae50SIngo Molnar * default configuration (or the MP table is broken). 1983f62bae50SIngo Molnar */ 19844401da61SYinghai Lu new_apicid = read_apic_id(); 19854401da61SYinghai Lu if (boot_cpu_physical_apicid != new_apicid) { 19864401da61SYinghai Lu boot_cpu_physical_apicid = new_apicid; 1987103428e5SCyrill Gorcunov /* 1988103428e5SCyrill Gorcunov * yeah -- we lie about apic_version 1989103428e5SCyrill Gorcunov * in case if apic was disabled via boot option 1990103428e5SCyrill Gorcunov * but it's not a problem for SMP compiled kernel 19914f45ed9fSDou Liyang * since apic_intr_mode_select is prepared for such 19924f45ed9fSDou Liyang * a case and disable smp mode 1993103428e5SCyrill Gorcunov */ 1994cff9ab2bSDenys Vlasenko boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 199508306ce6SCyrill Gorcunov } 1996f62bae50SIngo Molnar } 1997f62bae50SIngo Molnar 1998c0104d38SYinghai Lu void __init register_lapic_address(unsigned long address) 1999c0104d38SYinghai Lu { 2000c0104d38SYinghai Lu mp_lapic_addr = address; 2001c0104d38SYinghai Lu 20020450193bSYinghai Lu if (!x2apic_mode) { 2003c0104d38SYinghai Lu set_fixmap_nocache(FIX_APIC_BASE, address); 2004f1157141SYinghai Lu apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 20056de42119SBaoquan He APIC_BASE, address); 20060450193bSYinghai Lu } 2007c0104d38SYinghai Lu if (boot_cpu_physical_apicid == -1U) { 2008c0104d38SYinghai Lu boot_cpu_physical_apicid = read_apic_id(); 2009cff9ab2bSDenys Vlasenko boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 2010c0104d38SYinghai Lu } 2011c0104d38SYinghai Lu } 2012c0104d38SYinghai Lu 2013f62bae50SIngo Molnar /* 2014f62bae50SIngo Molnar * Local APIC interrupts 2015f62bae50SIngo Molnar */ 2016f62bae50SIngo Molnar 2017f62bae50SIngo Molnar /* 2018f62bae50SIngo Molnar * This interrupt should _never_ happen with our APIC/SMP architecture 2019f62bae50SIngo Molnar */ 202061069de7SThomas Gleixner __visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs) 2021f62bae50SIngo Molnar { 202261069de7SThomas Gleixner u8 vector = ~regs->orig_ax; 2023f62bae50SIngo Molnar u32 v; 2024f62bae50SIngo Molnar 202561069de7SThomas Gleixner entering_irq(); 202661069de7SThomas Gleixner trace_spurious_apic_entry(vector); 202761069de7SThomas Gleixner 2028f62bae50SIngo Molnar /* 2029f62bae50SIngo Molnar * Check if this really is a spurious interrupt and ACK it 2030f62bae50SIngo Molnar * if it is a vectored one. Just in case... 2031f62bae50SIngo Molnar * Spurious interrupts should not be ACKed. 2032f62bae50SIngo Molnar */ 20332414e021SJan Beulich v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); 20342414e021SJan Beulich if (v & (1 << (vector & 0x1f))) 2035f62bae50SIngo Molnar ack_APIC_irq(); 2036f62bae50SIngo Molnar 2037f62bae50SIngo Molnar inc_irq_stat(irq_spurious_count); 2038f62bae50SIngo Molnar 2039f62bae50SIngo Molnar /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 20402414e021SJan Beulich pr_info("spurious APIC interrupt through vector %02x on CPU#%d, " 20412414e021SJan Beulich "should never happen.\n", vector, smp_processor_id()); 2042eddc0e92SSeiji Aguchi 20432414e021SJan Beulich trace_spurious_apic_exit(vector); 2044cf910e83SSeiji Aguchi exiting_irq(); 2045f62bae50SIngo Molnar } 2046f62bae50SIngo Molnar 2047f62bae50SIngo Molnar /* 2048f62bae50SIngo Molnar * This interrupt should never happen with our APIC/SMP architecture 2049f62bae50SIngo Molnar */ 205061069de7SThomas Gleixner __visible void __irq_entry smp_error_interrupt(struct pt_regs *regs) 2051f62bae50SIngo Molnar { 20522b398bd9SYouquan Song static const char * const error_interrupt_reason[] = { 20532b398bd9SYouquan Song "Send CS error", /* APIC Error Bit 0 */ 20542b398bd9SYouquan Song "Receive CS error", /* APIC Error Bit 1 */ 20552b398bd9SYouquan Song "Send accept error", /* APIC Error Bit 2 */ 20562b398bd9SYouquan Song "Receive accept error", /* APIC Error Bit 3 */ 20572b398bd9SYouquan Song "Redirectable IPI", /* APIC Error Bit 4 */ 20582b398bd9SYouquan Song "Send illegal vector", /* APIC Error Bit 5 */ 20592b398bd9SYouquan Song "Received illegal vector", /* APIC Error Bit 6 */ 20602b398bd9SYouquan Song "Illegal register address", /* APIC Error Bit 7 */ 20612b398bd9SYouquan Song }; 206261069de7SThomas Gleixner u32 v, i = 0; 206361069de7SThomas Gleixner 206461069de7SThomas Gleixner entering_irq(); 206561069de7SThomas Gleixner trace_error_apic_entry(ERROR_APIC_VECTOR); 2066f62bae50SIngo Molnar 2067f62bae50SIngo Molnar /* First tickle the hardware, only then report what went on. -- REW */ 2068023de4a0SMaciej W. Rozycki if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ 2069f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 207060283df7SRichard Weinberger v = apic_read(APIC_ESR); 2071f62bae50SIngo Molnar ack_APIC_irq(); 2072f62bae50SIngo Molnar atomic_inc(&irq_err_count); 2073f62bae50SIngo Molnar 207460283df7SRichard Weinberger apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", 207560283df7SRichard Weinberger smp_processor_id(), v); 20762b398bd9SYouquan Song 207760283df7SRichard Weinberger v &= 0xff; 207860283df7SRichard Weinberger while (v) { 207960283df7SRichard Weinberger if (v & 0x1) 20802b398bd9SYouquan Song apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); 20812b398bd9SYouquan Song i++; 208260283df7SRichard Weinberger v >>= 1; 20834b8073e4SPeter Senna Tschudin } 20842b398bd9SYouquan Song 20852b398bd9SYouquan Song apic_printk(APIC_DEBUG, KERN_CONT "\n"); 20862b398bd9SYouquan Song 2087cf910e83SSeiji Aguchi trace_error_apic_exit(ERROR_APIC_VECTOR); 2088cf910e83SSeiji Aguchi exiting_irq(); 2089f62bae50SIngo Molnar } 2090f62bae50SIngo Molnar 2091f62bae50SIngo Molnar /** 2092f62bae50SIngo Molnar * connect_bsp_APIC - attach the APIC to the interrupt system 2093f62bae50SIngo Molnar */ 209405f7e46dSThomas Gleixner static void __init connect_bsp_APIC(void) 2095f62bae50SIngo Molnar { 2096f62bae50SIngo Molnar #ifdef CONFIG_X86_32 2097f62bae50SIngo Molnar if (pic_mode) { 2098f62bae50SIngo Molnar /* 2099f62bae50SIngo Molnar * Do not trust the local APIC being empty at bootup. 2100f62bae50SIngo Molnar */ 2101f62bae50SIngo Molnar clear_local_APIC(); 2102f62bae50SIngo Molnar /* 2103f62bae50SIngo Molnar * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 2104f62bae50SIngo Molnar * local APIC to INT and NMI lines. 2105f62bae50SIngo Molnar */ 2106f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "leaving PIC mode, " 2107f62bae50SIngo Molnar "enabling APIC mode.\n"); 2108c0eaa453SCyrill Gorcunov imcr_pic_to_apic(); 2109f62bae50SIngo Molnar } 2110f62bae50SIngo Molnar #endif 2111f62bae50SIngo Molnar } 2112f62bae50SIngo Molnar 2113f62bae50SIngo Molnar /** 2114f62bae50SIngo Molnar * disconnect_bsp_APIC - detach the APIC from the interrupt system 2115f62bae50SIngo Molnar * @virt_wire_setup: indicates, whether virtual wire mode is selected 2116f62bae50SIngo Molnar * 2117f62bae50SIngo Molnar * Virtual wire mode is necessary to deliver legacy interrupts even when the 2118f62bae50SIngo Molnar * APIC is disabled. 2119f62bae50SIngo Molnar */ 2120f62bae50SIngo Molnar void disconnect_bsp_APIC(int virt_wire_setup) 2121f62bae50SIngo Molnar { 2122f62bae50SIngo Molnar unsigned int value; 2123f62bae50SIngo Molnar 2124f62bae50SIngo Molnar #ifdef CONFIG_X86_32 2125f62bae50SIngo Molnar if (pic_mode) { 2126f62bae50SIngo Molnar /* 2127f62bae50SIngo Molnar * Put the board back into PIC mode (has an effect only on 2128f62bae50SIngo Molnar * certain older boards). Note that APIC interrupts, including 2129f62bae50SIngo Molnar * IPIs, won't work beyond this point! The only exception are 2130f62bae50SIngo Molnar * INIT IPIs. 2131f62bae50SIngo Molnar */ 2132f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "disabling APIC mode, " 2133f62bae50SIngo Molnar "entering PIC mode.\n"); 2134c0eaa453SCyrill Gorcunov imcr_apic_to_pic(); 2135f62bae50SIngo Molnar return; 2136f62bae50SIngo Molnar } 2137f62bae50SIngo Molnar #endif 2138f62bae50SIngo Molnar 2139f62bae50SIngo Molnar /* Go back to Virtual Wire compatibility mode */ 2140f62bae50SIngo Molnar 2141f62bae50SIngo Molnar /* For the spurious interrupt use vector F, and enable it */ 2142f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 2143f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 2144f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 2145f62bae50SIngo Molnar value |= 0xf; 2146f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 2147f62bae50SIngo Molnar 2148f62bae50SIngo Molnar if (!virt_wire_setup) { 2149f62bae50SIngo Molnar /* 2150f62bae50SIngo Molnar * For LVT0 make it edge triggered, active high, 2151f62bae50SIngo Molnar * external and enabled 2152f62bae50SIngo Molnar */ 2153f62bae50SIngo Molnar value = apic_read(APIC_LVT0); 2154f62bae50SIngo Molnar value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2155f62bae50SIngo Molnar APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2156f62bae50SIngo Molnar APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2157f62bae50SIngo Molnar value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2158f62bae50SIngo Molnar value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 2159f62bae50SIngo Molnar apic_write(APIC_LVT0, value); 2160f62bae50SIngo Molnar } else { 2161f62bae50SIngo Molnar /* Disable LVT0 */ 2162f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_LVT_MASKED); 2163f62bae50SIngo Molnar } 2164f62bae50SIngo Molnar 2165f62bae50SIngo Molnar /* 2166f62bae50SIngo Molnar * For LVT1 make it edge triggered, active high, 2167f62bae50SIngo Molnar * nmi and enabled 2168f62bae50SIngo Molnar */ 2169f62bae50SIngo Molnar value = apic_read(APIC_LVT1); 2170f62bae50SIngo Molnar value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2171f62bae50SIngo Molnar APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2172f62bae50SIngo Molnar APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2173f62bae50SIngo Molnar value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2174f62bae50SIngo Molnar value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 2175f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 2176f62bae50SIngo Molnar } 2177f62bae50SIngo Molnar 21788f54969dSGu Zheng /* 21798f54969dSGu Zheng * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated 21808f54969dSGu Zheng * contiguously, it equals to current allocated max logical CPU ID plus 1. 218112bf98b9SDou Liyang * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range, 218212bf98b9SDou Liyang * so the maximum of nr_logical_cpuids is nr_cpu_ids. 21838f54969dSGu Zheng * 21848f54969dSGu Zheng * NOTE: Reserve 0 for BSP. 21858f54969dSGu Zheng */ 21868f54969dSGu Zheng static int nr_logical_cpuids = 1; 21878f54969dSGu Zheng 21888f54969dSGu Zheng /* 21898f54969dSGu Zheng * Used to store mapping between logical CPU IDs and APIC IDs. 21908f54969dSGu Zheng */ 21918f54969dSGu Zheng static int cpuid_to_apicid[] = { 21928f54969dSGu Zheng [0 ... NR_CPUS - 1] = -1, 21938f54969dSGu Zheng }; 21948f54969dSGu Zheng 21958f54969dSGu Zheng /* 21968f54969dSGu Zheng * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids 21978f54969dSGu Zheng * and cpuid_to_apicid[] synchronized. 21988f54969dSGu Zheng */ 21998f54969dSGu Zheng static int allocate_logical_cpuid(int apicid) 22008f54969dSGu Zheng { 22018f54969dSGu Zheng int i; 22028f54969dSGu Zheng 22038f54969dSGu Zheng /* 22048f54969dSGu Zheng * cpuid <-> apicid mapping is persistent, so when a cpu is up, 22058f54969dSGu Zheng * check if the kernel has allocated a cpuid for it. 22068f54969dSGu Zheng */ 22078f54969dSGu Zheng for (i = 0; i < nr_logical_cpuids; i++) { 22088f54969dSGu Zheng if (cpuid_to_apicid[i] == apicid) 22098f54969dSGu Zheng return i; 22108f54969dSGu Zheng } 22118f54969dSGu Zheng 22128f54969dSGu Zheng /* Allocate a new cpuid. */ 22138f54969dSGu Zheng if (nr_logical_cpuids >= nr_cpu_ids) { 22149b130ad5SAlexey Dobriyan WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. " 22158f54969dSGu Zheng "Processor %d/0x%x and the rest are ignored.\n", 2216bb3f0a52SDou Liyang nr_cpu_ids, nr_logical_cpuids, apicid); 2217bb3f0a52SDou Liyang return -EINVAL; 22188f54969dSGu Zheng } 22198f54969dSGu Zheng 22208f54969dSGu Zheng cpuid_to_apicid[nr_logical_cpuids] = apicid; 22218f54969dSGu Zheng return nr_logical_cpuids++; 22228f54969dSGu Zheng } 22238f54969dSGu Zheng 22242b85b3d2SDou Liyang int generic_processor_info(int apicid, int version) 2225f62bae50SIngo Molnar { 222614cb6dcfSVivek Goyal int cpu, max = nr_cpu_ids; 222714cb6dcfSVivek Goyal bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, 222814cb6dcfSVivek Goyal phys_cpu_present_map); 222914cb6dcfSVivek Goyal 223014cb6dcfSVivek Goyal /* 2231151e0c7dSHATAYAMA Daisuke * boot_cpu_physical_apicid is designed to have the apicid 2232151e0c7dSHATAYAMA Daisuke * returned by read_apic_id(), i.e, the apicid of the 2233151e0c7dSHATAYAMA Daisuke * currently booting-up processor. However, on some platforms, 22345b4d1dbcSH. Peter Anvin * it is temporarily modified by the apicid reported as BSP 2235151e0c7dSHATAYAMA Daisuke * through MP table. Concretely: 2236151e0c7dSHATAYAMA Daisuke * 2237151e0c7dSHATAYAMA Daisuke * - arch/x86/kernel/mpparse.c: MP_processor_info() 2238151e0c7dSHATAYAMA Daisuke * - arch/x86/mm/amdtopology.c: amd_numa_init() 2239151e0c7dSHATAYAMA Daisuke * 2240151e0c7dSHATAYAMA Daisuke * This function is executed with the modified 2241151e0c7dSHATAYAMA Daisuke * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel 2242151e0c7dSHATAYAMA Daisuke * parameter doesn't work to disable APs on kdump 2nd kernel. 2243151e0c7dSHATAYAMA Daisuke * 2244151e0c7dSHATAYAMA Daisuke * Since fixing handling of boot_cpu_physical_apicid requires 2245151e0c7dSHATAYAMA Daisuke * another discussion and tests on each platform, we leave it 2246151e0c7dSHATAYAMA Daisuke * for now and here we use read_apic_id() directly in this 2247e2329b42SDou Liyang * function, generic_processor_info(). 2248151e0c7dSHATAYAMA Daisuke */ 2249151e0c7dSHATAYAMA Daisuke if (disabled_cpu_apicid != BAD_APICID && 2250151e0c7dSHATAYAMA Daisuke disabled_cpu_apicid != read_apic_id() && 2251151e0c7dSHATAYAMA Daisuke disabled_cpu_apicid == apicid) { 2252151e0c7dSHATAYAMA Daisuke int thiscpu = num_processors + disabled_cpus; 2253151e0c7dSHATAYAMA Daisuke 22545b4d1dbcSH. Peter Anvin pr_warning("APIC: Disabling requested cpu." 2255151e0c7dSHATAYAMA Daisuke " Processor %d/0x%x ignored.\n", 2256151e0c7dSHATAYAMA Daisuke thiscpu, apicid); 2257151e0c7dSHATAYAMA Daisuke 2258151e0c7dSHATAYAMA Daisuke disabled_cpus++; 2259151e0c7dSHATAYAMA Daisuke return -ENODEV; 2260151e0c7dSHATAYAMA Daisuke } 2261151e0c7dSHATAYAMA Daisuke 2262151e0c7dSHATAYAMA Daisuke /* 226314cb6dcfSVivek Goyal * If boot cpu has not been detected yet, then only allow upto 226414cb6dcfSVivek Goyal * nr_cpu_ids - 1 processors and keep one slot free for boot cpu 226514cb6dcfSVivek Goyal */ 226614cb6dcfSVivek Goyal if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && 226714cb6dcfSVivek Goyal apicid != boot_cpu_physical_apicid) { 226814cb6dcfSVivek Goyal int thiscpu = max + disabled_cpus - 1; 226914cb6dcfSVivek Goyal 227014cb6dcfSVivek Goyal pr_warning( 22713c8fad91SClaudio Fontana "APIC: NR_CPUS/possible_cpus limit of %i almost" 227214cb6dcfSVivek Goyal " reached. Keeping one slot for boot cpu." 227314cb6dcfSVivek Goyal " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 227414cb6dcfSVivek Goyal 227514cb6dcfSVivek Goyal disabled_cpus++; 22767e1f85f9SJiang Liu return -ENODEV; 227714cb6dcfSVivek Goyal } 2278f62bae50SIngo Molnar 2279f62bae50SIngo Molnar if (num_processors >= nr_cpu_ids) { 2280f62bae50SIngo Molnar int thiscpu = max + disabled_cpus; 2281f62bae50SIngo Molnar 2282df610d67SThomas Gleixner pr_warning("APIC: NR_CPUS/possible_cpus limit of %i " 2283df610d67SThomas Gleixner "reached. Processor %d/0x%x ignored.\n", 2284df610d67SThomas Gleixner max, thiscpu, apicid); 2285f62bae50SIngo Molnar 2286f62bae50SIngo Molnar disabled_cpus++; 22877e1f85f9SJiang Liu return -EINVAL; 2288f62bae50SIngo Molnar } 2289f62bae50SIngo Molnar 2290f62bae50SIngo Molnar if (apicid == boot_cpu_physical_apicid) { 2291f62bae50SIngo Molnar /* 2292f62bae50SIngo Molnar * x86_bios_cpu_apicid is required to have processors listed 2293f62bae50SIngo Molnar * in same order as logical cpu numbers. Hence the first 2294f62bae50SIngo Molnar * entry is BSP, and so on. 2295e5fea868SYinghai Lu * boot_cpu_init() already hold bit 0 in cpu_present_mask 2296e5fea868SYinghai Lu * for BSP. 2297f62bae50SIngo Molnar */ 2298f62bae50SIngo Molnar cpu = 0; 22998f54969dSGu Zheng 23008f54969dSGu Zheng /* Logical cpuid 0 is reserved for BSP. */ 23018f54969dSGu Zheng cpuid_to_apicid[0] = apicid; 23028f54969dSGu Zheng } else { 23038f54969dSGu Zheng cpu = allocate_logical_cpuid(apicid); 23048f54969dSGu Zheng if (cpu < 0) { 23058f54969dSGu Zheng disabled_cpus++; 23068f54969dSGu Zheng return -EINVAL; 23078f54969dSGu Zheng } 23088f54969dSGu Zheng } 2309e5fea868SYinghai Lu 2310e5fea868SYinghai Lu /* 2311e5fea868SYinghai Lu * Validate version 2312e5fea868SYinghai Lu */ 2313e5fea868SYinghai Lu if (version == 0x0) { 2314e5fea868SYinghai Lu pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", 2315e5fea868SYinghai Lu cpu, apicid); 2316e5fea868SYinghai Lu version = 0x10; 2317f62bae50SIngo Molnar } 2318e5fea868SYinghai Lu 2319cff9ab2bSDenys Vlasenko if (version != boot_cpu_apic_version) { 2320e5fea868SYinghai Lu pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", 2321cff9ab2bSDenys Vlasenko boot_cpu_apic_version, cpu, version); 2322e5fea868SYinghai Lu } 2323e5fea868SYinghai Lu 2324f62bae50SIngo Molnar if (apicid > max_physical_apicid) 2325f62bae50SIngo Molnar max_physical_apicid = apicid; 2326f62bae50SIngo Molnar 2327f62bae50SIngo Molnar #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 2328f62bae50SIngo Molnar early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 2329f62bae50SIngo Molnar early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 2330f62bae50SIngo Molnar #endif 2331acb8bc09STejun Heo #ifdef CONFIG_X86_32 2332acb8bc09STejun Heo early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 2333acb8bc09STejun Heo apic->x86_32_early_logical_apicid(cpu); 2334acb8bc09STejun Heo #endif 2335f62bae50SIngo Molnar set_cpu_possible(cpu, true); 2336f7c28833SGu Zheng physid_set(apicid, phys_cpu_present_map); 2337f62bae50SIngo Molnar set_cpu_present(cpu, true); 23382b85b3d2SDou Liyang num_processors++; 23397e1f85f9SJiang Liu 23407e1f85f9SJiang Liu return cpu; 2341f62bae50SIngo Molnar } 2342f62bae50SIngo Molnar 2343f62bae50SIngo Molnar int hard_smp_processor_id(void) 2344f62bae50SIngo Molnar { 2345f62bae50SIngo Molnar return read_apic_id(); 2346f62bae50SIngo Molnar } 2347f62bae50SIngo Molnar 2348f62bae50SIngo Molnar /* 23491551df64SMichael S. Tsirkin * Override the generic EOI implementation with an optimized version. 23501551df64SMichael S. Tsirkin * Only called during early boot when only one CPU is active and with 23511551df64SMichael S. Tsirkin * interrupts disabled, so we know this does not race with actual APIC driver 23521551df64SMichael S. Tsirkin * use. 23531551df64SMichael S. Tsirkin */ 23541551df64SMichael S. Tsirkin void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) 23551551df64SMichael S. Tsirkin { 23561551df64SMichael S. Tsirkin struct apic **drv; 23571551df64SMichael S. Tsirkin 23581551df64SMichael S. Tsirkin for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { 23591551df64SMichael S. Tsirkin /* Should happen once for each apic */ 23601551df64SMichael S. Tsirkin WARN_ON((*drv)->eoi_write == eoi_write); 23618ca22552SWanpeng Li (*drv)->native_eoi_write = (*drv)->eoi_write; 23621551df64SMichael S. Tsirkin (*drv)->eoi_write = eoi_write; 23631551df64SMichael S. Tsirkin } 23641551df64SMichael S. Tsirkin } 23651551df64SMichael S. Tsirkin 2366374aab33SThomas Gleixner static void __init apic_bsp_up_setup(void) 236705f7e46dSThomas Gleixner { 2368374aab33SThomas Gleixner #ifdef CONFIG_X86_64 23695d64d209SDou Liyang apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid)); 2370374aab33SThomas Gleixner #else 237105f7e46dSThomas Gleixner /* 2372374aab33SThomas Gleixner * Hack: In case of kdump, after a crash, kernel might be booting 2373374aab33SThomas Gleixner * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 2374374aab33SThomas Gleixner * might be zero if read from MP tables. Get it from LAPIC. 237505f7e46dSThomas Gleixner */ 2376374aab33SThomas Gleixner # ifdef CONFIG_CRASH_DUMP 2377374aab33SThomas Gleixner boot_cpu_physical_apicid = read_apic_id(); 2378374aab33SThomas Gleixner # endif 2379374aab33SThomas Gleixner #endif 2380374aab33SThomas Gleixner physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 238105f7e46dSThomas Gleixner } 238205f7e46dSThomas Gleixner 238305f7e46dSThomas Gleixner /** 238405f7e46dSThomas Gleixner * apic_bsp_setup - Setup function for local apic and io-apic 2385374aab33SThomas Gleixner * @upmode: Force UP mode (for APIC_init_uniprocessor) 238605f7e46dSThomas Gleixner * 238705f7e46dSThomas Gleixner * Returns: 238805f7e46dSThomas Gleixner * apic_id of BSP APIC 238905f7e46dSThomas Gleixner */ 23904b1244b4SDou Liyang void __init apic_bsp_setup(bool upmode) 239105f7e46dSThomas Gleixner { 239205f7e46dSThomas Gleixner connect_bsp_APIC(); 2393374aab33SThomas Gleixner if (upmode) 2394374aab33SThomas Gleixner apic_bsp_up_setup(); 239505f7e46dSThomas Gleixner setup_local_APIC(); 239605f7e46dSThomas Gleixner 239705f7e46dSThomas Gleixner enable_IO_APIC(); 2398374aab33SThomas Gleixner end_local_APIC_setup(); 2399374aab33SThomas Gleixner irq_remap_enable_fault_handling(); 240005f7e46dSThomas Gleixner setup_IO_APIC(); 2401e714a91fSThomas Gleixner } 2402e714a91fSThomas Gleixner 240330b8b006SThomas Gleixner #ifdef CONFIG_UP_LATE_INIT 240430b8b006SThomas Gleixner void __init up_late_init(void) 240530b8b006SThomas Gleixner { 24060c759131SDou Liyang if (apic_intr_mode == APIC_PIC) 24070c759131SDou Liyang return; 24080c759131SDou Liyang 24090c759131SDou Liyang /* Setup local timer */ 24100c759131SDou Liyang x86_init.timers.setup_percpu_clockev(); 241130b8b006SThomas Gleixner } 241230b8b006SThomas Gleixner #endif 241330b8b006SThomas Gleixner 2414e714a91fSThomas Gleixner /* 2415f62bae50SIngo Molnar * Power management 2416f62bae50SIngo Molnar */ 2417f62bae50SIngo Molnar #ifdef CONFIG_PM 2418f62bae50SIngo Molnar 2419f62bae50SIngo Molnar static struct { 2420f62bae50SIngo Molnar /* 2421f62bae50SIngo Molnar * 'active' is true if the local APIC was enabled by us and 2422f62bae50SIngo Molnar * not the BIOS; this signifies that we are also responsible 2423f62bae50SIngo Molnar * for disabling it before entering apm/acpi suspend 2424f62bae50SIngo Molnar */ 2425f62bae50SIngo Molnar int active; 2426f62bae50SIngo Molnar /* r/w apic fields */ 2427f62bae50SIngo Molnar unsigned int apic_id; 2428f62bae50SIngo Molnar unsigned int apic_taskpri; 2429f62bae50SIngo Molnar unsigned int apic_ldr; 2430f62bae50SIngo Molnar unsigned int apic_dfr; 2431f62bae50SIngo Molnar unsigned int apic_spiv; 2432f62bae50SIngo Molnar unsigned int apic_lvtt; 2433f62bae50SIngo Molnar unsigned int apic_lvtpc; 2434f62bae50SIngo Molnar unsigned int apic_lvt0; 2435f62bae50SIngo Molnar unsigned int apic_lvt1; 2436f62bae50SIngo Molnar unsigned int apic_lvterr; 2437f62bae50SIngo Molnar unsigned int apic_tmict; 2438f62bae50SIngo Molnar unsigned int apic_tdcr; 2439f62bae50SIngo Molnar unsigned int apic_thmr; 244042baa258SJuergen Gross unsigned int apic_cmci; 2441f62bae50SIngo Molnar } apic_pm_state; 2442f62bae50SIngo Molnar 2443f3c6ea1bSRafael J. Wysocki static int lapic_suspend(void) 2444f62bae50SIngo Molnar { 2445f62bae50SIngo Molnar unsigned long flags; 2446f62bae50SIngo Molnar int maxlvt; 2447f62bae50SIngo Molnar 2448f62bae50SIngo Molnar if (!apic_pm_state.active) 2449f62bae50SIngo Molnar return 0; 2450f62bae50SIngo Molnar 2451f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 2452f62bae50SIngo Molnar 2453f62bae50SIngo Molnar apic_pm_state.apic_id = apic_read(APIC_ID); 2454f62bae50SIngo Molnar apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2455f62bae50SIngo Molnar apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2456f62bae50SIngo Molnar apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2457f62bae50SIngo Molnar apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2458f62bae50SIngo Molnar apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2459f62bae50SIngo Molnar if (maxlvt >= 4) 2460f62bae50SIngo Molnar apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2461f62bae50SIngo Molnar apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2462f62bae50SIngo Molnar apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2463f62bae50SIngo Molnar apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2464f62bae50SIngo Molnar apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2465f62bae50SIngo Molnar apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 24664efc0670SAndi Kleen #ifdef CONFIG_X86_THERMAL_VECTOR 2467f62bae50SIngo Molnar if (maxlvt >= 5) 2468f62bae50SIngo Molnar apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2469f62bae50SIngo Molnar #endif 247042baa258SJuergen Gross #ifdef CONFIG_X86_MCE_INTEL 247142baa258SJuergen Gross if (maxlvt >= 6) 247242baa258SJuergen Gross apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI); 247342baa258SJuergen Gross #endif 2474f62bae50SIngo Molnar 2475f62bae50SIngo Molnar local_irq_save(flags); 2476f62bae50SIngo Molnar disable_local_APIC(); 2477fc1edaf9SSuresh Siddha 247895a02e97SSuresh Siddha irq_remapping_disable(); 2479fc1edaf9SSuresh Siddha 2480f62bae50SIngo Molnar local_irq_restore(flags); 2481f62bae50SIngo Molnar return 0; 2482f62bae50SIngo Molnar } 2483f62bae50SIngo Molnar 2484f3c6ea1bSRafael J. Wysocki static void lapic_resume(void) 2485f62bae50SIngo Molnar { 2486f62bae50SIngo Molnar unsigned int l, h; 2487f62bae50SIngo Molnar unsigned long flags; 248831dce14aSSuresh Siddha int maxlvt; 2489b24696bcSFenghua Yu 2490f62bae50SIngo Molnar if (!apic_pm_state.active) 2491f3c6ea1bSRafael J. Wysocki return; 2492f62bae50SIngo Molnar 2493b24696bcSFenghua Yu local_irq_save(flags); 2494336224baSJoerg Roedel 249531dce14aSSuresh Siddha /* 249631dce14aSSuresh Siddha * IO-APIC and PIC have their own resume routines. 249731dce14aSSuresh Siddha * We just mask them here to make sure the interrupt 249831dce14aSSuresh Siddha * subsystem is completely quiet while we enable x2apic 249931dce14aSSuresh Siddha * and interrupt-remapping. 250031dce14aSSuresh Siddha */ 250131dce14aSSuresh Siddha mask_ioapic_entries(); 2502b81bb373SJacob Pan legacy_pic->mask_all(); 2503f62bae50SIngo Molnar 2504659006bfSThomas Gleixner if (x2apic_mode) { 2505659006bfSThomas Gleixner __x2apic_enable(); 2506659006bfSThomas Gleixner } else { 2507f62bae50SIngo Molnar /* 2508f62bae50SIngo Molnar * Make sure the APICBASE points to the right address 2509f62bae50SIngo Molnar * 2510f62bae50SIngo Molnar * FIXME! This will be wrong if we ever support suspend on 2511f62bae50SIngo Molnar * SMP! We'll need to do this as part of the CPU restore! 2512f62bae50SIngo Molnar */ 2513cbf2829bSBryan O'Donoghue if (boot_cpu_data.x86 >= 6) { 2514f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, l, h); 2515f62bae50SIngo Molnar l &= ~MSR_IA32_APICBASE_BASE; 2516f62bae50SIngo Molnar l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2517f62bae50SIngo Molnar wrmsr(MSR_IA32_APICBASE, l, h); 2518f62bae50SIngo Molnar } 2519cbf2829bSBryan O'Donoghue } 2520f62bae50SIngo Molnar 2521b24696bcSFenghua Yu maxlvt = lapic_get_maxlvt(); 2522f62bae50SIngo Molnar apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2523f62bae50SIngo Molnar apic_write(APIC_ID, apic_pm_state.apic_id); 2524f62bae50SIngo Molnar apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2525f62bae50SIngo Molnar apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2526f62bae50SIngo Molnar apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2527f62bae50SIngo Molnar apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2528f62bae50SIngo Molnar apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2529f62bae50SIngo Molnar apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 253042baa258SJuergen Gross #ifdef CONFIG_X86_THERMAL_VECTOR 2531f62bae50SIngo Molnar if (maxlvt >= 5) 2532f62bae50SIngo Molnar apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2533f62bae50SIngo Molnar #endif 253442baa258SJuergen Gross #ifdef CONFIG_X86_MCE_INTEL 253542baa258SJuergen Gross if (maxlvt >= 6) 253642baa258SJuergen Gross apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci); 253742baa258SJuergen Gross #endif 2538f62bae50SIngo Molnar if (maxlvt >= 4) 2539f62bae50SIngo Molnar apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2540f62bae50SIngo Molnar apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2541f62bae50SIngo Molnar apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2542f62bae50SIngo Molnar apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2543f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 2544f62bae50SIngo Molnar apic_read(APIC_ESR); 2545f62bae50SIngo Molnar apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2546f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 2547f62bae50SIngo Molnar apic_read(APIC_ESR); 2548f62bae50SIngo Molnar 254995a02e97SSuresh Siddha irq_remapping_reenable(x2apic_mode); 255031dce14aSSuresh Siddha 2551f62bae50SIngo Molnar local_irq_restore(flags); 2552f62bae50SIngo Molnar } 2553f62bae50SIngo Molnar 2554f62bae50SIngo Molnar /* 2555f62bae50SIngo Molnar * This device has no shutdown method - fully functioning local APICs 2556f62bae50SIngo Molnar * are needed on every CPU up until machine_halt/restart/poweroff. 2557f62bae50SIngo Molnar */ 2558f62bae50SIngo Molnar 2559f3c6ea1bSRafael J. Wysocki static struct syscore_ops lapic_syscore_ops = { 2560f62bae50SIngo Molnar .resume = lapic_resume, 2561f62bae50SIngo Molnar .suspend = lapic_suspend, 2562f62bae50SIngo Molnar }; 2563f62bae50SIngo Molnar 2564148f9bb8SPaul Gortmaker static void apic_pm_activate(void) 2565f62bae50SIngo Molnar { 2566f62bae50SIngo Molnar apic_pm_state.active = 1; 2567f62bae50SIngo Molnar } 2568f62bae50SIngo Molnar 2569f62bae50SIngo Molnar static int __init init_lapic_sysfs(void) 2570f62bae50SIngo Molnar { 2571f62bae50SIngo Molnar /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 257293984fbdSBorislav Petkov if (boot_cpu_has(X86_FEATURE_APIC)) 2573f3c6ea1bSRafael J. Wysocki register_syscore_ops(&lapic_syscore_ops); 2574f62bae50SIngo Molnar 2575f3c6ea1bSRafael J. Wysocki return 0; 2576f62bae50SIngo Molnar } 2577b24696bcSFenghua Yu 2578b24696bcSFenghua Yu /* local apic needs to resume before other devices access its registers. */ 2579b24696bcSFenghua Yu core_initcall(init_lapic_sysfs); 2580f62bae50SIngo Molnar 2581f62bae50SIngo Molnar #else /* CONFIG_PM */ 2582f62bae50SIngo Molnar 2583f62bae50SIngo Molnar static void apic_pm_activate(void) { } 2584f62bae50SIngo Molnar 2585f62bae50SIngo Molnar #endif /* CONFIG_PM */ 2586f62bae50SIngo Molnar 2587f62bae50SIngo Molnar #ifdef CONFIG_X86_64 2588e0e42142SYinghai Lu 2589148f9bb8SPaul Gortmaker static int multi_checked; 2590148f9bb8SPaul Gortmaker static int multi; 2591e0e42142SYinghai Lu 2592148f9bb8SPaul Gortmaker static int set_multi(const struct dmi_system_id *d) 2593e0e42142SYinghai Lu { 2594e0e42142SYinghai Lu if (multi) 2595e0e42142SYinghai Lu return 0; 25966f0aced6SCyrill Gorcunov pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2597e0e42142SYinghai Lu multi = 1; 2598e0e42142SYinghai Lu return 0; 2599e0e42142SYinghai Lu } 2600e0e42142SYinghai Lu 2601148f9bb8SPaul Gortmaker static const struct dmi_system_id multi_dmi_table[] = { 2602e0e42142SYinghai Lu { 2603e0e42142SYinghai Lu .callback = set_multi, 2604e0e42142SYinghai Lu .ident = "IBM System Summit2", 2605e0e42142SYinghai Lu .matches = { 2606e0e42142SYinghai Lu DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2607e0e42142SYinghai Lu DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2608e0e42142SYinghai Lu }, 2609e0e42142SYinghai Lu }, 2610e0e42142SYinghai Lu {} 2611e0e42142SYinghai Lu }; 2612e0e42142SYinghai Lu 2613148f9bb8SPaul Gortmaker static void dmi_check_multi(void) 2614e0e42142SYinghai Lu { 2615e0e42142SYinghai Lu if (multi_checked) 2616e0e42142SYinghai Lu return; 2617e0e42142SYinghai Lu 2618e0e42142SYinghai Lu dmi_check_system(multi_dmi_table); 2619e0e42142SYinghai Lu multi_checked = 1; 2620e0e42142SYinghai Lu } 2621f62bae50SIngo Molnar 2622f62bae50SIngo Molnar /* 2623e0e42142SYinghai Lu * apic_is_clustered_box() -- Check if we can expect good TSC 2624e0e42142SYinghai Lu * 2625e0e42142SYinghai Lu * Thus far, the major user of this is IBM's Summit2 series: 2626e0e42142SYinghai Lu * Clustered boxes may have unsynced TSC problems if they are 2627e0e42142SYinghai Lu * multi-chassis. 2628e0e42142SYinghai Lu * Use DMI to check them 2629f62bae50SIngo Molnar */ 2630148f9bb8SPaul Gortmaker int apic_is_clustered_box(void) 2631e0e42142SYinghai Lu { 2632e0e42142SYinghai Lu dmi_check_multi(); 2633411cf9eeSOren Twaig return multi; 2634f62bae50SIngo Molnar } 2635f62bae50SIngo Molnar #endif 2636f62bae50SIngo Molnar 2637f62bae50SIngo Molnar /* 2638f62bae50SIngo Molnar * APIC command line parameters 2639f62bae50SIngo Molnar */ 2640f62bae50SIngo Molnar static int __init setup_disableapic(char *arg) 2641f62bae50SIngo Molnar { 2642f62bae50SIngo Molnar disable_apic = 1; 2643f62bae50SIngo Molnar setup_clear_cpu_cap(X86_FEATURE_APIC); 2644f62bae50SIngo Molnar return 0; 2645f62bae50SIngo Molnar } 2646f62bae50SIngo Molnar early_param("disableapic", setup_disableapic); 2647f62bae50SIngo Molnar 2648f62bae50SIngo Molnar /* same as disableapic, for compatibility */ 2649f62bae50SIngo Molnar static int __init setup_nolapic(char *arg) 2650f62bae50SIngo Molnar { 2651f62bae50SIngo Molnar return setup_disableapic(arg); 2652f62bae50SIngo Molnar } 2653f62bae50SIngo Molnar early_param("nolapic", setup_nolapic); 2654f62bae50SIngo Molnar 2655f62bae50SIngo Molnar static int __init parse_lapic_timer_c2_ok(char *arg) 2656f62bae50SIngo Molnar { 2657f62bae50SIngo Molnar local_apic_timer_c2_ok = 1; 2658f62bae50SIngo Molnar return 0; 2659f62bae50SIngo Molnar } 2660f62bae50SIngo Molnar early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2661f62bae50SIngo Molnar 2662f62bae50SIngo Molnar static int __init parse_disable_apic_timer(char *arg) 2663f62bae50SIngo Molnar { 2664f62bae50SIngo Molnar disable_apic_timer = 1; 2665f62bae50SIngo Molnar return 0; 2666f62bae50SIngo Molnar } 2667f62bae50SIngo Molnar early_param("noapictimer", parse_disable_apic_timer); 2668f62bae50SIngo Molnar 2669f62bae50SIngo Molnar static int __init parse_nolapic_timer(char *arg) 2670f62bae50SIngo Molnar { 2671f62bae50SIngo Molnar disable_apic_timer = 1; 2672f62bae50SIngo Molnar return 0; 2673f62bae50SIngo Molnar } 2674f62bae50SIngo Molnar early_param("nolapic_timer", parse_nolapic_timer); 2675f62bae50SIngo Molnar 2676f62bae50SIngo Molnar static int __init apic_set_verbosity(char *arg) 2677f62bae50SIngo Molnar { 2678f62bae50SIngo Molnar if (!arg) { 2679f62bae50SIngo Molnar #ifdef CONFIG_X86_64 2680f62bae50SIngo Molnar skip_ioapic_setup = 0; 2681f62bae50SIngo Molnar return 0; 2682f62bae50SIngo Molnar #endif 2683f62bae50SIngo Molnar return -EINVAL; 2684f62bae50SIngo Molnar } 2685f62bae50SIngo Molnar 2686f62bae50SIngo Molnar if (strcmp("debug", arg) == 0) 2687f62bae50SIngo Molnar apic_verbosity = APIC_DEBUG; 2688f62bae50SIngo Molnar else if (strcmp("verbose", arg) == 0) 2689f62bae50SIngo Molnar apic_verbosity = APIC_VERBOSE; 26904fcab669SDou Liyang #ifdef CONFIG_X86_64 2691f62bae50SIngo Molnar else { 2692f62bae50SIngo Molnar pr_warning("APIC Verbosity level %s not recognised" 2693f62bae50SIngo Molnar " use apic=verbose or apic=debug\n", arg); 2694f62bae50SIngo Molnar return -EINVAL; 2695f62bae50SIngo Molnar } 26964fcab669SDou Liyang #endif 2697f62bae50SIngo Molnar 2698f62bae50SIngo Molnar return 0; 2699f62bae50SIngo Molnar } 2700f62bae50SIngo Molnar early_param("apic", apic_set_verbosity); 2701f62bae50SIngo Molnar 2702f62bae50SIngo Molnar static int __init lapic_insert_resource(void) 2703f62bae50SIngo Molnar { 2704f62bae50SIngo Molnar if (!apic_phys) 2705f62bae50SIngo Molnar return -1; 2706f62bae50SIngo Molnar 2707f62bae50SIngo Molnar /* Put local APIC into the resource map. */ 2708f62bae50SIngo Molnar lapic_resource.start = apic_phys; 2709f62bae50SIngo Molnar lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2710f62bae50SIngo Molnar insert_resource(&iomem_resource, &lapic_resource); 2711f62bae50SIngo Molnar 2712f62bae50SIngo Molnar return 0; 2713f62bae50SIngo Molnar } 2714f62bae50SIngo Molnar 2715f62bae50SIngo Molnar /* 27161506c8dcSIngo Molnar * need call insert after e820__reserve_resources() 2717f62bae50SIngo Molnar * that is using request_resource 2718f62bae50SIngo Molnar */ 2719f62bae50SIngo Molnar late_initcall(lapic_insert_resource); 2720151e0c7dSHATAYAMA Daisuke 2721151e0c7dSHATAYAMA Daisuke static int __init apic_set_disabled_cpu_apicid(char *arg) 2722151e0c7dSHATAYAMA Daisuke { 2723151e0c7dSHATAYAMA Daisuke if (!arg || !get_option(&arg, &disabled_cpu_apicid)) 2724151e0c7dSHATAYAMA Daisuke return -EINVAL; 2725151e0c7dSHATAYAMA Daisuke 2726151e0c7dSHATAYAMA Daisuke return 0; 2727151e0c7dSHATAYAMA Daisuke } 2728151e0c7dSHATAYAMA Daisuke early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); 2729b7c4948eSHidehiro Kawai 2730b7c4948eSHidehiro Kawai static int __init apic_set_extnmi(char *arg) 2731b7c4948eSHidehiro Kawai { 2732b7c4948eSHidehiro Kawai if (!arg) 2733b7c4948eSHidehiro Kawai return -EINVAL; 2734b7c4948eSHidehiro Kawai 2735b7c4948eSHidehiro Kawai if (!strncmp("all", arg, 3)) 2736b7c4948eSHidehiro Kawai apic_extnmi = APIC_EXTNMI_ALL; 2737b7c4948eSHidehiro Kawai else if (!strncmp("none", arg, 4)) 2738b7c4948eSHidehiro Kawai apic_extnmi = APIC_EXTNMI_NONE; 2739b7c4948eSHidehiro Kawai else if (!strncmp("bsp", arg, 3)) 2740b7c4948eSHidehiro Kawai apic_extnmi = APIC_EXTNMI_BSP; 2741b7c4948eSHidehiro Kawai else { 2742b7c4948eSHidehiro Kawai pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg); 2743b7c4948eSHidehiro Kawai return -EINVAL; 2744b7c4948eSHidehiro Kawai } 2745b7c4948eSHidehiro Kawai 2746b7c4948eSHidehiro Kawai return 0; 2747b7c4948eSHidehiro Kawai } 2748b7c4948eSHidehiro Kawai early_param("apic_extnmi", apic_set_extnmi); 2749