1f62bae50SIngo Molnar /* 2f62bae50SIngo Molnar * Local APIC handling, local APIC timers 3f62bae50SIngo Molnar * 4f62bae50SIngo Molnar * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 5f62bae50SIngo Molnar * 6f62bae50SIngo Molnar * Fixes 7f62bae50SIngo Molnar * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8f62bae50SIngo Molnar * thanks to Eric Gilmore 9f62bae50SIngo Molnar * and Rolf G. Tews 10f62bae50SIngo Molnar * for testing these extensively. 11f62bae50SIngo Molnar * Maciej W. Rozycki : Various updates and fixes. 12f62bae50SIngo Molnar * Mikael Pettersson : Power Management for UP-APIC. 13f62bae50SIngo Molnar * Pavel Machek and 14f62bae50SIngo Molnar * Mikael Pettersson : PM converted to driver model. 15f62bae50SIngo Molnar */ 16f62bae50SIngo Molnar 17cdd6c482SIngo Molnar #include <linux/perf_event.h> 18f62bae50SIngo Molnar #include <linux/kernel_stat.h> 19f62bae50SIngo Molnar #include <linux/mc146818rtc.h> 20f62bae50SIngo Molnar #include <linux/acpi_pmtmr.h> 21f62bae50SIngo Molnar #include <linux/clockchips.h> 22f62bae50SIngo Molnar #include <linux/interrupt.h> 23f62bae50SIngo Molnar #include <linux/bootmem.h> 24f62bae50SIngo Molnar #include <linux/ftrace.h> 25f62bae50SIngo Molnar #include <linux/ioport.h> 26f62bae50SIngo Molnar #include <linux/module.h> 27f3c6ea1bSRafael J. Wysocki #include <linux/syscore_ops.h> 28f62bae50SIngo Molnar #include <linux/delay.h> 29f62bae50SIngo Molnar #include <linux/timex.h> 30334955efSRalf Baechle #include <linux/i8253.h> 31f62bae50SIngo Molnar #include <linux/dmar.h> 32f62bae50SIngo Molnar #include <linux/init.h> 33f62bae50SIngo Molnar #include <linux/cpu.h> 34f62bae50SIngo Molnar #include <linux/dmi.h> 35f62bae50SIngo Molnar #include <linux/smp.h> 36f62bae50SIngo Molnar #include <linux/mm.h> 37f62bae50SIngo Molnar 3883ab8514SSteven Rostedt (Red Hat) #include <asm/trace/irq_vectors.h> 398a8f422dSSuresh Siddha #include <asm/irq_remapping.h> 40cdd6c482SIngo Molnar #include <asm/perf_event.h> 41736decacSThomas Gleixner #include <asm/x86_init.h> 42f62bae50SIngo Molnar #include <asm/pgalloc.h> 4360063497SArun Sharma #include <linux/atomic.h> 44f62bae50SIngo Molnar #include <asm/mpspec.h> 45f62bae50SIngo Molnar #include <asm/i8259.h> 46f62bae50SIngo Molnar #include <asm/proto.h> 47f62bae50SIngo Molnar #include <asm/apic.h> 487167d08eSHenrik Kretzschmar #include <asm/io_apic.h> 49f62bae50SIngo Molnar #include <asm/desc.h> 50f62bae50SIngo Molnar #include <asm/hpet.h> 51f62bae50SIngo Molnar #include <asm/idle.h> 52f62bae50SIngo Molnar #include <asm/mtrr.h> 5316f871bcSRalf Baechle #include <asm/time.h> 54f62bae50SIngo Molnar #include <asm/smp.h> 55638bee71SH. Peter Anvin #include <asm/mce.h> 568c3ba8d0SKerstin Jonsson #include <asm/tsc.h> 572904ed8dSSheng Yang #include <asm/hypervisor.h> 58f62bae50SIngo Molnar 59f62bae50SIngo Molnar unsigned int num_processors; 60f62bae50SIngo Molnar 61148f9bb8SPaul Gortmaker unsigned disabled_cpus; 62f62bae50SIngo Molnar 63f62bae50SIngo Molnar /* Processor that is doing the boot up */ 64f62bae50SIngo Molnar unsigned int boot_cpu_physical_apicid = -1U; 65cc08e04cSDavid Rientjes EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); 66f62bae50SIngo Molnar 67f62bae50SIngo Molnar /* 68f62bae50SIngo Molnar * The highest APIC ID seen during enumeration. 69f62bae50SIngo Molnar */ 70a491cc90SJiang Liu static unsigned int max_physical_apicid; 71f62bae50SIngo Molnar 72f62bae50SIngo Molnar /* 73f62bae50SIngo Molnar * Bitmask of physically existing CPUs: 74f62bae50SIngo Molnar */ 75f62bae50SIngo Molnar physid_mask_t phys_cpu_present_map; 76f62bae50SIngo Molnar 77f62bae50SIngo Molnar /* 78151e0c7dSHATAYAMA Daisuke * Processor to be disabled specified by kernel parameter 79151e0c7dSHATAYAMA Daisuke * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to 80151e0c7dSHATAYAMA Daisuke * avoid undefined behaviour caused by sending INIT from AP to BSP. 81151e0c7dSHATAYAMA Daisuke */ 825b4d1dbcSH. Peter Anvin static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID; 83151e0c7dSHATAYAMA Daisuke 84151e0c7dSHATAYAMA Daisuke /* 85f62bae50SIngo Molnar * Map cpu index to physical APIC ID 86f62bae50SIngo Molnar */ 870816b0f0SVlad Zolotarov DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); 880816b0f0SVlad Zolotarov DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); 89f62bae50SIngo Molnar EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 90f62bae50SIngo Molnar EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 91f62bae50SIngo Molnar 92f62bae50SIngo Molnar #ifdef CONFIG_X86_32 934c321ff8STejun Heo 944c321ff8STejun Heo /* 954c321ff8STejun Heo * On x86_32, the mapping between cpu and logical apicid may vary 964c321ff8STejun Heo * depending on apic in use. The following early percpu variable is 974c321ff8STejun Heo * used for the mapping. This is where the behaviors of x86_64 and 32 984c321ff8STejun Heo * actually diverge. Let's keep it ugly for now. 994c321ff8STejun Heo */ 1000816b0f0SVlad Zolotarov DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); 1014c321ff8STejun Heo 102f62bae50SIngo Molnar /* Local APIC was disabled by the BIOS and enabled by the kernel */ 103f62bae50SIngo Molnar static int enabled_via_apicbase; 104f62bae50SIngo Molnar 105c0eaa453SCyrill Gorcunov /* 106c0eaa453SCyrill Gorcunov * Handle interrupt mode configuration register (IMCR). 107c0eaa453SCyrill Gorcunov * This register controls whether the interrupt signals 108c0eaa453SCyrill Gorcunov * that reach the BSP come from the master PIC or from the 109c0eaa453SCyrill Gorcunov * local APIC. Before entering Symmetric I/O Mode, either 110c0eaa453SCyrill Gorcunov * the BIOS or the operating system must switch out of 111c0eaa453SCyrill Gorcunov * PIC Mode by changing the IMCR. 112c0eaa453SCyrill Gorcunov */ 1135cda395fSAlexander van Heukelum static inline void imcr_pic_to_apic(void) 114c0eaa453SCyrill Gorcunov { 115c0eaa453SCyrill Gorcunov /* select IMCR register */ 116c0eaa453SCyrill Gorcunov outb(0x70, 0x22); 117c0eaa453SCyrill Gorcunov /* NMI and 8259 INTR go through APIC */ 118c0eaa453SCyrill Gorcunov outb(0x01, 0x23); 119c0eaa453SCyrill Gorcunov } 120c0eaa453SCyrill Gorcunov 1215cda395fSAlexander van Heukelum static inline void imcr_apic_to_pic(void) 122c0eaa453SCyrill Gorcunov { 123c0eaa453SCyrill Gorcunov /* select IMCR register */ 124c0eaa453SCyrill Gorcunov outb(0x70, 0x22); 125c0eaa453SCyrill Gorcunov /* NMI and 8259 INTR go directly to BSP */ 126c0eaa453SCyrill Gorcunov outb(0x00, 0x23); 127c0eaa453SCyrill Gorcunov } 128f62bae50SIngo Molnar #endif 129f62bae50SIngo Molnar 130279f1461SSuresh Siddha /* 131279f1461SSuresh Siddha * Knob to control our willingness to enable the local APIC. 132279f1461SSuresh Siddha * 133279f1461SSuresh Siddha * +1=force-enable 134279f1461SSuresh Siddha */ 135279f1461SSuresh Siddha static int force_enable_local_apic __initdata; 136dc9788f4SDavid Rientjes 137279f1461SSuresh Siddha /* 138279f1461SSuresh Siddha * APIC command line parameters 139279f1461SSuresh Siddha */ 140279f1461SSuresh Siddha static int __init parse_lapic(char *arg) 141279f1461SSuresh Siddha { 142279f1461SSuresh Siddha if (config_enabled(CONFIG_X86_32) && !arg) 143279f1461SSuresh Siddha force_enable_local_apic = 1; 14427cf9298SMathias Krause else if (arg && !strncmp(arg, "notscdeadline", 13)) 145279f1461SSuresh Siddha setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 146279f1461SSuresh Siddha return 0; 147279f1461SSuresh Siddha } 148279f1461SSuresh Siddha early_param("lapic", parse_lapic); 149279f1461SSuresh Siddha 150f62bae50SIngo Molnar #ifdef CONFIG_X86_64 151f62bae50SIngo Molnar static int apic_calibrate_pmtmr __initdata; 152f62bae50SIngo Molnar static __init int setup_apicpmtimer(char *s) 153f62bae50SIngo Molnar { 154f62bae50SIngo Molnar apic_calibrate_pmtmr = 1; 155f62bae50SIngo Molnar notsc_setup(NULL); 156f62bae50SIngo Molnar return 0; 157f62bae50SIngo Molnar } 158f62bae50SIngo Molnar __setup("apicpmtimer", setup_apicpmtimer); 159f62bae50SIngo Molnar #endif 160f62bae50SIngo Molnar 161f62bae50SIngo Molnar unsigned long mp_lapic_addr; 162f62bae50SIngo Molnar int disable_apic; 163f62bae50SIngo Molnar /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 16425874a29SHenrik Kretzschmar static int disable_apic_timer __initdata; 165f62bae50SIngo Molnar /* Local APIC timer works in C2 */ 166f62bae50SIngo Molnar int local_apic_timer_c2_ok; 167f62bae50SIngo Molnar EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 168f62bae50SIngo Molnar 1692414e021SJan Beulich int first_system_vector = FIRST_SYSTEM_VECTOR; 170f62bae50SIngo Molnar 171f62bae50SIngo Molnar /* 172f62bae50SIngo Molnar * Debug level, exported for io_apic.c 173f62bae50SIngo Molnar */ 174f62bae50SIngo Molnar unsigned int apic_verbosity; 175f62bae50SIngo Molnar 176f62bae50SIngo Molnar int pic_mode; 177f62bae50SIngo Molnar 178f62bae50SIngo Molnar /* Have we found an MP table */ 179f62bae50SIngo Molnar int smp_found_config; 180f62bae50SIngo Molnar 181f62bae50SIngo Molnar static struct resource lapic_resource = { 182f62bae50SIngo Molnar .name = "Local APIC", 183f62bae50SIngo Molnar .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 184f62bae50SIngo Molnar }; 185f62bae50SIngo Molnar 1861ade93efSJacob Pan unsigned int lapic_timer_frequency = 0; 187f62bae50SIngo Molnar 188f62bae50SIngo Molnar static void apic_pm_activate(void); 189f62bae50SIngo Molnar 190f62bae50SIngo Molnar static unsigned long apic_phys; 191f62bae50SIngo Molnar 192f62bae50SIngo Molnar /* 193f62bae50SIngo Molnar * Get the LAPIC version 194f62bae50SIngo Molnar */ 195f62bae50SIngo Molnar static inline int lapic_get_version(void) 196f62bae50SIngo Molnar { 197f62bae50SIngo Molnar return GET_APIC_VERSION(apic_read(APIC_LVR)); 198f62bae50SIngo Molnar } 199f62bae50SIngo Molnar 200f62bae50SIngo Molnar /* 201f62bae50SIngo Molnar * Check, if the APIC is integrated or a separate chip 202f62bae50SIngo Molnar */ 203f62bae50SIngo Molnar static inline int lapic_is_integrated(void) 204f62bae50SIngo Molnar { 205f62bae50SIngo Molnar #ifdef CONFIG_X86_64 206f62bae50SIngo Molnar return 1; 207f62bae50SIngo Molnar #else 208f62bae50SIngo Molnar return APIC_INTEGRATED(lapic_get_version()); 209f62bae50SIngo Molnar #endif 210f62bae50SIngo Molnar } 211f62bae50SIngo Molnar 212f62bae50SIngo Molnar /* 213f62bae50SIngo Molnar * Check, whether this is a modern or a first generation APIC 214f62bae50SIngo Molnar */ 215f62bae50SIngo Molnar static int modern_apic(void) 216f62bae50SIngo Molnar { 217f62bae50SIngo Molnar /* AMD systems use old APIC versions, so check the CPU */ 218f62bae50SIngo Molnar if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 219f62bae50SIngo Molnar boot_cpu_data.x86 >= 0xf) 220f62bae50SIngo Molnar return 1; 221f62bae50SIngo Molnar return lapic_get_version() >= 0x14; 222f62bae50SIngo Molnar } 223f62bae50SIngo Molnar 22408306ce6SCyrill Gorcunov /* 225a933c618SCyrill Gorcunov * right after this call apic become NOOP driven 226a933c618SCyrill Gorcunov * so apic->write/read doesn't do anything 22708306ce6SCyrill Gorcunov */ 22825874a29SHenrik Kretzschmar static void __init apic_disable(void) 22908306ce6SCyrill Gorcunov { 230f88f2b4fSCyrill Gorcunov pr_info("APIC: switched to apic NOOP\n"); 231a933c618SCyrill Gorcunov apic = &apic_noop; 23208306ce6SCyrill Gorcunov } 23308306ce6SCyrill Gorcunov 234f62bae50SIngo Molnar void native_apic_wait_icr_idle(void) 235f62bae50SIngo Molnar { 236f62bae50SIngo Molnar while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 237f62bae50SIngo Molnar cpu_relax(); 238f62bae50SIngo Molnar } 239f62bae50SIngo Molnar 240f62bae50SIngo Molnar u32 native_safe_apic_wait_icr_idle(void) 241f62bae50SIngo Molnar { 242f62bae50SIngo Molnar u32 send_status; 243f62bae50SIngo Molnar int timeout; 244f62bae50SIngo Molnar 245f62bae50SIngo Molnar timeout = 0; 246f62bae50SIngo Molnar do { 247f62bae50SIngo Molnar send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 248f62bae50SIngo Molnar if (!send_status) 249f62bae50SIngo Molnar break; 250b49d7d87SFernando Luis Vazquez Cao inc_irq_stat(icr_read_retry_count); 251f62bae50SIngo Molnar udelay(100); 252f62bae50SIngo Molnar } while (timeout++ < 1000); 253f62bae50SIngo Molnar 254f62bae50SIngo Molnar return send_status; 255f62bae50SIngo Molnar } 256f62bae50SIngo Molnar 257f62bae50SIngo Molnar void native_apic_icr_write(u32 low, u32 id) 258f62bae50SIngo Molnar { 259ea7bdc65SJan Kiszka unsigned long flags; 260ea7bdc65SJan Kiszka 261ea7bdc65SJan Kiszka local_irq_save(flags); 262f62bae50SIngo Molnar apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 263f62bae50SIngo Molnar apic_write(APIC_ICR, low); 264ea7bdc65SJan Kiszka local_irq_restore(flags); 265f62bae50SIngo Molnar } 266f62bae50SIngo Molnar 267f62bae50SIngo Molnar u64 native_apic_icr_read(void) 268f62bae50SIngo Molnar { 269f62bae50SIngo Molnar u32 icr1, icr2; 270f62bae50SIngo Molnar 271f62bae50SIngo Molnar icr2 = apic_read(APIC_ICR2); 272f62bae50SIngo Molnar icr1 = apic_read(APIC_ICR); 273f62bae50SIngo Molnar 274f62bae50SIngo Molnar return icr1 | ((u64)icr2 << 32); 275f62bae50SIngo Molnar } 276f62bae50SIngo Molnar 277f62bae50SIngo Molnar #ifdef CONFIG_X86_32 278f62bae50SIngo Molnar /** 279f62bae50SIngo Molnar * get_physical_broadcast - Get number of physical broadcast IDs 280f62bae50SIngo Molnar */ 281f62bae50SIngo Molnar int get_physical_broadcast(void) 282f62bae50SIngo Molnar { 283f62bae50SIngo Molnar return modern_apic() ? 0xff : 0xf; 284f62bae50SIngo Molnar } 285f62bae50SIngo Molnar #endif 286f62bae50SIngo Molnar 287f62bae50SIngo Molnar /** 288f62bae50SIngo Molnar * lapic_get_maxlvt - get the maximum number of local vector table entries 289f62bae50SIngo Molnar */ 290f62bae50SIngo Molnar int lapic_get_maxlvt(void) 291f62bae50SIngo Molnar { 292f62bae50SIngo Molnar unsigned int v; 293f62bae50SIngo Molnar 294f62bae50SIngo Molnar v = apic_read(APIC_LVR); 295f62bae50SIngo Molnar /* 296f62bae50SIngo Molnar * - we always have APIC integrated on 64bit mode 297f62bae50SIngo Molnar * - 82489DXs do not report # of LVT entries 298f62bae50SIngo Molnar */ 299f62bae50SIngo Molnar return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; 300f62bae50SIngo Molnar } 301f62bae50SIngo Molnar 302f62bae50SIngo Molnar /* 303f62bae50SIngo Molnar * Local APIC timer 304f62bae50SIngo Molnar */ 305f62bae50SIngo Molnar 306f62bae50SIngo Molnar /* Clock divisor */ 307f62bae50SIngo Molnar #define APIC_DIVISOR 16 308279f1461SSuresh Siddha #define TSC_DIVISOR 32 309f62bae50SIngo Molnar 310f62bae50SIngo Molnar /* 311f62bae50SIngo Molnar * This function sets up the local APIC timer, with a timeout of 312f62bae50SIngo Molnar * 'clocks' APIC bus clock. During calibration we actually call 313f62bae50SIngo Molnar * this function twice on the boot CPU, once with a bogus timeout 314f62bae50SIngo Molnar * value, second time for real. The other (noncalibrating) CPUs 315f62bae50SIngo Molnar * call this function only once, with the real, calibrated value. 316f62bae50SIngo Molnar * 317f62bae50SIngo Molnar * We do reads before writes even if unnecessary, to get around the 318f62bae50SIngo Molnar * P5 APIC double write bug. 319f62bae50SIngo Molnar */ 320f62bae50SIngo Molnar static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 321f62bae50SIngo Molnar { 322f62bae50SIngo Molnar unsigned int lvtt_value, tmp_value; 323f62bae50SIngo Molnar 324f62bae50SIngo Molnar lvtt_value = LOCAL_TIMER_VECTOR; 325f62bae50SIngo Molnar if (!oneshot) 326f62bae50SIngo Molnar lvtt_value |= APIC_LVT_TIMER_PERIODIC; 327279f1461SSuresh Siddha else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 328279f1461SSuresh Siddha lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; 329279f1461SSuresh Siddha 330f62bae50SIngo Molnar if (!lapic_is_integrated()) 331f62bae50SIngo Molnar lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 332f62bae50SIngo Molnar 333f62bae50SIngo Molnar if (!irqen) 334f62bae50SIngo Molnar lvtt_value |= APIC_LVT_MASKED; 335f62bae50SIngo Molnar 336f62bae50SIngo Molnar apic_write(APIC_LVTT, lvtt_value); 337f62bae50SIngo Molnar 338279f1461SSuresh Siddha if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { 3395d7c631dSShaohua Li /* 3405d7c631dSShaohua Li * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, 3415d7c631dSShaohua Li * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. 3425d7c631dSShaohua Li * According to Intel, MFENCE can do the serialization here. 3435d7c631dSShaohua Li */ 3445d7c631dSShaohua Li asm volatile("mfence" : : : "memory"); 3455d7c631dSShaohua Li 346279f1461SSuresh Siddha printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); 347279f1461SSuresh Siddha return; 348279f1461SSuresh Siddha } 349279f1461SSuresh Siddha 350f62bae50SIngo Molnar /* 351f62bae50SIngo Molnar * Divide PICLK by 16 352f62bae50SIngo Molnar */ 353f62bae50SIngo Molnar tmp_value = apic_read(APIC_TDCR); 354f62bae50SIngo Molnar apic_write(APIC_TDCR, 355f62bae50SIngo Molnar (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 356f62bae50SIngo Molnar APIC_TDR_DIV_16); 357f62bae50SIngo Molnar 358f62bae50SIngo Molnar if (!oneshot) 359f62bae50SIngo Molnar apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 360f62bae50SIngo Molnar } 361f62bae50SIngo Molnar 362f62bae50SIngo Molnar /* 363a68c439bSRobert Richter * Setup extended LVT, AMD specific 364f62bae50SIngo Molnar * 365a68c439bSRobert Richter * Software should use the LVT offsets the BIOS provides. The offsets 366a68c439bSRobert Richter * are determined by the subsystems using it like those for MCE 367a68c439bSRobert Richter * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 368a68c439bSRobert Richter * are supported. Beginning with family 10h at least 4 offsets are 369a68c439bSRobert Richter * available. 370f62bae50SIngo Molnar * 371a68c439bSRobert Richter * Since the offsets must be consistent for all cores, we keep track 372a68c439bSRobert Richter * of the LVT offsets in software and reserve the offset for the same 373a68c439bSRobert Richter * vector also to be used on other cores. An offset is freed by 374a68c439bSRobert Richter * setting the entry to APIC_EILVT_MASKED. 375a68c439bSRobert Richter * 376a68c439bSRobert Richter * If the BIOS is right, there should be no conflicts. Otherwise a 377a68c439bSRobert Richter * "[Firmware Bug]: ..." error message is generated. However, if 378a68c439bSRobert Richter * software does not properly determines the offsets, it is not 379a68c439bSRobert Richter * necessarily a BIOS bug. 380f62bae50SIngo Molnar */ 381f62bae50SIngo Molnar 382a68c439bSRobert Richter static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 383f62bae50SIngo Molnar 384a68c439bSRobert Richter static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 385a68c439bSRobert Richter { 386a68c439bSRobert Richter return (old & APIC_EILVT_MASKED) 387a68c439bSRobert Richter || (new == APIC_EILVT_MASKED) 388a68c439bSRobert Richter || ((new & ~APIC_EILVT_MASKED) == old); 389a68c439bSRobert Richter } 390a68c439bSRobert Richter 391a68c439bSRobert Richter static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 392a68c439bSRobert Richter { 3938abc3122SRobert Richter unsigned int rsvd, vector; 394a68c439bSRobert Richter 395a68c439bSRobert Richter if (offset >= APIC_EILVT_NR_MAX) 396a68c439bSRobert Richter return ~0; 397a68c439bSRobert Richter 3988abc3122SRobert Richter rsvd = atomic_read(&eilvt_offsets[offset]); 399a68c439bSRobert Richter do { 4008abc3122SRobert Richter vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ 4018abc3122SRobert Richter if (vector && !eilvt_entry_is_changeable(vector, new)) 402a68c439bSRobert Richter /* may not change if vectors are different */ 403a68c439bSRobert Richter return rsvd; 404a68c439bSRobert Richter rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 405a68c439bSRobert Richter } while (rsvd != new); 406a68c439bSRobert Richter 4078abc3122SRobert Richter rsvd &= ~APIC_EILVT_MASKED; 4088abc3122SRobert Richter if (rsvd && rsvd != vector) 4098abc3122SRobert Richter pr_info("LVT offset %d assigned for vector 0x%02x\n", 4108abc3122SRobert Richter offset, rsvd); 4118abc3122SRobert Richter 412a68c439bSRobert Richter return new; 413a68c439bSRobert Richter } 414a68c439bSRobert Richter 415a68c439bSRobert Richter /* 416a68c439bSRobert Richter * If mask=1, the LVT entry does not generate interrupts while mask=0 417cbf74ceaSRobert Richter * enables the vector. See also the BKDGs. Must be called with 418cbf74ceaSRobert Richter * preemption disabled. 419a68c439bSRobert Richter */ 420a68c439bSRobert Richter 42127afdf20SRobert Richter int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 422a68c439bSRobert Richter { 423a68c439bSRobert Richter unsigned long reg = APIC_EILVTn(offset); 424a68c439bSRobert Richter unsigned int new, old, reserved; 425a68c439bSRobert Richter 426a68c439bSRobert Richter new = (mask << 16) | (msg_type << 8) | vector; 427a68c439bSRobert Richter old = apic_read(reg); 428a68c439bSRobert Richter reserved = reserve_eilvt_offset(offset, new); 429a68c439bSRobert Richter 430a68c439bSRobert Richter if (reserved != new) { 431eb48c9cbSRobert Richter pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 432eb48c9cbSRobert Richter "vector 0x%x, but the register is already in use for " 433eb48c9cbSRobert Richter "vector 0x%x on another cpu\n", 434eb48c9cbSRobert Richter smp_processor_id(), reg, offset, new, reserved); 435a68c439bSRobert Richter return -EINVAL; 436a68c439bSRobert Richter } 437a68c439bSRobert Richter 438a68c439bSRobert Richter if (!eilvt_entry_is_changeable(old, new)) { 439eb48c9cbSRobert Richter pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 440eb48c9cbSRobert Richter "vector 0x%x, but the register is already in use for " 441eb48c9cbSRobert Richter "vector 0x%x on this cpu\n", 442eb48c9cbSRobert Richter smp_processor_id(), reg, offset, new, old); 443a68c439bSRobert Richter return -EBUSY; 444a68c439bSRobert Richter } 445a68c439bSRobert Richter 446a68c439bSRobert Richter apic_write(reg, new); 447a68c439bSRobert Richter 448a68c439bSRobert Richter return 0; 449f62bae50SIngo Molnar } 45027afdf20SRobert Richter EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 451f62bae50SIngo Molnar 452f62bae50SIngo Molnar /* 453f62bae50SIngo Molnar * Program the next event, relative to now 454f62bae50SIngo Molnar */ 455f62bae50SIngo Molnar static int lapic_next_event(unsigned long delta, 456f62bae50SIngo Molnar struct clock_event_device *evt) 457f62bae50SIngo Molnar { 458f62bae50SIngo Molnar apic_write(APIC_TMICT, delta); 459f62bae50SIngo Molnar return 0; 460f62bae50SIngo Molnar } 461f62bae50SIngo Molnar 462279f1461SSuresh Siddha static int lapic_next_deadline(unsigned long delta, 463279f1461SSuresh Siddha struct clock_event_device *evt) 464279f1461SSuresh Siddha { 465279f1461SSuresh Siddha u64 tsc; 466279f1461SSuresh Siddha 4674ea1636bSAndy Lutomirski tsc = rdtsc(); 468279f1461SSuresh Siddha wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); 469279f1461SSuresh Siddha return 0; 470279f1461SSuresh Siddha } 471279f1461SSuresh Siddha 472b23d8e52SViresh Kumar static int lapic_timer_shutdown(struct clock_event_device *evt) 473f62bae50SIngo Molnar { 474f62bae50SIngo Molnar unsigned int v; 475f62bae50SIngo Molnar 476f62bae50SIngo Molnar /* Lapic used as dummy for broadcast ? */ 477f62bae50SIngo Molnar if (evt->features & CLOCK_EVT_FEAT_DUMMY) 478b23d8e52SViresh Kumar return 0; 479f62bae50SIngo Molnar 480f62bae50SIngo Molnar v = apic_read(APIC_LVTT); 481f62bae50SIngo Molnar v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 482f62bae50SIngo Molnar apic_write(APIC_LVTT, v); 4836f9b4100SAndreas Herrmann apic_write(APIC_TMICT, 0); 484b23d8e52SViresh Kumar return 0; 485f62bae50SIngo Molnar } 486f62bae50SIngo Molnar 487b23d8e52SViresh Kumar static inline int 488b23d8e52SViresh Kumar lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot) 489b23d8e52SViresh Kumar { 490b23d8e52SViresh Kumar /* Lapic used as dummy for broadcast ? */ 491b23d8e52SViresh Kumar if (evt->features & CLOCK_EVT_FEAT_DUMMY) 492b23d8e52SViresh Kumar return 0; 493b23d8e52SViresh Kumar 494b23d8e52SViresh Kumar __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1); 495b23d8e52SViresh Kumar return 0; 496b23d8e52SViresh Kumar } 497b23d8e52SViresh Kumar 498b23d8e52SViresh Kumar static int lapic_timer_set_periodic(struct clock_event_device *evt) 499b23d8e52SViresh Kumar { 500b23d8e52SViresh Kumar return lapic_timer_set_periodic_oneshot(evt, false); 501b23d8e52SViresh Kumar } 502b23d8e52SViresh Kumar 503b23d8e52SViresh Kumar static int lapic_timer_set_oneshot(struct clock_event_device *evt) 504b23d8e52SViresh Kumar { 505b23d8e52SViresh Kumar return lapic_timer_set_periodic_oneshot(evt, true); 506f62bae50SIngo Molnar } 507f62bae50SIngo Molnar 508f62bae50SIngo Molnar /* 509f62bae50SIngo Molnar * Local APIC timer broadcast function 510f62bae50SIngo Molnar */ 511f62bae50SIngo Molnar static void lapic_timer_broadcast(const struct cpumask *mask) 512f62bae50SIngo Molnar { 513f62bae50SIngo Molnar #ifdef CONFIG_SMP 514f62bae50SIngo Molnar apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 515f62bae50SIngo Molnar #endif 516f62bae50SIngo Molnar } 517f62bae50SIngo Molnar 51825874a29SHenrik Kretzschmar 51925874a29SHenrik Kretzschmar /* 52025874a29SHenrik Kretzschmar * The local apic timer can be used for any function which is CPU local. 52125874a29SHenrik Kretzschmar */ 52225874a29SHenrik Kretzschmar static struct clock_event_device lapic_clockevent = { 52325874a29SHenrik Kretzschmar .name = "lapic", 524b23d8e52SViresh Kumar .features = CLOCK_EVT_FEAT_PERIODIC | 525b23d8e52SViresh Kumar CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP 526b23d8e52SViresh Kumar | CLOCK_EVT_FEAT_DUMMY, 52725874a29SHenrik Kretzschmar .shift = 32, 528b23d8e52SViresh Kumar .set_state_shutdown = lapic_timer_shutdown, 529b23d8e52SViresh Kumar .set_state_periodic = lapic_timer_set_periodic, 530b23d8e52SViresh Kumar .set_state_oneshot = lapic_timer_set_oneshot, 53125874a29SHenrik Kretzschmar .set_next_event = lapic_next_event, 53225874a29SHenrik Kretzschmar .broadcast = lapic_timer_broadcast, 53325874a29SHenrik Kretzschmar .rating = 100, 53425874a29SHenrik Kretzschmar .irq = -1, 53525874a29SHenrik Kretzschmar }; 53625874a29SHenrik Kretzschmar static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 53725874a29SHenrik Kretzschmar 538f62bae50SIngo Molnar /* 539421f91d2SUwe Kleine-König * Setup the local APIC timer for this CPU. Copy the initialized values 540f62bae50SIngo Molnar * of the boot CPU and register the clock event in the framework. 541f62bae50SIngo Molnar */ 542148f9bb8SPaul Gortmaker static void setup_APIC_timer(void) 543f62bae50SIngo Molnar { 54489cbc767SChristoph Lameter struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 545f62bae50SIngo Molnar 546349c004eSChristoph Lameter if (this_cpu_has(X86_FEATURE_ARAT)) { 547db954b58SVenkatesh Pallipadi lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 548db954b58SVenkatesh Pallipadi /* Make LAPIC timer preferrable over percpu HPET */ 549db954b58SVenkatesh Pallipadi lapic_clockevent.rating = 150; 550db954b58SVenkatesh Pallipadi } 551db954b58SVenkatesh Pallipadi 552f62bae50SIngo Molnar memcpy(levt, &lapic_clockevent, sizeof(*levt)); 553f62bae50SIngo Molnar levt->cpumask = cpumask_of(smp_processor_id()); 554f62bae50SIngo Molnar 555279f1461SSuresh Siddha if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 556279f1461SSuresh Siddha levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | 557279f1461SSuresh Siddha CLOCK_EVT_FEAT_DUMMY); 558279f1461SSuresh Siddha levt->set_next_event = lapic_next_deadline; 559279f1461SSuresh Siddha clockevents_config_and_register(levt, 560279f1461SSuresh Siddha (tsc_khz / TSC_DIVISOR) * 1000, 561279f1461SSuresh Siddha 0xF, ~0UL); 562279f1461SSuresh Siddha } else 563f62bae50SIngo Molnar clockevents_register_device(levt); 564f62bae50SIngo Molnar } 565f62bae50SIngo Molnar 566f62bae50SIngo Molnar /* 567f62bae50SIngo Molnar * In this functions we calibrate APIC bus clocks to the external timer. 568f62bae50SIngo Molnar * 569f62bae50SIngo Molnar * We want to do the calibration only once since we want to have local timer 570f62bae50SIngo Molnar * irqs syncron. CPUs connected by the same APIC bus have the very same bus 571f62bae50SIngo Molnar * frequency. 572f62bae50SIngo Molnar * 573f62bae50SIngo Molnar * This was previously done by reading the PIT/HPET and waiting for a wrap 574f62bae50SIngo Molnar * around to find out, that a tick has elapsed. I have a box, where the PIT 575f62bae50SIngo Molnar * readout is broken, so it never gets out of the wait loop again. This was 576f62bae50SIngo Molnar * also reported by others. 577f62bae50SIngo Molnar * 578f62bae50SIngo Molnar * Monitoring the jiffies value is inaccurate and the clockevents 579f62bae50SIngo Molnar * infrastructure allows us to do a simple substitution of the interrupt 580f62bae50SIngo Molnar * handler. 581f62bae50SIngo Molnar * 582f62bae50SIngo Molnar * The calibration routine also uses the pm_timer when possible, as the PIT 583f62bae50SIngo Molnar * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 584f62bae50SIngo Molnar * back to normal later in the boot process). 585f62bae50SIngo Molnar */ 586f62bae50SIngo Molnar 587f62bae50SIngo Molnar #define LAPIC_CAL_LOOPS (HZ/10) 588f62bae50SIngo Molnar 589f62bae50SIngo Molnar static __initdata int lapic_cal_loops = -1; 590f62bae50SIngo Molnar static __initdata long lapic_cal_t1, lapic_cal_t2; 591f62bae50SIngo Molnar static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 592f62bae50SIngo Molnar static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 593f62bae50SIngo Molnar static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 594f62bae50SIngo Molnar 595f62bae50SIngo Molnar /* 596f62bae50SIngo Molnar * Temporary interrupt handler. 597f62bae50SIngo Molnar */ 598f62bae50SIngo Molnar static void __init lapic_cal_handler(struct clock_event_device *dev) 599f62bae50SIngo Molnar { 600f62bae50SIngo Molnar unsigned long long tsc = 0; 601f62bae50SIngo Molnar long tapic = apic_read(APIC_TMCCT); 602f62bae50SIngo Molnar unsigned long pm = acpi_pm_read_early(); 603f62bae50SIngo Molnar 604f62bae50SIngo Molnar if (cpu_has_tsc) 6054ea1636bSAndy Lutomirski tsc = rdtsc(); 606f62bae50SIngo Molnar 607f62bae50SIngo Molnar switch (lapic_cal_loops++) { 608f62bae50SIngo Molnar case 0: 609f62bae50SIngo Molnar lapic_cal_t1 = tapic; 610f62bae50SIngo Molnar lapic_cal_tsc1 = tsc; 611f62bae50SIngo Molnar lapic_cal_pm1 = pm; 612f62bae50SIngo Molnar lapic_cal_j1 = jiffies; 613f62bae50SIngo Molnar break; 614f62bae50SIngo Molnar 615f62bae50SIngo Molnar case LAPIC_CAL_LOOPS: 616f62bae50SIngo Molnar lapic_cal_t2 = tapic; 617f62bae50SIngo Molnar lapic_cal_tsc2 = tsc; 618f62bae50SIngo Molnar if (pm < lapic_cal_pm1) 619f62bae50SIngo Molnar pm += ACPI_PM_OVRRUN; 620f62bae50SIngo Molnar lapic_cal_pm2 = pm; 621f62bae50SIngo Molnar lapic_cal_j2 = jiffies; 622f62bae50SIngo Molnar break; 623f62bae50SIngo Molnar } 624f62bae50SIngo Molnar } 625f62bae50SIngo Molnar 626f62bae50SIngo Molnar static int __init 627f62bae50SIngo Molnar calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 628f62bae50SIngo Molnar { 629f62bae50SIngo Molnar const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 630f62bae50SIngo Molnar const long pm_thresh = pm_100ms / 100; 631f62bae50SIngo Molnar unsigned long mult; 632f62bae50SIngo Molnar u64 res; 633f62bae50SIngo Molnar 634f62bae50SIngo Molnar #ifndef CONFIG_X86_PM_TIMER 635f62bae50SIngo Molnar return -1; 636f62bae50SIngo Molnar #endif 637f62bae50SIngo Molnar 638f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 639f62bae50SIngo Molnar 640f62bae50SIngo Molnar /* Check, if the PM timer is available */ 641f62bae50SIngo Molnar if (!deltapm) 642f62bae50SIngo Molnar return -1; 643f62bae50SIngo Molnar 644f62bae50SIngo Molnar mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 645f62bae50SIngo Molnar 646f62bae50SIngo Molnar if (deltapm > (pm_100ms - pm_thresh) && 647f62bae50SIngo Molnar deltapm < (pm_100ms + pm_thresh)) { 648f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 649f62bae50SIngo Molnar return 0; 650f62bae50SIngo Molnar } 651f62bae50SIngo Molnar 652f62bae50SIngo Molnar res = (((u64)deltapm) * mult) >> 22; 653f62bae50SIngo Molnar do_div(res, 1000000); 654f62bae50SIngo Molnar pr_warning("APIC calibration not consistent " 655f62bae50SIngo Molnar "with PM-Timer: %ldms instead of 100ms\n",(long)res); 656f62bae50SIngo Molnar 657f62bae50SIngo Molnar /* Correct the lapic counter value */ 658f62bae50SIngo Molnar res = (((u64)(*delta)) * pm_100ms); 659f62bae50SIngo Molnar do_div(res, deltapm); 660f62bae50SIngo Molnar pr_info("APIC delta adjusted to PM-Timer: " 661f62bae50SIngo Molnar "%lu (%ld)\n", (unsigned long)res, *delta); 662f62bae50SIngo Molnar *delta = (long)res; 663f62bae50SIngo Molnar 664f62bae50SIngo Molnar /* Correct the tsc counter value */ 665f62bae50SIngo Molnar if (cpu_has_tsc) { 666f62bae50SIngo Molnar res = (((u64)(*deltatsc)) * pm_100ms); 667f62bae50SIngo Molnar do_div(res, deltapm); 668f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 669f62bae50SIngo Molnar "PM-Timer: %lu (%ld)\n", 670f62bae50SIngo Molnar (unsigned long)res, *deltatsc); 671f62bae50SIngo Molnar *deltatsc = (long)res; 672f62bae50SIngo Molnar } 673f62bae50SIngo Molnar 674f62bae50SIngo Molnar return 0; 675f62bae50SIngo Molnar } 676f62bae50SIngo Molnar 677f62bae50SIngo Molnar static int __init calibrate_APIC_clock(void) 678f62bae50SIngo Molnar { 67989cbc767SChristoph Lameter struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 680f62bae50SIngo Molnar void (*real_handler)(struct clock_event_device *dev); 681f62bae50SIngo Molnar unsigned long deltaj; 682f62bae50SIngo Molnar long delta, deltatsc; 683f62bae50SIngo Molnar int pm_referenced = 0; 684f62bae50SIngo Molnar 6851ade93efSJacob Pan /** 6861ade93efSJacob Pan * check if lapic timer has already been calibrated by platform 6871ade93efSJacob Pan * specific routine, such as tsc calibration code. if so, we just fill 6881ade93efSJacob Pan * in the clockevent structure and return. 6891ade93efSJacob Pan */ 6901ade93efSJacob Pan 691279f1461SSuresh Siddha if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 692279f1461SSuresh Siddha return 0; 693279f1461SSuresh Siddha } else if (lapic_timer_frequency) { 6941ade93efSJacob Pan apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", 6951ade93efSJacob Pan lapic_timer_frequency); 6961ade93efSJacob Pan lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR, 6971ade93efSJacob Pan TICK_NSEC, lapic_clockevent.shift); 6981ade93efSJacob Pan lapic_clockevent.max_delta_ns = 6991ade93efSJacob Pan clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); 7001ade93efSJacob Pan lapic_clockevent.min_delta_ns = 7011ade93efSJacob Pan clockevent_delta2ns(0xF, &lapic_clockevent); 7021ade93efSJacob Pan lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 7031ade93efSJacob Pan return 0; 7041ade93efSJacob Pan } 7051ade93efSJacob Pan 706279f1461SSuresh Siddha apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 707279f1461SSuresh Siddha "calibrating APIC timer ...\n"); 708279f1461SSuresh Siddha 709f62bae50SIngo Molnar local_irq_disable(); 710f62bae50SIngo Molnar 711f62bae50SIngo Molnar /* Replace the global interrupt handler */ 712f62bae50SIngo Molnar real_handler = global_clock_event->event_handler; 713f62bae50SIngo Molnar global_clock_event->event_handler = lapic_cal_handler; 714f62bae50SIngo Molnar 715f62bae50SIngo Molnar /* 716f62bae50SIngo Molnar * Setup the APIC counter to maximum. There is no way the lapic 717f62bae50SIngo Molnar * can underflow in the 100ms detection time frame 718f62bae50SIngo Molnar */ 719f62bae50SIngo Molnar __setup_APIC_LVTT(0xffffffff, 0, 0); 720f62bae50SIngo Molnar 721f62bae50SIngo Molnar /* Let the interrupts run */ 722f62bae50SIngo Molnar local_irq_enable(); 723f62bae50SIngo Molnar 724f62bae50SIngo Molnar while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 725f62bae50SIngo Molnar cpu_relax(); 726f62bae50SIngo Molnar 727f62bae50SIngo Molnar local_irq_disable(); 728f62bae50SIngo Molnar 729f62bae50SIngo Molnar /* Restore the real event handler */ 730f62bae50SIngo Molnar global_clock_event->event_handler = real_handler; 731f62bae50SIngo Molnar 732f62bae50SIngo Molnar /* Build delta t1-t2 as apic timer counts down */ 733f62bae50SIngo Molnar delta = lapic_cal_t1 - lapic_cal_t2; 734f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 735f62bae50SIngo Molnar 736f62bae50SIngo Molnar deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 737f62bae50SIngo Molnar 738f62bae50SIngo Molnar /* we trust the PM based calibration if possible */ 739f62bae50SIngo Molnar pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 740f62bae50SIngo Molnar &delta, &deltatsc); 741f62bae50SIngo Molnar 742f62bae50SIngo Molnar /* Calculate the scaled math multiplication factor */ 743f62bae50SIngo Molnar lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 744f62bae50SIngo Molnar lapic_clockevent.shift); 745f62bae50SIngo Molnar lapic_clockevent.max_delta_ns = 7464aed89d6SPierre Tardy clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 747f62bae50SIngo Molnar lapic_clockevent.min_delta_ns = 748f62bae50SIngo Molnar clockevent_delta2ns(0xF, &lapic_clockevent); 749f62bae50SIngo Molnar 7501ade93efSJacob Pan lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 751f62bae50SIngo Molnar 752f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 753411462f6SThomas Gleixner apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 754f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 7551ade93efSJacob Pan lapic_timer_frequency); 756f62bae50SIngo Molnar 757f62bae50SIngo Molnar if (cpu_has_tsc) { 758f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 759f62bae50SIngo Molnar "%ld.%04ld MHz.\n", 760f62bae50SIngo Molnar (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 761f62bae50SIngo Molnar (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 762f62bae50SIngo Molnar } 763f62bae50SIngo Molnar 764f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 765f62bae50SIngo Molnar "%u.%04u MHz.\n", 7661ade93efSJacob Pan lapic_timer_frequency / (1000000 / HZ), 7671ade93efSJacob Pan lapic_timer_frequency % (1000000 / HZ)); 768f62bae50SIngo Molnar 769f62bae50SIngo Molnar /* 770f62bae50SIngo Molnar * Do a sanity check on the APIC calibration result 771f62bae50SIngo Molnar */ 7721ade93efSJacob Pan if (lapic_timer_frequency < (1000000 / HZ)) { 773f62bae50SIngo Molnar local_irq_enable(); 774f62bae50SIngo Molnar pr_warning("APIC frequency too slow, disabling apic timer\n"); 775f62bae50SIngo Molnar return -1; 776f62bae50SIngo Molnar } 777f62bae50SIngo Molnar 778f62bae50SIngo Molnar levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 779f62bae50SIngo Molnar 780f62bae50SIngo Molnar /* 781f62bae50SIngo Molnar * PM timer calibration failed or not turned on 782f62bae50SIngo Molnar * so lets try APIC timer based calibration 783f62bae50SIngo Molnar */ 784f62bae50SIngo Molnar if (!pm_referenced) { 785f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 786f62bae50SIngo Molnar 787f62bae50SIngo Molnar /* 788f62bae50SIngo Molnar * Setup the apic timer manually 789f62bae50SIngo Molnar */ 790f62bae50SIngo Molnar levt->event_handler = lapic_cal_handler; 791b23d8e52SViresh Kumar lapic_timer_set_periodic(levt); 792f62bae50SIngo Molnar lapic_cal_loops = -1; 793f62bae50SIngo Molnar 794f62bae50SIngo Molnar /* Let the interrupts run */ 795f62bae50SIngo Molnar local_irq_enable(); 796f62bae50SIngo Molnar 797f62bae50SIngo Molnar while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 798f62bae50SIngo Molnar cpu_relax(); 799f62bae50SIngo Molnar 800f62bae50SIngo Molnar /* Stop the lapic timer */ 801c948c260SThomas Gleixner local_irq_disable(); 802b23d8e52SViresh Kumar lapic_timer_shutdown(levt); 803f62bae50SIngo Molnar 804f62bae50SIngo Molnar /* Jiffies delta */ 805f62bae50SIngo Molnar deltaj = lapic_cal_j2 - lapic_cal_j1; 806f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 807f62bae50SIngo Molnar 808f62bae50SIngo Molnar /* Check, if the jiffies result is consistent */ 809f62bae50SIngo Molnar if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 810f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 811f62bae50SIngo Molnar else 812f62bae50SIngo Molnar levt->features |= CLOCK_EVT_FEAT_DUMMY; 813c948c260SThomas Gleixner } 814f62bae50SIngo Molnar local_irq_enable(); 815f62bae50SIngo Molnar 816f62bae50SIngo Molnar if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 817f62bae50SIngo Molnar pr_warning("APIC timer disabled due to verification failure\n"); 818f62bae50SIngo Molnar return -1; 819f62bae50SIngo Molnar } 820f62bae50SIngo Molnar 821f62bae50SIngo Molnar return 0; 822f62bae50SIngo Molnar } 823f62bae50SIngo Molnar 824f62bae50SIngo Molnar /* 825f62bae50SIngo Molnar * Setup the boot APIC 826f62bae50SIngo Molnar * 827f62bae50SIngo Molnar * Calibrate and verify the result. 828f62bae50SIngo Molnar */ 829f62bae50SIngo Molnar void __init setup_boot_APIC_clock(void) 830f62bae50SIngo Molnar { 831f62bae50SIngo Molnar /* 832f62bae50SIngo Molnar * The local apic timer can be disabled via the kernel 833f62bae50SIngo Molnar * commandline or from the CPU detection code. Register the lapic 834f62bae50SIngo Molnar * timer as a dummy clock event source on SMP systems, so the 835f62bae50SIngo Molnar * broadcast mechanism is used. On UP systems simply ignore it. 836f62bae50SIngo Molnar */ 837f62bae50SIngo Molnar if (disable_apic_timer) { 838f62bae50SIngo Molnar pr_info("Disabling APIC timer\n"); 839f62bae50SIngo Molnar /* No broadcast on UP ! */ 840f62bae50SIngo Molnar if (num_possible_cpus() > 1) { 841f62bae50SIngo Molnar lapic_clockevent.mult = 1; 842f62bae50SIngo Molnar setup_APIC_timer(); 843f62bae50SIngo Molnar } 844f62bae50SIngo Molnar return; 845f62bae50SIngo Molnar } 846f62bae50SIngo Molnar 847f62bae50SIngo Molnar if (calibrate_APIC_clock()) { 848f62bae50SIngo Molnar /* No broadcast on UP ! */ 849f62bae50SIngo Molnar if (num_possible_cpus() > 1) 850f62bae50SIngo Molnar setup_APIC_timer(); 851f62bae50SIngo Molnar return; 852f62bae50SIngo Molnar } 853f62bae50SIngo Molnar 854f62bae50SIngo Molnar /* 855f62bae50SIngo Molnar * If nmi_watchdog is set to IO_APIC, we need the 856f62bae50SIngo Molnar * PIT/HPET going. Otherwise register lapic as a dummy 857f62bae50SIngo Molnar * device. 858f62bae50SIngo Molnar */ 859f62bae50SIngo Molnar lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 860f62bae50SIngo Molnar 861f62bae50SIngo Molnar /* Setup the lapic or request the broadcast */ 862f62bae50SIngo Molnar setup_APIC_timer(); 863f62bae50SIngo Molnar } 864f62bae50SIngo Molnar 865148f9bb8SPaul Gortmaker void setup_secondary_APIC_clock(void) 866f62bae50SIngo Molnar { 867f62bae50SIngo Molnar setup_APIC_timer(); 868f62bae50SIngo Molnar } 869f62bae50SIngo Molnar 870f62bae50SIngo Molnar /* 871f62bae50SIngo Molnar * The guts of the apic timer interrupt 872f62bae50SIngo Molnar */ 873f62bae50SIngo Molnar static void local_apic_timer_interrupt(void) 874f62bae50SIngo Molnar { 875f62bae50SIngo Molnar int cpu = smp_processor_id(); 876f62bae50SIngo Molnar struct clock_event_device *evt = &per_cpu(lapic_events, cpu); 877f62bae50SIngo Molnar 878f62bae50SIngo Molnar /* 879f62bae50SIngo Molnar * Normally we should not be here till LAPIC has been initialized but 880f62bae50SIngo Molnar * in some cases like kdump, its possible that there is a pending LAPIC 881f62bae50SIngo Molnar * timer interrupt from previous kernel's context and is delivered in 882f62bae50SIngo Molnar * new kernel the moment interrupts are enabled. 883f62bae50SIngo Molnar * 884f62bae50SIngo Molnar * Interrupts are enabled early and LAPIC is setup much later, hence 885f62bae50SIngo Molnar * its possible that when we get here evt->event_handler is NULL. 886f62bae50SIngo Molnar * Check for event_handler being NULL and discard the interrupt as 887f62bae50SIngo Molnar * spurious. 888f62bae50SIngo Molnar */ 889f62bae50SIngo Molnar if (!evt->event_handler) { 890f62bae50SIngo Molnar pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); 891f62bae50SIngo Molnar /* Switch it off */ 892b23d8e52SViresh Kumar lapic_timer_shutdown(evt); 893f62bae50SIngo Molnar return; 894f62bae50SIngo Molnar } 895f62bae50SIngo Molnar 896f62bae50SIngo Molnar /* 897f62bae50SIngo Molnar * the NMI deadlock-detector uses this. 898f62bae50SIngo Molnar */ 899f62bae50SIngo Molnar inc_irq_stat(apic_timer_irqs); 900f62bae50SIngo Molnar 901f62bae50SIngo Molnar evt->event_handler(evt); 902f62bae50SIngo Molnar } 903f62bae50SIngo Molnar 904f62bae50SIngo Molnar /* 905f62bae50SIngo Molnar * Local APIC timer interrupt. This is the most natural way for doing 906f62bae50SIngo Molnar * local interrupts, but local timer interrupts can be emulated by 907f62bae50SIngo Molnar * broadcast interrupts too. [in case the hw doesn't support APIC timers] 908f62bae50SIngo Molnar * 909f62bae50SIngo Molnar * [ if a single-CPU system runs an SMP kernel then we call the local 910f62bae50SIngo Molnar * interrupt as well. Thus we cannot inline the local irq ... ] 911f62bae50SIngo Molnar */ 9121d9090e2SAndi Kleen __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 913f62bae50SIngo Molnar { 914f62bae50SIngo Molnar struct pt_regs *old_regs = set_irq_regs(regs); 915f62bae50SIngo Molnar 916f62bae50SIngo Molnar /* 917f62bae50SIngo Molnar * NOTE! We'd better ACK the irq immediately, 918f62bae50SIngo Molnar * because timer handling can be slow. 919eddc0e92SSeiji Aguchi * 920f62bae50SIngo Molnar * update_process_times() expects us to have done irq_enter(). 921f62bae50SIngo Molnar * Besides, if we don't timer interrupts ignore the global 922f62bae50SIngo Molnar * interrupt lock, which is the WrongThing (tm) to do. 923f62bae50SIngo Molnar */ 924eddc0e92SSeiji Aguchi entering_ack_irq(); 925f62bae50SIngo Molnar local_apic_timer_interrupt(); 926eddc0e92SSeiji Aguchi exiting_irq(); 927f62bae50SIngo Molnar 928f62bae50SIngo Molnar set_irq_regs(old_regs); 929f62bae50SIngo Molnar } 930f62bae50SIngo Molnar 9311d9090e2SAndi Kleen __visible void __irq_entry smp_trace_apic_timer_interrupt(struct pt_regs *regs) 932cf910e83SSeiji Aguchi { 933cf910e83SSeiji Aguchi struct pt_regs *old_regs = set_irq_regs(regs); 934cf910e83SSeiji Aguchi 935cf910e83SSeiji Aguchi /* 936cf910e83SSeiji Aguchi * NOTE! We'd better ACK the irq immediately, 937cf910e83SSeiji Aguchi * because timer handling can be slow. 938cf910e83SSeiji Aguchi * 939cf910e83SSeiji Aguchi * update_process_times() expects us to have done irq_enter(). 940cf910e83SSeiji Aguchi * Besides, if we don't timer interrupts ignore the global 941cf910e83SSeiji Aguchi * interrupt lock, which is the WrongThing (tm) to do. 942cf910e83SSeiji Aguchi */ 943cf910e83SSeiji Aguchi entering_ack_irq(); 944cf910e83SSeiji Aguchi trace_local_timer_entry(LOCAL_TIMER_VECTOR); 945cf910e83SSeiji Aguchi local_apic_timer_interrupt(); 946cf910e83SSeiji Aguchi trace_local_timer_exit(LOCAL_TIMER_VECTOR); 947cf910e83SSeiji Aguchi exiting_irq(); 948f62bae50SIngo Molnar 949f62bae50SIngo Molnar set_irq_regs(old_regs); 950f62bae50SIngo Molnar } 951f62bae50SIngo Molnar 952f62bae50SIngo Molnar int setup_profiling_timer(unsigned int multiplier) 953f62bae50SIngo Molnar { 954f62bae50SIngo Molnar return -EINVAL; 955f62bae50SIngo Molnar } 956f62bae50SIngo Molnar 957f62bae50SIngo Molnar /* 958f62bae50SIngo Molnar * Local APIC start and shutdown 959f62bae50SIngo Molnar */ 960f62bae50SIngo Molnar 961f62bae50SIngo Molnar /** 962f62bae50SIngo Molnar * clear_local_APIC - shutdown the local APIC 963f62bae50SIngo Molnar * 964f62bae50SIngo Molnar * This is called, when a CPU is disabled and before rebooting, so the state of 965f62bae50SIngo Molnar * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 966f62bae50SIngo Molnar * leftovers during boot. 967f62bae50SIngo Molnar */ 968f62bae50SIngo Molnar void clear_local_APIC(void) 969f62bae50SIngo Molnar { 970f62bae50SIngo Molnar int maxlvt; 971f62bae50SIngo Molnar u32 v; 972f62bae50SIngo Molnar 973f62bae50SIngo Molnar /* APIC hasn't been mapped yet */ 974fc1edaf9SSuresh Siddha if (!x2apic_mode && !apic_phys) 975f62bae50SIngo Molnar return; 976f62bae50SIngo Molnar 977f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 978f62bae50SIngo Molnar /* 979f62bae50SIngo Molnar * Masking an LVT entry can trigger a local APIC error 980f62bae50SIngo Molnar * if the vector is zero. Mask LVTERR first to prevent this. 981f62bae50SIngo Molnar */ 982f62bae50SIngo Molnar if (maxlvt >= 3) { 983f62bae50SIngo Molnar v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 984f62bae50SIngo Molnar apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 985f62bae50SIngo Molnar } 986f62bae50SIngo Molnar /* 987f62bae50SIngo Molnar * Careful: we have to set masks only first to deassert 988f62bae50SIngo Molnar * any level-triggered sources. 989f62bae50SIngo Molnar */ 990f62bae50SIngo Molnar v = apic_read(APIC_LVTT); 991f62bae50SIngo Molnar apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 992f62bae50SIngo Molnar v = apic_read(APIC_LVT0); 993f62bae50SIngo Molnar apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 994f62bae50SIngo Molnar v = apic_read(APIC_LVT1); 995f62bae50SIngo Molnar apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 996f62bae50SIngo Molnar if (maxlvt >= 4) { 997f62bae50SIngo Molnar v = apic_read(APIC_LVTPC); 998f62bae50SIngo Molnar apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 999f62bae50SIngo Molnar } 1000f62bae50SIngo Molnar 1001f62bae50SIngo Molnar /* lets not touch this if we didn't frob it */ 10024efc0670SAndi Kleen #ifdef CONFIG_X86_THERMAL_VECTOR 1003f62bae50SIngo Molnar if (maxlvt >= 5) { 1004f62bae50SIngo Molnar v = apic_read(APIC_LVTTHMR); 1005f62bae50SIngo Molnar apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 1006f62bae50SIngo Molnar } 1007f62bae50SIngo Molnar #endif 1008638bee71SH. Peter Anvin #ifdef CONFIG_X86_MCE_INTEL 1009638bee71SH. Peter Anvin if (maxlvt >= 6) { 1010638bee71SH. Peter Anvin v = apic_read(APIC_LVTCMCI); 1011638bee71SH. Peter Anvin if (!(v & APIC_LVT_MASKED)) 1012638bee71SH. Peter Anvin apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 1013638bee71SH. Peter Anvin } 1014638bee71SH. Peter Anvin #endif 1015638bee71SH. Peter Anvin 1016f62bae50SIngo Molnar /* 1017f62bae50SIngo Molnar * Clean APIC state for other OSs: 1018f62bae50SIngo Molnar */ 1019f62bae50SIngo Molnar apic_write(APIC_LVTT, APIC_LVT_MASKED); 1020f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_LVT_MASKED); 1021f62bae50SIngo Molnar apic_write(APIC_LVT1, APIC_LVT_MASKED); 1022f62bae50SIngo Molnar if (maxlvt >= 3) 1023f62bae50SIngo Molnar apic_write(APIC_LVTERR, APIC_LVT_MASKED); 1024f62bae50SIngo Molnar if (maxlvt >= 4) 1025f62bae50SIngo Molnar apic_write(APIC_LVTPC, APIC_LVT_MASKED); 1026f62bae50SIngo Molnar 1027f62bae50SIngo Molnar /* Integrated APIC (!82489DX) ? */ 1028f62bae50SIngo Molnar if (lapic_is_integrated()) { 1029f62bae50SIngo Molnar if (maxlvt > 3) 1030f62bae50SIngo Molnar /* Clear ESR due to Pentium errata 3AP and 11AP */ 1031f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1032f62bae50SIngo Molnar apic_read(APIC_ESR); 1033f62bae50SIngo Molnar } 1034f62bae50SIngo Molnar } 1035f62bae50SIngo Molnar 1036f62bae50SIngo Molnar /** 1037f62bae50SIngo Molnar * disable_local_APIC - clear and disable the local APIC 1038f62bae50SIngo Molnar */ 1039f62bae50SIngo Molnar void disable_local_APIC(void) 1040f62bae50SIngo Molnar { 1041f62bae50SIngo Molnar unsigned int value; 1042f62bae50SIngo Molnar 1043f62bae50SIngo Molnar /* APIC hasn't been mapped yet */ 1044fd19dce7SYinghai Lu if (!x2apic_mode && !apic_phys) 1045f62bae50SIngo Molnar return; 1046f62bae50SIngo Molnar 1047f62bae50SIngo Molnar clear_local_APIC(); 1048f62bae50SIngo Molnar 1049f62bae50SIngo Molnar /* 1050f62bae50SIngo Molnar * Disable APIC (implies clearing of registers 1051f62bae50SIngo Molnar * for 82489DX!). 1052f62bae50SIngo Molnar */ 1053f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 1054f62bae50SIngo Molnar value &= ~APIC_SPIV_APIC_ENABLED; 1055f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 1056f62bae50SIngo Molnar 1057f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1058f62bae50SIngo Molnar /* 1059f62bae50SIngo Molnar * When LAPIC was disabled by the BIOS and enabled by the kernel, 1060f62bae50SIngo Molnar * restore the disabled state. 1061f62bae50SIngo Molnar */ 1062f62bae50SIngo Molnar if (enabled_via_apicbase) { 1063f62bae50SIngo Molnar unsigned int l, h; 1064f62bae50SIngo Molnar 1065f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, l, h); 1066f62bae50SIngo Molnar l &= ~MSR_IA32_APICBASE_ENABLE; 1067f62bae50SIngo Molnar wrmsr(MSR_IA32_APICBASE, l, h); 1068f62bae50SIngo Molnar } 1069f62bae50SIngo Molnar #endif 1070f62bae50SIngo Molnar } 1071f62bae50SIngo Molnar 1072f62bae50SIngo Molnar /* 1073f62bae50SIngo Molnar * If Linux enabled the LAPIC against the BIOS default disable it down before 1074f62bae50SIngo Molnar * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 1075f62bae50SIngo Molnar * not power-off. Additionally clear all LVT entries before disable_local_APIC 1076f62bae50SIngo Molnar * for the case where Linux didn't enable the LAPIC. 1077f62bae50SIngo Molnar */ 1078f62bae50SIngo Molnar void lapic_shutdown(void) 1079f62bae50SIngo Molnar { 1080f62bae50SIngo Molnar unsigned long flags; 1081f62bae50SIngo Molnar 10828312136fSCyrill Gorcunov if (!cpu_has_apic && !apic_from_smp_config()) 1083f62bae50SIngo Molnar return; 1084f62bae50SIngo Molnar 1085f62bae50SIngo Molnar local_irq_save(flags); 1086f62bae50SIngo Molnar 1087f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1088f62bae50SIngo Molnar if (!enabled_via_apicbase) 1089f62bae50SIngo Molnar clear_local_APIC(); 1090f62bae50SIngo Molnar else 1091f62bae50SIngo Molnar #endif 1092f62bae50SIngo Molnar disable_local_APIC(); 1093f62bae50SIngo Molnar 1094f62bae50SIngo Molnar 1095f62bae50SIngo Molnar local_irq_restore(flags); 1096f62bae50SIngo Molnar } 1097f62bae50SIngo Molnar 1098f62bae50SIngo Molnar /** 1099f62bae50SIngo Molnar * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1100f62bae50SIngo Molnar */ 1101f62bae50SIngo Molnar void __init sync_Arb_IDs(void) 1102f62bae50SIngo Molnar { 1103f62bae50SIngo Molnar /* 1104f62bae50SIngo Molnar * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1105f62bae50SIngo Molnar * needed on AMD. 1106f62bae50SIngo Molnar */ 1107f62bae50SIngo Molnar if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1108f62bae50SIngo Molnar return; 1109f62bae50SIngo Molnar 1110f62bae50SIngo Molnar /* 1111f62bae50SIngo Molnar * Wait for idle. 1112f62bae50SIngo Molnar */ 1113f62bae50SIngo Molnar apic_wait_icr_idle(); 1114f62bae50SIngo Molnar 1115f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1116f62bae50SIngo Molnar apic_write(APIC_ICR, APIC_DEST_ALLINC | 1117f62bae50SIngo Molnar APIC_INT_LEVELTRIG | APIC_DM_INIT); 1118f62bae50SIngo Molnar } 1119f62bae50SIngo Molnar 1120f62bae50SIngo Molnar /* 1121f62bae50SIngo Molnar * An initial setup of the virtual wire mode. 1122f62bae50SIngo Molnar */ 1123f62bae50SIngo Molnar void __init init_bsp_APIC(void) 1124f62bae50SIngo Molnar { 1125f62bae50SIngo Molnar unsigned int value; 1126f62bae50SIngo Molnar 1127f62bae50SIngo Molnar /* 1128f62bae50SIngo Molnar * Don't do the setup now if we have a SMP BIOS as the 1129f62bae50SIngo Molnar * through-I/O-APIC virtual wire mode might be active. 1130f62bae50SIngo Molnar */ 1131f62bae50SIngo Molnar if (smp_found_config || !cpu_has_apic) 1132f62bae50SIngo Molnar return; 1133f62bae50SIngo Molnar 1134f62bae50SIngo Molnar /* 1135f62bae50SIngo Molnar * Do not trust the local APIC being empty at bootup. 1136f62bae50SIngo Molnar */ 1137f62bae50SIngo Molnar clear_local_APIC(); 1138f62bae50SIngo Molnar 1139f62bae50SIngo Molnar /* 1140f62bae50SIngo Molnar * Enable APIC. 1141f62bae50SIngo Molnar */ 1142f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 1143f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 1144f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 1145f62bae50SIngo Molnar 1146f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1147f62bae50SIngo Molnar /* This bit is reserved on P4/Xeon and should be cleared */ 1148f62bae50SIngo Molnar if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1149f62bae50SIngo Molnar (boot_cpu_data.x86 == 15)) 1150f62bae50SIngo Molnar value &= ~APIC_SPIV_FOCUS_DISABLED; 1151f62bae50SIngo Molnar else 1152f62bae50SIngo Molnar #endif 1153f62bae50SIngo Molnar value |= APIC_SPIV_FOCUS_DISABLED; 1154f62bae50SIngo Molnar value |= SPURIOUS_APIC_VECTOR; 1155f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 1156f62bae50SIngo Molnar 1157f62bae50SIngo Molnar /* 1158f62bae50SIngo Molnar * Set up the virtual wire mode. 1159f62bae50SIngo Molnar */ 1160f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_DM_EXTINT); 1161f62bae50SIngo Molnar value = APIC_DM_NMI; 1162f62bae50SIngo Molnar if (!lapic_is_integrated()) /* 82489DX */ 1163f62bae50SIngo Molnar value |= APIC_LVT_LEVEL_TRIGGER; 1164f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 1165f62bae50SIngo Molnar } 1166f62bae50SIngo Molnar 1167148f9bb8SPaul Gortmaker static void lapic_setup_esr(void) 1168f62bae50SIngo Molnar { 1169f62bae50SIngo Molnar unsigned int oldvalue, value, maxlvt; 1170f62bae50SIngo Molnar 1171f62bae50SIngo Molnar if (!lapic_is_integrated()) { 1172f62bae50SIngo Molnar pr_info("No ESR for 82489DX.\n"); 1173f62bae50SIngo Molnar return; 1174f62bae50SIngo Molnar } 1175f62bae50SIngo Molnar 1176f62bae50SIngo Molnar if (apic->disable_esr) { 1177f62bae50SIngo Molnar /* 1178f62bae50SIngo Molnar * Something untraceable is creating bad interrupts on 1179f62bae50SIngo Molnar * secondary quads ... for the moment, just leave the 1180f62bae50SIngo Molnar * ESR disabled - we can't do anything useful with the 1181f62bae50SIngo Molnar * errors anyway - mbligh 1182f62bae50SIngo Molnar */ 1183f62bae50SIngo Molnar pr_info("Leaving ESR disabled.\n"); 1184f62bae50SIngo Molnar return; 1185f62bae50SIngo Molnar } 1186f62bae50SIngo Molnar 1187f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 1188f62bae50SIngo Molnar if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1189f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1190f62bae50SIngo Molnar oldvalue = apic_read(APIC_ESR); 1191f62bae50SIngo Molnar 1192f62bae50SIngo Molnar /* enables sending errors */ 1193f62bae50SIngo Molnar value = ERROR_APIC_VECTOR; 1194f62bae50SIngo Molnar apic_write(APIC_LVTERR, value); 1195f62bae50SIngo Molnar 1196f62bae50SIngo Molnar /* 1197f62bae50SIngo Molnar * spec says clear errors after enabling vector. 1198f62bae50SIngo Molnar */ 1199f62bae50SIngo Molnar if (maxlvt > 3) 1200f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1201f62bae50SIngo Molnar value = apic_read(APIC_ESR); 1202f62bae50SIngo Molnar if (value != oldvalue) 1203f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "ESR value before enabling " 1204f62bae50SIngo Molnar "vector: 0x%08x after: 0x%08x\n", 1205f62bae50SIngo Molnar oldvalue, value); 1206f62bae50SIngo Molnar } 1207f62bae50SIngo Molnar 1208f62bae50SIngo Molnar /** 1209f62bae50SIngo Molnar * setup_local_APIC - setup the local APIC 12100aa002feSTejun Heo * 12110aa002feSTejun Heo * Used to setup local APIC while initializing BSP or bringin up APs. 12120aa002feSTejun Heo * Always called with preemption disabled. 1213f62bae50SIngo Molnar */ 1214148f9bb8SPaul Gortmaker void setup_local_APIC(void) 1215f62bae50SIngo Molnar { 12160aa002feSTejun Heo int cpu = smp_processor_id(); 12178c3ba8d0SKerstin Jonsson unsigned int value, queued; 12188c3ba8d0SKerstin Jonsson int i, j, acked = 0; 12198c3ba8d0SKerstin Jonsson unsigned long long tsc = 0, ntsc; 1220b47dcbdcSAndy Lutomirski long long max_loops = cpu_khz ? cpu_khz : 1000000; 12218c3ba8d0SKerstin Jonsson 12228c3ba8d0SKerstin Jonsson if (cpu_has_tsc) 12234ea1636bSAndy Lutomirski tsc = rdtsc(); 1224f62bae50SIngo Molnar 1225f62bae50SIngo Molnar if (disable_apic) { 12267167d08eSHenrik Kretzschmar disable_ioapic_support(); 1227f62bae50SIngo Molnar return; 1228f62bae50SIngo Molnar } 1229f62bae50SIngo Molnar 1230f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1231f62bae50SIngo Molnar /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1232f62bae50SIngo Molnar if (lapic_is_integrated() && apic->disable_esr) { 1233f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1234f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1235f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1236f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1237f62bae50SIngo Molnar } 1238f62bae50SIngo Molnar #endif 1239cdd6c482SIngo Molnar perf_events_lapic_init(); 1240f62bae50SIngo Molnar 1241f62bae50SIngo Molnar /* 1242f62bae50SIngo Molnar * Double-check whether this APIC is really registered. 1243f62bae50SIngo Molnar * This is meaningless in clustered apic mode, so we skip it. 1244f62bae50SIngo Molnar */ 1245c2777f98SDaniel Walker BUG_ON(!apic->apic_id_registered()); 1246f62bae50SIngo Molnar 1247f62bae50SIngo Molnar /* 1248f62bae50SIngo Molnar * Intel recommends to set DFR, LDR and TPR before enabling 1249f62bae50SIngo Molnar * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1250f62bae50SIngo Molnar * document number 292116). So here it goes... 1251f62bae50SIngo Molnar */ 1252f62bae50SIngo Molnar apic->init_apic_ldr(); 1253f62bae50SIngo Molnar 12546f802c4bSTejun Heo #ifdef CONFIG_X86_32 12556f802c4bSTejun Heo /* 1256acb8bc09STejun Heo * APIC LDR is initialized. If logical_apicid mapping was 1257acb8bc09STejun Heo * initialized during get_smp_config(), make sure it matches the 1258acb8bc09STejun Heo * actual value. 12596f802c4bSTejun Heo */ 1260acb8bc09STejun Heo i = early_per_cpu(x86_cpu_to_logical_apicid, cpu); 1261acb8bc09STejun Heo WARN_ON(i != BAD_APICID && i != logical_smp_processor_id()); 1262acb8bc09STejun Heo /* always use the value from LDR */ 12636f802c4bSTejun Heo early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 12646f802c4bSTejun Heo logical_smp_processor_id(); 12656f802c4bSTejun Heo #endif 12666f802c4bSTejun Heo 1267f62bae50SIngo Molnar /* 1268f62bae50SIngo Molnar * Set Task Priority to 'accept all'. We never change this 1269f62bae50SIngo Molnar * later on. 1270f62bae50SIngo Molnar */ 1271f62bae50SIngo Molnar value = apic_read(APIC_TASKPRI); 1272f62bae50SIngo Molnar value &= ~APIC_TPRI_MASK; 1273f62bae50SIngo Molnar apic_write(APIC_TASKPRI, value); 1274f62bae50SIngo Molnar 1275f62bae50SIngo Molnar /* 1276f62bae50SIngo Molnar * After a crash, we no longer service the interrupts and a pending 1277f62bae50SIngo Molnar * interrupt from previous kernel might still have ISR bit set. 1278f62bae50SIngo Molnar * 1279f62bae50SIngo Molnar * Most probably by now CPU has serviced that pending interrupt and 1280f62bae50SIngo Molnar * it might not have done the ack_APIC_irq() because it thought, 1281f62bae50SIngo Molnar * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1282f62bae50SIngo Molnar * does not clear the ISR bit and cpu thinks it has already serivced 1283f62bae50SIngo Molnar * the interrupt. Hence a vector might get locked. It was noticed 1284f62bae50SIngo Molnar * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1285f62bae50SIngo Molnar */ 12868c3ba8d0SKerstin Jonsson do { 12878c3ba8d0SKerstin Jonsson queued = 0; 12888c3ba8d0SKerstin Jonsson for (i = APIC_ISR_NR - 1; i >= 0; i--) 12898c3ba8d0SKerstin Jonsson queued |= apic_read(APIC_IRR + i*0x10); 12908c3ba8d0SKerstin Jonsson 1291f62bae50SIngo Molnar for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1292f62bae50SIngo Molnar value = apic_read(APIC_ISR + i*0x10); 1293f62bae50SIngo Molnar for (j = 31; j >= 0; j--) { 12948c3ba8d0SKerstin Jonsson if (value & (1<<j)) { 1295f62bae50SIngo Molnar ack_APIC_irq(); 12968c3ba8d0SKerstin Jonsson acked++; 1297f62bae50SIngo Molnar } 1298f62bae50SIngo Molnar } 12998c3ba8d0SKerstin Jonsson } 13008c3ba8d0SKerstin Jonsson if (acked > 256) { 13018c3ba8d0SKerstin Jonsson printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", 13028c3ba8d0SKerstin Jonsson acked); 13038c3ba8d0SKerstin Jonsson break; 13048c3ba8d0SKerstin Jonsson } 130542fa4250SShai Fultheim if (queued) { 1306b47dcbdcSAndy Lutomirski if (cpu_has_tsc && cpu_khz) { 13074ea1636bSAndy Lutomirski ntsc = rdtsc(); 13088c3ba8d0SKerstin Jonsson max_loops = (cpu_khz << 10) - (ntsc - tsc); 13098c3ba8d0SKerstin Jonsson } else 13108c3ba8d0SKerstin Jonsson max_loops--; 131142fa4250SShai Fultheim } 13128c3ba8d0SKerstin Jonsson } while (queued && max_loops > 0); 13138c3ba8d0SKerstin Jonsson WARN_ON(max_loops <= 0); 1314f62bae50SIngo Molnar 1315f62bae50SIngo Molnar /* 1316f62bae50SIngo Molnar * Now that we are all set up, enable the APIC 1317f62bae50SIngo Molnar */ 1318f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 1319f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 1320f62bae50SIngo Molnar /* 1321f62bae50SIngo Molnar * Enable APIC 1322f62bae50SIngo Molnar */ 1323f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 1324f62bae50SIngo Molnar 1325f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1326f62bae50SIngo Molnar /* 1327f62bae50SIngo Molnar * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1328f62bae50SIngo Molnar * certain networking cards. If high frequency interrupts are 1329f62bae50SIngo Molnar * happening on a particular IOAPIC pin, plus the IOAPIC routing 1330f62bae50SIngo Molnar * entry is masked/unmasked at a high rate as well then sooner or 1331f62bae50SIngo Molnar * later IOAPIC line gets 'stuck', no more interrupts are received 1332f62bae50SIngo Molnar * from the device. If focus CPU is disabled then the hang goes 1333f62bae50SIngo Molnar * away, oh well :-( 1334f62bae50SIngo Molnar * 1335f62bae50SIngo Molnar * [ This bug can be reproduced easily with a level-triggered 1336f62bae50SIngo Molnar * PCI Ne2000 networking cards and PII/PIII processors, dual 1337f62bae50SIngo Molnar * BX chipset. ] 1338f62bae50SIngo Molnar */ 1339f62bae50SIngo Molnar /* 1340f62bae50SIngo Molnar * Actually disabling the focus CPU check just makes the hang less 1341f62bae50SIngo Molnar * frequent as it makes the interrupt distributon model be more 1342f62bae50SIngo Molnar * like LRU than MRU (the short-term load is more even across CPUs). 1343f62bae50SIngo Molnar * See also the comment in end_level_ioapic_irq(). --macro 1344f62bae50SIngo Molnar */ 1345f62bae50SIngo Molnar 1346f62bae50SIngo Molnar /* 1347f62bae50SIngo Molnar * - enable focus processor (bit==0) 1348f62bae50SIngo Molnar * - 64bit mode always use processor focus 1349f62bae50SIngo Molnar * so no need to set it 1350f62bae50SIngo Molnar */ 1351f62bae50SIngo Molnar value &= ~APIC_SPIV_FOCUS_DISABLED; 1352f62bae50SIngo Molnar #endif 1353f62bae50SIngo Molnar 1354f62bae50SIngo Molnar /* 1355f62bae50SIngo Molnar * Set spurious IRQ vector 1356f62bae50SIngo Molnar */ 1357f62bae50SIngo Molnar value |= SPURIOUS_APIC_VECTOR; 1358f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 1359f62bae50SIngo Molnar 1360f62bae50SIngo Molnar /* 1361f62bae50SIngo Molnar * Set up LVT0, LVT1: 1362f62bae50SIngo Molnar * 1363f62bae50SIngo Molnar * set up through-local-APIC on the BP's LINT0. This is not 1364f62bae50SIngo Molnar * strictly necessary in pure symmetric-IO mode, but sometimes 1365f62bae50SIngo Molnar * we delegate interrupts to the 8259A. 1366f62bae50SIngo Molnar */ 1367f62bae50SIngo Molnar /* 1368f62bae50SIngo Molnar * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1369f62bae50SIngo Molnar */ 1370f62bae50SIngo Molnar value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 13710aa002feSTejun Heo if (!cpu && (pic_mode || !value)) { 1372f62bae50SIngo Molnar value = APIC_DM_EXTINT; 13730aa002feSTejun Heo apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1374f62bae50SIngo Molnar } else { 1375f62bae50SIngo Molnar value = APIC_DM_EXTINT | APIC_LVT_MASKED; 13760aa002feSTejun Heo apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1377f62bae50SIngo Molnar } 1378f62bae50SIngo Molnar apic_write(APIC_LVT0, value); 1379f62bae50SIngo Molnar 1380f62bae50SIngo Molnar /* 1381f62bae50SIngo Molnar * only the BP should see the LINT1 NMI signal, obviously. 1382f62bae50SIngo Molnar */ 13830aa002feSTejun Heo if (!cpu) 1384f62bae50SIngo Molnar value = APIC_DM_NMI; 1385f62bae50SIngo Molnar else 1386f62bae50SIngo Molnar value = APIC_DM_NMI | APIC_LVT_MASKED; 1387f62bae50SIngo Molnar if (!lapic_is_integrated()) /* 82489DX */ 1388f62bae50SIngo Molnar value |= APIC_LVT_LEVEL_TRIGGER; 1389f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 1390f62bae50SIngo Molnar 1391638bee71SH. Peter Anvin #ifdef CONFIG_X86_MCE_INTEL 1392638bee71SH. Peter Anvin /* Recheck CMCI information after local APIC is up on CPU #0 */ 13930aa002feSTejun Heo if (!cpu) 1394638bee71SH. Peter Anvin cmci_recheck(); 1395638bee71SH. Peter Anvin #endif 1396f62bae50SIngo Molnar } 1397f62bae50SIngo Molnar 139805f7e46dSThomas Gleixner static void end_local_APIC_setup(void) 1399f62bae50SIngo Molnar { 1400f62bae50SIngo Molnar lapic_setup_esr(); 1401f62bae50SIngo Molnar 1402f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1403f62bae50SIngo Molnar { 1404f62bae50SIngo Molnar unsigned int value; 1405f62bae50SIngo Molnar /* Disable the local apic timer */ 1406f62bae50SIngo Molnar value = apic_read(APIC_LVTT); 1407f62bae50SIngo Molnar value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1408f62bae50SIngo Molnar apic_write(APIC_LVTT, value); 1409f62bae50SIngo Molnar } 1410f62bae50SIngo Molnar #endif 1411f62bae50SIngo Molnar 1412f62bae50SIngo Molnar apic_pm_activate(); 14132fb270f3SJan Beulich } 14142fb270f3SJan Beulich 14157f7fbf45SKenji Kaneshige /* 141605f7e46dSThomas Gleixner * APIC setup function for application processors. Called from smpboot.c 14177f7fbf45SKenji Kaneshige */ 141805f7e46dSThomas Gleixner void apic_ap_setup(void) 141905f7e46dSThomas Gleixner { 142005f7e46dSThomas Gleixner setup_local_APIC(); 142105f7e46dSThomas Gleixner end_local_APIC_setup(); 1422f62bae50SIngo Molnar } 1423f62bae50SIngo Molnar 1424f62bae50SIngo Molnar #ifdef CONFIG_X86_X2APIC 1425bfb05070SThomas Gleixner int x2apic_mode; 142612e189d3SThomas Gleixner 142712e189d3SThomas Gleixner enum { 142812e189d3SThomas Gleixner X2APIC_OFF, 142912e189d3SThomas Gleixner X2APIC_ON, 143012e189d3SThomas Gleixner X2APIC_DISABLED, 143112e189d3SThomas Gleixner }; 143212e189d3SThomas Gleixner static int x2apic_state; 143312e189d3SThomas Gleixner 1434d786ad32SDenys Vlasenko static void __x2apic_disable(void) 143544e25ff9SThomas Gleixner { 143644e25ff9SThomas Gleixner u64 msr; 143744e25ff9SThomas Gleixner 1438a57e456aSThomas Gleixner if (!cpu_has_apic) 1439659006bfSThomas Gleixner return; 1440659006bfSThomas Gleixner 144144e25ff9SThomas Gleixner rdmsrl(MSR_IA32_APICBASE, msr); 144244e25ff9SThomas Gleixner if (!(msr & X2APIC_ENABLE)) 144344e25ff9SThomas Gleixner return; 144444e25ff9SThomas Gleixner /* Disable xapic and x2apic first and then reenable xapic mode */ 144544e25ff9SThomas Gleixner wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); 144644e25ff9SThomas Gleixner wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); 144744e25ff9SThomas Gleixner printk_once(KERN_INFO "x2apic disabled\n"); 144844e25ff9SThomas Gleixner } 144944e25ff9SThomas Gleixner 1450d786ad32SDenys Vlasenko static void __x2apic_enable(void) 1451659006bfSThomas Gleixner { 1452659006bfSThomas Gleixner u64 msr; 1453659006bfSThomas Gleixner 1454659006bfSThomas Gleixner rdmsrl(MSR_IA32_APICBASE, msr); 1455659006bfSThomas Gleixner if (msr & X2APIC_ENABLE) 1456659006bfSThomas Gleixner return; 1457659006bfSThomas Gleixner wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); 1458659006bfSThomas Gleixner printk_once(KERN_INFO "x2apic enabled\n"); 1459659006bfSThomas Gleixner } 1460659006bfSThomas Gleixner 1461bfb05070SThomas Gleixner static int __init setup_nox2apic(char *str) 1462bfb05070SThomas Gleixner { 1463bfb05070SThomas Gleixner if (x2apic_enabled()) { 1464bfb05070SThomas Gleixner int apicid = native_apic_msr_read(APIC_ID); 1465bfb05070SThomas Gleixner 1466bfb05070SThomas Gleixner if (apicid >= 255) { 1467bfb05070SThomas Gleixner pr_warning("Apicid: %08x, cannot enforce nox2apic\n", 1468bfb05070SThomas Gleixner apicid); 1469bfb05070SThomas Gleixner return 0; 1470bfb05070SThomas Gleixner } 147144e25ff9SThomas Gleixner pr_warning("x2apic already enabled.\n"); 147244e25ff9SThomas Gleixner __x2apic_disable(); 147344e25ff9SThomas Gleixner } 1474bfb05070SThomas Gleixner setup_clear_cpu_cap(X86_FEATURE_X2APIC); 147512e189d3SThomas Gleixner x2apic_state = X2APIC_DISABLED; 147644e25ff9SThomas Gleixner x2apic_mode = 0; 1477bfb05070SThomas Gleixner return 0; 1478bfb05070SThomas Gleixner } 1479bfb05070SThomas Gleixner early_param("nox2apic", setup_nox2apic); 1480bfb05070SThomas Gleixner 1481659006bfSThomas Gleixner /* Called from cpu_init() to enable x2apic on (secondary) cpus */ 1482659006bfSThomas Gleixner void x2apic_setup(void) 1483659006bfSThomas Gleixner { 1484659006bfSThomas Gleixner /* 1485659006bfSThomas Gleixner * If x2apic is not in ON state, disable it if already enabled 1486659006bfSThomas Gleixner * from BIOS. 1487659006bfSThomas Gleixner */ 1488659006bfSThomas Gleixner if (x2apic_state != X2APIC_ON) { 1489659006bfSThomas Gleixner __x2apic_disable(); 1490659006bfSThomas Gleixner return; 1491659006bfSThomas Gleixner } 1492659006bfSThomas Gleixner __x2apic_enable(); 1493659006bfSThomas Gleixner } 1494659006bfSThomas Gleixner 149544e25ff9SThomas Gleixner static __init void x2apic_disable(void) 1496fb209bd8SYinghai Lu { 1497a57e456aSThomas Gleixner u32 x2apic_id, state = x2apic_state; 1498fb209bd8SYinghai Lu 1499a57e456aSThomas Gleixner x2apic_mode = 0; 1500a57e456aSThomas Gleixner x2apic_state = X2APIC_DISABLED; 1501a57e456aSThomas Gleixner 1502a57e456aSThomas Gleixner if (state != X2APIC_ON) 1503a57e456aSThomas Gleixner return; 1504fb209bd8SYinghai Lu 15056d2d49d2SThomas Gleixner x2apic_id = read_apic_id(); 1506fb209bd8SYinghai Lu if (x2apic_id >= 255) 1507fb209bd8SYinghai Lu panic("Cannot disable x2apic, id: %08x\n", x2apic_id); 1508fb209bd8SYinghai Lu 150944e25ff9SThomas Gleixner __x2apic_disable(); 1510fb209bd8SYinghai Lu register_lapic_address(mp_lapic_addr); 1511fb209bd8SYinghai Lu } 1512fb209bd8SYinghai Lu 1513659006bfSThomas Gleixner static __init void x2apic_enable(void) 1514f62bae50SIngo Molnar { 1515659006bfSThomas Gleixner if (x2apic_state != X2APIC_OFF) 1516f62bae50SIngo Molnar return; 1517f62bae50SIngo Molnar 1518659006bfSThomas Gleixner x2apic_mode = 1; 151912e189d3SThomas Gleixner x2apic_state = X2APIC_ON; 1520659006bfSThomas Gleixner __x2apic_enable(); 1521f62bae50SIngo Molnar } 1522d524165cSThomas Gleixner 152362e61633SThomas Gleixner static __init void try_to_enable_x2apic(int remap_mode) 152407806c50SJiang Liu { 1525659006bfSThomas Gleixner if (x2apic_state == X2APIC_DISABLED) 152607806c50SJiang Liu return; 152707806c50SJiang Liu 152862e61633SThomas Gleixner if (remap_mode != IRQ_REMAP_X2APIC_MODE) { 152907806c50SJiang Liu /* IR is required if there is APIC ID > 255 even when running 153007806c50SJiang Liu * under KVM 153107806c50SJiang Liu */ 153207806c50SJiang Liu if (max_physical_apicid > 255 || 15338329aa9fSLinus Torvalds !hypervisor_x2apic_available()) { 153462e61633SThomas Gleixner pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); 153544e25ff9SThomas Gleixner x2apic_disable(); 153607806c50SJiang Liu return; 153707806c50SJiang Liu } 153807806c50SJiang Liu 153907806c50SJiang Liu /* 154007806c50SJiang Liu * without IR all CPUs can be addressed by IOAPIC/MSI 154107806c50SJiang Liu * only in physical mode 154207806c50SJiang Liu */ 154355eae7deSThomas Gleixner x2apic_phys = 1; 154407806c50SJiang Liu } 1545659006bfSThomas Gleixner x2apic_enable(); 154655eae7deSThomas Gleixner } 154755eae7deSThomas Gleixner 154855eae7deSThomas Gleixner void __init check_x2apic(void) 154955eae7deSThomas Gleixner { 155055eae7deSThomas Gleixner if (x2apic_enabled()) { 155155eae7deSThomas Gleixner pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); 155255eae7deSThomas Gleixner x2apic_mode = 1; 155312e189d3SThomas Gleixner x2apic_state = X2APIC_ON; 155412e189d3SThomas Gleixner } else if (!cpu_has_x2apic) { 155512e189d3SThomas Gleixner x2apic_state = X2APIC_DISABLED; 155655eae7deSThomas Gleixner } 155755eae7deSThomas Gleixner } 155855eae7deSThomas Gleixner #else /* CONFIG_X86_X2APIC */ 155955eae7deSThomas Gleixner static int __init validate_x2apic(void) 156055eae7deSThomas Gleixner { 156155eae7deSThomas Gleixner if (!apic_is_x2apic_enabled()) 156255eae7deSThomas Gleixner return 0; 156355eae7deSThomas Gleixner /* 156455eae7deSThomas Gleixner * Checkme: Can we simply turn off x2apic here instead of panic? 156555eae7deSThomas Gleixner */ 156655eae7deSThomas Gleixner panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n"); 156755eae7deSThomas Gleixner } 156855eae7deSThomas Gleixner early_initcall(validate_x2apic); 156955eae7deSThomas Gleixner 157062e61633SThomas Gleixner static inline void try_to_enable_x2apic(int remap_mode) { } 1571659006bfSThomas Gleixner static inline void __x2apic_enable(void) { } 157255eae7deSThomas Gleixner #endif /* !CONFIG_X86_X2APIC */ 157355eae7deSThomas Gleixner 157455eae7deSThomas Gleixner static int __init try_to_enable_IR(void) 157555eae7deSThomas Gleixner { 157655eae7deSThomas Gleixner #ifdef CONFIG_X86_IO_APIC 157755eae7deSThomas Gleixner if (!x2apic_enabled() && skip_ioapic_setup) { 157855eae7deSThomas Gleixner pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); 157955eae7deSThomas Gleixner return -1; 158055eae7deSThomas Gleixner } 158107806c50SJiang Liu #endif 158255eae7deSThomas Gleixner return irq_remapping_enable(); 1583ce69a784SGleb Natapov } 1584ce69a784SGleb Natapov 1585ce69a784SGleb Natapov void __init enable_IR_x2apic(void) 1586ce69a784SGleb Natapov { 1587ce69a784SGleb Natapov unsigned long flags; 158807806c50SJiang Liu int ret, ir_stat; 1589b7f42ab2SYinghai Lu 159007806c50SJiang Liu ir_stat = irq_remapping_prepare(); 159107806c50SJiang Liu if (ir_stat < 0 && !x2apic_supported()) 1592e670761fSYinghai Lu return; 1593ce69a784SGleb Natapov 159431dce14aSSuresh Siddha ret = save_ioapic_entries(); 1595f62bae50SIngo Molnar if (ret) { 1596f62bae50SIngo Molnar pr_info("Saving IO-APIC state failed: %d\n", ret); 1597fb209bd8SYinghai Lu return; 1598f62bae50SIngo Molnar } 1599f62bae50SIngo Molnar 160005c3dc2cSSuresh Siddha local_irq_save(flags); 1601b81bb373SJacob Pan legacy_pic->mask_all(); 160231dce14aSSuresh Siddha mask_ioapic_entries(); 160305c3dc2cSSuresh Siddha 160407806c50SJiang Liu /* If irq_remapping_prepare() succeded, try to enable it */ 160507806c50SJiang Liu if (ir_stat >= 0) 160607806c50SJiang Liu ir_stat = try_to_enable_IR(); 160707806c50SJiang Liu /* ir_stat contains the remap mode or an error code */ 160807806c50SJiang Liu try_to_enable_x2apic(ir_stat); 1609a31bc327SYinghai Lu 161007806c50SJiang Liu if (ir_stat < 0) 161131dce14aSSuresh Siddha restore_ioapic_entries(); 1612b81bb373SJacob Pan legacy_pic->restore_mask(); 1613f62bae50SIngo Molnar local_irq_restore(flags); 1614f62bae50SIngo Molnar } 161593758238SWeidong Han 1616f62bae50SIngo Molnar #ifdef CONFIG_X86_64 1617f62bae50SIngo Molnar /* 1618f62bae50SIngo Molnar * Detect and enable local APICs on non-SMP boards. 1619f62bae50SIngo Molnar * Original code written by Keir Fraser. 1620f62bae50SIngo Molnar * On AMD64 we trust the BIOS - if it says no APIC it is likely 1621f62bae50SIngo Molnar * not correctly set up (usually the APIC timer won't work etc.) 1622f62bae50SIngo Molnar */ 1623f62bae50SIngo Molnar static int __init detect_init_APIC(void) 1624f62bae50SIngo Molnar { 1625f62bae50SIngo Molnar if (!cpu_has_apic) { 1626f62bae50SIngo Molnar pr_info("No local APIC present\n"); 1627f62bae50SIngo Molnar return -1; 1628f62bae50SIngo Molnar } 1629f62bae50SIngo Molnar 1630f62bae50SIngo Molnar mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1631f62bae50SIngo Molnar return 0; 1632f62bae50SIngo Molnar } 1633f62bae50SIngo Molnar #else 16345a7ae78fSThomas Gleixner 163525874a29SHenrik Kretzschmar static int __init apic_verify(void) 16365a7ae78fSThomas Gleixner { 16375a7ae78fSThomas Gleixner u32 features, h, l; 16385a7ae78fSThomas Gleixner 16395a7ae78fSThomas Gleixner /* 16405a7ae78fSThomas Gleixner * The APIC feature bit should now be enabled 16415a7ae78fSThomas Gleixner * in `cpuid' 16425a7ae78fSThomas Gleixner */ 16435a7ae78fSThomas Gleixner features = cpuid_edx(1); 16445a7ae78fSThomas Gleixner if (!(features & (1 << X86_FEATURE_APIC))) { 16455a7ae78fSThomas Gleixner pr_warning("Could not enable APIC!\n"); 16465a7ae78fSThomas Gleixner return -1; 16475a7ae78fSThomas Gleixner } 16485a7ae78fSThomas Gleixner set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 16495a7ae78fSThomas Gleixner mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 16505a7ae78fSThomas Gleixner 16515a7ae78fSThomas Gleixner /* The BIOS may have set up the APIC at some other address */ 1652cbf2829bSBryan O'Donoghue if (boot_cpu_data.x86 >= 6) { 16535a7ae78fSThomas Gleixner rdmsr(MSR_IA32_APICBASE, l, h); 16545a7ae78fSThomas Gleixner if (l & MSR_IA32_APICBASE_ENABLE) 16555a7ae78fSThomas Gleixner mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1656cbf2829bSBryan O'Donoghue } 16575a7ae78fSThomas Gleixner 16585a7ae78fSThomas Gleixner pr_info("Found and enabled local APIC!\n"); 16595a7ae78fSThomas Gleixner return 0; 16605a7ae78fSThomas Gleixner } 16615a7ae78fSThomas Gleixner 166225874a29SHenrik Kretzschmar int __init apic_force_enable(unsigned long addr) 16635a7ae78fSThomas Gleixner { 16645a7ae78fSThomas Gleixner u32 h, l; 16655a7ae78fSThomas Gleixner 16665a7ae78fSThomas Gleixner if (disable_apic) 16675a7ae78fSThomas Gleixner return -1; 16685a7ae78fSThomas Gleixner 16695a7ae78fSThomas Gleixner /* 16705a7ae78fSThomas Gleixner * Some BIOSes disable the local APIC in the APIC_BASE 16715a7ae78fSThomas Gleixner * MSR. This can only be done in software for Intel P6 or later 16725a7ae78fSThomas Gleixner * and AMD K7 (Model > 1) or later. 16735a7ae78fSThomas Gleixner */ 1674cbf2829bSBryan O'Donoghue if (boot_cpu_data.x86 >= 6) { 16755a7ae78fSThomas Gleixner rdmsr(MSR_IA32_APICBASE, l, h); 16765a7ae78fSThomas Gleixner if (!(l & MSR_IA32_APICBASE_ENABLE)) { 16775a7ae78fSThomas Gleixner pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 16785a7ae78fSThomas Gleixner l &= ~MSR_IA32_APICBASE_BASE; 1679a906fdaaSThomas Gleixner l |= MSR_IA32_APICBASE_ENABLE | addr; 16805a7ae78fSThomas Gleixner wrmsr(MSR_IA32_APICBASE, l, h); 16815a7ae78fSThomas Gleixner enabled_via_apicbase = 1; 16825a7ae78fSThomas Gleixner } 1683cbf2829bSBryan O'Donoghue } 16845a7ae78fSThomas Gleixner return apic_verify(); 16855a7ae78fSThomas Gleixner } 16865a7ae78fSThomas Gleixner 1687f62bae50SIngo Molnar /* 1688f62bae50SIngo Molnar * Detect and initialize APIC 1689f62bae50SIngo Molnar */ 1690f62bae50SIngo Molnar static int __init detect_init_APIC(void) 1691f62bae50SIngo Molnar { 1692f62bae50SIngo Molnar /* Disabled by kernel option? */ 1693f62bae50SIngo Molnar if (disable_apic) 1694f62bae50SIngo Molnar return -1; 1695f62bae50SIngo Molnar 1696f62bae50SIngo Molnar switch (boot_cpu_data.x86_vendor) { 1697f62bae50SIngo Molnar case X86_VENDOR_AMD: 1698f62bae50SIngo Molnar if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1699f62bae50SIngo Molnar (boot_cpu_data.x86 >= 15)) 1700f62bae50SIngo Molnar break; 1701f62bae50SIngo Molnar goto no_apic; 1702f62bae50SIngo Molnar case X86_VENDOR_INTEL: 1703f62bae50SIngo Molnar if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1704f62bae50SIngo Molnar (boot_cpu_data.x86 == 5 && cpu_has_apic)) 1705f62bae50SIngo Molnar break; 1706f62bae50SIngo Molnar goto no_apic; 1707f62bae50SIngo Molnar default: 1708f62bae50SIngo Molnar goto no_apic; 1709f62bae50SIngo Molnar } 1710f62bae50SIngo Molnar 1711f62bae50SIngo Molnar if (!cpu_has_apic) { 1712f62bae50SIngo Molnar /* 1713f62bae50SIngo Molnar * Over-ride BIOS and try to enable the local APIC only if 1714f62bae50SIngo Molnar * "lapic" specified. 1715f62bae50SIngo Molnar */ 1716f62bae50SIngo Molnar if (!force_enable_local_apic) { 1717f62bae50SIngo Molnar pr_info("Local APIC disabled by BIOS -- " 1718f62bae50SIngo Molnar "you can enable it with \"lapic\"\n"); 1719f62bae50SIngo Molnar return -1; 1720f62bae50SIngo Molnar } 1721a906fdaaSThomas Gleixner if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) 17225a7ae78fSThomas Gleixner return -1; 17235a7ae78fSThomas Gleixner } else { 17245a7ae78fSThomas Gleixner if (apic_verify()) 1725f62bae50SIngo Molnar return -1; 1726f62bae50SIngo Molnar } 1727f62bae50SIngo Molnar 1728f62bae50SIngo Molnar apic_pm_activate(); 1729f62bae50SIngo Molnar 1730f62bae50SIngo Molnar return 0; 1731f62bae50SIngo Molnar 1732f62bae50SIngo Molnar no_apic: 1733f62bae50SIngo Molnar pr_info("No local APIC present or hardware disabled\n"); 1734f62bae50SIngo Molnar return -1; 1735f62bae50SIngo Molnar } 1736f62bae50SIngo Molnar #endif 1737f62bae50SIngo Molnar 1738f62bae50SIngo Molnar /** 1739f62bae50SIngo Molnar * init_apic_mappings - initialize APIC mappings 1740f62bae50SIngo Molnar */ 1741f62bae50SIngo Molnar void __init init_apic_mappings(void) 1742f62bae50SIngo Molnar { 17434401da61SYinghai Lu unsigned int new_apicid; 17444401da61SYinghai Lu 1745fc1edaf9SSuresh Siddha if (x2apic_mode) { 1746f62bae50SIngo Molnar boot_cpu_physical_apicid = read_apic_id(); 1747f62bae50SIngo Molnar return; 1748f62bae50SIngo Molnar } 1749f62bae50SIngo Molnar 17504797f6b0SYinghai Lu /* If no local APIC can be found return early */ 1751f62bae50SIngo Molnar if (!smp_found_config && detect_init_APIC()) { 17524797f6b0SYinghai Lu /* lets NOP'ify apic operations */ 17534797f6b0SYinghai Lu pr_info("APIC: disable apic facility\n"); 17544797f6b0SYinghai Lu apic_disable(); 17554797f6b0SYinghai Lu } else { 1756f62bae50SIngo Molnar apic_phys = mp_lapic_addr; 1757f62bae50SIngo Molnar 17584401da61SYinghai Lu /* 17594401da61SYinghai Lu * acpi lapic path already maps that address in 17604401da61SYinghai Lu * acpi_register_lapic_address() 17614401da61SYinghai Lu */ 17625989cd6aSEric W. Biederman if (!acpi_lapic && !smp_found_config) 1763326a2e6bSYinghai Lu register_lapic_address(apic_phys); 1764cec6be6dSCyrill Gorcunov } 1765f62bae50SIngo Molnar 1766f62bae50SIngo Molnar /* 1767f62bae50SIngo Molnar * Fetch the APIC ID of the BSP in case we have a 1768f62bae50SIngo Molnar * default configuration (or the MP table is broken). 1769f62bae50SIngo Molnar */ 17704401da61SYinghai Lu new_apicid = read_apic_id(); 17714401da61SYinghai Lu if (boot_cpu_physical_apicid != new_apicid) { 17724401da61SYinghai Lu boot_cpu_physical_apicid = new_apicid; 1773103428e5SCyrill Gorcunov /* 1774103428e5SCyrill Gorcunov * yeah -- we lie about apic_version 1775103428e5SCyrill Gorcunov * in case if apic was disabled via boot option 1776103428e5SCyrill Gorcunov * but it's not a problem for SMP compiled kernel 1777103428e5SCyrill Gorcunov * since smp_sanity_check is prepared for such a case 1778103428e5SCyrill Gorcunov * and disable smp mode 1779103428e5SCyrill Gorcunov */ 17804401da61SYinghai Lu apic_version[new_apicid] = 17814401da61SYinghai Lu GET_APIC_VERSION(apic_read(APIC_LVR)); 178208306ce6SCyrill Gorcunov } 1783f62bae50SIngo Molnar } 1784f62bae50SIngo Molnar 1785c0104d38SYinghai Lu void __init register_lapic_address(unsigned long address) 1786c0104d38SYinghai Lu { 1787c0104d38SYinghai Lu mp_lapic_addr = address; 1788c0104d38SYinghai Lu 17890450193bSYinghai Lu if (!x2apic_mode) { 1790c0104d38SYinghai Lu set_fixmap_nocache(FIX_APIC_BASE, address); 1791f1157141SYinghai Lu apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 1792f1157141SYinghai Lu APIC_BASE, mp_lapic_addr); 17930450193bSYinghai Lu } 1794c0104d38SYinghai Lu if (boot_cpu_physical_apicid == -1U) { 1795c0104d38SYinghai Lu boot_cpu_physical_apicid = read_apic_id(); 1796c0104d38SYinghai Lu apic_version[boot_cpu_physical_apicid] = 1797c0104d38SYinghai Lu GET_APIC_VERSION(apic_read(APIC_LVR)); 1798c0104d38SYinghai Lu } 1799c0104d38SYinghai Lu } 1800c0104d38SYinghai Lu 180156d91f13SYinghai Lu int apic_version[MAX_LOCAL_APIC]; 1802f62bae50SIngo Molnar 1803f62bae50SIngo Molnar /* 1804f62bae50SIngo Molnar * Local APIC interrupts 1805f62bae50SIngo Molnar */ 1806f62bae50SIngo Molnar 1807f62bae50SIngo Molnar /* 1808f62bae50SIngo Molnar * This interrupt should _never_ happen with our APIC/SMP architecture 1809f62bae50SIngo Molnar */ 1810d786ad32SDenys Vlasenko static void __smp_spurious_interrupt(u8 vector) 1811f62bae50SIngo Molnar { 1812f62bae50SIngo Molnar u32 v; 1813f62bae50SIngo Molnar 1814f62bae50SIngo Molnar /* 1815f62bae50SIngo Molnar * Check if this really is a spurious interrupt and ACK it 1816f62bae50SIngo Molnar * if it is a vectored one. Just in case... 1817f62bae50SIngo Molnar * Spurious interrupts should not be ACKed. 1818f62bae50SIngo Molnar */ 18192414e021SJan Beulich v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); 18202414e021SJan Beulich if (v & (1 << (vector & 0x1f))) 1821f62bae50SIngo Molnar ack_APIC_irq(); 1822f62bae50SIngo Molnar 1823f62bae50SIngo Molnar inc_irq_stat(irq_spurious_count); 1824f62bae50SIngo Molnar 1825f62bae50SIngo Molnar /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 18262414e021SJan Beulich pr_info("spurious APIC interrupt through vector %02x on CPU#%d, " 18272414e021SJan Beulich "should never happen.\n", vector, smp_processor_id()); 1828eddc0e92SSeiji Aguchi } 1829eddc0e92SSeiji Aguchi 18301d9090e2SAndi Kleen __visible void smp_spurious_interrupt(struct pt_regs *regs) 1831eddc0e92SSeiji Aguchi { 1832eddc0e92SSeiji Aguchi entering_irq(); 18332414e021SJan Beulich __smp_spurious_interrupt(~regs->orig_ax); 1834eddc0e92SSeiji Aguchi exiting_irq(); 1835f62bae50SIngo Molnar } 1836f62bae50SIngo Molnar 18371d9090e2SAndi Kleen __visible void smp_trace_spurious_interrupt(struct pt_regs *regs) 1838cf910e83SSeiji Aguchi { 18392414e021SJan Beulich u8 vector = ~regs->orig_ax; 18402414e021SJan Beulich 1841cf910e83SSeiji Aguchi entering_irq(); 18422414e021SJan Beulich trace_spurious_apic_entry(vector); 18432414e021SJan Beulich __smp_spurious_interrupt(vector); 18442414e021SJan Beulich trace_spurious_apic_exit(vector); 1845cf910e83SSeiji Aguchi exiting_irq(); 1846f62bae50SIngo Molnar } 1847f62bae50SIngo Molnar 1848f62bae50SIngo Molnar /* 1849f62bae50SIngo Molnar * This interrupt should never happen with our APIC/SMP architecture 1850f62bae50SIngo Molnar */ 1851d786ad32SDenys Vlasenko static void __smp_error_interrupt(struct pt_regs *regs) 1852f62bae50SIngo Molnar { 185360283df7SRichard Weinberger u32 v; 18542b398bd9SYouquan Song u32 i = 0; 18552b398bd9SYouquan Song static const char * const error_interrupt_reason[] = { 18562b398bd9SYouquan Song "Send CS error", /* APIC Error Bit 0 */ 18572b398bd9SYouquan Song "Receive CS error", /* APIC Error Bit 1 */ 18582b398bd9SYouquan Song "Send accept error", /* APIC Error Bit 2 */ 18592b398bd9SYouquan Song "Receive accept error", /* APIC Error Bit 3 */ 18602b398bd9SYouquan Song "Redirectable IPI", /* APIC Error Bit 4 */ 18612b398bd9SYouquan Song "Send illegal vector", /* APIC Error Bit 5 */ 18622b398bd9SYouquan Song "Received illegal vector", /* APIC Error Bit 6 */ 18632b398bd9SYouquan Song "Illegal register address", /* APIC Error Bit 7 */ 18642b398bd9SYouquan Song }; 1865f62bae50SIngo Molnar 1866f62bae50SIngo Molnar /* First tickle the hardware, only then report what went on. -- REW */ 1867023de4a0SMaciej W. Rozycki if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ 1868f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 186960283df7SRichard Weinberger v = apic_read(APIC_ESR); 1870f62bae50SIngo Molnar ack_APIC_irq(); 1871f62bae50SIngo Molnar atomic_inc(&irq_err_count); 1872f62bae50SIngo Molnar 187360283df7SRichard Weinberger apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", 187460283df7SRichard Weinberger smp_processor_id(), v); 18752b398bd9SYouquan Song 187660283df7SRichard Weinberger v &= 0xff; 187760283df7SRichard Weinberger while (v) { 187860283df7SRichard Weinberger if (v & 0x1) 18792b398bd9SYouquan Song apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); 18802b398bd9SYouquan Song i++; 188160283df7SRichard Weinberger v >>= 1; 18824b8073e4SPeter Senna Tschudin } 18832b398bd9SYouquan Song 18842b398bd9SYouquan Song apic_printk(APIC_DEBUG, KERN_CONT "\n"); 18852b398bd9SYouquan Song 1886eddc0e92SSeiji Aguchi } 1887eddc0e92SSeiji Aguchi 18881d9090e2SAndi Kleen __visible void smp_error_interrupt(struct pt_regs *regs) 1889eddc0e92SSeiji Aguchi { 1890eddc0e92SSeiji Aguchi entering_irq(); 1891eddc0e92SSeiji Aguchi __smp_error_interrupt(regs); 1892eddc0e92SSeiji Aguchi exiting_irq(); 1893f62bae50SIngo Molnar } 1894f62bae50SIngo Molnar 18951d9090e2SAndi Kleen __visible void smp_trace_error_interrupt(struct pt_regs *regs) 1896cf910e83SSeiji Aguchi { 1897cf910e83SSeiji Aguchi entering_irq(); 1898cf910e83SSeiji Aguchi trace_error_apic_entry(ERROR_APIC_VECTOR); 1899cf910e83SSeiji Aguchi __smp_error_interrupt(regs); 1900cf910e83SSeiji Aguchi trace_error_apic_exit(ERROR_APIC_VECTOR); 1901cf910e83SSeiji Aguchi exiting_irq(); 1902f62bae50SIngo Molnar } 1903f62bae50SIngo Molnar 1904f62bae50SIngo Molnar /** 1905f62bae50SIngo Molnar * connect_bsp_APIC - attach the APIC to the interrupt system 1906f62bae50SIngo Molnar */ 190705f7e46dSThomas Gleixner static void __init connect_bsp_APIC(void) 1908f62bae50SIngo Molnar { 1909f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1910f62bae50SIngo Molnar if (pic_mode) { 1911f62bae50SIngo Molnar /* 1912f62bae50SIngo Molnar * Do not trust the local APIC being empty at bootup. 1913f62bae50SIngo Molnar */ 1914f62bae50SIngo Molnar clear_local_APIC(); 1915f62bae50SIngo Molnar /* 1916f62bae50SIngo Molnar * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 1917f62bae50SIngo Molnar * local APIC to INT and NMI lines. 1918f62bae50SIngo Molnar */ 1919f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "leaving PIC mode, " 1920f62bae50SIngo Molnar "enabling APIC mode.\n"); 1921c0eaa453SCyrill Gorcunov imcr_pic_to_apic(); 1922f62bae50SIngo Molnar } 1923f62bae50SIngo Molnar #endif 1924f62bae50SIngo Molnar } 1925f62bae50SIngo Molnar 1926f62bae50SIngo Molnar /** 1927f62bae50SIngo Molnar * disconnect_bsp_APIC - detach the APIC from the interrupt system 1928f62bae50SIngo Molnar * @virt_wire_setup: indicates, whether virtual wire mode is selected 1929f62bae50SIngo Molnar * 1930f62bae50SIngo Molnar * Virtual wire mode is necessary to deliver legacy interrupts even when the 1931f62bae50SIngo Molnar * APIC is disabled. 1932f62bae50SIngo Molnar */ 1933f62bae50SIngo Molnar void disconnect_bsp_APIC(int virt_wire_setup) 1934f62bae50SIngo Molnar { 1935f62bae50SIngo Molnar unsigned int value; 1936f62bae50SIngo Molnar 1937f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1938f62bae50SIngo Molnar if (pic_mode) { 1939f62bae50SIngo Molnar /* 1940f62bae50SIngo Molnar * Put the board back into PIC mode (has an effect only on 1941f62bae50SIngo Molnar * certain older boards). Note that APIC interrupts, including 1942f62bae50SIngo Molnar * IPIs, won't work beyond this point! The only exception are 1943f62bae50SIngo Molnar * INIT IPIs. 1944f62bae50SIngo Molnar */ 1945f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "disabling APIC mode, " 1946f62bae50SIngo Molnar "entering PIC mode.\n"); 1947c0eaa453SCyrill Gorcunov imcr_apic_to_pic(); 1948f62bae50SIngo Molnar return; 1949f62bae50SIngo Molnar } 1950f62bae50SIngo Molnar #endif 1951f62bae50SIngo Molnar 1952f62bae50SIngo Molnar /* Go back to Virtual Wire compatibility mode */ 1953f62bae50SIngo Molnar 1954f62bae50SIngo Molnar /* For the spurious interrupt use vector F, and enable it */ 1955f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 1956f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 1957f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 1958f62bae50SIngo Molnar value |= 0xf; 1959f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 1960f62bae50SIngo Molnar 1961f62bae50SIngo Molnar if (!virt_wire_setup) { 1962f62bae50SIngo Molnar /* 1963f62bae50SIngo Molnar * For LVT0 make it edge triggered, active high, 1964f62bae50SIngo Molnar * external and enabled 1965f62bae50SIngo Molnar */ 1966f62bae50SIngo Molnar value = apic_read(APIC_LVT0); 1967f62bae50SIngo Molnar value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1968f62bae50SIngo Molnar APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1969f62bae50SIngo Molnar APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1970f62bae50SIngo Molnar value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1971f62bae50SIngo Molnar value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 1972f62bae50SIngo Molnar apic_write(APIC_LVT0, value); 1973f62bae50SIngo Molnar } else { 1974f62bae50SIngo Molnar /* Disable LVT0 */ 1975f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_LVT_MASKED); 1976f62bae50SIngo Molnar } 1977f62bae50SIngo Molnar 1978f62bae50SIngo Molnar /* 1979f62bae50SIngo Molnar * For LVT1 make it edge triggered, active high, 1980f62bae50SIngo Molnar * nmi and enabled 1981f62bae50SIngo Molnar */ 1982f62bae50SIngo Molnar value = apic_read(APIC_LVT1); 1983f62bae50SIngo Molnar value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1984f62bae50SIngo Molnar APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1985f62bae50SIngo Molnar APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1986f62bae50SIngo Molnar value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1987f62bae50SIngo Molnar value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 1988f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 1989f62bae50SIngo Molnar } 1990f62bae50SIngo Molnar 19917e1f85f9SJiang Liu int generic_processor_info(int apicid, int version) 1992f62bae50SIngo Molnar { 199314cb6dcfSVivek Goyal int cpu, max = nr_cpu_ids; 199414cb6dcfSVivek Goyal bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, 199514cb6dcfSVivek Goyal phys_cpu_present_map); 199614cb6dcfSVivek Goyal 199714cb6dcfSVivek Goyal /* 1998151e0c7dSHATAYAMA Daisuke * boot_cpu_physical_apicid is designed to have the apicid 1999151e0c7dSHATAYAMA Daisuke * returned by read_apic_id(), i.e, the apicid of the 2000151e0c7dSHATAYAMA Daisuke * currently booting-up processor. However, on some platforms, 20015b4d1dbcSH. Peter Anvin * it is temporarily modified by the apicid reported as BSP 2002151e0c7dSHATAYAMA Daisuke * through MP table. Concretely: 2003151e0c7dSHATAYAMA Daisuke * 2004151e0c7dSHATAYAMA Daisuke * - arch/x86/kernel/mpparse.c: MP_processor_info() 2005151e0c7dSHATAYAMA Daisuke * - arch/x86/mm/amdtopology.c: amd_numa_init() 2006151e0c7dSHATAYAMA Daisuke * 2007151e0c7dSHATAYAMA Daisuke * This function is executed with the modified 2008151e0c7dSHATAYAMA Daisuke * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel 2009151e0c7dSHATAYAMA Daisuke * parameter doesn't work to disable APs on kdump 2nd kernel. 2010151e0c7dSHATAYAMA Daisuke * 2011151e0c7dSHATAYAMA Daisuke * Since fixing handling of boot_cpu_physical_apicid requires 2012151e0c7dSHATAYAMA Daisuke * another discussion and tests on each platform, we leave it 2013151e0c7dSHATAYAMA Daisuke * for now and here we use read_apic_id() directly in this 2014151e0c7dSHATAYAMA Daisuke * function, generic_processor_info(). 2015151e0c7dSHATAYAMA Daisuke */ 2016151e0c7dSHATAYAMA Daisuke if (disabled_cpu_apicid != BAD_APICID && 2017151e0c7dSHATAYAMA Daisuke disabled_cpu_apicid != read_apic_id() && 2018151e0c7dSHATAYAMA Daisuke disabled_cpu_apicid == apicid) { 2019151e0c7dSHATAYAMA Daisuke int thiscpu = num_processors + disabled_cpus; 2020151e0c7dSHATAYAMA Daisuke 20215b4d1dbcSH. Peter Anvin pr_warning("APIC: Disabling requested cpu." 2022151e0c7dSHATAYAMA Daisuke " Processor %d/0x%x ignored.\n", 2023151e0c7dSHATAYAMA Daisuke thiscpu, apicid); 2024151e0c7dSHATAYAMA Daisuke 2025151e0c7dSHATAYAMA Daisuke disabled_cpus++; 2026151e0c7dSHATAYAMA Daisuke return -ENODEV; 2027151e0c7dSHATAYAMA Daisuke } 2028151e0c7dSHATAYAMA Daisuke 2029151e0c7dSHATAYAMA Daisuke /* 203014cb6dcfSVivek Goyal * If boot cpu has not been detected yet, then only allow upto 203114cb6dcfSVivek Goyal * nr_cpu_ids - 1 processors and keep one slot free for boot cpu 203214cb6dcfSVivek Goyal */ 203314cb6dcfSVivek Goyal if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && 203414cb6dcfSVivek Goyal apicid != boot_cpu_physical_apicid) { 203514cb6dcfSVivek Goyal int thiscpu = max + disabled_cpus - 1; 203614cb6dcfSVivek Goyal 203714cb6dcfSVivek Goyal pr_warning( 203814cb6dcfSVivek Goyal "ACPI: NR_CPUS/possible_cpus limit of %i almost" 203914cb6dcfSVivek Goyal " reached. Keeping one slot for boot cpu." 204014cb6dcfSVivek Goyal " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 204114cb6dcfSVivek Goyal 204214cb6dcfSVivek Goyal disabled_cpus++; 20437e1f85f9SJiang Liu return -ENODEV; 204414cb6dcfSVivek Goyal } 2045f62bae50SIngo Molnar 2046f62bae50SIngo Molnar if (num_processors >= nr_cpu_ids) { 2047f62bae50SIngo Molnar int thiscpu = max + disabled_cpus; 2048f62bae50SIngo Molnar 2049f62bae50SIngo Molnar pr_warning( 2050f62bae50SIngo Molnar "ACPI: NR_CPUS/possible_cpus limit of %i reached." 2051f62bae50SIngo Molnar " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2052f62bae50SIngo Molnar 2053f62bae50SIngo Molnar disabled_cpus++; 20547e1f85f9SJiang Liu return -EINVAL; 2055f62bae50SIngo Molnar } 2056f62bae50SIngo Molnar 2057f62bae50SIngo Molnar num_processors++; 2058f62bae50SIngo Molnar if (apicid == boot_cpu_physical_apicid) { 2059f62bae50SIngo Molnar /* 2060f62bae50SIngo Molnar * x86_bios_cpu_apicid is required to have processors listed 2061f62bae50SIngo Molnar * in same order as logical cpu numbers. Hence the first 2062f62bae50SIngo Molnar * entry is BSP, and so on. 2063e5fea868SYinghai Lu * boot_cpu_init() already hold bit 0 in cpu_present_mask 2064e5fea868SYinghai Lu * for BSP. 2065f62bae50SIngo Molnar */ 2066f62bae50SIngo Molnar cpu = 0; 2067e5fea868SYinghai Lu } else 2068e5fea868SYinghai Lu cpu = cpumask_next_zero(-1, cpu_present_mask); 2069e5fea868SYinghai Lu 2070e5fea868SYinghai Lu /* 2071e5fea868SYinghai Lu * Validate version 2072e5fea868SYinghai Lu */ 2073e5fea868SYinghai Lu if (version == 0x0) { 2074e5fea868SYinghai Lu pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", 2075e5fea868SYinghai Lu cpu, apicid); 2076e5fea868SYinghai Lu version = 0x10; 2077f62bae50SIngo Molnar } 2078e5fea868SYinghai Lu apic_version[apicid] = version; 2079e5fea868SYinghai Lu 2080e5fea868SYinghai Lu if (version != apic_version[boot_cpu_physical_apicid]) { 2081e5fea868SYinghai Lu pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", 2082e5fea868SYinghai Lu apic_version[boot_cpu_physical_apicid], cpu, version); 2083e5fea868SYinghai Lu } 2084e5fea868SYinghai Lu 2085e5fea868SYinghai Lu physid_set(apicid, phys_cpu_present_map); 2086f62bae50SIngo Molnar if (apicid > max_physical_apicid) 2087f62bae50SIngo Molnar max_physical_apicid = apicid; 2088f62bae50SIngo Molnar 2089f62bae50SIngo Molnar #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 2090f62bae50SIngo Molnar early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 2091f62bae50SIngo Molnar early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 2092f62bae50SIngo Molnar #endif 2093acb8bc09STejun Heo #ifdef CONFIG_X86_32 2094acb8bc09STejun Heo early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 2095acb8bc09STejun Heo apic->x86_32_early_logical_apicid(cpu); 2096acb8bc09STejun Heo #endif 2097f62bae50SIngo Molnar set_cpu_possible(cpu, true); 2098f62bae50SIngo Molnar set_cpu_present(cpu, true); 20997e1f85f9SJiang Liu 21007e1f85f9SJiang Liu return cpu; 2101f62bae50SIngo Molnar } 2102f62bae50SIngo Molnar 2103f62bae50SIngo Molnar int hard_smp_processor_id(void) 2104f62bae50SIngo Molnar { 2105f62bae50SIngo Molnar return read_apic_id(); 2106f62bae50SIngo Molnar } 2107f62bae50SIngo Molnar 2108f62bae50SIngo Molnar void default_init_apic_ldr(void) 2109f62bae50SIngo Molnar { 2110f62bae50SIngo Molnar unsigned long val; 2111f62bae50SIngo Molnar 2112f62bae50SIngo Molnar apic_write(APIC_DFR, APIC_DFR_VALUE); 2113f62bae50SIngo Molnar val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; 2114f62bae50SIngo Molnar val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); 2115f62bae50SIngo Molnar apic_write(APIC_LDR, val); 2116f62bae50SIngo Molnar } 2117f62bae50SIngo Molnar 2118ff164324SAlexander Gordeev int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 2119ff164324SAlexander Gordeev const struct cpumask *andmask, 2120ff164324SAlexander Gordeev unsigned int *apicid) 21216398268dSAlexander Gordeev { 2122ea3807eaSAlexander Gordeev unsigned int cpu; 21236398268dSAlexander Gordeev 21246398268dSAlexander Gordeev for_each_cpu_and(cpu, cpumask, andmask) { 21256398268dSAlexander Gordeev if (cpumask_test_cpu(cpu, cpu_online_mask)) 21266398268dSAlexander Gordeev break; 21276398268dSAlexander Gordeev } 2128ff164324SAlexander Gordeev 2129ea3807eaSAlexander Gordeev if (likely(cpu < nr_cpu_ids)) { 2130a5a39156SAlexander Gordeev *apicid = per_cpu(x86_cpu_to_apicid, cpu); 2131a5a39156SAlexander Gordeev return 0; 2132a5a39156SAlexander Gordeev } 2133ea3807eaSAlexander Gordeev 2134ea3807eaSAlexander Gordeev return -EINVAL; 21356398268dSAlexander Gordeev } 21366398268dSAlexander Gordeev 2137f62bae50SIngo Molnar /* 21381551df64SMichael S. Tsirkin * Override the generic EOI implementation with an optimized version. 21391551df64SMichael S. Tsirkin * Only called during early boot when only one CPU is active and with 21401551df64SMichael S. Tsirkin * interrupts disabled, so we know this does not race with actual APIC driver 21411551df64SMichael S. Tsirkin * use. 21421551df64SMichael S. Tsirkin */ 21431551df64SMichael S. Tsirkin void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) 21441551df64SMichael S. Tsirkin { 21451551df64SMichael S. Tsirkin struct apic **drv; 21461551df64SMichael S. Tsirkin 21471551df64SMichael S. Tsirkin for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { 21481551df64SMichael S. Tsirkin /* Should happen once for each apic */ 21491551df64SMichael S. Tsirkin WARN_ON((*drv)->eoi_write == eoi_write); 21501551df64SMichael S. Tsirkin (*drv)->eoi_write = eoi_write; 21511551df64SMichael S. Tsirkin } 21521551df64SMichael S. Tsirkin } 21531551df64SMichael S. Tsirkin 2154374aab33SThomas Gleixner static void __init apic_bsp_up_setup(void) 215505f7e46dSThomas Gleixner { 2156374aab33SThomas Gleixner #ifdef CONFIG_X86_64 2157374aab33SThomas Gleixner apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); 2158374aab33SThomas Gleixner #else 215905f7e46dSThomas Gleixner /* 2160374aab33SThomas Gleixner * Hack: In case of kdump, after a crash, kernel might be booting 2161374aab33SThomas Gleixner * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 2162374aab33SThomas Gleixner * might be zero if read from MP tables. Get it from LAPIC. 216305f7e46dSThomas Gleixner */ 2164374aab33SThomas Gleixner # ifdef CONFIG_CRASH_DUMP 2165374aab33SThomas Gleixner boot_cpu_physical_apicid = read_apic_id(); 2166374aab33SThomas Gleixner # endif 2167374aab33SThomas Gleixner #endif 2168374aab33SThomas Gleixner physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 216905f7e46dSThomas Gleixner } 217005f7e46dSThomas Gleixner 217105f7e46dSThomas Gleixner /** 217205f7e46dSThomas Gleixner * apic_bsp_setup - Setup function for local apic and io-apic 2173374aab33SThomas Gleixner * @upmode: Force UP mode (for APIC_init_uniprocessor) 217405f7e46dSThomas Gleixner * 217505f7e46dSThomas Gleixner * Returns: 217605f7e46dSThomas Gleixner * apic_id of BSP APIC 217705f7e46dSThomas Gleixner */ 2178374aab33SThomas Gleixner int __init apic_bsp_setup(bool upmode) 217905f7e46dSThomas Gleixner { 218005f7e46dSThomas Gleixner int id; 218105f7e46dSThomas Gleixner 218205f7e46dSThomas Gleixner connect_bsp_APIC(); 2183374aab33SThomas Gleixner if (upmode) 2184374aab33SThomas Gleixner apic_bsp_up_setup(); 218505f7e46dSThomas Gleixner setup_local_APIC(); 218605f7e46dSThomas Gleixner 218705f7e46dSThomas Gleixner if (x2apic_mode) 218805f7e46dSThomas Gleixner id = apic_read(APIC_LDR); 218905f7e46dSThomas Gleixner else 219005f7e46dSThomas Gleixner id = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 219105f7e46dSThomas Gleixner 219205f7e46dSThomas Gleixner enable_IO_APIC(); 2193374aab33SThomas Gleixner end_local_APIC_setup(); 2194374aab33SThomas Gleixner irq_remap_enable_fault_handling(); 219505f7e46dSThomas Gleixner setup_IO_APIC(); 21969c4d9c73SThomas Gleixner /* Setup local timer */ 21979c4d9c73SThomas Gleixner x86_init.timers.setup_percpu_clockev(); 219805f7e46dSThomas Gleixner return id; 219905f7e46dSThomas Gleixner } 220005f7e46dSThomas Gleixner 22011551df64SMichael S. Tsirkin /* 2202e714a91fSThomas Gleixner * This initializes the IO-APIC and APIC hardware if this is 2203e714a91fSThomas Gleixner * a UP kernel. 2204e714a91fSThomas Gleixner */ 2205e714a91fSThomas Gleixner int __init APIC_init_uniprocessor(void) 2206e714a91fSThomas Gleixner { 2207e714a91fSThomas Gleixner if (disable_apic) { 2208e714a91fSThomas Gleixner pr_info("Apic disabled\n"); 2209e714a91fSThomas Gleixner return -1; 2210e714a91fSThomas Gleixner } 2211e714a91fSThomas Gleixner #ifdef CONFIG_X86_64 2212e714a91fSThomas Gleixner if (!cpu_has_apic) { 2213e714a91fSThomas Gleixner disable_apic = 1; 2214e714a91fSThomas Gleixner pr_info("Apic disabled by BIOS\n"); 2215e714a91fSThomas Gleixner return -1; 2216e714a91fSThomas Gleixner } 2217e714a91fSThomas Gleixner #else 2218e714a91fSThomas Gleixner if (!smp_found_config && !cpu_has_apic) 2219e714a91fSThomas Gleixner return -1; 2220e714a91fSThomas Gleixner 2221e714a91fSThomas Gleixner /* 2222e714a91fSThomas Gleixner * Complain if the BIOS pretends there is one. 2223e714a91fSThomas Gleixner */ 2224e714a91fSThomas Gleixner if (!cpu_has_apic && 2225e714a91fSThomas Gleixner APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 2226e714a91fSThomas Gleixner pr_err("BIOS bug, local APIC 0x%x not detected!...\n", 2227e714a91fSThomas Gleixner boot_cpu_physical_apicid); 2228e714a91fSThomas Gleixner return -1; 2229e714a91fSThomas Gleixner } 2230e714a91fSThomas Gleixner #endif 2231e714a91fSThomas Gleixner 2232374aab33SThomas Gleixner if (!smp_found_config) 2233374aab33SThomas Gleixner disable_ioapic_support(); 2234374aab33SThomas Gleixner 2235e714a91fSThomas Gleixner default_setup_apic_routing(); 2236374aab33SThomas Gleixner apic_bsp_setup(true); 2237e714a91fSThomas Gleixner return 0; 2238e714a91fSThomas Gleixner } 2239e714a91fSThomas Gleixner 224030b8b006SThomas Gleixner #ifdef CONFIG_UP_LATE_INIT 224130b8b006SThomas Gleixner void __init up_late_init(void) 224230b8b006SThomas Gleixner { 224330b8b006SThomas Gleixner APIC_init_uniprocessor(); 224430b8b006SThomas Gleixner } 224530b8b006SThomas Gleixner #endif 224630b8b006SThomas Gleixner 2247e714a91fSThomas Gleixner /* 2248f62bae50SIngo Molnar * Power management 2249f62bae50SIngo Molnar */ 2250f62bae50SIngo Molnar #ifdef CONFIG_PM 2251f62bae50SIngo Molnar 2252f62bae50SIngo Molnar static struct { 2253f62bae50SIngo Molnar /* 2254f62bae50SIngo Molnar * 'active' is true if the local APIC was enabled by us and 2255f62bae50SIngo Molnar * not the BIOS; this signifies that we are also responsible 2256f62bae50SIngo Molnar * for disabling it before entering apm/acpi suspend 2257f62bae50SIngo Molnar */ 2258f62bae50SIngo Molnar int active; 2259f62bae50SIngo Molnar /* r/w apic fields */ 2260f62bae50SIngo Molnar unsigned int apic_id; 2261f62bae50SIngo Molnar unsigned int apic_taskpri; 2262f62bae50SIngo Molnar unsigned int apic_ldr; 2263f62bae50SIngo Molnar unsigned int apic_dfr; 2264f62bae50SIngo Molnar unsigned int apic_spiv; 2265f62bae50SIngo Molnar unsigned int apic_lvtt; 2266f62bae50SIngo Molnar unsigned int apic_lvtpc; 2267f62bae50SIngo Molnar unsigned int apic_lvt0; 2268f62bae50SIngo Molnar unsigned int apic_lvt1; 2269f62bae50SIngo Molnar unsigned int apic_lvterr; 2270f62bae50SIngo Molnar unsigned int apic_tmict; 2271f62bae50SIngo Molnar unsigned int apic_tdcr; 2272f62bae50SIngo Molnar unsigned int apic_thmr; 2273f62bae50SIngo Molnar } apic_pm_state; 2274f62bae50SIngo Molnar 2275f3c6ea1bSRafael J. Wysocki static int lapic_suspend(void) 2276f62bae50SIngo Molnar { 2277f62bae50SIngo Molnar unsigned long flags; 2278f62bae50SIngo Molnar int maxlvt; 2279f62bae50SIngo Molnar 2280f62bae50SIngo Molnar if (!apic_pm_state.active) 2281f62bae50SIngo Molnar return 0; 2282f62bae50SIngo Molnar 2283f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 2284f62bae50SIngo Molnar 2285f62bae50SIngo Molnar apic_pm_state.apic_id = apic_read(APIC_ID); 2286f62bae50SIngo Molnar apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2287f62bae50SIngo Molnar apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2288f62bae50SIngo Molnar apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2289f62bae50SIngo Molnar apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2290f62bae50SIngo Molnar apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2291f62bae50SIngo Molnar if (maxlvt >= 4) 2292f62bae50SIngo Molnar apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2293f62bae50SIngo Molnar apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2294f62bae50SIngo Molnar apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2295f62bae50SIngo Molnar apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2296f62bae50SIngo Molnar apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2297f62bae50SIngo Molnar apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 22984efc0670SAndi Kleen #ifdef CONFIG_X86_THERMAL_VECTOR 2299f62bae50SIngo Molnar if (maxlvt >= 5) 2300f62bae50SIngo Molnar apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2301f62bae50SIngo Molnar #endif 2302f62bae50SIngo Molnar 2303f62bae50SIngo Molnar local_irq_save(flags); 2304f62bae50SIngo Molnar disable_local_APIC(); 2305fc1edaf9SSuresh Siddha 230695a02e97SSuresh Siddha irq_remapping_disable(); 2307fc1edaf9SSuresh Siddha 2308f62bae50SIngo Molnar local_irq_restore(flags); 2309f62bae50SIngo Molnar return 0; 2310f62bae50SIngo Molnar } 2311f62bae50SIngo Molnar 2312f3c6ea1bSRafael J. Wysocki static void lapic_resume(void) 2313f62bae50SIngo Molnar { 2314f62bae50SIngo Molnar unsigned int l, h; 2315f62bae50SIngo Molnar unsigned long flags; 231631dce14aSSuresh Siddha int maxlvt; 2317b24696bcSFenghua Yu 2318f62bae50SIngo Molnar if (!apic_pm_state.active) 2319f3c6ea1bSRafael J. Wysocki return; 2320f62bae50SIngo Molnar 2321b24696bcSFenghua Yu local_irq_save(flags); 2322336224baSJoerg Roedel 232331dce14aSSuresh Siddha /* 232431dce14aSSuresh Siddha * IO-APIC and PIC have their own resume routines. 232531dce14aSSuresh Siddha * We just mask them here to make sure the interrupt 232631dce14aSSuresh Siddha * subsystem is completely quiet while we enable x2apic 232731dce14aSSuresh Siddha * and interrupt-remapping. 232831dce14aSSuresh Siddha */ 232931dce14aSSuresh Siddha mask_ioapic_entries(); 2330b81bb373SJacob Pan legacy_pic->mask_all(); 2331f62bae50SIngo Molnar 2332659006bfSThomas Gleixner if (x2apic_mode) { 2333659006bfSThomas Gleixner __x2apic_enable(); 2334659006bfSThomas Gleixner } else { 2335f62bae50SIngo Molnar /* 2336f62bae50SIngo Molnar * Make sure the APICBASE points to the right address 2337f62bae50SIngo Molnar * 2338f62bae50SIngo Molnar * FIXME! This will be wrong if we ever support suspend on 2339f62bae50SIngo Molnar * SMP! We'll need to do this as part of the CPU restore! 2340f62bae50SIngo Molnar */ 2341cbf2829bSBryan O'Donoghue if (boot_cpu_data.x86 >= 6) { 2342f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, l, h); 2343f62bae50SIngo Molnar l &= ~MSR_IA32_APICBASE_BASE; 2344f62bae50SIngo Molnar l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2345f62bae50SIngo Molnar wrmsr(MSR_IA32_APICBASE, l, h); 2346f62bae50SIngo Molnar } 2347cbf2829bSBryan O'Donoghue } 2348f62bae50SIngo Molnar 2349b24696bcSFenghua Yu maxlvt = lapic_get_maxlvt(); 2350f62bae50SIngo Molnar apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2351f62bae50SIngo Molnar apic_write(APIC_ID, apic_pm_state.apic_id); 2352f62bae50SIngo Molnar apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2353f62bae50SIngo Molnar apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2354f62bae50SIngo Molnar apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2355f62bae50SIngo Molnar apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2356f62bae50SIngo Molnar apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2357f62bae50SIngo Molnar apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 235871c69f7fSPaul Bolle #if defined(CONFIG_X86_MCE_INTEL) 2359f62bae50SIngo Molnar if (maxlvt >= 5) 2360f62bae50SIngo Molnar apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2361f62bae50SIngo Molnar #endif 2362f62bae50SIngo Molnar if (maxlvt >= 4) 2363f62bae50SIngo Molnar apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2364f62bae50SIngo Molnar apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2365f62bae50SIngo Molnar apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2366f62bae50SIngo Molnar apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2367f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 2368f62bae50SIngo Molnar apic_read(APIC_ESR); 2369f62bae50SIngo Molnar apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2370f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 2371f62bae50SIngo Molnar apic_read(APIC_ESR); 2372f62bae50SIngo Molnar 237395a02e97SSuresh Siddha irq_remapping_reenable(x2apic_mode); 237431dce14aSSuresh Siddha 2375f62bae50SIngo Molnar local_irq_restore(flags); 2376f62bae50SIngo Molnar } 2377f62bae50SIngo Molnar 2378f62bae50SIngo Molnar /* 2379f62bae50SIngo Molnar * This device has no shutdown method - fully functioning local APICs 2380f62bae50SIngo Molnar * are needed on every CPU up until machine_halt/restart/poweroff. 2381f62bae50SIngo Molnar */ 2382f62bae50SIngo Molnar 2383f3c6ea1bSRafael J. Wysocki static struct syscore_ops lapic_syscore_ops = { 2384f62bae50SIngo Molnar .resume = lapic_resume, 2385f62bae50SIngo Molnar .suspend = lapic_suspend, 2386f62bae50SIngo Molnar }; 2387f62bae50SIngo Molnar 2388148f9bb8SPaul Gortmaker static void apic_pm_activate(void) 2389f62bae50SIngo Molnar { 2390f62bae50SIngo Molnar apic_pm_state.active = 1; 2391f62bae50SIngo Molnar } 2392f62bae50SIngo Molnar 2393f62bae50SIngo Molnar static int __init init_lapic_sysfs(void) 2394f62bae50SIngo Molnar { 2395f62bae50SIngo Molnar /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2396f3c6ea1bSRafael J. Wysocki if (cpu_has_apic) 2397f3c6ea1bSRafael J. Wysocki register_syscore_ops(&lapic_syscore_ops); 2398f62bae50SIngo Molnar 2399f3c6ea1bSRafael J. Wysocki return 0; 2400f62bae50SIngo Molnar } 2401b24696bcSFenghua Yu 2402b24696bcSFenghua Yu /* local apic needs to resume before other devices access its registers. */ 2403b24696bcSFenghua Yu core_initcall(init_lapic_sysfs); 2404f62bae50SIngo Molnar 2405f62bae50SIngo Molnar #else /* CONFIG_PM */ 2406f62bae50SIngo Molnar 2407f62bae50SIngo Molnar static void apic_pm_activate(void) { } 2408f62bae50SIngo Molnar 2409f62bae50SIngo Molnar #endif /* CONFIG_PM */ 2410f62bae50SIngo Molnar 2411f62bae50SIngo Molnar #ifdef CONFIG_X86_64 2412e0e42142SYinghai Lu 2413148f9bb8SPaul Gortmaker static int multi_checked; 2414148f9bb8SPaul Gortmaker static int multi; 2415e0e42142SYinghai Lu 2416148f9bb8SPaul Gortmaker static int set_multi(const struct dmi_system_id *d) 2417e0e42142SYinghai Lu { 2418e0e42142SYinghai Lu if (multi) 2419e0e42142SYinghai Lu return 0; 24206f0aced6SCyrill Gorcunov pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2421e0e42142SYinghai Lu multi = 1; 2422e0e42142SYinghai Lu return 0; 2423e0e42142SYinghai Lu } 2424e0e42142SYinghai Lu 2425148f9bb8SPaul Gortmaker static const struct dmi_system_id multi_dmi_table[] = { 2426e0e42142SYinghai Lu { 2427e0e42142SYinghai Lu .callback = set_multi, 2428e0e42142SYinghai Lu .ident = "IBM System Summit2", 2429e0e42142SYinghai Lu .matches = { 2430e0e42142SYinghai Lu DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2431e0e42142SYinghai Lu DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2432e0e42142SYinghai Lu }, 2433e0e42142SYinghai Lu }, 2434e0e42142SYinghai Lu {} 2435e0e42142SYinghai Lu }; 2436e0e42142SYinghai Lu 2437148f9bb8SPaul Gortmaker static void dmi_check_multi(void) 2438e0e42142SYinghai Lu { 2439e0e42142SYinghai Lu if (multi_checked) 2440e0e42142SYinghai Lu return; 2441e0e42142SYinghai Lu 2442e0e42142SYinghai Lu dmi_check_system(multi_dmi_table); 2443e0e42142SYinghai Lu multi_checked = 1; 2444e0e42142SYinghai Lu } 2445f62bae50SIngo Molnar 2446f62bae50SIngo Molnar /* 2447e0e42142SYinghai Lu * apic_is_clustered_box() -- Check if we can expect good TSC 2448e0e42142SYinghai Lu * 2449e0e42142SYinghai Lu * Thus far, the major user of this is IBM's Summit2 series: 2450e0e42142SYinghai Lu * Clustered boxes may have unsynced TSC problems if they are 2451e0e42142SYinghai Lu * multi-chassis. 2452e0e42142SYinghai Lu * Use DMI to check them 2453f62bae50SIngo Molnar */ 2454148f9bb8SPaul Gortmaker int apic_is_clustered_box(void) 2455e0e42142SYinghai Lu { 2456e0e42142SYinghai Lu dmi_check_multi(); 2457411cf9eeSOren Twaig return multi; 2458f62bae50SIngo Molnar } 2459f62bae50SIngo Molnar #endif 2460f62bae50SIngo Molnar 2461f62bae50SIngo Molnar /* 2462f62bae50SIngo Molnar * APIC command line parameters 2463f62bae50SIngo Molnar */ 2464f62bae50SIngo Molnar static int __init setup_disableapic(char *arg) 2465f62bae50SIngo Molnar { 2466f62bae50SIngo Molnar disable_apic = 1; 2467f62bae50SIngo Molnar setup_clear_cpu_cap(X86_FEATURE_APIC); 2468f62bae50SIngo Molnar return 0; 2469f62bae50SIngo Molnar } 2470f62bae50SIngo Molnar early_param("disableapic", setup_disableapic); 2471f62bae50SIngo Molnar 2472f62bae50SIngo Molnar /* same as disableapic, for compatibility */ 2473f62bae50SIngo Molnar static int __init setup_nolapic(char *arg) 2474f62bae50SIngo Molnar { 2475f62bae50SIngo Molnar return setup_disableapic(arg); 2476f62bae50SIngo Molnar } 2477f62bae50SIngo Molnar early_param("nolapic", setup_nolapic); 2478f62bae50SIngo Molnar 2479f62bae50SIngo Molnar static int __init parse_lapic_timer_c2_ok(char *arg) 2480f62bae50SIngo Molnar { 2481f62bae50SIngo Molnar local_apic_timer_c2_ok = 1; 2482f62bae50SIngo Molnar return 0; 2483f62bae50SIngo Molnar } 2484f62bae50SIngo Molnar early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2485f62bae50SIngo Molnar 2486f62bae50SIngo Molnar static int __init parse_disable_apic_timer(char *arg) 2487f62bae50SIngo Molnar { 2488f62bae50SIngo Molnar disable_apic_timer = 1; 2489f62bae50SIngo Molnar return 0; 2490f62bae50SIngo Molnar } 2491f62bae50SIngo Molnar early_param("noapictimer", parse_disable_apic_timer); 2492f62bae50SIngo Molnar 2493f62bae50SIngo Molnar static int __init parse_nolapic_timer(char *arg) 2494f62bae50SIngo Molnar { 2495f62bae50SIngo Molnar disable_apic_timer = 1; 2496f62bae50SIngo Molnar return 0; 2497f62bae50SIngo Molnar } 2498f62bae50SIngo Molnar early_param("nolapic_timer", parse_nolapic_timer); 2499f62bae50SIngo Molnar 2500f62bae50SIngo Molnar static int __init apic_set_verbosity(char *arg) 2501f62bae50SIngo Molnar { 2502f62bae50SIngo Molnar if (!arg) { 2503f62bae50SIngo Molnar #ifdef CONFIG_X86_64 2504f62bae50SIngo Molnar skip_ioapic_setup = 0; 2505f62bae50SIngo Molnar return 0; 2506f62bae50SIngo Molnar #endif 2507f62bae50SIngo Molnar return -EINVAL; 2508f62bae50SIngo Molnar } 2509f62bae50SIngo Molnar 2510f62bae50SIngo Molnar if (strcmp("debug", arg) == 0) 2511f62bae50SIngo Molnar apic_verbosity = APIC_DEBUG; 2512f62bae50SIngo Molnar else if (strcmp("verbose", arg) == 0) 2513f62bae50SIngo Molnar apic_verbosity = APIC_VERBOSE; 2514f62bae50SIngo Molnar else { 2515f62bae50SIngo Molnar pr_warning("APIC Verbosity level %s not recognised" 2516f62bae50SIngo Molnar " use apic=verbose or apic=debug\n", arg); 2517f62bae50SIngo Molnar return -EINVAL; 2518f62bae50SIngo Molnar } 2519f62bae50SIngo Molnar 2520f62bae50SIngo Molnar return 0; 2521f62bae50SIngo Molnar } 2522f62bae50SIngo Molnar early_param("apic", apic_set_verbosity); 2523f62bae50SIngo Molnar 2524f62bae50SIngo Molnar static int __init lapic_insert_resource(void) 2525f62bae50SIngo Molnar { 2526f62bae50SIngo Molnar if (!apic_phys) 2527f62bae50SIngo Molnar return -1; 2528f62bae50SIngo Molnar 2529f62bae50SIngo Molnar /* Put local APIC into the resource map. */ 2530f62bae50SIngo Molnar lapic_resource.start = apic_phys; 2531f62bae50SIngo Molnar lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2532f62bae50SIngo Molnar insert_resource(&iomem_resource, &lapic_resource); 2533f62bae50SIngo Molnar 2534f62bae50SIngo Molnar return 0; 2535f62bae50SIngo Molnar } 2536f62bae50SIngo Molnar 2537f62bae50SIngo Molnar /* 2538f62bae50SIngo Molnar * need call insert after e820_reserve_resources() 2539f62bae50SIngo Molnar * that is using request_resource 2540f62bae50SIngo Molnar */ 2541f62bae50SIngo Molnar late_initcall(lapic_insert_resource); 2542151e0c7dSHATAYAMA Daisuke 2543151e0c7dSHATAYAMA Daisuke static int __init apic_set_disabled_cpu_apicid(char *arg) 2544151e0c7dSHATAYAMA Daisuke { 2545151e0c7dSHATAYAMA Daisuke if (!arg || !get_option(&arg, &disabled_cpu_apicid)) 2546151e0c7dSHATAYAMA Daisuke return -EINVAL; 2547151e0c7dSHATAYAMA Daisuke 2548151e0c7dSHATAYAMA Daisuke return 0; 2549151e0c7dSHATAYAMA Daisuke } 2550151e0c7dSHATAYAMA Daisuke early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); 2551