1f62bae50SIngo Molnar /* 2f62bae50SIngo Molnar * Local APIC handling, local APIC timers 3f62bae50SIngo Molnar * 4f62bae50SIngo Molnar * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 5f62bae50SIngo Molnar * 6f62bae50SIngo Molnar * Fixes 7f62bae50SIngo Molnar * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8f62bae50SIngo Molnar * thanks to Eric Gilmore 9f62bae50SIngo Molnar * and Rolf G. Tews 10f62bae50SIngo Molnar * for testing these extensively. 11f62bae50SIngo Molnar * Maciej W. Rozycki : Various updates and fixes. 12f62bae50SIngo Molnar * Mikael Pettersson : Power Management for UP-APIC. 13f62bae50SIngo Molnar * Pavel Machek and 14f62bae50SIngo Molnar * Mikael Pettersson : PM converted to driver model. 15f62bae50SIngo Molnar */ 16f62bae50SIngo Molnar 17cdd6c482SIngo Molnar #include <linux/perf_event.h> 18f62bae50SIngo Molnar #include <linux/kernel_stat.h> 19f62bae50SIngo Molnar #include <linux/mc146818rtc.h> 20f62bae50SIngo Molnar #include <linux/acpi_pmtmr.h> 21f62bae50SIngo Molnar #include <linux/clockchips.h> 22f62bae50SIngo Molnar #include <linux/interrupt.h> 23f62bae50SIngo Molnar #include <linux/bootmem.h> 24f62bae50SIngo Molnar #include <linux/ftrace.h> 25f62bae50SIngo Molnar #include <linux/ioport.h> 26f62bae50SIngo Molnar #include <linux/module.h> 27f3c6ea1bSRafael J. Wysocki #include <linux/syscore_ops.h> 28f62bae50SIngo Molnar #include <linux/delay.h> 29f62bae50SIngo Molnar #include <linux/timex.h> 30334955efSRalf Baechle #include <linux/i8253.h> 31f62bae50SIngo Molnar #include <linux/dmar.h> 32f62bae50SIngo Molnar #include <linux/init.h> 33f62bae50SIngo Molnar #include <linux/cpu.h> 34f62bae50SIngo Molnar #include <linux/dmi.h> 35f62bae50SIngo Molnar #include <linux/smp.h> 36f62bae50SIngo Molnar #include <linux/mm.h> 37f62bae50SIngo Molnar 3883ab8514SSteven Rostedt (Red Hat) #include <asm/trace/irq_vectors.h> 398a8f422dSSuresh Siddha #include <asm/irq_remapping.h> 40cdd6c482SIngo Molnar #include <asm/perf_event.h> 41736decacSThomas Gleixner #include <asm/x86_init.h> 42f62bae50SIngo Molnar #include <asm/pgalloc.h> 4360063497SArun Sharma #include <linux/atomic.h> 44f62bae50SIngo Molnar #include <asm/mpspec.h> 45f62bae50SIngo Molnar #include <asm/i8259.h> 46f62bae50SIngo Molnar #include <asm/proto.h> 47f62bae50SIngo Molnar #include <asm/apic.h> 487167d08eSHenrik Kretzschmar #include <asm/io_apic.h> 49f62bae50SIngo Molnar #include <asm/desc.h> 50f62bae50SIngo Molnar #include <asm/hpet.h> 51f62bae50SIngo Molnar #include <asm/idle.h> 52f62bae50SIngo Molnar #include <asm/mtrr.h> 5316f871bcSRalf Baechle #include <asm/time.h> 54f62bae50SIngo Molnar #include <asm/smp.h> 55638bee71SH. Peter Anvin #include <asm/mce.h> 568c3ba8d0SKerstin Jonsson #include <asm/tsc.h> 572904ed8dSSheng Yang #include <asm/hypervisor.h> 58f62bae50SIngo Molnar 59f62bae50SIngo Molnar unsigned int num_processors; 60f62bae50SIngo Molnar 61148f9bb8SPaul Gortmaker unsigned disabled_cpus; 62f62bae50SIngo Molnar 63f62bae50SIngo Molnar /* Processor that is doing the boot up */ 64f62bae50SIngo Molnar unsigned int boot_cpu_physical_apicid = -1U; 65cc08e04cSDavid Rientjes EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); 66f62bae50SIngo Molnar 67f62bae50SIngo Molnar /* 68f62bae50SIngo Molnar * The highest APIC ID seen during enumeration. 69f62bae50SIngo Molnar */ 70f62bae50SIngo Molnar unsigned int max_physical_apicid; 71f62bae50SIngo Molnar 72f62bae50SIngo Molnar /* 73f62bae50SIngo Molnar * Bitmask of physically existing CPUs: 74f62bae50SIngo Molnar */ 75f62bae50SIngo Molnar physid_mask_t phys_cpu_present_map; 76f62bae50SIngo Molnar 77f62bae50SIngo Molnar /* 78f62bae50SIngo Molnar * Map cpu index to physical APIC ID 79f62bae50SIngo Molnar */ 800816b0f0SVlad Zolotarov DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); 810816b0f0SVlad Zolotarov DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); 82f62bae50SIngo Molnar EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 83f62bae50SIngo Molnar EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 84f62bae50SIngo Molnar 85f62bae50SIngo Molnar #ifdef CONFIG_X86_32 864c321ff8STejun Heo 874c321ff8STejun Heo /* 884c321ff8STejun Heo * On x86_32, the mapping between cpu and logical apicid may vary 894c321ff8STejun Heo * depending on apic in use. The following early percpu variable is 904c321ff8STejun Heo * used for the mapping. This is where the behaviors of x86_64 and 32 914c321ff8STejun Heo * actually diverge. Let's keep it ugly for now. 924c321ff8STejun Heo */ 930816b0f0SVlad Zolotarov DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); 944c321ff8STejun Heo 95f62bae50SIngo Molnar /* Local APIC was disabled by the BIOS and enabled by the kernel */ 96f62bae50SIngo Molnar static int enabled_via_apicbase; 97f62bae50SIngo Molnar 98c0eaa453SCyrill Gorcunov /* 99c0eaa453SCyrill Gorcunov * Handle interrupt mode configuration register (IMCR). 100c0eaa453SCyrill Gorcunov * This register controls whether the interrupt signals 101c0eaa453SCyrill Gorcunov * that reach the BSP come from the master PIC or from the 102c0eaa453SCyrill Gorcunov * local APIC. Before entering Symmetric I/O Mode, either 103c0eaa453SCyrill Gorcunov * the BIOS or the operating system must switch out of 104c0eaa453SCyrill Gorcunov * PIC Mode by changing the IMCR. 105c0eaa453SCyrill Gorcunov */ 1065cda395fSAlexander van Heukelum static inline void imcr_pic_to_apic(void) 107c0eaa453SCyrill Gorcunov { 108c0eaa453SCyrill Gorcunov /* select IMCR register */ 109c0eaa453SCyrill Gorcunov outb(0x70, 0x22); 110c0eaa453SCyrill Gorcunov /* NMI and 8259 INTR go through APIC */ 111c0eaa453SCyrill Gorcunov outb(0x01, 0x23); 112c0eaa453SCyrill Gorcunov } 113c0eaa453SCyrill Gorcunov 1145cda395fSAlexander van Heukelum static inline void imcr_apic_to_pic(void) 115c0eaa453SCyrill Gorcunov { 116c0eaa453SCyrill Gorcunov /* select IMCR register */ 117c0eaa453SCyrill Gorcunov outb(0x70, 0x22); 118c0eaa453SCyrill Gorcunov /* NMI and 8259 INTR go directly to BSP */ 119c0eaa453SCyrill Gorcunov outb(0x00, 0x23); 120c0eaa453SCyrill Gorcunov } 121f62bae50SIngo Molnar #endif 122f62bae50SIngo Molnar 123279f1461SSuresh Siddha /* 124279f1461SSuresh Siddha * Knob to control our willingness to enable the local APIC. 125279f1461SSuresh Siddha * 126279f1461SSuresh Siddha * +1=force-enable 127279f1461SSuresh Siddha */ 128279f1461SSuresh Siddha static int force_enable_local_apic __initdata; 129279f1461SSuresh Siddha /* 130279f1461SSuresh Siddha * APIC command line parameters 131279f1461SSuresh Siddha */ 132279f1461SSuresh Siddha static int __init parse_lapic(char *arg) 133279f1461SSuresh Siddha { 134279f1461SSuresh Siddha if (config_enabled(CONFIG_X86_32) && !arg) 135279f1461SSuresh Siddha force_enable_local_apic = 1; 13627cf9298SMathias Krause else if (arg && !strncmp(arg, "notscdeadline", 13)) 137279f1461SSuresh Siddha setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 138279f1461SSuresh Siddha return 0; 139279f1461SSuresh Siddha } 140279f1461SSuresh Siddha early_param("lapic", parse_lapic); 141279f1461SSuresh Siddha 142f62bae50SIngo Molnar #ifdef CONFIG_X86_64 143f62bae50SIngo Molnar static int apic_calibrate_pmtmr __initdata; 144f62bae50SIngo Molnar static __init int setup_apicpmtimer(char *s) 145f62bae50SIngo Molnar { 146f62bae50SIngo Molnar apic_calibrate_pmtmr = 1; 147f62bae50SIngo Molnar notsc_setup(NULL); 148f62bae50SIngo Molnar return 0; 149f62bae50SIngo Molnar } 150f62bae50SIngo Molnar __setup("apicpmtimer", setup_apicpmtimer); 151f62bae50SIngo Molnar #endif 152f62bae50SIngo Molnar 153fc1edaf9SSuresh Siddha int x2apic_mode; 154f62bae50SIngo Molnar #ifdef CONFIG_X86_X2APIC 155f62bae50SIngo Molnar /* x2apic enabled before OS handover */ 156fb209bd8SYinghai Lu int x2apic_preenabled; 157fb209bd8SYinghai Lu static int x2apic_disabled; 158a31bc327SYinghai Lu static int nox2apic; 159f62bae50SIngo Molnar static __init int setup_nox2apic(char *str) 160f62bae50SIngo Molnar { 16139d83a5dSSuresh Siddha if (x2apic_enabled()) { 162a31bc327SYinghai Lu int apicid = native_apic_msr_read(APIC_ID); 163a31bc327SYinghai Lu 164a31bc327SYinghai Lu if (apicid >= 255) { 165a31bc327SYinghai Lu pr_warning("Apicid: %08x, cannot enforce nox2apic\n", 166a31bc327SYinghai Lu apicid); 16739d83a5dSSuresh Siddha return 0; 16839d83a5dSSuresh Siddha } 16939d83a5dSSuresh Siddha 170a31bc327SYinghai Lu pr_warning("x2apic already enabled. will disable it\n"); 171a31bc327SYinghai Lu } else 172f62bae50SIngo Molnar setup_clear_cpu_cap(X86_FEATURE_X2APIC); 173a31bc327SYinghai Lu 174a31bc327SYinghai Lu nox2apic = 1; 175a31bc327SYinghai Lu 176f62bae50SIngo Molnar return 0; 177f62bae50SIngo Molnar } 178f62bae50SIngo Molnar early_param("nox2apic", setup_nox2apic); 179f62bae50SIngo Molnar #endif 180f62bae50SIngo Molnar 181f62bae50SIngo Molnar unsigned long mp_lapic_addr; 182f62bae50SIngo Molnar int disable_apic; 183f62bae50SIngo Molnar /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 18425874a29SHenrik Kretzschmar static int disable_apic_timer __initdata; 185f62bae50SIngo Molnar /* Local APIC timer works in C2 */ 186f62bae50SIngo Molnar int local_apic_timer_c2_ok; 187f62bae50SIngo Molnar EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 188f62bae50SIngo Molnar 189f62bae50SIngo Molnar int first_system_vector = 0xfe; 190f62bae50SIngo Molnar 191f62bae50SIngo Molnar /* 192f62bae50SIngo Molnar * Debug level, exported for io_apic.c 193f62bae50SIngo Molnar */ 194f62bae50SIngo Molnar unsigned int apic_verbosity; 195f62bae50SIngo Molnar 196f62bae50SIngo Molnar int pic_mode; 197f62bae50SIngo Molnar 198f62bae50SIngo Molnar /* Have we found an MP table */ 199f62bae50SIngo Molnar int smp_found_config; 200f62bae50SIngo Molnar 201f62bae50SIngo Molnar static struct resource lapic_resource = { 202f62bae50SIngo Molnar .name = "Local APIC", 203f62bae50SIngo Molnar .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 204f62bae50SIngo Molnar }; 205f62bae50SIngo Molnar 2061ade93efSJacob Pan unsigned int lapic_timer_frequency = 0; 207f62bae50SIngo Molnar 208f62bae50SIngo Molnar static void apic_pm_activate(void); 209f62bae50SIngo Molnar 210f62bae50SIngo Molnar static unsigned long apic_phys; 211f62bae50SIngo Molnar 212f62bae50SIngo Molnar /* 213f62bae50SIngo Molnar * Get the LAPIC version 214f62bae50SIngo Molnar */ 215f62bae50SIngo Molnar static inline int lapic_get_version(void) 216f62bae50SIngo Molnar { 217f62bae50SIngo Molnar return GET_APIC_VERSION(apic_read(APIC_LVR)); 218f62bae50SIngo Molnar } 219f62bae50SIngo Molnar 220f62bae50SIngo Molnar /* 221f62bae50SIngo Molnar * Check, if the APIC is integrated or a separate chip 222f62bae50SIngo Molnar */ 223f62bae50SIngo Molnar static inline int lapic_is_integrated(void) 224f62bae50SIngo Molnar { 225f62bae50SIngo Molnar #ifdef CONFIG_X86_64 226f62bae50SIngo Molnar return 1; 227f62bae50SIngo Molnar #else 228f62bae50SIngo Molnar return APIC_INTEGRATED(lapic_get_version()); 229f62bae50SIngo Molnar #endif 230f62bae50SIngo Molnar } 231f62bae50SIngo Molnar 232f62bae50SIngo Molnar /* 233f62bae50SIngo Molnar * Check, whether this is a modern or a first generation APIC 234f62bae50SIngo Molnar */ 235f62bae50SIngo Molnar static int modern_apic(void) 236f62bae50SIngo Molnar { 237f62bae50SIngo Molnar /* AMD systems use old APIC versions, so check the CPU */ 238f62bae50SIngo Molnar if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 239f62bae50SIngo Molnar boot_cpu_data.x86 >= 0xf) 240f62bae50SIngo Molnar return 1; 241f62bae50SIngo Molnar return lapic_get_version() >= 0x14; 242f62bae50SIngo Molnar } 243f62bae50SIngo Molnar 24408306ce6SCyrill Gorcunov /* 245a933c618SCyrill Gorcunov * right after this call apic become NOOP driven 246a933c618SCyrill Gorcunov * so apic->write/read doesn't do anything 24708306ce6SCyrill Gorcunov */ 24825874a29SHenrik Kretzschmar static void __init apic_disable(void) 24908306ce6SCyrill Gorcunov { 250f88f2b4fSCyrill Gorcunov pr_info("APIC: switched to apic NOOP\n"); 251a933c618SCyrill Gorcunov apic = &apic_noop; 25208306ce6SCyrill Gorcunov } 25308306ce6SCyrill Gorcunov 254f62bae50SIngo Molnar void native_apic_wait_icr_idle(void) 255f62bae50SIngo Molnar { 256f62bae50SIngo Molnar while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 257f62bae50SIngo Molnar cpu_relax(); 258f62bae50SIngo Molnar } 259f62bae50SIngo Molnar 260f62bae50SIngo Molnar u32 native_safe_apic_wait_icr_idle(void) 261f62bae50SIngo Molnar { 262f62bae50SIngo Molnar u32 send_status; 263f62bae50SIngo Molnar int timeout; 264f62bae50SIngo Molnar 265f62bae50SIngo Molnar timeout = 0; 266f62bae50SIngo Molnar do { 267f62bae50SIngo Molnar send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 268f62bae50SIngo Molnar if (!send_status) 269f62bae50SIngo Molnar break; 270b49d7d87SFernando Luis Vazquez Cao inc_irq_stat(icr_read_retry_count); 271f62bae50SIngo Molnar udelay(100); 272f62bae50SIngo Molnar } while (timeout++ < 1000); 273f62bae50SIngo Molnar 274f62bae50SIngo Molnar return send_status; 275f62bae50SIngo Molnar } 276f62bae50SIngo Molnar 277f62bae50SIngo Molnar void native_apic_icr_write(u32 low, u32 id) 278f62bae50SIngo Molnar { 279f62bae50SIngo Molnar apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 280f62bae50SIngo Molnar apic_write(APIC_ICR, low); 281f62bae50SIngo Molnar } 282f62bae50SIngo Molnar 283f62bae50SIngo Molnar u64 native_apic_icr_read(void) 284f62bae50SIngo Molnar { 285f62bae50SIngo Molnar u32 icr1, icr2; 286f62bae50SIngo Molnar 287f62bae50SIngo Molnar icr2 = apic_read(APIC_ICR2); 288f62bae50SIngo Molnar icr1 = apic_read(APIC_ICR); 289f62bae50SIngo Molnar 290f62bae50SIngo Molnar return icr1 | ((u64)icr2 << 32); 291f62bae50SIngo Molnar } 292f62bae50SIngo Molnar 293f62bae50SIngo Molnar #ifdef CONFIG_X86_32 294f62bae50SIngo Molnar /** 295f62bae50SIngo Molnar * get_physical_broadcast - Get number of physical broadcast IDs 296f62bae50SIngo Molnar */ 297f62bae50SIngo Molnar int get_physical_broadcast(void) 298f62bae50SIngo Molnar { 299f62bae50SIngo Molnar return modern_apic() ? 0xff : 0xf; 300f62bae50SIngo Molnar } 301f62bae50SIngo Molnar #endif 302f62bae50SIngo Molnar 303f62bae50SIngo Molnar /** 304f62bae50SIngo Molnar * lapic_get_maxlvt - get the maximum number of local vector table entries 305f62bae50SIngo Molnar */ 306f62bae50SIngo Molnar int lapic_get_maxlvt(void) 307f62bae50SIngo Molnar { 308f62bae50SIngo Molnar unsigned int v; 309f62bae50SIngo Molnar 310f62bae50SIngo Molnar v = apic_read(APIC_LVR); 311f62bae50SIngo Molnar /* 312f62bae50SIngo Molnar * - we always have APIC integrated on 64bit mode 313f62bae50SIngo Molnar * - 82489DXs do not report # of LVT entries 314f62bae50SIngo Molnar */ 315f62bae50SIngo Molnar return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; 316f62bae50SIngo Molnar } 317f62bae50SIngo Molnar 318f62bae50SIngo Molnar /* 319f62bae50SIngo Molnar * Local APIC timer 320f62bae50SIngo Molnar */ 321f62bae50SIngo Molnar 322f62bae50SIngo Molnar /* Clock divisor */ 323f62bae50SIngo Molnar #define APIC_DIVISOR 16 324279f1461SSuresh Siddha #define TSC_DIVISOR 32 325f62bae50SIngo Molnar 326f62bae50SIngo Molnar /* 327f62bae50SIngo Molnar * This function sets up the local APIC timer, with a timeout of 328f62bae50SIngo Molnar * 'clocks' APIC bus clock. During calibration we actually call 329f62bae50SIngo Molnar * this function twice on the boot CPU, once with a bogus timeout 330f62bae50SIngo Molnar * value, second time for real. The other (noncalibrating) CPUs 331f62bae50SIngo Molnar * call this function only once, with the real, calibrated value. 332f62bae50SIngo Molnar * 333f62bae50SIngo Molnar * We do reads before writes even if unnecessary, to get around the 334f62bae50SIngo Molnar * P5 APIC double write bug. 335f62bae50SIngo Molnar */ 336f62bae50SIngo Molnar static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 337f62bae50SIngo Molnar { 338f62bae50SIngo Molnar unsigned int lvtt_value, tmp_value; 339f62bae50SIngo Molnar 340f62bae50SIngo Molnar lvtt_value = LOCAL_TIMER_VECTOR; 341f62bae50SIngo Molnar if (!oneshot) 342f62bae50SIngo Molnar lvtt_value |= APIC_LVT_TIMER_PERIODIC; 343279f1461SSuresh Siddha else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 344279f1461SSuresh Siddha lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; 345279f1461SSuresh Siddha 346f62bae50SIngo Molnar if (!lapic_is_integrated()) 347f62bae50SIngo Molnar lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 348f62bae50SIngo Molnar 349f62bae50SIngo Molnar if (!irqen) 350f62bae50SIngo Molnar lvtt_value |= APIC_LVT_MASKED; 351f62bae50SIngo Molnar 352f62bae50SIngo Molnar apic_write(APIC_LVTT, lvtt_value); 353f62bae50SIngo Molnar 354279f1461SSuresh Siddha if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { 355279f1461SSuresh Siddha printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); 356279f1461SSuresh Siddha return; 357279f1461SSuresh Siddha } 358279f1461SSuresh Siddha 359f62bae50SIngo Molnar /* 360f62bae50SIngo Molnar * Divide PICLK by 16 361f62bae50SIngo Molnar */ 362f62bae50SIngo Molnar tmp_value = apic_read(APIC_TDCR); 363f62bae50SIngo Molnar apic_write(APIC_TDCR, 364f62bae50SIngo Molnar (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 365f62bae50SIngo Molnar APIC_TDR_DIV_16); 366f62bae50SIngo Molnar 367f62bae50SIngo Molnar if (!oneshot) 368f62bae50SIngo Molnar apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 369f62bae50SIngo Molnar } 370f62bae50SIngo Molnar 371f62bae50SIngo Molnar /* 372a68c439bSRobert Richter * Setup extended LVT, AMD specific 373f62bae50SIngo Molnar * 374a68c439bSRobert Richter * Software should use the LVT offsets the BIOS provides. The offsets 375a68c439bSRobert Richter * are determined by the subsystems using it like those for MCE 376a68c439bSRobert Richter * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 377a68c439bSRobert Richter * are supported. Beginning with family 10h at least 4 offsets are 378a68c439bSRobert Richter * available. 379f62bae50SIngo Molnar * 380a68c439bSRobert Richter * Since the offsets must be consistent for all cores, we keep track 381a68c439bSRobert Richter * of the LVT offsets in software and reserve the offset for the same 382a68c439bSRobert Richter * vector also to be used on other cores. An offset is freed by 383a68c439bSRobert Richter * setting the entry to APIC_EILVT_MASKED. 384a68c439bSRobert Richter * 385a68c439bSRobert Richter * If the BIOS is right, there should be no conflicts. Otherwise a 386a68c439bSRobert Richter * "[Firmware Bug]: ..." error message is generated. However, if 387a68c439bSRobert Richter * software does not properly determines the offsets, it is not 388a68c439bSRobert Richter * necessarily a BIOS bug. 389f62bae50SIngo Molnar */ 390f62bae50SIngo Molnar 391a68c439bSRobert Richter static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 392f62bae50SIngo Molnar 393a68c439bSRobert Richter static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 394a68c439bSRobert Richter { 395a68c439bSRobert Richter return (old & APIC_EILVT_MASKED) 396a68c439bSRobert Richter || (new == APIC_EILVT_MASKED) 397a68c439bSRobert Richter || ((new & ~APIC_EILVT_MASKED) == old); 398a68c439bSRobert Richter } 399a68c439bSRobert Richter 400a68c439bSRobert Richter static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 401a68c439bSRobert Richter { 4028abc3122SRobert Richter unsigned int rsvd, vector; 403a68c439bSRobert Richter 404a68c439bSRobert Richter if (offset >= APIC_EILVT_NR_MAX) 405a68c439bSRobert Richter return ~0; 406a68c439bSRobert Richter 4078abc3122SRobert Richter rsvd = atomic_read(&eilvt_offsets[offset]); 408a68c439bSRobert Richter do { 4098abc3122SRobert Richter vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ 4108abc3122SRobert Richter if (vector && !eilvt_entry_is_changeable(vector, new)) 411a68c439bSRobert Richter /* may not change if vectors are different */ 412a68c439bSRobert Richter return rsvd; 413a68c439bSRobert Richter rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 414a68c439bSRobert Richter } while (rsvd != new); 415a68c439bSRobert Richter 4168abc3122SRobert Richter rsvd &= ~APIC_EILVT_MASKED; 4178abc3122SRobert Richter if (rsvd && rsvd != vector) 4188abc3122SRobert Richter pr_info("LVT offset %d assigned for vector 0x%02x\n", 4198abc3122SRobert Richter offset, rsvd); 4208abc3122SRobert Richter 421a68c439bSRobert Richter return new; 422a68c439bSRobert Richter } 423a68c439bSRobert Richter 424a68c439bSRobert Richter /* 425a68c439bSRobert Richter * If mask=1, the LVT entry does not generate interrupts while mask=0 426cbf74ceaSRobert Richter * enables the vector. See also the BKDGs. Must be called with 427cbf74ceaSRobert Richter * preemption disabled. 428a68c439bSRobert Richter */ 429a68c439bSRobert Richter 43027afdf20SRobert Richter int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 431a68c439bSRobert Richter { 432a68c439bSRobert Richter unsigned long reg = APIC_EILVTn(offset); 433a68c439bSRobert Richter unsigned int new, old, reserved; 434a68c439bSRobert Richter 435a68c439bSRobert Richter new = (mask << 16) | (msg_type << 8) | vector; 436a68c439bSRobert Richter old = apic_read(reg); 437a68c439bSRobert Richter reserved = reserve_eilvt_offset(offset, new); 438a68c439bSRobert Richter 439a68c439bSRobert Richter if (reserved != new) { 440eb48c9cbSRobert Richter pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 441eb48c9cbSRobert Richter "vector 0x%x, but the register is already in use for " 442eb48c9cbSRobert Richter "vector 0x%x on another cpu\n", 443eb48c9cbSRobert Richter smp_processor_id(), reg, offset, new, reserved); 444a68c439bSRobert Richter return -EINVAL; 445a68c439bSRobert Richter } 446a68c439bSRobert Richter 447a68c439bSRobert Richter if (!eilvt_entry_is_changeable(old, new)) { 448eb48c9cbSRobert Richter pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 449eb48c9cbSRobert Richter "vector 0x%x, but the register is already in use for " 450eb48c9cbSRobert Richter "vector 0x%x on this cpu\n", 451eb48c9cbSRobert Richter smp_processor_id(), reg, offset, new, old); 452a68c439bSRobert Richter return -EBUSY; 453a68c439bSRobert Richter } 454a68c439bSRobert Richter 455a68c439bSRobert Richter apic_write(reg, new); 456a68c439bSRobert Richter 457a68c439bSRobert Richter return 0; 458f62bae50SIngo Molnar } 45927afdf20SRobert Richter EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 460f62bae50SIngo Molnar 461f62bae50SIngo Molnar /* 462f62bae50SIngo Molnar * Program the next event, relative to now 463f62bae50SIngo Molnar */ 464f62bae50SIngo Molnar static int lapic_next_event(unsigned long delta, 465f62bae50SIngo Molnar struct clock_event_device *evt) 466f62bae50SIngo Molnar { 467f62bae50SIngo Molnar apic_write(APIC_TMICT, delta); 468f62bae50SIngo Molnar return 0; 469f62bae50SIngo Molnar } 470f62bae50SIngo Molnar 471279f1461SSuresh Siddha static int lapic_next_deadline(unsigned long delta, 472279f1461SSuresh Siddha struct clock_event_device *evt) 473279f1461SSuresh Siddha { 474279f1461SSuresh Siddha u64 tsc; 475279f1461SSuresh Siddha 476279f1461SSuresh Siddha rdtscll(tsc); 477279f1461SSuresh Siddha wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); 478279f1461SSuresh Siddha return 0; 479279f1461SSuresh Siddha } 480279f1461SSuresh Siddha 481f62bae50SIngo Molnar /* 482f62bae50SIngo Molnar * Setup the lapic timer in periodic or oneshot mode 483f62bae50SIngo Molnar */ 484f62bae50SIngo Molnar static void lapic_timer_setup(enum clock_event_mode mode, 485f62bae50SIngo Molnar struct clock_event_device *evt) 486f62bae50SIngo Molnar { 487f62bae50SIngo Molnar unsigned long flags; 488f62bae50SIngo Molnar unsigned int v; 489f62bae50SIngo Molnar 490f62bae50SIngo Molnar /* Lapic used as dummy for broadcast ? */ 491f62bae50SIngo Molnar if (evt->features & CLOCK_EVT_FEAT_DUMMY) 492f62bae50SIngo Molnar return; 493f62bae50SIngo Molnar 494f62bae50SIngo Molnar local_irq_save(flags); 495f62bae50SIngo Molnar 496f62bae50SIngo Molnar switch (mode) { 497f62bae50SIngo Molnar case CLOCK_EVT_MODE_PERIODIC: 498f62bae50SIngo Molnar case CLOCK_EVT_MODE_ONESHOT: 4991ade93efSJacob Pan __setup_APIC_LVTT(lapic_timer_frequency, 500f62bae50SIngo Molnar mode != CLOCK_EVT_MODE_PERIODIC, 1); 501f62bae50SIngo Molnar break; 502f62bae50SIngo Molnar case CLOCK_EVT_MODE_UNUSED: 503f62bae50SIngo Molnar case CLOCK_EVT_MODE_SHUTDOWN: 504f62bae50SIngo Molnar v = apic_read(APIC_LVTT); 505f62bae50SIngo Molnar v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 506f62bae50SIngo Molnar apic_write(APIC_LVTT, v); 5076f9b4100SAndreas Herrmann apic_write(APIC_TMICT, 0); 508f62bae50SIngo Molnar break; 509f62bae50SIngo Molnar case CLOCK_EVT_MODE_RESUME: 510f62bae50SIngo Molnar /* Nothing to do here */ 511f62bae50SIngo Molnar break; 512f62bae50SIngo Molnar } 513f62bae50SIngo Molnar 514f62bae50SIngo Molnar local_irq_restore(flags); 515f62bae50SIngo Molnar } 516f62bae50SIngo Molnar 517f62bae50SIngo Molnar /* 518f62bae50SIngo Molnar * Local APIC timer broadcast function 519f62bae50SIngo Molnar */ 520f62bae50SIngo Molnar static void lapic_timer_broadcast(const struct cpumask *mask) 521f62bae50SIngo Molnar { 522f62bae50SIngo Molnar #ifdef CONFIG_SMP 523f62bae50SIngo Molnar apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 524f62bae50SIngo Molnar #endif 525f62bae50SIngo Molnar } 526f62bae50SIngo Molnar 52725874a29SHenrik Kretzschmar 52825874a29SHenrik Kretzschmar /* 52925874a29SHenrik Kretzschmar * The local apic timer can be used for any function which is CPU local. 53025874a29SHenrik Kretzschmar */ 53125874a29SHenrik Kretzschmar static struct clock_event_device lapic_clockevent = { 53225874a29SHenrik Kretzschmar .name = "lapic", 53325874a29SHenrik Kretzschmar .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT 53425874a29SHenrik Kretzschmar | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, 53525874a29SHenrik Kretzschmar .shift = 32, 53625874a29SHenrik Kretzschmar .set_mode = lapic_timer_setup, 53725874a29SHenrik Kretzschmar .set_next_event = lapic_next_event, 53825874a29SHenrik Kretzschmar .broadcast = lapic_timer_broadcast, 53925874a29SHenrik Kretzschmar .rating = 100, 54025874a29SHenrik Kretzschmar .irq = -1, 54125874a29SHenrik Kretzschmar }; 54225874a29SHenrik Kretzschmar static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 54325874a29SHenrik Kretzschmar 544f62bae50SIngo Molnar /* 545421f91d2SUwe Kleine-König * Setup the local APIC timer for this CPU. Copy the initialized values 546f62bae50SIngo Molnar * of the boot CPU and register the clock event in the framework. 547f62bae50SIngo Molnar */ 548148f9bb8SPaul Gortmaker static void setup_APIC_timer(void) 549f62bae50SIngo Molnar { 550f62bae50SIngo Molnar struct clock_event_device *levt = &__get_cpu_var(lapic_events); 551f62bae50SIngo Molnar 552349c004eSChristoph Lameter if (this_cpu_has(X86_FEATURE_ARAT)) { 553db954b58SVenkatesh Pallipadi lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 554db954b58SVenkatesh Pallipadi /* Make LAPIC timer preferrable over percpu HPET */ 555db954b58SVenkatesh Pallipadi lapic_clockevent.rating = 150; 556db954b58SVenkatesh Pallipadi } 557db954b58SVenkatesh Pallipadi 558f62bae50SIngo Molnar memcpy(levt, &lapic_clockevent, sizeof(*levt)); 559f62bae50SIngo Molnar levt->cpumask = cpumask_of(smp_processor_id()); 560f62bae50SIngo Molnar 561279f1461SSuresh Siddha if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 562279f1461SSuresh Siddha levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | 563279f1461SSuresh Siddha CLOCK_EVT_FEAT_DUMMY); 564279f1461SSuresh Siddha levt->set_next_event = lapic_next_deadline; 565279f1461SSuresh Siddha clockevents_config_and_register(levt, 566279f1461SSuresh Siddha (tsc_khz / TSC_DIVISOR) * 1000, 567279f1461SSuresh Siddha 0xF, ~0UL); 568279f1461SSuresh Siddha } else 569f62bae50SIngo Molnar clockevents_register_device(levt); 570f62bae50SIngo Molnar } 571f62bae50SIngo Molnar 572f62bae50SIngo Molnar /* 573f62bae50SIngo Molnar * In this functions we calibrate APIC bus clocks to the external timer. 574f62bae50SIngo Molnar * 575f62bae50SIngo Molnar * We want to do the calibration only once since we want to have local timer 576f62bae50SIngo Molnar * irqs syncron. CPUs connected by the same APIC bus have the very same bus 577f62bae50SIngo Molnar * frequency. 578f62bae50SIngo Molnar * 579f62bae50SIngo Molnar * This was previously done by reading the PIT/HPET and waiting for a wrap 580f62bae50SIngo Molnar * around to find out, that a tick has elapsed. I have a box, where the PIT 581f62bae50SIngo Molnar * readout is broken, so it never gets out of the wait loop again. This was 582f62bae50SIngo Molnar * also reported by others. 583f62bae50SIngo Molnar * 584f62bae50SIngo Molnar * Monitoring the jiffies value is inaccurate and the clockevents 585f62bae50SIngo Molnar * infrastructure allows us to do a simple substitution of the interrupt 586f62bae50SIngo Molnar * handler. 587f62bae50SIngo Molnar * 588f62bae50SIngo Molnar * The calibration routine also uses the pm_timer when possible, as the PIT 589f62bae50SIngo Molnar * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 590f62bae50SIngo Molnar * back to normal later in the boot process). 591f62bae50SIngo Molnar */ 592f62bae50SIngo Molnar 593f62bae50SIngo Molnar #define LAPIC_CAL_LOOPS (HZ/10) 594f62bae50SIngo Molnar 595f62bae50SIngo Molnar static __initdata int lapic_cal_loops = -1; 596f62bae50SIngo Molnar static __initdata long lapic_cal_t1, lapic_cal_t2; 597f62bae50SIngo Molnar static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 598f62bae50SIngo Molnar static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 599f62bae50SIngo Molnar static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 600f62bae50SIngo Molnar 601f62bae50SIngo Molnar /* 602f62bae50SIngo Molnar * Temporary interrupt handler. 603f62bae50SIngo Molnar */ 604f62bae50SIngo Molnar static void __init lapic_cal_handler(struct clock_event_device *dev) 605f62bae50SIngo Molnar { 606f62bae50SIngo Molnar unsigned long long tsc = 0; 607f62bae50SIngo Molnar long tapic = apic_read(APIC_TMCCT); 608f62bae50SIngo Molnar unsigned long pm = acpi_pm_read_early(); 609f62bae50SIngo Molnar 610f62bae50SIngo Molnar if (cpu_has_tsc) 611f62bae50SIngo Molnar rdtscll(tsc); 612f62bae50SIngo Molnar 613f62bae50SIngo Molnar switch (lapic_cal_loops++) { 614f62bae50SIngo Molnar case 0: 615f62bae50SIngo Molnar lapic_cal_t1 = tapic; 616f62bae50SIngo Molnar lapic_cal_tsc1 = tsc; 617f62bae50SIngo Molnar lapic_cal_pm1 = pm; 618f62bae50SIngo Molnar lapic_cal_j1 = jiffies; 619f62bae50SIngo Molnar break; 620f62bae50SIngo Molnar 621f62bae50SIngo Molnar case LAPIC_CAL_LOOPS: 622f62bae50SIngo Molnar lapic_cal_t2 = tapic; 623f62bae50SIngo Molnar lapic_cal_tsc2 = tsc; 624f62bae50SIngo Molnar if (pm < lapic_cal_pm1) 625f62bae50SIngo Molnar pm += ACPI_PM_OVRRUN; 626f62bae50SIngo Molnar lapic_cal_pm2 = pm; 627f62bae50SIngo Molnar lapic_cal_j2 = jiffies; 628f62bae50SIngo Molnar break; 629f62bae50SIngo Molnar } 630f62bae50SIngo Molnar } 631f62bae50SIngo Molnar 632f62bae50SIngo Molnar static int __init 633f62bae50SIngo Molnar calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 634f62bae50SIngo Molnar { 635f62bae50SIngo Molnar const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 636f62bae50SIngo Molnar const long pm_thresh = pm_100ms / 100; 637f62bae50SIngo Molnar unsigned long mult; 638f62bae50SIngo Molnar u64 res; 639f62bae50SIngo Molnar 640f62bae50SIngo Molnar #ifndef CONFIG_X86_PM_TIMER 641f62bae50SIngo Molnar return -1; 642f62bae50SIngo Molnar #endif 643f62bae50SIngo Molnar 644f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 645f62bae50SIngo Molnar 646f62bae50SIngo Molnar /* Check, if the PM timer is available */ 647f62bae50SIngo Molnar if (!deltapm) 648f62bae50SIngo Molnar return -1; 649f62bae50SIngo Molnar 650f62bae50SIngo Molnar mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 651f62bae50SIngo Molnar 652f62bae50SIngo Molnar if (deltapm > (pm_100ms - pm_thresh) && 653f62bae50SIngo Molnar deltapm < (pm_100ms + pm_thresh)) { 654f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 655f62bae50SIngo Molnar return 0; 656f62bae50SIngo Molnar } 657f62bae50SIngo Molnar 658f62bae50SIngo Molnar res = (((u64)deltapm) * mult) >> 22; 659f62bae50SIngo Molnar do_div(res, 1000000); 660f62bae50SIngo Molnar pr_warning("APIC calibration not consistent " 661f62bae50SIngo Molnar "with PM-Timer: %ldms instead of 100ms\n",(long)res); 662f62bae50SIngo Molnar 663f62bae50SIngo Molnar /* Correct the lapic counter value */ 664f62bae50SIngo Molnar res = (((u64)(*delta)) * pm_100ms); 665f62bae50SIngo Molnar do_div(res, deltapm); 666f62bae50SIngo Molnar pr_info("APIC delta adjusted to PM-Timer: " 667f62bae50SIngo Molnar "%lu (%ld)\n", (unsigned long)res, *delta); 668f62bae50SIngo Molnar *delta = (long)res; 669f62bae50SIngo Molnar 670f62bae50SIngo Molnar /* Correct the tsc counter value */ 671f62bae50SIngo Molnar if (cpu_has_tsc) { 672f62bae50SIngo Molnar res = (((u64)(*deltatsc)) * pm_100ms); 673f62bae50SIngo Molnar do_div(res, deltapm); 674f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 675f62bae50SIngo Molnar "PM-Timer: %lu (%ld)\n", 676f62bae50SIngo Molnar (unsigned long)res, *deltatsc); 677f62bae50SIngo Molnar *deltatsc = (long)res; 678f62bae50SIngo Molnar } 679f62bae50SIngo Molnar 680f62bae50SIngo Molnar return 0; 681f62bae50SIngo Molnar } 682f62bae50SIngo Molnar 683f62bae50SIngo Molnar static int __init calibrate_APIC_clock(void) 684f62bae50SIngo Molnar { 685f62bae50SIngo Molnar struct clock_event_device *levt = &__get_cpu_var(lapic_events); 686f62bae50SIngo Molnar void (*real_handler)(struct clock_event_device *dev); 687f62bae50SIngo Molnar unsigned long deltaj; 688f62bae50SIngo Molnar long delta, deltatsc; 689f62bae50SIngo Molnar int pm_referenced = 0; 690f62bae50SIngo Molnar 6911ade93efSJacob Pan /** 6921ade93efSJacob Pan * check if lapic timer has already been calibrated by platform 6931ade93efSJacob Pan * specific routine, such as tsc calibration code. if so, we just fill 6941ade93efSJacob Pan * in the clockevent structure and return. 6951ade93efSJacob Pan */ 6961ade93efSJacob Pan 697279f1461SSuresh Siddha if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 698279f1461SSuresh Siddha return 0; 699279f1461SSuresh Siddha } else if (lapic_timer_frequency) { 7001ade93efSJacob Pan apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", 7011ade93efSJacob Pan lapic_timer_frequency); 7021ade93efSJacob Pan lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR, 7031ade93efSJacob Pan TICK_NSEC, lapic_clockevent.shift); 7041ade93efSJacob Pan lapic_clockevent.max_delta_ns = 7051ade93efSJacob Pan clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); 7061ade93efSJacob Pan lapic_clockevent.min_delta_ns = 7071ade93efSJacob Pan clockevent_delta2ns(0xF, &lapic_clockevent); 7081ade93efSJacob Pan lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 7091ade93efSJacob Pan return 0; 7101ade93efSJacob Pan } 7111ade93efSJacob Pan 712279f1461SSuresh Siddha apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 713279f1461SSuresh Siddha "calibrating APIC timer ...\n"); 714279f1461SSuresh Siddha 715f62bae50SIngo Molnar local_irq_disable(); 716f62bae50SIngo Molnar 717f62bae50SIngo Molnar /* Replace the global interrupt handler */ 718f62bae50SIngo Molnar real_handler = global_clock_event->event_handler; 719f62bae50SIngo Molnar global_clock_event->event_handler = lapic_cal_handler; 720f62bae50SIngo Molnar 721f62bae50SIngo Molnar /* 722f62bae50SIngo Molnar * Setup the APIC counter to maximum. There is no way the lapic 723f62bae50SIngo Molnar * can underflow in the 100ms detection time frame 724f62bae50SIngo Molnar */ 725f62bae50SIngo Molnar __setup_APIC_LVTT(0xffffffff, 0, 0); 726f62bae50SIngo Molnar 727f62bae50SIngo Molnar /* Let the interrupts run */ 728f62bae50SIngo Molnar local_irq_enable(); 729f62bae50SIngo Molnar 730f62bae50SIngo Molnar while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 731f62bae50SIngo Molnar cpu_relax(); 732f62bae50SIngo Molnar 733f62bae50SIngo Molnar local_irq_disable(); 734f62bae50SIngo Molnar 735f62bae50SIngo Molnar /* Restore the real event handler */ 736f62bae50SIngo Molnar global_clock_event->event_handler = real_handler; 737f62bae50SIngo Molnar 738f62bae50SIngo Molnar /* Build delta t1-t2 as apic timer counts down */ 739f62bae50SIngo Molnar delta = lapic_cal_t1 - lapic_cal_t2; 740f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 741f62bae50SIngo Molnar 742f62bae50SIngo Molnar deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 743f62bae50SIngo Molnar 744f62bae50SIngo Molnar /* we trust the PM based calibration if possible */ 745f62bae50SIngo Molnar pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 746f62bae50SIngo Molnar &delta, &deltatsc); 747f62bae50SIngo Molnar 748f62bae50SIngo Molnar /* Calculate the scaled math multiplication factor */ 749f62bae50SIngo Molnar lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 750f62bae50SIngo Molnar lapic_clockevent.shift); 751f62bae50SIngo Molnar lapic_clockevent.max_delta_ns = 7524aed89d6SPierre Tardy clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 753f62bae50SIngo Molnar lapic_clockevent.min_delta_ns = 754f62bae50SIngo Molnar clockevent_delta2ns(0xF, &lapic_clockevent); 755f62bae50SIngo Molnar 7561ade93efSJacob Pan lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 757f62bae50SIngo Molnar 758f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 759411462f6SThomas Gleixner apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 760f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 7611ade93efSJacob Pan lapic_timer_frequency); 762f62bae50SIngo Molnar 763f62bae50SIngo Molnar if (cpu_has_tsc) { 764f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 765f62bae50SIngo Molnar "%ld.%04ld MHz.\n", 766f62bae50SIngo Molnar (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 767f62bae50SIngo Molnar (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 768f62bae50SIngo Molnar } 769f62bae50SIngo Molnar 770f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 771f62bae50SIngo Molnar "%u.%04u MHz.\n", 7721ade93efSJacob Pan lapic_timer_frequency / (1000000 / HZ), 7731ade93efSJacob Pan lapic_timer_frequency % (1000000 / HZ)); 774f62bae50SIngo Molnar 775f62bae50SIngo Molnar /* 776f62bae50SIngo Molnar * Do a sanity check on the APIC calibration result 777f62bae50SIngo Molnar */ 7781ade93efSJacob Pan if (lapic_timer_frequency < (1000000 / HZ)) { 779f62bae50SIngo Molnar local_irq_enable(); 780f62bae50SIngo Molnar pr_warning("APIC frequency too slow, disabling apic timer\n"); 781f62bae50SIngo Molnar return -1; 782f62bae50SIngo Molnar } 783f62bae50SIngo Molnar 784f62bae50SIngo Molnar levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 785f62bae50SIngo Molnar 786f62bae50SIngo Molnar /* 787f62bae50SIngo Molnar * PM timer calibration failed or not turned on 788f62bae50SIngo Molnar * so lets try APIC timer based calibration 789f62bae50SIngo Molnar */ 790f62bae50SIngo Molnar if (!pm_referenced) { 791f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 792f62bae50SIngo Molnar 793f62bae50SIngo Molnar /* 794f62bae50SIngo Molnar * Setup the apic timer manually 795f62bae50SIngo Molnar */ 796f62bae50SIngo Molnar levt->event_handler = lapic_cal_handler; 797f62bae50SIngo Molnar lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); 798f62bae50SIngo Molnar lapic_cal_loops = -1; 799f62bae50SIngo Molnar 800f62bae50SIngo Molnar /* Let the interrupts run */ 801f62bae50SIngo Molnar local_irq_enable(); 802f62bae50SIngo Molnar 803f62bae50SIngo Molnar while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 804f62bae50SIngo Molnar cpu_relax(); 805f62bae50SIngo Molnar 806f62bae50SIngo Molnar /* Stop the lapic timer */ 807f62bae50SIngo Molnar lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); 808f62bae50SIngo Molnar 809f62bae50SIngo Molnar /* Jiffies delta */ 810f62bae50SIngo Molnar deltaj = lapic_cal_j2 - lapic_cal_j1; 811f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 812f62bae50SIngo Molnar 813f62bae50SIngo Molnar /* Check, if the jiffies result is consistent */ 814f62bae50SIngo Molnar if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 815f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 816f62bae50SIngo Molnar else 817f62bae50SIngo Molnar levt->features |= CLOCK_EVT_FEAT_DUMMY; 818f62bae50SIngo Molnar } else 819f62bae50SIngo Molnar local_irq_enable(); 820f62bae50SIngo Molnar 821f62bae50SIngo Molnar if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 822f62bae50SIngo Molnar pr_warning("APIC timer disabled due to verification failure\n"); 823f62bae50SIngo Molnar return -1; 824f62bae50SIngo Molnar } 825f62bae50SIngo Molnar 826f62bae50SIngo Molnar return 0; 827f62bae50SIngo Molnar } 828f62bae50SIngo Molnar 829f62bae50SIngo Molnar /* 830f62bae50SIngo Molnar * Setup the boot APIC 831f62bae50SIngo Molnar * 832f62bae50SIngo Molnar * Calibrate and verify the result. 833f62bae50SIngo Molnar */ 834f62bae50SIngo Molnar void __init setup_boot_APIC_clock(void) 835f62bae50SIngo Molnar { 836f62bae50SIngo Molnar /* 837f62bae50SIngo Molnar * The local apic timer can be disabled via the kernel 838f62bae50SIngo Molnar * commandline or from the CPU detection code. Register the lapic 839f62bae50SIngo Molnar * timer as a dummy clock event source on SMP systems, so the 840f62bae50SIngo Molnar * broadcast mechanism is used. On UP systems simply ignore it. 841f62bae50SIngo Molnar */ 842f62bae50SIngo Molnar if (disable_apic_timer) { 843f62bae50SIngo Molnar pr_info("Disabling APIC timer\n"); 844f62bae50SIngo Molnar /* No broadcast on UP ! */ 845f62bae50SIngo Molnar if (num_possible_cpus() > 1) { 846f62bae50SIngo Molnar lapic_clockevent.mult = 1; 847f62bae50SIngo Molnar setup_APIC_timer(); 848f62bae50SIngo Molnar } 849f62bae50SIngo Molnar return; 850f62bae50SIngo Molnar } 851f62bae50SIngo Molnar 852f62bae50SIngo Molnar if (calibrate_APIC_clock()) { 853f62bae50SIngo Molnar /* No broadcast on UP ! */ 854f62bae50SIngo Molnar if (num_possible_cpus() > 1) 855f62bae50SIngo Molnar setup_APIC_timer(); 856f62bae50SIngo Molnar return; 857f62bae50SIngo Molnar } 858f62bae50SIngo Molnar 859f62bae50SIngo Molnar /* 860f62bae50SIngo Molnar * If nmi_watchdog is set to IO_APIC, we need the 861f62bae50SIngo Molnar * PIT/HPET going. Otherwise register lapic as a dummy 862f62bae50SIngo Molnar * device. 863f62bae50SIngo Molnar */ 864f62bae50SIngo Molnar lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 865f62bae50SIngo Molnar 866f62bae50SIngo Molnar /* Setup the lapic or request the broadcast */ 867f62bae50SIngo Molnar setup_APIC_timer(); 868f62bae50SIngo Molnar } 869f62bae50SIngo Molnar 870148f9bb8SPaul Gortmaker void setup_secondary_APIC_clock(void) 871f62bae50SIngo Molnar { 872f62bae50SIngo Molnar setup_APIC_timer(); 873f62bae50SIngo Molnar } 874f62bae50SIngo Molnar 875f62bae50SIngo Molnar /* 876f62bae50SIngo Molnar * The guts of the apic timer interrupt 877f62bae50SIngo Molnar */ 878f62bae50SIngo Molnar static void local_apic_timer_interrupt(void) 879f62bae50SIngo Molnar { 880f62bae50SIngo Molnar int cpu = smp_processor_id(); 881f62bae50SIngo Molnar struct clock_event_device *evt = &per_cpu(lapic_events, cpu); 882f62bae50SIngo Molnar 883f62bae50SIngo Molnar /* 884f62bae50SIngo Molnar * Normally we should not be here till LAPIC has been initialized but 885f62bae50SIngo Molnar * in some cases like kdump, its possible that there is a pending LAPIC 886f62bae50SIngo Molnar * timer interrupt from previous kernel's context and is delivered in 887f62bae50SIngo Molnar * new kernel the moment interrupts are enabled. 888f62bae50SIngo Molnar * 889f62bae50SIngo Molnar * Interrupts are enabled early and LAPIC is setup much later, hence 890f62bae50SIngo Molnar * its possible that when we get here evt->event_handler is NULL. 891f62bae50SIngo Molnar * Check for event_handler being NULL and discard the interrupt as 892f62bae50SIngo Molnar * spurious. 893f62bae50SIngo Molnar */ 894f62bae50SIngo Molnar if (!evt->event_handler) { 895f62bae50SIngo Molnar pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); 896f62bae50SIngo Molnar /* Switch it off */ 897f62bae50SIngo Molnar lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); 898f62bae50SIngo Molnar return; 899f62bae50SIngo Molnar } 900f62bae50SIngo Molnar 901f62bae50SIngo Molnar /* 902f62bae50SIngo Molnar * the NMI deadlock-detector uses this. 903f62bae50SIngo Molnar */ 904f62bae50SIngo Molnar inc_irq_stat(apic_timer_irqs); 905f62bae50SIngo Molnar 906f62bae50SIngo Molnar evt->event_handler(evt); 907f62bae50SIngo Molnar } 908f62bae50SIngo Molnar 909f62bae50SIngo Molnar /* 910f62bae50SIngo Molnar * Local APIC timer interrupt. This is the most natural way for doing 911f62bae50SIngo Molnar * local interrupts, but local timer interrupts can be emulated by 912f62bae50SIngo Molnar * broadcast interrupts too. [in case the hw doesn't support APIC timers] 913f62bae50SIngo Molnar * 914f62bae50SIngo Molnar * [ if a single-CPU system runs an SMP kernel then we call the local 915f62bae50SIngo Molnar * interrupt as well. Thus we cannot inline the local irq ... ] 916f62bae50SIngo Molnar */ 9171d9090e2SAndi Kleen __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 918f62bae50SIngo Molnar { 919f62bae50SIngo Molnar struct pt_regs *old_regs = set_irq_regs(regs); 920f62bae50SIngo Molnar 921f62bae50SIngo Molnar /* 922f62bae50SIngo Molnar * NOTE! We'd better ACK the irq immediately, 923f62bae50SIngo Molnar * because timer handling can be slow. 924eddc0e92SSeiji Aguchi * 925f62bae50SIngo Molnar * update_process_times() expects us to have done irq_enter(). 926f62bae50SIngo Molnar * Besides, if we don't timer interrupts ignore the global 927f62bae50SIngo Molnar * interrupt lock, which is the WrongThing (tm) to do. 928f62bae50SIngo Molnar */ 929eddc0e92SSeiji Aguchi entering_ack_irq(); 930f62bae50SIngo Molnar local_apic_timer_interrupt(); 931eddc0e92SSeiji Aguchi exiting_irq(); 932f62bae50SIngo Molnar 933f62bae50SIngo Molnar set_irq_regs(old_regs); 934f62bae50SIngo Molnar } 935f62bae50SIngo Molnar 9361d9090e2SAndi Kleen __visible void __irq_entry smp_trace_apic_timer_interrupt(struct pt_regs *regs) 937cf910e83SSeiji Aguchi { 938cf910e83SSeiji Aguchi struct pt_regs *old_regs = set_irq_regs(regs); 939cf910e83SSeiji Aguchi 940cf910e83SSeiji Aguchi /* 941cf910e83SSeiji Aguchi * NOTE! We'd better ACK the irq immediately, 942cf910e83SSeiji Aguchi * because timer handling can be slow. 943cf910e83SSeiji Aguchi * 944cf910e83SSeiji Aguchi * update_process_times() expects us to have done irq_enter(). 945cf910e83SSeiji Aguchi * Besides, if we don't timer interrupts ignore the global 946cf910e83SSeiji Aguchi * interrupt lock, which is the WrongThing (tm) to do. 947cf910e83SSeiji Aguchi */ 948cf910e83SSeiji Aguchi entering_ack_irq(); 949cf910e83SSeiji Aguchi trace_local_timer_entry(LOCAL_TIMER_VECTOR); 950cf910e83SSeiji Aguchi local_apic_timer_interrupt(); 951cf910e83SSeiji Aguchi trace_local_timer_exit(LOCAL_TIMER_VECTOR); 952cf910e83SSeiji Aguchi exiting_irq(); 953f62bae50SIngo Molnar 954f62bae50SIngo Molnar set_irq_regs(old_regs); 955f62bae50SIngo Molnar } 956f62bae50SIngo Molnar 957f62bae50SIngo Molnar int setup_profiling_timer(unsigned int multiplier) 958f62bae50SIngo Molnar { 959f62bae50SIngo Molnar return -EINVAL; 960f62bae50SIngo Molnar } 961f62bae50SIngo Molnar 962f62bae50SIngo Molnar /* 963f62bae50SIngo Molnar * Local APIC start and shutdown 964f62bae50SIngo Molnar */ 965f62bae50SIngo Molnar 966f62bae50SIngo Molnar /** 967f62bae50SIngo Molnar * clear_local_APIC - shutdown the local APIC 968f62bae50SIngo Molnar * 969f62bae50SIngo Molnar * This is called, when a CPU is disabled and before rebooting, so the state of 970f62bae50SIngo Molnar * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 971f62bae50SIngo Molnar * leftovers during boot. 972f62bae50SIngo Molnar */ 973f62bae50SIngo Molnar void clear_local_APIC(void) 974f62bae50SIngo Molnar { 975f62bae50SIngo Molnar int maxlvt; 976f62bae50SIngo Molnar u32 v; 977f62bae50SIngo Molnar 978f62bae50SIngo Molnar /* APIC hasn't been mapped yet */ 979fc1edaf9SSuresh Siddha if (!x2apic_mode && !apic_phys) 980f62bae50SIngo Molnar return; 981f62bae50SIngo Molnar 982f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 983f62bae50SIngo Molnar /* 984f62bae50SIngo Molnar * Masking an LVT entry can trigger a local APIC error 985f62bae50SIngo Molnar * if the vector is zero. Mask LVTERR first to prevent this. 986f62bae50SIngo Molnar */ 987f62bae50SIngo Molnar if (maxlvt >= 3) { 988f62bae50SIngo Molnar v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 989f62bae50SIngo Molnar apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 990f62bae50SIngo Molnar } 991f62bae50SIngo Molnar /* 992f62bae50SIngo Molnar * Careful: we have to set masks only first to deassert 993f62bae50SIngo Molnar * any level-triggered sources. 994f62bae50SIngo Molnar */ 995f62bae50SIngo Molnar v = apic_read(APIC_LVTT); 996f62bae50SIngo Molnar apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 997f62bae50SIngo Molnar v = apic_read(APIC_LVT0); 998f62bae50SIngo Molnar apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 999f62bae50SIngo Molnar v = apic_read(APIC_LVT1); 1000f62bae50SIngo Molnar apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 1001f62bae50SIngo Molnar if (maxlvt >= 4) { 1002f62bae50SIngo Molnar v = apic_read(APIC_LVTPC); 1003f62bae50SIngo Molnar apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 1004f62bae50SIngo Molnar } 1005f62bae50SIngo Molnar 1006f62bae50SIngo Molnar /* lets not touch this if we didn't frob it */ 10074efc0670SAndi Kleen #ifdef CONFIG_X86_THERMAL_VECTOR 1008f62bae50SIngo Molnar if (maxlvt >= 5) { 1009f62bae50SIngo Molnar v = apic_read(APIC_LVTTHMR); 1010f62bae50SIngo Molnar apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 1011f62bae50SIngo Molnar } 1012f62bae50SIngo Molnar #endif 1013638bee71SH. Peter Anvin #ifdef CONFIG_X86_MCE_INTEL 1014638bee71SH. Peter Anvin if (maxlvt >= 6) { 1015638bee71SH. Peter Anvin v = apic_read(APIC_LVTCMCI); 1016638bee71SH. Peter Anvin if (!(v & APIC_LVT_MASKED)) 1017638bee71SH. Peter Anvin apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 1018638bee71SH. Peter Anvin } 1019638bee71SH. Peter Anvin #endif 1020638bee71SH. Peter Anvin 1021f62bae50SIngo Molnar /* 1022f62bae50SIngo Molnar * Clean APIC state for other OSs: 1023f62bae50SIngo Molnar */ 1024f62bae50SIngo Molnar apic_write(APIC_LVTT, APIC_LVT_MASKED); 1025f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_LVT_MASKED); 1026f62bae50SIngo Molnar apic_write(APIC_LVT1, APIC_LVT_MASKED); 1027f62bae50SIngo Molnar if (maxlvt >= 3) 1028f62bae50SIngo Molnar apic_write(APIC_LVTERR, APIC_LVT_MASKED); 1029f62bae50SIngo Molnar if (maxlvt >= 4) 1030f62bae50SIngo Molnar apic_write(APIC_LVTPC, APIC_LVT_MASKED); 1031f62bae50SIngo Molnar 1032f62bae50SIngo Molnar /* Integrated APIC (!82489DX) ? */ 1033f62bae50SIngo Molnar if (lapic_is_integrated()) { 1034f62bae50SIngo Molnar if (maxlvt > 3) 1035f62bae50SIngo Molnar /* Clear ESR due to Pentium errata 3AP and 11AP */ 1036f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1037f62bae50SIngo Molnar apic_read(APIC_ESR); 1038f62bae50SIngo Molnar } 1039f62bae50SIngo Molnar } 1040f62bae50SIngo Molnar 1041f62bae50SIngo Molnar /** 1042f62bae50SIngo Molnar * disable_local_APIC - clear and disable the local APIC 1043f62bae50SIngo Molnar */ 1044f62bae50SIngo Molnar void disable_local_APIC(void) 1045f62bae50SIngo Molnar { 1046f62bae50SIngo Molnar unsigned int value; 1047f62bae50SIngo Molnar 1048f62bae50SIngo Molnar /* APIC hasn't been mapped yet */ 1049fd19dce7SYinghai Lu if (!x2apic_mode && !apic_phys) 1050f62bae50SIngo Molnar return; 1051f62bae50SIngo Molnar 1052f62bae50SIngo Molnar clear_local_APIC(); 1053f62bae50SIngo Molnar 1054f62bae50SIngo Molnar /* 1055f62bae50SIngo Molnar * Disable APIC (implies clearing of registers 1056f62bae50SIngo Molnar * for 82489DX!). 1057f62bae50SIngo Molnar */ 1058f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 1059f62bae50SIngo Molnar value &= ~APIC_SPIV_APIC_ENABLED; 1060f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 1061f62bae50SIngo Molnar 1062f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1063f62bae50SIngo Molnar /* 1064f62bae50SIngo Molnar * When LAPIC was disabled by the BIOS and enabled by the kernel, 1065f62bae50SIngo Molnar * restore the disabled state. 1066f62bae50SIngo Molnar */ 1067f62bae50SIngo Molnar if (enabled_via_apicbase) { 1068f62bae50SIngo Molnar unsigned int l, h; 1069f62bae50SIngo Molnar 1070f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, l, h); 1071f62bae50SIngo Molnar l &= ~MSR_IA32_APICBASE_ENABLE; 1072f62bae50SIngo Molnar wrmsr(MSR_IA32_APICBASE, l, h); 1073f62bae50SIngo Molnar } 1074f62bae50SIngo Molnar #endif 1075f62bae50SIngo Molnar } 1076f62bae50SIngo Molnar 1077f62bae50SIngo Molnar /* 1078f62bae50SIngo Molnar * If Linux enabled the LAPIC against the BIOS default disable it down before 1079f62bae50SIngo Molnar * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 1080f62bae50SIngo Molnar * not power-off. Additionally clear all LVT entries before disable_local_APIC 1081f62bae50SIngo Molnar * for the case where Linux didn't enable the LAPIC. 1082f62bae50SIngo Molnar */ 1083f62bae50SIngo Molnar void lapic_shutdown(void) 1084f62bae50SIngo Molnar { 1085f62bae50SIngo Molnar unsigned long flags; 1086f62bae50SIngo Molnar 10878312136fSCyrill Gorcunov if (!cpu_has_apic && !apic_from_smp_config()) 1088f62bae50SIngo Molnar return; 1089f62bae50SIngo Molnar 1090f62bae50SIngo Molnar local_irq_save(flags); 1091f62bae50SIngo Molnar 1092f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1093f62bae50SIngo Molnar if (!enabled_via_apicbase) 1094f62bae50SIngo Molnar clear_local_APIC(); 1095f62bae50SIngo Molnar else 1096f62bae50SIngo Molnar #endif 1097f62bae50SIngo Molnar disable_local_APIC(); 1098f62bae50SIngo Molnar 1099f62bae50SIngo Molnar 1100f62bae50SIngo Molnar local_irq_restore(flags); 1101f62bae50SIngo Molnar } 1102f62bae50SIngo Molnar 1103f62bae50SIngo Molnar /* 1104f62bae50SIngo Molnar * This is to verify that we're looking at a real local APIC. 1105f62bae50SIngo Molnar * Check these against your board if the CPUs aren't getting 1106f62bae50SIngo Molnar * started for no apparent reason. 1107f62bae50SIngo Molnar */ 1108f62bae50SIngo Molnar int __init verify_local_APIC(void) 1109f62bae50SIngo Molnar { 1110f62bae50SIngo Molnar unsigned int reg0, reg1; 1111f62bae50SIngo Molnar 1112f62bae50SIngo Molnar /* 1113f62bae50SIngo Molnar * The version register is read-only in a real APIC. 1114f62bae50SIngo Molnar */ 1115f62bae50SIngo Molnar reg0 = apic_read(APIC_LVR); 1116f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); 1117f62bae50SIngo Molnar apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); 1118f62bae50SIngo Molnar reg1 = apic_read(APIC_LVR); 1119f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); 1120f62bae50SIngo Molnar 1121f62bae50SIngo Molnar /* 1122f62bae50SIngo Molnar * The two version reads above should print the same 1123f62bae50SIngo Molnar * numbers. If the second one is different, then we 1124f62bae50SIngo Molnar * poke at a non-APIC. 1125f62bae50SIngo Molnar */ 1126f62bae50SIngo Molnar if (reg1 != reg0) 1127f62bae50SIngo Molnar return 0; 1128f62bae50SIngo Molnar 1129f62bae50SIngo Molnar /* 1130f62bae50SIngo Molnar * Check if the version looks reasonably. 1131f62bae50SIngo Molnar */ 1132f62bae50SIngo Molnar reg1 = GET_APIC_VERSION(reg0); 1133f62bae50SIngo Molnar if (reg1 == 0x00 || reg1 == 0xff) 1134f62bae50SIngo Molnar return 0; 1135f62bae50SIngo Molnar reg1 = lapic_get_maxlvt(); 1136f62bae50SIngo Molnar if (reg1 < 0x02 || reg1 == 0xff) 1137f62bae50SIngo Molnar return 0; 1138f62bae50SIngo Molnar 1139f62bae50SIngo Molnar /* 1140f62bae50SIngo Molnar * The ID register is read/write in a real APIC. 1141f62bae50SIngo Molnar */ 1142f62bae50SIngo Molnar reg0 = apic_read(APIC_ID); 1143f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); 1144f62bae50SIngo Molnar apic_write(APIC_ID, reg0 ^ apic->apic_id_mask); 1145f62bae50SIngo Molnar reg1 = apic_read(APIC_ID); 1146f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); 1147f62bae50SIngo Molnar apic_write(APIC_ID, reg0); 1148f62bae50SIngo Molnar if (reg1 != (reg0 ^ apic->apic_id_mask)) 1149f62bae50SIngo Molnar return 0; 1150f62bae50SIngo Molnar 1151f62bae50SIngo Molnar /* 1152f62bae50SIngo Molnar * The next two are just to see if we have sane values. 1153f62bae50SIngo Molnar * They're only really relevant if we're in Virtual Wire 1154f62bae50SIngo Molnar * compatibility mode, but most boxes are anymore. 1155f62bae50SIngo Molnar */ 1156f62bae50SIngo Molnar reg0 = apic_read(APIC_LVT0); 1157f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); 1158f62bae50SIngo Molnar reg1 = apic_read(APIC_LVT1); 1159f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); 1160f62bae50SIngo Molnar 1161f62bae50SIngo Molnar return 1; 1162f62bae50SIngo Molnar } 1163f62bae50SIngo Molnar 1164f62bae50SIngo Molnar /** 1165f62bae50SIngo Molnar * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1166f62bae50SIngo Molnar */ 1167f62bae50SIngo Molnar void __init sync_Arb_IDs(void) 1168f62bae50SIngo Molnar { 1169f62bae50SIngo Molnar /* 1170f62bae50SIngo Molnar * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1171f62bae50SIngo Molnar * needed on AMD. 1172f62bae50SIngo Molnar */ 1173f62bae50SIngo Molnar if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1174f62bae50SIngo Molnar return; 1175f62bae50SIngo Molnar 1176f62bae50SIngo Molnar /* 1177f62bae50SIngo Molnar * Wait for idle. 1178f62bae50SIngo Molnar */ 1179f62bae50SIngo Molnar apic_wait_icr_idle(); 1180f62bae50SIngo Molnar 1181f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1182f62bae50SIngo Molnar apic_write(APIC_ICR, APIC_DEST_ALLINC | 1183f62bae50SIngo Molnar APIC_INT_LEVELTRIG | APIC_DM_INIT); 1184f62bae50SIngo Molnar } 1185f62bae50SIngo Molnar 1186f62bae50SIngo Molnar /* 1187f62bae50SIngo Molnar * An initial setup of the virtual wire mode. 1188f62bae50SIngo Molnar */ 1189f62bae50SIngo Molnar void __init init_bsp_APIC(void) 1190f62bae50SIngo Molnar { 1191f62bae50SIngo Molnar unsigned int value; 1192f62bae50SIngo Molnar 1193f62bae50SIngo Molnar /* 1194f62bae50SIngo Molnar * Don't do the setup now if we have a SMP BIOS as the 1195f62bae50SIngo Molnar * through-I/O-APIC virtual wire mode might be active. 1196f62bae50SIngo Molnar */ 1197f62bae50SIngo Molnar if (smp_found_config || !cpu_has_apic) 1198f62bae50SIngo Molnar return; 1199f62bae50SIngo Molnar 1200f62bae50SIngo Molnar /* 1201f62bae50SIngo Molnar * Do not trust the local APIC being empty at bootup. 1202f62bae50SIngo Molnar */ 1203f62bae50SIngo Molnar clear_local_APIC(); 1204f62bae50SIngo Molnar 1205f62bae50SIngo Molnar /* 1206f62bae50SIngo Molnar * Enable APIC. 1207f62bae50SIngo Molnar */ 1208f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 1209f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 1210f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 1211f62bae50SIngo Molnar 1212f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1213f62bae50SIngo Molnar /* This bit is reserved on P4/Xeon and should be cleared */ 1214f62bae50SIngo Molnar if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1215f62bae50SIngo Molnar (boot_cpu_data.x86 == 15)) 1216f62bae50SIngo Molnar value &= ~APIC_SPIV_FOCUS_DISABLED; 1217f62bae50SIngo Molnar else 1218f62bae50SIngo Molnar #endif 1219f62bae50SIngo Molnar value |= APIC_SPIV_FOCUS_DISABLED; 1220f62bae50SIngo Molnar value |= SPURIOUS_APIC_VECTOR; 1221f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 1222f62bae50SIngo Molnar 1223f62bae50SIngo Molnar /* 1224f62bae50SIngo Molnar * Set up the virtual wire mode. 1225f62bae50SIngo Molnar */ 1226f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_DM_EXTINT); 1227f62bae50SIngo Molnar value = APIC_DM_NMI; 1228f62bae50SIngo Molnar if (!lapic_is_integrated()) /* 82489DX */ 1229f62bae50SIngo Molnar value |= APIC_LVT_LEVEL_TRIGGER; 1230f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 1231f62bae50SIngo Molnar } 1232f62bae50SIngo Molnar 1233148f9bb8SPaul Gortmaker static void lapic_setup_esr(void) 1234f62bae50SIngo Molnar { 1235f62bae50SIngo Molnar unsigned int oldvalue, value, maxlvt; 1236f62bae50SIngo Molnar 1237f62bae50SIngo Molnar if (!lapic_is_integrated()) { 1238f62bae50SIngo Molnar pr_info("No ESR for 82489DX.\n"); 1239f62bae50SIngo Molnar return; 1240f62bae50SIngo Molnar } 1241f62bae50SIngo Molnar 1242f62bae50SIngo Molnar if (apic->disable_esr) { 1243f62bae50SIngo Molnar /* 1244f62bae50SIngo Molnar * Something untraceable is creating bad interrupts on 1245f62bae50SIngo Molnar * secondary quads ... for the moment, just leave the 1246f62bae50SIngo Molnar * ESR disabled - we can't do anything useful with the 1247f62bae50SIngo Molnar * errors anyway - mbligh 1248f62bae50SIngo Molnar */ 1249f62bae50SIngo Molnar pr_info("Leaving ESR disabled.\n"); 1250f62bae50SIngo Molnar return; 1251f62bae50SIngo Molnar } 1252f62bae50SIngo Molnar 1253f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 1254f62bae50SIngo Molnar if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1255f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1256f62bae50SIngo Molnar oldvalue = apic_read(APIC_ESR); 1257f62bae50SIngo Molnar 1258f62bae50SIngo Molnar /* enables sending errors */ 1259f62bae50SIngo Molnar value = ERROR_APIC_VECTOR; 1260f62bae50SIngo Molnar apic_write(APIC_LVTERR, value); 1261f62bae50SIngo Molnar 1262f62bae50SIngo Molnar /* 1263f62bae50SIngo Molnar * spec says clear errors after enabling vector. 1264f62bae50SIngo Molnar */ 1265f62bae50SIngo Molnar if (maxlvt > 3) 1266f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1267f62bae50SIngo Molnar value = apic_read(APIC_ESR); 1268f62bae50SIngo Molnar if (value != oldvalue) 1269f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "ESR value before enabling " 1270f62bae50SIngo Molnar "vector: 0x%08x after: 0x%08x\n", 1271f62bae50SIngo Molnar oldvalue, value); 1272f62bae50SIngo Molnar } 1273f62bae50SIngo Molnar 1274f62bae50SIngo Molnar /** 1275f62bae50SIngo Molnar * setup_local_APIC - setup the local APIC 12760aa002feSTejun Heo * 12770aa002feSTejun Heo * Used to setup local APIC while initializing BSP or bringin up APs. 12780aa002feSTejun Heo * Always called with preemption disabled. 1279f62bae50SIngo Molnar */ 1280148f9bb8SPaul Gortmaker void setup_local_APIC(void) 1281f62bae50SIngo Molnar { 12820aa002feSTejun Heo int cpu = smp_processor_id(); 12838c3ba8d0SKerstin Jonsson unsigned int value, queued; 12848c3ba8d0SKerstin Jonsson int i, j, acked = 0; 12858c3ba8d0SKerstin Jonsson unsigned long long tsc = 0, ntsc; 12868c3ba8d0SKerstin Jonsson long long max_loops = cpu_khz; 12878c3ba8d0SKerstin Jonsson 12888c3ba8d0SKerstin Jonsson if (cpu_has_tsc) 12898c3ba8d0SKerstin Jonsson rdtscll(tsc); 1290f62bae50SIngo Molnar 1291f62bae50SIngo Molnar if (disable_apic) { 12927167d08eSHenrik Kretzschmar disable_ioapic_support(); 1293f62bae50SIngo Molnar return; 1294f62bae50SIngo Molnar } 1295f62bae50SIngo Molnar 1296f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1297f62bae50SIngo Molnar /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1298f62bae50SIngo Molnar if (lapic_is_integrated() && apic->disable_esr) { 1299f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1300f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1301f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1302f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1303f62bae50SIngo Molnar } 1304f62bae50SIngo Molnar #endif 1305cdd6c482SIngo Molnar perf_events_lapic_init(); 1306f62bae50SIngo Molnar 1307f62bae50SIngo Molnar /* 1308f62bae50SIngo Molnar * Double-check whether this APIC is really registered. 1309f62bae50SIngo Molnar * This is meaningless in clustered apic mode, so we skip it. 1310f62bae50SIngo Molnar */ 1311c2777f98SDaniel Walker BUG_ON(!apic->apic_id_registered()); 1312f62bae50SIngo Molnar 1313f62bae50SIngo Molnar /* 1314f62bae50SIngo Molnar * Intel recommends to set DFR, LDR and TPR before enabling 1315f62bae50SIngo Molnar * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1316f62bae50SIngo Molnar * document number 292116). So here it goes... 1317f62bae50SIngo Molnar */ 1318f62bae50SIngo Molnar apic->init_apic_ldr(); 1319f62bae50SIngo Molnar 13206f802c4bSTejun Heo #ifdef CONFIG_X86_32 13216f802c4bSTejun Heo /* 1322acb8bc09STejun Heo * APIC LDR is initialized. If logical_apicid mapping was 1323acb8bc09STejun Heo * initialized during get_smp_config(), make sure it matches the 1324acb8bc09STejun Heo * actual value. 13256f802c4bSTejun Heo */ 1326acb8bc09STejun Heo i = early_per_cpu(x86_cpu_to_logical_apicid, cpu); 1327acb8bc09STejun Heo WARN_ON(i != BAD_APICID && i != logical_smp_processor_id()); 1328acb8bc09STejun Heo /* always use the value from LDR */ 13296f802c4bSTejun Heo early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 13306f802c4bSTejun Heo logical_smp_processor_id(); 1331c4b90c11STejun Heo 1332c4b90c11STejun Heo /* 1333c4b90c11STejun Heo * Some NUMA implementations (NUMAQ) don't initialize apicid to 1334c4b90c11STejun Heo * node mapping during NUMA init. Now that logical apicid is 1335c4b90c11STejun Heo * guaranteed to be known, give it another chance. This is already 1336c4b90c11STejun Heo * a bit too late - percpu allocation has already happened without 1337c4b90c11STejun Heo * proper NUMA affinity. 1338c4b90c11STejun Heo */ 133984914ed0STejun Heo if (apic->x86_32_numa_cpu_node) 1340c4b90c11STejun Heo set_apicid_to_node(early_per_cpu(x86_cpu_to_apicid, cpu), 1341c4b90c11STejun Heo apic->x86_32_numa_cpu_node(cpu)); 13426f802c4bSTejun Heo #endif 13436f802c4bSTejun Heo 1344f62bae50SIngo Molnar /* 1345f62bae50SIngo Molnar * Set Task Priority to 'accept all'. We never change this 1346f62bae50SIngo Molnar * later on. 1347f62bae50SIngo Molnar */ 1348f62bae50SIngo Molnar value = apic_read(APIC_TASKPRI); 1349f62bae50SIngo Molnar value &= ~APIC_TPRI_MASK; 1350f62bae50SIngo Molnar apic_write(APIC_TASKPRI, value); 1351f62bae50SIngo Molnar 1352f62bae50SIngo Molnar /* 1353f62bae50SIngo Molnar * After a crash, we no longer service the interrupts and a pending 1354f62bae50SIngo Molnar * interrupt from previous kernel might still have ISR bit set. 1355f62bae50SIngo Molnar * 1356f62bae50SIngo Molnar * Most probably by now CPU has serviced that pending interrupt and 1357f62bae50SIngo Molnar * it might not have done the ack_APIC_irq() because it thought, 1358f62bae50SIngo Molnar * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1359f62bae50SIngo Molnar * does not clear the ISR bit and cpu thinks it has already serivced 1360f62bae50SIngo Molnar * the interrupt. Hence a vector might get locked. It was noticed 1361f62bae50SIngo Molnar * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1362f62bae50SIngo Molnar */ 13638c3ba8d0SKerstin Jonsson do { 13648c3ba8d0SKerstin Jonsson queued = 0; 13658c3ba8d0SKerstin Jonsson for (i = APIC_ISR_NR - 1; i >= 0; i--) 13668c3ba8d0SKerstin Jonsson queued |= apic_read(APIC_IRR + i*0x10); 13678c3ba8d0SKerstin Jonsson 1368f62bae50SIngo Molnar for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1369f62bae50SIngo Molnar value = apic_read(APIC_ISR + i*0x10); 1370f62bae50SIngo Molnar for (j = 31; j >= 0; j--) { 13718c3ba8d0SKerstin Jonsson if (value & (1<<j)) { 1372f62bae50SIngo Molnar ack_APIC_irq(); 13738c3ba8d0SKerstin Jonsson acked++; 1374f62bae50SIngo Molnar } 1375f62bae50SIngo Molnar } 13768c3ba8d0SKerstin Jonsson } 13778c3ba8d0SKerstin Jonsson if (acked > 256) { 13788c3ba8d0SKerstin Jonsson printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", 13798c3ba8d0SKerstin Jonsson acked); 13808c3ba8d0SKerstin Jonsson break; 13818c3ba8d0SKerstin Jonsson } 138242fa4250SShai Fultheim if (queued) { 13838c3ba8d0SKerstin Jonsson if (cpu_has_tsc) { 13848c3ba8d0SKerstin Jonsson rdtscll(ntsc); 13858c3ba8d0SKerstin Jonsson max_loops = (cpu_khz << 10) - (ntsc - tsc); 13868c3ba8d0SKerstin Jonsson } else 13878c3ba8d0SKerstin Jonsson max_loops--; 138842fa4250SShai Fultheim } 13898c3ba8d0SKerstin Jonsson } while (queued && max_loops > 0); 13908c3ba8d0SKerstin Jonsson WARN_ON(max_loops <= 0); 1391f62bae50SIngo Molnar 1392f62bae50SIngo Molnar /* 1393f62bae50SIngo Molnar * Now that we are all set up, enable the APIC 1394f62bae50SIngo Molnar */ 1395f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 1396f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 1397f62bae50SIngo Molnar /* 1398f62bae50SIngo Molnar * Enable APIC 1399f62bae50SIngo Molnar */ 1400f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 1401f62bae50SIngo Molnar 1402f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1403f62bae50SIngo Molnar /* 1404f62bae50SIngo Molnar * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1405f62bae50SIngo Molnar * certain networking cards. If high frequency interrupts are 1406f62bae50SIngo Molnar * happening on a particular IOAPIC pin, plus the IOAPIC routing 1407f62bae50SIngo Molnar * entry is masked/unmasked at a high rate as well then sooner or 1408f62bae50SIngo Molnar * later IOAPIC line gets 'stuck', no more interrupts are received 1409f62bae50SIngo Molnar * from the device. If focus CPU is disabled then the hang goes 1410f62bae50SIngo Molnar * away, oh well :-( 1411f62bae50SIngo Molnar * 1412f62bae50SIngo Molnar * [ This bug can be reproduced easily with a level-triggered 1413f62bae50SIngo Molnar * PCI Ne2000 networking cards and PII/PIII processors, dual 1414f62bae50SIngo Molnar * BX chipset. ] 1415f62bae50SIngo Molnar */ 1416f62bae50SIngo Molnar /* 1417f62bae50SIngo Molnar * Actually disabling the focus CPU check just makes the hang less 1418f62bae50SIngo Molnar * frequent as it makes the interrupt distributon model be more 1419f62bae50SIngo Molnar * like LRU than MRU (the short-term load is more even across CPUs). 1420f62bae50SIngo Molnar * See also the comment in end_level_ioapic_irq(). --macro 1421f62bae50SIngo Molnar */ 1422f62bae50SIngo Molnar 1423f62bae50SIngo Molnar /* 1424f62bae50SIngo Molnar * - enable focus processor (bit==0) 1425f62bae50SIngo Molnar * - 64bit mode always use processor focus 1426f62bae50SIngo Molnar * so no need to set it 1427f62bae50SIngo Molnar */ 1428f62bae50SIngo Molnar value &= ~APIC_SPIV_FOCUS_DISABLED; 1429f62bae50SIngo Molnar #endif 1430f62bae50SIngo Molnar 1431f62bae50SIngo Molnar /* 1432f62bae50SIngo Molnar * Set spurious IRQ vector 1433f62bae50SIngo Molnar */ 1434f62bae50SIngo Molnar value |= SPURIOUS_APIC_VECTOR; 1435f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 1436f62bae50SIngo Molnar 1437f62bae50SIngo Molnar /* 1438f62bae50SIngo Molnar * Set up LVT0, LVT1: 1439f62bae50SIngo Molnar * 1440f62bae50SIngo Molnar * set up through-local-APIC on the BP's LINT0. This is not 1441f62bae50SIngo Molnar * strictly necessary in pure symmetric-IO mode, but sometimes 1442f62bae50SIngo Molnar * we delegate interrupts to the 8259A. 1443f62bae50SIngo Molnar */ 1444f62bae50SIngo Molnar /* 1445f62bae50SIngo Molnar * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1446f62bae50SIngo Molnar */ 1447f62bae50SIngo Molnar value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 14480aa002feSTejun Heo if (!cpu && (pic_mode || !value)) { 1449f62bae50SIngo Molnar value = APIC_DM_EXTINT; 14500aa002feSTejun Heo apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1451f62bae50SIngo Molnar } else { 1452f62bae50SIngo Molnar value = APIC_DM_EXTINT | APIC_LVT_MASKED; 14530aa002feSTejun Heo apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1454f62bae50SIngo Molnar } 1455f62bae50SIngo Molnar apic_write(APIC_LVT0, value); 1456f62bae50SIngo Molnar 1457f62bae50SIngo Molnar /* 1458f62bae50SIngo Molnar * only the BP should see the LINT1 NMI signal, obviously. 1459f62bae50SIngo Molnar */ 14600aa002feSTejun Heo if (!cpu) 1461f62bae50SIngo Molnar value = APIC_DM_NMI; 1462f62bae50SIngo Molnar else 1463f62bae50SIngo Molnar value = APIC_DM_NMI | APIC_LVT_MASKED; 1464f62bae50SIngo Molnar if (!lapic_is_integrated()) /* 82489DX */ 1465f62bae50SIngo Molnar value |= APIC_LVT_LEVEL_TRIGGER; 1466f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 1467f62bae50SIngo Molnar 1468638bee71SH. Peter Anvin #ifdef CONFIG_X86_MCE_INTEL 1469638bee71SH. Peter Anvin /* Recheck CMCI information after local APIC is up on CPU #0 */ 14700aa002feSTejun Heo if (!cpu) 1471638bee71SH. Peter Anvin cmci_recheck(); 1472638bee71SH. Peter Anvin #endif 1473f62bae50SIngo Molnar } 1474f62bae50SIngo Molnar 1475148f9bb8SPaul Gortmaker void end_local_APIC_setup(void) 1476f62bae50SIngo Molnar { 1477f62bae50SIngo Molnar lapic_setup_esr(); 1478f62bae50SIngo Molnar 1479f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1480f62bae50SIngo Molnar { 1481f62bae50SIngo Molnar unsigned int value; 1482f62bae50SIngo Molnar /* Disable the local apic timer */ 1483f62bae50SIngo Molnar value = apic_read(APIC_LVTT); 1484f62bae50SIngo Molnar value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1485f62bae50SIngo Molnar apic_write(APIC_LVTT, value); 1486f62bae50SIngo Molnar } 1487f62bae50SIngo Molnar #endif 1488f62bae50SIngo Molnar 1489f62bae50SIngo Molnar apic_pm_activate(); 14902fb270f3SJan Beulich } 14912fb270f3SJan Beulich 14922fb270f3SJan Beulich void __init bsp_end_local_APIC_setup(void) 14932fb270f3SJan Beulich { 14942fb270f3SJan Beulich end_local_APIC_setup(); 14957f7fbf45SKenji Kaneshige 14967f7fbf45SKenji Kaneshige /* 14977f7fbf45SKenji Kaneshige * Now that local APIC setup is completed for BP, configure the fault 14987f7fbf45SKenji Kaneshige * handling for interrupt remapping. 14997f7fbf45SKenji Kaneshige */ 150095a02e97SSuresh Siddha irq_remap_enable_fault_handling(); 15017f7fbf45SKenji Kaneshige 1502f62bae50SIngo Molnar } 1503f62bae50SIngo Molnar 1504f62bae50SIngo Molnar #ifdef CONFIG_X86_X2APIC 1505fb209bd8SYinghai Lu /* 1506fb209bd8SYinghai Lu * Need to disable xapic and x2apic at the same time and then enable xapic mode 1507fb209bd8SYinghai Lu */ 1508fb209bd8SYinghai Lu static inline void __disable_x2apic(u64 msr) 1509fb209bd8SYinghai Lu { 1510fb209bd8SYinghai Lu wrmsrl(MSR_IA32_APICBASE, 1511fb209bd8SYinghai Lu msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); 1512fb209bd8SYinghai Lu wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); 1513fb209bd8SYinghai Lu } 1514fb209bd8SYinghai Lu 1515a31bc327SYinghai Lu static __init void disable_x2apic(void) 1516fb209bd8SYinghai Lu { 1517fb209bd8SYinghai Lu u64 msr; 1518fb209bd8SYinghai Lu 1519fb209bd8SYinghai Lu if (!cpu_has_x2apic) 1520fb209bd8SYinghai Lu return; 1521fb209bd8SYinghai Lu 1522fb209bd8SYinghai Lu rdmsrl(MSR_IA32_APICBASE, msr); 1523fb209bd8SYinghai Lu if (msr & X2APIC_ENABLE) { 1524fb209bd8SYinghai Lu u32 x2apic_id = read_apic_id(); 1525fb209bd8SYinghai Lu 1526fb209bd8SYinghai Lu if (x2apic_id >= 255) 1527fb209bd8SYinghai Lu panic("Cannot disable x2apic, id: %08x\n", x2apic_id); 1528fb209bd8SYinghai Lu 1529fb209bd8SYinghai Lu pr_info("Disabling x2apic\n"); 1530fb209bd8SYinghai Lu __disable_x2apic(msr); 1531fb209bd8SYinghai Lu 1532a31bc327SYinghai Lu if (nox2apic) { 1533a31bc327SYinghai Lu clear_cpu_cap(&cpu_data(0), X86_FEATURE_X2APIC); 1534a31bc327SYinghai Lu setup_clear_cpu_cap(X86_FEATURE_X2APIC); 1535a31bc327SYinghai Lu } 1536a31bc327SYinghai Lu 1537fb209bd8SYinghai Lu x2apic_disabled = 1; 1538fb209bd8SYinghai Lu x2apic_mode = 0; 1539fb209bd8SYinghai Lu 1540fb209bd8SYinghai Lu register_lapic_address(mp_lapic_addr); 1541fb209bd8SYinghai Lu } 1542fb209bd8SYinghai Lu } 1543fb209bd8SYinghai Lu 1544f62bae50SIngo Molnar void check_x2apic(void) 1545f62bae50SIngo Molnar { 1546ef1f87aaSSuresh Siddha if (x2apic_enabled()) { 1547f62bae50SIngo Molnar pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); 1548fc1edaf9SSuresh Siddha x2apic_preenabled = x2apic_mode = 1; 1549f62bae50SIngo Molnar } 1550f62bae50SIngo Molnar } 1551f62bae50SIngo Molnar 1552f62bae50SIngo Molnar void enable_x2apic(void) 1553f62bae50SIngo Molnar { 1554fb209bd8SYinghai Lu u64 msr; 1555fb209bd8SYinghai Lu 1556fb209bd8SYinghai Lu rdmsrl(MSR_IA32_APICBASE, msr); 1557fb209bd8SYinghai Lu if (x2apic_disabled) { 1558fb209bd8SYinghai Lu __disable_x2apic(msr); 1559fb209bd8SYinghai Lu return; 1560fb209bd8SYinghai Lu } 1561f62bae50SIngo Molnar 1562fc1edaf9SSuresh Siddha if (!x2apic_mode) 1563f62bae50SIngo Molnar return; 1564f62bae50SIngo Molnar 1565f62bae50SIngo Molnar if (!(msr & X2APIC_ENABLE)) { 1566450b1e8dSMike Travis printk_once(KERN_INFO "Enabling x2apic\n"); 1567fb209bd8SYinghai Lu wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); 1568f62bae50SIngo Molnar } 1569f62bae50SIngo Molnar } 157093758238SWeidong Han #endif /* CONFIG_X86_X2APIC */ 1571f62bae50SIngo Molnar 1572ce69a784SGleb Natapov int __init enable_IR(void) 1573f62bae50SIngo Molnar { 1574d3f13810SSuresh Siddha #ifdef CONFIG_IRQ_REMAP 157595a02e97SSuresh Siddha if (!irq_remapping_supported()) { 157693758238SWeidong Han pr_debug("intr-remapping not supported\n"); 157741750d31SSuresh Siddha return -1; 157893758238SWeidong Han } 157993758238SWeidong Han 158093758238SWeidong Han if (!x2apic_preenabled && skip_ioapic_setup) { 158193758238SWeidong Han pr_info("Skipped enabling intr-remap because of skipping " 158293758238SWeidong Han "io-apic setup\n"); 158341750d31SSuresh Siddha return -1; 1584f62bae50SIngo Molnar } 1585f62bae50SIngo Molnar 158695a02e97SSuresh Siddha return irq_remapping_enable(); 1587ce69a784SGleb Natapov #endif 158841750d31SSuresh Siddha return -1; 1589ce69a784SGleb Natapov } 1590ce69a784SGleb Natapov 1591ce69a784SGleb Natapov void __init enable_IR_x2apic(void) 1592ce69a784SGleb Natapov { 1593ce69a784SGleb Natapov unsigned long flags; 1594ce69a784SGleb Natapov int ret, x2apic_enabled = 0; 1595736baef4SJoerg Roedel int hardware_init_ret; 1596b7f42ab2SYinghai Lu 1597736baef4SJoerg Roedel /* Make sure irq_remap_ops are initialized */ 159895a02e97SSuresh Siddha setup_irq_remapping_ops(); 1599736baef4SJoerg Roedel 160095a02e97SSuresh Siddha hardware_init_ret = irq_remapping_prepare(); 1601736baef4SJoerg Roedel if (hardware_init_ret && !x2apic_supported()) 1602e670761fSYinghai Lu return; 1603ce69a784SGleb Natapov 160431dce14aSSuresh Siddha ret = save_ioapic_entries(); 1605f62bae50SIngo Molnar if (ret) { 1606f62bae50SIngo Molnar pr_info("Saving IO-APIC state failed: %d\n", ret); 1607fb209bd8SYinghai Lu return; 1608f62bae50SIngo Molnar } 1609f62bae50SIngo Molnar 161005c3dc2cSSuresh Siddha local_irq_save(flags); 1611b81bb373SJacob Pan legacy_pic->mask_all(); 161231dce14aSSuresh Siddha mask_ioapic_entries(); 161305c3dc2cSSuresh Siddha 1614a31bc327SYinghai Lu if (x2apic_preenabled && nox2apic) 1615a31bc327SYinghai Lu disable_x2apic(); 1616a31bc327SYinghai Lu 1617736baef4SJoerg Roedel if (hardware_init_ret) 161841750d31SSuresh Siddha ret = -1; 1619b7f42ab2SYinghai Lu else 1620ce69a784SGleb Natapov ret = enable_IR(); 1621b7f42ab2SYinghai Lu 1622fb209bd8SYinghai Lu if (!x2apic_supported()) 1623a31bc327SYinghai Lu goto skip_x2apic; 1624fb209bd8SYinghai Lu 162541750d31SSuresh Siddha if (ret < 0) { 1626ce69a784SGleb Natapov /* IR is required if there is APIC ID > 255 even when running 1627ce69a784SGleb Natapov * under KVM 1628ce69a784SGleb Natapov */ 16292904ed8dSSheng Yang if (max_physical_apicid > 255 || 1630fb209bd8SYinghai Lu !hypervisor_x2apic_available()) { 1631fb209bd8SYinghai Lu if (x2apic_preenabled) 1632fb209bd8SYinghai Lu disable_x2apic(); 1633a31bc327SYinghai Lu goto skip_x2apic; 1634fb209bd8SYinghai Lu } 1635ce69a784SGleb Natapov /* 1636ce69a784SGleb Natapov * without IR all CPUs can be addressed by IOAPIC/MSI 1637ce69a784SGleb Natapov * only in physical mode 1638ce69a784SGleb Natapov */ 1639ce69a784SGleb Natapov x2apic_force_phys(); 1640ce69a784SGleb Natapov } 1641f62bae50SIngo Molnar 1642fb209bd8SYinghai Lu if (ret == IRQ_REMAP_XAPIC_MODE) { 1643fb209bd8SYinghai Lu pr_info("x2apic not enabled, IRQ remapping is in xapic mode\n"); 1644a31bc327SYinghai Lu goto skip_x2apic; 1645fb209bd8SYinghai Lu } 164641750d31SSuresh Siddha 1647ce69a784SGleb Natapov x2apic_enabled = 1; 164893758238SWeidong Han 1649fc1edaf9SSuresh Siddha if (x2apic_supported() && !x2apic_mode) { 1650fc1edaf9SSuresh Siddha x2apic_mode = 1; 1651f62bae50SIngo Molnar enable_x2apic(); 165293758238SWeidong Han pr_info("Enabled x2apic\n"); 1653f62bae50SIngo Molnar } 1654f62bae50SIngo Molnar 1655a31bc327SYinghai Lu skip_x2apic: 165641750d31SSuresh Siddha if (ret < 0) /* IR enabling failed */ 165731dce14aSSuresh Siddha restore_ioapic_entries(); 1658b81bb373SJacob Pan legacy_pic->restore_mask(); 1659f62bae50SIngo Molnar local_irq_restore(flags); 1660f62bae50SIngo Molnar } 166193758238SWeidong Han 1662f62bae50SIngo Molnar #ifdef CONFIG_X86_64 1663f62bae50SIngo Molnar /* 1664f62bae50SIngo Molnar * Detect and enable local APICs on non-SMP boards. 1665f62bae50SIngo Molnar * Original code written by Keir Fraser. 1666f62bae50SIngo Molnar * On AMD64 we trust the BIOS - if it says no APIC it is likely 1667f62bae50SIngo Molnar * not correctly set up (usually the APIC timer won't work etc.) 1668f62bae50SIngo Molnar */ 1669f62bae50SIngo Molnar static int __init detect_init_APIC(void) 1670f62bae50SIngo Molnar { 1671f62bae50SIngo Molnar if (!cpu_has_apic) { 1672f62bae50SIngo Molnar pr_info("No local APIC present\n"); 1673f62bae50SIngo Molnar return -1; 1674f62bae50SIngo Molnar } 1675f62bae50SIngo Molnar 1676f62bae50SIngo Molnar mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1677f62bae50SIngo Molnar return 0; 1678f62bae50SIngo Molnar } 1679f62bae50SIngo Molnar #else 16805a7ae78fSThomas Gleixner 168125874a29SHenrik Kretzschmar static int __init apic_verify(void) 16825a7ae78fSThomas Gleixner { 16835a7ae78fSThomas Gleixner u32 features, h, l; 16845a7ae78fSThomas Gleixner 16855a7ae78fSThomas Gleixner /* 16865a7ae78fSThomas Gleixner * The APIC feature bit should now be enabled 16875a7ae78fSThomas Gleixner * in `cpuid' 16885a7ae78fSThomas Gleixner */ 16895a7ae78fSThomas Gleixner features = cpuid_edx(1); 16905a7ae78fSThomas Gleixner if (!(features & (1 << X86_FEATURE_APIC))) { 16915a7ae78fSThomas Gleixner pr_warning("Could not enable APIC!\n"); 16925a7ae78fSThomas Gleixner return -1; 16935a7ae78fSThomas Gleixner } 16945a7ae78fSThomas Gleixner set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 16955a7ae78fSThomas Gleixner mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 16965a7ae78fSThomas Gleixner 16975a7ae78fSThomas Gleixner /* The BIOS may have set up the APIC at some other address */ 1698cbf2829bSBryan O'Donoghue if (boot_cpu_data.x86 >= 6) { 16995a7ae78fSThomas Gleixner rdmsr(MSR_IA32_APICBASE, l, h); 17005a7ae78fSThomas Gleixner if (l & MSR_IA32_APICBASE_ENABLE) 17015a7ae78fSThomas Gleixner mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1702cbf2829bSBryan O'Donoghue } 17035a7ae78fSThomas Gleixner 17045a7ae78fSThomas Gleixner pr_info("Found and enabled local APIC!\n"); 17055a7ae78fSThomas Gleixner return 0; 17065a7ae78fSThomas Gleixner } 17075a7ae78fSThomas Gleixner 170825874a29SHenrik Kretzschmar int __init apic_force_enable(unsigned long addr) 17095a7ae78fSThomas Gleixner { 17105a7ae78fSThomas Gleixner u32 h, l; 17115a7ae78fSThomas Gleixner 17125a7ae78fSThomas Gleixner if (disable_apic) 17135a7ae78fSThomas Gleixner return -1; 17145a7ae78fSThomas Gleixner 17155a7ae78fSThomas Gleixner /* 17165a7ae78fSThomas Gleixner * Some BIOSes disable the local APIC in the APIC_BASE 17175a7ae78fSThomas Gleixner * MSR. This can only be done in software for Intel P6 or later 17185a7ae78fSThomas Gleixner * and AMD K7 (Model > 1) or later. 17195a7ae78fSThomas Gleixner */ 1720cbf2829bSBryan O'Donoghue if (boot_cpu_data.x86 >= 6) { 17215a7ae78fSThomas Gleixner rdmsr(MSR_IA32_APICBASE, l, h); 17225a7ae78fSThomas Gleixner if (!(l & MSR_IA32_APICBASE_ENABLE)) { 17235a7ae78fSThomas Gleixner pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 17245a7ae78fSThomas Gleixner l &= ~MSR_IA32_APICBASE_BASE; 1725a906fdaaSThomas Gleixner l |= MSR_IA32_APICBASE_ENABLE | addr; 17265a7ae78fSThomas Gleixner wrmsr(MSR_IA32_APICBASE, l, h); 17275a7ae78fSThomas Gleixner enabled_via_apicbase = 1; 17285a7ae78fSThomas Gleixner } 1729cbf2829bSBryan O'Donoghue } 17305a7ae78fSThomas Gleixner return apic_verify(); 17315a7ae78fSThomas Gleixner } 17325a7ae78fSThomas Gleixner 1733f62bae50SIngo Molnar /* 1734f62bae50SIngo Molnar * Detect and initialize APIC 1735f62bae50SIngo Molnar */ 1736f62bae50SIngo Molnar static int __init detect_init_APIC(void) 1737f62bae50SIngo Molnar { 1738f62bae50SIngo Molnar /* Disabled by kernel option? */ 1739f62bae50SIngo Molnar if (disable_apic) 1740f62bae50SIngo Molnar return -1; 1741f62bae50SIngo Molnar 1742f62bae50SIngo Molnar switch (boot_cpu_data.x86_vendor) { 1743f62bae50SIngo Molnar case X86_VENDOR_AMD: 1744f62bae50SIngo Molnar if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1745f62bae50SIngo Molnar (boot_cpu_data.x86 >= 15)) 1746f62bae50SIngo Molnar break; 1747f62bae50SIngo Molnar goto no_apic; 1748f62bae50SIngo Molnar case X86_VENDOR_INTEL: 1749f62bae50SIngo Molnar if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1750f62bae50SIngo Molnar (boot_cpu_data.x86 == 5 && cpu_has_apic)) 1751f62bae50SIngo Molnar break; 1752f62bae50SIngo Molnar goto no_apic; 1753f62bae50SIngo Molnar default: 1754f62bae50SIngo Molnar goto no_apic; 1755f62bae50SIngo Molnar } 1756f62bae50SIngo Molnar 1757f62bae50SIngo Molnar if (!cpu_has_apic) { 1758f62bae50SIngo Molnar /* 1759f62bae50SIngo Molnar * Over-ride BIOS and try to enable the local APIC only if 1760f62bae50SIngo Molnar * "lapic" specified. 1761f62bae50SIngo Molnar */ 1762f62bae50SIngo Molnar if (!force_enable_local_apic) { 1763f62bae50SIngo Molnar pr_info("Local APIC disabled by BIOS -- " 1764f62bae50SIngo Molnar "you can enable it with \"lapic\"\n"); 1765f62bae50SIngo Molnar return -1; 1766f62bae50SIngo Molnar } 1767a906fdaaSThomas Gleixner if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) 17685a7ae78fSThomas Gleixner return -1; 17695a7ae78fSThomas Gleixner } else { 17705a7ae78fSThomas Gleixner if (apic_verify()) 1771f62bae50SIngo Molnar return -1; 1772f62bae50SIngo Molnar } 1773f62bae50SIngo Molnar 1774f62bae50SIngo Molnar apic_pm_activate(); 1775f62bae50SIngo Molnar 1776f62bae50SIngo Molnar return 0; 1777f62bae50SIngo Molnar 1778f62bae50SIngo Molnar no_apic: 1779f62bae50SIngo Molnar pr_info("No local APIC present or hardware disabled\n"); 1780f62bae50SIngo Molnar return -1; 1781f62bae50SIngo Molnar } 1782f62bae50SIngo Molnar #endif 1783f62bae50SIngo Molnar 1784f62bae50SIngo Molnar /** 1785f62bae50SIngo Molnar * init_apic_mappings - initialize APIC mappings 1786f62bae50SIngo Molnar */ 1787f62bae50SIngo Molnar void __init init_apic_mappings(void) 1788f62bae50SIngo Molnar { 17894401da61SYinghai Lu unsigned int new_apicid; 17904401da61SYinghai Lu 1791fc1edaf9SSuresh Siddha if (x2apic_mode) { 1792f62bae50SIngo Molnar boot_cpu_physical_apicid = read_apic_id(); 1793f62bae50SIngo Molnar return; 1794f62bae50SIngo Molnar } 1795f62bae50SIngo Molnar 17964797f6b0SYinghai Lu /* If no local APIC can be found return early */ 1797f62bae50SIngo Molnar if (!smp_found_config && detect_init_APIC()) { 17984797f6b0SYinghai Lu /* lets NOP'ify apic operations */ 17994797f6b0SYinghai Lu pr_info("APIC: disable apic facility\n"); 18004797f6b0SYinghai Lu apic_disable(); 18014797f6b0SYinghai Lu } else { 1802f62bae50SIngo Molnar apic_phys = mp_lapic_addr; 1803f62bae50SIngo Molnar 18044401da61SYinghai Lu /* 18054401da61SYinghai Lu * acpi lapic path already maps that address in 18064401da61SYinghai Lu * acpi_register_lapic_address() 18074401da61SYinghai Lu */ 18085989cd6aSEric W. Biederman if (!acpi_lapic && !smp_found_config) 1809326a2e6bSYinghai Lu register_lapic_address(apic_phys); 1810cec6be6dSCyrill Gorcunov } 1811f62bae50SIngo Molnar 1812f62bae50SIngo Molnar /* 1813f62bae50SIngo Molnar * Fetch the APIC ID of the BSP in case we have a 1814f62bae50SIngo Molnar * default configuration (or the MP table is broken). 1815f62bae50SIngo Molnar */ 18164401da61SYinghai Lu new_apicid = read_apic_id(); 18174401da61SYinghai Lu if (boot_cpu_physical_apicid != new_apicid) { 18184401da61SYinghai Lu boot_cpu_physical_apicid = new_apicid; 1819103428e5SCyrill Gorcunov /* 1820103428e5SCyrill Gorcunov * yeah -- we lie about apic_version 1821103428e5SCyrill Gorcunov * in case if apic was disabled via boot option 1822103428e5SCyrill Gorcunov * but it's not a problem for SMP compiled kernel 1823103428e5SCyrill Gorcunov * since smp_sanity_check is prepared for such a case 1824103428e5SCyrill Gorcunov * and disable smp mode 1825103428e5SCyrill Gorcunov */ 18264401da61SYinghai Lu apic_version[new_apicid] = 18274401da61SYinghai Lu GET_APIC_VERSION(apic_read(APIC_LVR)); 182808306ce6SCyrill Gorcunov } 1829f62bae50SIngo Molnar } 1830f62bae50SIngo Molnar 1831c0104d38SYinghai Lu void __init register_lapic_address(unsigned long address) 1832c0104d38SYinghai Lu { 1833c0104d38SYinghai Lu mp_lapic_addr = address; 1834c0104d38SYinghai Lu 18350450193bSYinghai Lu if (!x2apic_mode) { 1836c0104d38SYinghai Lu set_fixmap_nocache(FIX_APIC_BASE, address); 1837f1157141SYinghai Lu apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 1838f1157141SYinghai Lu APIC_BASE, mp_lapic_addr); 18390450193bSYinghai Lu } 1840c0104d38SYinghai Lu if (boot_cpu_physical_apicid == -1U) { 1841c0104d38SYinghai Lu boot_cpu_physical_apicid = read_apic_id(); 1842c0104d38SYinghai Lu apic_version[boot_cpu_physical_apicid] = 1843c0104d38SYinghai Lu GET_APIC_VERSION(apic_read(APIC_LVR)); 1844c0104d38SYinghai Lu } 1845c0104d38SYinghai Lu } 1846c0104d38SYinghai Lu 1847f62bae50SIngo Molnar /* 1848f62bae50SIngo Molnar * This initializes the IO-APIC and APIC hardware if this is 1849f62bae50SIngo Molnar * a UP kernel. 1850f62bae50SIngo Molnar */ 185156d91f13SYinghai Lu int apic_version[MAX_LOCAL_APIC]; 1852f62bae50SIngo Molnar 1853f62bae50SIngo Molnar int __init APIC_init_uniprocessor(void) 1854f62bae50SIngo Molnar { 1855f62bae50SIngo Molnar if (disable_apic) { 1856f62bae50SIngo Molnar pr_info("Apic disabled\n"); 1857f62bae50SIngo Molnar return -1; 1858f62bae50SIngo Molnar } 1859f62bae50SIngo Molnar #ifdef CONFIG_X86_64 1860f62bae50SIngo Molnar if (!cpu_has_apic) { 1861f62bae50SIngo Molnar disable_apic = 1; 1862f62bae50SIngo Molnar pr_info("Apic disabled by BIOS\n"); 1863f62bae50SIngo Molnar return -1; 1864f62bae50SIngo Molnar } 1865f62bae50SIngo Molnar #else 1866f62bae50SIngo Molnar if (!smp_found_config && !cpu_has_apic) 1867f62bae50SIngo Molnar return -1; 1868f62bae50SIngo Molnar 1869f62bae50SIngo Molnar /* 1870f62bae50SIngo Molnar * Complain if the BIOS pretends there is one. 1871f62bae50SIngo Molnar */ 1872f62bae50SIngo Molnar if (!cpu_has_apic && 1873f62bae50SIngo Molnar APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 1874f62bae50SIngo Molnar pr_err("BIOS bug, local APIC 0x%x not detected!...\n", 1875f62bae50SIngo Molnar boot_cpu_physical_apicid); 1876f62bae50SIngo Molnar return -1; 1877f62bae50SIngo Molnar } 1878f62bae50SIngo Molnar #endif 1879f62bae50SIngo Molnar 1880f62bae50SIngo Molnar default_setup_apic_routing(); 1881f62bae50SIngo Molnar 1882f62bae50SIngo Molnar verify_local_APIC(); 1883f62bae50SIngo Molnar connect_bsp_APIC(); 1884f62bae50SIngo Molnar 1885f62bae50SIngo Molnar #ifdef CONFIG_X86_64 1886f62bae50SIngo Molnar apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); 1887f62bae50SIngo Molnar #else 1888f62bae50SIngo Molnar /* 1889f62bae50SIngo Molnar * Hack: In case of kdump, after a crash, kernel might be booting 1890f62bae50SIngo Molnar * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 1891f62bae50SIngo Molnar * might be zero if read from MP tables. Get it from LAPIC. 1892f62bae50SIngo Molnar */ 1893f62bae50SIngo Molnar # ifdef CONFIG_CRASH_DUMP 1894f62bae50SIngo Molnar boot_cpu_physical_apicid = read_apic_id(); 1895f62bae50SIngo Molnar # endif 1896f62bae50SIngo Molnar #endif 1897f62bae50SIngo Molnar physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1898f62bae50SIngo Molnar setup_local_APIC(); 1899f62bae50SIngo Molnar 1900f62bae50SIngo Molnar #ifdef CONFIG_X86_IO_APIC 1901f62bae50SIngo Molnar /* 1902f62bae50SIngo Molnar * Now enable IO-APICs, actually call clear_IO_APIC 1903f62bae50SIngo Molnar * We need clear_IO_APIC before enabling error vector 1904f62bae50SIngo Molnar */ 1905f62bae50SIngo Molnar if (!skip_ioapic_setup && nr_ioapics) 1906f62bae50SIngo Molnar enable_IO_APIC(); 1907f62bae50SIngo Molnar #endif 1908f62bae50SIngo Molnar 19092fb270f3SJan Beulich bsp_end_local_APIC_setup(); 1910f62bae50SIngo Molnar 1911f62bae50SIngo Molnar #ifdef CONFIG_X86_IO_APIC 1912f62bae50SIngo Molnar if (smp_found_config && !skip_ioapic_setup && nr_ioapics) 1913f62bae50SIngo Molnar setup_IO_APIC(); 1914f62bae50SIngo Molnar else { 1915f62bae50SIngo Molnar nr_ioapics = 0; 1916f62bae50SIngo Molnar } 1917f62bae50SIngo Molnar #endif 1918f62bae50SIngo Molnar 1919736decacSThomas Gleixner x86_init.timers.setup_percpu_clockev(); 1920f62bae50SIngo Molnar return 0; 1921f62bae50SIngo Molnar } 1922f62bae50SIngo Molnar 1923f62bae50SIngo Molnar /* 1924f62bae50SIngo Molnar * Local APIC interrupts 1925f62bae50SIngo Molnar */ 1926f62bae50SIngo Molnar 1927f62bae50SIngo Molnar /* 1928f62bae50SIngo Molnar * This interrupt should _never_ happen with our APIC/SMP architecture 1929f62bae50SIngo Molnar */ 1930eddc0e92SSeiji Aguchi static inline void __smp_spurious_interrupt(void) 1931f62bae50SIngo Molnar { 1932f62bae50SIngo Molnar u32 v; 1933f62bae50SIngo Molnar 1934f62bae50SIngo Molnar /* 1935f62bae50SIngo Molnar * Check if this really is a spurious interrupt and ACK it 1936f62bae50SIngo Molnar * if it is a vectored one. Just in case... 1937f62bae50SIngo Molnar * Spurious interrupts should not be ACKed. 1938f62bae50SIngo Molnar */ 1939f62bae50SIngo Molnar v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); 1940f62bae50SIngo Molnar if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) 1941f62bae50SIngo Molnar ack_APIC_irq(); 1942f62bae50SIngo Molnar 1943f62bae50SIngo Molnar inc_irq_stat(irq_spurious_count); 1944f62bae50SIngo Molnar 1945f62bae50SIngo Molnar /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 1946f62bae50SIngo Molnar pr_info("spurious APIC interrupt on CPU#%d, " 1947f62bae50SIngo Molnar "should never happen.\n", smp_processor_id()); 1948eddc0e92SSeiji Aguchi } 1949eddc0e92SSeiji Aguchi 19501d9090e2SAndi Kleen __visible void smp_spurious_interrupt(struct pt_regs *regs) 1951eddc0e92SSeiji Aguchi { 1952eddc0e92SSeiji Aguchi entering_irq(); 1953eddc0e92SSeiji Aguchi __smp_spurious_interrupt(); 1954eddc0e92SSeiji Aguchi exiting_irq(); 1955f62bae50SIngo Molnar } 1956f62bae50SIngo Molnar 19571d9090e2SAndi Kleen __visible void smp_trace_spurious_interrupt(struct pt_regs *regs) 1958cf910e83SSeiji Aguchi { 1959cf910e83SSeiji Aguchi entering_irq(); 1960cf910e83SSeiji Aguchi trace_spurious_apic_entry(SPURIOUS_APIC_VECTOR); 1961cf910e83SSeiji Aguchi __smp_spurious_interrupt(); 1962cf910e83SSeiji Aguchi trace_spurious_apic_exit(SPURIOUS_APIC_VECTOR); 1963cf910e83SSeiji Aguchi exiting_irq(); 1964f62bae50SIngo Molnar } 1965f62bae50SIngo Molnar 1966f62bae50SIngo Molnar /* 1967f62bae50SIngo Molnar * This interrupt should never happen with our APIC/SMP architecture 1968f62bae50SIngo Molnar */ 1969eddc0e92SSeiji Aguchi static inline void __smp_error_interrupt(struct pt_regs *regs) 1970f62bae50SIngo Molnar { 19712b398bd9SYouquan Song u32 v0, v1; 19722b398bd9SYouquan Song u32 i = 0; 19732b398bd9SYouquan Song static const char * const error_interrupt_reason[] = { 19742b398bd9SYouquan Song "Send CS error", /* APIC Error Bit 0 */ 19752b398bd9SYouquan Song "Receive CS error", /* APIC Error Bit 1 */ 19762b398bd9SYouquan Song "Send accept error", /* APIC Error Bit 2 */ 19772b398bd9SYouquan Song "Receive accept error", /* APIC Error Bit 3 */ 19782b398bd9SYouquan Song "Redirectable IPI", /* APIC Error Bit 4 */ 19792b398bd9SYouquan Song "Send illegal vector", /* APIC Error Bit 5 */ 19802b398bd9SYouquan Song "Received illegal vector", /* APIC Error Bit 6 */ 19812b398bd9SYouquan Song "Illegal register address", /* APIC Error Bit 7 */ 19822b398bd9SYouquan Song }; 1983f62bae50SIngo Molnar 1984f62bae50SIngo Molnar /* First tickle the hardware, only then report what went on. -- REW */ 19852b398bd9SYouquan Song v0 = apic_read(APIC_ESR); 1986f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1987f62bae50SIngo Molnar v1 = apic_read(APIC_ESR); 1988f62bae50SIngo Molnar ack_APIC_irq(); 1989f62bae50SIngo Molnar atomic_inc(&irq_err_count); 1990f62bae50SIngo Molnar 19912b398bd9SYouquan Song apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x(%02x)", 19922b398bd9SYouquan Song smp_processor_id(), v0 , v1); 19932b398bd9SYouquan Song 19942b398bd9SYouquan Song v1 = v1 & 0xff; 19952b398bd9SYouquan Song while (v1) { 19962b398bd9SYouquan Song if (v1 & 0x1) 19972b398bd9SYouquan Song apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); 19982b398bd9SYouquan Song i++; 19992b398bd9SYouquan Song v1 >>= 1; 20004b8073e4SPeter Senna Tschudin } 20012b398bd9SYouquan Song 20022b398bd9SYouquan Song apic_printk(APIC_DEBUG, KERN_CONT "\n"); 20032b398bd9SYouquan Song 2004eddc0e92SSeiji Aguchi } 2005eddc0e92SSeiji Aguchi 20061d9090e2SAndi Kleen __visible void smp_error_interrupt(struct pt_regs *regs) 2007eddc0e92SSeiji Aguchi { 2008eddc0e92SSeiji Aguchi entering_irq(); 2009eddc0e92SSeiji Aguchi __smp_error_interrupt(regs); 2010eddc0e92SSeiji Aguchi exiting_irq(); 2011f62bae50SIngo Molnar } 2012f62bae50SIngo Molnar 20131d9090e2SAndi Kleen __visible void smp_trace_error_interrupt(struct pt_regs *regs) 2014cf910e83SSeiji Aguchi { 2015cf910e83SSeiji Aguchi entering_irq(); 2016cf910e83SSeiji Aguchi trace_error_apic_entry(ERROR_APIC_VECTOR); 2017cf910e83SSeiji Aguchi __smp_error_interrupt(regs); 2018cf910e83SSeiji Aguchi trace_error_apic_exit(ERROR_APIC_VECTOR); 2019cf910e83SSeiji Aguchi exiting_irq(); 2020f62bae50SIngo Molnar } 2021f62bae50SIngo Molnar 2022f62bae50SIngo Molnar /** 2023f62bae50SIngo Molnar * connect_bsp_APIC - attach the APIC to the interrupt system 2024f62bae50SIngo Molnar */ 2025f62bae50SIngo Molnar void __init connect_bsp_APIC(void) 2026f62bae50SIngo Molnar { 2027f62bae50SIngo Molnar #ifdef CONFIG_X86_32 2028f62bae50SIngo Molnar if (pic_mode) { 2029f62bae50SIngo Molnar /* 2030f62bae50SIngo Molnar * Do not trust the local APIC being empty at bootup. 2031f62bae50SIngo Molnar */ 2032f62bae50SIngo Molnar clear_local_APIC(); 2033f62bae50SIngo Molnar /* 2034f62bae50SIngo Molnar * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 2035f62bae50SIngo Molnar * local APIC to INT and NMI lines. 2036f62bae50SIngo Molnar */ 2037f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "leaving PIC mode, " 2038f62bae50SIngo Molnar "enabling APIC mode.\n"); 2039c0eaa453SCyrill Gorcunov imcr_pic_to_apic(); 2040f62bae50SIngo Molnar } 2041f62bae50SIngo Molnar #endif 2042f62bae50SIngo Molnar if (apic->enable_apic_mode) 2043f62bae50SIngo Molnar apic->enable_apic_mode(); 2044f62bae50SIngo Molnar } 2045f62bae50SIngo Molnar 2046f62bae50SIngo Molnar /** 2047f62bae50SIngo Molnar * disconnect_bsp_APIC - detach the APIC from the interrupt system 2048f62bae50SIngo Molnar * @virt_wire_setup: indicates, whether virtual wire mode is selected 2049f62bae50SIngo Molnar * 2050f62bae50SIngo Molnar * Virtual wire mode is necessary to deliver legacy interrupts even when the 2051f62bae50SIngo Molnar * APIC is disabled. 2052f62bae50SIngo Molnar */ 2053f62bae50SIngo Molnar void disconnect_bsp_APIC(int virt_wire_setup) 2054f62bae50SIngo Molnar { 2055f62bae50SIngo Molnar unsigned int value; 2056f62bae50SIngo Molnar 2057f62bae50SIngo Molnar #ifdef CONFIG_X86_32 2058f62bae50SIngo Molnar if (pic_mode) { 2059f62bae50SIngo Molnar /* 2060f62bae50SIngo Molnar * Put the board back into PIC mode (has an effect only on 2061f62bae50SIngo Molnar * certain older boards). Note that APIC interrupts, including 2062f62bae50SIngo Molnar * IPIs, won't work beyond this point! The only exception are 2063f62bae50SIngo Molnar * INIT IPIs. 2064f62bae50SIngo Molnar */ 2065f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "disabling APIC mode, " 2066f62bae50SIngo Molnar "entering PIC mode.\n"); 2067c0eaa453SCyrill Gorcunov imcr_apic_to_pic(); 2068f62bae50SIngo Molnar return; 2069f62bae50SIngo Molnar } 2070f62bae50SIngo Molnar #endif 2071f62bae50SIngo Molnar 2072f62bae50SIngo Molnar /* Go back to Virtual Wire compatibility mode */ 2073f62bae50SIngo Molnar 2074f62bae50SIngo Molnar /* For the spurious interrupt use vector F, and enable it */ 2075f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 2076f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 2077f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 2078f62bae50SIngo Molnar value |= 0xf; 2079f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 2080f62bae50SIngo Molnar 2081f62bae50SIngo Molnar if (!virt_wire_setup) { 2082f62bae50SIngo Molnar /* 2083f62bae50SIngo Molnar * For LVT0 make it edge triggered, active high, 2084f62bae50SIngo Molnar * external and enabled 2085f62bae50SIngo Molnar */ 2086f62bae50SIngo Molnar value = apic_read(APIC_LVT0); 2087f62bae50SIngo Molnar value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2088f62bae50SIngo Molnar APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2089f62bae50SIngo Molnar APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2090f62bae50SIngo Molnar value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2091f62bae50SIngo Molnar value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 2092f62bae50SIngo Molnar apic_write(APIC_LVT0, value); 2093f62bae50SIngo Molnar } else { 2094f62bae50SIngo Molnar /* Disable LVT0 */ 2095f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_LVT_MASKED); 2096f62bae50SIngo Molnar } 2097f62bae50SIngo Molnar 2098f62bae50SIngo Molnar /* 2099f62bae50SIngo Molnar * For LVT1 make it edge triggered, active high, 2100f62bae50SIngo Molnar * nmi and enabled 2101f62bae50SIngo Molnar */ 2102f62bae50SIngo Molnar value = apic_read(APIC_LVT1); 2103f62bae50SIngo Molnar value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2104f62bae50SIngo Molnar APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2105f62bae50SIngo Molnar APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2106f62bae50SIngo Molnar value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2107f62bae50SIngo Molnar value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 2108f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 2109f62bae50SIngo Molnar } 2110f62bae50SIngo Molnar 2111148f9bb8SPaul Gortmaker void generic_processor_info(int apicid, int version) 2112f62bae50SIngo Molnar { 211314cb6dcfSVivek Goyal int cpu, max = nr_cpu_ids; 211414cb6dcfSVivek Goyal bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, 211514cb6dcfSVivek Goyal phys_cpu_present_map); 211614cb6dcfSVivek Goyal 211714cb6dcfSVivek Goyal /* 211814cb6dcfSVivek Goyal * If boot cpu has not been detected yet, then only allow upto 211914cb6dcfSVivek Goyal * nr_cpu_ids - 1 processors and keep one slot free for boot cpu 212014cb6dcfSVivek Goyal */ 212114cb6dcfSVivek Goyal if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && 212214cb6dcfSVivek Goyal apicid != boot_cpu_physical_apicid) { 212314cb6dcfSVivek Goyal int thiscpu = max + disabled_cpus - 1; 212414cb6dcfSVivek Goyal 212514cb6dcfSVivek Goyal pr_warning( 212614cb6dcfSVivek Goyal "ACPI: NR_CPUS/possible_cpus limit of %i almost" 212714cb6dcfSVivek Goyal " reached. Keeping one slot for boot cpu." 212814cb6dcfSVivek Goyal " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 212914cb6dcfSVivek Goyal 213014cb6dcfSVivek Goyal disabled_cpus++; 213114cb6dcfSVivek Goyal return; 213214cb6dcfSVivek Goyal } 2133f62bae50SIngo Molnar 2134f62bae50SIngo Molnar if (num_processors >= nr_cpu_ids) { 2135f62bae50SIngo Molnar int thiscpu = max + disabled_cpus; 2136f62bae50SIngo Molnar 2137f62bae50SIngo Molnar pr_warning( 2138f62bae50SIngo Molnar "ACPI: NR_CPUS/possible_cpus limit of %i reached." 2139f62bae50SIngo Molnar " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2140f62bae50SIngo Molnar 2141f62bae50SIngo Molnar disabled_cpus++; 2142f62bae50SIngo Molnar return; 2143f62bae50SIngo Molnar } 2144f62bae50SIngo Molnar 2145f62bae50SIngo Molnar num_processors++; 2146f62bae50SIngo Molnar if (apicid == boot_cpu_physical_apicid) { 2147f62bae50SIngo Molnar /* 2148f62bae50SIngo Molnar * x86_bios_cpu_apicid is required to have processors listed 2149f62bae50SIngo Molnar * in same order as logical cpu numbers. Hence the first 2150f62bae50SIngo Molnar * entry is BSP, and so on. 2151e5fea868SYinghai Lu * boot_cpu_init() already hold bit 0 in cpu_present_mask 2152e5fea868SYinghai Lu * for BSP. 2153f62bae50SIngo Molnar */ 2154f62bae50SIngo Molnar cpu = 0; 2155e5fea868SYinghai Lu } else 2156e5fea868SYinghai Lu cpu = cpumask_next_zero(-1, cpu_present_mask); 2157e5fea868SYinghai Lu 2158e5fea868SYinghai Lu /* 2159e5fea868SYinghai Lu * Validate version 2160e5fea868SYinghai Lu */ 2161e5fea868SYinghai Lu if (version == 0x0) { 2162e5fea868SYinghai Lu pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", 2163e5fea868SYinghai Lu cpu, apicid); 2164e5fea868SYinghai Lu version = 0x10; 2165f62bae50SIngo Molnar } 2166e5fea868SYinghai Lu apic_version[apicid] = version; 2167e5fea868SYinghai Lu 2168e5fea868SYinghai Lu if (version != apic_version[boot_cpu_physical_apicid]) { 2169e5fea868SYinghai Lu pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", 2170e5fea868SYinghai Lu apic_version[boot_cpu_physical_apicid], cpu, version); 2171e5fea868SYinghai Lu } 2172e5fea868SYinghai Lu 2173e5fea868SYinghai Lu physid_set(apicid, phys_cpu_present_map); 2174f62bae50SIngo Molnar if (apicid > max_physical_apicid) 2175f62bae50SIngo Molnar max_physical_apicid = apicid; 2176f62bae50SIngo Molnar 2177f62bae50SIngo Molnar #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 2178f62bae50SIngo Molnar early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 2179f62bae50SIngo Molnar early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 2180f62bae50SIngo Molnar #endif 2181acb8bc09STejun Heo #ifdef CONFIG_X86_32 2182acb8bc09STejun Heo early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 2183acb8bc09STejun Heo apic->x86_32_early_logical_apicid(cpu); 2184acb8bc09STejun Heo #endif 2185f62bae50SIngo Molnar set_cpu_possible(cpu, true); 2186f62bae50SIngo Molnar set_cpu_present(cpu, true); 2187f62bae50SIngo Molnar } 2188f62bae50SIngo Molnar 2189f62bae50SIngo Molnar int hard_smp_processor_id(void) 2190f62bae50SIngo Molnar { 2191f62bae50SIngo Molnar return read_apic_id(); 2192f62bae50SIngo Molnar } 2193f62bae50SIngo Molnar 2194f62bae50SIngo Molnar void default_init_apic_ldr(void) 2195f62bae50SIngo Molnar { 2196f62bae50SIngo Molnar unsigned long val; 2197f62bae50SIngo Molnar 2198f62bae50SIngo Molnar apic_write(APIC_DFR, APIC_DFR_VALUE); 2199f62bae50SIngo Molnar val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; 2200f62bae50SIngo Molnar val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); 2201f62bae50SIngo Molnar apic_write(APIC_LDR, val); 2202f62bae50SIngo Molnar } 2203f62bae50SIngo Molnar 2204ff164324SAlexander Gordeev int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 2205ff164324SAlexander Gordeev const struct cpumask *andmask, 2206ff164324SAlexander Gordeev unsigned int *apicid) 22076398268dSAlexander Gordeev { 2208ea3807eaSAlexander Gordeev unsigned int cpu; 22096398268dSAlexander Gordeev 22106398268dSAlexander Gordeev for_each_cpu_and(cpu, cpumask, andmask) { 22116398268dSAlexander Gordeev if (cpumask_test_cpu(cpu, cpu_online_mask)) 22126398268dSAlexander Gordeev break; 22136398268dSAlexander Gordeev } 2214ff164324SAlexander Gordeev 2215ea3807eaSAlexander Gordeev if (likely(cpu < nr_cpu_ids)) { 2216a5a39156SAlexander Gordeev *apicid = per_cpu(x86_cpu_to_apicid, cpu); 2217a5a39156SAlexander Gordeev return 0; 2218a5a39156SAlexander Gordeev } 2219ea3807eaSAlexander Gordeev 2220ea3807eaSAlexander Gordeev return -EINVAL; 22216398268dSAlexander Gordeev } 22226398268dSAlexander Gordeev 2223f62bae50SIngo Molnar /* 22241551df64SMichael S. Tsirkin * Override the generic EOI implementation with an optimized version. 22251551df64SMichael S. Tsirkin * Only called during early boot when only one CPU is active and with 22261551df64SMichael S. Tsirkin * interrupts disabled, so we know this does not race with actual APIC driver 22271551df64SMichael S. Tsirkin * use. 22281551df64SMichael S. Tsirkin */ 22291551df64SMichael S. Tsirkin void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) 22301551df64SMichael S. Tsirkin { 22311551df64SMichael S. Tsirkin struct apic **drv; 22321551df64SMichael S. Tsirkin 22331551df64SMichael S. Tsirkin for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { 22341551df64SMichael S. Tsirkin /* Should happen once for each apic */ 22351551df64SMichael S. Tsirkin WARN_ON((*drv)->eoi_write == eoi_write); 22361551df64SMichael S. Tsirkin (*drv)->eoi_write = eoi_write; 22371551df64SMichael S. Tsirkin } 22381551df64SMichael S. Tsirkin } 22391551df64SMichael S. Tsirkin 22401551df64SMichael S. Tsirkin /* 2241f62bae50SIngo Molnar * Power management 2242f62bae50SIngo Molnar */ 2243f62bae50SIngo Molnar #ifdef CONFIG_PM 2244f62bae50SIngo Molnar 2245f62bae50SIngo Molnar static struct { 2246f62bae50SIngo Molnar /* 2247f62bae50SIngo Molnar * 'active' is true if the local APIC was enabled by us and 2248f62bae50SIngo Molnar * not the BIOS; this signifies that we are also responsible 2249f62bae50SIngo Molnar * for disabling it before entering apm/acpi suspend 2250f62bae50SIngo Molnar */ 2251f62bae50SIngo Molnar int active; 2252f62bae50SIngo Molnar /* r/w apic fields */ 2253f62bae50SIngo Molnar unsigned int apic_id; 2254f62bae50SIngo Molnar unsigned int apic_taskpri; 2255f62bae50SIngo Molnar unsigned int apic_ldr; 2256f62bae50SIngo Molnar unsigned int apic_dfr; 2257f62bae50SIngo Molnar unsigned int apic_spiv; 2258f62bae50SIngo Molnar unsigned int apic_lvtt; 2259f62bae50SIngo Molnar unsigned int apic_lvtpc; 2260f62bae50SIngo Molnar unsigned int apic_lvt0; 2261f62bae50SIngo Molnar unsigned int apic_lvt1; 2262f62bae50SIngo Molnar unsigned int apic_lvterr; 2263f62bae50SIngo Molnar unsigned int apic_tmict; 2264f62bae50SIngo Molnar unsigned int apic_tdcr; 2265f62bae50SIngo Molnar unsigned int apic_thmr; 2266f62bae50SIngo Molnar } apic_pm_state; 2267f62bae50SIngo Molnar 2268f3c6ea1bSRafael J. Wysocki static int lapic_suspend(void) 2269f62bae50SIngo Molnar { 2270f62bae50SIngo Molnar unsigned long flags; 2271f62bae50SIngo Molnar int maxlvt; 2272f62bae50SIngo Molnar 2273f62bae50SIngo Molnar if (!apic_pm_state.active) 2274f62bae50SIngo Molnar return 0; 2275f62bae50SIngo Molnar 2276f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 2277f62bae50SIngo Molnar 2278f62bae50SIngo Molnar apic_pm_state.apic_id = apic_read(APIC_ID); 2279f62bae50SIngo Molnar apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2280f62bae50SIngo Molnar apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2281f62bae50SIngo Molnar apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2282f62bae50SIngo Molnar apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2283f62bae50SIngo Molnar apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2284f62bae50SIngo Molnar if (maxlvt >= 4) 2285f62bae50SIngo Molnar apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2286f62bae50SIngo Molnar apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2287f62bae50SIngo Molnar apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2288f62bae50SIngo Molnar apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2289f62bae50SIngo Molnar apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2290f62bae50SIngo Molnar apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 22914efc0670SAndi Kleen #ifdef CONFIG_X86_THERMAL_VECTOR 2292f62bae50SIngo Molnar if (maxlvt >= 5) 2293f62bae50SIngo Molnar apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2294f62bae50SIngo Molnar #endif 2295f62bae50SIngo Molnar 2296f62bae50SIngo Molnar local_irq_save(flags); 2297f62bae50SIngo Molnar disable_local_APIC(); 2298fc1edaf9SSuresh Siddha 229995a02e97SSuresh Siddha irq_remapping_disable(); 2300fc1edaf9SSuresh Siddha 2301f62bae50SIngo Molnar local_irq_restore(flags); 2302f62bae50SIngo Molnar return 0; 2303f62bae50SIngo Molnar } 2304f62bae50SIngo Molnar 2305f3c6ea1bSRafael J. Wysocki static void lapic_resume(void) 2306f62bae50SIngo Molnar { 2307f62bae50SIngo Molnar unsigned int l, h; 2308f62bae50SIngo Molnar unsigned long flags; 230931dce14aSSuresh Siddha int maxlvt; 2310b24696bcSFenghua Yu 2311f62bae50SIngo Molnar if (!apic_pm_state.active) 2312f3c6ea1bSRafael J. Wysocki return; 2313f62bae50SIngo Molnar 2314b24696bcSFenghua Yu local_irq_save(flags); 2315336224baSJoerg Roedel 231631dce14aSSuresh Siddha /* 231731dce14aSSuresh Siddha * IO-APIC and PIC have their own resume routines. 231831dce14aSSuresh Siddha * We just mask them here to make sure the interrupt 231931dce14aSSuresh Siddha * subsystem is completely quiet while we enable x2apic 232031dce14aSSuresh Siddha * and interrupt-remapping. 232131dce14aSSuresh Siddha */ 232231dce14aSSuresh Siddha mask_ioapic_entries(); 2323b81bb373SJacob Pan legacy_pic->mask_all(); 2324f62bae50SIngo Molnar 2325fc1edaf9SSuresh Siddha if (x2apic_mode) 2326f62bae50SIngo Molnar enable_x2apic(); 2327cf6567feSSuresh Siddha else { 2328f62bae50SIngo Molnar /* 2329f62bae50SIngo Molnar * Make sure the APICBASE points to the right address 2330f62bae50SIngo Molnar * 2331f62bae50SIngo Molnar * FIXME! This will be wrong if we ever support suspend on 2332f62bae50SIngo Molnar * SMP! We'll need to do this as part of the CPU restore! 2333f62bae50SIngo Molnar */ 2334cbf2829bSBryan O'Donoghue if (boot_cpu_data.x86 >= 6) { 2335f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, l, h); 2336f62bae50SIngo Molnar l &= ~MSR_IA32_APICBASE_BASE; 2337f62bae50SIngo Molnar l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2338f62bae50SIngo Molnar wrmsr(MSR_IA32_APICBASE, l, h); 2339f62bae50SIngo Molnar } 2340cbf2829bSBryan O'Donoghue } 2341f62bae50SIngo Molnar 2342b24696bcSFenghua Yu maxlvt = lapic_get_maxlvt(); 2343f62bae50SIngo Molnar apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2344f62bae50SIngo Molnar apic_write(APIC_ID, apic_pm_state.apic_id); 2345f62bae50SIngo Molnar apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2346f62bae50SIngo Molnar apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2347f62bae50SIngo Molnar apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2348f62bae50SIngo Molnar apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2349f62bae50SIngo Molnar apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2350f62bae50SIngo Molnar apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 235171c69f7fSPaul Bolle #if defined(CONFIG_X86_MCE_INTEL) 2352f62bae50SIngo Molnar if (maxlvt >= 5) 2353f62bae50SIngo Molnar apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2354f62bae50SIngo Molnar #endif 2355f62bae50SIngo Molnar if (maxlvt >= 4) 2356f62bae50SIngo Molnar apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2357f62bae50SIngo Molnar apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2358f62bae50SIngo Molnar apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2359f62bae50SIngo Molnar apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2360f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 2361f62bae50SIngo Molnar apic_read(APIC_ESR); 2362f62bae50SIngo Molnar apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2363f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 2364f62bae50SIngo Molnar apic_read(APIC_ESR); 2365f62bae50SIngo Molnar 236695a02e97SSuresh Siddha irq_remapping_reenable(x2apic_mode); 236731dce14aSSuresh Siddha 2368f62bae50SIngo Molnar local_irq_restore(flags); 2369f62bae50SIngo Molnar } 2370f62bae50SIngo Molnar 2371f62bae50SIngo Molnar /* 2372f62bae50SIngo Molnar * This device has no shutdown method - fully functioning local APICs 2373f62bae50SIngo Molnar * are needed on every CPU up until machine_halt/restart/poweroff. 2374f62bae50SIngo Molnar */ 2375f62bae50SIngo Molnar 2376f3c6ea1bSRafael J. Wysocki static struct syscore_ops lapic_syscore_ops = { 2377f62bae50SIngo Molnar .resume = lapic_resume, 2378f62bae50SIngo Molnar .suspend = lapic_suspend, 2379f62bae50SIngo Molnar }; 2380f62bae50SIngo Molnar 2381148f9bb8SPaul Gortmaker static void apic_pm_activate(void) 2382f62bae50SIngo Molnar { 2383f62bae50SIngo Molnar apic_pm_state.active = 1; 2384f62bae50SIngo Molnar } 2385f62bae50SIngo Molnar 2386f62bae50SIngo Molnar static int __init init_lapic_sysfs(void) 2387f62bae50SIngo Molnar { 2388f62bae50SIngo Molnar /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2389f3c6ea1bSRafael J. Wysocki if (cpu_has_apic) 2390f3c6ea1bSRafael J. Wysocki register_syscore_ops(&lapic_syscore_ops); 2391f62bae50SIngo Molnar 2392f3c6ea1bSRafael J. Wysocki return 0; 2393f62bae50SIngo Molnar } 2394b24696bcSFenghua Yu 2395b24696bcSFenghua Yu /* local apic needs to resume before other devices access its registers. */ 2396b24696bcSFenghua Yu core_initcall(init_lapic_sysfs); 2397f62bae50SIngo Molnar 2398f62bae50SIngo Molnar #else /* CONFIG_PM */ 2399f62bae50SIngo Molnar 2400f62bae50SIngo Molnar static void apic_pm_activate(void) { } 2401f62bae50SIngo Molnar 2402f62bae50SIngo Molnar #endif /* CONFIG_PM */ 2403f62bae50SIngo Molnar 2404f62bae50SIngo Molnar #ifdef CONFIG_X86_64 2405e0e42142SYinghai Lu 2406148f9bb8SPaul Gortmaker static int apic_cluster_num(void) 2407f62bae50SIngo Molnar { 2408f62bae50SIngo Molnar int i, clusters, zeros; 2409f62bae50SIngo Molnar unsigned id; 2410f62bae50SIngo Molnar u16 *bios_cpu_apicid; 2411f62bae50SIngo Molnar DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); 2412f62bae50SIngo Molnar 2413f62bae50SIngo Molnar bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); 2414f62bae50SIngo Molnar bitmap_zero(clustermap, NUM_APIC_CLUSTERS); 2415f62bae50SIngo Molnar 2416f62bae50SIngo Molnar for (i = 0; i < nr_cpu_ids; i++) { 2417f62bae50SIngo Molnar /* are we being called early in kernel startup? */ 2418f62bae50SIngo Molnar if (bios_cpu_apicid) { 2419f62bae50SIngo Molnar id = bios_cpu_apicid[i]; 2420f62bae50SIngo Molnar } else if (i < nr_cpu_ids) { 2421f62bae50SIngo Molnar if (cpu_present(i)) 2422f62bae50SIngo Molnar id = per_cpu(x86_bios_cpu_apicid, i); 2423f62bae50SIngo Molnar else 2424f62bae50SIngo Molnar continue; 2425f62bae50SIngo Molnar } else 2426f62bae50SIngo Molnar break; 2427f62bae50SIngo Molnar 2428f62bae50SIngo Molnar if (id != BAD_APICID) 2429f62bae50SIngo Molnar __set_bit(APIC_CLUSTERID(id), clustermap); 2430f62bae50SIngo Molnar } 2431f62bae50SIngo Molnar 2432f62bae50SIngo Molnar /* Problem: Partially populated chassis may not have CPUs in some of 2433f62bae50SIngo Molnar * the APIC clusters they have been allocated. Only present CPUs have 2434f62bae50SIngo Molnar * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. 2435f62bae50SIngo Molnar * Since clusters are allocated sequentially, count zeros only if 2436f62bae50SIngo Molnar * they are bounded by ones. 2437f62bae50SIngo Molnar */ 2438f62bae50SIngo Molnar clusters = 0; 2439f62bae50SIngo Molnar zeros = 0; 2440f62bae50SIngo Molnar for (i = 0; i < NUM_APIC_CLUSTERS; i++) { 2441f62bae50SIngo Molnar if (test_bit(i, clustermap)) { 2442f62bae50SIngo Molnar clusters += 1 + zeros; 2443f62bae50SIngo Molnar zeros = 0; 2444f62bae50SIngo Molnar } else 2445f62bae50SIngo Molnar ++zeros; 2446f62bae50SIngo Molnar } 2447f62bae50SIngo Molnar 2448e0e42142SYinghai Lu return clusters; 2449e0e42142SYinghai Lu } 2450e0e42142SYinghai Lu 2451148f9bb8SPaul Gortmaker static int multi_checked; 2452148f9bb8SPaul Gortmaker static int multi; 2453e0e42142SYinghai Lu 2454148f9bb8SPaul Gortmaker static int set_multi(const struct dmi_system_id *d) 2455e0e42142SYinghai Lu { 2456e0e42142SYinghai Lu if (multi) 2457e0e42142SYinghai Lu return 0; 24586f0aced6SCyrill Gorcunov pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2459e0e42142SYinghai Lu multi = 1; 2460e0e42142SYinghai Lu return 0; 2461e0e42142SYinghai Lu } 2462e0e42142SYinghai Lu 2463148f9bb8SPaul Gortmaker static const struct dmi_system_id multi_dmi_table[] = { 2464e0e42142SYinghai Lu { 2465e0e42142SYinghai Lu .callback = set_multi, 2466e0e42142SYinghai Lu .ident = "IBM System Summit2", 2467e0e42142SYinghai Lu .matches = { 2468e0e42142SYinghai Lu DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2469e0e42142SYinghai Lu DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2470e0e42142SYinghai Lu }, 2471e0e42142SYinghai Lu }, 2472e0e42142SYinghai Lu {} 2473e0e42142SYinghai Lu }; 2474e0e42142SYinghai Lu 2475148f9bb8SPaul Gortmaker static void dmi_check_multi(void) 2476e0e42142SYinghai Lu { 2477e0e42142SYinghai Lu if (multi_checked) 2478e0e42142SYinghai Lu return; 2479e0e42142SYinghai Lu 2480e0e42142SYinghai Lu dmi_check_system(multi_dmi_table); 2481e0e42142SYinghai Lu multi_checked = 1; 2482e0e42142SYinghai Lu } 2483f62bae50SIngo Molnar 2484f62bae50SIngo Molnar /* 2485e0e42142SYinghai Lu * apic_is_clustered_box() -- Check if we can expect good TSC 2486e0e42142SYinghai Lu * 2487e0e42142SYinghai Lu * Thus far, the major user of this is IBM's Summit2 series: 2488e0e42142SYinghai Lu * Clustered boxes may have unsynced TSC problems if they are 2489e0e42142SYinghai Lu * multi-chassis. 2490e0e42142SYinghai Lu * Use DMI to check them 2491f62bae50SIngo Molnar */ 2492148f9bb8SPaul Gortmaker int apic_is_clustered_box(void) 2493e0e42142SYinghai Lu { 2494e0e42142SYinghai Lu dmi_check_multi(); 2495e0e42142SYinghai Lu if (multi) 2496e0e42142SYinghai Lu return 1; 2497e0e42142SYinghai Lu 2498e0e42142SYinghai Lu if (!is_vsmp_box()) 2499e0e42142SYinghai Lu return 0; 2500e0e42142SYinghai Lu 2501e0e42142SYinghai Lu /* 2502e0e42142SYinghai Lu * ScaleMP vSMPowered boxes have one cluster per board and TSCs are 2503e0e42142SYinghai Lu * not guaranteed to be synced between boards 2504e0e42142SYinghai Lu */ 2505e0e42142SYinghai Lu if (apic_cluster_num() > 1) 2506e0e42142SYinghai Lu return 1; 2507e0e42142SYinghai Lu 2508e0e42142SYinghai Lu return 0; 2509f62bae50SIngo Molnar } 2510f62bae50SIngo Molnar #endif 2511f62bae50SIngo Molnar 2512f62bae50SIngo Molnar /* 2513f62bae50SIngo Molnar * APIC command line parameters 2514f62bae50SIngo Molnar */ 2515f62bae50SIngo Molnar static int __init setup_disableapic(char *arg) 2516f62bae50SIngo Molnar { 2517f62bae50SIngo Molnar disable_apic = 1; 2518f62bae50SIngo Molnar setup_clear_cpu_cap(X86_FEATURE_APIC); 2519f62bae50SIngo Molnar return 0; 2520f62bae50SIngo Molnar } 2521f62bae50SIngo Molnar early_param("disableapic", setup_disableapic); 2522f62bae50SIngo Molnar 2523f62bae50SIngo Molnar /* same as disableapic, for compatibility */ 2524f62bae50SIngo Molnar static int __init setup_nolapic(char *arg) 2525f62bae50SIngo Molnar { 2526f62bae50SIngo Molnar return setup_disableapic(arg); 2527f62bae50SIngo Molnar } 2528f62bae50SIngo Molnar early_param("nolapic", setup_nolapic); 2529f62bae50SIngo Molnar 2530f62bae50SIngo Molnar static int __init parse_lapic_timer_c2_ok(char *arg) 2531f62bae50SIngo Molnar { 2532f62bae50SIngo Molnar local_apic_timer_c2_ok = 1; 2533f62bae50SIngo Molnar return 0; 2534f62bae50SIngo Molnar } 2535f62bae50SIngo Molnar early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2536f62bae50SIngo Molnar 2537f62bae50SIngo Molnar static int __init parse_disable_apic_timer(char *arg) 2538f62bae50SIngo Molnar { 2539f62bae50SIngo Molnar disable_apic_timer = 1; 2540f62bae50SIngo Molnar return 0; 2541f62bae50SIngo Molnar } 2542f62bae50SIngo Molnar early_param("noapictimer", parse_disable_apic_timer); 2543f62bae50SIngo Molnar 2544f62bae50SIngo Molnar static int __init parse_nolapic_timer(char *arg) 2545f62bae50SIngo Molnar { 2546f62bae50SIngo Molnar disable_apic_timer = 1; 2547f62bae50SIngo Molnar return 0; 2548f62bae50SIngo Molnar } 2549f62bae50SIngo Molnar early_param("nolapic_timer", parse_nolapic_timer); 2550f62bae50SIngo Molnar 2551f62bae50SIngo Molnar static int __init apic_set_verbosity(char *arg) 2552f62bae50SIngo Molnar { 2553f62bae50SIngo Molnar if (!arg) { 2554f62bae50SIngo Molnar #ifdef CONFIG_X86_64 2555f62bae50SIngo Molnar skip_ioapic_setup = 0; 2556f62bae50SIngo Molnar return 0; 2557f62bae50SIngo Molnar #endif 2558f62bae50SIngo Molnar return -EINVAL; 2559f62bae50SIngo Molnar } 2560f62bae50SIngo Molnar 2561f62bae50SIngo Molnar if (strcmp("debug", arg) == 0) 2562f62bae50SIngo Molnar apic_verbosity = APIC_DEBUG; 2563f62bae50SIngo Molnar else if (strcmp("verbose", arg) == 0) 2564f62bae50SIngo Molnar apic_verbosity = APIC_VERBOSE; 2565f62bae50SIngo Molnar else { 2566f62bae50SIngo Molnar pr_warning("APIC Verbosity level %s not recognised" 2567f62bae50SIngo Molnar " use apic=verbose or apic=debug\n", arg); 2568f62bae50SIngo Molnar return -EINVAL; 2569f62bae50SIngo Molnar } 2570f62bae50SIngo Molnar 2571f62bae50SIngo Molnar return 0; 2572f62bae50SIngo Molnar } 2573f62bae50SIngo Molnar early_param("apic", apic_set_verbosity); 2574f62bae50SIngo Molnar 2575f62bae50SIngo Molnar static int __init lapic_insert_resource(void) 2576f62bae50SIngo Molnar { 2577f62bae50SIngo Molnar if (!apic_phys) 2578f62bae50SIngo Molnar return -1; 2579f62bae50SIngo Molnar 2580f62bae50SIngo Molnar /* Put local APIC into the resource map. */ 2581f62bae50SIngo Molnar lapic_resource.start = apic_phys; 2582f62bae50SIngo Molnar lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2583f62bae50SIngo Molnar insert_resource(&iomem_resource, &lapic_resource); 2584f62bae50SIngo Molnar 2585f62bae50SIngo Molnar return 0; 2586f62bae50SIngo Molnar } 2587f62bae50SIngo Molnar 2588f62bae50SIngo Molnar /* 2589f62bae50SIngo Molnar * need call insert after e820_reserve_resources() 2590f62bae50SIngo Molnar * that is using request_resource 2591f62bae50SIngo Molnar */ 2592f62bae50SIngo Molnar late_initcall(lapic_insert_resource); 2593