1f62bae50SIngo Molnar /* 2f62bae50SIngo Molnar * Local APIC handling, local APIC timers 3f62bae50SIngo Molnar * 4f62bae50SIngo Molnar * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 5f62bae50SIngo Molnar * 6f62bae50SIngo Molnar * Fixes 7f62bae50SIngo Molnar * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8f62bae50SIngo Molnar * thanks to Eric Gilmore 9f62bae50SIngo Molnar * and Rolf G. Tews 10f62bae50SIngo Molnar * for testing these extensively. 11f62bae50SIngo Molnar * Maciej W. Rozycki : Various updates and fixes. 12f62bae50SIngo Molnar * Mikael Pettersson : Power Management for UP-APIC. 13f62bae50SIngo Molnar * Pavel Machek and 14f62bae50SIngo Molnar * Mikael Pettersson : PM converted to driver model. 15f62bae50SIngo Molnar */ 16f62bae50SIngo Molnar 17cdd6c482SIngo Molnar #include <linux/perf_event.h> 18f62bae50SIngo Molnar #include <linux/kernel_stat.h> 19f62bae50SIngo Molnar #include <linux/mc146818rtc.h> 20f62bae50SIngo Molnar #include <linux/acpi_pmtmr.h> 21f62bae50SIngo Molnar #include <linux/clockchips.h> 22f62bae50SIngo Molnar #include <linux/interrupt.h> 23f62bae50SIngo Molnar #include <linux/bootmem.h> 24f62bae50SIngo Molnar #include <linux/ftrace.h> 25f62bae50SIngo Molnar #include <linux/ioport.h> 26f62bae50SIngo Molnar #include <linux/module.h> 27f62bae50SIngo Molnar #include <linux/sysdev.h> 28f62bae50SIngo Molnar #include <linux/delay.h> 29f62bae50SIngo Molnar #include <linux/timex.h> 30f62bae50SIngo Molnar #include <linux/dmar.h> 31f62bae50SIngo Molnar #include <linux/init.h> 32f62bae50SIngo Molnar #include <linux/cpu.h> 33f62bae50SIngo Molnar #include <linux/dmi.h> 34f62bae50SIngo Molnar #include <linux/smp.h> 35f62bae50SIngo Molnar #include <linux/mm.h> 36f62bae50SIngo Molnar 37cdd6c482SIngo Molnar #include <asm/perf_event.h> 38736decacSThomas Gleixner #include <asm/x86_init.h> 39f62bae50SIngo Molnar #include <asm/pgalloc.h> 40f62bae50SIngo Molnar #include <asm/atomic.h> 41f62bae50SIngo Molnar #include <asm/mpspec.h> 42f62bae50SIngo Molnar #include <asm/i8253.h> 43f62bae50SIngo Molnar #include <asm/i8259.h> 44f62bae50SIngo Molnar #include <asm/proto.h> 45f62bae50SIngo Molnar #include <asm/apic.h> 46f62bae50SIngo Molnar #include <asm/desc.h> 47f62bae50SIngo Molnar #include <asm/hpet.h> 48f62bae50SIngo Molnar #include <asm/idle.h> 49f62bae50SIngo Molnar #include <asm/mtrr.h> 50f62bae50SIngo Molnar #include <asm/smp.h> 51638bee71SH. Peter Anvin #include <asm/mce.h> 528c3ba8d0SKerstin Jonsson #include <asm/tsc.h> 532904ed8dSSheng Yang #include <asm/hypervisor.h> 54f62bae50SIngo Molnar 55f62bae50SIngo Molnar unsigned int num_processors; 56f62bae50SIngo Molnar 57f62bae50SIngo Molnar unsigned disabled_cpus __cpuinitdata; 58f62bae50SIngo Molnar 59f62bae50SIngo Molnar /* Processor that is doing the boot up */ 60f62bae50SIngo Molnar unsigned int boot_cpu_physical_apicid = -1U; 61f62bae50SIngo Molnar 62f62bae50SIngo Molnar /* 63f62bae50SIngo Molnar * The highest APIC ID seen during enumeration. 64f62bae50SIngo Molnar */ 65f62bae50SIngo Molnar unsigned int max_physical_apicid; 66f62bae50SIngo Molnar 67f62bae50SIngo Molnar /* 68f62bae50SIngo Molnar * Bitmask of physically existing CPUs: 69f62bae50SIngo Molnar */ 70f62bae50SIngo Molnar physid_mask_t phys_cpu_present_map; 71f62bae50SIngo Molnar 72f62bae50SIngo Molnar /* 73f62bae50SIngo Molnar * Map cpu index to physical APIC ID 74f62bae50SIngo Molnar */ 75f62bae50SIngo Molnar DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID); 76f62bae50SIngo Molnar DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID); 77f62bae50SIngo Molnar EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 78f62bae50SIngo Molnar EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 79f62bae50SIngo Molnar 80f62bae50SIngo Molnar #ifdef CONFIG_X86_32 814c321ff8STejun Heo 824c321ff8STejun Heo #ifdef CONFIG_SMP 834c321ff8STejun Heo /* 844c321ff8STejun Heo * On x86_32, the mapping between cpu and logical apicid may vary 854c321ff8STejun Heo * depending on apic in use. The following early percpu variable is 864c321ff8STejun Heo * used for the mapping. This is where the behaviors of x86_64 and 32 874c321ff8STejun Heo * actually diverge. Let's keep it ugly for now. 884c321ff8STejun Heo */ 894c321ff8STejun Heo DEFINE_EARLY_PER_CPU(int, x86_cpu_to_logical_apicid, BAD_APICID); 904c321ff8STejun Heo #endif 914c321ff8STejun Heo 92f62bae50SIngo Molnar /* 93f62bae50SIngo Molnar * Knob to control our willingness to enable the local APIC. 94f62bae50SIngo Molnar * 95f62bae50SIngo Molnar * +1=force-enable 96f62bae50SIngo Molnar */ 97f62bae50SIngo Molnar static int force_enable_local_apic; 98f62bae50SIngo Molnar /* 99f62bae50SIngo Molnar * APIC command line parameters 100f62bae50SIngo Molnar */ 101f62bae50SIngo Molnar static int __init parse_lapic(char *arg) 102f62bae50SIngo Molnar { 103f62bae50SIngo Molnar force_enable_local_apic = 1; 104f62bae50SIngo Molnar return 0; 105f62bae50SIngo Molnar } 106f62bae50SIngo Molnar early_param("lapic", parse_lapic); 107f62bae50SIngo Molnar /* Local APIC was disabled by the BIOS and enabled by the kernel */ 108f62bae50SIngo Molnar static int enabled_via_apicbase; 109f62bae50SIngo Molnar 110c0eaa453SCyrill Gorcunov /* 111c0eaa453SCyrill Gorcunov * Handle interrupt mode configuration register (IMCR). 112c0eaa453SCyrill Gorcunov * This register controls whether the interrupt signals 113c0eaa453SCyrill Gorcunov * that reach the BSP come from the master PIC or from the 114c0eaa453SCyrill Gorcunov * local APIC. Before entering Symmetric I/O Mode, either 115c0eaa453SCyrill Gorcunov * the BIOS or the operating system must switch out of 116c0eaa453SCyrill Gorcunov * PIC Mode by changing the IMCR. 117c0eaa453SCyrill Gorcunov */ 1185cda395fSAlexander van Heukelum static inline void imcr_pic_to_apic(void) 119c0eaa453SCyrill Gorcunov { 120c0eaa453SCyrill Gorcunov /* select IMCR register */ 121c0eaa453SCyrill Gorcunov outb(0x70, 0x22); 122c0eaa453SCyrill Gorcunov /* NMI and 8259 INTR go through APIC */ 123c0eaa453SCyrill Gorcunov outb(0x01, 0x23); 124c0eaa453SCyrill Gorcunov } 125c0eaa453SCyrill Gorcunov 1265cda395fSAlexander van Heukelum static inline void imcr_apic_to_pic(void) 127c0eaa453SCyrill Gorcunov { 128c0eaa453SCyrill Gorcunov /* select IMCR register */ 129c0eaa453SCyrill Gorcunov outb(0x70, 0x22); 130c0eaa453SCyrill Gorcunov /* NMI and 8259 INTR go directly to BSP */ 131c0eaa453SCyrill Gorcunov outb(0x00, 0x23); 132c0eaa453SCyrill Gorcunov } 133f62bae50SIngo Molnar #endif 134f62bae50SIngo Molnar 135f62bae50SIngo Molnar #ifdef CONFIG_X86_64 136f62bae50SIngo Molnar static int apic_calibrate_pmtmr __initdata; 137f62bae50SIngo Molnar static __init int setup_apicpmtimer(char *s) 138f62bae50SIngo Molnar { 139f62bae50SIngo Molnar apic_calibrate_pmtmr = 1; 140f62bae50SIngo Molnar notsc_setup(NULL); 141f62bae50SIngo Molnar return 0; 142f62bae50SIngo Molnar } 143f62bae50SIngo Molnar __setup("apicpmtimer", setup_apicpmtimer); 144f62bae50SIngo Molnar #endif 145f62bae50SIngo Molnar 146fc1edaf9SSuresh Siddha int x2apic_mode; 147f62bae50SIngo Molnar #ifdef CONFIG_X86_X2APIC 148f62bae50SIngo Molnar /* x2apic enabled before OS handover */ 149f62bae50SIngo Molnar static int x2apic_preenabled; 150f62bae50SIngo Molnar static __init int setup_nox2apic(char *str) 151f62bae50SIngo Molnar { 15239d83a5dSSuresh Siddha if (x2apic_enabled()) { 15339d83a5dSSuresh Siddha pr_warning("Bios already enabled x2apic, " 15439d83a5dSSuresh Siddha "can't enforce nox2apic"); 15539d83a5dSSuresh Siddha return 0; 15639d83a5dSSuresh Siddha } 15739d83a5dSSuresh Siddha 158f62bae50SIngo Molnar setup_clear_cpu_cap(X86_FEATURE_X2APIC); 159f62bae50SIngo Molnar return 0; 160f62bae50SIngo Molnar } 161f62bae50SIngo Molnar early_param("nox2apic", setup_nox2apic); 162f62bae50SIngo Molnar #endif 163f62bae50SIngo Molnar 164f62bae50SIngo Molnar unsigned long mp_lapic_addr; 165f62bae50SIngo Molnar int disable_apic; 166f62bae50SIngo Molnar /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 167f62bae50SIngo Molnar static int disable_apic_timer __cpuinitdata; 168f62bae50SIngo Molnar /* Local APIC timer works in C2 */ 169f62bae50SIngo Molnar int local_apic_timer_c2_ok; 170f62bae50SIngo Molnar EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 171f62bae50SIngo Molnar 172f62bae50SIngo Molnar int first_system_vector = 0xfe; 173f62bae50SIngo Molnar 174f62bae50SIngo Molnar /* 175f62bae50SIngo Molnar * Debug level, exported for io_apic.c 176f62bae50SIngo Molnar */ 177f62bae50SIngo Molnar unsigned int apic_verbosity; 178f62bae50SIngo Molnar 179f62bae50SIngo Molnar int pic_mode; 180f62bae50SIngo Molnar 181f62bae50SIngo Molnar /* Have we found an MP table */ 182f62bae50SIngo Molnar int smp_found_config; 183f62bae50SIngo Molnar 184f62bae50SIngo Molnar static struct resource lapic_resource = { 185f62bae50SIngo Molnar .name = "Local APIC", 186f62bae50SIngo Molnar .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 187f62bae50SIngo Molnar }; 188f62bae50SIngo Molnar 189f62bae50SIngo Molnar static unsigned int calibration_result; 190f62bae50SIngo Molnar 191f62bae50SIngo Molnar static int lapic_next_event(unsigned long delta, 192f62bae50SIngo Molnar struct clock_event_device *evt); 193f62bae50SIngo Molnar static void lapic_timer_setup(enum clock_event_mode mode, 194f62bae50SIngo Molnar struct clock_event_device *evt); 195f62bae50SIngo Molnar static void lapic_timer_broadcast(const struct cpumask *mask); 196f62bae50SIngo Molnar static void apic_pm_activate(void); 197f62bae50SIngo Molnar 198f62bae50SIngo Molnar /* 199f62bae50SIngo Molnar * The local apic timer can be used for any function which is CPU local. 200f62bae50SIngo Molnar */ 201f62bae50SIngo Molnar static struct clock_event_device lapic_clockevent = { 202f62bae50SIngo Molnar .name = "lapic", 203f62bae50SIngo Molnar .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT 204f62bae50SIngo Molnar | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, 205f62bae50SIngo Molnar .shift = 32, 206f62bae50SIngo Molnar .set_mode = lapic_timer_setup, 207f62bae50SIngo Molnar .set_next_event = lapic_next_event, 208f62bae50SIngo Molnar .broadcast = lapic_timer_broadcast, 209f62bae50SIngo Molnar .rating = 100, 210f62bae50SIngo Molnar .irq = -1, 211f62bae50SIngo Molnar }; 212f62bae50SIngo Molnar static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 213f62bae50SIngo Molnar 214f62bae50SIngo Molnar static unsigned long apic_phys; 215f62bae50SIngo Molnar 216f62bae50SIngo Molnar /* 217f62bae50SIngo Molnar * Get the LAPIC version 218f62bae50SIngo Molnar */ 219f62bae50SIngo Molnar static inline int lapic_get_version(void) 220f62bae50SIngo Molnar { 221f62bae50SIngo Molnar return GET_APIC_VERSION(apic_read(APIC_LVR)); 222f62bae50SIngo Molnar } 223f62bae50SIngo Molnar 224f62bae50SIngo Molnar /* 225f62bae50SIngo Molnar * Check, if the APIC is integrated or a separate chip 226f62bae50SIngo Molnar */ 227f62bae50SIngo Molnar static inline int lapic_is_integrated(void) 228f62bae50SIngo Molnar { 229f62bae50SIngo Molnar #ifdef CONFIG_X86_64 230f62bae50SIngo Molnar return 1; 231f62bae50SIngo Molnar #else 232f62bae50SIngo Molnar return APIC_INTEGRATED(lapic_get_version()); 233f62bae50SIngo Molnar #endif 234f62bae50SIngo Molnar } 235f62bae50SIngo Molnar 236f62bae50SIngo Molnar /* 237f62bae50SIngo Molnar * Check, whether this is a modern or a first generation APIC 238f62bae50SIngo Molnar */ 239f62bae50SIngo Molnar static int modern_apic(void) 240f62bae50SIngo Molnar { 241f62bae50SIngo Molnar /* AMD systems use old APIC versions, so check the CPU */ 242f62bae50SIngo Molnar if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 243f62bae50SIngo Molnar boot_cpu_data.x86 >= 0xf) 244f62bae50SIngo Molnar return 1; 245f62bae50SIngo Molnar return lapic_get_version() >= 0x14; 246f62bae50SIngo Molnar } 247f62bae50SIngo Molnar 24808306ce6SCyrill Gorcunov /* 249a933c618SCyrill Gorcunov * right after this call apic become NOOP driven 250a933c618SCyrill Gorcunov * so apic->write/read doesn't do anything 25108306ce6SCyrill Gorcunov */ 25208306ce6SCyrill Gorcunov void apic_disable(void) 25308306ce6SCyrill Gorcunov { 254f88f2b4fSCyrill Gorcunov pr_info("APIC: switched to apic NOOP\n"); 255a933c618SCyrill Gorcunov apic = &apic_noop; 25608306ce6SCyrill Gorcunov } 25708306ce6SCyrill Gorcunov 258f62bae50SIngo Molnar void native_apic_wait_icr_idle(void) 259f62bae50SIngo Molnar { 260f62bae50SIngo Molnar while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 261f62bae50SIngo Molnar cpu_relax(); 262f62bae50SIngo Molnar } 263f62bae50SIngo Molnar 264f62bae50SIngo Molnar u32 native_safe_apic_wait_icr_idle(void) 265f62bae50SIngo Molnar { 266f62bae50SIngo Molnar u32 send_status; 267f62bae50SIngo Molnar int timeout; 268f62bae50SIngo Molnar 269f62bae50SIngo Molnar timeout = 0; 270f62bae50SIngo Molnar do { 271f62bae50SIngo Molnar send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 272f62bae50SIngo Molnar if (!send_status) 273f62bae50SIngo Molnar break; 274f62bae50SIngo Molnar udelay(100); 275f62bae50SIngo Molnar } while (timeout++ < 1000); 276f62bae50SIngo Molnar 277f62bae50SIngo Molnar return send_status; 278f62bae50SIngo Molnar } 279f62bae50SIngo Molnar 280f62bae50SIngo Molnar void native_apic_icr_write(u32 low, u32 id) 281f62bae50SIngo Molnar { 282f62bae50SIngo Molnar apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 283f62bae50SIngo Molnar apic_write(APIC_ICR, low); 284f62bae50SIngo Molnar } 285f62bae50SIngo Molnar 286f62bae50SIngo Molnar u64 native_apic_icr_read(void) 287f62bae50SIngo Molnar { 288f62bae50SIngo Molnar u32 icr1, icr2; 289f62bae50SIngo Molnar 290f62bae50SIngo Molnar icr2 = apic_read(APIC_ICR2); 291f62bae50SIngo Molnar icr1 = apic_read(APIC_ICR); 292f62bae50SIngo Molnar 293f62bae50SIngo Molnar return icr1 | ((u64)icr2 << 32); 294f62bae50SIngo Molnar } 295f62bae50SIngo Molnar 296f62bae50SIngo Molnar /** 297f62bae50SIngo Molnar * enable_NMI_through_LVT0 - enable NMI through local vector table 0 298f62bae50SIngo Molnar */ 299f62bae50SIngo Molnar void __cpuinit enable_NMI_through_LVT0(void) 300f62bae50SIngo Molnar { 301f62bae50SIngo Molnar unsigned int v; 302f62bae50SIngo Molnar 303f62bae50SIngo Molnar /* unmask and set to NMI */ 304f62bae50SIngo Molnar v = APIC_DM_NMI; 305f62bae50SIngo Molnar 306f62bae50SIngo Molnar /* Level triggered for 82489DX (32bit mode) */ 307f62bae50SIngo Molnar if (!lapic_is_integrated()) 308f62bae50SIngo Molnar v |= APIC_LVT_LEVEL_TRIGGER; 309f62bae50SIngo Molnar 310f62bae50SIngo Molnar apic_write(APIC_LVT0, v); 311f62bae50SIngo Molnar } 312f62bae50SIngo Molnar 313f62bae50SIngo Molnar #ifdef CONFIG_X86_32 314f62bae50SIngo Molnar /** 315f62bae50SIngo Molnar * get_physical_broadcast - Get number of physical broadcast IDs 316f62bae50SIngo Molnar */ 317f62bae50SIngo Molnar int get_physical_broadcast(void) 318f62bae50SIngo Molnar { 319f62bae50SIngo Molnar return modern_apic() ? 0xff : 0xf; 320f62bae50SIngo Molnar } 321f62bae50SIngo Molnar #endif 322f62bae50SIngo Molnar 323f62bae50SIngo Molnar /** 324f62bae50SIngo Molnar * lapic_get_maxlvt - get the maximum number of local vector table entries 325f62bae50SIngo Molnar */ 326f62bae50SIngo Molnar int lapic_get_maxlvt(void) 327f62bae50SIngo Molnar { 328f62bae50SIngo Molnar unsigned int v; 329f62bae50SIngo Molnar 330f62bae50SIngo Molnar v = apic_read(APIC_LVR); 331f62bae50SIngo Molnar /* 332f62bae50SIngo Molnar * - we always have APIC integrated on 64bit mode 333f62bae50SIngo Molnar * - 82489DXs do not report # of LVT entries 334f62bae50SIngo Molnar */ 335f62bae50SIngo Molnar return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; 336f62bae50SIngo Molnar } 337f62bae50SIngo Molnar 338f62bae50SIngo Molnar /* 339f62bae50SIngo Molnar * Local APIC timer 340f62bae50SIngo Molnar */ 341f62bae50SIngo Molnar 342f62bae50SIngo Molnar /* Clock divisor */ 343f62bae50SIngo Molnar #define APIC_DIVISOR 16 344f62bae50SIngo Molnar 345f62bae50SIngo Molnar /* 346f62bae50SIngo Molnar * This function sets up the local APIC timer, with a timeout of 347f62bae50SIngo Molnar * 'clocks' APIC bus clock. During calibration we actually call 348f62bae50SIngo Molnar * this function twice on the boot CPU, once with a bogus timeout 349f62bae50SIngo Molnar * value, second time for real. The other (noncalibrating) CPUs 350f62bae50SIngo Molnar * call this function only once, with the real, calibrated value. 351f62bae50SIngo Molnar * 352f62bae50SIngo Molnar * We do reads before writes even if unnecessary, to get around the 353f62bae50SIngo Molnar * P5 APIC double write bug. 354f62bae50SIngo Molnar */ 355f62bae50SIngo Molnar static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 356f62bae50SIngo Molnar { 357f62bae50SIngo Molnar unsigned int lvtt_value, tmp_value; 358f62bae50SIngo Molnar 359f62bae50SIngo Molnar lvtt_value = LOCAL_TIMER_VECTOR; 360f62bae50SIngo Molnar if (!oneshot) 361f62bae50SIngo Molnar lvtt_value |= APIC_LVT_TIMER_PERIODIC; 362f62bae50SIngo Molnar if (!lapic_is_integrated()) 363f62bae50SIngo Molnar lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 364f62bae50SIngo Molnar 365f62bae50SIngo Molnar if (!irqen) 366f62bae50SIngo Molnar lvtt_value |= APIC_LVT_MASKED; 367f62bae50SIngo Molnar 368f62bae50SIngo Molnar apic_write(APIC_LVTT, lvtt_value); 369f62bae50SIngo Molnar 370f62bae50SIngo Molnar /* 371f62bae50SIngo Molnar * Divide PICLK by 16 372f62bae50SIngo Molnar */ 373f62bae50SIngo Molnar tmp_value = apic_read(APIC_TDCR); 374f62bae50SIngo Molnar apic_write(APIC_TDCR, 375f62bae50SIngo Molnar (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 376f62bae50SIngo Molnar APIC_TDR_DIV_16); 377f62bae50SIngo Molnar 378f62bae50SIngo Molnar if (!oneshot) 379f62bae50SIngo Molnar apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 380f62bae50SIngo Molnar } 381f62bae50SIngo Molnar 382f62bae50SIngo Molnar /* 383a68c439bSRobert Richter * Setup extended LVT, AMD specific 384f62bae50SIngo Molnar * 385a68c439bSRobert Richter * Software should use the LVT offsets the BIOS provides. The offsets 386a68c439bSRobert Richter * are determined by the subsystems using it like those for MCE 387a68c439bSRobert Richter * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 388a68c439bSRobert Richter * are supported. Beginning with family 10h at least 4 offsets are 389a68c439bSRobert Richter * available. 390f62bae50SIngo Molnar * 391a68c439bSRobert Richter * Since the offsets must be consistent for all cores, we keep track 392a68c439bSRobert Richter * of the LVT offsets in software and reserve the offset for the same 393a68c439bSRobert Richter * vector also to be used on other cores. An offset is freed by 394a68c439bSRobert Richter * setting the entry to APIC_EILVT_MASKED. 395a68c439bSRobert Richter * 396a68c439bSRobert Richter * If the BIOS is right, there should be no conflicts. Otherwise a 397a68c439bSRobert Richter * "[Firmware Bug]: ..." error message is generated. However, if 398a68c439bSRobert Richter * software does not properly determines the offsets, it is not 399a68c439bSRobert Richter * necessarily a BIOS bug. 400f62bae50SIngo Molnar */ 401f62bae50SIngo Molnar 402a68c439bSRobert Richter static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 403f62bae50SIngo Molnar 404a68c439bSRobert Richter static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 405a68c439bSRobert Richter { 406a68c439bSRobert Richter return (old & APIC_EILVT_MASKED) 407a68c439bSRobert Richter || (new == APIC_EILVT_MASKED) 408a68c439bSRobert Richter || ((new & ~APIC_EILVT_MASKED) == old); 409a68c439bSRobert Richter } 410a68c439bSRobert Richter 411a68c439bSRobert Richter static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 412a68c439bSRobert Richter { 413a68c439bSRobert Richter unsigned int rsvd; /* 0: uninitialized */ 414a68c439bSRobert Richter 415a68c439bSRobert Richter if (offset >= APIC_EILVT_NR_MAX) 416a68c439bSRobert Richter return ~0; 417a68c439bSRobert Richter 418a68c439bSRobert Richter rsvd = atomic_read(&eilvt_offsets[offset]) & ~APIC_EILVT_MASKED; 419a68c439bSRobert Richter do { 420a68c439bSRobert Richter if (rsvd && 421a68c439bSRobert Richter !eilvt_entry_is_changeable(rsvd, new)) 422a68c439bSRobert Richter /* may not change if vectors are different */ 423a68c439bSRobert Richter return rsvd; 424a68c439bSRobert Richter rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 425a68c439bSRobert Richter } while (rsvd != new); 426a68c439bSRobert Richter 427a68c439bSRobert Richter return new; 428a68c439bSRobert Richter } 429a68c439bSRobert Richter 430a68c439bSRobert Richter /* 431a68c439bSRobert Richter * If mask=1, the LVT entry does not generate interrupts while mask=0 432a68c439bSRobert Richter * enables the vector. See also the BKDGs. 433a68c439bSRobert Richter */ 434a68c439bSRobert Richter 43527afdf20SRobert Richter int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 436a68c439bSRobert Richter { 437a68c439bSRobert Richter unsigned long reg = APIC_EILVTn(offset); 438a68c439bSRobert Richter unsigned int new, old, reserved; 439a68c439bSRobert Richter 440a68c439bSRobert Richter new = (mask << 16) | (msg_type << 8) | vector; 441a68c439bSRobert Richter old = apic_read(reg); 442a68c439bSRobert Richter reserved = reserve_eilvt_offset(offset, new); 443a68c439bSRobert Richter 444a68c439bSRobert Richter if (reserved != new) { 445eb48c9cbSRobert Richter pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 446eb48c9cbSRobert Richter "vector 0x%x, but the register is already in use for " 447eb48c9cbSRobert Richter "vector 0x%x on another cpu\n", 448eb48c9cbSRobert Richter smp_processor_id(), reg, offset, new, reserved); 449a68c439bSRobert Richter return -EINVAL; 450a68c439bSRobert Richter } 451a68c439bSRobert Richter 452a68c439bSRobert Richter if (!eilvt_entry_is_changeable(old, new)) { 453eb48c9cbSRobert Richter pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 454eb48c9cbSRobert Richter "vector 0x%x, but the register is already in use for " 455eb48c9cbSRobert Richter "vector 0x%x on this cpu\n", 456eb48c9cbSRobert Richter smp_processor_id(), reg, offset, new, old); 457a68c439bSRobert Richter return -EBUSY; 458a68c439bSRobert Richter } 459a68c439bSRobert Richter 460a68c439bSRobert Richter apic_write(reg, new); 461a68c439bSRobert Richter 462a68c439bSRobert Richter return 0; 463f62bae50SIngo Molnar } 46427afdf20SRobert Richter EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 465f62bae50SIngo Molnar 466f62bae50SIngo Molnar /* 467f62bae50SIngo Molnar * Program the next event, relative to now 468f62bae50SIngo Molnar */ 469f62bae50SIngo Molnar static int lapic_next_event(unsigned long delta, 470f62bae50SIngo Molnar struct clock_event_device *evt) 471f62bae50SIngo Molnar { 472f62bae50SIngo Molnar apic_write(APIC_TMICT, delta); 473f62bae50SIngo Molnar return 0; 474f62bae50SIngo Molnar } 475f62bae50SIngo Molnar 476f62bae50SIngo Molnar /* 477f62bae50SIngo Molnar * Setup the lapic timer in periodic or oneshot mode 478f62bae50SIngo Molnar */ 479f62bae50SIngo Molnar static void lapic_timer_setup(enum clock_event_mode mode, 480f62bae50SIngo Molnar struct clock_event_device *evt) 481f62bae50SIngo Molnar { 482f62bae50SIngo Molnar unsigned long flags; 483f62bae50SIngo Molnar unsigned int v; 484f62bae50SIngo Molnar 485f62bae50SIngo Molnar /* Lapic used as dummy for broadcast ? */ 486f62bae50SIngo Molnar if (evt->features & CLOCK_EVT_FEAT_DUMMY) 487f62bae50SIngo Molnar return; 488f62bae50SIngo Molnar 489f62bae50SIngo Molnar local_irq_save(flags); 490f62bae50SIngo Molnar 491f62bae50SIngo Molnar switch (mode) { 492f62bae50SIngo Molnar case CLOCK_EVT_MODE_PERIODIC: 493f62bae50SIngo Molnar case CLOCK_EVT_MODE_ONESHOT: 494f62bae50SIngo Molnar __setup_APIC_LVTT(calibration_result, 495f62bae50SIngo Molnar mode != CLOCK_EVT_MODE_PERIODIC, 1); 496f62bae50SIngo Molnar break; 497f62bae50SIngo Molnar case CLOCK_EVT_MODE_UNUSED: 498f62bae50SIngo Molnar case CLOCK_EVT_MODE_SHUTDOWN: 499f62bae50SIngo Molnar v = apic_read(APIC_LVTT); 500f62bae50SIngo Molnar v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 501f62bae50SIngo Molnar apic_write(APIC_LVTT, v); 5026f9b4100SAndreas Herrmann apic_write(APIC_TMICT, 0); 503f62bae50SIngo Molnar break; 504f62bae50SIngo Molnar case CLOCK_EVT_MODE_RESUME: 505f62bae50SIngo Molnar /* Nothing to do here */ 506f62bae50SIngo Molnar break; 507f62bae50SIngo Molnar } 508f62bae50SIngo Molnar 509f62bae50SIngo Molnar local_irq_restore(flags); 510f62bae50SIngo Molnar } 511f62bae50SIngo Molnar 512f62bae50SIngo Molnar /* 513f62bae50SIngo Molnar * Local APIC timer broadcast function 514f62bae50SIngo Molnar */ 515f62bae50SIngo Molnar static void lapic_timer_broadcast(const struct cpumask *mask) 516f62bae50SIngo Molnar { 517f62bae50SIngo Molnar #ifdef CONFIG_SMP 518f62bae50SIngo Molnar apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 519f62bae50SIngo Molnar #endif 520f62bae50SIngo Molnar } 521f62bae50SIngo Molnar 522f62bae50SIngo Molnar /* 523421f91d2SUwe Kleine-König * Setup the local APIC timer for this CPU. Copy the initialized values 524f62bae50SIngo Molnar * of the boot CPU and register the clock event in the framework. 525f62bae50SIngo Molnar */ 526f62bae50SIngo Molnar static void __cpuinit setup_APIC_timer(void) 527f62bae50SIngo Molnar { 528f62bae50SIngo Molnar struct clock_event_device *levt = &__get_cpu_var(lapic_events); 529f62bae50SIngo Molnar 5307b543a53STejun Heo if (cpu_has(__this_cpu_ptr(&cpu_info), X86_FEATURE_ARAT)) { 531db954b58SVenkatesh Pallipadi lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 532db954b58SVenkatesh Pallipadi /* Make LAPIC timer preferrable over percpu HPET */ 533db954b58SVenkatesh Pallipadi lapic_clockevent.rating = 150; 534db954b58SVenkatesh Pallipadi } 535db954b58SVenkatesh Pallipadi 536f62bae50SIngo Molnar memcpy(levt, &lapic_clockevent, sizeof(*levt)); 537f62bae50SIngo Molnar levt->cpumask = cpumask_of(smp_processor_id()); 538f62bae50SIngo Molnar 539f62bae50SIngo Molnar clockevents_register_device(levt); 540f62bae50SIngo Molnar } 541f62bae50SIngo Molnar 542f62bae50SIngo Molnar /* 543f62bae50SIngo Molnar * In this functions we calibrate APIC bus clocks to the external timer. 544f62bae50SIngo Molnar * 545f62bae50SIngo Molnar * We want to do the calibration only once since we want to have local timer 546f62bae50SIngo Molnar * irqs syncron. CPUs connected by the same APIC bus have the very same bus 547f62bae50SIngo Molnar * frequency. 548f62bae50SIngo Molnar * 549f62bae50SIngo Molnar * This was previously done by reading the PIT/HPET and waiting for a wrap 550f62bae50SIngo Molnar * around to find out, that a tick has elapsed. I have a box, where the PIT 551f62bae50SIngo Molnar * readout is broken, so it never gets out of the wait loop again. This was 552f62bae50SIngo Molnar * also reported by others. 553f62bae50SIngo Molnar * 554f62bae50SIngo Molnar * Monitoring the jiffies value is inaccurate and the clockevents 555f62bae50SIngo Molnar * infrastructure allows us to do a simple substitution of the interrupt 556f62bae50SIngo Molnar * handler. 557f62bae50SIngo Molnar * 558f62bae50SIngo Molnar * The calibration routine also uses the pm_timer when possible, as the PIT 559f62bae50SIngo Molnar * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 560f62bae50SIngo Molnar * back to normal later in the boot process). 561f62bae50SIngo Molnar */ 562f62bae50SIngo Molnar 563f62bae50SIngo Molnar #define LAPIC_CAL_LOOPS (HZ/10) 564f62bae50SIngo Molnar 565f62bae50SIngo Molnar static __initdata int lapic_cal_loops = -1; 566f62bae50SIngo Molnar static __initdata long lapic_cal_t1, lapic_cal_t2; 567f62bae50SIngo Molnar static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 568f62bae50SIngo Molnar static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 569f62bae50SIngo Molnar static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 570f62bae50SIngo Molnar 571f62bae50SIngo Molnar /* 572f62bae50SIngo Molnar * Temporary interrupt handler. 573f62bae50SIngo Molnar */ 574f62bae50SIngo Molnar static void __init lapic_cal_handler(struct clock_event_device *dev) 575f62bae50SIngo Molnar { 576f62bae50SIngo Molnar unsigned long long tsc = 0; 577f62bae50SIngo Molnar long tapic = apic_read(APIC_TMCCT); 578f62bae50SIngo Molnar unsigned long pm = acpi_pm_read_early(); 579f62bae50SIngo Molnar 580f62bae50SIngo Molnar if (cpu_has_tsc) 581f62bae50SIngo Molnar rdtscll(tsc); 582f62bae50SIngo Molnar 583f62bae50SIngo Molnar switch (lapic_cal_loops++) { 584f62bae50SIngo Molnar case 0: 585f62bae50SIngo Molnar lapic_cal_t1 = tapic; 586f62bae50SIngo Molnar lapic_cal_tsc1 = tsc; 587f62bae50SIngo Molnar lapic_cal_pm1 = pm; 588f62bae50SIngo Molnar lapic_cal_j1 = jiffies; 589f62bae50SIngo Molnar break; 590f62bae50SIngo Molnar 591f62bae50SIngo Molnar case LAPIC_CAL_LOOPS: 592f62bae50SIngo Molnar lapic_cal_t2 = tapic; 593f62bae50SIngo Molnar lapic_cal_tsc2 = tsc; 594f62bae50SIngo Molnar if (pm < lapic_cal_pm1) 595f62bae50SIngo Molnar pm += ACPI_PM_OVRRUN; 596f62bae50SIngo Molnar lapic_cal_pm2 = pm; 597f62bae50SIngo Molnar lapic_cal_j2 = jiffies; 598f62bae50SIngo Molnar break; 599f62bae50SIngo Molnar } 600f62bae50SIngo Molnar } 601f62bae50SIngo Molnar 602f62bae50SIngo Molnar static int __init 603f62bae50SIngo Molnar calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 604f62bae50SIngo Molnar { 605f62bae50SIngo Molnar const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 606f62bae50SIngo Molnar const long pm_thresh = pm_100ms / 100; 607f62bae50SIngo Molnar unsigned long mult; 608f62bae50SIngo Molnar u64 res; 609f62bae50SIngo Molnar 610f62bae50SIngo Molnar #ifndef CONFIG_X86_PM_TIMER 611f62bae50SIngo Molnar return -1; 612f62bae50SIngo Molnar #endif 613f62bae50SIngo Molnar 614f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 615f62bae50SIngo Molnar 616f62bae50SIngo Molnar /* Check, if the PM timer is available */ 617f62bae50SIngo Molnar if (!deltapm) 618f62bae50SIngo Molnar return -1; 619f62bae50SIngo Molnar 620f62bae50SIngo Molnar mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 621f62bae50SIngo Molnar 622f62bae50SIngo Molnar if (deltapm > (pm_100ms - pm_thresh) && 623f62bae50SIngo Molnar deltapm < (pm_100ms + pm_thresh)) { 624f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 625f62bae50SIngo Molnar return 0; 626f62bae50SIngo Molnar } 627f62bae50SIngo Molnar 628f62bae50SIngo Molnar res = (((u64)deltapm) * mult) >> 22; 629f62bae50SIngo Molnar do_div(res, 1000000); 630f62bae50SIngo Molnar pr_warning("APIC calibration not consistent " 631f62bae50SIngo Molnar "with PM-Timer: %ldms instead of 100ms\n",(long)res); 632f62bae50SIngo Molnar 633f62bae50SIngo Molnar /* Correct the lapic counter value */ 634f62bae50SIngo Molnar res = (((u64)(*delta)) * pm_100ms); 635f62bae50SIngo Molnar do_div(res, deltapm); 636f62bae50SIngo Molnar pr_info("APIC delta adjusted to PM-Timer: " 637f62bae50SIngo Molnar "%lu (%ld)\n", (unsigned long)res, *delta); 638f62bae50SIngo Molnar *delta = (long)res; 639f62bae50SIngo Molnar 640f62bae50SIngo Molnar /* Correct the tsc counter value */ 641f62bae50SIngo Molnar if (cpu_has_tsc) { 642f62bae50SIngo Molnar res = (((u64)(*deltatsc)) * pm_100ms); 643f62bae50SIngo Molnar do_div(res, deltapm); 644f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 645f62bae50SIngo Molnar "PM-Timer: %lu (%ld)\n", 646f62bae50SIngo Molnar (unsigned long)res, *deltatsc); 647f62bae50SIngo Molnar *deltatsc = (long)res; 648f62bae50SIngo Molnar } 649f62bae50SIngo Molnar 650f62bae50SIngo Molnar return 0; 651f62bae50SIngo Molnar } 652f62bae50SIngo Molnar 653f62bae50SIngo Molnar static int __init calibrate_APIC_clock(void) 654f62bae50SIngo Molnar { 655f62bae50SIngo Molnar struct clock_event_device *levt = &__get_cpu_var(lapic_events); 656f62bae50SIngo Molnar void (*real_handler)(struct clock_event_device *dev); 657f62bae50SIngo Molnar unsigned long deltaj; 658f62bae50SIngo Molnar long delta, deltatsc; 659f62bae50SIngo Molnar int pm_referenced = 0; 660f62bae50SIngo Molnar 661f62bae50SIngo Molnar local_irq_disable(); 662f62bae50SIngo Molnar 663f62bae50SIngo Molnar /* Replace the global interrupt handler */ 664f62bae50SIngo Molnar real_handler = global_clock_event->event_handler; 665f62bae50SIngo Molnar global_clock_event->event_handler = lapic_cal_handler; 666f62bae50SIngo Molnar 667f62bae50SIngo Molnar /* 668f62bae50SIngo Molnar * Setup the APIC counter to maximum. There is no way the lapic 669f62bae50SIngo Molnar * can underflow in the 100ms detection time frame 670f62bae50SIngo Molnar */ 671f62bae50SIngo Molnar __setup_APIC_LVTT(0xffffffff, 0, 0); 672f62bae50SIngo Molnar 673f62bae50SIngo Molnar /* Let the interrupts run */ 674f62bae50SIngo Molnar local_irq_enable(); 675f62bae50SIngo Molnar 676f62bae50SIngo Molnar while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 677f62bae50SIngo Molnar cpu_relax(); 678f62bae50SIngo Molnar 679f62bae50SIngo Molnar local_irq_disable(); 680f62bae50SIngo Molnar 681f62bae50SIngo Molnar /* Restore the real event handler */ 682f62bae50SIngo Molnar global_clock_event->event_handler = real_handler; 683f62bae50SIngo Molnar 684f62bae50SIngo Molnar /* Build delta t1-t2 as apic timer counts down */ 685f62bae50SIngo Molnar delta = lapic_cal_t1 - lapic_cal_t2; 686f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 687f62bae50SIngo Molnar 688f62bae50SIngo Molnar deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 689f62bae50SIngo Molnar 690f62bae50SIngo Molnar /* we trust the PM based calibration if possible */ 691f62bae50SIngo Molnar pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 692f62bae50SIngo Molnar &delta, &deltatsc); 693f62bae50SIngo Molnar 694f62bae50SIngo Molnar /* Calculate the scaled math multiplication factor */ 695f62bae50SIngo Molnar lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 696f62bae50SIngo Molnar lapic_clockevent.shift); 697f62bae50SIngo Molnar lapic_clockevent.max_delta_ns = 6984aed89d6SPierre Tardy clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 699f62bae50SIngo Molnar lapic_clockevent.min_delta_ns = 700f62bae50SIngo Molnar clockevent_delta2ns(0xF, &lapic_clockevent); 701f62bae50SIngo Molnar 702f62bae50SIngo Molnar calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 703f62bae50SIngo Molnar 704f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 705411462f6SThomas Gleixner apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 706f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 707f62bae50SIngo Molnar calibration_result); 708f62bae50SIngo Molnar 709f62bae50SIngo Molnar if (cpu_has_tsc) { 710f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 711f62bae50SIngo Molnar "%ld.%04ld MHz.\n", 712f62bae50SIngo Molnar (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 713f62bae50SIngo Molnar (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 714f62bae50SIngo Molnar } 715f62bae50SIngo Molnar 716f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 717f62bae50SIngo Molnar "%u.%04u MHz.\n", 718f62bae50SIngo Molnar calibration_result / (1000000 / HZ), 719f62bae50SIngo Molnar calibration_result % (1000000 / HZ)); 720f62bae50SIngo Molnar 721f62bae50SIngo Molnar /* 722f62bae50SIngo Molnar * Do a sanity check on the APIC calibration result 723f62bae50SIngo Molnar */ 724f62bae50SIngo Molnar if (calibration_result < (1000000 / HZ)) { 725f62bae50SIngo Molnar local_irq_enable(); 726f62bae50SIngo Molnar pr_warning("APIC frequency too slow, disabling apic timer\n"); 727f62bae50SIngo Molnar return -1; 728f62bae50SIngo Molnar } 729f62bae50SIngo Molnar 730f62bae50SIngo Molnar levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 731f62bae50SIngo Molnar 732f62bae50SIngo Molnar /* 733f62bae50SIngo Molnar * PM timer calibration failed or not turned on 734f62bae50SIngo Molnar * so lets try APIC timer based calibration 735f62bae50SIngo Molnar */ 736f62bae50SIngo Molnar if (!pm_referenced) { 737f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 738f62bae50SIngo Molnar 739f62bae50SIngo Molnar /* 740f62bae50SIngo Molnar * Setup the apic timer manually 741f62bae50SIngo Molnar */ 742f62bae50SIngo Molnar levt->event_handler = lapic_cal_handler; 743f62bae50SIngo Molnar lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); 744f62bae50SIngo Molnar lapic_cal_loops = -1; 745f62bae50SIngo Molnar 746f62bae50SIngo Molnar /* Let the interrupts run */ 747f62bae50SIngo Molnar local_irq_enable(); 748f62bae50SIngo Molnar 749f62bae50SIngo Molnar while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 750f62bae50SIngo Molnar cpu_relax(); 751f62bae50SIngo Molnar 752f62bae50SIngo Molnar /* Stop the lapic timer */ 753f62bae50SIngo Molnar lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); 754f62bae50SIngo Molnar 755f62bae50SIngo Molnar /* Jiffies delta */ 756f62bae50SIngo Molnar deltaj = lapic_cal_j2 - lapic_cal_j1; 757f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 758f62bae50SIngo Molnar 759f62bae50SIngo Molnar /* Check, if the jiffies result is consistent */ 760f62bae50SIngo Molnar if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 761f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 762f62bae50SIngo Molnar else 763f62bae50SIngo Molnar levt->features |= CLOCK_EVT_FEAT_DUMMY; 764f62bae50SIngo Molnar } else 765f62bae50SIngo Molnar local_irq_enable(); 766f62bae50SIngo Molnar 767f62bae50SIngo Molnar if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 768f62bae50SIngo Molnar pr_warning("APIC timer disabled due to verification failure\n"); 769f62bae50SIngo Molnar return -1; 770f62bae50SIngo Molnar } 771f62bae50SIngo Molnar 772f62bae50SIngo Molnar return 0; 773f62bae50SIngo Molnar } 774f62bae50SIngo Molnar 775f62bae50SIngo Molnar /* 776f62bae50SIngo Molnar * Setup the boot APIC 777f62bae50SIngo Molnar * 778f62bae50SIngo Molnar * Calibrate and verify the result. 779f62bae50SIngo Molnar */ 780f62bae50SIngo Molnar void __init setup_boot_APIC_clock(void) 781f62bae50SIngo Molnar { 782f62bae50SIngo Molnar /* 783f62bae50SIngo Molnar * The local apic timer can be disabled via the kernel 784f62bae50SIngo Molnar * commandline or from the CPU detection code. Register the lapic 785f62bae50SIngo Molnar * timer as a dummy clock event source on SMP systems, so the 786f62bae50SIngo Molnar * broadcast mechanism is used. On UP systems simply ignore it. 787f62bae50SIngo Molnar */ 788f62bae50SIngo Molnar if (disable_apic_timer) { 789f62bae50SIngo Molnar pr_info("Disabling APIC timer\n"); 790f62bae50SIngo Molnar /* No broadcast on UP ! */ 791f62bae50SIngo Molnar if (num_possible_cpus() > 1) { 792f62bae50SIngo Molnar lapic_clockevent.mult = 1; 793f62bae50SIngo Molnar setup_APIC_timer(); 794f62bae50SIngo Molnar } 795f62bae50SIngo Molnar return; 796f62bae50SIngo Molnar } 797f62bae50SIngo Molnar 798f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 799f62bae50SIngo Molnar "calibrating APIC timer ...\n"); 800f62bae50SIngo Molnar 801f62bae50SIngo Molnar if (calibrate_APIC_clock()) { 802f62bae50SIngo Molnar /* No broadcast on UP ! */ 803f62bae50SIngo Molnar if (num_possible_cpus() > 1) 804f62bae50SIngo Molnar setup_APIC_timer(); 805f62bae50SIngo Molnar return; 806f62bae50SIngo Molnar } 807f62bae50SIngo Molnar 808f62bae50SIngo Molnar /* 809f62bae50SIngo Molnar * If nmi_watchdog is set to IO_APIC, we need the 810f62bae50SIngo Molnar * PIT/HPET going. Otherwise register lapic as a dummy 811f62bae50SIngo Molnar * device. 812f62bae50SIngo Molnar */ 813f62bae50SIngo Molnar lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 814f62bae50SIngo Molnar 815f62bae50SIngo Molnar /* Setup the lapic or request the broadcast */ 816f62bae50SIngo Molnar setup_APIC_timer(); 817f62bae50SIngo Molnar } 818f62bae50SIngo Molnar 819f62bae50SIngo Molnar void __cpuinit setup_secondary_APIC_clock(void) 820f62bae50SIngo Molnar { 821f62bae50SIngo Molnar setup_APIC_timer(); 822f62bae50SIngo Molnar } 823f62bae50SIngo Molnar 824f62bae50SIngo Molnar /* 825f62bae50SIngo Molnar * The guts of the apic timer interrupt 826f62bae50SIngo Molnar */ 827f62bae50SIngo Molnar static void local_apic_timer_interrupt(void) 828f62bae50SIngo Molnar { 829f62bae50SIngo Molnar int cpu = smp_processor_id(); 830f62bae50SIngo Molnar struct clock_event_device *evt = &per_cpu(lapic_events, cpu); 831f62bae50SIngo Molnar 832f62bae50SIngo Molnar /* 833f62bae50SIngo Molnar * Normally we should not be here till LAPIC has been initialized but 834f62bae50SIngo Molnar * in some cases like kdump, its possible that there is a pending LAPIC 835f62bae50SIngo Molnar * timer interrupt from previous kernel's context and is delivered in 836f62bae50SIngo Molnar * new kernel the moment interrupts are enabled. 837f62bae50SIngo Molnar * 838f62bae50SIngo Molnar * Interrupts are enabled early and LAPIC is setup much later, hence 839f62bae50SIngo Molnar * its possible that when we get here evt->event_handler is NULL. 840f62bae50SIngo Molnar * Check for event_handler being NULL and discard the interrupt as 841f62bae50SIngo Molnar * spurious. 842f62bae50SIngo Molnar */ 843f62bae50SIngo Molnar if (!evt->event_handler) { 844f62bae50SIngo Molnar pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); 845f62bae50SIngo Molnar /* Switch it off */ 846f62bae50SIngo Molnar lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); 847f62bae50SIngo Molnar return; 848f62bae50SIngo Molnar } 849f62bae50SIngo Molnar 850f62bae50SIngo Molnar /* 851f62bae50SIngo Molnar * the NMI deadlock-detector uses this. 852f62bae50SIngo Molnar */ 853f62bae50SIngo Molnar inc_irq_stat(apic_timer_irqs); 854f62bae50SIngo Molnar 855f62bae50SIngo Molnar evt->event_handler(evt); 856f62bae50SIngo Molnar } 857f62bae50SIngo Molnar 858f62bae50SIngo Molnar /* 859f62bae50SIngo Molnar * Local APIC timer interrupt. This is the most natural way for doing 860f62bae50SIngo Molnar * local interrupts, but local timer interrupts can be emulated by 861f62bae50SIngo Molnar * broadcast interrupts too. [in case the hw doesn't support APIC timers] 862f62bae50SIngo Molnar * 863f62bae50SIngo Molnar * [ if a single-CPU system runs an SMP kernel then we call the local 864f62bae50SIngo Molnar * interrupt as well. Thus we cannot inline the local irq ... ] 865f62bae50SIngo Molnar */ 866f62bae50SIngo Molnar void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 867f62bae50SIngo Molnar { 868f62bae50SIngo Molnar struct pt_regs *old_regs = set_irq_regs(regs); 869f62bae50SIngo Molnar 870f62bae50SIngo Molnar /* 871f62bae50SIngo Molnar * NOTE! We'd better ACK the irq immediately, 872f62bae50SIngo Molnar * because timer handling can be slow. 873f62bae50SIngo Molnar */ 874f62bae50SIngo Molnar ack_APIC_irq(); 875f62bae50SIngo Molnar /* 876f62bae50SIngo Molnar * update_process_times() expects us to have done irq_enter(). 877f62bae50SIngo Molnar * Besides, if we don't timer interrupts ignore the global 878f62bae50SIngo Molnar * interrupt lock, which is the WrongThing (tm) to do. 879f62bae50SIngo Molnar */ 880f62bae50SIngo Molnar exit_idle(); 881f62bae50SIngo Molnar irq_enter(); 882f62bae50SIngo Molnar local_apic_timer_interrupt(); 883f62bae50SIngo Molnar irq_exit(); 884f62bae50SIngo Molnar 885f62bae50SIngo Molnar set_irq_regs(old_regs); 886f62bae50SIngo Molnar } 887f62bae50SIngo Molnar 888f62bae50SIngo Molnar int setup_profiling_timer(unsigned int multiplier) 889f62bae50SIngo Molnar { 890f62bae50SIngo Molnar return -EINVAL; 891f62bae50SIngo Molnar } 892f62bae50SIngo Molnar 893f62bae50SIngo Molnar /* 894f62bae50SIngo Molnar * Local APIC start and shutdown 895f62bae50SIngo Molnar */ 896f62bae50SIngo Molnar 897f62bae50SIngo Molnar /** 898f62bae50SIngo Molnar * clear_local_APIC - shutdown the local APIC 899f62bae50SIngo Molnar * 900f62bae50SIngo Molnar * This is called, when a CPU is disabled and before rebooting, so the state of 901f62bae50SIngo Molnar * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 902f62bae50SIngo Molnar * leftovers during boot. 903f62bae50SIngo Molnar */ 904f62bae50SIngo Molnar void clear_local_APIC(void) 905f62bae50SIngo Molnar { 906f62bae50SIngo Molnar int maxlvt; 907f62bae50SIngo Molnar u32 v; 908f62bae50SIngo Molnar 909f62bae50SIngo Molnar /* APIC hasn't been mapped yet */ 910fc1edaf9SSuresh Siddha if (!x2apic_mode && !apic_phys) 911f62bae50SIngo Molnar return; 912f62bae50SIngo Molnar 913f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 914f62bae50SIngo Molnar /* 915f62bae50SIngo Molnar * Masking an LVT entry can trigger a local APIC error 916f62bae50SIngo Molnar * if the vector is zero. Mask LVTERR first to prevent this. 917f62bae50SIngo Molnar */ 918f62bae50SIngo Molnar if (maxlvt >= 3) { 919f62bae50SIngo Molnar v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 920f62bae50SIngo Molnar apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 921f62bae50SIngo Molnar } 922f62bae50SIngo Molnar /* 923f62bae50SIngo Molnar * Careful: we have to set masks only first to deassert 924f62bae50SIngo Molnar * any level-triggered sources. 925f62bae50SIngo Molnar */ 926f62bae50SIngo Molnar v = apic_read(APIC_LVTT); 927f62bae50SIngo Molnar apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 928f62bae50SIngo Molnar v = apic_read(APIC_LVT0); 929f62bae50SIngo Molnar apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 930f62bae50SIngo Molnar v = apic_read(APIC_LVT1); 931f62bae50SIngo Molnar apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 932f62bae50SIngo Molnar if (maxlvt >= 4) { 933f62bae50SIngo Molnar v = apic_read(APIC_LVTPC); 934f62bae50SIngo Molnar apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 935f62bae50SIngo Molnar } 936f62bae50SIngo Molnar 937f62bae50SIngo Molnar /* lets not touch this if we didn't frob it */ 9384efc0670SAndi Kleen #ifdef CONFIG_X86_THERMAL_VECTOR 939f62bae50SIngo Molnar if (maxlvt >= 5) { 940f62bae50SIngo Molnar v = apic_read(APIC_LVTTHMR); 941f62bae50SIngo Molnar apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 942f62bae50SIngo Molnar } 943f62bae50SIngo Molnar #endif 944638bee71SH. Peter Anvin #ifdef CONFIG_X86_MCE_INTEL 945638bee71SH. Peter Anvin if (maxlvt >= 6) { 946638bee71SH. Peter Anvin v = apic_read(APIC_LVTCMCI); 947638bee71SH. Peter Anvin if (!(v & APIC_LVT_MASKED)) 948638bee71SH. Peter Anvin apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 949638bee71SH. Peter Anvin } 950638bee71SH. Peter Anvin #endif 951638bee71SH. Peter Anvin 952f62bae50SIngo Molnar /* 953f62bae50SIngo Molnar * Clean APIC state for other OSs: 954f62bae50SIngo Molnar */ 955f62bae50SIngo Molnar apic_write(APIC_LVTT, APIC_LVT_MASKED); 956f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_LVT_MASKED); 957f62bae50SIngo Molnar apic_write(APIC_LVT1, APIC_LVT_MASKED); 958f62bae50SIngo Molnar if (maxlvt >= 3) 959f62bae50SIngo Molnar apic_write(APIC_LVTERR, APIC_LVT_MASKED); 960f62bae50SIngo Molnar if (maxlvt >= 4) 961f62bae50SIngo Molnar apic_write(APIC_LVTPC, APIC_LVT_MASKED); 962f62bae50SIngo Molnar 963f62bae50SIngo Molnar /* Integrated APIC (!82489DX) ? */ 964f62bae50SIngo Molnar if (lapic_is_integrated()) { 965f62bae50SIngo Molnar if (maxlvt > 3) 966f62bae50SIngo Molnar /* Clear ESR due to Pentium errata 3AP and 11AP */ 967f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 968f62bae50SIngo Molnar apic_read(APIC_ESR); 969f62bae50SIngo Molnar } 970f62bae50SIngo Molnar } 971f62bae50SIngo Molnar 972f62bae50SIngo Molnar /** 973f62bae50SIngo Molnar * disable_local_APIC - clear and disable the local APIC 974f62bae50SIngo Molnar */ 975f62bae50SIngo Molnar void disable_local_APIC(void) 976f62bae50SIngo Molnar { 977f62bae50SIngo Molnar unsigned int value; 978f62bae50SIngo Molnar 979f62bae50SIngo Molnar /* APIC hasn't been mapped yet */ 980fd19dce7SYinghai Lu if (!x2apic_mode && !apic_phys) 981f62bae50SIngo Molnar return; 982f62bae50SIngo Molnar 983f62bae50SIngo Molnar clear_local_APIC(); 984f62bae50SIngo Molnar 985f62bae50SIngo Molnar /* 986f62bae50SIngo Molnar * Disable APIC (implies clearing of registers 987f62bae50SIngo Molnar * for 82489DX!). 988f62bae50SIngo Molnar */ 989f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 990f62bae50SIngo Molnar value &= ~APIC_SPIV_APIC_ENABLED; 991f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 992f62bae50SIngo Molnar 993f62bae50SIngo Molnar #ifdef CONFIG_X86_32 994f62bae50SIngo Molnar /* 995f62bae50SIngo Molnar * When LAPIC was disabled by the BIOS and enabled by the kernel, 996f62bae50SIngo Molnar * restore the disabled state. 997f62bae50SIngo Molnar */ 998f62bae50SIngo Molnar if (enabled_via_apicbase) { 999f62bae50SIngo Molnar unsigned int l, h; 1000f62bae50SIngo Molnar 1001f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, l, h); 1002f62bae50SIngo Molnar l &= ~MSR_IA32_APICBASE_ENABLE; 1003f62bae50SIngo Molnar wrmsr(MSR_IA32_APICBASE, l, h); 1004f62bae50SIngo Molnar } 1005f62bae50SIngo Molnar #endif 1006f62bae50SIngo Molnar } 1007f62bae50SIngo Molnar 1008f62bae50SIngo Molnar /* 1009f62bae50SIngo Molnar * If Linux enabled the LAPIC against the BIOS default disable it down before 1010f62bae50SIngo Molnar * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 1011f62bae50SIngo Molnar * not power-off. Additionally clear all LVT entries before disable_local_APIC 1012f62bae50SIngo Molnar * for the case where Linux didn't enable the LAPIC. 1013f62bae50SIngo Molnar */ 1014f62bae50SIngo Molnar void lapic_shutdown(void) 1015f62bae50SIngo Molnar { 1016f62bae50SIngo Molnar unsigned long flags; 1017f62bae50SIngo Molnar 10188312136fSCyrill Gorcunov if (!cpu_has_apic && !apic_from_smp_config()) 1019f62bae50SIngo Molnar return; 1020f62bae50SIngo Molnar 1021f62bae50SIngo Molnar local_irq_save(flags); 1022f62bae50SIngo Molnar 1023f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1024f62bae50SIngo Molnar if (!enabled_via_apicbase) 1025f62bae50SIngo Molnar clear_local_APIC(); 1026f62bae50SIngo Molnar else 1027f62bae50SIngo Molnar #endif 1028f62bae50SIngo Molnar disable_local_APIC(); 1029f62bae50SIngo Molnar 1030f62bae50SIngo Molnar 1031f62bae50SIngo Molnar local_irq_restore(flags); 1032f62bae50SIngo Molnar } 1033f62bae50SIngo Molnar 1034f62bae50SIngo Molnar /* 1035f62bae50SIngo Molnar * This is to verify that we're looking at a real local APIC. 1036f62bae50SIngo Molnar * Check these against your board if the CPUs aren't getting 1037f62bae50SIngo Molnar * started for no apparent reason. 1038f62bae50SIngo Molnar */ 1039f62bae50SIngo Molnar int __init verify_local_APIC(void) 1040f62bae50SIngo Molnar { 1041f62bae50SIngo Molnar unsigned int reg0, reg1; 1042f62bae50SIngo Molnar 1043f62bae50SIngo Molnar /* 1044f62bae50SIngo Molnar * The version register is read-only in a real APIC. 1045f62bae50SIngo Molnar */ 1046f62bae50SIngo Molnar reg0 = apic_read(APIC_LVR); 1047f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); 1048f62bae50SIngo Molnar apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); 1049f62bae50SIngo Molnar reg1 = apic_read(APIC_LVR); 1050f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); 1051f62bae50SIngo Molnar 1052f62bae50SIngo Molnar /* 1053f62bae50SIngo Molnar * The two version reads above should print the same 1054f62bae50SIngo Molnar * numbers. If the second one is different, then we 1055f62bae50SIngo Molnar * poke at a non-APIC. 1056f62bae50SIngo Molnar */ 1057f62bae50SIngo Molnar if (reg1 != reg0) 1058f62bae50SIngo Molnar return 0; 1059f62bae50SIngo Molnar 1060f62bae50SIngo Molnar /* 1061f62bae50SIngo Molnar * Check if the version looks reasonably. 1062f62bae50SIngo Molnar */ 1063f62bae50SIngo Molnar reg1 = GET_APIC_VERSION(reg0); 1064f62bae50SIngo Molnar if (reg1 == 0x00 || reg1 == 0xff) 1065f62bae50SIngo Molnar return 0; 1066f62bae50SIngo Molnar reg1 = lapic_get_maxlvt(); 1067f62bae50SIngo Molnar if (reg1 < 0x02 || reg1 == 0xff) 1068f62bae50SIngo Molnar return 0; 1069f62bae50SIngo Molnar 1070f62bae50SIngo Molnar /* 1071f62bae50SIngo Molnar * The ID register is read/write in a real APIC. 1072f62bae50SIngo Molnar */ 1073f62bae50SIngo Molnar reg0 = apic_read(APIC_ID); 1074f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); 1075f62bae50SIngo Molnar apic_write(APIC_ID, reg0 ^ apic->apic_id_mask); 1076f62bae50SIngo Molnar reg1 = apic_read(APIC_ID); 1077f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); 1078f62bae50SIngo Molnar apic_write(APIC_ID, reg0); 1079f62bae50SIngo Molnar if (reg1 != (reg0 ^ apic->apic_id_mask)) 1080f62bae50SIngo Molnar return 0; 1081f62bae50SIngo Molnar 1082f62bae50SIngo Molnar /* 1083f62bae50SIngo Molnar * The next two are just to see if we have sane values. 1084f62bae50SIngo Molnar * They're only really relevant if we're in Virtual Wire 1085f62bae50SIngo Molnar * compatibility mode, but most boxes are anymore. 1086f62bae50SIngo Molnar */ 1087f62bae50SIngo Molnar reg0 = apic_read(APIC_LVT0); 1088f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); 1089f62bae50SIngo Molnar reg1 = apic_read(APIC_LVT1); 1090f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); 1091f62bae50SIngo Molnar 1092f62bae50SIngo Molnar return 1; 1093f62bae50SIngo Molnar } 1094f62bae50SIngo Molnar 1095f62bae50SIngo Molnar /** 1096f62bae50SIngo Molnar * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1097f62bae50SIngo Molnar */ 1098f62bae50SIngo Molnar void __init sync_Arb_IDs(void) 1099f62bae50SIngo Molnar { 1100f62bae50SIngo Molnar /* 1101f62bae50SIngo Molnar * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1102f62bae50SIngo Molnar * needed on AMD. 1103f62bae50SIngo Molnar */ 1104f62bae50SIngo Molnar if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1105f62bae50SIngo Molnar return; 1106f62bae50SIngo Molnar 1107f62bae50SIngo Molnar /* 1108f62bae50SIngo Molnar * Wait for idle. 1109f62bae50SIngo Molnar */ 1110f62bae50SIngo Molnar apic_wait_icr_idle(); 1111f62bae50SIngo Molnar 1112f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1113f62bae50SIngo Molnar apic_write(APIC_ICR, APIC_DEST_ALLINC | 1114f62bae50SIngo Molnar APIC_INT_LEVELTRIG | APIC_DM_INIT); 1115f62bae50SIngo Molnar } 1116f62bae50SIngo Molnar 1117f62bae50SIngo Molnar /* 1118f62bae50SIngo Molnar * An initial setup of the virtual wire mode. 1119f62bae50SIngo Molnar */ 1120f62bae50SIngo Molnar void __init init_bsp_APIC(void) 1121f62bae50SIngo Molnar { 1122f62bae50SIngo Molnar unsigned int value; 1123f62bae50SIngo Molnar 1124f62bae50SIngo Molnar /* 1125f62bae50SIngo Molnar * Don't do the setup now if we have a SMP BIOS as the 1126f62bae50SIngo Molnar * through-I/O-APIC virtual wire mode might be active. 1127f62bae50SIngo Molnar */ 1128f62bae50SIngo Molnar if (smp_found_config || !cpu_has_apic) 1129f62bae50SIngo Molnar return; 1130f62bae50SIngo Molnar 1131f62bae50SIngo Molnar /* 1132f62bae50SIngo Molnar * Do not trust the local APIC being empty at bootup. 1133f62bae50SIngo Molnar */ 1134f62bae50SIngo Molnar clear_local_APIC(); 1135f62bae50SIngo Molnar 1136f62bae50SIngo Molnar /* 1137f62bae50SIngo Molnar * Enable APIC. 1138f62bae50SIngo Molnar */ 1139f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 1140f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 1141f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 1142f62bae50SIngo Molnar 1143f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1144f62bae50SIngo Molnar /* This bit is reserved on P4/Xeon and should be cleared */ 1145f62bae50SIngo Molnar if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1146f62bae50SIngo Molnar (boot_cpu_data.x86 == 15)) 1147f62bae50SIngo Molnar value &= ~APIC_SPIV_FOCUS_DISABLED; 1148f62bae50SIngo Molnar else 1149f62bae50SIngo Molnar #endif 1150f62bae50SIngo Molnar value |= APIC_SPIV_FOCUS_DISABLED; 1151f62bae50SIngo Molnar value |= SPURIOUS_APIC_VECTOR; 1152f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 1153f62bae50SIngo Molnar 1154f62bae50SIngo Molnar /* 1155f62bae50SIngo Molnar * Set up the virtual wire mode. 1156f62bae50SIngo Molnar */ 1157f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_DM_EXTINT); 1158f62bae50SIngo Molnar value = APIC_DM_NMI; 1159f62bae50SIngo Molnar if (!lapic_is_integrated()) /* 82489DX */ 1160f62bae50SIngo Molnar value |= APIC_LVT_LEVEL_TRIGGER; 1161f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 1162f62bae50SIngo Molnar } 1163f62bae50SIngo Molnar 1164f62bae50SIngo Molnar static void __cpuinit lapic_setup_esr(void) 1165f62bae50SIngo Molnar { 1166f62bae50SIngo Molnar unsigned int oldvalue, value, maxlvt; 1167f62bae50SIngo Molnar 1168f62bae50SIngo Molnar if (!lapic_is_integrated()) { 1169f62bae50SIngo Molnar pr_info("No ESR for 82489DX.\n"); 1170f62bae50SIngo Molnar return; 1171f62bae50SIngo Molnar } 1172f62bae50SIngo Molnar 1173f62bae50SIngo Molnar if (apic->disable_esr) { 1174f62bae50SIngo Molnar /* 1175f62bae50SIngo Molnar * Something untraceable is creating bad interrupts on 1176f62bae50SIngo Molnar * secondary quads ... for the moment, just leave the 1177f62bae50SIngo Molnar * ESR disabled - we can't do anything useful with the 1178f62bae50SIngo Molnar * errors anyway - mbligh 1179f62bae50SIngo Molnar */ 1180f62bae50SIngo Molnar pr_info("Leaving ESR disabled.\n"); 1181f62bae50SIngo Molnar return; 1182f62bae50SIngo Molnar } 1183f62bae50SIngo Molnar 1184f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 1185f62bae50SIngo Molnar if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1186f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1187f62bae50SIngo Molnar oldvalue = apic_read(APIC_ESR); 1188f62bae50SIngo Molnar 1189f62bae50SIngo Molnar /* enables sending errors */ 1190f62bae50SIngo Molnar value = ERROR_APIC_VECTOR; 1191f62bae50SIngo Molnar apic_write(APIC_LVTERR, value); 1192f62bae50SIngo Molnar 1193f62bae50SIngo Molnar /* 1194f62bae50SIngo Molnar * spec says clear errors after enabling vector. 1195f62bae50SIngo Molnar */ 1196f62bae50SIngo Molnar if (maxlvt > 3) 1197f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1198f62bae50SIngo Molnar value = apic_read(APIC_ESR); 1199f62bae50SIngo Molnar if (value != oldvalue) 1200f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "ESR value before enabling " 1201f62bae50SIngo Molnar "vector: 0x%08x after: 0x%08x\n", 1202f62bae50SIngo Molnar oldvalue, value); 1203f62bae50SIngo Molnar } 1204f62bae50SIngo Molnar 1205f62bae50SIngo Molnar /** 1206f62bae50SIngo Molnar * setup_local_APIC - setup the local APIC 12070aa002feSTejun Heo * 12080aa002feSTejun Heo * Used to setup local APIC while initializing BSP or bringin up APs. 12090aa002feSTejun Heo * Always called with preemption disabled. 1210f62bae50SIngo Molnar */ 1211f62bae50SIngo Molnar void __cpuinit setup_local_APIC(void) 1212f62bae50SIngo Molnar { 12130aa002feSTejun Heo int cpu = smp_processor_id(); 12148c3ba8d0SKerstin Jonsson unsigned int value, queued; 12158c3ba8d0SKerstin Jonsson int i, j, acked = 0; 12168c3ba8d0SKerstin Jonsson unsigned long long tsc = 0, ntsc; 12178c3ba8d0SKerstin Jonsson long long max_loops = cpu_khz; 12188c3ba8d0SKerstin Jonsson 12198c3ba8d0SKerstin Jonsson if (cpu_has_tsc) 12208c3ba8d0SKerstin Jonsson rdtscll(tsc); 1221f62bae50SIngo Molnar 1222f62bae50SIngo Molnar if (disable_apic) { 1223f62bae50SIngo Molnar arch_disable_smp_support(); 1224f62bae50SIngo Molnar return; 1225f62bae50SIngo Molnar } 1226f62bae50SIngo Molnar 1227f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1228f62bae50SIngo Molnar /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1229f62bae50SIngo Molnar if (lapic_is_integrated() && apic->disable_esr) { 1230f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1231f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1232f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1233f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1234f62bae50SIngo Molnar } 1235f62bae50SIngo Molnar #endif 1236cdd6c482SIngo Molnar perf_events_lapic_init(); 1237f62bae50SIngo Molnar 1238f62bae50SIngo Molnar /* 1239f62bae50SIngo Molnar * Double-check whether this APIC is really registered. 1240f62bae50SIngo Molnar * This is meaningless in clustered apic mode, so we skip it. 1241f62bae50SIngo Molnar */ 1242c2777f98SDaniel Walker BUG_ON(!apic->apic_id_registered()); 1243f62bae50SIngo Molnar 1244f62bae50SIngo Molnar /* 1245f62bae50SIngo Molnar * Intel recommends to set DFR, LDR and TPR before enabling 1246f62bae50SIngo Molnar * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1247f62bae50SIngo Molnar * document number 292116). So here it goes... 1248f62bae50SIngo Molnar */ 1249f62bae50SIngo Molnar apic->init_apic_ldr(); 1250f62bae50SIngo Molnar 12516f802c4bSTejun Heo #ifdef CONFIG_X86_32 12526f802c4bSTejun Heo /* 1253acb8bc09STejun Heo * APIC LDR is initialized. If logical_apicid mapping was 1254acb8bc09STejun Heo * initialized during get_smp_config(), make sure it matches the 1255acb8bc09STejun Heo * actual value. 12566f802c4bSTejun Heo */ 1257acb8bc09STejun Heo i = early_per_cpu(x86_cpu_to_logical_apicid, cpu); 1258acb8bc09STejun Heo WARN_ON(i != BAD_APICID && i != logical_smp_processor_id()); 1259acb8bc09STejun Heo /* always use the value from LDR */ 12606f802c4bSTejun Heo early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 12616f802c4bSTejun Heo logical_smp_processor_id(); 12626f802c4bSTejun Heo #endif 12636f802c4bSTejun Heo 1264f62bae50SIngo Molnar /* 1265f62bae50SIngo Molnar * Set Task Priority to 'accept all'. We never change this 1266f62bae50SIngo Molnar * later on. 1267f62bae50SIngo Molnar */ 1268f62bae50SIngo Molnar value = apic_read(APIC_TASKPRI); 1269f62bae50SIngo Molnar value &= ~APIC_TPRI_MASK; 1270f62bae50SIngo Molnar apic_write(APIC_TASKPRI, value); 1271f62bae50SIngo Molnar 1272f62bae50SIngo Molnar /* 1273f62bae50SIngo Molnar * After a crash, we no longer service the interrupts and a pending 1274f62bae50SIngo Molnar * interrupt from previous kernel might still have ISR bit set. 1275f62bae50SIngo Molnar * 1276f62bae50SIngo Molnar * Most probably by now CPU has serviced that pending interrupt and 1277f62bae50SIngo Molnar * it might not have done the ack_APIC_irq() because it thought, 1278f62bae50SIngo Molnar * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1279f62bae50SIngo Molnar * does not clear the ISR bit and cpu thinks it has already serivced 1280f62bae50SIngo Molnar * the interrupt. Hence a vector might get locked. It was noticed 1281f62bae50SIngo Molnar * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1282f62bae50SIngo Molnar */ 12838c3ba8d0SKerstin Jonsson do { 12848c3ba8d0SKerstin Jonsson queued = 0; 12858c3ba8d0SKerstin Jonsson for (i = APIC_ISR_NR - 1; i >= 0; i--) 12868c3ba8d0SKerstin Jonsson queued |= apic_read(APIC_IRR + i*0x10); 12878c3ba8d0SKerstin Jonsson 1288f62bae50SIngo Molnar for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1289f62bae50SIngo Molnar value = apic_read(APIC_ISR + i*0x10); 1290f62bae50SIngo Molnar for (j = 31; j >= 0; j--) { 12918c3ba8d0SKerstin Jonsson if (value & (1<<j)) { 1292f62bae50SIngo Molnar ack_APIC_irq(); 12938c3ba8d0SKerstin Jonsson acked++; 1294f62bae50SIngo Molnar } 1295f62bae50SIngo Molnar } 12968c3ba8d0SKerstin Jonsson } 12978c3ba8d0SKerstin Jonsson if (acked > 256) { 12988c3ba8d0SKerstin Jonsson printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", 12998c3ba8d0SKerstin Jonsson acked); 13008c3ba8d0SKerstin Jonsson break; 13018c3ba8d0SKerstin Jonsson } 13028c3ba8d0SKerstin Jonsson if (cpu_has_tsc) { 13038c3ba8d0SKerstin Jonsson rdtscll(ntsc); 13048c3ba8d0SKerstin Jonsson max_loops = (cpu_khz << 10) - (ntsc - tsc); 13058c3ba8d0SKerstin Jonsson } else 13068c3ba8d0SKerstin Jonsson max_loops--; 13078c3ba8d0SKerstin Jonsson } while (queued && max_loops > 0); 13088c3ba8d0SKerstin Jonsson WARN_ON(max_loops <= 0); 1309f62bae50SIngo Molnar 1310f62bae50SIngo Molnar /* 1311f62bae50SIngo Molnar * Now that we are all set up, enable the APIC 1312f62bae50SIngo Molnar */ 1313f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 1314f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 1315f62bae50SIngo Molnar /* 1316f62bae50SIngo Molnar * Enable APIC 1317f62bae50SIngo Molnar */ 1318f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 1319f62bae50SIngo Molnar 1320f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1321f62bae50SIngo Molnar /* 1322f62bae50SIngo Molnar * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1323f62bae50SIngo Molnar * certain networking cards. If high frequency interrupts are 1324f62bae50SIngo Molnar * happening on a particular IOAPIC pin, plus the IOAPIC routing 1325f62bae50SIngo Molnar * entry is masked/unmasked at a high rate as well then sooner or 1326f62bae50SIngo Molnar * later IOAPIC line gets 'stuck', no more interrupts are received 1327f62bae50SIngo Molnar * from the device. If focus CPU is disabled then the hang goes 1328f62bae50SIngo Molnar * away, oh well :-( 1329f62bae50SIngo Molnar * 1330f62bae50SIngo Molnar * [ This bug can be reproduced easily with a level-triggered 1331f62bae50SIngo Molnar * PCI Ne2000 networking cards and PII/PIII processors, dual 1332f62bae50SIngo Molnar * BX chipset. ] 1333f62bae50SIngo Molnar */ 1334f62bae50SIngo Molnar /* 1335f62bae50SIngo Molnar * Actually disabling the focus CPU check just makes the hang less 1336f62bae50SIngo Molnar * frequent as it makes the interrupt distributon model be more 1337f62bae50SIngo Molnar * like LRU than MRU (the short-term load is more even across CPUs). 1338f62bae50SIngo Molnar * See also the comment in end_level_ioapic_irq(). --macro 1339f62bae50SIngo Molnar */ 1340f62bae50SIngo Molnar 1341f62bae50SIngo Molnar /* 1342f62bae50SIngo Molnar * - enable focus processor (bit==0) 1343f62bae50SIngo Molnar * - 64bit mode always use processor focus 1344f62bae50SIngo Molnar * so no need to set it 1345f62bae50SIngo Molnar */ 1346f62bae50SIngo Molnar value &= ~APIC_SPIV_FOCUS_DISABLED; 1347f62bae50SIngo Molnar #endif 1348f62bae50SIngo Molnar 1349f62bae50SIngo Molnar /* 1350f62bae50SIngo Molnar * Set spurious IRQ vector 1351f62bae50SIngo Molnar */ 1352f62bae50SIngo Molnar value |= SPURIOUS_APIC_VECTOR; 1353f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 1354f62bae50SIngo Molnar 1355f62bae50SIngo Molnar /* 1356f62bae50SIngo Molnar * Set up LVT0, LVT1: 1357f62bae50SIngo Molnar * 1358f62bae50SIngo Molnar * set up through-local-APIC on the BP's LINT0. This is not 1359f62bae50SIngo Molnar * strictly necessary in pure symmetric-IO mode, but sometimes 1360f62bae50SIngo Molnar * we delegate interrupts to the 8259A. 1361f62bae50SIngo Molnar */ 1362f62bae50SIngo Molnar /* 1363f62bae50SIngo Molnar * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1364f62bae50SIngo Molnar */ 1365f62bae50SIngo Molnar value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 13660aa002feSTejun Heo if (!cpu && (pic_mode || !value)) { 1367f62bae50SIngo Molnar value = APIC_DM_EXTINT; 13680aa002feSTejun Heo apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1369f62bae50SIngo Molnar } else { 1370f62bae50SIngo Molnar value = APIC_DM_EXTINT | APIC_LVT_MASKED; 13710aa002feSTejun Heo apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1372f62bae50SIngo Molnar } 1373f62bae50SIngo Molnar apic_write(APIC_LVT0, value); 1374f62bae50SIngo Molnar 1375f62bae50SIngo Molnar /* 1376f62bae50SIngo Molnar * only the BP should see the LINT1 NMI signal, obviously. 1377f62bae50SIngo Molnar */ 13780aa002feSTejun Heo if (!cpu) 1379f62bae50SIngo Molnar value = APIC_DM_NMI; 1380f62bae50SIngo Molnar else 1381f62bae50SIngo Molnar value = APIC_DM_NMI | APIC_LVT_MASKED; 1382f62bae50SIngo Molnar if (!lapic_is_integrated()) /* 82489DX */ 1383f62bae50SIngo Molnar value |= APIC_LVT_LEVEL_TRIGGER; 1384f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 1385f62bae50SIngo Molnar 1386638bee71SH. Peter Anvin #ifdef CONFIG_X86_MCE_INTEL 1387638bee71SH. Peter Anvin /* Recheck CMCI information after local APIC is up on CPU #0 */ 13880aa002feSTejun Heo if (!cpu) 1389638bee71SH. Peter Anvin cmci_recheck(); 1390638bee71SH. Peter Anvin #endif 1391f62bae50SIngo Molnar } 1392f62bae50SIngo Molnar 1393f62bae50SIngo Molnar void __cpuinit end_local_APIC_setup(void) 1394f62bae50SIngo Molnar { 1395f62bae50SIngo Molnar lapic_setup_esr(); 1396f62bae50SIngo Molnar 1397f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1398f62bae50SIngo Molnar { 1399f62bae50SIngo Molnar unsigned int value; 1400f62bae50SIngo Molnar /* Disable the local apic timer */ 1401f62bae50SIngo Molnar value = apic_read(APIC_LVTT); 1402f62bae50SIngo Molnar value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1403f62bae50SIngo Molnar apic_write(APIC_LVTT, value); 1404f62bae50SIngo Molnar } 1405f62bae50SIngo Molnar #endif 1406f62bae50SIngo Molnar 1407f62bae50SIngo Molnar apic_pm_activate(); 14087f7fbf45SKenji Kaneshige 14097f7fbf45SKenji Kaneshige /* 14107f7fbf45SKenji Kaneshige * Now that local APIC setup is completed for BP, configure the fault 14117f7fbf45SKenji Kaneshige * handling for interrupt remapping. 14127f7fbf45SKenji Kaneshige */ 14137f7fbf45SKenji Kaneshige if (!smp_processor_id() && intr_remapping_enabled) 14147f7fbf45SKenji Kaneshige enable_drhd_fault_handling(); 14157f7fbf45SKenji Kaneshige 1416f62bae50SIngo Molnar } 1417f62bae50SIngo Molnar 1418f62bae50SIngo Molnar #ifdef CONFIG_X86_X2APIC 1419f62bae50SIngo Molnar void check_x2apic(void) 1420f62bae50SIngo Molnar { 1421ef1f87aaSSuresh Siddha if (x2apic_enabled()) { 1422f62bae50SIngo Molnar pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); 1423fc1edaf9SSuresh Siddha x2apic_preenabled = x2apic_mode = 1; 1424f62bae50SIngo Molnar } 1425f62bae50SIngo Molnar } 1426f62bae50SIngo Molnar 1427f62bae50SIngo Molnar void enable_x2apic(void) 1428f62bae50SIngo Molnar { 1429f62bae50SIngo Molnar int msr, msr2; 1430f62bae50SIngo Molnar 1431fc1edaf9SSuresh Siddha if (!x2apic_mode) 1432f62bae50SIngo Molnar return; 1433f62bae50SIngo Molnar 1434f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, msr, msr2); 1435f62bae50SIngo Molnar if (!(msr & X2APIC_ENABLE)) { 1436450b1e8dSMike Travis printk_once(KERN_INFO "Enabling x2apic\n"); 1437f62bae50SIngo Molnar wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); 1438f62bae50SIngo Molnar } 1439f62bae50SIngo Molnar } 144093758238SWeidong Han #endif /* CONFIG_X86_X2APIC */ 1441f62bae50SIngo Molnar 1442ce69a784SGleb Natapov int __init enable_IR(void) 1443f62bae50SIngo Molnar { 1444f62bae50SIngo Molnar #ifdef CONFIG_INTR_REMAP 144593758238SWeidong Han if (!intr_remapping_supported()) { 144693758238SWeidong Han pr_debug("intr-remapping not supported\n"); 1447ce69a784SGleb Natapov return 0; 144893758238SWeidong Han } 144993758238SWeidong Han 145093758238SWeidong Han if (!x2apic_preenabled && skip_ioapic_setup) { 145193758238SWeidong Han pr_info("Skipped enabling intr-remap because of skipping " 145293758238SWeidong Han "io-apic setup\n"); 1453ce69a784SGleb Natapov return 0; 1454f62bae50SIngo Molnar } 1455f62bae50SIngo Molnar 1456ce69a784SGleb Natapov if (enable_intr_remapping(x2apic_supported())) 1457ce69a784SGleb Natapov return 0; 1458ce69a784SGleb Natapov 1459ce69a784SGleb Natapov pr_info("Enabled Interrupt-remapping\n"); 1460ce69a784SGleb Natapov 1461ce69a784SGleb Natapov return 1; 1462ce69a784SGleb Natapov 1463ce69a784SGleb Natapov #endif 1464ce69a784SGleb Natapov return 0; 1465ce69a784SGleb Natapov } 1466ce69a784SGleb Natapov 1467ce69a784SGleb Natapov void __init enable_IR_x2apic(void) 1468ce69a784SGleb Natapov { 1469ce69a784SGleb Natapov unsigned long flags; 1470ce69a784SGleb Natapov struct IO_APIC_route_entry **ioapic_entries = NULL; 1471ce69a784SGleb Natapov int ret, x2apic_enabled = 0; 1472e670761fSYinghai Lu int dmar_table_init_ret; 1473b7f42ab2SYinghai Lu 1474b7f42ab2SYinghai Lu dmar_table_init_ret = dmar_table_init(); 1475e670761fSYinghai Lu if (dmar_table_init_ret && !x2apic_supported()) 1476e670761fSYinghai Lu return; 1477ce69a784SGleb Natapov 1478b24696bcSFenghua Yu ioapic_entries = alloc_ioapic_entries(); 1479b24696bcSFenghua Yu if (!ioapic_entries) { 1480ce69a784SGleb Natapov pr_err("Allocate ioapic_entries failed\n"); 1481ce69a784SGleb Natapov goto out; 1482b24696bcSFenghua Yu } 1483b24696bcSFenghua Yu 1484b24696bcSFenghua Yu ret = save_IO_APIC_setup(ioapic_entries); 1485f62bae50SIngo Molnar if (ret) { 1486f62bae50SIngo Molnar pr_info("Saving IO-APIC state failed: %d\n", ret); 1487ce69a784SGleb Natapov goto out; 1488f62bae50SIngo Molnar } 1489f62bae50SIngo Molnar 149005c3dc2cSSuresh Siddha local_irq_save(flags); 1491b81bb373SJacob Pan legacy_pic->mask_all(); 1492ce69a784SGleb Natapov mask_IO_APIC_setup(ioapic_entries); 149305c3dc2cSSuresh Siddha 1494b7f42ab2SYinghai Lu if (dmar_table_init_ret) 1495b7f42ab2SYinghai Lu ret = 0; 1496b7f42ab2SYinghai Lu else 1497ce69a784SGleb Natapov ret = enable_IR(); 1498b7f42ab2SYinghai Lu 1499ce69a784SGleb Natapov if (!ret) { 1500ce69a784SGleb Natapov /* IR is required if there is APIC ID > 255 even when running 1501ce69a784SGleb Natapov * under KVM 1502ce69a784SGleb Natapov */ 15032904ed8dSSheng Yang if (max_physical_apicid > 255 || 15042904ed8dSSheng Yang !hypervisor_x2apic_available()) 1505ce69a784SGleb Natapov goto nox2apic; 1506ce69a784SGleb Natapov /* 1507ce69a784SGleb Natapov * without IR all CPUs can be addressed by IOAPIC/MSI 1508ce69a784SGleb Natapov * only in physical mode 1509ce69a784SGleb Natapov */ 1510ce69a784SGleb Natapov x2apic_force_phys(); 1511ce69a784SGleb Natapov } 1512f62bae50SIngo Molnar 1513ce69a784SGleb Natapov x2apic_enabled = 1; 151493758238SWeidong Han 1515fc1edaf9SSuresh Siddha if (x2apic_supported() && !x2apic_mode) { 1516fc1edaf9SSuresh Siddha x2apic_mode = 1; 1517f62bae50SIngo Molnar enable_x2apic(); 151893758238SWeidong Han pr_info("Enabled x2apic\n"); 1519f62bae50SIngo Molnar } 1520f62bae50SIngo Molnar 1521ce69a784SGleb Natapov nox2apic: 1522ce69a784SGleb Natapov if (!ret) /* IR enabling failed */ 1523b24696bcSFenghua Yu restore_IO_APIC_setup(ioapic_entries); 1524b81bb373SJacob Pan legacy_pic->restore_mask(); 1525f62bae50SIngo Molnar local_irq_restore(flags); 1526f62bae50SIngo Molnar 1527ce69a784SGleb Natapov out: 1528b24696bcSFenghua Yu if (ioapic_entries) 1529b24696bcSFenghua Yu free_ioapic_entries(ioapic_entries); 153093758238SWeidong Han 1531ce69a784SGleb Natapov if (x2apic_enabled) 153293758238SWeidong Han return; 153393758238SWeidong Han 153493758238SWeidong Han if (x2apic_preenabled) 1535ce69a784SGleb Natapov panic("x2apic: enabled by BIOS but kernel init failed."); 153693758238SWeidong Han else if (cpu_has_x2apic) 1537ce69a784SGleb Natapov pr_info("Not enabling x2apic, Intr-remapping init failed.\n"); 1538f62bae50SIngo Molnar } 153993758238SWeidong Han 1540f62bae50SIngo Molnar #ifdef CONFIG_X86_64 1541f62bae50SIngo Molnar /* 1542f62bae50SIngo Molnar * Detect and enable local APICs on non-SMP boards. 1543f62bae50SIngo Molnar * Original code written by Keir Fraser. 1544f62bae50SIngo Molnar * On AMD64 we trust the BIOS - if it says no APIC it is likely 1545f62bae50SIngo Molnar * not correctly set up (usually the APIC timer won't work etc.) 1546f62bae50SIngo Molnar */ 1547f62bae50SIngo Molnar static int __init detect_init_APIC(void) 1548f62bae50SIngo Molnar { 1549f62bae50SIngo Molnar if (!cpu_has_apic) { 1550f62bae50SIngo Molnar pr_info("No local APIC present\n"); 1551f62bae50SIngo Molnar return -1; 1552f62bae50SIngo Molnar } 1553f62bae50SIngo Molnar 1554f62bae50SIngo Molnar mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1555f62bae50SIngo Molnar return 0; 1556f62bae50SIngo Molnar } 1557f62bae50SIngo Molnar #else 15585a7ae78fSThomas Gleixner 15595a7ae78fSThomas Gleixner static int apic_verify(void) 15605a7ae78fSThomas Gleixner { 15615a7ae78fSThomas Gleixner u32 features, h, l; 15625a7ae78fSThomas Gleixner 15635a7ae78fSThomas Gleixner /* 15645a7ae78fSThomas Gleixner * The APIC feature bit should now be enabled 15655a7ae78fSThomas Gleixner * in `cpuid' 15665a7ae78fSThomas Gleixner */ 15675a7ae78fSThomas Gleixner features = cpuid_edx(1); 15685a7ae78fSThomas Gleixner if (!(features & (1 << X86_FEATURE_APIC))) { 15695a7ae78fSThomas Gleixner pr_warning("Could not enable APIC!\n"); 15705a7ae78fSThomas Gleixner return -1; 15715a7ae78fSThomas Gleixner } 15725a7ae78fSThomas Gleixner set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 15735a7ae78fSThomas Gleixner mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 15745a7ae78fSThomas Gleixner 15755a7ae78fSThomas Gleixner /* The BIOS may have set up the APIC at some other address */ 15765a7ae78fSThomas Gleixner rdmsr(MSR_IA32_APICBASE, l, h); 15775a7ae78fSThomas Gleixner if (l & MSR_IA32_APICBASE_ENABLE) 15785a7ae78fSThomas Gleixner mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 15795a7ae78fSThomas Gleixner 15805a7ae78fSThomas Gleixner pr_info("Found and enabled local APIC!\n"); 15815a7ae78fSThomas Gleixner return 0; 15825a7ae78fSThomas Gleixner } 15835a7ae78fSThomas Gleixner 15845a7ae78fSThomas Gleixner int apic_force_enable(void) 15855a7ae78fSThomas Gleixner { 15865a7ae78fSThomas Gleixner u32 h, l; 15875a7ae78fSThomas Gleixner 15885a7ae78fSThomas Gleixner if (disable_apic) 15895a7ae78fSThomas Gleixner return -1; 15905a7ae78fSThomas Gleixner 15915a7ae78fSThomas Gleixner /* 15925a7ae78fSThomas Gleixner * Some BIOSes disable the local APIC in the APIC_BASE 15935a7ae78fSThomas Gleixner * MSR. This can only be done in software for Intel P6 or later 15945a7ae78fSThomas Gleixner * and AMD K7 (Model > 1) or later. 15955a7ae78fSThomas Gleixner */ 15965a7ae78fSThomas Gleixner rdmsr(MSR_IA32_APICBASE, l, h); 15975a7ae78fSThomas Gleixner if (!(l & MSR_IA32_APICBASE_ENABLE)) { 15985a7ae78fSThomas Gleixner pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 15995a7ae78fSThomas Gleixner l &= ~MSR_IA32_APICBASE_BASE; 16005a7ae78fSThomas Gleixner l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; 16015a7ae78fSThomas Gleixner wrmsr(MSR_IA32_APICBASE, l, h); 16025a7ae78fSThomas Gleixner enabled_via_apicbase = 1; 16035a7ae78fSThomas Gleixner } 16045a7ae78fSThomas Gleixner return apic_verify(); 16055a7ae78fSThomas Gleixner } 16065a7ae78fSThomas Gleixner 1607f62bae50SIngo Molnar /* 1608f62bae50SIngo Molnar * Detect and initialize APIC 1609f62bae50SIngo Molnar */ 1610f62bae50SIngo Molnar static int __init detect_init_APIC(void) 1611f62bae50SIngo Molnar { 1612f62bae50SIngo Molnar /* Disabled by kernel option? */ 1613f62bae50SIngo Molnar if (disable_apic) 1614f62bae50SIngo Molnar return -1; 1615f62bae50SIngo Molnar 1616f62bae50SIngo Molnar switch (boot_cpu_data.x86_vendor) { 1617f62bae50SIngo Molnar case X86_VENDOR_AMD: 1618f62bae50SIngo Molnar if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1619f62bae50SIngo Molnar (boot_cpu_data.x86 >= 15)) 1620f62bae50SIngo Molnar break; 1621f62bae50SIngo Molnar goto no_apic; 1622f62bae50SIngo Molnar case X86_VENDOR_INTEL: 1623f62bae50SIngo Molnar if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1624f62bae50SIngo Molnar (boot_cpu_data.x86 == 5 && cpu_has_apic)) 1625f62bae50SIngo Molnar break; 1626f62bae50SIngo Molnar goto no_apic; 1627f62bae50SIngo Molnar default: 1628f62bae50SIngo Molnar goto no_apic; 1629f62bae50SIngo Molnar } 1630f62bae50SIngo Molnar 1631f62bae50SIngo Molnar if (!cpu_has_apic) { 1632f62bae50SIngo Molnar /* 1633f62bae50SIngo Molnar * Over-ride BIOS and try to enable the local APIC only if 1634f62bae50SIngo Molnar * "lapic" specified. 1635f62bae50SIngo Molnar */ 1636f62bae50SIngo Molnar if (!force_enable_local_apic) { 1637f62bae50SIngo Molnar pr_info("Local APIC disabled by BIOS -- " 1638f62bae50SIngo Molnar "you can enable it with \"lapic\"\n"); 1639f62bae50SIngo Molnar return -1; 1640f62bae50SIngo Molnar } 16415a7ae78fSThomas Gleixner if (apic_force_enable()) 16425a7ae78fSThomas Gleixner return -1; 16435a7ae78fSThomas Gleixner } else { 16445a7ae78fSThomas Gleixner if (apic_verify()) 1645f62bae50SIngo Molnar return -1; 1646f62bae50SIngo Molnar } 1647f62bae50SIngo Molnar 1648f62bae50SIngo Molnar apic_pm_activate(); 1649f62bae50SIngo Molnar 1650f62bae50SIngo Molnar return 0; 1651f62bae50SIngo Molnar 1652f62bae50SIngo Molnar no_apic: 1653f62bae50SIngo Molnar pr_info("No local APIC present or hardware disabled\n"); 1654f62bae50SIngo Molnar return -1; 1655f62bae50SIngo Molnar } 1656f62bae50SIngo Molnar #endif 1657f62bae50SIngo Molnar 1658f62bae50SIngo Molnar /** 1659f62bae50SIngo Molnar * init_apic_mappings - initialize APIC mappings 1660f62bae50SIngo Molnar */ 1661f62bae50SIngo Molnar void __init init_apic_mappings(void) 1662f62bae50SIngo Molnar { 16634401da61SYinghai Lu unsigned int new_apicid; 16644401da61SYinghai Lu 1665fc1edaf9SSuresh Siddha if (x2apic_mode) { 1666f62bae50SIngo Molnar boot_cpu_physical_apicid = read_apic_id(); 1667f62bae50SIngo Molnar return; 1668f62bae50SIngo Molnar } 1669f62bae50SIngo Molnar 16704797f6b0SYinghai Lu /* If no local APIC can be found return early */ 1671f62bae50SIngo Molnar if (!smp_found_config && detect_init_APIC()) { 16724797f6b0SYinghai Lu /* lets NOP'ify apic operations */ 16734797f6b0SYinghai Lu pr_info("APIC: disable apic facility\n"); 16744797f6b0SYinghai Lu apic_disable(); 16754797f6b0SYinghai Lu } else { 1676f62bae50SIngo Molnar apic_phys = mp_lapic_addr; 1677f62bae50SIngo Molnar 16784401da61SYinghai Lu /* 16794401da61SYinghai Lu * acpi lapic path already maps that address in 16804401da61SYinghai Lu * acpi_register_lapic_address() 16814401da61SYinghai Lu */ 16825989cd6aSEric W. Biederman if (!acpi_lapic && !smp_found_config) 1683326a2e6bSYinghai Lu register_lapic_address(apic_phys); 1684cec6be6dSCyrill Gorcunov } 1685f62bae50SIngo Molnar 1686f62bae50SIngo Molnar /* 1687f62bae50SIngo Molnar * Fetch the APIC ID of the BSP in case we have a 1688f62bae50SIngo Molnar * default configuration (or the MP table is broken). 1689f62bae50SIngo Molnar */ 16904401da61SYinghai Lu new_apicid = read_apic_id(); 16914401da61SYinghai Lu if (boot_cpu_physical_apicid != new_apicid) { 16924401da61SYinghai Lu boot_cpu_physical_apicid = new_apicid; 1693103428e5SCyrill Gorcunov /* 1694103428e5SCyrill Gorcunov * yeah -- we lie about apic_version 1695103428e5SCyrill Gorcunov * in case if apic was disabled via boot option 1696103428e5SCyrill Gorcunov * but it's not a problem for SMP compiled kernel 1697103428e5SCyrill Gorcunov * since smp_sanity_check is prepared for such a case 1698103428e5SCyrill Gorcunov * and disable smp mode 1699103428e5SCyrill Gorcunov */ 17004401da61SYinghai Lu apic_version[new_apicid] = 17014401da61SYinghai Lu GET_APIC_VERSION(apic_read(APIC_LVR)); 170208306ce6SCyrill Gorcunov } 1703f62bae50SIngo Molnar } 1704f62bae50SIngo Molnar 1705c0104d38SYinghai Lu void __init register_lapic_address(unsigned long address) 1706c0104d38SYinghai Lu { 1707c0104d38SYinghai Lu mp_lapic_addr = address; 1708c0104d38SYinghai Lu 17090450193bSYinghai Lu if (!x2apic_mode) { 1710c0104d38SYinghai Lu set_fixmap_nocache(FIX_APIC_BASE, address); 1711f1157141SYinghai Lu apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 1712f1157141SYinghai Lu APIC_BASE, mp_lapic_addr); 17130450193bSYinghai Lu } 1714c0104d38SYinghai Lu if (boot_cpu_physical_apicid == -1U) { 1715c0104d38SYinghai Lu boot_cpu_physical_apicid = read_apic_id(); 1716c0104d38SYinghai Lu apic_version[boot_cpu_physical_apicid] = 1717c0104d38SYinghai Lu GET_APIC_VERSION(apic_read(APIC_LVR)); 1718c0104d38SYinghai Lu } 1719c0104d38SYinghai Lu } 1720c0104d38SYinghai Lu 1721f62bae50SIngo Molnar /* 1722f62bae50SIngo Molnar * This initializes the IO-APIC and APIC hardware if this is 1723f62bae50SIngo Molnar * a UP kernel. 1724f62bae50SIngo Molnar */ 172556d91f13SYinghai Lu int apic_version[MAX_LOCAL_APIC]; 1726f62bae50SIngo Molnar 1727f62bae50SIngo Molnar int __init APIC_init_uniprocessor(void) 1728f62bae50SIngo Molnar { 1729f62bae50SIngo Molnar if (disable_apic) { 1730f62bae50SIngo Molnar pr_info("Apic disabled\n"); 1731f62bae50SIngo Molnar return -1; 1732f62bae50SIngo Molnar } 1733f62bae50SIngo Molnar #ifdef CONFIG_X86_64 1734f62bae50SIngo Molnar if (!cpu_has_apic) { 1735f62bae50SIngo Molnar disable_apic = 1; 1736f62bae50SIngo Molnar pr_info("Apic disabled by BIOS\n"); 1737f62bae50SIngo Molnar return -1; 1738f62bae50SIngo Molnar } 1739f62bae50SIngo Molnar #else 1740f62bae50SIngo Molnar if (!smp_found_config && !cpu_has_apic) 1741f62bae50SIngo Molnar return -1; 1742f62bae50SIngo Molnar 1743f62bae50SIngo Molnar /* 1744f62bae50SIngo Molnar * Complain if the BIOS pretends there is one. 1745f62bae50SIngo Molnar */ 1746f62bae50SIngo Molnar if (!cpu_has_apic && 1747f62bae50SIngo Molnar APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 1748f62bae50SIngo Molnar pr_err("BIOS bug, local APIC 0x%x not detected!...\n", 1749f62bae50SIngo Molnar boot_cpu_physical_apicid); 1750f62bae50SIngo Molnar return -1; 1751f62bae50SIngo Molnar } 1752f62bae50SIngo Molnar #endif 1753f62bae50SIngo Molnar 1754f62bae50SIngo Molnar default_setup_apic_routing(); 1755f62bae50SIngo Molnar 1756f62bae50SIngo Molnar verify_local_APIC(); 1757f62bae50SIngo Molnar connect_bsp_APIC(); 1758f62bae50SIngo Molnar 1759f62bae50SIngo Molnar #ifdef CONFIG_X86_64 1760f62bae50SIngo Molnar apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); 1761f62bae50SIngo Molnar #else 1762f62bae50SIngo Molnar /* 1763f62bae50SIngo Molnar * Hack: In case of kdump, after a crash, kernel might be booting 1764f62bae50SIngo Molnar * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 1765f62bae50SIngo Molnar * might be zero if read from MP tables. Get it from LAPIC. 1766f62bae50SIngo Molnar */ 1767f62bae50SIngo Molnar # ifdef CONFIG_CRASH_DUMP 1768f62bae50SIngo Molnar boot_cpu_physical_apicid = read_apic_id(); 1769f62bae50SIngo Molnar # endif 1770f62bae50SIngo Molnar #endif 1771f62bae50SIngo Molnar physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1772f62bae50SIngo Molnar setup_local_APIC(); 1773f62bae50SIngo Molnar 1774f62bae50SIngo Molnar #ifdef CONFIG_X86_IO_APIC 1775f62bae50SIngo Molnar /* 1776f62bae50SIngo Molnar * Now enable IO-APICs, actually call clear_IO_APIC 1777f62bae50SIngo Molnar * We need clear_IO_APIC before enabling error vector 1778f62bae50SIngo Molnar */ 1779f62bae50SIngo Molnar if (!skip_ioapic_setup && nr_ioapics) 1780f62bae50SIngo Molnar enable_IO_APIC(); 1781f62bae50SIngo Molnar #endif 1782f62bae50SIngo Molnar 1783f62bae50SIngo Molnar end_local_APIC_setup(); 1784f62bae50SIngo Molnar 1785f62bae50SIngo Molnar #ifdef CONFIG_X86_IO_APIC 1786f62bae50SIngo Molnar if (smp_found_config && !skip_ioapic_setup && nr_ioapics) 1787f62bae50SIngo Molnar setup_IO_APIC(); 1788f62bae50SIngo Molnar else { 1789f62bae50SIngo Molnar nr_ioapics = 0; 1790f62bae50SIngo Molnar } 1791f62bae50SIngo Molnar #endif 1792f62bae50SIngo Molnar 1793736decacSThomas Gleixner x86_init.timers.setup_percpu_clockev(); 1794f62bae50SIngo Molnar return 0; 1795f62bae50SIngo Molnar } 1796f62bae50SIngo Molnar 1797f62bae50SIngo Molnar /* 1798f62bae50SIngo Molnar * Local APIC interrupts 1799f62bae50SIngo Molnar */ 1800f62bae50SIngo Molnar 1801f62bae50SIngo Molnar /* 1802f62bae50SIngo Molnar * This interrupt should _never_ happen with our APIC/SMP architecture 1803f62bae50SIngo Molnar */ 1804f62bae50SIngo Molnar void smp_spurious_interrupt(struct pt_regs *regs) 1805f62bae50SIngo Molnar { 1806f62bae50SIngo Molnar u32 v; 1807f62bae50SIngo Molnar 1808f62bae50SIngo Molnar exit_idle(); 1809f62bae50SIngo Molnar irq_enter(); 1810f62bae50SIngo Molnar /* 1811f62bae50SIngo Molnar * Check if this really is a spurious interrupt and ACK it 1812f62bae50SIngo Molnar * if it is a vectored one. Just in case... 1813f62bae50SIngo Molnar * Spurious interrupts should not be ACKed. 1814f62bae50SIngo Molnar */ 1815f62bae50SIngo Molnar v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); 1816f62bae50SIngo Molnar if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) 1817f62bae50SIngo Molnar ack_APIC_irq(); 1818f62bae50SIngo Molnar 1819f62bae50SIngo Molnar inc_irq_stat(irq_spurious_count); 1820f62bae50SIngo Molnar 1821f62bae50SIngo Molnar /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 1822f62bae50SIngo Molnar pr_info("spurious APIC interrupt on CPU#%d, " 1823f62bae50SIngo Molnar "should never happen.\n", smp_processor_id()); 1824f62bae50SIngo Molnar irq_exit(); 1825f62bae50SIngo Molnar } 1826f62bae50SIngo Molnar 1827f62bae50SIngo Molnar /* 1828f62bae50SIngo Molnar * This interrupt should never happen with our APIC/SMP architecture 1829f62bae50SIngo Molnar */ 1830f62bae50SIngo Molnar void smp_error_interrupt(struct pt_regs *regs) 1831f62bae50SIngo Molnar { 1832f62bae50SIngo Molnar u32 v, v1; 1833f62bae50SIngo Molnar 1834f62bae50SIngo Molnar exit_idle(); 1835f62bae50SIngo Molnar irq_enter(); 1836f62bae50SIngo Molnar /* First tickle the hardware, only then report what went on. -- REW */ 1837f62bae50SIngo Molnar v = apic_read(APIC_ESR); 1838f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1839f62bae50SIngo Molnar v1 = apic_read(APIC_ESR); 1840f62bae50SIngo Molnar ack_APIC_irq(); 1841f62bae50SIngo Molnar atomic_inc(&irq_err_count); 1842f62bae50SIngo Molnar 1843f62bae50SIngo Molnar /* 1844f62bae50SIngo Molnar * Here is what the APIC error bits mean: 1845f62bae50SIngo Molnar * 0: Send CS error 1846f62bae50SIngo Molnar * 1: Receive CS error 1847f62bae50SIngo Molnar * 2: Send accept error 1848f62bae50SIngo Molnar * 3: Receive accept error 1849f62bae50SIngo Molnar * 4: Reserved 1850f62bae50SIngo Molnar * 5: Send illegal vector 1851f62bae50SIngo Molnar * 6: Received illegal vector 1852f62bae50SIngo Molnar * 7: Illegal register address 1853f62bae50SIngo Molnar */ 1854f62bae50SIngo Molnar pr_debug("APIC error on CPU%d: %02x(%02x)\n", 1855f62bae50SIngo Molnar smp_processor_id(), v , v1); 1856f62bae50SIngo Molnar irq_exit(); 1857f62bae50SIngo Molnar } 1858f62bae50SIngo Molnar 1859f62bae50SIngo Molnar /** 1860f62bae50SIngo Molnar * connect_bsp_APIC - attach the APIC to the interrupt system 1861f62bae50SIngo Molnar */ 1862f62bae50SIngo Molnar void __init connect_bsp_APIC(void) 1863f62bae50SIngo Molnar { 1864f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1865f62bae50SIngo Molnar if (pic_mode) { 1866f62bae50SIngo Molnar /* 1867f62bae50SIngo Molnar * Do not trust the local APIC being empty at bootup. 1868f62bae50SIngo Molnar */ 1869f62bae50SIngo Molnar clear_local_APIC(); 1870f62bae50SIngo Molnar /* 1871f62bae50SIngo Molnar * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 1872f62bae50SIngo Molnar * local APIC to INT and NMI lines. 1873f62bae50SIngo Molnar */ 1874f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "leaving PIC mode, " 1875f62bae50SIngo Molnar "enabling APIC mode.\n"); 1876c0eaa453SCyrill Gorcunov imcr_pic_to_apic(); 1877f62bae50SIngo Molnar } 1878f62bae50SIngo Molnar #endif 1879f62bae50SIngo Molnar if (apic->enable_apic_mode) 1880f62bae50SIngo Molnar apic->enable_apic_mode(); 1881f62bae50SIngo Molnar } 1882f62bae50SIngo Molnar 1883f62bae50SIngo Molnar /** 1884f62bae50SIngo Molnar * disconnect_bsp_APIC - detach the APIC from the interrupt system 1885f62bae50SIngo Molnar * @virt_wire_setup: indicates, whether virtual wire mode is selected 1886f62bae50SIngo Molnar * 1887f62bae50SIngo Molnar * Virtual wire mode is necessary to deliver legacy interrupts even when the 1888f62bae50SIngo Molnar * APIC is disabled. 1889f62bae50SIngo Molnar */ 1890f62bae50SIngo Molnar void disconnect_bsp_APIC(int virt_wire_setup) 1891f62bae50SIngo Molnar { 1892f62bae50SIngo Molnar unsigned int value; 1893f62bae50SIngo Molnar 1894f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1895f62bae50SIngo Molnar if (pic_mode) { 1896f62bae50SIngo Molnar /* 1897f62bae50SIngo Molnar * Put the board back into PIC mode (has an effect only on 1898f62bae50SIngo Molnar * certain older boards). Note that APIC interrupts, including 1899f62bae50SIngo Molnar * IPIs, won't work beyond this point! The only exception are 1900f62bae50SIngo Molnar * INIT IPIs. 1901f62bae50SIngo Molnar */ 1902f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "disabling APIC mode, " 1903f62bae50SIngo Molnar "entering PIC mode.\n"); 1904c0eaa453SCyrill Gorcunov imcr_apic_to_pic(); 1905f62bae50SIngo Molnar return; 1906f62bae50SIngo Molnar } 1907f62bae50SIngo Molnar #endif 1908f62bae50SIngo Molnar 1909f62bae50SIngo Molnar /* Go back to Virtual Wire compatibility mode */ 1910f62bae50SIngo Molnar 1911f62bae50SIngo Molnar /* For the spurious interrupt use vector F, and enable it */ 1912f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 1913f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 1914f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 1915f62bae50SIngo Molnar value |= 0xf; 1916f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 1917f62bae50SIngo Molnar 1918f62bae50SIngo Molnar if (!virt_wire_setup) { 1919f62bae50SIngo Molnar /* 1920f62bae50SIngo Molnar * For LVT0 make it edge triggered, active high, 1921f62bae50SIngo Molnar * external and enabled 1922f62bae50SIngo Molnar */ 1923f62bae50SIngo Molnar value = apic_read(APIC_LVT0); 1924f62bae50SIngo Molnar value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1925f62bae50SIngo Molnar APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1926f62bae50SIngo Molnar APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1927f62bae50SIngo Molnar value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1928f62bae50SIngo Molnar value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 1929f62bae50SIngo Molnar apic_write(APIC_LVT0, value); 1930f62bae50SIngo Molnar } else { 1931f62bae50SIngo Molnar /* Disable LVT0 */ 1932f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_LVT_MASKED); 1933f62bae50SIngo Molnar } 1934f62bae50SIngo Molnar 1935f62bae50SIngo Molnar /* 1936f62bae50SIngo Molnar * For LVT1 make it edge triggered, active high, 1937f62bae50SIngo Molnar * nmi and enabled 1938f62bae50SIngo Molnar */ 1939f62bae50SIngo Molnar value = apic_read(APIC_LVT1); 1940f62bae50SIngo Molnar value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1941f62bae50SIngo Molnar APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1942f62bae50SIngo Molnar APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1943f62bae50SIngo Molnar value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1944f62bae50SIngo Molnar value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 1945f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 1946f62bae50SIngo Molnar } 1947f62bae50SIngo Molnar 1948f62bae50SIngo Molnar void __cpuinit generic_processor_info(int apicid, int version) 1949f62bae50SIngo Molnar { 1950f62bae50SIngo Molnar int cpu; 1951f62bae50SIngo Molnar 1952f62bae50SIngo Molnar /* 1953f62bae50SIngo Molnar * Validate version 1954f62bae50SIngo Molnar */ 1955f62bae50SIngo Molnar if (version == 0x0) { 1956f62bae50SIngo Molnar pr_warning("BIOS bug, APIC version is 0 for CPU#%d! " 1957f62bae50SIngo Molnar "fixing up to 0x10. (tell your hw vendor)\n", 1958f62bae50SIngo Molnar version); 1959f62bae50SIngo Molnar version = 0x10; 1960f62bae50SIngo Molnar } 1961f62bae50SIngo Molnar apic_version[apicid] = version; 1962f62bae50SIngo Molnar 1963f62bae50SIngo Molnar if (num_processors >= nr_cpu_ids) { 1964f62bae50SIngo Molnar int max = nr_cpu_ids; 1965f62bae50SIngo Molnar int thiscpu = max + disabled_cpus; 1966f62bae50SIngo Molnar 1967f62bae50SIngo Molnar pr_warning( 1968f62bae50SIngo Molnar "ACPI: NR_CPUS/possible_cpus limit of %i reached." 1969f62bae50SIngo Molnar " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 1970f62bae50SIngo Molnar 1971f62bae50SIngo Molnar disabled_cpus++; 1972f62bae50SIngo Molnar return; 1973f62bae50SIngo Molnar } 1974f62bae50SIngo Molnar 1975f62bae50SIngo Molnar num_processors++; 1976f62bae50SIngo Molnar cpu = cpumask_next_zero(-1, cpu_present_mask); 1977f62bae50SIngo Molnar 1978f62bae50SIngo Molnar if (version != apic_version[boot_cpu_physical_apicid]) 1979f62bae50SIngo Molnar WARN_ONCE(1, 1980f62bae50SIngo Molnar "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n", 1981f62bae50SIngo Molnar apic_version[boot_cpu_physical_apicid], cpu, version); 1982f62bae50SIngo Molnar 1983f62bae50SIngo Molnar physid_set(apicid, phys_cpu_present_map); 1984f62bae50SIngo Molnar if (apicid == boot_cpu_physical_apicid) { 1985f62bae50SIngo Molnar /* 1986f62bae50SIngo Molnar * x86_bios_cpu_apicid is required to have processors listed 1987f62bae50SIngo Molnar * in same order as logical cpu numbers. Hence the first 1988f62bae50SIngo Molnar * entry is BSP, and so on. 1989f62bae50SIngo Molnar */ 1990f62bae50SIngo Molnar cpu = 0; 1991f62bae50SIngo Molnar } 1992f62bae50SIngo Molnar if (apicid > max_physical_apicid) 1993f62bae50SIngo Molnar max_physical_apicid = apicid; 1994f62bae50SIngo Molnar 1995f62bae50SIngo Molnar #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 1996f62bae50SIngo Molnar early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 1997f62bae50SIngo Molnar early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 1998f62bae50SIngo Molnar #endif 1999acb8bc09STejun Heo #ifdef CONFIG_X86_32 2000acb8bc09STejun Heo early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 2001acb8bc09STejun Heo apic->x86_32_early_logical_apicid(cpu); 2002acb8bc09STejun Heo #endif 2003f62bae50SIngo Molnar set_cpu_possible(cpu, true); 2004f62bae50SIngo Molnar set_cpu_present(cpu, true); 2005f62bae50SIngo Molnar } 2006f62bae50SIngo Molnar 2007f62bae50SIngo Molnar int hard_smp_processor_id(void) 2008f62bae50SIngo Molnar { 2009f62bae50SIngo Molnar return read_apic_id(); 2010f62bae50SIngo Molnar } 2011f62bae50SIngo Molnar 2012f62bae50SIngo Molnar void default_init_apic_ldr(void) 2013f62bae50SIngo Molnar { 2014f62bae50SIngo Molnar unsigned long val; 2015f62bae50SIngo Molnar 2016f62bae50SIngo Molnar apic_write(APIC_DFR, APIC_DFR_VALUE); 2017f62bae50SIngo Molnar val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; 2018f62bae50SIngo Molnar val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); 2019f62bae50SIngo Molnar apic_write(APIC_LDR, val); 2020f62bae50SIngo Molnar } 2021f62bae50SIngo Molnar 2022f62bae50SIngo Molnar #ifdef CONFIG_X86_32 2023f62bae50SIngo Molnar int default_apicid_to_node(int logical_apicid) 2024f62bae50SIngo Molnar { 2025f62bae50SIngo Molnar #ifdef CONFIG_SMP 2026f62bae50SIngo Molnar return apicid_2_node[hard_smp_processor_id()]; 2027f62bae50SIngo Molnar #else 2028f62bae50SIngo Molnar return 0; 2029f62bae50SIngo Molnar #endif 2030f62bae50SIngo Molnar } 2031f62bae50SIngo Molnar #endif 2032f62bae50SIngo Molnar 2033f62bae50SIngo Molnar /* 2034f62bae50SIngo Molnar * Power management 2035f62bae50SIngo Molnar */ 2036f62bae50SIngo Molnar #ifdef CONFIG_PM 2037f62bae50SIngo Molnar 2038f62bae50SIngo Molnar static struct { 2039f62bae50SIngo Molnar /* 2040f62bae50SIngo Molnar * 'active' is true if the local APIC was enabled by us and 2041f62bae50SIngo Molnar * not the BIOS; this signifies that we are also responsible 2042f62bae50SIngo Molnar * for disabling it before entering apm/acpi suspend 2043f62bae50SIngo Molnar */ 2044f62bae50SIngo Molnar int active; 2045f62bae50SIngo Molnar /* r/w apic fields */ 2046f62bae50SIngo Molnar unsigned int apic_id; 2047f62bae50SIngo Molnar unsigned int apic_taskpri; 2048f62bae50SIngo Molnar unsigned int apic_ldr; 2049f62bae50SIngo Molnar unsigned int apic_dfr; 2050f62bae50SIngo Molnar unsigned int apic_spiv; 2051f62bae50SIngo Molnar unsigned int apic_lvtt; 2052f62bae50SIngo Molnar unsigned int apic_lvtpc; 2053f62bae50SIngo Molnar unsigned int apic_lvt0; 2054f62bae50SIngo Molnar unsigned int apic_lvt1; 2055f62bae50SIngo Molnar unsigned int apic_lvterr; 2056f62bae50SIngo Molnar unsigned int apic_tmict; 2057f62bae50SIngo Molnar unsigned int apic_tdcr; 2058f62bae50SIngo Molnar unsigned int apic_thmr; 2059f62bae50SIngo Molnar } apic_pm_state; 2060f62bae50SIngo Molnar 2061f62bae50SIngo Molnar static int lapic_suspend(struct sys_device *dev, pm_message_t state) 2062f62bae50SIngo Molnar { 2063f62bae50SIngo Molnar unsigned long flags; 2064f62bae50SIngo Molnar int maxlvt; 2065f62bae50SIngo Molnar 2066f62bae50SIngo Molnar if (!apic_pm_state.active) 2067f62bae50SIngo Molnar return 0; 2068f62bae50SIngo Molnar 2069f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 2070f62bae50SIngo Molnar 2071f62bae50SIngo Molnar apic_pm_state.apic_id = apic_read(APIC_ID); 2072f62bae50SIngo Molnar apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2073f62bae50SIngo Molnar apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2074f62bae50SIngo Molnar apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2075f62bae50SIngo Molnar apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2076f62bae50SIngo Molnar apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2077f62bae50SIngo Molnar if (maxlvt >= 4) 2078f62bae50SIngo Molnar apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2079f62bae50SIngo Molnar apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2080f62bae50SIngo Molnar apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2081f62bae50SIngo Molnar apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2082f62bae50SIngo Molnar apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2083f62bae50SIngo Molnar apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 20844efc0670SAndi Kleen #ifdef CONFIG_X86_THERMAL_VECTOR 2085f62bae50SIngo Molnar if (maxlvt >= 5) 2086f62bae50SIngo Molnar apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2087f62bae50SIngo Molnar #endif 2088f62bae50SIngo Molnar 2089f62bae50SIngo Molnar local_irq_save(flags); 2090f62bae50SIngo Molnar disable_local_APIC(); 2091fc1edaf9SSuresh Siddha 2092b24696bcSFenghua Yu if (intr_remapping_enabled) 2093b24696bcSFenghua Yu disable_intr_remapping(); 2094fc1edaf9SSuresh Siddha 2095f62bae50SIngo Molnar local_irq_restore(flags); 2096f62bae50SIngo Molnar return 0; 2097f62bae50SIngo Molnar } 2098f62bae50SIngo Molnar 2099f62bae50SIngo Molnar static int lapic_resume(struct sys_device *dev) 2100f62bae50SIngo Molnar { 2101f62bae50SIngo Molnar unsigned int l, h; 2102f62bae50SIngo Molnar unsigned long flags; 2103f62bae50SIngo Molnar int maxlvt; 21043d58829bSJiri Slaby int ret = 0; 2105b24696bcSFenghua Yu struct IO_APIC_route_entry **ioapic_entries = NULL; 2106b24696bcSFenghua Yu 2107f62bae50SIngo Molnar if (!apic_pm_state.active) 2108f62bae50SIngo Molnar return 0; 2109f62bae50SIngo Molnar 2110b24696bcSFenghua Yu local_irq_save(flags); 21119a2755c3SWeidong Han if (intr_remapping_enabled) { 2112b24696bcSFenghua Yu ioapic_entries = alloc_ioapic_entries(); 2113b24696bcSFenghua Yu if (!ioapic_entries) { 2114b24696bcSFenghua Yu WARN(1, "Alloc ioapic_entries in lapic resume failed."); 21153d58829bSJiri Slaby ret = -ENOMEM; 21163d58829bSJiri Slaby goto restore; 2117b24696bcSFenghua Yu } 2118b24696bcSFenghua Yu 2119b24696bcSFenghua Yu ret = save_IO_APIC_setup(ioapic_entries); 2120b24696bcSFenghua Yu if (ret) { 2121b24696bcSFenghua Yu WARN(1, "Saving IO-APIC state failed: %d\n", ret); 2122b24696bcSFenghua Yu free_ioapic_entries(ioapic_entries); 21233d58829bSJiri Slaby goto restore; 2124b24696bcSFenghua Yu } 2125b24696bcSFenghua Yu 2126b24696bcSFenghua Yu mask_IO_APIC_setup(ioapic_entries); 2127b81bb373SJacob Pan legacy_pic->mask_all(); 2128b24696bcSFenghua Yu } 2129f62bae50SIngo Molnar 2130fc1edaf9SSuresh Siddha if (x2apic_mode) 2131f62bae50SIngo Molnar enable_x2apic(); 2132cf6567feSSuresh Siddha else { 2133f62bae50SIngo Molnar /* 2134f62bae50SIngo Molnar * Make sure the APICBASE points to the right address 2135f62bae50SIngo Molnar * 2136f62bae50SIngo Molnar * FIXME! This will be wrong if we ever support suspend on 2137f62bae50SIngo Molnar * SMP! We'll need to do this as part of the CPU restore! 2138f62bae50SIngo Molnar */ 2139f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, l, h); 2140f62bae50SIngo Molnar l &= ~MSR_IA32_APICBASE_BASE; 2141f62bae50SIngo Molnar l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2142f62bae50SIngo Molnar wrmsr(MSR_IA32_APICBASE, l, h); 2143f62bae50SIngo Molnar } 2144f62bae50SIngo Molnar 2145b24696bcSFenghua Yu maxlvt = lapic_get_maxlvt(); 2146f62bae50SIngo Molnar apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2147f62bae50SIngo Molnar apic_write(APIC_ID, apic_pm_state.apic_id); 2148f62bae50SIngo Molnar apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2149f62bae50SIngo Molnar apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2150f62bae50SIngo Molnar apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2151f62bae50SIngo Molnar apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2152f62bae50SIngo Molnar apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2153f62bae50SIngo Molnar apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2154f62bae50SIngo Molnar #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) 2155f62bae50SIngo Molnar if (maxlvt >= 5) 2156f62bae50SIngo Molnar apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2157f62bae50SIngo Molnar #endif 2158f62bae50SIngo Molnar if (maxlvt >= 4) 2159f62bae50SIngo Molnar apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2160f62bae50SIngo Molnar apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2161f62bae50SIngo Molnar apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2162f62bae50SIngo Molnar apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2163f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 2164f62bae50SIngo Molnar apic_read(APIC_ESR); 2165f62bae50SIngo Molnar apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2166f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 2167f62bae50SIngo Molnar apic_read(APIC_ESR); 2168f62bae50SIngo Molnar 21699a2755c3SWeidong Han if (intr_remapping_enabled) { 2170fc1edaf9SSuresh Siddha reenable_intr_remapping(x2apic_mode); 2171b81bb373SJacob Pan legacy_pic->restore_mask(); 2172b24696bcSFenghua Yu restore_IO_APIC_setup(ioapic_entries); 2173b24696bcSFenghua Yu free_ioapic_entries(ioapic_entries); 2174b24696bcSFenghua Yu } 21753d58829bSJiri Slaby restore: 2176f62bae50SIngo Molnar local_irq_restore(flags); 2177f62bae50SIngo Molnar 21783d58829bSJiri Slaby return ret; 2179f62bae50SIngo Molnar } 2180f62bae50SIngo Molnar 2181f62bae50SIngo Molnar /* 2182f62bae50SIngo Molnar * This device has no shutdown method - fully functioning local APICs 2183f62bae50SIngo Molnar * are needed on every CPU up until machine_halt/restart/poweroff. 2184f62bae50SIngo Molnar */ 2185f62bae50SIngo Molnar 2186f62bae50SIngo Molnar static struct sysdev_class lapic_sysclass = { 2187f62bae50SIngo Molnar .name = "lapic", 2188f62bae50SIngo Molnar .resume = lapic_resume, 2189f62bae50SIngo Molnar .suspend = lapic_suspend, 2190f62bae50SIngo Molnar }; 2191f62bae50SIngo Molnar 2192f62bae50SIngo Molnar static struct sys_device device_lapic = { 2193f62bae50SIngo Molnar .id = 0, 2194f62bae50SIngo Molnar .cls = &lapic_sysclass, 2195f62bae50SIngo Molnar }; 2196f62bae50SIngo Molnar 2197f62bae50SIngo Molnar static void __cpuinit apic_pm_activate(void) 2198f62bae50SIngo Molnar { 2199f62bae50SIngo Molnar apic_pm_state.active = 1; 2200f62bae50SIngo Molnar } 2201f62bae50SIngo Molnar 2202f62bae50SIngo Molnar static int __init init_lapic_sysfs(void) 2203f62bae50SIngo Molnar { 2204f62bae50SIngo Molnar int error; 2205f62bae50SIngo Molnar 2206f62bae50SIngo Molnar if (!cpu_has_apic) 2207f62bae50SIngo Molnar return 0; 2208f62bae50SIngo Molnar /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2209f62bae50SIngo Molnar 2210f62bae50SIngo Molnar error = sysdev_class_register(&lapic_sysclass); 2211f62bae50SIngo Molnar if (!error) 2212f62bae50SIngo Molnar error = sysdev_register(&device_lapic); 2213f62bae50SIngo Molnar return error; 2214f62bae50SIngo Molnar } 2215b24696bcSFenghua Yu 2216b24696bcSFenghua Yu /* local apic needs to resume before other devices access its registers. */ 2217b24696bcSFenghua Yu core_initcall(init_lapic_sysfs); 2218f62bae50SIngo Molnar 2219f62bae50SIngo Molnar #else /* CONFIG_PM */ 2220f62bae50SIngo Molnar 2221f62bae50SIngo Molnar static void apic_pm_activate(void) { } 2222f62bae50SIngo Molnar 2223f62bae50SIngo Molnar #endif /* CONFIG_PM */ 2224f62bae50SIngo Molnar 2225f62bae50SIngo Molnar #ifdef CONFIG_X86_64 2226e0e42142SYinghai Lu 2227e0e42142SYinghai Lu static int __cpuinit apic_cluster_num(void) 2228f62bae50SIngo Molnar { 2229f62bae50SIngo Molnar int i, clusters, zeros; 2230f62bae50SIngo Molnar unsigned id; 2231f62bae50SIngo Molnar u16 *bios_cpu_apicid; 2232f62bae50SIngo Molnar DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); 2233f62bae50SIngo Molnar 2234f62bae50SIngo Molnar bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); 2235f62bae50SIngo Molnar bitmap_zero(clustermap, NUM_APIC_CLUSTERS); 2236f62bae50SIngo Molnar 2237f62bae50SIngo Molnar for (i = 0; i < nr_cpu_ids; i++) { 2238f62bae50SIngo Molnar /* are we being called early in kernel startup? */ 2239f62bae50SIngo Molnar if (bios_cpu_apicid) { 2240f62bae50SIngo Molnar id = bios_cpu_apicid[i]; 2241f62bae50SIngo Molnar } else if (i < nr_cpu_ids) { 2242f62bae50SIngo Molnar if (cpu_present(i)) 2243f62bae50SIngo Molnar id = per_cpu(x86_bios_cpu_apicid, i); 2244f62bae50SIngo Molnar else 2245f62bae50SIngo Molnar continue; 2246f62bae50SIngo Molnar } else 2247f62bae50SIngo Molnar break; 2248f62bae50SIngo Molnar 2249f62bae50SIngo Molnar if (id != BAD_APICID) 2250f62bae50SIngo Molnar __set_bit(APIC_CLUSTERID(id), clustermap); 2251f62bae50SIngo Molnar } 2252f62bae50SIngo Molnar 2253f62bae50SIngo Molnar /* Problem: Partially populated chassis may not have CPUs in some of 2254f62bae50SIngo Molnar * the APIC clusters they have been allocated. Only present CPUs have 2255f62bae50SIngo Molnar * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. 2256f62bae50SIngo Molnar * Since clusters are allocated sequentially, count zeros only if 2257f62bae50SIngo Molnar * they are bounded by ones. 2258f62bae50SIngo Molnar */ 2259f62bae50SIngo Molnar clusters = 0; 2260f62bae50SIngo Molnar zeros = 0; 2261f62bae50SIngo Molnar for (i = 0; i < NUM_APIC_CLUSTERS; i++) { 2262f62bae50SIngo Molnar if (test_bit(i, clustermap)) { 2263f62bae50SIngo Molnar clusters += 1 + zeros; 2264f62bae50SIngo Molnar zeros = 0; 2265f62bae50SIngo Molnar } else 2266f62bae50SIngo Molnar ++zeros; 2267f62bae50SIngo Molnar } 2268f62bae50SIngo Molnar 2269e0e42142SYinghai Lu return clusters; 2270e0e42142SYinghai Lu } 2271e0e42142SYinghai Lu 2272e0e42142SYinghai Lu static int __cpuinitdata multi_checked; 2273e0e42142SYinghai Lu static int __cpuinitdata multi; 2274e0e42142SYinghai Lu 2275e0e42142SYinghai Lu static int __cpuinit set_multi(const struct dmi_system_id *d) 2276e0e42142SYinghai Lu { 2277e0e42142SYinghai Lu if (multi) 2278e0e42142SYinghai Lu return 0; 22796f0aced6SCyrill Gorcunov pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2280e0e42142SYinghai Lu multi = 1; 2281e0e42142SYinghai Lu return 0; 2282e0e42142SYinghai Lu } 2283e0e42142SYinghai Lu 2284e0e42142SYinghai Lu static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = { 2285e0e42142SYinghai Lu { 2286e0e42142SYinghai Lu .callback = set_multi, 2287e0e42142SYinghai Lu .ident = "IBM System Summit2", 2288e0e42142SYinghai Lu .matches = { 2289e0e42142SYinghai Lu DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2290e0e42142SYinghai Lu DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2291e0e42142SYinghai Lu }, 2292e0e42142SYinghai Lu }, 2293e0e42142SYinghai Lu {} 2294e0e42142SYinghai Lu }; 2295e0e42142SYinghai Lu 2296e0e42142SYinghai Lu static void __cpuinit dmi_check_multi(void) 2297e0e42142SYinghai Lu { 2298e0e42142SYinghai Lu if (multi_checked) 2299e0e42142SYinghai Lu return; 2300e0e42142SYinghai Lu 2301e0e42142SYinghai Lu dmi_check_system(multi_dmi_table); 2302e0e42142SYinghai Lu multi_checked = 1; 2303e0e42142SYinghai Lu } 2304f62bae50SIngo Molnar 2305f62bae50SIngo Molnar /* 2306e0e42142SYinghai Lu * apic_is_clustered_box() -- Check if we can expect good TSC 2307e0e42142SYinghai Lu * 2308e0e42142SYinghai Lu * Thus far, the major user of this is IBM's Summit2 series: 2309e0e42142SYinghai Lu * Clustered boxes may have unsynced TSC problems if they are 2310e0e42142SYinghai Lu * multi-chassis. 2311e0e42142SYinghai Lu * Use DMI to check them 2312f62bae50SIngo Molnar */ 2313e0e42142SYinghai Lu __cpuinit int apic_is_clustered_box(void) 2314e0e42142SYinghai Lu { 2315e0e42142SYinghai Lu dmi_check_multi(); 2316e0e42142SYinghai Lu if (multi) 2317e0e42142SYinghai Lu return 1; 2318e0e42142SYinghai Lu 2319e0e42142SYinghai Lu if (!is_vsmp_box()) 2320e0e42142SYinghai Lu return 0; 2321e0e42142SYinghai Lu 2322e0e42142SYinghai Lu /* 2323e0e42142SYinghai Lu * ScaleMP vSMPowered boxes have one cluster per board and TSCs are 2324e0e42142SYinghai Lu * not guaranteed to be synced between boards 2325e0e42142SYinghai Lu */ 2326e0e42142SYinghai Lu if (apic_cluster_num() > 1) 2327e0e42142SYinghai Lu return 1; 2328e0e42142SYinghai Lu 2329e0e42142SYinghai Lu return 0; 2330f62bae50SIngo Molnar } 2331f62bae50SIngo Molnar #endif 2332f62bae50SIngo Molnar 2333f62bae50SIngo Molnar /* 2334f62bae50SIngo Molnar * APIC command line parameters 2335f62bae50SIngo Molnar */ 2336f62bae50SIngo Molnar static int __init setup_disableapic(char *arg) 2337f62bae50SIngo Molnar { 2338f62bae50SIngo Molnar disable_apic = 1; 2339f62bae50SIngo Molnar setup_clear_cpu_cap(X86_FEATURE_APIC); 2340f62bae50SIngo Molnar return 0; 2341f62bae50SIngo Molnar } 2342f62bae50SIngo Molnar early_param("disableapic", setup_disableapic); 2343f62bae50SIngo Molnar 2344f62bae50SIngo Molnar /* same as disableapic, for compatibility */ 2345f62bae50SIngo Molnar static int __init setup_nolapic(char *arg) 2346f62bae50SIngo Molnar { 2347f62bae50SIngo Molnar return setup_disableapic(arg); 2348f62bae50SIngo Molnar } 2349f62bae50SIngo Molnar early_param("nolapic", setup_nolapic); 2350f62bae50SIngo Molnar 2351f62bae50SIngo Molnar static int __init parse_lapic_timer_c2_ok(char *arg) 2352f62bae50SIngo Molnar { 2353f62bae50SIngo Molnar local_apic_timer_c2_ok = 1; 2354f62bae50SIngo Molnar return 0; 2355f62bae50SIngo Molnar } 2356f62bae50SIngo Molnar early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2357f62bae50SIngo Molnar 2358f62bae50SIngo Molnar static int __init parse_disable_apic_timer(char *arg) 2359f62bae50SIngo Molnar { 2360f62bae50SIngo Molnar disable_apic_timer = 1; 2361f62bae50SIngo Molnar return 0; 2362f62bae50SIngo Molnar } 2363f62bae50SIngo Molnar early_param("noapictimer", parse_disable_apic_timer); 2364f62bae50SIngo Molnar 2365f62bae50SIngo Molnar static int __init parse_nolapic_timer(char *arg) 2366f62bae50SIngo Molnar { 2367f62bae50SIngo Molnar disable_apic_timer = 1; 2368f62bae50SIngo Molnar return 0; 2369f62bae50SIngo Molnar } 2370f62bae50SIngo Molnar early_param("nolapic_timer", parse_nolapic_timer); 2371f62bae50SIngo Molnar 2372f62bae50SIngo Molnar static int __init apic_set_verbosity(char *arg) 2373f62bae50SIngo Molnar { 2374f62bae50SIngo Molnar if (!arg) { 2375f62bae50SIngo Molnar #ifdef CONFIG_X86_64 2376f62bae50SIngo Molnar skip_ioapic_setup = 0; 2377f62bae50SIngo Molnar return 0; 2378f62bae50SIngo Molnar #endif 2379f62bae50SIngo Molnar return -EINVAL; 2380f62bae50SIngo Molnar } 2381f62bae50SIngo Molnar 2382f62bae50SIngo Molnar if (strcmp("debug", arg) == 0) 2383f62bae50SIngo Molnar apic_verbosity = APIC_DEBUG; 2384f62bae50SIngo Molnar else if (strcmp("verbose", arg) == 0) 2385f62bae50SIngo Molnar apic_verbosity = APIC_VERBOSE; 2386f62bae50SIngo Molnar else { 2387f62bae50SIngo Molnar pr_warning("APIC Verbosity level %s not recognised" 2388f62bae50SIngo Molnar " use apic=verbose or apic=debug\n", arg); 2389f62bae50SIngo Molnar return -EINVAL; 2390f62bae50SIngo Molnar } 2391f62bae50SIngo Molnar 2392f62bae50SIngo Molnar return 0; 2393f62bae50SIngo Molnar } 2394f62bae50SIngo Molnar early_param("apic", apic_set_verbosity); 2395f62bae50SIngo Molnar 2396f62bae50SIngo Molnar static int __init lapic_insert_resource(void) 2397f62bae50SIngo Molnar { 2398f62bae50SIngo Molnar if (!apic_phys) 2399f62bae50SIngo Molnar return -1; 2400f62bae50SIngo Molnar 2401f62bae50SIngo Molnar /* Put local APIC into the resource map. */ 2402f62bae50SIngo Molnar lapic_resource.start = apic_phys; 2403f62bae50SIngo Molnar lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2404f62bae50SIngo Molnar insert_resource(&iomem_resource, &lapic_resource); 2405f62bae50SIngo Molnar 2406f62bae50SIngo Molnar return 0; 2407f62bae50SIngo Molnar } 2408f62bae50SIngo Molnar 2409f62bae50SIngo Molnar /* 2410f62bae50SIngo Molnar * need call insert after e820_reserve_resources() 2411f62bae50SIngo Molnar * that is using request_resource 2412f62bae50SIngo Molnar */ 2413f62bae50SIngo Molnar late_initcall(lapic_insert_resource); 2414