1f62bae50SIngo Molnar /* 2f62bae50SIngo Molnar * Local APIC handling, local APIC timers 3f62bae50SIngo Molnar * 4f62bae50SIngo Molnar * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 5f62bae50SIngo Molnar * 6f62bae50SIngo Molnar * Fixes 7f62bae50SIngo Molnar * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8f62bae50SIngo Molnar * thanks to Eric Gilmore 9f62bae50SIngo Molnar * and Rolf G. Tews 10f62bae50SIngo Molnar * for testing these extensively. 11f62bae50SIngo Molnar * Maciej W. Rozycki : Various updates and fixes. 12f62bae50SIngo Molnar * Mikael Pettersson : Power Management for UP-APIC. 13f62bae50SIngo Molnar * Pavel Machek and 14f62bae50SIngo Molnar * Mikael Pettersson : PM converted to driver model. 15f62bae50SIngo Molnar */ 16f62bae50SIngo Molnar 17cdd6c482SIngo Molnar #include <linux/perf_event.h> 18f62bae50SIngo Molnar #include <linux/kernel_stat.h> 19f62bae50SIngo Molnar #include <linux/mc146818rtc.h> 20f62bae50SIngo Molnar #include <linux/acpi_pmtmr.h> 21f62bae50SIngo Molnar #include <linux/clockchips.h> 22f62bae50SIngo Molnar #include <linux/interrupt.h> 23f62bae50SIngo Molnar #include <linux/bootmem.h> 24f62bae50SIngo Molnar #include <linux/ftrace.h> 25f62bae50SIngo Molnar #include <linux/ioport.h> 26186f4360SPaul Gortmaker #include <linux/export.h> 27f3c6ea1bSRafael J. Wysocki #include <linux/syscore_ops.h> 28f62bae50SIngo Molnar #include <linux/delay.h> 29f62bae50SIngo Molnar #include <linux/timex.h> 30334955efSRalf Baechle #include <linux/i8253.h> 31f62bae50SIngo Molnar #include <linux/dmar.h> 32f62bae50SIngo Molnar #include <linux/init.h> 33f62bae50SIngo Molnar #include <linux/cpu.h> 34f62bae50SIngo Molnar #include <linux/dmi.h> 35f62bae50SIngo Molnar #include <linux/smp.h> 36f62bae50SIngo Molnar #include <linux/mm.h> 37f62bae50SIngo Molnar 3883ab8514SSteven Rostedt (Red Hat) #include <asm/trace/irq_vectors.h> 398a8f422dSSuresh Siddha #include <asm/irq_remapping.h> 40cdd6c482SIngo Molnar #include <asm/perf_event.h> 41736decacSThomas Gleixner #include <asm/x86_init.h> 42f62bae50SIngo Molnar #include <asm/pgalloc.h> 4360063497SArun Sharma #include <linux/atomic.h> 44f62bae50SIngo Molnar #include <asm/mpspec.h> 45f62bae50SIngo Molnar #include <asm/i8259.h> 46f62bae50SIngo Molnar #include <asm/proto.h> 47f62bae50SIngo Molnar #include <asm/apic.h> 487167d08eSHenrik Kretzschmar #include <asm/io_apic.h> 49f62bae50SIngo Molnar #include <asm/desc.h> 50f62bae50SIngo Molnar #include <asm/hpet.h> 51f62bae50SIngo Molnar #include <asm/mtrr.h> 5216f871bcSRalf Baechle #include <asm/time.h> 53f62bae50SIngo Molnar #include <asm/smp.h> 54638bee71SH. Peter Anvin #include <asm/mce.h> 558c3ba8d0SKerstin Jonsson #include <asm/tsc.h> 562904ed8dSSheng Yang #include <asm/hypervisor.h> 57bd9240a1SPeter Zijlstra #include <asm/cpu_device_id.h> 58bd9240a1SPeter Zijlstra #include <asm/intel-family.h> 59f62bae50SIngo Molnar 60f62bae50SIngo Molnar unsigned int num_processors; 61f62bae50SIngo Molnar 62148f9bb8SPaul Gortmaker unsigned disabled_cpus; 63f62bae50SIngo Molnar 64f62bae50SIngo Molnar /* Processor that is doing the boot up */ 65f62bae50SIngo Molnar unsigned int boot_cpu_physical_apicid = -1U; 66cc08e04cSDavid Rientjes EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); 67f62bae50SIngo Molnar 68cff9ab2bSDenys Vlasenko u8 boot_cpu_apic_version; 69cff9ab2bSDenys Vlasenko 70f62bae50SIngo Molnar /* 71f62bae50SIngo Molnar * The highest APIC ID seen during enumeration. 72f62bae50SIngo Molnar */ 73a491cc90SJiang Liu static unsigned int max_physical_apicid; 74f62bae50SIngo Molnar 75f62bae50SIngo Molnar /* 76f62bae50SIngo Molnar * Bitmask of physically existing CPUs: 77f62bae50SIngo Molnar */ 78f62bae50SIngo Molnar physid_mask_t phys_cpu_present_map; 79f62bae50SIngo Molnar 80f62bae50SIngo Molnar /* 81151e0c7dSHATAYAMA Daisuke * Processor to be disabled specified by kernel parameter 82151e0c7dSHATAYAMA Daisuke * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to 83151e0c7dSHATAYAMA Daisuke * avoid undefined behaviour caused by sending INIT from AP to BSP. 84151e0c7dSHATAYAMA Daisuke */ 855b4d1dbcSH. Peter Anvin static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID; 86151e0c7dSHATAYAMA Daisuke 87151e0c7dSHATAYAMA Daisuke /* 88b7c4948eSHidehiro Kawai * This variable controls which CPUs receive external NMIs. By default, 89b7c4948eSHidehiro Kawai * external NMIs are delivered only to the BSP. 90b7c4948eSHidehiro Kawai */ 91b7c4948eSHidehiro Kawai static int apic_extnmi = APIC_EXTNMI_BSP; 92b7c4948eSHidehiro Kawai 93b7c4948eSHidehiro Kawai /* 94f62bae50SIngo Molnar * Map cpu index to physical APIC ID 95f62bae50SIngo Molnar */ 960816b0f0SVlad Zolotarov DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); 970816b0f0SVlad Zolotarov DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); 983e9e57faSVitaly Kuznetsov DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX); 99f62bae50SIngo Molnar EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 100f62bae50SIngo Molnar EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 1013e9e57faSVitaly Kuznetsov EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); 102f62bae50SIngo Molnar 103f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1044c321ff8STejun Heo 1054c321ff8STejun Heo /* 1064c321ff8STejun Heo * On x86_32, the mapping between cpu and logical apicid may vary 1074c321ff8STejun Heo * depending on apic in use. The following early percpu variable is 1084c321ff8STejun Heo * used for the mapping. This is where the behaviors of x86_64 and 32 1094c321ff8STejun Heo * actually diverge. Let's keep it ugly for now. 1104c321ff8STejun Heo */ 1110816b0f0SVlad Zolotarov DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); 1124c321ff8STejun Heo 113f62bae50SIngo Molnar /* Local APIC was disabled by the BIOS and enabled by the kernel */ 114f62bae50SIngo Molnar static int enabled_via_apicbase; 115f62bae50SIngo Molnar 116c0eaa453SCyrill Gorcunov /* 117c0eaa453SCyrill Gorcunov * Handle interrupt mode configuration register (IMCR). 118c0eaa453SCyrill Gorcunov * This register controls whether the interrupt signals 119c0eaa453SCyrill Gorcunov * that reach the BSP come from the master PIC or from the 120c0eaa453SCyrill Gorcunov * local APIC. Before entering Symmetric I/O Mode, either 121c0eaa453SCyrill Gorcunov * the BIOS or the operating system must switch out of 122c0eaa453SCyrill Gorcunov * PIC Mode by changing the IMCR. 123c0eaa453SCyrill Gorcunov */ 1245cda395fSAlexander van Heukelum static inline void imcr_pic_to_apic(void) 125c0eaa453SCyrill Gorcunov { 126c0eaa453SCyrill Gorcunov /* select IMCR register */ 127c0eaa453SCyrill Gorcunov outb(0x70, 0x22); 128c0eaa453SCyrill Gorcunov /* NMI and 8259 INTR go through APIC */ 129c0eaa453SCyrill Gorcunov outb(0x01, 0x23); 130c0eaa453SCyrill Gorcunov } 131c0eaa453SCyrill Gorcunov 1325cda395fSAlexander van Heukelum static inline void imcr_apic_to_pic(void) 133c0eaa453SCyrill Gorcunov { 134c0eaa453SCyrill Gorcunov /* select IMCR register */ 135c0eaa453SCyrill Gorcunov outb(0x70, 0x22); 136c0eaa453SCyrill Gorcunov /* NMI and 8259 INTR go directly to BSP */ 137c0eaa453SCyrill Gorcunov outb(0x00, 0x23); 138c0eaa453SCyrill Gorcunov } 139f62bae50SIngo Molnar #endif 140f62bae50SIngo Molnar 141279f1461SSuresh Siddha /* 142279f1461SSuresh Siddha * Knob to control our willingness to enable the local APIC. 143279f1461SSuresh Siddha * 144279f1461SSuresh Siddha * +1=force-enable 145279f1461SSuresh Siddha */ 146279f1461SSuresh Siddha static int force_enable_local_apic __initdata; 147dc9788f4SDavid Rientjes 148279f1461SSuresh Siddha /* 149279f1461SSuresh Siddha * APIC command line parameters 150279f1461SSuresh Siddha */ 151279f1461SSuresh Siddha static int __init parse_lapic(char *arg) 152279f1461SSuresh Siddha { 15397f2645fSMasahiro Yamada if (IS_ENABLED(CONFIG_X86_32) && !arg) 154279f1461SSuresh Siddha force_enable_local_apic = 1; 15527cf9298SMathias Krause else if (arg && !strncmp(arg, "notscdeadline", 13)) 156279f1461SSuresh Siddha setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 157279f1461SSuresh Siddha return 0; 158279f1461SSuresh Siddha } 159279f1461SSuresh Siddha early_param("lapic", parse_lapic); 160279f1461SSuresh Siddha 161f62bae50SIngo Molnar #ifdef CONFIG_X86_64 162f62bae50SIngo Molnar static int apic_calibrate_pmtmr __initdata; 163f62bae50SIngo Molnar static __init int setup_apicpmtimer(char *s) 164f62bae50SIngo Molnar { 165f62bae50SIngo Molnar apic_calibrate_pmtmr = 1; 166f62bae50SIngo Molnar notsc_setup(NULL); 167f62bae50SIngo Molnar return 0; 168f62bae50SIngo Molnar } 169f62bae50SIngo Molnar __setup("apicpmtimer", setup_apicpmtimer); 170f62bae50SIngo Molnar #endif 171f62bae50SIngo Molnar 172f62bae50SIngo Molnar unsigned long mp_lapic_addr; 173f62bae50SIngo Molnar int disable_apic; 174f62bae50SIngo Molnar /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 17525874a29SHenrik Kretzschmar static int disable_apic_timer __initdata; 176f62bae50SIngo Molnar /* Local APIC timer works in C2 */ 177f62bae50SIngo Molnar int local_apic_timer_c2_ok; 178f62bae50SIngo Molnar EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 179f62bae50SIngo Molnar 180f62bae50SIngo Molnar /* 181f62bae50SIngo Molnar * Debug level, exported for io_apic.c 182f62bae50SIngo Molnar */ 183f62bae50SIngo Molnar unsigned int apic_verbosity; 184f62bae50SIngo Molnar 185f62bae50SIngo Molnar int pic_mode; 186f62bae50SIngo Molnar 187f62bae50SIngo Molnar /* Have we found an MP table */ 188f62bae50SIngo Molnar int smp_found_config; 189f62bae50SIngo Molnar 190f62bae50SIngo Molnar static struct resource lapic_resource = { 191f62bae50SIngo Molnar .name = "Local APIC", 192f62bae50SIngo Molnar .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 193f62bae50SIngo Molnar }; 194f62bae50SIngo Molnar 1951ade93efSJacob Pan unsigned int lapic_timer_frequency = 0; 196f62bae50SIngo Molnar 197f62bae50SIngo Molnar static void apic_pm_activate(void); 198f62bae50SIngo Molnar 199f62bae50SIngo Molnar static unsigned long apic_phys; 200f62bae50SIngo Molnar 201f62bae50SIngo Molnar /* 202f62bae50SIngo Molnar * Get the LAPIC version 203f62bae50SIngo Molnar */ 204f62bae50SIngo Molnar static inline int lapic_get_version(void) 205f62bae50SIngo Molnar { 206f62bae50SIngo Molnar return GET_APIC_VERSION(apic_read(APIC_LVR)); 207f62bae50SIngo Molnar } 208f62bae50SIngo Molnar 209f62bae50SIngo Molnar /* 210f62bae50SIngo Molnar * Check, if the APIC is integrated or a separate chip 211f62bae50SIngo Molnar */ 212f62bae50SIngo Molnar static inline int lapic_is_integrated(void) 213f62bae50SIngo Molnar { 214f62bae50SIngo Molnar #ifdef CONFIG_X86_64 215f62bae50SIngo Molnar return 1; 216f62bae50SIngo Molnar #else 217f62bae50SIngo Molnar return APIC_INTEGRATED(lapic_get_version()); 218f62bae50SIngo Molnar #endif 219f62bae50SIngo Molnar } 220f62bae50SIngo Molnar 221f62bae50SIngo Molnar /* 222f62bae50SIngo Molnar * Check, whether this is a modern or a first generation APIC 223f62bae50SIngo Molnar */ 224f62bae50SIngo Molnar static int modern_apic(void) 225f62bae50SIngo Molnar { 226f62bae50SIngo Molnar /* AMD systems use old APIC versions, so check the CPU */ 227f62bae50SIngo Molnar if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 228f62bae50SIngo Molnar boot_cpu_data.x86 >= 0xf) 229f62bae50SIngo Molnar return 1; 230f62bae50SIngo Molnar return lapic_get_version() >= 0x14; 231f62bae50SIngo Molnar } 232f62bae50SIngo Molnar 23308306ce6SCyrill Gorcunov /* 234a933c618SCyrill Gorcunov * right after this call apic become NOOP driven 235a933c618SCyrill Gorcunov * so apic->write/read doesn't do anything 23608306ce6SCyrill Gorcunov */ 23725874a29SHenrik Kretzschmar static void __init apic_disable(void) 23808306ce6SCyrill Gorcunov { 239f88f2b4fSCyrill Gorcunov pr_info("APIC: switched to apic NOOP\n"); 240a933c618SCyrill Gorcunov apic = &apic_noop; 24108306ce6SCyrill Gorcunov } 24208306ce6SCyrill Gorcunov 243f62bae50SIngo Molnar void native_apic_wait_icr_idle(void) 244f62bae50SIngo Molnar { 245f62bae50SIngo Molnar while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 246f62bae50SIngo Molnar cpu_relax(); 247f62bae50SIngo Molnar } 248f62bae50SIngo Molnar 249f62bae50SIngo Molnar u32 native_safe_apic_wait_icr_idle(void) 250f62bae50SIngo Molnar { 251f62bae50SIngo Molnar u32 send_status; 252f62bae50SIngo Molnar int timeout; 253f62bae50SIngo Molnar 254f62bae50SIngo Molnar timeout = 0; 255f62bae50SIngo Molnar do { 256f62bae50SIngo Molnar send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 257f62bae50SIngo Molnar if (!send_status) 258f62bae50SIngo Molnar break; 259b49d7d87SFernando Luis Vazquez Cao inc_irq_stat(icr_read_retry_count); 260f62bae50SIngo Molnar udelay(100); 261f62bae50SIngo Molnar } while (timeout++ < 1000); 262f62bae50SIngo Molnar 263f62bae50SIngo Molnar return send_status; 264f62bae50SIngo Molnar } 265f62bae50SIngo Molnar 266f62bae50SIngo Molnar void native_apic_icr_write(u32 low, u32 id) 267f62bae50SIngo Molnar { 268ea7bdc65SJan Kiszka unsigned long flags; 269ea7bdc65SJan Kiszka 270ea7bdc65SJan Kiszka local_irq_save(flags); 271f62bae50SIngo Molnar apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 272f62bae50SIngo Molnar apic_write(APIC_ICR, low); 273ea7bdc65SJan Kiszka local_irq_restore(flags); 274f62bae50SIngo Molnar } 275f62bae50SIngo Molnar 276f62bae50SIngo Molnar u64 native_apic_icr_read(void) 277f62bae50SIngo Molnar { 278f62bae50SIngo Molnar u32 icr1, icr2; 279f62bae50SIngo Molnar 280f62bae50SIngo Molnar icr2 = apic_read(APIC_ICR2); 281f62bae50SIngo Molnar icr1 = apic_read(APIC_ICR); 282f62bae50SIngo Molnar 283f62bae50SIngo Molnar return icr1 | ((u64)icr2 << 32); 284f62bae50SIngo Molnar } 285f62bae50SIngo Molnar 286f62bae50SIngo Molnar #ifdef CONFIG_X86_32 287f62bae50SIngo Molnar /** 288f62bae50SIngo Molnar * get_physical_broadcast - Get number of physical broadcast IDs 289f62bae50SIngo Molnar */ 290f62bae50SIngo Molnar int get_physical_broadcast(void) 291f62bae50SIngo Molnar { 292f62bae50SIngo Molnar return modern_apic() ? 0xff : 0xf; 293f62bae50SIngo Molnar } 294f62bae50SIngo Molnar #endif 295f62bae50SIngo Molnar 296f62bae50SIngo Molnar /** 297f62bae50SIngo Molnar * lapic_get_maxlvt - get the maximum number of local vector table entries 298f62bae50SIngo Molnar */ 299f62bae50SIngo Molnar int lapic_get_maxlvt(void) 300f62bae50SIngo Molnar { 301f62bae50SIngo Molnar unsigned int v; 302f62bae50SIngo Molnar 303f62bae50SIngo Molnar v = apic_read(APIC_LVR); 304f62bae50SIngo Molnar /* 305f62bae50SIngo Molnar * - we always have APIC integrated on 64bit mode 306f62bae50SIngo Molnar * - 82489DXs do not report # of LVT entries 307f62bae50SIngo Molnar */ 308f62bae50SIngo Molnar return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; 309f62bae50SIngo Molnar } 310f62bae50SIngo Molnar 311f62bae50SIngo Molnar /* 312f62bae50SIngo Molnar * Local APIC timer 313f62bae50SIngo Molnar */ 314f62bae50SIngo Molnar 315f62bae50SIngo Molnar /* Clock divisor */ 316f62bae50SIngo Molnar #define APIC_DIVISOR 16 3171a9e4c56SNicolai Stange #define TSC_DIVISOR 8 318f62bae50SIngo Molnar 319f62bae50SIngo Molnar /* 320f62bae50SIngo Molnar * This function sets up the local APIC timer, with a timeout of 321f62bae50SIngo Molnar * 'clocks' APIC bus clock. During calibration we actually call 322f62bae50SIngo Molnar * this function twice on the boot CPU, once with a bogus timeout 323f62bae50SIngo Molnar * value, second time for real. The other (noncalibrating) CPUs 324f62bae50SIngo Molnar * call this function only once, with the real, calibrated value. 325f62bae50SIngo Molnar * 326f62bae50SIngo Molnar * We do reads before writes even if unnecessary, to get around the 327f62bae50SIngo Molnar * P5 APIC double write bug. 328f62bae50SIngo Molnar */ 329f62bae50SIngo Molnar static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 330f62bae50SIngo Molnar { 331f62bae50SIngo Molnar unsigned int lvtt_value, tmp_value; 332f62bae50SIngo Molnar 333f62bae50SIngo Molnar lvtt_value = LOCAL_TIMER_VECTOR; 334f62bae50SIngo Molnar if (!oneshot) 335f62bae50SIngo Molnar lvtt_value |= APIC_LVT_TIMER_PERIODIC; 336279f1461SSuresh Siddha else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 337279f1461SSuresh Siddha lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; 338279f1461SSuresh Siddha 339f62bae50SIngo Molnar if (!lapic_is_integrated()) 340f62bae50SIngo Molnar lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 341f62bae50SIngo Molnar 342f62bae50SIngo Molnar if (!irqen) 343f62bae50SIngo Molnar lvtt_value |= APIC_LVT_MASKED; 344f62bae50SIngo Molnar 345f62bae50SIngo Molnar apic_write(APIC_LVTT, lvtt_value); 346f62bae50SIngo Molnar 347279f1461SSuresh Siddha if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { 3485d7c631dSShaohua Li /* 3495d7c631dSShaohua Li * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, 3505d7c631dSShaohua Li * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. 3515d7c631dSShaohua Li * According to Intel, MFENCE can do the serialization here. 3525d7c631dSShaohua Li */ 3535d7c631dSShaohua Li asm volatile("mfence" : : : "memory"); 3545d7c631dSShaohua Li 355279f1461SSuresh Siddha printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); 356279f1461SSuresh Siddha return; 357279f1461SSuresh Siddha } 358279f1461SSuresh Siddha 359f62bae50SIngo Molnar /* 360f62bae50SIngo Molnar * Divide PICLK by 16 361f62bae50SIngo Molnar */ 362f62bae50SIngo Molnar tmp_value = apic_read(APIC_TDCR); 363f62bae50SIngo Molnar apic_write(APIC_TDCR, 364f62bae50SIngo Molnar (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 365f62bae50SIngo Molnar APIC_TDR_DIV_16); 366f62bae50SIngo Molnar 367f62bae50SIngo Molnar if (!oneshot) 368f62bae50SIngo Molnar apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 369f62bae50SIngo Molnar } 370f62bae50SIngo Molnar 371f62bae50SIngo Molnar /* 372a68c439bSRobert Richter * Setup extended LVT, AMD specific 373f62bae50SIngo Molnar * 374a68c439bSRobert Richter * Software should use the LVT offsets the BIOS provides. The offsets 375a68c439bSRobert Richter * are determined by the subsystems using it like those for MCE 376a68c439bSRobert Richter * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 377a68c439bSRobert Richter * are supported. Beginning with family 10h at least 4 offsets are 378a68c439bSRobert Richter * available. 379f62bae50SIngo Molnar * 380a68c439bSRobert Richter * Since the offsets must be consistent for all cores, we keep track 381a68c439bSRobert Richter * of the LVT offsets in software and reserve the offset for the same 382a68c439bSRobert Richter * vector also to be used on other cores. An offset is freed by 383a68c439bSRobert Richter * setting the entry to APIC_EILVT_MASKED. 384a68c439bSRobert Richter * 385a68c439bSRobert Richter * If the BIOS is right, there should be no conflicts. Otherwise a 386a68c439bSRobert Richter * "[Firmware Bug]: ..." error message is generated. However, if 387a68c439bSRobert Richter * software does not properly determines the offsets, it is not 388a68c439bSRobert Richter * necessarily a BIOS bug. 389f62bae50SIngo Molnar */ 390f62bae50SIngo Molnar 391a68c439bSRobert Richter static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 392f62bae50SIngo Molnar 393a68c439bSRobert Richter static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 394a68c439bSRobert Richter { 395a68c439bSRobert Richter return (old & APIC_EILVT_MASKED) 396a68c439bSRobert Richter || (new == APIC_EILVT_MASKED) 397a68c439bSRobert Richter || ((new & ~APIC_EILVT_MASKED) == old); 398a68c439bSRobert Richter } 399a68c439bSRobert Richter 400a68c439bSRobert Richter static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 401a68c439bSRobert Richter { 4028abc3122SRobert Richter unsigned int rsvd, vector; 403a68c439bSRobert Richter 404a68c439bSRobert Richter if (offset >= APIC_EILVT_NR_MAX) 405a68c439bSRobert Richter return ~0; 406a68c439bSRobert Richter 4078abc3122SRobert Richter rsvd = atomic_read(&eilvt_offsets[offset]); 408a68c439bSRobert Richter do { 4098abc3122SRobert Richter vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ 4108abc3122SRobert Richter if (vector && !eilvt_entry_is_changeable(vector, new)) 411a68c439bSRobert Richter /* may not change if vectors are different */ 412a68c439bSRobert Richter return rsvd; 413a68c439bSRobert Richter rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 414a68c439bSRobert Richter } while (rsvd != new); 415a68c439bSRobert Richter 4168abc3122SRobert Richter rsvd &= ~APIC_EILVT_MASKED; 4178abc3122SRobert Richter if (rsvd && rsvd != vector) 4188abc3122SRobert Richter pr_info("LVT offset %d assigned for vector 0x%02x\n", 4198abc3122SRobert Richter offset, rsvd); 4208abc3122SRobert Richter 421a68c439bSRobert Richter return new; 422a68c439bSRobert Richter } 423a68c439bSRobert Richter 424a68c439bSRobert Richter /* 425a68c439bSRobert Richter * If mask=1, the LVT entry does not generate interrupts while mask=0 426cbf74ceaSRobert Richter * enables the vector. See also the BKDGs. Must be called with 427cbf74ceaSRobert Richter * preemption disabled. 428a68c439bSRobert Richter */ 429a68c439bSRobert Richter 43027afdf20SRobert Richter int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 431a68c439bSRobert Richter { 432a68c439bSRobert Richter unsigned long reg = APIC_EILVTn(offset); 433a68c439bSRobert Richter unsigned int new, old, reserved; 434a68c439bSRobert Richter 435a68c439bSRobert Richter new = (mask << 16) | (msg_type << 8) | vector; 436a68c439bSRobert Richter old = apic_read(reg); 437a68c439bSRobert Richter reserved = reserve_eilvt_offset(offset, new); 438a68c439bSRobert Richter 439a68c439bSRobert Richter if (reserved != new) { 440eb48c9cbSRobert Richter pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 441eb48c9cbSRobert Richter "vector 0x%x, but the register is already in use for " 442eb48c9cbSRobert Richter "vector 0x%x on another cpu\n", 443eb48c9cbSRobert Richter smp_processor_id(), reg, offset, new, reserved); 444a68c439bSRobert Richter return -EINVAL; 445a68c439bSRobert Richter } 446a68c439bSRobert Richter 447a68c439bSRobert Richter if (!eilvt_entry_is_changeable(old, new)) { 448eb48c9cbSRobert Richter pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 449eb48c9cbSRobert Richter "vector 0x%x, but the register is already in use for " 450eb48c9cbSRobert Richter "vector 0x%x on this cpu\n", 451eb48c9cbSRobert Richter smp_processor_id(), reg, offset, new, old); 452a68c439bSRobert Richter return -EBUSY; 453a68c439bSRobert Richter } 454a68c439bSRobert Richter 455a68c439bSRobert Richter apic_write(reg, new); 456a68c439bSRobert Richter 457a68c439bSRobert Richter return 0; 458f62bae50SIngo Molnar } 45927afdf20SRobert Richter EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 460f62bae50SIngo Molnar 461f62bae50SIngo Molnar /* 462f62bae50SIngo Molnar * Program the next event, relative to now 463f62bae50SIngo Molnar */ 464f62bae50SIngo Molnar static int lapic_next_event(unsigned long delta, 465f62bae50SIngo Molnar struct clock_event_device *evt) 466f62bae50SIngo Molnar { 467f62bae50SIngo Molnar apic_write(APIC_TMICT, delta); 468f62bae50SIngo Molnar return 0; 469f62bae50SIngo Molnar } 470f62bae50SIngo Molnar 471279f1461SSuresh Siddha static int lapic_next_deadline(unsigned long delta, 472279f1461SSuresh Siddha struct clock_event_device *evt) 473279f1461SSuresh Siddha { 474279f1461SSuresh Siddha u64 tsc; 475279f1461SSuresh Siddha 4764ea1636bSAndy Lutomirski tsc = rdtsc(); 477279f1461SSuresh Siddha wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); 478279f1461SSuresh Siddha return 0; 479279f1461SSuresh Siddha } 480279f1461SSuresh Siddha 481b23d8e52SViresh Kumar static int lapic_timer_shutdown(struct clock_event_device *evt) 482f62bae50SIngo Molnar { 483f62bae50SIngo Molnar unsigned int v; 484f62bae50SIngo Molnar 485f62bae50SIngo Molnar /* Lapic used as dummy for broadcast ? */ 486f62bae50SIngo Molnar if (evt->features & CLOCK_EVT_FEAT_DUMMY) 487b23d8e52SViresh Kumar return 0; 488f62bae50SIngo Molnar 489f62bae50SIngo Molnar v = apic_read(APIC_LVTT); 490f62bae50SIngo Molnar v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 491f62bae50SIngo Molnar apic_write(APIC_LVTT, v); 4926f9b4100SAndreas Herrmann apic_write(APIC_TMICT, 0); 493b23d8e52SViresh Kumar return 0; 494f62bae50SIngo Molnar } 495f62bae50SIngo Molnar 496b23d8e52SViresh Kumar static inline int 497b23d8e52SViresh Kumar lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot) 498b23d8e52SViresh Kumar { 499b23d8e52SViresh Kumar /* Lapic used as dummy for broadcast ? */ 500b23d8e52SViresh Kumar if (evt->features & CLOCK_EVT_FEAT_DUMMY) 501b23d8e52SViresh Kumar return 0; 502b23d8e52SViresh Kumar 503b23d8e52SViresh Kumar __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1); 504b23d8e52SViresh Kumar return 0; 505b23d8e52SViresh Kumar } 506b23d8e52SViresh Kumar 507b23d8e52SViresh Kumar static int lapic_timer_set_periodic(struct clock_event_device *evt) 508b23d8e52SViresh Kumar { 509b23d8e52SViresh Kumar return lapic_timer_set_periodic_oneshot(evt, false); 510b23d8e52SViresh Kumar } 511b23d8e52SViresh Kumar 512b23d8e52SViresh Kumar static int lapic_timer_set_oneshot(struct clock_event_device *evt) 513b23d8e52SViresh Kumar { 514b23d8e52SViresh Kumar return lapic_timer_set_periodic_oneshot(evt, true); 515f62bae50SIngo Molnar } 516f62bae50SIngo Molnar 517f62bae50SIngo Molnar /* 518f62bae50SIngo Molnar * Local APIC timer broadcast function 519f62bae50SIngo Molnar */ 520f62bae50SIngo Molnar static void lapic_timer_broadcast(const struct cpumask *mask) 521f62bae50SIngo Molnar { 522f62bae50SIngo Molnar #ifdef CONFIG_SMP 523f62bae50SIngo Molnar apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 524f62bae50SIngo Molnar #endif 525f62bae50SIngo Molnar } 526f62bae50SIngo Molnar 52725874a29SHenrik Kretzschmar 52825874a29SHenrik Kretzschmar /* 52925874a29SHenrik Kretzschmar * The local apic timer can be used for any function which is CPU local. 53025874a29SHenrik Kretzschmar */ 53125874a29SHenrik Kretzschmar static struct clock_event_device lapic_clockevent = { 53225874a29SHenrik Kretzschmar .name = "lapic", 533b23d8e52SViresh Kumar .features = CLOCK_EVT_FEAT_PERIODIC | 534b23d8e52SViresh Kumar CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP 535b23d8e52SViresh Kumar | CLOCK_EVT_FEAT_DUMMY, 53625874a29SHenrik Kretzschmar .shift = 32, 537b23d8e52SViresh Kumar .set_state_shutdown = lapic_timer_shutdown, 538b23d8e52SViresh Kumar .set_state_periodic = lapic_timer_set_periodic, 539b23d8e52SViresh Kumar .set_state_oneshot = lapic_timer_set_oneshot, 540914122c3SFrederic Weisbecker .set_state_oneshot_stopped = lapic_timer_shutdown, 54125874a29SHenrik Kretzschmar .set_next_event = lapic_next_event, 54225874a29SHenrik Kretzschmar .broadcast = lapic_timer_broadcast, 54325874a29SHenrik Kretzschmar .rating = 100, 54425874a29SHenrik Kretzschmar .irq = -1, 54525874a29SHenrik Kretzschmar }; 54625874a29SHenrik Kretzschmar static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 54725874a29SHenrik Kretzschmar 548bd9240a1SPeter Zijlstra #define DEADLINE_MODEL_MATCH_FUNC(model, func) \ 549bd9240a1SPeter Zijlstra { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&func } 550bd9240a1SPeter Zijlstra 551bd9240a1SPeter Zijlstra #define DEADLINE_MODEL_MATCH_REV(model, rev) \ 552bd9240a1SPeter Zijlstra { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)rev } 553bd9240a1SPeter Zijlstra 554bd9240a1SPeter Zijlstra static u32 hsx_deadline_rev(void) 555bd9240a1SPeter Zijlstra { 556bd9240a1SPeter Zijlstra switch (boot_cpu_data.x86_mask) { 557bd9240a1SPeter Zijlstra case 0x02: return 0x3a; /* EP */ 558bd9240a1SPeter Zijlstra case 0x04: return 0x0f; /* EX */ 559bd9240a1SPeter Zijlstra } 560bd9240a1SPeter Zijlstra 561bd9240a1SPeter Zijlstra return ~0U; 562bd9240a1SPeter Zijlstra } 563bd9240a1SPeter Zijlstra 564bd9240a1SPeter Zijlstra static u32 bdx_deadline_rev(void) 565bd9240a1SPeter Zijlstra { 566bd9240a1SPeter Zijlstra switch (boot_cpu_data.x86_mask) { 567bd9240a1SPeter Zijlstra case 0x02: return 0x00000011; 568bd9240a1SPeter Zijlstra case 0x03: return 0x0700000e; 569bd9240a1SPeter Zijlstra case 0x04: return 0x0f00000c; 570bd9240a1SPeter Zijlstra case 0x05: return 0x0e000003; 571bd9240a1SPeter Zijlstra } 572bd9240a1SPeter Zijlstra 573bd9240a1SPeter Zijlstra return ~0U; 574bd9240a1SPeter Zijlstra } 575bd9240a1SPeter Zijlstra 576bd9240a1SPeter Zijlstra static const struct x86_cpu_id deadline_match[] = { 577bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X, hsx_deadline_rev), 578bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X, 0x0b000020), 579bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_XEON_D, bdx_deadline_rev), 580bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_X, 0x02000014), 581bd9240a1SPeter Zijlstra 582bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_CORE, 0x22), 583bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_ULT, 0x20), 584bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_GT3E, 0x17), 585bd9240a1SPeter Zijlstra 586bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_CORE, 0x25), 587bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_GT3E, 0x17), 588bd9240a1SPeter Zijlstra 589bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE, 0xb2), 590bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP, 0xb2), 591bd9240a1SPeter Zijlstra 592bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE, 0x52), 593bd9240a1SPeter Zijlstra DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP, 0x52), 594bd9240a1SPeter Zijlstra 595bd9240a1SPeter Zijlstra {}, 596bd9240a1SPeter Zijlstra }; 597bd9240a1SPeter Zijlstra 598bd9240a1SPeter Zijlstra static void apic_check_deadline_errata(void) 599bd9240a1SPeter Zijlstra { 600594a30fbSHans de Goede const struct x86_cpu_id *m; 601bd9240a1SPeter Zijlstra u32 rev; 602bd9240a1SPeter Zijlstra 603594a30fbSHans de Goede if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 604594a30fbSHans de Goede return; 605594a30fbSHans de Goede 606594a30fbSHans de Goede m = x86_match_cpu(deadline_match); 607bd9240a1SPeter Zijlstra if (!m) 608bd9240a1SPeter Zijlstra return; 609bd9240a1SPeter Zijlstra 610bd9240a1SPeter Zijlstra /* 611bd9240a1SPeter Zijlstra * Function pointers will have the MSB set due to address layout, 612bd9240a1SPeter Zijlstra * immediate revisions will not. 613bd9240a1SPeter Zijlstra */ 614bd9240a1SPeter Zijlstra if ((long)m->driver_data < 0) 615bd9240a1SPeter Zijlstra rev = ((u32 (*)(void))(m->driver_data))(); 616bd9240a1SPeter Zijlstra else 617bd9240a1SPeter Zijlstra rev = (u32)m->driver_data; 618bd9240a1SPeter Zijlstra 619bd9240a1SPeter Zijlstra if (boot_cpu_data.microcode >= rev) 620bd9240a1SPeter Zijlstra return; 621bd9240a1SPeter Zijlstra 622bd9240a1SPeter Zijlstra setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 623bd9240a1SPeter Zijlstra pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; " 624bd9240a1SPeter Zijlstra "please update microcode to version: 0x%x (or later)\n", rev); 625bd9240a1SPeter Zijlstra } 626bd9240a1SPeter Zijlstra 627f62bae50SIngo Molnar /* 628421f91d2SUwe Kleine-König * Setup the local APIC timer for this CPU. Copy the initialized values 629f62bae50SIngo Molnar * of the boot CPU and register the clock event in the framework. 630f62bae50SIngo Molnar */ 631148f9bb8SPaul Gortmaker static void setup_APIC_timer(void) 632f62bae50SIngo Molnar { 63389cbc767SChristoph Lameter struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 634f62bae50SIngo Molnar 635349c004eSChristoph Lameter if (this_cpu_has(X86_FEATURE_ARAT)) { 636db954b58SVenkatesh Pallipadi lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 637db954b58SVenkatesh Pallipadi /* Make LAPIC timer preferrable over percpu HPET */ 638db954b58SVenkatesh Pallipadi lapic_clockevent.rating = 150; 639db954b58SVenkatesh Pallipadi } 640db954b58SVenkatesh Pallipadi 641f62bae50SIngo Molnar memcpy(levt, &lapic_clockevent, sizeof(*levt)); 642f62bae50SIngo Molnar levt->cpumask = cpumask_of(smp_processor_id()); 643f62bae50SIngo Molnar 644279f1461SSuresh Siddha if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 645c6e9f42bSPeter Zijlstra levt->name = "lapic-deadline"; 646279f1461SSuresh Siddha levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | 647279f1461SSuresh Siddha CLOCK_EVT_FEAT_DUMMY); 648279f1461SSuresh Siddha levt->set_next_event = lapic_next_deadline; 649279f1461SSuresh Siddha clockevents_config_and_register(levt, 6501a9e4c56SNicolai Stange tsc_khz * (1000 / TSC_DIVISOR), 651279f1461SSuresh Siddha 0xF, ~0UL); 652279f1461SSuresh Siddha } else 653f62bae50SIngo Molnar clockevents_register_device(levt); 654f62bae50SIngo Molnar } 655f62bae50SIngo Molnar 656f62bae50SIngo Molnar /* 6576731b0d6SNicolai Stange * Install the updated TSC frequency from recalibration at the TSC 6586731b0d6SNicolai Stange * deadline clockevent devices. 6596731b0d6SNicolai Stange */ 6606731b0d6SNicolai Stange static void __lapic_update_tsc_freq(void *info) 6616731b0d6SNicolai Stange { 6626731b0d6SNicolai Stange struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 6636731b0d6SNicolai Stange 6646731b0d6SNicolai Stange if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 6656731b0d6SNicolai Stange return; 6666731b0d6SNicolai Stange 6676731b0d6SNicolai Stange clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR)); 6686731b0d6SNicolai Stange } 6696731b0d6SNicolai Stange 6706731b0d6SNicolai Stange void lapic_update_tsc_freq(void) 6716731b0d6SNicolai Stange { 6726731b0d6SNicolai Stange /* 6736731b0d6SNicolai Stange * The clockevent device's ->mult and ->shift can both be 6746731b0d6SNicolai Stange * changed. In order to avoid races, schedule the frequency 6756731b0d6SNicolai Stange * update code on each CPU. 6766731b0d6SNicolai Stange */ 6776731b0d6SNicolai Stange on_each_cpu(__lapic_update_tsc_freq, NULL, 0); 6786731b0d6SNicolai Stange } 6796731b0d6SNicolai Stange 6806731b0d6SNicolai Stange /* 681f62bae50SIngo Molnar * In this functions we calibrate APIC bus clocks to the external timer. 682f62bae50SIngo Molnar * 683f62bae50SIngo Molnar * We want to do the calibration only once since we want to have local timer 684f62bae50SIngo Molnar * irqs syncron. CPUs connected by the same APIC bus have the very same bus 685f62bae50SIngo Molnar * frequency. 686f62bae50SIngo Molnar * 687f62bae50SIngo Molnar * This was previously done by reading the PIT/HPET and waiting for a wrap 688f62bae50SIngo Molnar * around to find out, that a tick has elapsed. I have a box, where the PIT 689f62bae50SIngo Molnar * readout is broken, so it never gets out of the wait loop again. This was 690f62bae50SIngo Molnar * also reported by others. 691f62bae50SIngo Molnar * 692f62bae50SIngo Molnar * Monitoring the jiffies value is inaccurate and the clockevents 693f62bae50SIngo Molnar * infrastructure allows us to do a simple substitution of the interrupt 694f62bae50SIngo Molnar * handler. 695f62bae50SIngo Molnar * 696f62bae50SIngo Molnar * The calibration routine also uses the pm_timer when possible, as the PIT 697f62bae50SIngo Molnar * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 698f62bae50SIngo Molnar * back to normal later in the boot process). 699f62bae50SIngo Molnar */ 700f62bae50SIngo Molnar 701f62bae50SIngo Molnar #define LAPIC_CAL_LOOPS (HZ/10) 702f62bae50SIngo Molnar 703f62bae50SIngo Molnar static __initdata int lapic_cal_loops = -1; 704f62bae50SIngo Molnar static __initdata long lapic_cal_t1, lapic_cal_t2; 705f62bae50SIngo Molnar static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 706f62bae50SIngo Molnar static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 707f62bae50SIngo Molnar static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 708f62bae50SIngo Molnar 709f62bae50SIngo Molnar /* 710f62bae50SIngo Molnar * Temporary interrupt handler. 711f62bae50SIngo Molnar */ 712f62bae50SIngo Molnar static void __init lapic_cal_handler(struct clock_event_device *dev) 713f62bae50SIngo Molnar { 714f62bae50SIngo Molnar unsigned long long tsc = 0; 715f62bae50SIngo Molnar long tapic = apic_read(APIC_TMCCT); 716f62bae50SIngo Molnar unsigned long pm = acpi_pm_read_early(); 717f62bae50SIngo Molnar 71859e21e3dSBorislav Petkov if (boot_cpu_has(X86_FEATURE_TSC)) 7194ea1636bSAndy Lutomirski tsc = rdtsc(); 720f62bae50SIngo Molnar 721f62bae50SIngo Molnar switch (lapic_cal_loops++) { 722f62bae50SIngo Molnar case 0: 723f62bae50SIngo Molnar lapic_cal_t1 = tapic; 724f62bae50SIngo Molnar lapic_cal_tsc1 = tsc; 725f62bae50SIngo Molnar lapic_cal_pm1 = pm; 726f62bae50SIngo Molnar lapic_cal_j1 = jiffies; 727f62bae50SIngo Molnar break; 728f62bae50SIngo Molnar 729f62bae50SIngo Molnar case LAPIC_CAL_LOOPS: 730f62bae50SIngo Molnar lapic_cal_t2 = tapic; 731f62bae50SIngo Molnar lapic_cal_tsc2 = tsc; 732f62bae50SIngo Molnar if (pm < lapic_cal_pm1) 733f62bae50SIngo Molnar pm += ACPI_PM_OVRRUN; 734f62bae50SIngo Molnar lapic_cal_pm2 = pm; 735f62bae50SIngo Molnar lapic_cal_j2 = jiffies; 736f62bae50SIngo Molnar break; 737f62bae50SIngo Molnar } 738f62bae50SIngo Molnar } 739f62bae50SIngo Molnar 740f62bae50SIngo Molnar static int __init 741f62bae50SIngo Molnar calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 742f62bae50SIngo Molnar { 743f62bae50SIngo Molnar const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 744f62bae50SIngo Molnar const long pm_thresh = pm_100ms / 100; 745f62bae50SIngo Molnar unsigned long mult; 746f62bae50SIngo Molnar u64 res; 747f62bae50SIngo Molnar 748f62bae50SIngo Molnar #ifndef CONFIG_X86_PM_TIMER 749f62bae50SIngo Molnar return -1; 750f62bae50SIngo Molnar #endif 751f62bae50SIngo Molnar 752f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 753f62bae50SIngo Molnar 754f62bae50SIngo Molnar /* Check, if the PM timer is available */ 755f62bae50SIngo Molnar if (!deltapm) 756f62bae50SIngo Molnar return -1; 757f62bae50SIngo Molnar 758f62bae50SIngo Molnar mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 759f62bae50SIngo Molnar 760f62bae50SIngo Molnar if (deltapm > (pm_100ms - pm_thresh) && 761f62bae50SIngo Molnar deltapm < (pm_100ms + pm_thresh)) { 762f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 763f62bae50SIngo Molnar return 0; 764f62bae50SIngo Molnar } 765f62bae50SIngo Molnar 766f62bae50SIngo Molnar res = (((u64)deltapm) * mult) >> 22; 767f62bae50SIngo Molnar do_div(res, 1000000); 768f62bae50SIngo Molnar pr_warning("APIC calibration not consistent " 769f62bae50SIngo Molnar "with PM-Timer: %ldms instead of 100ms\n",(long)res); 770f62bae50SIngo Molnar 771f62bae50SIngo Molnar /* Correct the lapic counter value */ 772f62bae50SIngo Molnar res = (((u64)(*delta)) * pm_100ms); 773f62bae50SIngo Molnar do_div(res, deltapm); 774f62bae50SIngo Molnar pr_info("APIC delta adjusted to PM-Timer: " 775f62bae50SIngo Molnar "%lu (%ld)\n", (unsigned long)res, *delta); 776f62bae50SIngo Molnar *delta = (long)res; 777f62bae50SIngo Molnar 778f62bae50SIngo Molnar /* Correct the tsc counter value */ 77959e21e3dSBorislav Petkov if (boot_cpu_has(X86_FEATURE_TSC)) { 780f62bae50SIngo Molnar res = (((u64)(*deltatsc)) * pm_100ms); 781f62bae50SIngo Molnar do_div(res, deltapm); 782f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 783f62bae50SIngo Molnar "PM-Timer: %lu (%ld)\n", 784f62bae50SIngo Molnar (unsigned long)res, *deltatsc); 785f62bae50SIngo Molnar *deltatsc = (long)res; 786f62bae50SIngo Molnar } 787f62bae50SIngo Molnar 788f62bae50SIngo Molnar return 0; 789f62bae50SIngo Molnar } 790f62bae50SIngo Molnar 791f62bae50SIngo Molnar static int __init calibrate_APIC_clock(void) 792f62bae50SIngo Molnar { 79389cbc767SChristoph Lameter struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 794f62bae50SIngo Molnar void (*real_handler)(struct clock_event_device *dev); 795f62bae50SIngo Molnar unsigned long deltaj; 796f62bae50SIngo Molnar long delta, deltatsc; 797f62bae50SIngo Molnar int pm_referenced = 0; 798f62bae50SIngo Molnar 7991ade93efSJacob Pan /** 8001ade93efSJacob Pan * check if lapic timer has already been calibrated by platform 8011ade93efSJacob Pan * specific routine, such as tsc calibration code. if so, we just fill 8021ade93efSJacob Pan * in the clockevent structure and return. 8031ade93efSJacob Pan */ 8041ade93efSJacob Pan 805279f1461SSuresh Siddha if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 806279f1461SSuresh Siddha return 0; 807279f1461SSuresh Siddha } else if (lapic_timer_frequency) { 8081ade93efSJacob Pan apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", 8091ade93efSJacob Pan lapic_timer_frequency); 8101ade93efSJacob Pan lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR, 8111ade93efSJacob Pan TICK_NSEC, lapic_clockevent.shift); 8121ade93efSJacob Pan lapic_clockevent.max_delta_ns = 8131ade93efSJacob Pan clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); 814747d04b3SNicolai Stange lapic_clockevent.max_delta_ticks = 0x7FFFFF; 8151ade93efSJacob Pan lapic_clockevent.min_delta_ns = 8161ade93efSJacob Pan clockevent_delta2ns(0xF, &lapic_clockevent); 817747d04b3SNicolai Stange lapic_clockevent.min_delta_ticks = 0xF; 8181ade93efSJacob Pan lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 8191ade93efSJacob Pan return 0; 8201ade93efSJacob Pan } 8211ade93efSJacob Pan 822279f1461SSuresh Siddha apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 823279f1461SSuresh Siddha "calibrating APIC timer ...\n"); 824279f1461SSuresh Siddha 825f62bae50SIngo Molnar local_irq_disable(); 826f62bae50SIngo Molnar 827f62bae50SIngo Molnar /* Replace the global interrupt handler */ 828f62bae50SIngo Molnar real_handler = global_clock_event->event_handler; 829f62bae50SIngo Molnar global_clock_event->event_handler = lapic_cal_handler; 830f62bae50SIngo Molnar 831f62bae50SIngo Molnar /* 832f62bae50SIngo Molnar * Setup the APIC counter to maximum. There is no way the lapic 833f62bae50SIngo Molnar * can underflow in the 100ms detection time frame 834f62bae50SIngo Molnar */ 835f62bae50SIngo Molnar __setup_APIC_LVTT(0xffffffff, 0, 0); 836f62bae50SIngo Molnar 837f62bae50SIngo Molnar /* Let the interrupts run */ 838f62bae50SIngo Molnar local_irq_enable(); 839f62bae50SIngo Molnar 840f62bae50SIngo Molnar while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 841f62bae50SIngo Molnar cpu_relax(); 842f62bae50SIngo Molnar 843f62bae50SIngo Molnar local_irq_disable(); 844f62bae50SIngo Molnar 845f62bae50SIngo Molnar /* Restore the real event handler */ 846f62bae50SIngo Molnar global_clock_event->event_handler = real_handler; 847f62bae50SIngo Molnar 848f62bae50SIngo Molnar /* Build delta t1-t2 as apic timer counts down */ 849f62bae50SIngo Molnar delta = lapic_cal_t1 - lapic_cal_t2; 850f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 851f62bae50SIngo Molnar 852f62bae50SIngo Molnar deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 853f62bae50SIngo Molnar 854f62bae50SIngo Molnar /* we trust the PM based calibration if possible */ 855f62bae50SIngo Molnar pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 856f62bae50SIngo Molnar &delta, &deltatsc); 857f62bae50SIngo Molnar 858f62bae50SIngo Molnar /* Calculate the scaled math multiplication factor */ 859f62bae50SIngo Molnar lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 860f62bae50SIngo Molnar lapic_clockevent.shift); 861f62bae50SIngo Molnar lapic_clockevent.max_delta_ns = 8624aed89d6SPierre Tardy clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 863747d04b3SNicolai Stange lapic_clockevent.max_delta_ticks = 0x7FFFFFFF; 864f62bae50SIngo Molnar lapic_clockevent.min_delta_ns = 865f62bae50SIngo Molnar clockevent_delta2ns(0xF, &lapic_clockevent); 866747d04b3SNicolai Stange lapic_clockevent.min_delta_ticks = 0xF; 867f62bae50SIngo Molnar 8681ade93efSJacob Pan lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 869f62bae50SIngo Molnar 870f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 871411462f6SThomas Gleixner apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 872f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 8731ade93efSJacob Pan lapic_timer_frequency); 874f62bae50SIngo Molnar 87559e21e3dSBorislav Petkov if (boot_cpu_has(X86_FEATURE_TSC)) { 876f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 877f62bae50SIngo Molnar "%ld.%04ld MHz.\n", 878f62bae50SIngo Molnar (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 879f62bae50SIngo Molnar (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 880f62bae50SIngo Molnar } 881f62bae50SIngo Molnar 882f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 883f62bae50SIngo Molnar "%u.%04u MHz.\n", 8841ade93efSJacob Pan lapic_timer_frequency / (1000000 / HZ), 8851ade93efSJacob Pan lapic_timer_frequency % (1000000 / HZ)); 886f62bae50SIngo Molnar 887f62bae50SIngo Molnar /* 888f62bae50SIngo Molnar * Do a sanity check on the APIC calibration result 889f62bae50SIngo Molnar */ 8901ade93efSJacob Pan if (lapic_timer_frequency < (1000000 / HZ)) { 891f62bae50SIngo Molnar local_irq_enable(); 892f62bae50SIngo Molnar pr_warning("APIC frequency too slow, disabling apic timer\n"); 893f62bae50SIngo Molnar return -1; 894f62bae50SIngo Molnar } 895f62bae50SIngo Molnar 896f62bae50SIngo Molnar levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 897f62bae50SIngo Molnar 898f62bae50SIngo Molnar /* 899f62bae50SIngo Molnar * PM timer calibration failed or not turned on 900f62bae50SIngo Molnar * so lets try APIC timer based calibration 901f62bae50SIngo Molnar */ 902f62bae50SIngo Molnar if (!pm_referenced) { 903f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 904f62bae50SIngo Molnar 905f62bae50SIngo Molnar /* 906f62bae50SIngo Molnar * Setup the apic timer manually 907f62bae50SIngo Molnar */ 908f62bae50SIngo Molnar levt->event_handler = lapic_cal_handler; 909b23d8e52SViresh Kumar lapic_timer_set_periodic(levt); 910f62bae50SIngo Molnar lapic_cal_loops = -1; 911f62bae50SIngo Molnar 912f62bae50SIngo Molnar /* Let the interrupts run */ 913f62bae50SIngo Molnar local_irq_enable(); 914f62bae50SIngo Molnar 915f62bae50SIngo Molnar while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 916f62bae50SIngo Molnar cpu_relax(); 917f62bae50SIngo Molnar 918f62bae50SIngo Molnar /* Stop the lapic timer */ 919c948c260SThomas Gleixner local_irq_disable(); 920b23d8e52SViresh Kumar lapic_timer_shutdown(levt); 921f62bae50SIngo Molnar 922f62bae50SIngo Molnar /* Jiffies delta */ 923f62bae50SIngo Molnar deltaj = lapic_cal_j2 - lapic_cal_j1; 924f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 925f62bae50SIngo Molnar 926f62bae50SIngo Molnar /* Check, if the jiffies result is consistent */ 927f62bae50SIngo Molnar if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 928f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 929f62bae50SIngo Molnar else 930f62bae50SIngo Molnar levt->features |= CLOCK_EVT_FEAT_DUMMY; 931c948c260SThomas Gleixner } 932f62bae50SIngo Molnar local_irq_enable(); 933f62bae50SIngo Molnar 934f62bae50SIngo Molnar if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 935f62bae50SIngo Molnar pr_warning("APIC timer disabled due to verification failure\n"); 936f62bae50SIngo Molnar return -1; 937f62bae50SIngo Molnar } 938f62bae50SIngo Molnar 939f62bae50SIngo Molnar return 0; 940f62bae50SIngo Molnar } 941f62bae50SIngo Molnar 942f62bae50SIngo Molnar /* 943f62bae50SIngo Molnar * Setup the boot APIC 944f62bae50SIngo Molnar * 945f62bae50SIngo Molnar * Calibrate and verify the result. 946f62bae50SIngo Molnar */ 947f62bae50SIngo Molnar void __init setup_boot_APIC_clock(void) 948f62bae50SIngo Molnar { 949f62bae50SIngo Molnar /* 950f62bae50SIngo Molnar * The local apic timer can be disabled via the kernel 951f62bae50SIngo Molnar * commandline or from the CPU detection code. Register the lapic 952f62bae50SIngo Molnar * timer as a dummy clock event source on SMP systems, so the 953f62bae50SIngo Molnar * broadcast mechanism is used. On UP systems simply ignore it. 954f62bae50SIngo Molnar */ 955f62bae50SIngo Molnar if (disable_apic_timer) { 956f62bae50SIngo Molnar pr_info("Disabling APIC timer\n"); 957f62bae50SIngo Molnar /* No broadcast on UP ! */ 958f62bae50SIngo Molnar if (num_possible_cpus() > 1) { 959f62bae50SIngo Molnar lapic_clockevent.mult = 1; 960f62bae50SIngo Molnar setup_APIC_timer(); 961f62bae50SIngo Molnar } 962f62bae50SIngo Molnar return; 963f62bae50SIngo Molnar } 964f62bae50SIngo Molnar 965f62bae50SIngo Molnar if (calibrate_APIC_clock()) { 966f62bae50SIngo Molnar /* No broadcast on UP ! */ 967f62bae50SIngo Molnar if (num_possible_cpus() > 1) 968f62bae50SIngo Molnar setup_APIC_timer(); 969f62bae50SIngo Molnar return; 970f62bae50SIngo Molnar } 971f62bae50SIngo Molnar 972f62bae50SIngo Molnar /* 973f62bae50SIngo Molnar * If nmi_watchdog is set to IO_APIC, we need the 974f62bae50SIngo Molnar * PIT/HPET going. Otherwise register lapic as a dummy 975f62bae50SIngo Molnar * device. 976f62bae50SIngo Molnar */ 977f62bae50SIngo Molnar lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 978f62bae50SIngo Molnar 979f62bae50SIngo Molnar /* Setup the lapic or request the broadcast */ 980f62bae50SIngo Molnar setup_APIC_timer(); 98107c94a38SBorislav Petkov amd_e400_c1e_apic_setup(); 982f62bae50SIngo Molnar } 983f62bae50SIngo Molnar 984148f9bb8SPaul Gortmaker void setup_secondary_APIC_clock(void) 985f62bae50SIngo Molnar { 986f62bae50SIngo Molnar setup_APIC_timer(); 98707c94a38SBorislav Petkov amd_e400_c1e_apic_setup(); 988f62bae50SIngo Molnar } 989f62bae50SIngo Molnar 990f62bae50SIngo Molnar /* 991f62bae50SIngo Molnar * The guts of the apic timer interrupt 992f62bae50SIngo Molnar */ 993f62bae50SIngo Molnar static void local_apic_timer_interrupt(void) 994f62bae50SIngo Molnar { 9953bec6defSThomas Gleixner struct clock_event_device *evt = this_cpu_ptr(&lapic_events); 996f62bae50SIngo Molnar 997f62bae50SIngo Molnar /* 998f62bae50SIngo Molnar * Normally we should not be here till LAPIC has been initialized but 999f62bae50SIngo Molnar * in some cases like kdump, its possible that there is a pending LAPIC 1000f62bae50SIngo Molnar * timer interrupt from previous kernel's context and is delivered in 1001f62bae50SIngo Molnar * new kernel the moment interrupts are enabled. 1002f62bae50SIngo Molnar * 1003f62bae50SIngo Molnar * Interrupts are enabled early and LAPIC is setup much later, hence 1004f62bae50SIngo Molnar * its possible that when we get here evt->event_handler is NULL. 1005f62bae50SIngo Molnar * Check for event_handler being NULL and discard the interrupt as 1006f62bae50SIngo Molnar * spurious. 1007f62bae50SIngo Molnar */ 1008f62bae50SIngo Molnar if (!evt->event_handler) { 10093bec6defSThomas Gleixner pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", 10103bec6defSThomas Gleixner smp_processor_id()); 1011f62bae50SIngo Molnar /* Switch it off */ 1012b23d8e52SViresh Kumar lapic_timer_shutdown(evt); 1013f62bae50SIngo Molnar return; 1014f62bae50SIngo Molnar } 1015f62bae50SIngo Molnar 1016f62bae50SIngo Molnar /* 1017f62bae50SIngo Molnar * the NMI deadlock-detector uses this. 1018f62bae50SIngo Molnar */ 1019f62bae50SIngo Molnar inc_irq_stat(apic_timer_irqs); 1020f62bae50SIngo Molnar 1021f62bae50SIngo Molnar evt->event_handler(evt); 1022f62bae50SIngo Molnar } 1023f62bae50SIngo Molnar 1024f62bae50SIngo Molnar /* 1025f62bae50SIngo Molnar * Local APIC timer interrupt. This is the most natural way for doing 1026f62bae50SIngo Molnar * local interrupts, but local timer interrupts can be emulated by 1027f62bae50SIngo Molnar * broadcast interrupts too. [in case the hw doesn't support APIC timers] 1028f62bae50SIngo Molnar * 1029f62bae50SIngo Molnar * [ if a single-CPU system runs an SMP kernel then we call the local 1030f62bae50SIngo Molnar * interrupt as well. Thus we cannot inline the local irq ... ] 1031f62bae50SIngo Molnar */ 10321d9090e2SAndi Kleen __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 1033f62bae50SIngo Molnar { 1034f62bae50SIngo Molnar struct pt_regs *old_regs = set_irq_regs(regs); 1035f62bae50SIngo Molnar 1036f62bae50SIngo Molnar /* 1037f62bae50SIngo Molnar * NOTE! We'd better ACK the irq immediately, 1038f62bae50SIngo Molnar * because timer handling can be slow. 1039eddc0e92SSeiji Aguchi * 1040f62bae50SIngo Molnar * update_process_times() expects us to have done irq_enter(). 1041f62bae50SIngo Molnar * Besides, if we don't timer interrupts ignore the global 1042f62bae50SIngo Molnar * interrupt lock, which is the WrongThing (tm) to do. 1043f62bae50SIngo Molnar */ 1044eddc0e92SSeiji Aguchi entering_ack_irq(); 1045cf910e83SSeiji Aguchi trace_local_timer_entry(LOCAL_TIMER_VECTOR); 1046cf910e83SSeiji Aguchi local_apic_timer_interrupt(); 1047cf910e83SSeiji Aguchi trace_local_timer_exit(LOCAL_TIMER_VECTOR); 1048cf910e83SSeiji Aguchi exiting_irq(); 1049f62bae50SIngo Molnar 1050f62bae50SIngo Molnar set_irq_regs(old_regs); 1051f62bae50SIngo Molnar } 1052f62bae50SIngo Molnar 1053f62bae50SIngo Molnar int setup_profiling_timer(unsigned int multiplier) 1054f62bae50SIngo Molnar { 1055f62bae50SIngo Molnar return -EINVAL; 1056f62bae50SIngo Molnar } 1057f62bae50SIngo Molnar 1058f62bae50SIngo Molnar /* 1059f62bae50SIngo Molnar * Local APIC start and shutdown 1060f62bae50SIngo Molnar */ 1061f62bae50SIngo Molnar 1062f62bae50SIngo Molnar /** 1063f62bae50SIngo Molnar * clear_local_APIC - shutdown the local APIC 1064f62bae50SIngo Molnar * 1065f62bae50SIngo Molnar * This is called, when a CPU is disabled and before rebooting, so the state of 1066f62bae50SIngo Molnar * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 1067f62bae50SIngo Molnar * leftovers during boot. 1068f62bae50SIngo Molnar */ 1069f62bae50SIngo Molnar void clear_local_APIC(void) 1070f62bae50SIngo Molnar { 1071f62bae50SIngo Molnar int maxlvt; 1072f62bae50SIngo Molnar u32 v; 1073f62bae50SIngo Molnar 1074f62bae50SIngo Molnar /* APIC hasn't been mapped yet */ 1075fc1edaf9SSuresh Siddha if (!x2apic_mode && !apic_phys) 1076f62bae50SIngo Molnar return; 1077f62bae50SIngo Molnar 1078f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 1079f62bae50SIngo Molnar /* 1080f62bae50SIngo Molnar * Masking an LVT entry can trigger a local APIC error 1081f62bae50SIngo Molnar * if the vector is zero. Mask LVTERR first to prevent this. 1082f62bae50SIngo Molnar */ 1083f62bae50SIngo Molnar if (maxlvt >= 3) { 1084f62bae50SIngo Molnar v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 1085f62bae50SIngo Molnar apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 1086f62bae50SIngo Molnar } 1087f62bae50SIngo Molnar /* 1088f62bae50SIngo Molnar * Careful: we have to set masks only first to deassert 1089f62bae50SIngo Molnar * any level-triggered sources. 1090f62bae50SIngo Molnar */ 1091f62bae50SIngo Molnar v = apic_read(APIC_LVTT); 1092f62bae50SIngo Molnar apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 1093f62bae50SIngo Molnar v = apic_read(APIC_LVT0); 1094f62bae50SIngo Molnar apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 1095f62bae50SIngo Molnar v = apic_read(APIC_LVT1); 1096f62bae50SIngo Molnar apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 1097f62bae50SIngo Molnar if (maxlvt >= 4) { 1098f62bae50SIngo Molnar v = apic_read(APIC_LVTPC); 1099f62bae50SIngo Molnar apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 1100f62bae50SIngo Molnar } 1101f62bae50SIngo Molnar 1102f62bae50SIngo Molnar /* lets not touch this if we didn't frob it */ 11034efc0670SAndi Kleen #ifdef CONFIG_X86_THERMAL_VECTOR 1104f62bae50SIngo Molnar if (maxlvt >= 5) { 1105f62bae50SIngo Molnar v = apic_read(APIC_LVTTHMR); 1106f62bae50SIngo Molnar apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 1107f62bae50SIngo Molnar } 1108f62bae50SIngo Molnar #endif 1109638bee71SH. Peter Anvin #ifdef CONFIG_X86_MCE_INTEL 1110638bee71SH. Peter Anvin if (maxlvt >= 6) { 1111638bee71SH. Peter Anvin v = apic_read(APIC_LVTCMCI); 1112638bee71SH. Peter Anvin if (!(v & APIC_LVT_MASKED)) 1113638bee71SH. Peter Anvin apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 1114638bee71SH. Peter Anvin } 1115638bee71SH. Peter Anvin #endif 1116638bee71SH. Peter Anvin 1117f62bae50SIngo Molnar /* 1118f62bae50SIngo Molnar * Clean APIC state for other OSs: 1119f62bae50SIngo Molnar */ 1120f62bae50SIngo Molnar apic_write(APIC_LVTT, APIC_LVT_MASKED); 1121f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_LVT_MASKED); 1122f62bae50SIngo Molnar apic_write(APIC_LVT1, APIC_LVT_MASKED); 1123f62bae50SIngo Molnar if (maxlvt >= 3) 1124f62bae50SIngo Molnar apic_write(APIC_LVTERR, APIC_LVT_MASKED); 1125f62bae50SIngo Molnar if (maxlvt >= 4) 1126f62bae50SIngo Molnar apic_write(APIC_LVTPC, APIC_LVT_MASKED); 1127f62bae50SIngo Molnar 1128f62bae50SIngo Molnar /* Integrated APIC (!82489DX) ? */ 1129f62bae50SIngo Molnar if (lapic_is_integrated()) { 1130f62bae50SIngo Molnar if (maxlvt > 3) 1131f62bae50SIngo Molnar /* Clear ESR due to Pentium errata 3AP and 11AP */ 1132f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1133f62bae50SIngo Molnar apic_read(APIC_ESR); 1134f62bae50SIngo Molnar } 1135f62bae50SIngo Molnar } 1136f62bae50SIngo Molnar 1137f62bae50SIngo Molnar /** 1138f62bae50SIngo Molnar * disable_local_APIC - clear and disable the local APIC 1139f62bae50SIngo Molnar */ 1140f62bae50SIngo Molnar void disable_local_APIC(void) 1141f62bae50SIngo Molnar { 1142f62bae50SIngo Molnar unsigned int value; 1143f62bae50SIngo Molnar 1144f62bae50SIngo Molnar /* APIC hasn't been mapped yet */ 1145fd19dce7SYinghai Lu if (!x2apic_mode && !apic_phys) 1146f62bae50SIngo Molnar return; 1147f62bae50SIngo Molnar 1148f62bae50SIngo Molnar clear_local_APIC(); 1149f62bae50SIngo Molnar 1150f62bae50SIngo Molnar /* 1151f62bae50SIngo Molnar * Disable APIC (implies clearing of registers 1152f62bae50SIngo Molnar * for 82489DX!). 1153f62bae50SIngo Molnar */ 1154f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 1155f62bae50SIngo Molnar value &= ~APIC_SPIV_APIC_ENABLED; 1156f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 1157f62bae50SIngo Molnar 1158f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1159f62bae50SIngo Molnar /* 1160f62bae50SIngo Molnar * When LAPIC was disabled by the BIOS and enabled by the kernel, 1161f62bae50SIngo Molnar * restore the disabled state. 1162f62bae50SIngo Molnar */ 1163f62bae50SIngo Molnar if (enabled_via_apicbase) { 1164f62bae50SIngo Molnar unsigned int l, h; 1165f62bae50SIngo Molnar 1166f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, l, h); 1167f62bae50SIngo Molnar l &= ~MSR_IA32_APICBASE_ENABLE; 1168f62bae50SIngo Molnar wrmsr(MSR_IA32_APICBASE, l, h); 1169f62bae50SIngo Molnar } 1170f62bae50SIngo Molnar #endif 1171f62bae50SIngo Molnar } 1172f62bae50SIngo Molnar 1173f62bae50SIngo Molnar /* 1174f62bae50SIngo Molnar * If Linux enabled the LAPIC against the BIOS default disable it down before 1175f62bae50SIngo Molnar * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 1176f62bae50SIngo Molnar * not power-off. Additionally clear all LVT entries before disable_local_APIC 1177f62bae50SIngo Molnar * for the case where Linux didn't enable the LAPIC. 1178f62bae50SIngo Molnar */ 1179f62bae50SIngo Molnar void lapic_shutdown(void) 1180f62bae50SIngo Molnar { 1181f62bae50SIngo Molnar unsigned long flags; 1182f62bae50SIngo Molnar 118393984fbdSBorislav Petkov if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) 1184f62bae50SIngo Molnar return; 1185f62bae50SIngo Molnar 1186f62bae50SIngo Molnar local_irq_save(flags); 1187f62bae50SIngo Molnar 1188f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1189f62bae50SIngo Molnar if (!enabled_via_apicbase) 1190f62bae50SIngo Molnar clear_local_APIC(); 1191f62bae50SIngo Molnar else 1192f62bae50SIngo Molnar #endif 1193f62bae50SIngo Molnar disable_local_APIC(); 1194f62bae50SIngo Molnar 1195f62bae50SIngo Molnar 1196f62bae50SIngo Molnar local_irq_restore(flags); 1197f62bae50SIngo Molnar } 1198f62bae50SIngo Molnar 1199f62bae50SIngo Molnar /** 1200f62bae50SIngo Molnar * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1201f62bae50SIngo Molnar */ 1202f62bae50SIngo Molnar void __init sync_Arb_IDs(void) 1203f62bae50SIngo Molnar { 1204f62bae50SIngo Molnar /* 1205f62bae50SIngo Molnar * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1206f62bae50SIngo Molnar * needed on AMD. 1207f62bae50SIngo Molnar */ 1208f62bae50SIngo Molnar if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1209f62bae50SIngo Molnar return; 1210f62bae50SIngo Molnar 1211f62bae50SIngo Molnar /* 1212f62bae50SIngo Molnar * Wait for idle. 1213f62bae50SIngo Molnar */ 1214f62bae50SIngo Molnar apic_wait_icr_idle(); 1215f62bae50SIngo Molnar 1216f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1217f62bae50SIngo Molnar apic_write(APIC_ICR, APIC_DEST_ALLINC | 1218f62bae50SIngo Molnar APIC_INT_LEVELTRIG | APIC_DM_INIT); 1219f62bae50SIngo Molnar } 1220f62bae50SIngo Molnar 12210114a8e8SDou Liyang enum apic_intr_mode { 12220114a8e8SDou Liyang APIC_PIC, 12230114a8e8SDou Liyang APIC_VIRTUAL_WIRE, 12240114a8e8SDou Liyang APIC_SYMMETRIC_IO, 12250114a8e8SDou Liyang }; 12260114a8e8SDou Liyang 12270114a8e8SDou Liyang static int __init apic_intr_mode_select(void) 12280114a8e8SDou Liyang { 12290114a8e8SDou Liyang /* Check kernel option */ 12300114a8e8SDou Liyang if (disable_apic) { 12310114a8e8SDou Liyang pr_info("APIC disabled via kernel command line\n"); 12320114a8e8SDou Liyang return APIC_PIC; 12330114a8e8SDou Liyang } 12340114a8e8SDou Liyang 12350114a8e8SDou Liyang /* Check BIOS */ 12360114a8e8SDou Liyang #ifdef CONFIG_X86_64 12370114a8e8SDou Liyang /* On 64-bit, the APIC must be integrated, Check local APIC only */ 12380114a8e8SDou Liyang if (!boot_cpu_has(X86_FEATURE_APIC)) { 12390114a8e8SDou Liyang disable_apic = 1; 12400114a8e8SDou Liyang pr_info("APIC disabled by BIOS\n"); 12410114a8e8SDou Liyang return APIC_PIC; 12420114a8e8SDou Liyang } 12430114a8e8SDou Liyang #else 12440114a8e8SDou Liyang /* On 32-bit, the APIC may be integrated APIC or 82489DX */ 12450114a8e8SDou Liyang 12460114a8e8SDou Liyang /* Neither 82489DX nor integrated APIC ? */ 12470114a8e8SDou Liyang if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) { 12480114a8e8SDou Liyang disable_apic = 1; 12490114a8e8SDou Liyang return APIC_PIC; 12500114a8e8SDou Liyang } 12510114a8e8SDou Liyang 12520114a8e8SDou Liyang /* If the BIOS pretends there is an integrated APIC ? */ 12530114a8e8SDou Liyang if (!boot_cpu_has(X86_FEATURE_APIC) && 12540114a8e8SDou Liyang APIC_INTEGRATED(boot_cpu_apic_version)) { 12550114a8e8SDou Liyang disable_apic = 1; 12560114a8e8SDou Liyang pr_err(FW_BUG "Local APIC %d not detected, force emulation\n", 12570114a8e8SDou Liyang boot_cpu_physical_apicid); 12580114a8e8SDou Liyang return APIC_PIC; 12590114a8e8SDou Liyang } 12600114a8e8SDou Liyang #endif 12610114a8e8SDou Liyang 12620114a8e8SDou Liyang /* Check MP table or ACPI MADT configuration */ 12630114a8e8SDou Liyang if (!smp_found_config) { 12640114a8e8SDou Liyang disable_ioapic_support(); 12650114a8e8SDou Liyang if (!acpi_lapic) 12660114a8e8SDou Liyang pr_info("APIC: ACPI MADT or MP tables are not detected\n"); 12670114a8e8SDou Liyang return APIC_VIRTUAL_WIRE; 12680114a8e8SDou Liyang } 12690114a8e8SDou Liyang 12700114a8e8SDou Liyang return APIC_SYMMETRIC_IO; 12710114a8e8SDou Liyang } 12720114a8e8SDou Liyang 1273f62bae50SIngo Molnar /* 1274f62bae50SIngo Molnar * An initial setup of the virtual wire mode. 1275f62bae50SIngo Molnar */ 1276f62bae50SIngo Molnar void __init init_bsp_APIC(void) 1277f62bae50SIngo Molnar { 1278f62bae50SIngo Molnar unsigned int value; 1279f62bae50SIngo Molnar 1280f62bae50SIngo Molnar /* 1281f62bae50SIngo Molnar * Don't do the setup now if we have a SMP BIOS as the 1282f62bae50SIngo Molnar * through-I/O-APIC virtual wire mode might be active. 1283f62bae50SIngo Molnar */ 128493984fbdSBorislav Petkov if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC)) 1285f62bae50SIngo Molnar return; 1286f62bae50SIngo Molnar 1287f62bae50SIngo Molnar /* 1288f62bae50SIngo Molnar * Do not trust the local APIC being empty at bootup. 1289f62bae50SIngo Molnar */ 1290f62bae50SIngo Molnar clear_local_APIC(); 1291f62bae50SIngo Molnar 1292f62bae50SIngo Molnar /* 1293f62bae50SIngo Molnar * Enable APIC. 1294f62bae50SIngo Molnar */ 1295f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 1296f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 1297f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 1298f62bae50SIngo Molnar 1299f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1300f62bae50SIngo Molnar /* This bit is reserved on P4/Xeon and should be cleared */ 1301f62bae50SIngo Molnar if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1302f62bae50SIngo Molnar (boot_cpu_data.x86 == 15)) 1303f62bae50SIngo Molnar value &= ~APIC_SPIV_FOCUS_DISABLED; 1304f62bae50SIngo Molnar else 1305f62bae50SIngo Molnar #endif 1306f62bae50SIngo Molnar value |= APIC_SPIV_FOCUS_DISABLED; 1307f62bae50SIngo Molnar value |= SPURIOUS_APIC_VECTOR; 1308f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 1309f62bae50SIngo Molnar 1310f62bae50SIngo Molnar /* 1311f62bae50SIngo Molnar * Set up the virtual wire mode. 1312f62bae50SIngo Molnar */ 1313f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_DM_EXTINT); 1314f62bae50SIngo Molnar value = APIC_DM_NMI; 1315f62bae50SIngo Molnar if (!lapic_is_integrated()) /* 82489DX */ 1316f62bae50SIngo Molnar value |= APIC_LVT_LEVEL_TRIGGER; 1317b7c4948eSHidehiro Kawai if (apic_extnmi == APIC_EXTNMI_NONE) 1318b7c4948eSHidehiro Kawai value |= APIC_LVT_MASKED; 1319f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 1320f62bae50SIngo Molnar } 1321f62bae50SIngo Molnar 13224b1669e8SDou Liyang /* Init the interrupt delivery mode for the BSP */ 13234b1669e8SDou Liyang void __init apic_intr_mode_init(void) 13244b1669e8SDou Liyang { 13254b1669e8SDou Liyang switch (apic_intr_mode_select()) { 13264b1669e8SDou Liyang case APIC_PIC: 13274b1669e8SDou Liyang pr_info("APIC: Keep in PIC mode(8259)\n"); 13284b1669e8SDou Liyang return; 13294b1669e8SDou Liyang case APIC_VIRTUAL_WIRE: 13304b1669e8SDou Liyang pr_info("APIC: Switch to virtual wire mode setup\n"); 13314b1669e8SDou Liyang return; 13324b1669e8SDou Liyang case APIC_SYMMETRIC_IO: 13334b1669e8SDou Liyang pr_info("APIC: Switch to symmectic I/O mode setup\n"); 13344b1669e8SDou Liyang return; 13354b1669e8SDou Liyang } 13364b1669e8SDou Liyang } 13374b1669e8SDou Liyang 1338148f9bb8SPaul Gortmaker static void lapic_setup_esr(void) 1339f62bae50SIngo Molnar { 1340f62bae50SIngo Molnar unsigned int oldvalue, value, maxlvt; 1341f62bae50SIngo Molnar 1342f62bae50SIngo Molnar if (!lapic_is_integrated()) { 1343f62bae50SIngo Molnar pr_info("No ESR for 82489DX.\n"); 1344f62bae50SIngo Molnar return; 1345f62bae50SIngo Molnar } 1346f62bae50SIngo Molnar 1347f62bae50SIngo Molnar if (apic->disable_esr) { 1348f62bae50SIngo Molnar /* 1349f62bae50SIngo Molnar * Something untraceable is creating bad interrupts on 1350f62bae50SIngo Molnar * secondary quads ... for the moment, just leave the 1351f62bae50SIngo Molnar * ESR disabled - we can't do anything useful with the 1352f62bae50SIngo Molnar * errors anyway - mbligh 1353f62bae50SIngo Molnar */ 1354f62bae50SIngo Molnar pr_info("Leaving ESR disabled.\n"); 1355f62bae50SIngo Molnar return; 1356f62bae50SIngo Molnar } 1357f62bae50SIngo Molnar 1358f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 1359f62bae50SIngo Molnar if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1360f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1361f62bae50SIngo Molnar oldvalue = apic_read(APIC_ESR); 1362f62bae50SIngo Molnar 1363f62bae50SIngo Molnar /* enables sending errors */ 1364f62bae50SIngo Molnar value = ERROR_APIC_VECTOR; 1365f62bae50SIngo Molnar apic_write(APIC_LVTERR, value); 1366f62bae50SIngo Molnar 1367f62bae50SIngo Molnar /* 1368f62bae50SIngo Molnar * spec says clear errors after enabling vector. 1369f62bae50SIngo Molnar */ 1370f62bae50SIngo Molnar if (maxlvt > 3) 1371f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1372f62bae50SIngo Molnar value = apic_read(APIC_ESR); 1373f62bae50SIngo Molnar if (value != oldvalue) 1374f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "ESR value before enabling " 1375f62bae50SIngo Molnar "vector: 0x%08x after: 0x%08x\n", 1376f62bae50SIngo Molnar oldvalue, value); 1377f62bae50SIngo Molnar } 1378f62bae50SIngo Molnar 1379f62bae50SIngo Molnar /** 1380f62bae50SIngo Molnar * setup_local_APIC - setup the local APIC 13810aa002feSTejun Heo * 1382543113d2SDou Liyang * Used to setup local APIC while initializing BSP or bringing up APs. 13830aa002feSTejun Heo * Always called with preemption disabled. 1384f62bae50SIngo Molnar */ 1385148f9bb8SPaul Gortmaker void setup_local_APIC(void) 1386f62bae50SIngo Molnar { 13870aa002feSTejun Heo int cpu = smp_processor_id(); 13888c3ba8d0SKerstin Jonsson unsigned int value, queued; 13898c3ba8d0SKerstin Jonsson int i, j, acked = 0; 13908c3ba8d0SKerstin Jonsson unsigned long long tsc = 0, ntsc; 1391b47dcbdcSAndy Lutomirski long long max_loops = cpu_khz ? cpu_khz : 1000000; 13928c3ba8d0SKerstin Jonsson 139359e21e3dSBorislav Petkov if (boot_cpu_has(X86_FEATURE_TSC)) 13944ea1636bSAndy Lutomirski tsc = rdtsc(); 1395f62bae50SIngo Molnar 1396f62bae50SIngo Molnar if (disable_apic) { 13977167d08eSHenrik Kretzschmar disable_ioapic_support(); 1398f62bae50SIngo Molnar return; 1399f62bae50SIngo Molnar } 1400f62bae50SIngo Molnar 1401f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1402f62bae50SIngo Molnar /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1403f62bae50SIngo Molnar if (lapic_is_integrated() && apic->disable_esr) { 1404f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1405f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1406f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1407f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1408f62bae50SIngo Molnar } 1409f62bae50SIngo Molnar #endif 1410cdd6c482SIngo Molnar perf_events_lapic_init(); 1411f62bae50SIngo Molnar 1412f62bae50SIngo Molnar /* 1413f62bae50SIngo Molnar * Double-check whether this APIC is really registered. 1414f62bae50SIngo Molnar * This is meaningless in clustered apic mode, so we skip it. 1415f62bae50SIngo Molnar */ 1416c2777f98SDaniel Walker BUG_ON(!apic->apic_id_registered()); 1417f62bae50SIngo Molnar 1418f62bae50SIngo Molnar /* 1419f62bae50SIngo Molnar * Intel recommends to set DFR, LDR and TPR before enabling 1420f62bae50SIngo Molnar * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1421f62bae50SIngo Molnar * document number 292116). So here it goes... 1422f62bae50SIngo Molnar */ 1423f62bae50SIngo Molnar apic->init_apic_ldr(); 1424f62bae50SIngo Molnar 14256f802c4bSTejun Heo #ifdef CONFIG_X86_32 14266f802c4bSTejun Heo /* 1427acb8bc09STejun Heo * APIC LDR is initialized. If logical_apicid mapping was 1428acb8bc09STejun Heo * initialized during get_smp_config(), make sure it matches the 1429acb8bc09STejun Heo * actual value. 14306f802c4bSTejun Heo */ 1431acb8bc09STejun Heo i = early_per_cpu(x86_cpu_to_logical_apicid, cpu); 1432acb8bc09STejun Heo WARN_ON(i != BAD_APICID && i != logical_smp_processor_id()); 1433acb8bc09STejun Heo /* always use the value from LDR */ 14346f802c4bSTejun Heo early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 14356f802c4bSTejun Heo logical_smp_processor_id(); 14366f802c4bSTejun Heo #endif 14376f802c4bSTejun Heo 1438f62bae50SIngo Molnar /* 1439f62bae50SIngo Molnar * Set Task Priority to 'accept all'. We never change this 1440f62bae50SIngo Molnar * later on. 1441f62bae50SIngo Molnar */ 1442f62bae50SIngo Molnar value = apic_read(APIC_TASKPRI); 1443f62bae50SIngo Molnar value &= ~APIC_TPRI_MASK; 1444f62bae50SIngo Molnar apic_write(APIC_TASKPRI, value); 1445f62bae50SIngo Molnar 1446f62bae50SIngo Molnar /* 1447f62bae50SIngo Molnar * After a crash, we no longer service the interrupts and a pending 1448f62bae50SIngo Molnar * interrupt from previous kernel might still have ISR bit set. 1449f62bae50SIngo Molnar * 1450f62bae50SIngo Molnar * Most probably by now CPU has serviced that pending interrupt and 1451f62bae50SIngo Molnar * it might not have done the ack_APIC_irq() because it thought, 1452f62bae50SIngo Molnar * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1453f62bae50SIngo Molnar * does not clear the ISR bit and cpu thinks it has already serivced 1454f62bae50SIngo Molnar * the interrupt. Hence a vector might get locked. It was noticed 1455f62bae50SIngo Molnar * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1456f62bae50SIngo Molnar */ 14578c3ba8d0SKerstin Jonsson do { 14588c3ba8d0SKerstin Jonsson queued = 0; 14598c3ba8d0SKerstin Jonsson for (i = APIC_ISR_NR - 1; i >= 0; i--) 14608c3ba8d0SKerstin Jonsson queued |= apic_read(APIC_IRR + i*0x10); 14618c3ba8d0SKerstin Jonsson 1462f62bae50SIngo Molnar for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1463f62bae50SIngo Molnar value = apic_read(APIC_ISR + i*0x10); 1464f62bae50SIngo Molnar for (j = 31; j >= 0; j--) { 14658c3ba8d0SKerstin Jonsson if (value & (1<<j)) { 1466f62bae50SIngo Molnar ack_APIC_irq(); 14678c3ba8d0SKerstin Jonsson acked++; 1468f62bae50SIngo Molnar } 1469f62bae50SIngo Molnar } 14708c3ba8d0SKerstin Jonsson } 14718c3ba8d0SKerstin Jonsson if (acked > 256) { 14728c3ba8d0SKerstin Jonsson printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", 14738c3ba8d0SKerstin Jonsson acked); 14748c3ba8d0SKerstin Jonsson break; 14758c3ba8d0SKerstin Jonsson } 147642fa4250SShai Fultheim if (queued) { 147759e21e3dSBorislav Petkov if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) { 14784ea1636bSAndy Lutomirski ntsc = rdtsc(); 14798c3ba8d0SKerstin Jonsson max_loops = (cpu_khz << 10) - (ntsc - tsc); 14808c3ba8d0SKerstin Jonsson } else 14818c3ba8d0SKerstin Jonsson max_loops--; 148242fa4250SShai Fultheim } 14838c3ba8d0SKerstin Jonsson } while (queued && max_loops > 0); 14848c3ba8d0SKerstin Jonsson WARN_ON(max_loops <= 0); 1485f62bae50SIngo Molnar 1486f62bae50SIngo Molnar /* 1487f62bae50SIngo Molnar * Now that we are all set up, enable the APIC 1488f62bae50SIngo Molnar */ 1489f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 1490f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 1491f62bae50SIngo Molnar /* 1492f62bae50SIngo Molnar * Enable APIC 1493f62bae50SIngo Molnar */ 1494f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 1495f62bae50SIngo Molnar 1496f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1497f62bae50SIngo Molnar /* 1498f62bae50SIngo Molnar * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1499f62bae50SIngo Molnar * certain networking cards. If high frequency interrupts are 1500f62bae50SIngo Molnar * happening on a particular IOAPIC pin, plus the IOAPIC routing 1501f62bae50SIngo Molnar * entry is masked/unmasked at a high rate as well then sooner or 1502f62bae50SIngo Molnar * later IOAPIC line gets 'stuck', no more interrupts are received 1503f62bae50SIngo Molnar * from the device. If focus CPU is disabled then the hang goes 1504f62bae50SIngo Molnar * away, oh well :-( 1505f62bae50SIngo Molnar * 1506f62bae50SIngo Molnar * [ This bug can be reproduced easily with a level-triggered 1507f62bae50SIngo Molnar * PCI Ne2000 networking cards and PII/PIII processors, dual 1508f62bae50SIngo Molnar * BX chipset. ] 1509f62bae50SIngo Molnar */ 1510f62bae50SIngo Molnar /* 1511f62bae50SIngo Molnar * Actually disabling the focus CPU check just makes the hang less 1512f62bae50SIngo Molnar * frequent as it makes the interrupt distributon model be more 1513f62bae50SIngo Molnar * like LRU than MRU (the short-term load is more even across CPUs). 1514f62bae50SIngo Molnar */ 1515f62bae50SIngo Molnar 1516f62bae50SIngo Molnar /* 1517f62bae50SIngo Molnar * - enable focus processor (bit==0) 1518f62bae50SIngo Molnar * - 64bit mode always use processor focus 1519f62bae50SIngo Molnar * so no need to set it 1520f62bae50SIngo Molnar */ 1521f62bae50SIngo Molnar value &= ~APIC_SPIV_FOCUS_DISABLED; 1522f62bae50SIngo Molnar #endif 1523f62bae50SIngo Molnar 1524f62bae50SIngo Molnar /* 1525f62bae50SIngo Molnar * Set spurious IRQ vector 1526f62bae50SIngo Molnar */ 1527f62bae50SIngo Molnar value |= SPURIOUS_APIC_VECTOR; 1528f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 1529f62bae50SIngo Molnar 1530f62bae50SIngo Molnar /* 1531f62bae50SIngo Molnar * Set up LVT0, LVT1: 1532f62bae50SIngo Molnar * 1533f62bae50SIngo Molnar * set up through-local-APIC on the BP's LINT0. This is not 1534f62bae50SIngo Molnar * strictly necessary in pure symmetric-IO mode, but sometimes 1535f62bae50SIngo Molnar * we delegate interrupts to the 8259A. 1536f62bae50SIngo Molnar */ 1537f62bae50SIngo Molnar /* 1538f62bae50SIngo Molnar * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1539f62bae50SIngo Molnar */ 1540f62bae50SIngo Molnar value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 15410aa002feSTejun Heo if (!cpu && (pic_mode || !value)) { 1542f62bae50SIngo Molnar value = APIC_DM_EXTINT; 15430aa002feSTejun Heo apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1544f62bae50SIngo Molnar } else { 1545f62bae50SIngo Molnar value = APIC_DM_EXTINT | APIC_LVT_MASKED; 15460aa002feSTejun Heo apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1547f62bae50SIngo Molnar } 1548f62bae50SIngo Molnar apic_write(APIC_LVT0, value); 1549f62bae50SIngo Molnar 1550f62bae50SIngo Molnar /* 1551b7c4948eSHidehiro Kawai * Only the BSP sees the LINT1 NMI signal by default. This can be 1552b7c4948eSHidehiro Kawai * modified by apic_extnmi= boot option. 1553f62bae50SIngo Molnar */ 1554b7c4948eSHidehiro Kawai if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) || 1555b7c4948eSHidehiro Kawai apic_extnmi == APIC_EXTNMI_ALL) 1556f62bae50SIngo Molnar value = APIC_DM_NMI; 1557f62bae50SIngo Molnar else 1558f62bae50SIngo Molnar value = APIC_DM_NMI | APIC_LVT_MASKED; 1559f62bae50SIngo Molnar if (!lapic_is_integrated()) /* 82489DX */ 1560f62bae50SIngo Molnar value |= APIC_LVT_LEVEL_TRIGGER; 1561f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 1562f62bae50SIngo Molnar 1563638bee71SH. Peter Anvin #ifdef CONFIG_X86_MCE_INTEL 1564638bee71SH. Peter Anvin /* Recheck CMCI information after local APIC is up on CPU #0 */ 15650aa002feSTejun Heo if (!cpu) 1566638bee71SH. Peter Anvin cmci_recheck(); 1567638bee71SH. Peter Anvin #endif 1568f62bae50SIngo Molnar } 1569f62bae50SIngo Molnar 157005f7e46dSThomas Gleixner static void end_local_APIC_setup(void) 1571f62bae50SIngo Molnar { 1572f62bae50SIngo Molnar lapic_setup_esr(); 1573f62bae50SIngo Molnar 1574f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1575f62bae50SIngo Molnar { 1576f62bae50SIngo Molnar unsigned int value; 1577f62bae50SIngo Molnar /* Disable the local apic timer */ 1578f62bae50SIngo Molnar value = apic_read(APIC_LVTT); 1579f62bae50SIngo Molnar value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1580f62bae50SIngo Molnar apic_write(APIC_LVTT, value); 1581f62bae50SIngo Molnar } 1582f62bae50SIngo Molnar #endif 1583f62bae50SIngo Molnar 1584f62bae50SIngo Molnar apic_pm_activate(); 15852fb270f3SJan Beulich } 15862fb270f3SJan Beulich 15877f7fbf45SKenji Kaneshige /* 158805f7e46dSThomas Gleixner * APIC setup function for application processors. Called from smpboot.c 15897f7fbf45SKenji Kaneshige */ 159005f7e46dSThomas Gleixner void apic_ap_setup(void) 159105f7e46dSThomas Gleixner { 159205f7e46dSThomas Gleixner setup_local_APIC(); 159305f7e46dSThomas Gleixner end_local_APIC_setup(); 1594f62bae50SIngo Molnar } 1595f62bae50SIngo Molnar 1596f62bae50SIngo Molnar #ifdef CONFIG_X86_X2APIC 1597bfb05070SThomas Gleixner int x2apic_mode; 159812e189d3SThomas Gleixner 159912e189d3SThomas Gleixner enum { 160012e189d3SThomas Gleixner X2APIC_OFF, 160112e189d3SThomas Gleixner X2APIC_ON, 160212e189d3SThomas Gleixner X2APIC_DISABLED, 160312e189d3SThomas Gleixner }; 160412e189d3SThomas Gleixner static int x2apic_state; 160512e189d3SThomas Gleixner 1606d786ad32SDenys Vlasenko static void __x2apic_disable(void) 160744e25ff9SThomas Gleixner { 160844e25ff9SThomas Gleixner u64 msr; 160944e25ff9SThomas Gleixner 161093984fbdSBorislav Petkov if (!boot_cpu_has(X86_FEATURE_APIC)) 1611659006bfSThomas Gleixner return; 1612659006bfSThomas Gleixner 161344e25ff9SThomas Gleixner rdmsrl(MSR_IA32_APICBASE, msr); 161444e25ff9SThomas Gleixner if (!(msr & X2APIC_ENABLE)) 161544e25ff9SThomas Gleixner return; 161644e25ff9SThomas Gleixner /* Disable xapic and x2apic first and then reenable xapic mode */ 161744e25ff9SThomas Gleixner wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); 161844e25ff9SThomas Gleixner wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); 161944e25ff9SThomas Gleixner printk_once(KERN_INFO "x2apic disabled\n"); 162044e25ff9SThomas Gleixner } 162144e25ff9SThomas Gleixner 1622d786ad32SDenys Vlasenko static void __x2apic_enable(void) 1623659006bfSThomas Gleixner { 1624659006bfSThomas Gleixner u64 msr; 1625659006bfSThomas Gleixner 1626659006bfSThomas Gleixner rdmsrl(MSR_IA32_APICBASE, msr); 1627659006bfSThomas Gleixner if (msr & X2APIC_ENABLE) 1628659006bfSThomas Gleixner return; 1629659006bfSThomas Gleixner wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); 1630659006bfSThomas Gleixner printk_once(KERN_INFO "x2apic enabled\n"); 1631659006bfSThomas Gleixner } 1632659006bfSThomas Gleixner 1633bfb05070SThomas Gleixner static int __init setup_nox2apic(char *str) 1634bfb05070SThomas Gleixner { 1635bfb05070SThomas Gleixner if (x2apic_enabled()) { 1636bfb05070SThomas Gleixner int apicid = native_apic_msr_read(APIC_ID); 1637bfb05070SThomas Gleixner 1638bfb05070SThomas Gleixner if (apicid >= 255) { 1639bfb05070SThomas Gleixner pr_warning("Apicid: %08x, cannot enforce nox2apic\n", 1640bfb05070SThomas Gleixner apicid); 1641bfb05070SThomas Gleixner return 0; 1642bfb05070SThomas Gleixner } 164344e25ff9SThomas Gleixner pr_warning("x2apic already enabled.\n"); 164444e25ff9SThomas Gleixner __x2apic_disable(); 164544e25ff9SThomas Gleixner } 1646bfb05070SThomas Gleixner setup_clear_cpu_cap(X86_FEATURE_X2APIC); 164712e189d3SThomas Gleixner x2apic_state = X2APIC_DISABLED; 164844e25ff9SThomas Gleixner x2apic_mode = 0; 1649bfb05070SThomas Gleixner return 0; 1650bfb05070SThomas Gleixner } 1651bfb05070SThomas Gleixner early_param("nox2apic", setup_nox2apic); 1652bfb05070SThomas Gleixner 1653659006bfSThomas Gleixner /* Called from cpu_init() to enable x2apic on (secondary) cpus */ 1654659006bfSThomas Gleixner void x2apic_setup(void) 1655659006bfSThomas Gleixner { 1656659006bfSThomas Gleixner /* 1657659006bfSThomas Gleixner * If x2apic is not in ON state, disable it if already enabled 1658659006bfSThomas Gleixner * from BIOS. 1659659006bfSThomas Gleixner */ 1660659006bfSThomas Gleixner if (x2apic_state != X2APIC_ON) { 1661659006bfSThomas Gleixner __x2apic_disable(); 1662659006bfSThomas Gleixner return; 1663659006bfSThomas Gleixner } 1664659006bfSThomas Gleixner __x2apic_enable(); 1665659006bfSThomas Gleixner } 1666659006bfSThomas Gleixner 166744e25ff9SThomas Gleixner static __init void x2apic_disable(void) 1668fb209bd8SYinghai Lu { 1669a57e456aSThomas Gleixner u32 x2apic_id, state = x2apic_state; 1670fb209bd8SYinghai Lu 1671a57e456aSThomas Gleixner x2apic_mode = 0; 1672a57e456aSThomas Gleixner x2apic_state = X2APIC_DISABLED; 1673a57e456aSThomas Gleixner 1674a57e456aSThomas Gleixner if (state != X2APIC_ON) 1675a57e456aSThomas Gleixner return; 1676fb209bd8SYinghai Lu 16776d2d49d2SThomas Gleixner x2apic_id = read_apic_id(); 1678fb209bd8SYinghai Lu if (x2apic_id >= 255) 1679fb209bd8SYinghai Lu panic("Cannot disable x2apic, id: %08x\n", x2apic_id); 1680fb209bd8SYinghai Lu 168144e25ff9SThomas Gleixner __x2apic_disable(); 1682fb209bd8SYinghai Lu register_lapic_address(mp_lapic_addr); 1683fb209bd8SYinghai Lu } 1684fb209bd8SYinghai Lu 1685659006bfSThomas Gleixner static __init void x2apic_enable(void) 1686f62bae50SIngo Molnar { 1687659006bfSThomas Gleixner if (x2apic_state != X2APIC_OFF) 1688f62bae50SIngo Molnar return; 1689f62bae50SIngo Molnar 1690659006bfSThomas Gleixner x2apic_mode = 1; 169112e189d3SThomas Gleixner x2apic_state = X2APIC_ON; 1692659006bfSThomas Gleixner __x2apic_enable(); 1693f62bae50SIngo Molnar } 1694d524165cSThomas Gleixner 169562e61633SThomas Gleixner static __init void try_to_enable_x2apic(int remap_mode) 169607806c50SJiang Liu { 1697659006bfSThomas Gleixner if (x2apic_state == X2APIC_DISABLED) 169807806c50SJiang Liu return; 169907806c50SJiang Liu 170062e61633SThomas Gleixner if (remap_mode != IRQ_REMAP_X2APIC_MODE) { 170107806c50SJiang Liu /* IR is required if there is APIC ID > 255 even when running 170207806c50SJiang Liu * under KVM 170307806c50SJiang Liu */ 170407806c50SJiang Liu if (max_physical_apicid > 255 || 17058329aa9fSLinus Torvalds !hypervisor_x2apic_available()) { 170662e61633SThomas Gleixner pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); 170744e25ff9SThomas Gleixner x2apic_disable(); 170807806c50SJiang Liu return; 170907806c50SJiang Liu } 171007806c50SJiang Liu 171107806c50SJiang Liu /* 171207806c50SJiang Liu * without IR all CPUs can be addressed by IOAPIC/MSI 171307806c50SJiang Liu * only in physical mode 171407806c50SJiang Liu */ 171555eae7deSThomas Gleixner x2apic_phys = 1; 171607806c50SJiang Liu } 1717659006bfSThomas Gleixner x2apic_enable(); 171855eae7deSThomas Gleixner } 171955eae7deSThomas Gleixner 172055eae7deSThomas Gleixner void __init check_x2apic(void) 172155eae7deSThomas Gleixner { 172255eae7deSThomas Gleixner if (x2apic_enabled()) { 172355eae7deSThomas Gleixner pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); 172455eae7deSThomas Gleixner x2apic_mode = 1; 172512e189d3SThomas Gleixner x2apic_state = X2APIC_ON; 172662436a4dSBorislav Petkov } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) { 172712e189d3SThomas Gleixner x2apic_state = X2APIC_DISABLED; 172855eae7deSThomas Gleixner } 172955eae7deSThomas Gleixner } 173055eae7deSThomas Gleixner #else /* CONFIG_X86_X2APIC */ 173155eae7deSThomas Gleixner static int __init validate_x2apic(void) 173255eae7deSThomas Gleixner { 173355eae7deSThomas Gleixner if (!apic_is_x2apic_enabled()) 173455eae7deSThomas Gleixner return 0; 173555eae7deSThomas Gleixner /* 173655eae7deSThomas Gleixner * Checkme: Can we simply turn off x2apic here instead of panic? 173755eae7deSThomas Gleixner */ 173855eae7deSThomas Gleixner panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n"); 173955eae7deSThomas Gleixner } 174055eae7deSThomas Gleixner early_initcall(validate_x2apic); 174155eae7deSThomas Gleixner 174262e61633SThomas Gleixner static inline void try_to_enable_x2apic(int remap_mode) { } 1743659006bfSThomas Gleixner static inline void __x2apic_enable(void) { } 174455eae7deSThomas Gleixner #endif /* !CONFIG_X86_X2APIC */ 174555eae7deSThomas Gleixner 1746ce69a784SGleb Natapov void __init enable_IR_x2apic(void) 1747ce69a784SGleb Natapov { 1748ce69a784SGleb Natapov unsigned long flags; 174907806c50SJiang Liu int ret, ir_stat; 1750b7f42ab2SYinghai Lu 175111277aabSDou Liyang if (skip_ioapic_setup) { 175211277aabSDou Liyang pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); 17532e63ad4bSWanpeng Li return; 175411277aabSDou Liyang } 17552e63ad4bSWanpeng Li 175607806c50SJiang Liu ir_stat = irq_remapping_prepare(); 175707806c50SJiang Liu if (ir_stat < 0 && !x2apic_supported()) 1758e670761fSYinghai Lu return; 1759ce69a784SGleb Natapov 176031dce14aSSuresh Siddha ret = save_ioapic_entries(); 1761f62bae50SIngo Molnar if (ret) { 1762f62bae50SIngo Molnar pr_info("Saving IO-APIC state failed: %d\n", ret); 1763fb209bd8SYinghai Lu return; 1764f62bae50SIngo Molnar } 1765f62bae50SIngo Molnar 176605c3dc2cSSuresh Siddha local_irq_save(flags); 1767b81bb373SJacob Pan legacy_pic->mask_all(); 176831dce14aSSuresh Siddha mask_ioapic_entries(); 176905c3dc2cSSuresh Siddha 17706a6256f9SAdam Buchbinder /* If irq_remapping_prepare() succeeded, try to enable it */ 177107806c50SJiang Liu if (ir_stat >= 0) 177211277aabSDou Liyang ir_stat = irq_remapping_enable(); 177307806c50SJiang Liu /* ir_stat contains the remap mode or an error code */ 177407806c50SJiang Liu try_to_enable_x2apic(ir_stat); 1775a31bc327SYinghai Lu 177607806c50SJiang Liu if (ir_stat < 0) 177731dce14aSSuresh Siddha restore_ioapic_entries(); 1778b81bb373SJacob Pan legacy_pic->restore_mask(); 1779f62bae50SIngo Molnar local_irq_restore(flags); 1780f62bae50SIngo Molnar } 178193758238SWeidong Han 1782f62bae50SIngo Molnar #ifdef CONFIG_X86_64 1783f62bae50SIngo Molnar /* 1784f62bae50SIngo Molnar * Detect and enable local APICs on non-SMP boards. 1785f62bae50SIngo Molnar * Original code written by Keir Fraser. 1786f62bae50SIngo Molnar * On AMD64 we trust the BIOS - if it says no APIC it is likely 1787f62bae50SIngo Molnar * not correctly set up (usually the APIC timer won't work etc.) 1788f62bae50SIngo Molnar */ 1789f62bae50SIngo Molnar static int __init detect_init_APIC(void) 1790f62bae50SIngo Molnar { 179193984fbdSBorislav Petkov if (!boot_cpu_has(X86_FEATURE_APIC)) { 1792f62bae50SIngo Molnar pr_info("No local APIC present\n"); 1793f62bae50SIngo Molnar return -1; 1794f62bae50SIngo Molnar } 1795f62bae50SIngo Molnar 1796f62bae50SIngo Molnar mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1797f62bae50SIngo Molnar return 0; 1798f62bae50SIngo Molnar } 1799f62bae50SIngo Molnar #else 18005a7ae78fSThomas Gleixner 180125874a29SHenrik Kretzschmar static int __init apic_verify(void) 18025a7ae78fSThomas Gleixner { 18035a7ae78fSThomas Gleixner u32 features, h, l; 18045a7ae78fSThomas Gleixner 18055a7ae78fSThomas Gleixner /* 18065a7ae78fSThomas Gleixner * The APIC feature bit should now be enabled 18075a7ae78fSThomas Gleixner * in `cpuid' 18085a7ae78fSThomas Gleixner */ 18095a7ae78fSThomas Gleixner features = cpuid_edx(1); 18105a7ae78fSThomas Gleixner if (!(features & (1 << X86_FEATURE_APIC))) { 18115a7ae78fSThomas Gleixner pr_warning("Could not enable APIC!\n"); 18125a7ae78fSThomas Gleixner return -1; 18135a7ae78fSThomas Gleixner } 18145a7ae78fSThomas Gleixner set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 18155a7ae78fSThomas Gleixner mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 18165a7ae78fSThomas Gleixner 18175a7ae78fSThomas Gleixner /* The BIOS may have set up the APIC at some other address */ 1818cbf2829bSBryan O'Donoghue if (boot_cpu_data.x86 >= 6) { 18195a7ae78fSThomas Gleixner rdmsr(MSR_IA32_APICBASE, l, h); 18205a7ae78fSThomas Gleixner if (l & MSR_IA32_APICBASE_ENABLE) 18215a7ae78fSThomas Gleixner mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1822cbf2829bSBryan O'Donoghue } 18235a7ae78fSThomas Gleixner 18245a7ae78fSThomas Gleixner pr_info("Found and enabled local APIC!\n"); 18255a7ae78fSThomas Gleixner return 0; 18265a7ae78fSThomas Gleixner } 18275a7ae78fSThomas Gleixner 182825874a29SHenrik Kretzschmar int __init apic_force_enable(unsigned long addr) 18295a7ae78fSThomas Gleixner { 18305a7ae78fSThomas Gleixner u32 h, l; 18315a7ae78fSThomas Gleixner 18325a7ae78fSThomas Gleixner if (disable_apic) 18335a7ae78fSThomas Gleixner return -1; 18345a7ae78fSThomas Gleixner 18355a7ae78fSThomas Gleixner /* 18365a7ae78fSThomas Gleixner * Some BIOSes disable the local APIC in the APIC_BASE 18375a7ae78fSThomas Gleixner * MSR. This can only be done in software for Intel P6 or later 18385a7ae78fSThomas Gleixner * and AMD K7 (Model > 1) or later. 18395a7ae78fSThomas Gleixner */ 1840cbf2829bSBryan O'Donoghue if (boot_cpu_data.x86 >= 6) { 18415a7ae78fSThomas Gleixner rdmsr(MSR_IA32_APICBASE, l, h); 18425a7ae78fSThomas Gleixner if (!(l & MSR_IA32_APICBASE_ENABLE)) { 18435a7ae78fSThomas Gleixner pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 18445a7ae78fSThomas Gleixner l &= ~MSR_IA32_APICBASE_BASE; 1845a906fdaaSThomas Gleixner l |= MSR_IA32_APICBASE_ENABLE | addr; 18465a7ae78fSThomas Gleixner wrmsr(MSR_IA32_APICBASE, l, h); 18475a7ae78fSThomas Gleixner enabled_via_apicbase = 1; 18485a7ae78fSThomas Gleixner } 1849cbf2829bSBryan O'Donoghue } 18505a7ae78fSThomas Gleixner return apic_verify(); 18515a7ae78fSThomas Gleixner } 18525a7ae78fSThomas Gleixner 1853f62bae50SIngo Molnar /* 1854f62bae50SIngo Molnar * Detect and initialize APIC 1855f62bae50SIngo Molnar */ 1856f62bae50SIngo Molnar static int __init detect_init_APIC(void) 1857f62bae50SIngo Molnar { 1858f62bae50SIngo Molnar /* Disabled by kernel option? */ 1859f62bae50SIngo Molnar if (disable_apic) 1860f62bae50SIngo Molnar return -1; 1861f62bae50SIngo Molnar 1862f62bae50SIngo Molnar switch (boot_cpu_data.x86_vendor) { 1863f62bae50SIngo Molnar case X86_VENDOR_AMD: 1864f62bae50SIngo Molnar if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1865f62bae50SIngo Molnar (boot_cpu_data.x86 >= 15)) 1866f62bae50SIngo Molnar break; 1867f62bae50SIngo Molnar goto no_apic; 1868f62bae50SIngo Molnar case X86_VENDOR_INTEL: 1869f62bae50SIngo Molnar if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 187093984fbdSBorislav Petkov (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC))) 1871f62bae50SIngo Molnar break; 1872f62bae50SIngo Molnar goto no_apic; 1873f62bae50SIngo Molnar default: 1874f62bae50SIngo Molnar goto no_apic; 1875f62bae50SIngo Molnar } 1876f62bae50SIngo Molnar 187793984fbdSBorislav Petkov if (!boot_cpu_has(X86_FEATURE_APIC)) { 1878f62bae50SIngo Molnar /* 1879f62bae50SIngo Molnar * Over-ride BIOS and try to enable the local APIC only if 1880f62bae50SIngo Molnar * "lapic" specified. 1881f62bae50SIngo Molnar */ 1882f62bae50SIngo Molnar if (!force_enable_local_apic) { 1883f62bae50SIngo Molnar pr_info("Local APIC disabled by BIOS -- " 1884f62bae50SIngo Molnar "you can enable it with \"lapic\"\n"); 1885f62bae50SIngo Molnar return -1; 1886f62bae50SIngo Molnar } 1887a906fdaaSThomas Gleixner if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) 18885a7ae78fSThomas Gleixner return -1; 18895a7ae78fSThomas Gleixner } else { 18905a7ae78fSThomas Gleixner if (apic_verify()) 1891f62bae50SIngo Molnar return -1; 1892f62bae50SIngo Molnar } 1893f62bae50SIngo Molnar 1894f62bae50SIngo Molnar apic_pm_activate(); 1895f62bae50SIngo Molnar 1896f62bae50SIngo Molnar return 0; 1897f62bae50SIngo Molnar 1898f62bae50SIngo Molnar no_apic: 1899f62bae50SIngo Molnar pr_info("No local APIC present or hardware disabled\n"); 1900f62bae50SIngo Molnar return -1; 1901f62bae50SIngo Molnar } 1902f62bae50SIngo Molnar #endif 1903f62bae50SIngo Molnar 1904f62bae50SIngo Molnar /** 1905f62bae50SIngo Molnar * init_apic_mappings - initialize APIC mappings 1906f62bae50SIngo Molnar */ 1907f62bae50SIngo Molnar void __init init_apic_mappings(void) 1908f62bae50SIngo Molnar { 19094401da61SYinghai Lu unsigned int new_apicid; 19104401da61SYinghai Lu 1911bd9240a1SPeter Zijlstra apic_check_deadline_errata(); 1912bd9240a1SPeter Zijlstra 1913fc1edaf9SSuresh Siddha if (x2apic_mode) { 1914f62bae50SIngo Molnar boot_cpu_physical_apicid = read_apic_id(); 1915f62bae50SIngo Molnar return; 1916f62bae50SIngo Molnar } 1917f62bae50SIngo Molnar 19184797f6b0SYinghai Lu /* If no local APIC can be found return early */ 1919f62bae50SIngo Molnar if (!smp_found_config && detect_init_APIC()) { 19204797f6b0SYinghai Lu /* lets NOP'ify apic operations */ 19214797f6b0SYinghai Lu pr_info("APIC: disable apic facility\n"); 19224797f6b0SYinghai Lu apic_disable(); 19234797f6b0SYinghai Lu } else { 1924f62bae50SIngo Molnar apic_phys = mp_lapic_addr; 1925f62bae50SIngo Molnar 19264401da61SYinghai Lu /* 19275ba039a5SDou Liyang * If the system has ACPI MADT tables or MP info, the LAPIC 19285ba039a5SDou Liyang * address is already registered. 19294401da61SYinghai Lu */ 19305989cd6aSEric W. Biederman if (!acpi_lapic && !smp_found_config) 1931326a2e6bSYinghai Lu register_lapic_address(apic_phys); 1932cec6be6dSCyrill Gorcunov } 1933f62bae50SIngo Molnar 1934f62bae50SIngo Molnar /* 1935f62bae50SIngo Molnar * Fetch the APIC ID of the BSP in case we have a 1936f62bae50SIngo Molnar * default configuration (or the MP table is broken). 1937f62bae50SIngo Molnar */ 19384401da61SYinghai Lu new_apicid = read_apic_id(); 19394401da61SYinghai Lu if (boot_cpu_physical_apicid != new_apicid) { 19404401da61SYinghai Lu boot_cpu_physical_apicid = new_apicid; 1941103428e5SCyrill Gorcunov /* 1942103428e5SCyrill Gorcunov * yeah -- we lie about apic_version 1943103428e5SCyrill Gorcunov * in case if apic was disabled via boot option 1944103428e5SCyrill Gorcunov * but it's not a problem for SMP compiled kernel 1945103428e5SCyrill Gorcunov * since smp_sanity_check is prepared for such a case 1946103428e5SCyrill Gorcunov * and disable smp mode 1947103428e5SCyrill Gorcunov */ 1948cff9ab2bSDenys Vlasenko boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 194908306ce6SCyrill Gorcunov } 1950f62bae50SIngo Molnar } 1951f62bae50SIngo Molnar 1952c0104d38SYinghai Lu void __init register_lapic_address(unsigned long address) 1953c0104d38SYinghai Lu { 1954c0104d38SYinghai Lu mp_lapic_addr = address; 1955c0104d38SYinghai Lu 19560450193bSYinghai Lu if (!x2apic_mode) { 1957c0104d38SYinghai Lu set_fixmap_nocache(FIX_APIC_BASE, address); 1958f1157141SYinghai Lu apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 19596de42119SBaoquan He APIC_BASE, address); 19600450193bSYinghai Lu } 1961c0104d38SYinghai Lu if (boot_cpu_physical_apicid == -1U) { 1962c0104d38SYinghai Lu boot_cpu_physical_apicid = read_apic_id(); 1963cff9ab2bSDenys Vlasenko boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 1964c0104d38SYinghai Lu } 1965c0104d38SYinghai Lu } 1966c0104d38SYinghai Lu 1967f62bae50SIngo Molnar /* 1968f62bae50SIngo Molnar * Local APIC interrupts 1969f62bae50SIngo Molnar */ 1970f62bae50SIngo Molnar 1971f62bae50SIngo Molnar /* 1972f62bae50SIngo Molnar * This interrupt should _never_ happen with our APIC/SMP architecture 1973f62bae50SIngo Molnar */ 197461069de7SThomas Gleixner __visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs) 1975f62bae50SIngo Molnar { 197661069de7SThomas Gleixner u8 vector = ~regs->orig_ax; 1977f62bae50SIngo Molnar u32 v; 1978f62bae50SIngo Molnar 197961069de7SThomas Gleixner entering_irq(); 198061069de7SThomas Gleixner trace_spurious_apic_entry(vector); 198161069de7SThomas Gleixner 1982f62bae50SIngo Molnar /* 1983f62bae50SIngo Molnar * Check if this really is a spurious interrupt and ACK it 1984f62bae50SIngo Molnar * if it is a vectored one. Just in case... 1985f62bae50SIngo Molnar * Spurious interrupts should not be ACKed. 1986f62bae50SIngo Molnar */ 19872414e021SJan Beulich v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); 19882414e021SJan Beulich if (v & (1 << (vector & 0x1f))) 1989f62bae50SIngo Molnar ack_APIC_irq(); 1990f62bae50SIngo Molnar 1991f62bae50SIngo Molnar inc_irq_stat(irq_spurious_count); 1992f62bae50SIngo Molnar 1993f62bae50SIngo Molnar /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 19942414e021SJan Beulich pr_info("spurious APIC interrupt through vector %02x on CPU#%d, " 19952414e021SJan Beulich "should never happen.\n", vector, smp_processor_id()); 1996eddc0e92SSeiji Aguchi 19972414e021SJan Beulich trace_spurious_apic_exit(vector); 1998cf910e83SSeiji Aguchi exiting_irq(); 1999f62bae50SIngo Molnar } 2000f62bae50SIngo Molnar 2001f62bae50SIngo Molnar /* 2002f62bae50SIngo Molnar * This interrupt should never happen with our APIC/SMP architecture 2003f62bae50SIngo Molnar */ 200461069de7SThomas Gleixner __visible void __irq_entry smp_error_interrupt(struct pt_regs *regs) 2005f62bae50SIngo Molnar { 20062b398bd9SYouquan Song static const char * const error_interrupt_reason[] = { 20072b398bd9SYouquan Song "Send CS error", /* APIC Error Bit 0 */ 20082b398bd9SYouquan Song "Receive CS error", /* APIC Error Bit 1 */ 20092b398bd9SYouquan Song "Send accept error", /* APIC Error Bit 2 */ 20102b398bd9SYouquan Song "Receive accept error", /* APIC Error Bit 3 */ 20112b398bd9SYouquan Song "Redirectable IPI", /* APIC Error Bit 4 */ 20122b398bd9SYouquan Song "Send illegal vector", /* APIC Error Bit 5 */ 20132b398bd9SYouquan Song "Received illegal vector", /* APIC Error Bit 6 */ 20142b398bd9SYouquan Song "Illegal register address", /* APIC Error Bit 7 */ 20152b398bd9SYouquan Song }; 201661069de7SThomas Gleixner u32 v, i = 0; 201761069de7SThomas Gleixner 201861069de7SThomas Gleixner entering_irq(); 201961069de7SThomas Gleixner trace_error_apic_entry(ERROR_APIC_VECTOR); 2020f62bae50SIngo Molnar 2021f62bae50SIngo Molnar /* First tickle the hardware, only then report what went on. -- REW */ 2022023de4a0SMaciej W. Rozycki if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ 2023f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 202460283df7SRichard Weinberger v = apic_read(APIC_ESR); 2025f62bae50SIngo Molnar ack_APIC_irq(); 2026f62bae50SIngo Molnar atomic_inc(&irq_err_count); 2027f62bae50SIngo Molnar 202860283df7SRichard Weinberger apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", 202960283df7SRichard Weinberger smp_processor_id(), v); 20302b398bd9SYouquan Song 203160283df7SRichard Weinberger v &= 0xff; 203260283df7SRichard Weinberger while (v) { 203360283df7SRichard Weinberger if (v & 0x1) 20342b398bd9SYouquan Song apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); 20352b398bd9SYouquan Song i++; 203660283df7SRichard Weinberger v >>= 1; 20374b8073e4SPeter Senna Tschudin } 20382b398bd9SYouquan Song 20392b398bd9SYouquan Song apic_printk(APIC_DEBUG, KERN_CONT "\n"); 20402b398bd9SYouquan Song 2041cf910e83SSeiji Aguchi trace_error_apic_exit(ERROR_APIC_VECTOR); 2042cf910e83SSeiji Aguchi exiting_irq(); 2043f62bae50SIngo Molnar } 2044f62bae50SIngo Molnar 2045f62bae50SIngo Molnar /** 2046f62bae50SIngo Molnar * connect_bsp_APIC - attach the APIC to the interrupt system 2047f62bae50SIngo Molnar */ 204805f7e46dSThomas Gleixner static void __init connect_bsp_APIC(void) 2049f62bae50SIngo Molnar { 2050f62bae50SIngo Molnar #ifdef CONFIG_X86_32 2051f62bae50SIngo Molnar if (pic_mode) { 2052f62bae50SIngo Molnar /* 2053f62bae50SIngo Molnar * Do not trust the local APIC being empty at bootup. 2054f62bae50SIngo Molnar */ 2055f62bae50SIngo Molnar clear_local_APIC(); 2056f62bae50SIngo Molnar /* 2057f62bae50SIngo Molnar * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 2058f62bae50SIngo Molnar * local APIC to INT and NMI lines. 2059f62bae50SIngo Molnar */ 2060f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "leaving PIC mode, " 2061f62bae50SIngo Molnar "enabling APIC mode.\n"); 2062c0eaa453SCyrill Gorcunov imcr_pic_to_apic(); 2063f62bae50SIngo Molnar } 2064f62bae50SIngo Molnar #endif 2065f62bae50SIngo Molnar } 2066f62bae50SIngo Molnar 2067f62bae50SIngo Molnar /** 2068f62bae50SIngo Molnar * disconnect_bsp_APIC - detach the APIC from the interrupt system 2069f62bae50SIngo Molnar * @virt_wire_setup: indicates, whether virtual wire mode is selected 2070f62bae50SIngo Molnar * 2071f62bae50SIngo Molnar * Virtual wire mode is necessary to deliver legacy interrupts even when the 2072f62bae50SIngo Molnar * APIC is disabled. 2073f62bae50SIngo Molnar */ 2074f62bae50SIngo Molnar void disconnect_bsp_APIC(int virt_wire_setup) 2075f62bae50SIngo Molnar { 2076f62bae50SIngo Molnar unsigned int value; 2077f62bae50SIngo Molnar 2078f62bae50SIngo Molnar #ifdef CONFIG_X86_32 2079f62bae50SIngo Molnar if (pic_mode) { 2080f62bae50SIngo Molnar /* 2081f62bae50SIngo Molnar * Put the board back into PIC mode (has an effect only on 2082f62bae50SIngo Molnar * certain older boards). Note that APIC interrupts, including 2083f62bae50SIngo Molnar * IPIs, won't work beyond this point! The only exception are 2084f62bae50SIngo Molnar * INIT IPIs. 2085f62bae50SIngo Molnar */ 2086f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "disabling APIC mode, " 2087f62bae50SIngo Molnar "entering PIC mode.\n"); 2088c0eaa453SCyrill Gorcunov imcr_apic_to_pic(); 2089f62bae50SIngo Molnar return; 2090f62bae50SIngo Molnar } 2091f62bae50SIngo Molnar #endif 2092f62bae50SIngo Molnar 2093f62bae50SIngo Molnar /* Go back to Virtual Wire compatibility mode */ 2094f62bae50SIngo Molnar 2095f62bae50SIngo Molnar /* For the spurious interrupt use vector F, and enable it */ 2096f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 2097f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 2098f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 2099f62bae50SIngo Molnar value |= 0xf; 2100f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 2101f62bae50SIngo Molnar 2102f62bae50SIngo Molnar if (!virt_wire_setup) { 2103f62bae50SIngo Molnar /* 2104f62bae50SIngo Molnar * For LVT0 make it edge triggered, active high, 2105f62bae50SIngo Molnar * external and enabled 2106f62bae50SIngo Molnar */ 2107f62bae50SIngo Molnar value = apic_read(APIC_LVT0); 2108f62bae50SIngo Molnar value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2109f62bae50SIngo Molnar APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2110f62bae50SIngo Molnar APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2111f62bae50SIngo Molnar value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2112f62bae50SIngo Molnar value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 2113f62bae50SIngo Molnar apic_write(APIC_LVT0, value); 2114f62bae50SIngo Molnar } else { 2115f62bae50SIngo Molnar /* Disable LVT0 */ 2116f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_LVT_MASKED); 2117f62bae50SIngo Molnar } 2118f62bae50SIngo Molnar 2119f62bae50SIngo Molnar /* 2120f62bae50SIngo Molnar * For LVT1 make it edge triggered, active high, 2121f62bae50SIngo Molnar * nmi and enabled 2122f62bae50SIngo Molnar */ 2123f62bae50SIngo Molnar value = apic_read(APIC_LVT1); 2124f62bae50SIngo Molnar value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2125f62bae50SIngo Molnar APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2126f62bae50SIngo Molnar APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2127f62bae50SIngo Molnar value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2128f62bae50SIngo Molnar value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 2129f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 2130f62bae50SIngo Molnar } 2131f62bae50SIngo Molnar 21328f54969dSGu Zheng /* 21338f54969dSGu Zheng * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated 21348f54969dSGu Zheng * contiguously, it equals to current allocated max logical CPU ID plus 1. 213512bf98b9SDou Liyang * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range, 213612bf98b9SDou Liyang * so the maximum of nr_logical_cpuids is nr_cpu_ids. 21378f54969dSGu Zheng * 21388f54969dSGu Zheng * NOTE: Reserve 0 for BSP. 21398f54969dSGu Zheng */ 21408f54969dSGu Zheng static int nr_logical_cpuids = 1; 21418f54969dSGu Zheng 21428f54969dSGu Zheng /* 21438f54969dSGu Zheng * Used to store mapping between logical CPU IDs and APIC IDs. 21448f54969dSGu Zheng */ 21458f54969dSGu Zheng static int cpuid_to_apicid[] = { 21468f54969dSGu Zheng [0 ... NR_CPUS - 1] = -1, 21478f54969dSGu Zheng }; 21488f54969dSGu Zheng 21498f54969dSGu Zheng /* 21508f54969dSGu Zheng * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids 21518f54969dSGu Zheng * and cpuid_to_apicid[] synchronized. 21528f54969dSGu Zheng */ 21538f54969dSGu Zheng static int allocate_logical_cpuid(int apicid) 21548f54969dSGu Zheng { 21558f54969dSGu Zheng int i; 21568f54969dSGu Zheng 21578f54969dSGu Zheng /* 21588f54969dSGu Zheng * cpuid <-> apicid mapping is persistent, so when a cpu is up, 21598f54969dSGu Zheng * check if the kernel has allocated a cpuid for it. 21608f54969dSGu Zheng */ 21618f54969dSGu Zheng for (i = 0; i < nr_logical_cpuids; i++) { 21628f54969dSGu Zheng if (cpuid_to_apicid[i] == apicid) 21638f54969dSGu Zheng return i; 21648f54969dSGu Zheng } 21658f54969dSGu Zheng 21668f54969dSGu Zheng /* Allocate a new cpuid. */ 21678f54969dSGu Zheng if (nr_logical_cpuids >= nr_cpu_ids) { 21689b130ad5SAlexey Dobriyan WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. " 21698f54969dSGu Zheng "Processor %d/0x%x and the rest are ignored.\n", 2170bb3f0a52SDou Liyang nr_cpu_ids, nr_logical_cpuids, apicid); 2171bb3f0a52SDou Liyang return -EINVAL; 21728f54969dSGu Zheng } 21738f54969dSGu Zheng 21748f54969dSGu Zheng cpuid_to_apicid[nr_logical_cpuids] = apicid; 21758f54969dSGu Zheng return nr_logical_cpuids++; 21768f54969dSGu Zheng } 21778f54969dSGu Zheng 21782b85b3d2SDou Liyang int generic_processor_info(int apicid, int version) 2179f62bae50SIngo Molnar { 218014cb6dcfSVivek Goyal int cpu, max = nr_cpu_ids; 218114cb6dcfSVivek Goyal bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, 218214cb6dcfSVivek Goyal phys_cpu_present_map); 218314cb6dcfSVivek Goyal 218414cb6dcfSVivek Goyal /* 2185151e0c7dSHATAYAMA Daisuke * boot_cpu_physical_apicid is designed to have the apicid 2186151e0c7dSHATAYAMA Daisuke * returned by read_apic_id(), i.e, the apicid of the 2187151e0c7dSHATAYAMA Daisuke * currently booting-up processor. However, on some platforms, 21885b4d1dbcSH. Peter Anvin * it is temporarily modified by the apicid reported as BSP 2189151e0c7dSHATAYAMA Daisuke * through MP table. Concretely: 2190151e0c7dSHATAYAMA Daisuke * 2191151e0c7dSHATAYAMA Daisuke * - arch/x86/kernel/mpparse.c: MP_processor_info() 2192151e0c7dSHATAYAMA Daisuke * - arch/x86/mm/amdtopology.c: amd_numa_init() 2193151e0c7dSHATAYAMA Daisuke * 2194151e0c7dSHATAYAMA Daisuke * This function is executed with the modified 2195151e0c7dSHATAYAMA Daisuke * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel 2196151e0c7dSHATAYAMA Daisuke * parameter doesn't work to disable APs on kdump 2nd kernel. 2197151e0c7dSHATAYAMA Daisuke * 2198151e0c7dSHATAYAMA Daisuke * Since fixing handling of boot_cpu_physical_apicid requires 2199151e0c7dSHATAYAMA Daisuke * another discussion and tests on each platform, we leave it 2200151e0c7dSHATAYAMA Daisuke * for now and here we use read_apic_id() directly in this 2201e2329b42SDou Liyang * function, generic_processor_info(). 2202151e0c7dSHATAYAMA Daisuke */ 2203151e0c7dSHATAYAMA Daisuke if (disabled_cpu_apicid != BAD_APICID && 2204151e0c7dSHATAYAMA Daisuke disabled_cpu_apicid != read_apic_id() && 2205151e0c7dSHATAYAMA Daisuke disabled_cpu_apicid == apicid) { 2206151e0c7dSHATAYAMA Daisuke int thiscpu = num_processors + disabled_cpus; 2207151e0c7dSHATAYAMA Daisuke 22085b4d1dbcSH. Peter Anvin pr_warning("APIC: Disabling requested cpu." 2209151e0c7dSHATAYAMA Daisuke " Processor %d/0x%x ignored.\n", 2210151e0c7dSHATAYAMA Daisuke thiscpu, apicid); 2211151e0c7dSHATAYAMA Daisuke 2212151e0c7dSHATAYAMA Daisuke disabled_cpus++; 2213151e0c7dSHATAYAMA Daisuke return -ENODEV; 2214151e0c7dSHATAYAMA Daisuke } 2215151e0c7dSHATAYAMA Daisuke 2216151e0c7dSHATAYAMA Daisuke /* 221714cb6dcfSVivek Goyal * If boot cpu has not been detected yet, then only allow upto 221814cb6dcfSVivek Goyal * nr_cpu_ids - 1 processors and keep one slot free for boot cpu 221914cb6dcfSVivek Goyal */ 222014cb6dcfSVivek Goyal if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && 222114cb6dcfSVivek Goyal apicid != boot_cpu_physical_apicid) { 222214cb6dcfSVivek Goyal int thiscpu = max + disabled_cpus - 1; 222314cb6dcfSVivek Goyal 222414cb6dcfSVivek Goyal pr_warning( 22253c8fad91SClaudio Fontana "APIC: NR_CPUS/possible_cpus limit of %i almost" 222614cb6dcfSVivek Goyal " reached. Keeping one slot for boot cpu." 222714cb6dcfSVivek Goyal " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 222814cb6dcfSVivek Goyal 222914cb6dcfSVivek Goyal disabled_cpus++; 22307e1f85f9SJiang Liu return -ENODEV; 223114cb6dcfSVivek Goyal } 2232f62bae50SIngo Molnar 2233f62bae50SIngo Molnar if (num_processors >= nr_cpu_ids) { 2234f62bae50SIngo Molnar int thiscpu = max + disabled_cpus; 2235f62bae50SIngo Molnar 2236df610d67SThomas Gleixner pr_warning("APIC: NR_CPUS/possible_cpus limit of %i " 2237df610d67SThomas Gleixner "reached. Processor %d/0x%x ignored.\n", 2238df610d67SThomas Gleixner max, thiscpu, apicid); 2239f62bae50SIngo Molnar 2240f62bae50SIngo Molnar disabled_cpus++; 22417e1f85f9SJiang Liu return -EINVAL; 2242f62bae50SIngo Molnar } 2243f62bae50SIngo Molnar 2244f62bae50SIngo Molnar if (apicid == boot_cpu_physical_apicid) { 2245f62bae50SIngo Molnar /* 2246f62bae50SIngo Molnar * x86_bios_cpu_apicid is required to have processors listed 2247f62bae50SIngo Molnar * in same order as logical cpu numbers. Hence the first 2248f62bae50SIngo Molnar * entry is BSP, and so on. 2249e5fea868SYinghai Lu * boot_cpu_init() already hold bit 0 in cpu_present_mask 2250e5fea868SYinghai Lu * for BSP. 2251f62bae50SIngo Molnar */ 2252f62bae50SIngo Molnar cpu = 0; 22538f54969dSGu Zheng 22548f54969dSGu Zheng /* Logical cpuid 0 is reserved for BSP. */ 22558f54969dSGu Zheng cpuid_to_apicid[0] = apicid; 22568f54969dSGu Zheng } else { 22578f54969dSGu Zheng cpu = allocate_logical_cpuid(apicid); 22588f54969dSGu Zheng if (cpu < 0) { 22598f54969dSGu Zheng disabled_cpus++; 22608f54969dSGu Zheng return -EINVAL; 22618f54969dSGu Zheng } 22628f54969dSGu Zheng } 2263e5fea868SYinghai Lu 2264e5fea868SYinghai Lu /* 2265e5fea868SYinghai Lu * Validate version 2266e5fea868SYinghai Lu */ 2267e5fea868SYinghai Lu if (version == 0x0) { 2268e5fea868SYinghai Lu pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", 2269e5fea868SYinghai Lu cpu, apicid); 2270e5fea868SYinghai Lu version = 0x10; 2271f62bae50SIngo Molnar } 2272e5fea868SYinghai Lu 2273cff9ab2bSDenys Vlasenko if (version != boot_cpu_apic_version) { 2274e5fea868SYinghai Lu pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", 2275cff9ab2bSDenys Vlasenko boot_cpu_apic_version, cpu, version); 2276e5fea868SYinghai Lu } 2277e5fea868SYinghai Lu 2278f62bae50SIngo Molnar if (apicid > max_physical_apicid) 2279f62bae50SIngo Molnar max_physical_apicid = apicid; 2280f62bae50SIngo Molnar 2281f62bae50SIngo Molnar #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 2282f62bae50SIngo Molnar early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 2283f62bae50SIngo Molnar early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 2284f62bae50SIngo Molnar #endif 2285acb8bc09STejun Heo #ifdef CONFIG_X86_32 2286acb8bc09STejun Heo early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 2287acb8bc09STejun Heo apic->x86_32_early_logical_apicid(cpu); 2288acb8bc09STejun Heo #endif 2289f62bae50SIngo Molnar set_cpu_possible(cpu, true); 2290f7c28833SGu Zheng physid_set(apicid, phys_cpu_present_map); 2291f62bae50SIngo Molnar set_cpu_present(cpu, true); 22922b85b3d2SDou Liyang num_processors++; 22937e1f85f9SJiang Liu 22947e1f85f9SJiang Liu return cpu; 2295f62bae50SIngo Molnar } 2296f62bae50SIngo Molnar 2297f62bae50SIngo Molnar int hard_smp_processor_id(void) 2298f62bae50SIngo Molnar { 2299f62bae50SIngo Molnar return read_apic_id(); 2300f62bae50SIngo Molnar } 2301f62bae50SIngo Molnar 2302f62bae50SIngo Molnar void default_init_apic_ldr(void) 2303f62bae50SIngo Molnar { 2304f62bae50SIngo Molnar unsigned long val; 2305f62bae50SIngo Molnar 2306f62bae50SIngo Molnar apic_write(APIC_DFR, APIC_DFR_VALUE); 2307f62bae50SIngo Molnar val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; 2308f62bae50SIngo Molnar val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); 2309f62bae50SIngo Molnar apic_write(APIC_LDR, val); 2310f62bae50SIngo Molnar } 2311f62bae50SIngo Molnar 23120e24f7c9SThomas Gleixner int default_cpu_mask_to_apicid(const struct cpumask *mask, 23130e24f7c9SThomas Gleixner struct irq_data *irqdata, 23140e24f7c9SThomas Gleixner unsigned int *apicid) 23156398268dSAlexander Gordeev { 231691cd9cb7SThomas Gleixner unsigned int cpu = cpumask_first(mask); 23176398268dSAlexander Gordeev 231852b166afSThomas Gleixner if (cpu >= nr_cpu_ids) 231952b166afSThomas Gleixner return -EINVAL; 2320a5a39156SAlexander Gordeev *apicid = per_cpu(x86_cpu_to_apicid, cpu); 2321c7d6c9ddSThomas Gleixner irq_data_update_effective_affinity(irqdata, cpumask_of(cpu)); 2322a5a39156SAlexander Gordeev return 0; 2323a5a39156SAlexander Gordeev } 2324ea3807eaSAlexander Gordeev 23250e24f7c9SThomas Gleixner int flat_cpu_mask_to_apicid(const struct cpumask *mask, 23260e24f7c9SThomas Gleixner struct irq_data *irqdata, 23270e24f7c9SThomas Gleixner unsigned int *apicid) 23280e24f7c9SThomas Gleixner 2329ad95212eSThomas Gleixner { 2330c7d6c9ddSThomas Gleixner struct cpumask *effmsk = irq_data_get_effective_affinity_mask(irqdata); 233191cd9cb7SThomas Gleixner unsigned long cpu_mask = cpumask_bits(mask)[0] & APIC_ALL_CPUS; 2332ad95212eSThomas Gleixner 233352b166afSThomas Gleixner if (!cpu_mask) 233452b166afSThomas Gleixner return -EINVAL; 2335ad95212eSThomas Gleixner *apicid = (unsigned int)cpu_mask; 2336c7d6c9ddSThomas Gleixner cpumask_bits(effmsk)[0] = cpu_mask; 2337ad95212eSThomas Gleixner return 0; 2338ad95212eSThomas Gleixner } 2339ad95212eSThomas Gleixner 2340f62bae50SIngo Molnar /* 23411551df64SMichael S. Tsirkin * Override the generic EOI implementation with an optimized version. 23421551df64SMichael S. Tsirkin * Only called during early boot when only one CPU is active and with 23431551df64SMichael S. Tsirkin * interrupts disabled, so we know this does not race with actual APIC driver 23441551df64SMichael S. Tsirkin * use. 23451551df64SMichael S. Tsirkin */ 23461551df64SMichael S. Tsirkin void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) 23471551df64SMichael S. Tsirkin { 23481551df64SMichael S. Tsirkin struct apic **drv; 23491551df64SMichael S. Tsirkin 23501551df64SMichael S. Tsirkin for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { 23511551df64SMichael S. Tsirkin /* Should happen once for each apic */ 23521551df64SMichael S. Tsirkin WARN_ON((*drv)->eoi_write == eoi_write); 23538ca22552SWanpeng Li (*drv)->native_eoi_write = (*drv)->eoi_write; 23541551df64SMichael S. Tsirkin (*drv)->eoi_write = eoi_write; 23551551df64SMichael S. Tsirkin } 23561551df64SMichael S. Tsirkin } 23571551df64SMichael S. Tsirkin 2358374aab33SThomas Gleixner static void __init apic_bsp_up_setup(void) 235905f7e46dSThomas Gleixner { 2360374aab33SThomas Gleixner #ifdef CONFIG_X86_64 23615d64d209SDou Liyang apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid)); 2362374aab33SThomas Gleixner #else 236305f7e46dSThomas Gleixner /* 2364374aab33SThomas Gleixner * Hack: In case of kdump, after a crash, kernel might be booting 2365374aab33SThomas Gleixner * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 2366374aab33SThomas Gleixner * might be zero if read from MP tables. Get it from LAPIC. 236705f7e46dSThomas Gleixner */ 2368374aab33SThomas Gleixner # ifdef CONFIG_CRASH_DUMP 2369374aab33SThomas Gleixner boot_cpu_physical_apicid = read_apic_id(); 2370374aab33SThomas Gleixner # endif 2371374aab33SThomas Gleixner #endif 2372374aab33SThomas Gleixner physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 237305f7e46dSThomas Gleixner } 237405f7e46dSThomas Gleixner 237505f7e46dSThomas Gleixner /** 237605f7e46dSThomas Gleixner * apic_bsp_setup - Setup function for local apic and io-apic 2377374aab33SThomas Gleixner * @upmode: Force UP mode (for APIC_init_uniprocessor) 237805f7e46dSThomas Gleixner * 237905f7e46dSThomas Gleixner * Returns: 238005f7e46dSThomas Gleixner * apic_id of BSP APIC 238105f7e46dSThomas Gleixner */ 2382374aab33SThomas Gleixner int __init apic_bsp_setup(bool upmode) 238305f7e46dSThomas Gleixner { 238405f7e46dSThomas Gleixner int id; 238505f7e46dSThomas Gleixner 238605f7e46dSThomas Gleixner connect_bsp_APIC(); 2387374aab33SThomas Gleixner if (upmode) 2388374aab33SThomas Gleixner apic_bsp_up_setup(); 238905f7e46dSThomas Gleixner setup_local_APIC(); 239005f7e46dSThomas Gleixner 239105f7e46dSThomas Gleixner if (x2apic_mode) 239205f7e46dSThomas Gleixner id = apic_read(APIC_LDR); 239305f7e46dSThomas Gleixner else 239405f7e46dSThomas Gleixner id = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 239505f7e46dSThomas Gleixner 239605f7e46dSThomas Gleixner enable_IO_APIC(); 2397374aab33SThomas Gleixner end_local_APIC_setup(); 2398374aab33SThomas Gleixner irq_remap_enable_fault_handling(); 239905f7e46dSThomas Gleixner setup_IO_APIC(); 240005f7e46dSThomas Gleixner return id; 240105f7e46dSThomas Gleixner } 240205f7e46dSThomas Gleixner 24031551df64SMichael S. Tsirkin /* 2404e714a91fSThomas Gleixner * This initializes the IO-APIC and APIC hardware if this is 2405e714a91fSThomas Gleixner * a UP kernel. 2406e714a91fSThomas Gleixner */ 2407e714a91fSThomas Gleixner int __init APIC_init_uniprocessor(void) 2408e714a91fSThomas Gleixner { 2409e714a91fSThomas Gleixner if (disable_apic) { 2410e714a91fSThomas Gleixner pr_info("Apic disabled\n"); 2411e714a91fSThomas Gleixner return -1; 2412e714a91fSThomas Gleixner } 2413e714a91fSThomas Gleixner #ifdef CONFIG_X86_64 241493984fbdSBorislav Petkov if (!boot_cpu_has(X86_FEATURE_APIC)) { 2415e714a91fSThomas Gleixner disable_apic = 1; 2416e714a91fSThomas Gleixner pr_info("Apic disabled by BIOS\n"); 2417e714a91fSThomas Gleixner return -1; 2418e714a91fSThomas Gleixner } 2419e714a91fSThomas Gleixner #else 242093984fbdSBorislav Petkov if (!smp_found_config && !boot_cpu_has(X86_FEATURE_APIC)) 2421e714a91fSThomas Gleixner return -1; 2422e714a91fSThomas Gleixner 2423e714a91fSThomas Gleixner /* 2424e714a91fSThomas Gleixner * Complain if the BIOS pretends there is one. 2425e714a91fSThomas Gleixner */ 242693984fbdSBorislav Petkov if (!boot_cpu_has(X86_FEATURE_APIC) && 2427cff9ab2bSDenys Vlasenko APIC_INTEGRATED(boot_cpu_apic_version)) { 2428e714a91fSThomas Gleixner pr_err("BIOS bug, local APIC 0x%x not detected!...\n", 2429e714a91fSThomas Gleixner boot_cpu_physical_apicid); 2430e714a91fSThomas Gleixner return -1; 2431e714a91fSThomas Gleixner } 2432e714a91fSThomas Gleixner #endif 2433e714a91fSThomas Gleixner 2434374aab33SThomas Gleixner if (!smp_found_config) 2435374aab33SThomas Gleixner disable_ioapic_support(); 2436374aab33SThomas Gleixner 2437e714a91fSThomas Gleixner default_setup_apic_routing(); 2438374aab33SThomas Gleixner apic_bsp_setup(true); 2439a2510d15SDou Liyang /* Setup local timer */ 2440a2510d15SDou Liyang x86_init.timers.setup_percpu_clockev(); 2441e714a91fSThomas Gleixner return 0; 2442e714a91fSThomas Gleixner } 2443e714a91fSThomas Gleixner 244430b8b006SThomas Gleixner #ifdef CONFIG_UP_LATE_INIT 244530b8b006SThomas Gleixner void __init up_late_init(void) 244630b8b006SThomas Gleixner { 244730b8b006SThomas Gleixner APIC_init_uniprocessor(); 244830b8b006SThomas Gleixner } 244930b8b006SThomas Gleixner #endif 245030b8b006SThomas Gleixner 2451e714a91fSThomas Gleixner /* 2452f62bae50SIngo Molnar * Power management 2453f62bae50SIngo Molnar */ 2454f62bae50SIngo Molnar #ifdef CONFIG_PM 2455f62bae50SIngo Molnar 2456f62bae50SIngo Molnar static struct { 2457f62bae50SIngo Molnar /* 2458f62bae50SIngo Molnar * 'active' is true if the local APIC was enabled by us and 2459f62bae50SIngo Molnar * not the BIOS; this signifies that we are also responsible 2460f62bae50SIngo Molnar * for disabling it before entering apm/acpi suspend 2461f62bae50SIngo Molnar */ 2462f62bae50SIngo Molnar int active; 2463f62bae50SIngo Molnar /* r/w apic fields */ 2464f62bae50SIngo Molnar unsigned int apic_id; 2465f62bae50SIngo Molnar unsigned int apic_taskpri; 2466f62bae50SIngo Molnar unsigned int apic_ldr; 2467f62bae50SIngo Molnar unsigned int apic_dfr; 2468f62bae50SIngo Molnar unsigned int apic_spiv; 2469f62bae50SIngo Molnar unsigned int apic_lvtt; 2470f62bae50SIngo Molnar unsigned int apic_lvtpc; 2471f62bae50SIngo Molnar unsigned int apic_lvt0; 2472f62bae50SIngo Molnar unsigned int apic_lvt1; 2473f62bae50SIngo Molnar unsigned int apic_lvterr; 2474f62bae50SIngo Molnar unsigned int apic_tmict; 2475f62bae50SIngo Molnar unsigned int apic_tdcr; 2476f62bae50SIngo Molnar unsigned int apic_thmr; 247742baa258SJuergen Gross unsigned int apic_cmci; 2478f62bae50SIngo Molnar } apic_pm_state; 2479f62bae50SIngo Molnar 2480f3c6ea1bSRafael J. Wysocki static int lapic_suspend(void) 2481f62bae50SIngo Molnar { 2482f62bae50SIngo Molnar unsigned long flags; 2483f62bae50SIngo Molnar int maxlvt; 2484f62bae50SIngo Molnar 2485f62bae50SIngo Molnar if (!apic_pm_state.active) 2486f62bae50SIngo Molnar return 0; 2487f62bae50SIngo Molnar 2488f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 2489f62bae50SIngo Molnar 2490f62bae50SIngo Molnar apic_pm_state.apic_id = apic_read(APIC_ID); 2491f62bae50SIngo Molnar apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2492f62bae50SIngo Molnar apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2493f62bae50SIngo Molnar apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2494f62bae50SIngo Molnar apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2495f62bae50SIngo Molnar apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2496f62bae50SIngo Molnar if (maxlvt >= 4) 2497f62bae50SIngo Molnar apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2498f62bae50SIngo Molnar apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2499f62bae50SIngo Molnar apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2500f62bae50SIngo Molnar apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2501f62bae50SIngo Molnar apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2502f62bae50SIngo Molnar apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 25034efc0670SAndi Kleen #ifdef CONFIG_X86_THERMAL_VECTOR 2504f62bae50SIngo Molnar if (maxlvt >= 5) 2505f62bae50SIngo Molnar apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2506f62bae50SIngo Molnar #endif 250742baa258SJuergen Gross #ifdef CONFIG_X86_MCE_INTEL 250842baa258SJuergen Gross if (maxlvt >= 6) 250942baa258SJuergen Gross apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI); 251042baa258SJuergen Gross #endif 2511f62bae50SIngo Molnar 2512f62bae50SIngo Molnar local_irq_save(flags); 2513f62bae50SIngo Molnar disable_local_APIC(); 2514fc1edaf9SSuresh Siddha 251595a02e97SSuresh Siddha irq_remapping_disable(); 2516fc1edaf9SSuresh Siddha 2517f62bae50SIngo Molnar local_irq_restore(flags); 2518f62bae50SIngo Molnar return 0; 2519f62bae50SIngo Molnar } 2520f62bae50SIngo Molnar 2521f3c6ea1bSRafael J. Wysocki static void lapic_resume(void) 2522f62bae50SIngo Molnar { 2523f62bae50SIngo Molnar unsigned int l, h; 2524f62bae50SIngo Molnar unsigned long flags; 252531dce14aSSuresh Siddha int maxlvt; 2526b24696bcSFenghua Yu 2527f62bae50SIngo Molnar if (!apic_pm_state.active) 2528f3c6ea1bSRafael J. Wysocki return; 2529f62bae50SIngo Molnar 2530b24696bcSFenghua Yu local_irq_save(flags); 2531336224baSJoerg Roedel 253231dce14aSSuresh Siddha /* 253331dce14aSSuresh Siddha * IO-APIC and PIC have their own resume routines. 253431dce14aSSuresh Siddha * We just mask them here to make sure the interrupt 253531dce14aSSuresh Siddha * subsystem is completely quiet while we enable x2apic 253631dce14aSSuresh Siddha * and interrupt-remapping. 253731dce14aSSuresh Siddha */ 253831dce14aSSuresh Siddha mask_ioapic_entries(); 2539b81bb373SJacob Pan legacy_pic->mask_all(); 2540f62bae50SIngo Molnar 2541659006bfSThomas Gleixner if (x2apic_mode) { 2542659006bfSThomas Gleixner __x2apic_enable(); 2543659006bfSThomas Gleixner } else { 2544f62bae50SIngo Molnar /* 2545f62bae50SIngo Molnar * Make sure the APICBASE points to the right address 2546f62bae50SIngo Molnar * 2547f62bae50SIngo Molnar * FIXME! This will be wrong if we ever support suspend on 2548f62bae50SIngo Molnar * SMP! We'll need to do this as part of the CPU restore! 2549f62bae50SIngo Molnar */ 2550cbf2829bSBryan O'Donoghue if (boot_cpu_data.x86 >= 6) { 2551f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, l, h); 2552f62bae50SIngo Molnar l &= ~MSR_IA32_APICBASE_BASE; 2553f62bae50SIngo Molnar l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2554f62bae50SIngo Molnar wrmsr(MSR_IA32_APICBASE, l, h); 2555f62bae50SIngo Molnar } 2556cbf2829bSBryan O'Donoghue } 2557f62bae50SIngo Molnar 2558b24696bcSFenghua Yu maxlvt = lapic_get_maxlvt(); 2559f62bae50SIngo Molnar apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2560f62bae50SIngo Molnar apic_write(APIC_ID, apic_pm_state.apic_id); 2561f62bae50SIngo Molnar apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2562f62bae50SIngo Molnar apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2563f62bae50SIngo Molnar apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2564f62bae50SIngo Molnar apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2565f62bae50SIngo Molnar apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2566f62bae50SIngo Molnar apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 256742baa258SJuergen Gross #ifdef CONFIG_X86_THERMAL_VECTOR 2568f62bae50SIngo Molnar if (maxlvt >= 5) 2569f62bae50SIngo Molnar apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2570f62bae50SIngo Molnar #endif 257142baa258SJuergen Gross #ifdef CONFIG_X86_MCE_INTEL 257242baa258SJuergen Gross if (maxlvt >= 6) 257342baa258SJuergen Gross apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci); 257442baa258SJuergen Gross #endif 2575f62bae50SIngo Molnar if (maxlvt >= 4) 2576f62bae50SIngo Molnar apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2577f62bae50SIngo Molnar apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2578f62bae50SIngo Molnar apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2579f62bae50SIngo Molnar apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2580f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 2581f62bae50SIngo Molnar apic_read(APIC_ESR); 2582f62bae50SIngo Molnar apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2583f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 2584f62bae50SIngo Molnar apic_read(APIC_ESR); 2585f62bae50SIngo Molnar 258695a02e97SSuresh Siddha irq_remapping_reenable(x2apic_mode); 258731dce14aSSuresh Siddha 2588f62bae50SIngo Molnar local_irq_restore(flags); 2589f62bae50SIngo Molnar } 2590f62bae50SIngo Molnar 2591f62bae50SIngo Molnar /* 2592f62bae50SIngo Molnar * This device has no shutdown method - fully functioning local APICs 2593f62bae50SIngo Molnar * are needed on every CPU up until machine_halt/restart/poweroff. 2594f62bae50SIngo Molnar */ 2595f62bae50SIngo Molnar 2596f3c6ea1bSRafael J. Wysocki static struct syscore_ops lapic_syscore_ops = { 2597f62bae50SIngo Molnar .resume = lapic_resume, 2598f62bae50SIngo Molnar .suspend = lapic_suspend, 2599f62bae50SIngo Molnar }; 2600f62bae50SIngo Molnar 2601148f9bb8SPaul Gortmaker static void apic_pm_activate(void) 2602f62bae50SIngo Molnar { 2603f62bae50SIngo Molnar apic_pm_state.active = 1; 2604f62bae50SIngo Molnar } 2605f62bae50SIngo Molnar 2606f62bae50SIngo Molnar static int __init init_lapic_sysfs(void) 2607f62bae50SIngo Molnar { 2608f62bae50SIngo Molnar /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 260993984fbdSBorislav Petkov if (boot_cpu_has(X86_FEATURE_APIC)) 2610f3c6ea1bSRafael J. Wysocki register_syscore_ops(&lapic_syscore_ops); 2611f62bae50SIngo Molnar 2612f3c6ea1bSRafael J. Wysocki return 0; 2613f62bae50SIngo Molnar } 2614b24696bcSFenghua Yu 2615b24696bcSFenghua Yu /* local apic needs to resume before other devices access its registers. */ 2616b24696bcSFenghua Yu core_initcall(init_lapic_sysfs); 2617f62bae50SIngo Molnar 2618f62bae50SIngo Molnar #else /* CONFIG_PM */ 2619f62bae50SIngo Molnar 2620f62bae50SIngo Molnar static void apic_pm_activate(void) { } 2621f62bae50SIngo Molnar 2622f62bae50SIngo Molnar #endif /* CONFIG_PM */ 2623f62bae50SIngo Molnar 2624f62bae50SIngo Molnar #ifdef CONFIG_X86_64 2625e0e42142SYinghai Lu 2626148f9bb8SPaul Gortmaker static int multi_checked; 2627148f9bb8SPaul Gortmaker static int multi; 2628e0e42142SYinghai Lu 2629148f9bb8SPaul Gortmaker static int set_multi(const struct dmi_system_id *d) 2630e0e42142SYinghai Lu { 2631e0e42142SYinghai Lu if (multi) 2632e0e42142SYinghai Lu return 0; 26336f0aced6SCyrill Gorcunov pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2634e0e42142SYinghai Lu multi = 1; 2635e0e42142SYinghai Lu return 0; 2636e0e42142SYinghai Lu } 2637e0e42142SYinghai Lu 2638148f9bb8SPaul Gortmaker static const struct dmi_system_id multi_dmi_table[] = { 2639e0e42142SYinghai Lu { 2640e0e42142SYinghai Lu .callback = set_multi, 2641e0e42142SYinghai Lu .ident = "IBM System Summit2", 2642e0e42142SYinghai Lu .matches = { 2643e0e42142SYinghai Lu DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2644e0e42142SYinghai Lu DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2645e0e42142SYinghai Lu }, 2646e0e42142SYinghai Lu }, 2647e0e42142SYinghai Lu {} 2648e0e42142SYinghai Lu }; 2649e0e42142SYinghai Lu 2650148f9bb8SPaul Gortmaker static void dmi_check_multi(void) 2651e0e42142SYinghai Lu { 2652e0e42142SYinghai Lu if (multi_checked) 2653e0e42142SYinghai Lu return; 2654e0e42142SYinghai Lu 2655e0e42142SYinghai Lu dmi_check_system(multi_dmi_table); 2656e0e42142SYinghai Lu multi_checked = 1; 2657e0e42142SYinghai Lu } 2658f62bae50SIngo Molnar 2659f62bae50SIngo Molnar /* 2660e0e42142SYinghai Lu * apic_is_clustered_box() -- Check if we can expect good TSC 2661e0e42142SYinghai Lu * 2662e0e42142SYinghai Lu * Thus far, the major user of this is IBM's Summit2 series: 2663e0e42142SYinghai Lu * Clustered boxes may have unsynced TSC problems if they are 2664e0e42142SYinghai Lu * multi-chassis. 2665e0e42142SYinghai Lu * Use DMI to check them 2666f62bae50SIngo Molnar */ 2667148f9bb8SPaul Gortmaker int apic_is_clustered_box(void) 2668e0e42142SYinghai Lu { 2669e0e42142SYinghai Lu dmi_check_multi(); 2670411cf9eeSOren Twaig return multi; 2671f62bae50SIngo Molnar } 2672f62bae50SIngo Molnar #endif 2673f62bae50SIngo Molnar 2674f62bae50SIngo Molnar /* 2675f62bae50SIngo Molnar * APIC command line parameters 2676f62bae50SIngo Molnar */ 2677f62bae50SIngo Molnar static int __init setup_disableapic(char *arg) 2678f62bae50SIngo Molnar { 2679f62bae50SIngo Molnar disable_apic = 1; 2680f62bae50SIngo Molnar setup_clear_cpu_cap(X86_FEATURE_APIC); 2681f62bae50SIngo Molnar return 0; 2682f62bae50SIngo Molnar } 2683f62bae50SIngo Molnar early_param("disableapic", setup_disableapic); 2684f62bae50SIngo Molnar 2685f62bae50SIngo Molnar /* same as disableapic, for compatibility */ 2686f62bae50SIngo Molnar static int __init setup_nolapic(char *arg) 2687f62bae50SIngo Molnar { 2688f62bae50SIngo Molnar return setup_disableapic(arg); 2689f62bae50SIngo Molnar } 2690f62bae50SIngo Molnar early_param("nolapic", setup_nolapic); 2691f62bae50SIngo Molnar 2692f62bae50SIngo Molnar static int __init parse_lapic_timer_c2_ok(char *arg) 2693f62bae50SIngo Molnar { 2694f62bae50SIngo Molnar local_apic_timer_c2_ok = 1; 2695f62bae50SIngo Molnar return 0; 2696f62bae50SIngo Molnar } 2697f62bae50SIngo Molnar early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2698f62bae50SIngo Molnar 2699f62bae50SIngo Molnar static int __init parse_disable_apic_timer(char *arg) 2700f62bae50SIngo Molnar { 2701f62bae50SIngo Molnar disable_apic_timer = 1; 2702f62bae50SIngo Molnar return 0; 2703f62bae50SIngo Molnar } 2704f62bae50SIngo Molnar early_param("noapictimer", parse_disable_apic_timer); 2705f62bae50SIngo Molnar 2706f62bae50SIngo Molnar static int __init parse_nolapic_timer(char *arg) 2707f62bae50SIngo Molnar { 2708f62bae50SIngo Molnar disable_apic_timer = 1; 2709f62bae50SIngo Molnar return 0; 2710f62bae50SIngo Molnar } 2711f62bae50SIngo Molnar early_param("nolapic_timer", parse_nolapic_timer); 2712f62bae50SIngo Molnar 2713f62bae50SIngo Molnar static int __init apic_set_verbosity(char *arg) 2714f62bae50SIngo Molnar { 2715f62bae50SIngo Molnar if (!arg) { 2716f62bae50SIngo Molnar #ifdef CONFIG_X86_64 2717f62bae50SIngo Molnar skip_ioapic_setup = 0; 2718f62bae50SIngo Molnar return 0; 2719f62bae50SIngo Molnar #endif 2720f62bae50SIngo Molnar return -EINVAL; 2721f62bae50SIngo Molnar } 2722f62bae50SIngo Molnar 2723f62bae50SIngo Molnar if (strcmp("debug", arg) == 0) 2724f62bae50SIngo Molnar apic_verbosity = APIC_DEBUG; 2725f62bae50SIngo Molnar else if (strcmp("verbose", arg) == 0) 2726f62bae50SIngo Molnar apic_verbosity = APIC_VERBOSE; 2727f62bae50SIngo Molnar else { 2728f62bae50SIngo Molnar pr_warning("APIC Verbosity level %s not recognised" 2729f62bae50SIngo Molnar " use apic=verbose or apic=debug\n", arg); 2730f62bae50SIngo Molnar return -EINVAL; 2731f62bae50SIngo Molnar } 2732f62bae50SIngo Molnar 2733f62bae50SIngo Molnar return 0; 2734f62bae50SIngo Molnar } 2735f62bae50SIngo Molnar early_param("apic", apic_set_verbosity); 2736f62bae50SIngo Molnar 2737f62bae50SIngo Molnar static int __init lapic_insert_resource(void) 2738f62bae50SIngo Molnar { 2739f62bae50SIngo Molnar if (!apic_phys) 2740f62bae50SIngo Molnar return -1; 2741f62bae50SIngo Molnar 2742f62bae50SIngo Molnar /* Put local APIC into the resource map. */ 2743f62bae50SIngo Molnar lapic_resource.start = apic_phys; 2744f62bae50SIngo Molnar lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2745f62bae50SIngo Molnar insert_resource(&iomem_resource, &lapic_resource); 2746f62bae50SIngo Molnar 2747f62bae50SIngo Molnar return 0; 2748f62bae50SIngo Molnar } 2749f62bae50SIngo Molnar 2750f62bae50SIngo Molnar /* 27511506c8dcSIngo Molnar * need call insert after e820__reserve_resources() 2752f62bae50SIngo Molnar * that is using request_resource 2753f62bae50SIngo Molnar */ 2754f62bae50SIngo Molnar late_initcall(lapic_insert_resource); 2755151e0c7dSHATAYAMA Daisuke 2756151e0c7dSHATAYAMA Daisuke static int __init apic_set_disabled_cpu_apicid(char *arg) 2757151e0c7dSHATAYAMA Daisuke { 2758151e0c7dSHATAYAMA Daisuke if (!arg || !get_option(&arg, &disabled_cpu_apicid)) 2759151e0c7dSHATAYAMA Daisuke return -EINVAL; 2760151e0c7dSHATAYAMA Daisuke 2761151e0c7dSHATAYAMA Daisuke return 0; 2762151e0c7dSHATAYAMA Daisuke } 2763151e0c7dSHATAYAMA Daisuke early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); 2764b7c4948eSHidehiro Kawai 2765b7c4948eSHidehiro Kawai static int __init apic_set_extnmi(char *arg) 2766b7c4948eSHidehiro Kawai { 2767b7c4948eSHidehiro Kawai if (!arg) 2768b7c4948eSHidehiro Kawai return -EINVAL; 2769b7c4948eSHidehiro Kawai 2770b7c4948eSHidehiro Kawai if (!strncmp("all", arg, 3)) 2771b7c4948eSHidehiro Kawai apic_extnmi = APIC_EXTNMI_ALL; 2772b7c4948eSHidehiro Kawai else if (!strncmp("none", arg, 4)) 2773b7c4948eSHidehiro Kawai apic_extnmi = APIC_EXTNMI_NONE; 2774b7c4948eSHidehiro Kawai else if (!strncmp("bsp", arg, 3)) 2775b7c4948eSHidehiro Kawai apic_extnmi = APIC_EXTNMI_BSP; 2776b7c4948eSHidehiro Kawai else { 2777b7c4948eSHidehiro Kawai pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg); 2778b7c4948eSHidehiro Kawai return -EINVAL; 2779b7c4948eSHidehiro Kawai } 2780b7c4948eSHidehiro Kawai 2781b7c4948eSHidehiro Kawai return 0; 2782b7c4948eSHidehiro Kawai } 2783b7c4948eSHidehiro Kawai early_param("apic_extnmi", apic_set_extnmi); 2784