1457c8996SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2f62bae50SIngo Molnar /* 3f62bae50SIngo Molnar * Local APIC handling, local APIC timers 4f62bae50SIngo Molnar * 5f62bae50SIngo Molnar * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6f62bae50SIngo Molnar * 7f62bae50SIngo Molnar * Fixes 8f62bae50SIngo Molnar * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 9f62bae50SIngo Molnar * thanks to Eric Gilmore 10f62bae50SIngo Molnar * and Rolf G. Tews 11f62bae50SIngo Molnar * for testing these extensively. 12f62bae50SIngo Molnar * Maciej W. Rozycki : Various updates and fixes. 13f62bae50SIngo Molnar * Mikael Pettersson : Power Management for UP-APIC. 14f62bae50SIngo Molnar * Pavel Machek and 15f62bae50SIngo Molnar * Mikael Pettersson : PM converted to driver model. 16f62bae50SIngo Molnar */ 17f62bae50SIngo Molnar 18cdd6c482SIngo Molnar #include <linux/perf_event.h> 19f62bae50SIngo Molnar #include <linux/kernel_stat.h> 20f62bae50SIngo Molnar #include <linux/mc146818rtc.h> 21f62bae50SIngo Molnar #include <linux/acpi_pmtmr.h> 22f62bae50SIngo Molnar #include <linux/clockchips.h> 23f62bae50SIngo Molnar #include <linux/interrupt.h> 2457c8a661SMike Rapoport #include <linux/memblock.h> 25f62bae50SIngo Molnar #include <linux/ftrace.h> 26f62bae50SIngo Molnar #include <linux/ioport.h> 27186f4360SPaul Gortmaker #include <linux/export.h> 28f3c6ea1bSRafael J. Wysocki #include <linux/syscore_ops.h> 29f62bae50SIngo Molnar #include <linux/delay.h> 30f62bae50SIngo Molnar #include <linux/timex.h> 31334955efSRalf Baechle #include <linux/i8253.h> 32f62bae50SIngo Molnar #include <linux/dmar.h> 33f62bae50SIngo Molnar #include <linux/init.h> 34f62bae50SIngo Molnar #include <linux/cpu.h> 35f62bae50SIngo Molnar #include <linux/dmi.h> 36f62bae50SIngo Molnar #include <linux/smp.h> 37f62bae50SIngo Molnar #include <linux/mm.h> 38f62bae50SIngo Molnar 3983ab8514SSteven Rostedt (Red Hat) #include <asm/trace/irq_vectors.h> 408a8f422dSSuresh Siddha #include <asm/irq_remapping.h> 41cdd6c482SIngo Molnar #include <asm/perf_event.h> 42736decacSThomas Gleixner #include <asm/x86_init.h> 4360063497SArun Sharma #include <linux/atomic.h> 44f62bae50SIngo Molnar #include <asm/mpspec.h> 45f62bae50SIngo Molnar #include <asm/i8259.h> 46f62bae50SIngo Molnar #include <asm/proto.h> 47ad3bc25aSBorislav Petkov #include <asm/traps.h> 48f62bae50SIngo Molnar #include <asm/apic.h> 4913c01139SIngo Molnar #include <asm/acpi.h> 507167d08eSHenrik Kretzschmar #include <asm/io_apic.h> 51f62bae50SIngo Molnar #include <asm/desc.h> 52f62bae50SIngo Molnar #include <asm/hpet.h> 53f62bae50SIngo Molnar #include <asm/mtrr.h> 5416f871bcSRalf Baechle #include <asm/time.h> 55f62bae50SIngo Molnar #include <asm/smp.h> 56638bee71SH. Peter Anvin #include <asm/mce.h> 578c3ba8d0SKerstin Jonsson #include <asm/tsc.h> 582904ed8dSSheng Yang #include <asm/hypervisor.h> 59bd9240a1SPeter Zijlstra #include <asm/cpu_device_id.h> 60bd9240a1SPeter Zijlstra #include <asm/intel-family.h> 61447ae316SNicolai Stange #include <asm/irq_regs.h> 62f62bae50SIngo Molnar 63f62bae50SIngo Molnar unsigned int num_processors; 64f62bae50SIngo Molnar 65148f9bb8SPaul Gortmaker unsigned disabled_cpus; 66f62bae50SIngo Molnar 67f62bae50SIngo Molnar /* Processor that is doing the boot up */ 686444b40eSSean Christopherson unsigned int boot_cpu_physical_apicid __ro_after_init = -1U; 69cc08e04cSDavid Rientjes EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); 70f62bae50SIngo Molnar 716444b40eSSean Christopherson u8 boot_cpu_apic_version __ro_after_init; 72cff9ab2bSDenys Vlasenko 73f62bae50SIngo Molnar /* 74f62bae50SIngo Molnar * The highest APIC ID seen during enumeration. 75f62bae50SIngo Molnar */ 76a491cc90SJiang Liu static unsigned int max_physical_apicid; 77f62bae50SIngo Molnar 78f62bae50SIngo Molnar /* 79f62bae50SIngo Molnar * Bitmask of physically existing CPUs: 80f62bae50SIngo Molnar */ 81f62bae50SIngo Molnar physid_mask_t phys_cpu_present_map; 82f62bae50SIngo Molnar 83f62bae50SIngo Molnar /* 84151e0c7dSHATAYAMA Daisuke * Processor to be disabled specified by kernel parameter 85151e0c7dSHATAYAMA Daisuke * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to 86151e0c7dSHATAYAMA Daisuke * avoid undefined behaviour caused by sending INIT from AP to BSP. 87151e0c7dSHATAYAMA Daisuke */ 886444b40eSSean Christopherson static unsigned int disabled_cpu_apicid __ro_after_init = BAD_APICID; 89151e0c7dSHATAYAMA Daisuke 90151e0c7dSHATAYAMA Daisuke /* 91b7c4948eSHidehiro Kawai * This variable controls which CPUs receive external NMIs. By default, 92b7c4948eSHidehiro Kawai * external NMIs are delivered only to the BSP. 93b7c4948eSHidehiro Kawai */ 946444b40eSSean Christopherson static int apic_extnmi __ro_after_init = APIC_EXTNMI_BSP; 95b7c4948eSHidehiro Kawai 96b7c4948eSHidehiro Kawai /* 97f62bae50SIngo Molnar * Map cpu index to physical APIC ID 98f62bae50SIngo Molnar */ 990816b0f0SVlad Zolotarov DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); 1000816b0f0SVlad Zolotarov DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); 1013e9e57faSVitaly Kuznetsov DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX); 102f62bae50SIngo Molnar EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 103f62bae50SIngo Molnar EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 1043e9e57faSVitaly Kuznetsov EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); 105f62bae50SIngo Molnar 106f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1074c321ff8STejun Heo 1084c321ff8STejun Heo /* 1094c321ff8STejun Heo * On x86_32, the mapping between cpu and logical apicid may vary 1104c321ff8STejun Heo * depending on apic in use. The following early percpu variable is 1114c321ff8STejun Heo * used for the mapping. This is where the behaviors of x86_64 and 32 1124c321ff8STejun Heo * actually diverge. Let's keep it ugly for now. 1134c321ff8STejun Heo */ 1140816b0f0SVlad Zolotarov DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); 1154c321ff8STejun Heo 116f62bae50SIngo Molnar /* Local APIC was disabled by the BIOS and enabled by the kernel */ 1176444b40eSSean Christopherson static int enabled_via_apicbase __ro_after_init; 118f62bae50SIngo Molnar 119c0eaa453SCyrill Gorcunov /* 120c0eaa453SCyrill Gorcunov * Handle interrupt mode configuration register (IMCR). 121c0eaa453SCyrill Gorcunov * This register controls whether the interrupt signals 122c0eaa453SCyrill Gorcunov * that reach the BSP come from the master PIC or from the 123c0eaa453SCyrill Gorcunov * local APIC. Before entering Symmetric I/O Mode, either 124c0eaa453SCyrill Gorcunov * the BIOS or the operating system must switch out of 125c0eaa453SCyrill Gorcunov * PIC Mode by changing the IMCR. 126c0eaa453SCyrill Gorcunov */ 1275cda395fSAlexander van Heukelum static inline void imcr_pic_to_apic(void) 128c0eaa453SCyrill Gorcunov { 129c0eaa453SCyrill Gorcunov /* select IMCR register */ 130c0eaa453SCyrill Gorcunov outb(0x70, 0x22); 131c0eaa453SCyrill Gorcunov /* NMI and 8259 INTR go through APIC */ 132c0eaa453SCyrill Gorcunov outb(0x01, 0x23); 133c0eaa453SCyrill Gorcunov } 134c0eaa453SCyrill Gorcunov 1355cda395fSAlexander van Heukelum static inline void imcr_apic_to_pic(void) 136c0eaa453SCyrill Gorcunov { 137c0eaa453SCyrill Gorcunov /* select IMCR register */ 138c0eaa453SCyrill Gorcunov outb(0x70, 0x22); 139c0eaa453SCyrill Gorcunov /* NMI and 8259 INTR go directly to BSP */ 140c0eaa453SCyrill Gorcunov outb(0x00, 0x23); 141c0eaa453SCyrill Gorcunov } 142f62bae50SIngo Molnar #endif 143f62bae50SIngo Molnar 144279f1461SSuresh Siddha /* 145279f1461SSuresh Siddha * Knob to control our willingness to enable the local APIC. 146279f1461SSuresh Siddha * 147279f1461SSuresh Siddha * +1=force-enable 148279f1461SSuresh Siddha */ 149279f1461SSuresh Siddha static int force_enable_local_apic __initdata; 150dc9788f4SDavid Rientjes 151279f1461SSuresh Siddha /* 152279f1461SSuresh Siddha * APIC command line parameters 153279f1461SSuresh Siddha */ 154279f1461SSuresh Siddha static int __init parse_lapic(char *arg) 155279f1461SSuresh Siddha { 15697f2645fSMasahiro Yamada if (IS_ENABLED(CONFIG_X86_32) && !arg) 157279f1461SSuresh Siddha force_enable_local_apic = 1; 15827cf9298SMathias Krause else if (arg && !strncmp(arg, "notscdeadline", 13)) 159279f1461SSuresh Siddha setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 160279f1461SSuresh Siddha return 0; 161279f1461SSuresh Siddha } 162279f1461SSuresh Siddha early_param("lapic", parse_lapic); 163279f1461SSuresh Siddha 164f62bae50SIngo Molnar #ifdef CONFIG_X86_64 165f62bae50SIngo Molnar static int apic_calibrate_pmtmr __initdata; 166f62bae50SIngo Molnar static __init int setup_apicpmtimer(char *s) 167f62bae50SIngo Molnar { 168f62bae50SIngo Molnar apic_calibrate_pmtmr = 1; 169f62bae50SIngo Molnar notsc_setup(NULL); 170f62bae50SIngo Molnar return 0; 171f62bae50SIngo Molnar } 172f62bae50SIngo Molnar __setup("apicpmtimer", setup_apicpmtimer); 173f62bae50SIngo Molnar #endif 174f62bae50SIngo Molnar 1756444b40eSSean Christopherson unsigned long mp_lapic_addr __ro_after_init; 1766444b40eSSean Christopherson int disable_apic __ro_after_init; 177f62bae50SIngo Molnar /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 17825874a29SHenrik Kretzschmar static int disable_apic_timer __initdata; 179f62bae50SIngo Molnar /* Local APIC timer works in C2 */ 1806444b40eSSean Christopherson int local_apic_timer_c2_ok __ro_after_init; 181f62bae50SIngo Molnar EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 182f62bae50SIngo Molnar 183f62bae50SIngo Molnar /* 184f62bae50SIngo Molnar * Debug level, exported for io_apic.c 185f62bae50SIngo Molnar */ 1866444b40eSSean Christopherson int apic_verbosity __ro_after_init; 187f62bae50SIngo Molnar 1886444b40eSSean Christopherson int pic_mode __ro_after_init; 189f62bae50SIngo Molnar 190f62bae50SIngo Molnar /* Have we found an MP table */ 1916444b40eSSean Christopherson int smp_found_config __ro_after_init; 192f62bae50SIngo Molnar 193f62bae50SIngo Molnar static struct resource lapic_resource = { 194f62bae50SIngo Molnar .name = "Local APIC", 195f62bae50SIngo Molnar .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 196f62bae50SIngo Molnar }; 197f62bae50SIngo Molnar 19852ae346bSDaniel Drake unsigned int lapic_timer_period = 0; 199f62bae50SIngo Molnar 200f62bae50SIngo Molnar static void apic_pm_activate(void); 201f62bae50SIngo Molnar 2026444b40eSSean Christopherson static unsigned long apic_phys __ro_after_init; 203f62bae50SIngo Molnar 204f62bae50SIngo Molnar /* 205f62bae50SIngo Molnar * Get the LAPIC version 206f62bae50SIngo Molnar */ 207f62bae50SIngo Molnar static inline int lapic_get_version(void) 208f62bae50SIngo Molnar { 209f62bae50SIngo Molnar return GET_APIC_VERSION(apic_read(APIC_LVR)); 210f62bae50SIngo Molnar } 211f62bae50SIngo Molnar 212f62bae50SIngo Molnar /* 213f62bae50SIngo Molnar * Check, if the APIC is integrated or a separate chip 214f62bae50SIngo Molnar */ 215f62bae50SIngo Molnar static inline int lapic_is_integrated(void) 216f62bae50SIngo Molnar { 217f62bae50SIngo Molnar return APIC_INTEGRATED(lapic_get_version()); 218f62bae50SIngo Molnar } 219f62bae50SIngo Molnar 220f62bae50SIngo Molnar /* 221f62bae50SIngo Molnar * Check, whether this is a modern or a first generation APIC 222f62bae50SIngo Molnar */ 223f62bae50SIngo Molnar static int modern_apic(void) 224f62bae50SIngo Molnar { 225f62bae50SIngo Molnar /* AMD systems use old APIC versions, so check the CPU */ 226f62bae50SIngo Molnar if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 227f62bae50SIngo Molnar boot_cpu_data.x86 >= 0xf) 228f62bae50SIngo Molnar return 1; 229da33dfefSPu Wen 230da33dfefSPu Wen /* Hygon systems use modern APIC */ 231da33dfefSPu Wen if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 232da33dfefSPu Wen return 1; 233da33dfefSPu Wen 234f62bae50SIngo Molnar return lapic_get_version() >= 0x14; 235f62bae50SIngo Molnar } 236f62bae50SIngo Molnar 23708306ce6SCyrill Gorcunov /* 238a933c618SCyrill Gorcunov * right after this call apic become NOOP driven 239a933c618SCyrill Gorcunov * so apic->write/read doesn't do anything 24008306ce6SCyrill Gorcunov */ 24125874a29SHenrik Kretzschmar static void __init apic_disable(void) 24208306ce6SCyrill Gorcunov { 243f88f2b4fSCyrill Gorcunov pr_info("APIC: switched to apic NOOP\n"); 244a933c618SCyrill Gorcunov apic = &apic_noop; 24508306ce6SCyrill Gorcunov } 24608306ce6SCyrill Gorcunov 247f62bae50SIngo Molnar void native_apic_wait_icr_idle(void) 248f62bae50SIngo Molnar { 249f62bae50SIngo Molnar while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 250f62bae50SIngo Molnar cpu_relax(); 251f62bae50SIngo Molnar } 252f62bae50SIngo Molnar 253f62bae50SIngo Molnar u32 native_safe_apic_wait_icr_idle(void) 254f62bae50SIngo Molnar { 255f62bae50SIngo Molnar u32 send_status; 256f62bae50SIngo Molnar int timeout; 257f62bae50SIngo Molnar 258f62bae50SIngo Molnar timeout = 0; 259f62bae50SIngo Molnar do { 260f62bae50SIngo Molnar send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 261f62bae50SIngo Molnar if (!send_status) 262f62bae50SIngo Molnar break; 263b49d7d87SFernando Luis Vazquez Cao inc_irq_stat(icr_read_retry_count); 264f62bae50SIngo Molnar udelay(100); 265f62bae50SIngo Molnar } while (timeout++ < 1000); 266f62bae50SIngo Molnar 267f62bae50SIngo Molnar return send_status; 268f62bae50SIngo Molnar } 269f62bae50SIngo Molnar 270f62bae50SIngo Molnar void native_apic_icr_write(u32 low, u32 id) 271f62bae50SIngo Molnar { 272ea7bdc65SJan Kiszka unsigned long flags; 273ea7bdc65SJan Kiszka 274ea7bdc65SJan Kiszka local_irq_save(flags); 275f62bae50SIngo Molnar apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 276f62bae50SIngo Molnar apic_write(APIC_ICR, low); 277ea7bdc65SJan Kiszka local_irq_restore(flags); 278f62bae50SIngo Molnar } 279f62bae50SIngo Molnar 280f62bae50SIngo Molnar u64 native_apic_icr_read(void) 281f62bae50SIngo Molnar { 282f62bae50SIngo Molnar u32 icr1, icr2; 283f62bae50SIngo Molnar 284f62bae50SIngo Molnar icr2 = apic_read(APIC_ICR2); 285f62bae50SIngo Molnar icr1 = apic_read(APIC_ICR); 286f62bae50SIngo Molnar 287f62bae50SIngo Molnar return icr1 | ((u64)icr2 << 32); 288f62bae50SIngo Molnar } 289f62bae50SIngo Molnar 290f62bae50SIngo Molnar #ifdef CONFIG_X86_32 291f62bae50SIngo Molnar /** 292f62bae50SIngo Molnar * get_physical_broadcast - Get number of physical broadcast IDs 293f62bae50SIngo Molnar */ 294f62bae50SIngo Molnar int get_physical_broadcast(void) 295f62bae50SIngo Molnar { 296f62bae50SIngo Molnar return modern_apic() ? 0xff : 0xf; 297f62bae50SIngo Molnar } 298f62bae50SIngo Molnar #endif 299f62bae50SIngo Molnar 300f62bae50SIngo Molnar /** 301f62bae50SIngo Molnar * lapic_get_maxlvt - get the maximum number of local vector table entries 302f62bae50SIngo Molnar */ 303f62bae50SIngo Molnar int lapic_get_maxlvt(void) 304f62bae50SIngo Molnar { 305f62bae50SIngo Molnar /* 306f62bae50SIngo Molnar * - we always have APIC integrated on 64bit mode 307f62bae50SIngo Molnar * - 82489DXs do not report # of LVT entries 308f62bae50SIngo Molnar */ 309ae41a2a4SDou Liyang return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2; 310f62bae50SIngo Molnar } 311f62bae50SIngo Molnar 312f62bae50SIngo Molnar /* 313f62bae50SIngo Molnar * Local APIC timer 314f62bae50SIngo Molnar */ 315f62bae50SIngo Molnar 316f62bae50SIngo Molnar /* Clock divisor */ 317f62bae50SIngo Molnar #define APIC_DIVISOR 16 3181a9e4c56SNicolai Stange #define TSC_DIVISOR 8 319f62bae50SIngo Molnar 320f62bae50SIngo Molnar /* 321f62bae50SIngo Molnar * This function sets up the local APIC timer, with a timeout of 322f62bae50SIngo Molnar * 'clocks' APIC bus clock. During calibration we actually call 323f62bae50SIngo Molnar * this function twice on the boot CPU, once with a bogus timeout 324f62bae50SIngo Molnar * value, second time for real. The other (noncalibrating) CPUs 325f62bae50SIngo Molnar * call this function only once, with the real, calibrated value. 326f62bae50SIngo Molnar * 327f62bae50SIngo Molnar * We do reads before writes even if unnecessary, to get around the 328f62bae50SIngo Molnar * P5 APIC double write bug. 329f62bae50SIngo Molnar */ 330f62bae50SIngo Molnar static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 331f62bae50SIngo Molnar { 332f62bae50SIngo Molnar unsigned int lvtt_value, tmp_value; 333f62bae50SIngo Molnar 334f62bae50SIngo Molnar lvtt_value = LOCAL_TIMER_VECTOR; 335f62bae50SIngo Molnar if (!oneshot) 336f62bae50SIngo Molnar lvtt_value |= APIC_LVT_TIMER_PERIODIC; 337279f1461SSuresh Siddha else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 338279f1461SSuresh Siddha lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; 339279f1461SSuresh Siddha 340f62bae50SIngo Molnar if (!lapic_is_integrated()) 341f62bae50SIngo Molnar lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 342f62bae50SIngo Molnar 343f62bae50SIngo Molnar if (!irqen) 344f62bae50SIngo Molnar lvtt_value |= APIC_LVT_MASKED; 345f62bae50SIngo Molnar 346f62bae50SIngo Molnar apic_write(APIC_LVTT, lvtt_value); 347f62bae50SIngo Molnar 348279f1461SSuresh Siddha if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { 3495d7c631dSShaohua Li /* 3505d7c631dSShaohua Li * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, 3515d7c631dSShaohua Li * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. 3525d7c631dSShaohua Li * According to Intel, MFENCE can do the serialization here. 3535d7c631dSShaohua Li */ 3545d7c631dSShaohua Li asm volatile("mfence" : : : "memory"); 355279f1461SSuresh Siddha return; 356279f1461SSuresh Siddha } 357279f1461SSuresh Siddha 358f62bae50SIngo Molnar /* 359f62bae50SIngo Molnar * Divide PICLK by 16 360f62bae50SIngo Molnar */ 361f62bae50SIngo Molnar tmp_value = apic_read(APIC_TDCR); 362f62bae50SIngo Molnar apic_write(APIC_TDCR, 363f62bae50SIngo Molnar (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 364f62bae50SIngo Molnar APIC_TDR_DIV_16); 365f62bae50SIngo Molnar 366f62bae50SIngo Molnar if (!oneshot) 367f62bae50SIngo Molnar apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 368f62bae50SIngo Molnar } 369f62bae50SIngo Molnar 370f62bae50SIngo Molnar /* 371a68c439bSRobert Richter * Setup extended LVT, AMD specific 372f62bae50SIngo Molnar * 373a68c439bSRobert Richter * Software should use the LVT offsets the BIOS provides. The offsets 374a68c439bSRobert Richter * are determined by the subsystems using it like those for MCE 375a68c439bSRobert Richter * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 376a68c439bSRobert Richter * are supported. Beginning with family 10h at least 4 offsets are 377a68c439bSRobert Richter * available. 378f62bae50SIngo Molnar * 379a68c439bSRobert Richter * Since the offsets must be consistent for all cores, we keep track 380a68c439bSRobert Richter * of the LVT offsets in software and reserve the offset for the same 381a68c439bSRobert Richter * vector also to be used on other cores. An offset is freed by 382a68c439bSRobert Richter * setting the entry to APIC_EILVT_MASKED. 383a68c439bSRobert Richter * 384a68c439bSRobert Richter * If the BIOS is right, there should be no conflicts. Otherwise a 385a68c439bSRobert Richter * "[Firmware Bug]: ..." error message is generated. However, if 386a68c439bSRobert Richter * software does not properly determines the offsets, it is not 387a68c439bSRobert Richter * necessarily a BIOS bug. 388f62bae50SIngo Molnar */ 389f62bae50SIngo Molnar 390a68c439bSRobert Richter static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 391f62bae50SIngo Molnar 392a68c439bSRobert Richter static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 393a68c439bSRobert Richter { 394a68c439bSRobert Richter return (old & APIC_EILVT_MASKED) 395a68c439bSRobert Richter || (new == APIC_EILVT_MASKED) 396a68c439bSRobert Richter || ((new & ~APIC_EILVT_MASKED) == old); 397a68c439bSRobert Richter } 398a68c439bSRobert Richter 399a68c439bSRobert Richter static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 400a68c439bSRobert Richter { 4018abc3122SRobert Richter unsigned int rsvd, vector; 402a68c439bSRobert Richter 403a68c439bSRobert Richter if (offset >= APIC_EILVT_NR_MAX) 404a68c439bSRobert Richter return ~0; 405a68c439bSRobert Richter 4068abc3122SRobert Richter rsvd = atomic_read(&eilvt_offsets[offset]); 407a68c439bSRobert Richter do { 4088abc3122SRobert Richter vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ 4098abc3122SRobert Richter if (vector && !eilvt_entry_is_changeable(vector, new)) 410a68c439bSRobert Richter /* may not change if vectors are different */ 411a68c439bSRobert Richter return rsvd; 412a68c439bSRobert Richter rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 413a68c439bSRobert Richter } while (rsvd != new); 414a68c439bSRobert Richter 4158abc3122SRobert Richter rsvd &= ~APIC_EILVT_MASKED; 4168abc3122SRobert Richter if (rsvd && rsvd != vector) 4178abc3122SRobert Richter pr_info("LVT offset %d assigned for vector 0x%02x\n", 4188abc3122SRobert Richter offset, rsvd); 4198abc3122SRobert Richter 420a68c439bSRobert Richter return new; 421a68c439bSRobert Richter } 422a68c439bSRobert Richter 423a68c439bSRobert Richter /* 424a68c439bSRobert Richter * If mask=1, the LVT entry does not generate interrupts while mask=0 425cbf74ceaSRobert Richter * enables the vector. See also the BKDGs. Must be called with 426cbf74ceaSRobert Richter * preemption disabled. 427a68c439bSRobert Richter */ 428a68c439bSRobert Richter 42927afdf20SRobert Richter int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 430a68c439bSRobert Richter { 431a68c439bSRobert Richter unsigned long reg = APIC_EILVTn(offset); 432a68c439bSRobert Richter unsigned int new, old, reserved; 433a68c439bSRobert Richter 434a68c439bSRobert Richter new = (mask << 16) | (msg_type << 8) | vector; 435a68c439bSRobert Richter old = apic_read(reg); 436a68c439bSRobert Richter reserved = reserve_eilvt_offset(offset, new); 437a68c439bSRobert Richter 438a68c439bSRobert Richter if (reserved != new) { 439eb48c9cbSRobert Richter pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 440eb48c9cbSRobert Richter "vector 0x%x, but the register is already in use for " 441eb48c9cbSRobert Richter "vector 0x%x on another cpu\n", 442eb48c9cbSRobert Richter smp_processor_id(), reg, offset, new, reserved); 443a68c439bSRobert Richter return -EINVAL; 444a68c439bSRobert Richter } 445a68c439bSRobert Richter 446a68c439bSRobert Richter if (!eilvt_entry_is_changeable(old, new)) { 447eb48c9cbSRobert Richter pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 448eb48c9cbSRobert Richter "vector 0x%x, but the register is already in use for " 449eb48c9cbSRobert Richter "vector 0x%x on this cpu\n", 450eb48c9cbSRobert Richter smp_processor_id(), reg, offset, new, old); 451a68c439bSRobert Richter return -EBUSY; 452a68c439bSRobert Richter } 453a68c439bSRobert Richter 454a68c439bSRobert Richter apic_write(reg, new); 455a68c439bSRobert Richter 456a68c439bSRobert Richter return 0; 457f62bae50SIngo Molnar } 45827afdf20SRobert Richter EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 459f62bae50SIngo Molnar 460f62bae50SIngo Molnar /* 461f62bae50SIngo Molnar * Program the next event, relative to now 462f62bae50SIngo Molnar */ 463f62bae50SIngo Molnar static int lapic_next_event(unsigned long delta, 464f62bae50SIngo Molnar struct clock_event_device *evt) 465f62bae50SIngo Molnar { 466f62bae50SIngo Molnar apic_write(APIC_TMICT, delta); 467f62bae50SIngo Molnar return 0; 468f62bae50SIngo Molnar } 469f62bae50SIngo Molnar 470279f1461SSuresh Siddha static int lapic_next_deadline(unsigned long delta, 471279f1461SSuresh Siddha struct clock_event_device *evt) 472279f1461SSuresh Siddha { 473279f1461SSuresh Siddha u64 tsc; 474279f1461SSuresh Siddha 4754ea1636bSAndy Lutomirski tsc = rdtsc(); 476279f1461SSuresh Siddha wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); 477279f1461SSuresh Siddha return 0; 478279f1461SSuresh Siddha } 479279f1461SSuresh Siddha 480b23d8e52SViresh Kumar static int lapic_timer_shutdown(struct clock_event_device *evt) 481f62bae50SIngo Molnar { 482f62bae50SIngo Molnar unsigned int v; 483f62bae50SIngo Molnar 484f62bae50SIngo Molnar /* Lapic used as dummy for broadcast ? */ 485f62bae50SIngo Molnar if (evt->features & CLOCK_EVT_FEAT_DUMMY) 486b23d8e52SViresh Kumar return 0; 487f62bae50SIngo Molnar 488f62bae50SIngo Molnar v = apic_read(APIC_LVTT); 489f62bae50SIngo Molnar v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 490f62bae50SIngo Molnar apic_write(APIC_LVTT, v); 4916f9b4100SAndreas Herrmann apic_write(APIC_TMICT, 0); 492b23d8e52SViresh Kumar return 0; 493f62bae50SIngo Molnar } 494f62bae50SIngo Molnar 495b23d8e52SViresh Kumar static inline int 496b23d8e52SViresh Kumar lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot) 497b23d8e52SViresh Kumar { 498b23d8e52SViresh Kumar /* Lapic used as dummy for broadcast ? */ 499b23d8e52SViresh Kumar if (evt->features & CLOCK_EVT_FEAT_DUMMY) 500b23d8e52SViresh Kumar return 0; 501b23d8e52SViresh Kumar 50252ae346bSDaniel Drake __setup_APIC_LVTT(lapic_timer_period, oneshot, 1); 503b23d8e52SViresh Kumar return 0; 504b23d8e52SViresh Kumar } 505b23d8e52SViresh Kumar 506b23d8e52SViresh Kumar static int lapic_timer_set_periodic(struct clock_event_device *evt) 507b23d8e52SViresh Kumar { 508b23d8e52SViresh Kumar return lapic_timer_set_periodic_oneshot(evt, false); 509b23d8e52SViresh Kumar } 510b23d8e52SViresh Kumar 511b23d8e52SViresh Kumar static int lapic_timer_set_oneshot(struct clock_event_device *evt) 512b23d8e52SViresh Kumar { 513b23d8e52SViresh Kumar return lapic_timer_set_periodic_oneshot(evt, true); 514f62bae50SIngo Molnar } 515f62bae50SIngo Molnar 516f62bae50SIngo Molnar /* 517f62bae50SIngo Molnar * Local APIC timer broadcast function 518f62bae50SIngo Molnar */ 519f62bae50SIngo Molnar static void lapic_timer_broadcast(const struct cpumask *mask) 520f62bae50SIngo Molnar { 521f62bae50SIngo Molnar #ifdef CONFIG_SMP 522f62bae50SIngo Molnar apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 523f62bae50SIngo Molnar #endif 524f62bae50SIngo Molnar } 525f62bae50SIngo Molnar 52625874a29SHenrik Kretzschmar 52725874a29SHenrik Kretzschmar /* 52825874a29SHenrik Kretzschmar * The local apic timer can be used for any function which is CPU local. 52925874a29SHenrik Kretzschmar */ 53025874a29SHenrik Kretzschmar static struct clock_event_device lapic_clockevent = { 53125874a29SHenrik Kretzschmar .name = "lapic", 532b23d8e52SViresh Kumar .features = CLOCK_EVT_FEAT_PERIODIC | 533b23d8e52SViresh Kumar CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP 534b23d8e52SViresh Kumar | CLOCK_EVT_FEAT_DUMMY, 53525874a29SHenrik Kretzschmar .shift = 32, 536b23d8e52SViresh Kumar .set_state_shutdown = lapic_timer_shutdown, 537b23d8e52SViresh Kumar .set_state_periodic = lapic_timer_set_periodic, 538b23d8e52SViresh Kumar .set_state_oneshot = lapic_timer_set_oneshot, 539914122c3SFrederic Weisbecker .set_state_oneshot_stopped = lapic_timer_shutdown, 54025874a29SHenrik Kretzschmar .set_next_event = lapic_next_event, 54125874a29SHenrik Kretzschmar .broadcast = lapic_timer_broadcast, 54225874a29SHenrik Kretzschmar .rating = 100, 54325874a29SHenrik Kretzschmar .irq = -1, 54425874a29SHenrik Kretzschmar }; 54525874a29SHenrik Kretzschmar static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 54625874a29SHenrik Kretzschmar 547c84cb373SThomas Gleixner static const struct x86_cpu_id deadline_match[] __initconst = { 54866abf238SBorislav Petkov X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(HASWELL_X, X86_STEPPINGS(0x2, 0x2), 0x3a), /* EP */ 54966abf238SBorislav Petkov X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(HASWELL_X, X86_STEPPINGS(0x4, 0x4), 0x0f), /* EX */ 55066abf238SBorislav Petkov 551adefe55eSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL( BROADWELL_X, 0x0b000020), 55266abf238SBorislav Petkov 55366abf238SBorislav Petkov X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x2, 0x2), 0x00000011), 55466abf238SBorislav Petkov X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x3, 0x3), 0x0700000e), 55566abf238SBorislav Petkov X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x4, 0x4), 0x0f00000c), 55666abf238SBorislav Petkov X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x5, 0x5), 0x0e000003), 55766abf238SBorislav Petkov 55866abf238SBorislav Petkov X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x3, 0x3), 0x01000136), 55966abf238SBorislav Petkov X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x4, 0x4), 0x02000014), 56066abf238SBorislav Petkov X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x5, 0xf), 0), 561bd9240a1SPeter Zijlstra 562adefe55eSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL( HASWELL, 0x22), 563adefe55eSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL( HASWELL_L, 0x20), 564adefe55eSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL( HASWELL_G, 0x17), 565bd9240a1SPeter Zijlstra 566adefe55eSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL( BROADWELL, 0x25), 567adefe55eSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL( BROADWELL_G, 0x17), 568bd9240a1SPeter Zijlstra 569adefe55eSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL( SKYLAKE_L, 0xb2), 570adefe55eSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL( SKYLAKE, 0xb2), 571bd9240a1SPeter Zijlstra 572adefe55eSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL( KABYLAKE_L, 0x52), 573adefe55eSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL( KABYLAKE, 0x52), 574bd9240a1SPeter Zijlstra 575bd9240a1SPeter Zijlstra {}, 576bd9240a1SPeter Zijlstra }; 577bd9240a1SPeter Zijlstra 578c84cb373SThomas Gleixner static __init bool apic_validate_deadline_timer(void) 579bd9240a1SPeter Zijlstra { 580594a30fbSHans de Goede const struct x86_cpu_id *m; 581bd9240a1SPeter Zijlstra u32 rev; 582bd9240a1SPeter Zijlstra 583c84cb373SThomas Gleixner if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 584c84cb373SThomas Gleixner return false; 585c84cb373SThomas Gleixner if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) 586c84cb373SThomas Gleixner return true; 587594a30fbSHans de Goede 588594a30fbSHans de Goede m = x86_match_cpu(deadline_match); 589bd9240a1SPeter Zijlstra if (!m) 590c84cb373SThomas Gleixner return true; 591bd9240a1SPeter Zijlstra 592bd9240a1SPeter Zijlstra rev = (u32)m->driver_data; 593bd9240a1SPeter Zijlstra 594bd9240a1SPeter Zijlstra if (boot_cpu_data.microcode >= rev) 595c84cb373SThomas Gleixner return true; 596bd9240a1SPeter Zijlstra 597bd9240a1SPeter Zijlstra setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 598bd9240a1SPeter Zijlstra pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; " 599bd9240a1SPeter Zijlstra "please update microcode to version: 0x%x (or later)\n", rev); 600c84cb373SThomas Gleixner return false; 601bd9240a1SPeter Zijlstra } 602bd9240a1SPeter Zijlstra 603f62bae50SIngo Molnar /* 604421f91d2SUwe Kleine-König * Setup the local APIC timer for this CPU. Copy the initialized values 605f62bae50SIngo Molnar * of the boot CPU and register the clock event in the framework. 606f62bae50SIngo Molnar */ 607148f9bb8SPaul Gortmaker static void setup_APIC_timer(void) 608f62bae50SIngo Molnar { 60989cbc767SChristoph Lameter struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 610f62bae50SIngo Molnar 611349c004eSChristoph Lameter if (this_cpu_has(X86_FEATURE_ARAT)) { 612db954b58SVenkatesh Pallipadi lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 613db954b58SVenkatesh Pallipadi /* Make LAPIC timer preferrable over percpu HPET */ 614db954b58SVenkatesh Pallipadi lapic_clockevent.rating = 150; 615db954b58SVenkatesh Pallipadi } 616db954b58SVenkatesh Pallipadi 617f62bae50SIngo Molnar memcpy(levt, &lapic_clockevent, sizeof(*levt)); 618f62bae50SIngo Molnar levt->cpumask = cpumask_of(smp_processor_id()); 619f62bae50SIngo Molnar 620279f1461SSuresh Siddha if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 621c6e9f42bSPeter Zijlstra levt->name = "lapic-deadline"; 622279f1461SSuresh Siddha levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | 623279f1461SSuresh Siddha CLOCK_EVT_FEAT_DUMMY); 624279f1461SSuresh Siddha levt->set_next_event = lapic_next_deadline; 625279f1461SSuresh Siddha clockevents_config_and_register(levt, 6261a9e4c56SNicolai Stange tsc_khz * (1000 / TSC_DIVISOR), 627279f1461SSuresh Siddha 0xF, ~0UL); 628279f1461SSuresh Siddha } else 629f62bae50SIngo Molnar clockevents_register_device(levt); 630f62bae50SIngo Molnar } 631f62bae50SIngo Molnar 632f62bae50SIngo Molnar /* 6336731b0d6SNicolai Stange * Install the updated TSC frequency from recalibration at the TSC 6346731b0d6SNicolai Stange * deadline clockevent devices. 6356731b0d6SNicolai Stange */ 6366731b0d6SNicolai Stange static void __lapic_update_tsc_freq(void *info) 6376731b0d6SNicolai Stange { 6386731b0d6SNicolai Stange struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 6396731b0d6SNicolai Stange 6406731b0d6SNicolai Stange if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 6416731b0d6SNicolai Stange return; 6426731b0d6SNicolai Stange 6436731b0d6SNicolai Stange clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR)); 6446731b0d6SNicolai Stange } 6456731b0d6SNicolai Stange 6466731b0d6SNicolai Stange void lapic_update_tsc_freq(void) 6476731b0d6SNicolai Stange { 6486731b0d6SNicolai Stange /* 6496731b0d6SNicolai Stange * The clockevent device's ->mult and ->shift can both be 6506731b0d6SNicolai Stange * changed. In order to avoid races, schedule the frequency 6516731b0d6SNicolai Stange * update code on each CPU. 6526731b0d6SNicolai Stange */ 6536731b0d6SNicolai Stange on_each_cpu(__lapic_update_tsc_freq, NULL, 0); 6546731b0d6SNicolai Stange } 6556731b0d6SNicolai Stange 6566731b0d6SNicolai Stange /* 657f62bae50SIngo Molnar * In this functions we calibrate APIC bus clocks to the external timer. 658f62bae50SIngo Molnar * 659f62bae50SIngo Molnar * We want to do the calibration only once since we want to have local timer 660f62bae50SIngo Molnar * irqs syncron. CPUs connected by the same APIC bus have the very same bus 661f62bae50SIngo Molnar * frequency. 662f62bae50SIngo Molnar * 663f62bae50SIngo Molnar * This was previously done by reading the PIT/HPET and waiting for a wrap 664f62bae50SIngo Molnar * around to find out, that a tick has elapsed. I have a box, where the PIT 665f62bae50SIngo Molnar * readout is broken, so it never gets out of the wait loop again. This was 666f62bae50SIngo Molnar * also reported by others. 667f62bae50SIngo Molnar * 668f62bae50SIngo Molnar * Monitoring the jiffies value is inaccurate and the clockevents 669f62bae50SIngo Molnar * infrastructure allows us to do a simple substitution of the interrupt 670f62bae50SIngo Molnar * handler. 671f62bae50SIngo Molnar * 672f62bae50SIngo Molnar * The calibration routine also uses the pm_timer when possible, as the PIT 673f62bae50SIngo Molnar * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 674f62bae50SIngo Molnar * back to normal later in the boot process). 675f62bae50SIngo Molnar */ 676f62bae50SIngo Molnar 677f62bae50SIngo Molnar #define LAPIC_CAL_LOOPS (HZ/10) 678f62bae50SIngo Molnar 679f62bae50SIngo Molnar static __initdata int lapic_cal_loops = -1; 680f62bae50SIngo Molnar static __initdata long lapic_cal_t1, lapic_cal_t2; 681f62bae50SIngo Molnar static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 682f62bae50SIngo Molnar static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 683f62bae50SIngo Molnar static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 684f62bae50SIngo Molnar 685f62bae50SIngo Molnar /* 686f897e60aSThomas Gleixner * Temporary interrupt handler and polled calibration function. 687f62bae50SIngo Molnar */ 688f62bae50SIngo Molnar static void __init lapic_cal_handler(struct clock_event_device *dev) 689f62bae50SIngo Molnar { 690f62bae50SIngo Molnar unsigned long long tsc = 0; 691f62bae50SIngo Molnar long tapic = apic_read(APIC_TMCCT); 692f62bae50SIngo Molnar unsigned long pm = acpi_pm_read_early(); 693f62bae50SIngo Molnar 69459e21e3dSBorislav Petkov if (boot_cpu_has(X86_FEATURE_TSC)) 6954ea1636bSAndy Lutomirski tsc = rdtsc(); 696f62bae50SIngo Molnar 697f62bae50SIngo Molnar switch (lapic_cal_loops++) { 698f62bae50SIngo Molnar case 0: 699f62bae50SIngo Molnar lapic_cal_t1 = tapic; 700f62bae50SIngo Molnar lapic_cal_tsc1 = tsc; 701f62bae50SIngo Molnar lapic_cal_pm1 = pm; 702f62bae50SIngo Molnar lapic_cal_j1 = jiffies; 703f62bae50SIngo Molnar break; 704f62bae50SIngo Molnar 705f62bae50SIngo Molnar case LAPIC_CAL_LOOPS: 706f62bae50SIngo Molnar lapic_cal_t2 = tapic; 707f62bae50SIngo Molnar lapic_cal_tsc2 = tsc; 708f62bae50SIngo Molnar if (pm < lapic_cal_pm1) 709f62bae50SIngo Molnar pm += ACPI_PM_OVRRUN; 710f62bae50SIngo Molnar lapic_cal_pm2 = pm; 711f62bae50SIngo Molnar lapic_cal_j2 = jiffies; 712f62bae50SIngo Molnar break; 713f62bae50SIngo Molnar } 714f62bae50SIngo Molnar } 715f62bae50SIngo Molnar 716f62bae50SIngo Molnar static int __init 717f62bae50SIngo Molnar calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 718f62bae50SIngo Molnar { 719f62bae50SIngo Molnar const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 720f62bae50SIngo Molnar const long pm_thresh = pm_100ms / 100; 721f62bae50SIngo Molnar unsigned long mult; 722f62bae50SIngo Molnar u64 res; 723f62bae50SIngo Molnar 724f62bae50SIngo Molnar #ifndef CONFIG_X86_PM_TIMER 725f62bae50SIngo Molnar return -1; 726f62bae50SIngo Molnar #endif 727f62bae50SIngo Molnar 728f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 729f62bae50SIngo Molnar 730f62bae50SIngo Molnar /* Check, if the PM timer is available */ 731f62bae50SIngo Molnar if (!deltapm) 732f62bae50SIngo Molnar return -1; 733f62bae50SIngo Molnar 734f62bae50SIngo Molnar mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 735f62bae50SIngo Molnar 736f62bae50SIngo Molnar if (deltapm > (pm_100ms - pm_thresh) && 737f62bae50SIngo Molnar deltapm < (pm_100ms + pm_thresh)) { 738f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 739f62bae50SIngo Molnar return 0; 740f62bae50SIngo Molnar } 741f62bae50SIngo Molnar 742f62bae50SIngo Molnar res = (((u64)deltapm) * mult) >> 22; 743f62bae50SIngo Molnar do_div(res, 1000000); 7448d3bcc44SKefeng Wang pr_warn("APIC calibration not consistent " 745f62bae50SIngo Molnar "with PM-Timer: %ldms instead of 100ms\n", (long)res); 746f62bae50SIngo Molnar 747f62bae50SIngo Molnar /* Correct the lapic counter value */ 748f62bae50SIngo Molnar res = (((u64)(*delta)) * pm_100ms); 749f62bae50SIngo Molnar do_div(res, deltapm); 750f62bae50SIngo Molnar pr_info("APIC delta adjusted to PM-Timer: " 751f62bae50SIngo Molnar "%lu (%ld)\n", (unsigned long)res, *delta); 752f62bae50SIngo Molnar *delta = (long)res; 753f62bae50SIngo Molnar 754f62bae50SIngo Molnar /* Correct the tsc counter value */ 75559e21e3dSBorislav Petkov if (boot_cpu_has(X86_FEATURE_TSC)) { 756f62bae50SIngo Molnar res = (((u64)(*deltatsc)) * pm_100ms); 757f62bae50SIngo Molnar do_div(res, deltapm); 758f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 759f62bae50SIngo Molnar "PM-Timer: %lu (%ld)\n", 760f62bae50SIngo Molnar (unsigned long)res, *deltatsc); 761f62bae50SIngo Molnar *deltatsc = (long)res; 762f62bae50SIngo Molnar } 763f62bae50SIngo Molnar 764f62bae50SIngo Molnar return 0; 765f62bae50SIngo Molnar } 766f62bae50SIngo Molnar 7676eb4f082SJacob Pan static int __init lapic_init_clockevent(void) 7686eb4f082SJacob Pan { 76952ae346bSDaniel Drake if (!lapic_timer_period) 7706eb4f082SJacob Pan return -1; 7716eb4f082SJacob Pan 7726eb4f082SJacob Pan /* Calculate the scaled math multiplication factor */ 77352ae346bSDaniel Drake lapic_clockevent.mult = div_sc(lapic_timer_period/APIC_DIVISOR, 7746eb4f082SJacob Pan TICK_NSEC, lapic_clockevent.shift); 7756eb4f082SJacob Pan lapic_clockevent.max_delta_ns = 7766eb4f082SJacob Pan clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 7776eb4f082SJacob Pan lapic_clockevent.max_delta_ticks = 0x7FFFFFFF; 7786eb4f082SJacob Pan lapic_clockevent.min_delta_ns = 7796eb4f082SJacob Pan clockevent_delta2ns(0xF, &lapic_clockevent); 7806eb4f082SJacob Pan lapic_clockevent.min_delta_ticks = 0xF; 7816eb4f082SJacob Pan 7826eb4f082SJacob Pan return 0; 7836eb4f082SJacob Pan } 7846eb4f082SJacob Pan 785c8c40767SThomas Gleixner bool __init apic_needs_pit(void) 786c8c40767SThomas Gleixner { 787c8c40767SThomas Gleixner /* 788c8c40767SThomas Gleixner * If the frequencies are not known, PIT is required for both TSC 789c8c40767SThomas Gleixner * and apic timer calibration. 790c8c40767SThomas Gleixner */ 791c8c40767SThomas Gleixner if (!tsc_khz || !cpu_khz) 792c8c40767SThomas Gleixner return true; 793c8c40767SThomas Gleixner 79497992387SThomas Gleixner /* Is there an APIC at all or is it disabled? */ 79597992387SThomas Gleixner if (!boot_cpu_has(X86_FEATURE_APIC) || disable_apic) 79697992387SThomas Gleixner return true; 79797992387SThomas Gleixner 79897992387SThomas Gleixner /* 79997992387SThomas Gleixner * If interrupt delivery mode is legacy PIC or virtual wire without 80097992387SThomas Gleixner * configuration, the local APIC timer wont be set up. Make sure 80197992387SThomas Gleixner * that the PIT is initialized. 80297992387SThomas Gleixner */ 80397992387SThomas Gleixner if (apic_intr_mode == APIC_PIC || 80497992387SThomas Gleixner apic_intr_mode == APIC_VIRTUAL_WIRE_NO_CONFIG) 805c8c40767SThomas Gleixner return true; 806c8c40767SThomas Gleixner 807afa8b475SJan Stancek /* Virt guests may lack ARAT, but still have DEADLINE */ 808afa8b475SJan Stancek if (!boot_cpu_has(X86_FEATURE_ARAT)) 809afa8b475SJan Stancek return true; 810afa8b475SJan Stancek 811c8c40767SThomas Gleixner /* Deadline timer is based on TSC so no further PIT action required */ 812c8c40767SThomas Gleixner if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 813c8c40767SThomas Gleixner return false; 814c8c40767SThomas Gleixner 815c8c40767SThomas Gleixner /* APIC timer disabled? */ 816c8c40767SThomas Gleixner if (disable_apic_timer) 817c8c40767SThomas Gleixner return true; 818c8c40767SThomas Gleixner /* 819c8c40767SThomas Gleixner * The APIC timer frequency is known already, no PIT calibration 820c8c40767SThomas Gleixner * required. If unknown, let the PIT be initialized. 821c8c40767SThomas Gleixner */ 822c8c40767SThomas Gleixner return lapic_timer_period == 0; 823c8c40767SThomas Gleixner } 824c8c40767SThomas Gleixner 825f62bae50SIngo Molnar static int __init calibrate_APIC_clock(void) 826f62bae50SIngo Molnar { 82789cbc767SChristoph Lameter struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 828f897e60aSThomas Gleixner u64 tsc_perj = 0, tsc_start = 0; 829f897e60aSThomas Gleixner unsigned long jif_start; 830f62bae50SIngo Molnar unsigned long deltaj; 831f62bae50SIngo Molnar long delta, deltatsc; 832f62bae50SIngo Molnar int pm_referenced = 0; 833f62bae50SIngo Molnar 8346eb4f082SJacob Pan if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 8356eb4f082SJacob Pan return 0; 8366eb4f082SJacob Pan 8376eb4f082SJacob Pan /* 8386eb4f082SJacob Pan * Check if lapic timer has already been calibrated by platform 8396eb4f082SJacob Pan * specific routine, such as tsc calibration code. If so just fill 8401ade93efSJacob Pan * in the clockevent structure and return. 8411ade93efSJacob Pan */ 8426eb4f082SJacob Pan if (!lapic_init_clockevent()) { 8431ade93efSJacob Pan apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", 84452ae346bSDaniel Drake lapic_timer_period); 8456eb4f082SJacob Pan /* 8466eb4f082SJacob Pan * Direct calibration methods must have an always running 8476eb4f082SJacob Pan * local APIC timer, no need for broadcast timer. 8486eb4f082SJacob Pan */ 8491ade93efSJacob Pan lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 8501ade93efSJacob Pan return 0; 8511ade93efSJacob Pan } 8521ade93efSJacob Pan 853279f1461SSuresh Siddha apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 854279f1461SSuresh Siddha "calibrating APIC timer ...\n"); 855279f1461SSuresh Siddha 856f897e60aSThomas Gleixner /* 857f897e60aSThomas Gleixner * There are platforms w/o global clockevent devices. Instead of 858f897e60aSThomas Gleixner * making the calibration conditional on that, use a polling based 859f897e60aSThomas Gleixner * approach everywhere. 860f897e60aSThomas Gleixner */ 861f62bae50SIngo Molnar local_irq_disable(); 862f62bae50SIngo Molnar 863f62bae50SIngo Molnar /* 864f62bae50SIngo Molnar * Setup the APIC counter to maximum. There is no way the lapic 865f62bae50SIngo Molnar * can underflow in the 100ms detection time frame 866f62bae50SIngo Molnar */ 867f62bae50SIngo Molnar __setup_APIC_LVTT(0xffffffff, 0, 0); 868f62bae50SIngo Molnar 869f897e60aSThomas Gleixner /* 870f897e60aSThomas Gleixner * Methods to terminate the calibration loop: 871f897e60aSThomas Gleixner * 1) Global clockevent if available (jiffies) 872f897e60aSThomas Gleixner * 2) TSC if available and frequency is known 873f897e60aSThomas Gleixner */ 874f897e60aSThomas Gleixner jif_start = READ_ONCE(jiffies); 875f897e60aSThomas Gleixner 876f897e60aSThomas Gleixner if (tsc_khz) { 877f897e60aSThomas Gleixner tsc_start = rdtsc(); 878f897e60aSThomas Gleixner tsc_perj = div_u64((u64)tsc_khz * 1000, HZ); 879f897e60aSThomas Gleixner } 880f897e60aSThomas Gleixner 881f897e60aSThomas Gleixner /* 882f897e60aSThomas Gleixner * Enable interrupts so the tick can fire, if a global 883f897e60aSThomas Gleixner * clockevent device is available 884f897e60aSThomas Gleixner */ 885f62bae50SIngo Molnar local_irq_enable(); 886f62bae50SIngo Molnar 887f897e60aSThomas Gleixner while (lapic_cal_loops <= LAPIC_CAL_LOOPS) { 888f897e60aSThomas Gleixner /* Wait for a tick to elapse */ 889f897e60aSThomas Gleixner while (1) { 890f897e60aSThomas Gleixner if (tsc_khz) { 891f897e60aSThomas Gleixner u64 tsc_now = rdtsc(); 892f897e60aSThomas Gleixner if ((tsc_now - tsc_start) >= tsc_perj) { 893f897e60aSThomas Gleixner tsc_start += tsc_perj; 894f897e60aSThomas Gleixner break; 895f897e60aSThomas Gleixner } 896f897e60aSThomas Gleixner } else { 897f897e60aSThomas Gleixner unsigned long jif_now = READ_ONCE(jiffies); 898f897e60aSThomas Gleixner 899f897e60aSThomas Gleixner if (time_after(jif_now, jif_start)) { 900f897e60aSThomas Gleixner jif_start = jif_now; 901f897e60aSThomas Gleixner break; 902f897e60aSThomas Gleixner } 903f897e60aSThomas Gleixner } 904f62bae50SIngo Molnar cpu_relax(); 905f897e60aSThomas Gleixner } 906f897e60aSThomas Gleixner 907f897e60aSThomas Gleixner /* Invoke the calibration routine */ 908f897e60aSThomas Gleixner local_irq_disable(); 909f897e60aSThomas Gleixner lapic_cal_handler(NULL); 910f897e60aSThomas Gleixner local_irq_enable(); 911f897e60aSThomas Gleixner } 912f62bae50SIngo Molnar 913f62bae50SIngo Molnar local_irq_disable(); 914f62bae50SIngo Molnar 915f62bae50SIngo Molnar /* Build delta t1-t2 as apic timer counts down */ 916f62bae50SIngo Molnar delta = lapic_cal_t1 - lapic_cal_t2; 917f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 918f62bae50SIngo Molnar 919f62bae50SIngo Molnar deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 920f62bae50SIngo Molnar 921f62bae50SIngo Molnar /* we trust the PM based calibration if possible */ 922f62bae50SIngo Molnar pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 923f62bae50SIngo Molnar &delta, &deltatsc); 924f62bae50SIngo Molnar 92552ae346bSDaniel Drake lapic_timer_period = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 9266eb4f082SJacob Pan lapic_init_clockevent(); 927f62bae50SIngo Molnar 928f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 929411462f6SThomas Gleixner apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 930f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 93152ae346bSDaniel Drake lapic_timer_period); 932f62bae50SIngo Molnar 93359e21e3dSBorislav Petkov if (boot_cpu_has(X86_FEATURE_TSC)) { 934f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 935f62bae50SIngo Molnar "%ld.%04ld MHz.\n", 936f62bae50SIngo Molnar (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 937f62bae50SIngo Molnar (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 938f62bae50SIngo Molnar } 939f62bae50SIngo Molnar 940f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 941f62bae50SIngo Molnar "%u.%04u MHz.\n", 94252ae346bSDaniel Drake lapic_timer_period / (1000000 / HZ), 94352ae346bSDaniel Drake lapic_timer_period % (1000000 / HZ)); 944f62bae50SIngo Molnar 945f62bae50SIngo Molnar /* 946f62bae50SIngo Molnar * Do a sanity check on the APIC calibration result 947f62bae50SIngo Molnar */ 94852ae346bSDaniel Drake if (lapic_timer_period < (1000000 / HZ)) { 949f62bae50SIngo Molnar local_irq_enable(); 9508d3bcc44SKefeng Wang pr_warn("APIC frequency too slow, disabling apic timer\n"); 951f62bae50SIngo Molnar return -1; 952f62bae50SIngo Molnar } 953f62bae50SIngo Molnar 954f62bae50SIngo Molnar levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 955f62bae50SIngo Molnar 956f62bae50SIngo Molnar /* 957f897e60aSThomas Gleixner * PM timer calibration failed or not turned on so lets try APIC 958f897e60aSThomas Gleixner * timer based calibration, if a global clockevent device is 959f897e60aSThomas Gleixner * available. 960f62bae50SIngo Molnar */ 961f897e60aSThomas Gleixner if (!pm_referenced && global_clock_event) { 962f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 963f62bae50SIngo Molnar 964f62bae50SIngo Molnar /* 965f62bae50SIngo Molnar * Setup the apic timer manually 966f62bae50SIngo Molnar */ 967f62bae50SIngo Molnar levt->event_handler = lapic_cal_handler; 968b23d8e52SViresh Kumar lapic_timer_set_periodic(levt); 969f62bae50SIngo Molnar lapic_cal_loops = -1; 970f62bae50SIngo Molnar 971f62bae50SIngo Molnar /* Let the interrupts run */ 972f62bae50SIngo Molnar local_irq_enable(); 973f62bae50SIngo Molnar 974f62bae50SIngo Molnar while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 975f62bae50SIngo Molnar cpu_relax(); 976f62bae50SIngo Molnar 977f62bae50SIngo Molnar /* Stop the lapic timer */ 978c948c260SThomas Gleixner local_irq_disable(); 979b23d8e52SViresh Kumar lapic_timer_shutdown(levt); 980f62bae50SIngo Molnar 981f62bae50SIngo Molnar /* Jiffies delta */ 982f62bae50SIngo Molnar deltaj = lapic_cal_j2 - lapic_cal_j1; 983f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 984f62bae50SIngo Molnar 985f62bae50SIngo Molnar /* Check, if the jiffies result is consistent */ 986f62bae50SIngo Molnar if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 987f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 988f62bae50SIngo Molnar else 989f62bae50SIngo Molnar levt->features |= CLOCK_EVT_FEAT_DUMMY; 990c948c260SThomas Gleixner } 991f62bae50SIngo Molnar local_irq_enable(); 992f62bae50SIngo Molnar 993f62bae50SIngo Molnar if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 9948d3bcc44SKefeng Wang pr_warn("APIC timer disabled due to verification failure\n"); 995f62bae50SIngo Molnar return -1; 996f62bae50SIngo Molnar } 997f62bae50SIngo Molnar 998f62bae50SIngo Molnar return 0; 999f62bae50SIngo Molnar } 1000f62bae50SIngo Molnar 1001f62bae50SIngo Molnar /* 1002f62bae50SIngo Molnar * Setup the boot APIC 1003f62bae50SIngo Molnar * 1004f62bae50SIngo Molnar * Calibrate and verify the result. 1005f62bae50SIngo Molnar */ 1006f62bae50SIngo Molnar void __init setup_boot_APIC_clock(void) 1007f62bae50SIngo Molnar { 1008f62bae50SIngo Molnar /* 1009f62bae50SIngo Molnar * The local apic timer can be disabled via the kernel 1010f62bae50SIngo Molnar * commandline or from the CPU detection code. Register the lapic 1011f62bae50SIngo Molnar * timer as a dummy clock event source on SMP systems, so the 1012f62bae50SIngo Molnar * broadcast mechanism is used. On UP systems simply ignore it. 1013f62bae50SIngo Molnar */ 1014f62bae50SIngo Molnar if (disable_apic_timer) { 1015f62bae50SIngo Molnar pr_info("Disabling APIC timer\n"); 1016f62bae50SIngo Molnar /* No broadcast on UP ! */ 1017f62bae50SIngo Molnar if (num_possible_cpus() > 1) { 1018f62bae50SIngo Molnar lapic_clockevent.mult = 1; 1019f62bae50SIngo Molnar setup_APIC_timer(); 1020f62bae50SIngo Molnar } 1021f62bae50SIngo Molnar return; 1022f62bae50SIngo Molnar } 1023f62bae50SIngo Molnar 1024f62bae50SIngo Molnar if (calibrate_APIC_clock()) { 1025f62bae50SIngo Molnar /* No broadcast on UP ! */ 1026f62bae50SIngo Molnar if (num_possible_cpus() > 1) 1027f62bae50SIngo Molnar setup_APIC_timer(); 1028f62bae50SIngo Molnar return; 1029f62bae50SIngo Molnar } 1030f62bae50SIngo Molnar 1031f62bae50SIngo Molnar /* 1032f62bae50SIngo Molnar * If nmi_watchdog is set to IO_APIC, we need the 1033f62bae50SIngo Molnar * PIT/HPET going. Otherwise register lapic as a dummy 1034f62bae50SIngo Molnar * device. 1035f62bae50SIngo Molnar */ 1036f62bae50SIngo Molnar lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 1037f62bae50SIngo Molnar 1038f62bae50SIngo Molnar /* Setup the lapic or request the broadcast */ 1039f62bae50SIngo Molnar setup_APIC_timer(); 104007c94a38SBorislav Petkov amd_e400_c1e_apic_setup(); 1041f62bae50SIngo Molnar } 1042f62bae50SIngo Molnar 1043148f9bb8SPaul Gortmaker void setup_secondary_APIC_clock(void) 1044f62bae50SIngo Molnar { 1045f62bae50SIngo Molnar setup_APIC_timer(); 104607c94a38SBorislav Petkov amd_e400_c1e_apic_setup(); 1047f62bae50SIngo Molnar } 1048f62bae50SIngo Molnar 1049f62bae50SIngo Molnar /* 1050f62bae50SIngo Molnar * The guts of the apic timer interrupt 1051f62bae50SIngo Molnar */ 1052f62bae50SIngo Molnar static void local_apic_timer_interrupt(void) 1053f62bae50SIngo Molnar { 10543bec6defSThomas Gleixner struct clock_event_device *evt = this_cpu_ptr(&lapic_events); 1055f62bae50SIngo Molnar 1056f62bae50SIngo Molnar /* 1057f62bae50SIngo Molnar * Normally we should not be here till LAPIC has been initialized but 1058f62bae50SIngo Molnar * in some cases like kdump, its possible that there is a pending LAPIC 1059f62bae50SIngo Molnar * timer interrupt from previous kernel's context and is delivered in 1060f62bae50SIngo Molnar * new kernel the moment interrupts are enabled. 1061f62bae50SIngo Molnar * 1062f62bae50SIngo Molnar * Interrupts are enabled early and LAPIC is setup much later, hence 1063f62bae50SIngo Molnar * its possible that when we get here evt->event_handler is NULL. 1064f62bae50SIngo Molnar * Check for event_handler being NULL and discard the interrupt as 1065f62bae50SIngo Molnar * spurious. 1066f62bae50SIngo Molnar */ 1067f62bae50SIngo Molnar if (!evt->event_handler) { 10688d3bcc44SKefeng Wang pr_warn("Spurious LAPIC timer interrupt on cpu %d\n", 10693bec6defSThomas Gleixner smp_processor_id()); 1070f62bae50SIngo Molnar /* Switch it off */ 1071b23d8e52SViresh Kumar lapic_timer_shutdown(evt); 1072f62bae50SIngo Molnar return; 1073f62bae50SIngo Molnar } 1074f62bae50SIngo Molnar 1075f62bae50SIngo Molnar /* 1076f62bae50SIngo Molnar * the NMI deadlock-detector uses this. 1077f62bae50SIngo Molnar */ 1078f62bae50SIngo Molnar inc_irq_stat(apic_timer_irqs); 1079f62bae50SIngo Molnar 1080f62bae50SIngo Molnar evt->event_handler(evt); 1081f62bae50SIngo Molnar } 1082f62bae50SIngo Molnar 1083f62bae50SIngo Molnar /* 1084f62bae50SIngo Molnar * Local APIC timer interrupt. This is the most natural way for doing 1085f62bae50SIngo Molnar * local interrupts, but local timer interrupts can be emulated by 1086f62bae50SIngo Molnar * broadcast interrupts too. [in case the hw doesn't support APIC timers] 1087f62bae50SIngo Molnar * 1088f62bae50SIngo Molnar * [ if a single-CPU system runs an SMP kernel then we call the local 1089f62bae50SIngo Molnar * interrupt as well. Thus we cannot inline the local irq ... ] 1090f62bae50SIngo Molnar */ 1091db0338eeSThomas Gleixner DEFINE_IDTENTRY_SYSVEC(sysvec_apic_timer_interrupt) 1092f62bae50SIngo Molnar { 1093f62bae50SIngo Molnar struct pt_regs *old_regs = set_irq_regs(regs); 1094f62bae50SIngo Molnar 1095db0338eeSThomas Gleixner ack_APIC_irq(); 1096cf910e83SSeiji Aguchi trace_local_timer_entry(LOCAL_TIMER_VECTOR); 1097cf910e83SSeiji Aguchi local_apic_timer_interrupt(); 1098cf910e83SSeiji Aguchi trace_local_timer_exit(LOCAL_TIMER_VECTOR); 1099f62bae50SIngo Molnar 1100f62bae50SIngo Molnar set_irq_regs(old_regs); 1101f62bae50SIngo Molnar } 1102f62bae50SIngo Molnar 1103f62bae50SIngo Molnar int setup_profiling_timer(unsigned int multiplier) 1104f62bae50SIngo Molnar { 1105f62bae50SIngo Molnar return -EINVAL; 1106f62bae50SIngo Molnar } 1107f62bae50SIngo Molnar 1108f62bae50SIngo Molnar /* 1109f62bae50SIngo Molnar * Local APIC start and shutdown 1110f62bae50SIngo Molnar */ 1111f62bae50SIngo Molnar 1112f62bae50SIngo Molnar /** 1113f62bae50SIngo Molnar * clear_local_APIC - shutdown the local APIC 1114f62bae50SIngo Molnar * 1115f62bae50SIngo Molnar * This is called, when a CPU is disabled and before rebooting, so the state of 1116f62bae50SIngo Molnar * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 1117f62bae50SIngo Molnar * leftovers during boot. 1118f62bae50SIngo Molnar */ 1119f62bae50SIngo Molnar void clear_local_APIC(void) 1120f62bae50SIngo Molnar { 1121f62bae50SIngo Molnar int maxlvt; 1122f62bae50SIngo Molnar u32 v; 1123f62bae50SIngo Molnar 1124f62bae50SIngo Molnar /* APIC hasn't been mapped yet */ 1125fc1edaf9SSuresh Siddha if (!x2apic_mode && !apic_phys) 1126f62bae50SIngo Molnar return; 1127f62bae50SIngo Molnar 1128f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 1129f62bae50SIngo Molnar /* 1130f62bae50SIngo Molnar * Masking an LVT entry can trigger a local APIC error 1131f62bae50SIngo Molnar * if the vector is zero. Mask LVTERR first to prevent this. 1132f62bae50SIngo Molnar */ 1133f62bae50SIngo Molnar if (maxlvt >= 3) { 1134f62bae50SIngo Molnar v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 1135f62bae50SIngo Molnar apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 1136f62bae50SIngo Molnar } 1137f62bae50SIngo Molnar /* 1138f62bae50SIngo Molnar * Careful: we have to set masks only first to deassert 1139f62bae50SIngo Molnar * any level-triggered sources. 1140f62bae50SIngo Molnar */ 1141f62bae50SIngo Molnar v = apic_read(APIC_LVTT); 1142f62bae50SIngo Molnar apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 1143f62bae50SIngo Molnar v = apic_read(APIC_LVT0); 1144f62bae50SIngo Molnar apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 1145f62bae50SIngo Molnar v = apic_read(APIC_LVT1); 1146f62bae50SIngo Molnar apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 1147f62bae50SIngo Molnar if (maxlvt >= 4) { 1148f62bae50SIngo Molnar v = apic_read(APIC_LVTPC); 1149f62bae50SIngo Molnar apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 1150f62bae50SIngo Molnar } 1151f62bae50SIngo Molnar 1152f62bae50SIngo Molnar /* lets not touch this if we didn't frob it */ 11534efc0670SAndi Kleen #ifdef CONFIG_X86_THERMAL_VECTOR 1154f62bae50SIngo Molnar if (maxlvt >= 5) { 1155f62bae50SIngo Molnar v = apic_read(APIC_LVTTHMR); 1156f62bae50SIngo Molnar apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 1157f62bae50SIngo Molnar } 1158f62bae50SIngo Molnar #endif 1159638bee71SH. Peter Anvin #ifdef CONFIG_X86_MCE_INTEL 1160638bee71SH. Peter Anvin if (maxlvt >= 6) { 1161638bee71SH. Peter Anvin v = apic_read(APIC_LVTCMCI); 1162638bee71SH. Peter Anvin if (!(v & APIC_LVT_MASKED)) 1163638bee71SH. Peter Anvin apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 1164638bee71SH. Peter Anvin } 1165638bee71SH. Peter Anvin #endif 1166638bee71SH. Peter Anvin 1167f62bae50SIngo Molnar /* 1168f62bae50SIngo Molnar * Clean APIC state for other OSs: 1169f62bae50SIngo Molnar */ 1170f62bae50SIngo Molnar apic_write(APIC_LVTT, APIC_LVT_MASKED); 1171f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_LVT_MASKED); 1172f62bae50SIngo Molnar apic_write(APIC_LVT1, APIC_LVT_MASKED); 1173f62bae50SIngo Molnar if (maxlvt >= 3) 1174f62bae50SIngo Molnar apic_write(APIC_LVTERR, APIC_LVT_MASKED); 1175f62bae50SIngo Molnar if (maxlvt >= 4) 1176f62bae50SIngo Molnar apic_write(APIC_LVTPC, APIC_LVT_MASKED); 1177f62bae50SIngo Molnar 1178f62bae50SIngo Molnar /* Integrated APIC (!82489DX) ? */ 1179f62bae50SIngo Molnar if (lapic_is_integrated()) { 1180f62bae50SIngo Molnar if (maxlvt > 3) 1181f62bae50SIngo Molnar /* Clear ESR due to Pentium errata 3AP and 11AP */ 1182f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1183f62bae50SIngo Molnar apic_read(APIC_ESR); 1184f62bae50SIngo Molnar } 1185f62bae50SIngo Molnar } 1186f62bae50SIngo Molnar 1187f62bae50SIngo Molnar /** 118860dcaad5SThomas Gleixner * apic_soft_disable - Clears and software disables the local APIC on hotplug 118960dcaad5SThomas Gleixner * 119060dcaad5SThomas Gleixner * Contrary to disable_local_APIC() this does not touch the enable bit in 119160dcaad5SThomas Gleixner * MSR_IA32_APICBASE. Clearing that bit on systems based on the 3 wire APIC 119260dcaad5SThomas Gleixner * bus would require a hardware reset as the APIC would lose track of bus 119360dcaad5SThomas Gleixner * arbitration. On systems with FSB delivery APICBASE could be disabled, 119460dcaad5SThomas Gleixner * but it has to be guaranteed that no interrupt is sent to the APIC while 119560dcaad5SThomas Gleixner * in that state and it's not clear from the SDM whether it still responds 119660dcaad5SThomas Gleixner * to INIT/SIPI messages. Stay on the safe side and use software disable. 119760dcaad5SThomas Gleixner */ 119860dcaad5SThomas Gleixner void apic_soft_disable(void) 119960dcaad5SThomas Gleixner { 120060dcaad5SThomas Gleixner u32 value; 120160dcaad5SThomas Gleixner 120260dcaad5SThomas Gleixner clear_local_APIC(); 120360dcaad5SThomas Gleixner 120460dcaad5SThomas Gleixner /* Soft disable APIC (implies clearing of registers for 82489DX!). */ 120560dcaad5SThomas Gleixner value = apic_read(APIC_SPIV); 120660dcaad5SThomas Gleixner value &= ~APIC_SPIV_APIC_ENABLED; 120760dcaad5SThomas Gleixner apic_write(APIC_SPIV, value); 120860dcaad5SThomas Gleixner } 120960dcaad5SThomas Gleixner 121060dcaad5SThomas Gleixner /** 1211f62bae50SIngo Molnar * disable_local_APIC - clear and disable the local APIC 1212f62bae50SIngo Molnar */ 1213f62bae50SIngo Molnar void disable_local_APIC(void) 1214f62bae50SIngo Molnar { 1215f62bae50SIngo Molnar /* APIC hasn't been mapped yet */ 1216fd19dce7SYinghai Lu if (!x2apic_mode && !apic_phys) 1217f62bae50SIngo Molnar return; 1218f62bae50SIngo Molnar 121960dcaad5SThomas Gleixner apic_soft_disable(); 1220f62bae50SIngo Molnar 1221f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1222f62bae50SIngo Molnar /* 1223f62bae50SIngo Molnar * When LAPIC was disabled by the BIOS and enabled by the kernel, 1224f62bae50SIngo Molnar * restore the disabled state. 1225f62bae50SIngo Molnar */ 1226f62bae50SIngo Molnar if (enabled_via_apicbase) { 1227f62bae50SIngo Molnar unsigned int l, h; 1228f62bae50SIngo Molnar 1229f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, l, h); 1230f62bae50SIngo Molnar l &= ~MSR_IA32_APICBASE_ENABLE; 1231f62bae50SIngo Molnar wrmsr(MSR_IA32_APICBASE, l, h); 1232f62bae50SIngo Molnar } 1233f62bae50SIngo Molnar #endif 1234f62bae50SIngo Molnar } 1235f62bae50SIngo Molnar 1236f62bae50SIngo Molnar /* 1237f62bae50SIngo Molnar * If Linux enabled the LAPIC against the BIOS default disable it down before 1238f62bae50SIngo Molnar * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 1239f62bae50SIngo Molnar * not power-off. Additionally clear all LVT entries before disable_local_APIC 1240f62bae50SIngo Molnar * for the case where Linux didn't enable the LAPIC. 1241f62bae50SIngo Molnar */ 1242f62bae50SIngo Molnar void lapic_shutdown(void) 1243f62bae50SIngo Molnar { 1244f62bae50SIngo Molnar unsigned long flags; 1245f62bae50SIngo Molnar 124693984fbdSBorislav Petkov if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) 1247f62bae50SIngo Molnar return; 1248f62bae50SIngo Molnar 1249f62bae50SIngo Molnar local_irq_save(flags); 1250f62bae50SIngo Molnar 1251f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1252f62bae50SIngo Molnar if (!enabled_via_apicbase) 1253f62bae50SIngo Molnar clear_local_APIC(); 1254f62bae50SIngo Molnar else 1255f62bae50SIngo Molnar #endif 1256f62bae50SIngo Molnar disable_local_APIC(); 1257f62bae50SIngo Molnar 1258f62bae50SIngo Molnar 1259f62bae50SIngo Molnar local_irq_restore(flags); 1260f62bae50SIngo Molnar } 1261f62bae50SIngo Molnar 1262f62bae50SIngo Molnar /** 1263f62bae50SIngo Molnar * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1264f62bae50SIngo Molnar */ 1265f62bae50SIngo Molnar void __init sync_Arb_IDs(void) 1266f62bae50SIngo Molnar { 1267f62bae50SIngo Molnar /* 1268f62bae50SIngo Molnar * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1269f62bae50SIngo Molnar * needed on AMD. 1270f62bae50SIngo Molnar */ 1271f62bae50SIngo Molnar if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1272f62bae50SIngo Molnar return; 1273f62bae50SIngo Molnar 1274f62bae50SIngo Molnar /* 1275f62bae50SIngo Molnar * Wait for idle. 1276f62bae50SIngo Molnar */ 1277f62bae50SIngo Molnar apic_wait_icr_idle(); 1278f62bae50SIngo Molnar 1279f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1280f62bae50SIngo Molnar apic_write(APIC_ICR, APIC_DEST_ALLINC | 1281f62bae50SIngo Molnar APIC_INT_LEVELTRIG | APIC_DM_INIT); 1282f62bae50SIngo Molnar } 1283f62bae50SIngo Molnar 12846444b40eSSean Christopherson enum apic_intr_mode_id apic_intr_mode __ro_after_init; 12850114a8e8SDou Liyang 128697992387SThomas Gleixner static int __init __apic_intr_mode_select(void) 1287f62bae50SIngo Molnar { 12880114a8e8SDou Liyang /* Check kernel option */ 12890114a8e8SDou Liyang if (disable_apic) { 12900114a8e8SDou Liyang pr_info("APIC disabled via kernel command line\n"); 12910114a8e8SDou Liyang return APIC_PIC; 12920114a8e8SDou Liyang } 1293f62bae50SIngo Molnar 12940114a8e8SDou Liyang /* Check BIOS */ 12950114a8e8SDou Liyang #ifdef CONFIG_X86_64 12960114a8e8SDou Liyang /* On 64-bit, the APIC must be integrated, Check local APIC only */ 12970114a8e8SDou Liyang if (!boot_cpu_has(X86_FEATURE_APIC)) { 12980114a8e8SDou Liyang disable_apic = 1; 12990114a8e8SDou Liyang pr_info("APIC disabled by BIOS\n"); 13000114a8e8SDou Liyang return APIC_PIC; 13010114a8e8SDou Liyang } 13020114a8e8SDou Liyang #else 13030114a8e8SDou Liyang /* On 32-bit, the APIC may be integrated APIC or 82489DX */ 1304f62bae50SIngo Molnar 13050114a8e8SDou Liyang /* Neither 82489DX nor integrated APIC ? */ 13060114a8e8SDou Liyang if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) { 13070114a8e8SDou Liyang disable_apic = 1; 13080114a8e8SDou Liyang return APIC_PIC; 13090114a8e8SDou Liyang } 1310f62bae50SIngo Molnar 13110114a8e8SDou Liyang /* If the BIOS pretends there is an integrated APIC ? */ 13120114a8e8SDou Liyang if (!boot_cpu_has(X86_FEATURE_APIC) && 13130114a8e8SDou Liyang APIC_INTEGRATED(boot_cpu_apic_version)) { 13140114a8e8SDou Liyang disable_apic = 1; 13150114a8e8SDou Liyang pr_err(FW_BUG "Local APIC %d not detected, force emulation\n", 13160114a8e8SDou Liyang boot_cpu_physical_apicid); 13170114a8e8SDou Liyang return APIC_PIC; 13180114a8e8SDou Liyang } 1319f62bae50SIngo Molnar #endif 1320f62bae50SIngo Molnar 13210114a8e8SDou Liyang /* Check MP table or ACPI MADT configuration */ 13220114a8e8SDou Liyang if (!smp_found_config) { 13230114a8e8SDou Liyang disable_ioapic_support(); 13243e730dadSDou Liyang if (!acpi_lapic) { 13250114a8e8SDou Liyang pr_info("APIC: ACPI MADT or MP tables are not detected\n"); 13263e730dadSDou Liyang return APIC_VIRTUAL_WIRE_NO_CONFIG; 13273e730dadSDou Liyang } 13280114a8e8SDou Liyang return APIC_VIRTUAL_WIRE; 13290114a8e8SDou Liyang } 13300114a8e8SDou Liyang 13313e730dadSDou Liyang #ifdef CONFIG_SMP 13323e730dadSDou Liyang /* If SMP should be disabled, then really disable it! */ 13333e730dadSDou Liyang if (!setup_max_cpus) { 13343e730dadSDou Liyang pr_info("APIC: SMP mode deactivated\n"); 13353e730dadSDou Liyang return APIC_SYMMETRIC_IO_NO_ROUTING; 13363e730dadSDou Liyang } 13373e730dadSDou Liyang 13383e730dadSDou Liyang if (read_apic_id() != boot_cpu_physical_apicid) { 13393e730dadSDou Liyang panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 13403e730dadSDou Liyang read_apic_id(), boot_cpu_physical_apicid); 13413e730dadSDou Liyang /* Or can we switch back to PIC here? */ 13423e730dadSDou Liyang } 13433e730dadSDou Liyang #endif 13443e730dadSDou Liyang 13450114a8e8SDou Liyang return APIC_SYMMETRIC_IO; 13460114a8e8SDou Liyang } 13470114a8e8SDou Liyang 134897992387SThomas Gleixner /* Select the interrupt delivery mode for the BSP */ 134997992387SThomas Gleixner void __init apic_intr_mode_select(void) 135097992387SThomas Gleixner { 135197992387SThomas Gleixner apic_intr_mode = __apic_intr_mode_select(); 135297992387SThomas Gleixner } 135397992387SThomas Gleixner 1354fc90ccfdSVille Syrjälä /* 1355fc90ccfdSVille Syrjälä * An initial setup of the virtual wire mode. 1356fc90ccfdSVille Syrjälä */ 1357fc90ccfdSVille Syrjälä void __init init_bsp_APIC(void) 1358fc90ccfdSVille Syrjälä { 1359fc90ccfdSVille Syrjälä unsigned int value; 1360fc90ccfdSVille Syrjälä 1361fc90ccfdSVille Syrjälä /* 1362fc90ccfdSVille Syrjälä * Don't do the setup now if we have a SMP BIOS as the 1363fc90ccfdSVille Syrjälä * through-I/O-APIC virtual wire mode might be active. 1364fc90ccfdSVille Syrjälä */ 1365fc90ccfdSVille Syrjälä if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC)) 1366fc90ccfdSVille Syrjälä return; 1367fc90ccfdSVille Syrjälä 1368fc90ccfdSVille Syrjälä /* 1369fc90ccfdSVille Syrjälä * Do not trust the local APIC being empty at bootup. 1370fc90ccfdSVille Syrjälä */ 1371fc90ccfdSVille Syrjälä clear_local_APIC(); 1372fc90ccfdSVille Syrjälä 1373fc90ccfdSVille Syrjälä /* 1374fc90ccfdSVille Syrjälä * Enable APIC. 1375fc90ccfdSVille Syrjälä */ 1376fc90ccfdSVille Syrjälä value = apic_read(APIC_SPIV); 1377fc90ccfdSVille Syrjälä value &= ~APIC_VECTOR_MASK; 1378fc90ccfdSVille Syrjälä value |= APIC_SPIV_APIC_ENABLED; 1379fc90ccfdSVille Syrjälä 1380fc90ccfdSVille Syrjälä #ifdef CONFIG_X86_32 1381fc90ccfdSVille Syrjälä /* This bit is reserved on P4/Xeon and should be cleared */ 1382fc90ccfdSVille Syrjälä if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1383fc90ccfdSVille Syrjälä (boot_cpu_data.x86 == 15)) 1384fc90ccfdSVille Syrjälä value &= ~APIC_SPIV_FOCUS_DISABLED; 1385fc90ccfdSVille Syrjälä else 1386fc90ccfdSVille Syrjälä #endif 1387fc90ccfdSVille Syrjälä value |= APIC_SPIV_FOCUS_DISABLED; 1388fc90ccfdSVille Syrjälä value |= SPURIOUS_APIC_VECTOR; 1389fc90ccfdSVille Syrjälä apic_write(APIC_SPIV, value); 1390fc90ccfdSVille Syrjälä 1391fc90ccfdSVille Syrjälä /* 1392fc90ccfdSVille Syrjälä * Set up the virtual wire mode. 1393fc90ccfdSVille Syrjälä */ 1394fc90ccfdSVille Syrjälä apic_write(APIC_LVT0, APIC_DM_EXTINT); 1395fc90ccfdSVille Syrjälä value = APIC_DM_NMI; 1396fc90ccfdSVille Syrjälä if (!lapic_is_integrated()) /* 82489DX */ 1397fc90ccfdSVille Syrjälä value |= APIC_LVT_LEVEL_TRIGGER; 1398fc90ccfdSVille Syrjälä if (apic_extnmi == APIC_EXTNMI_NONE) 1399fc90ccfdSVille Syrjälä value |= APIC_LVT_MASKED; 1400fc90ccfdSVille Syrjälä apic_write(APIC_LVT1, value); 1401fc90ccfdSVille Syrjälä } 1402fc90ccfdSVille Syrjälä 1403748b170cSThomas Gleixner static void __init apic_bsp_setup(bool upmode); 1404748b170cSThomas Gleixner 14054b1669e8SDou Liyang /* Init the interrupt delivery mode for the BSP */ 14064b1669e8SDou Liyang void __init apic_intr_mode_init(void) 14074b1669e8SDou Liyang { 14080c759131SDou Liyang bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT); 14093e730dadSDou Liyang 14104f45ed9fSDou Liyang switch (apic_intr_mode) { 14114b1669e8SDou Liyang case APIC_PIC: 14124b1669e8SDou Liyang pr_info("APIC: Keep in PIC mode(8259)\n"); 14134b1669e8SDou Liyang return; 14144b1669e8SDou Liyang case APIC_VIRTUAL_WIRE: 14154b1669e8SDou Liyang pr_info("APIC: Switch to virtual wire mode setup\n"); 14163e730dadSDou Liyang default_setup_apic_routing(); 14173e730dadSDou Liyang break; 14183e730dadSDou Liyang case APIC_VIRTUAL_WIRE_NO_CONFIG: 14193e730dadSDou Liyang pr_info("APIC: Switch to virtual wire mode setup with no configuration\n"); 14203e730dadSDou Liyang upmode = true; 14213e730dadSDou Liyang default_setup_apic_routing(); 14223e730dadSDou Liyang break; 14234b1669e8SDou Liyang case APIC_SYMMETRIC_IO: 142479761ce8SColin Ian King pr_info("APIC: Switch to symmetric I/O mode setup\n"); 14253e730dadSDou Liyang default_setup_apic_routing(); 14263e730dadSDou Liyang break; 14273e730dadSDou Liyang case APIC_SYMMETRIC_IO_NO_ROUTING: 142879761ce8SColin Ian King pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n"); 14293e730dadSDou Liyang break; 14304b1669e8SDou Liyang } 14313e730dadSDou Liyang 1432bb733e43SThomas Gleixner if (x86_platform.apic_post_init) 1433bb733e43SThomas Gleixner x86_platform.apic_post_init(); 1434bb733e43SThomas Gleixner 14353e730dadSDou Liyang apic_bsp_setup(upmode); 1436f62bae50SIngo Molnar } 1437f62bae50SIngo Molnar 1438148f9bb8SPaul Gortmaker static void lapic_setup_esr(void) 1439f62bae50SIngo Molnar { 1440f62bae50SIngo Molnar unsigned int oldvalue, value, maxlvt; 1441f62bae50SIngo Molnar 1442f62bae50SIngo Molnar if (!lapic_is_integrated()) { 1443f62bae50SIngo Molnar pr_info("No ESR for 82489DX.\n"); 1444f62bae50SIngo Molnar return; 1445f62bae50SIngo Molnar } 1446f62bae50SIngo Molnar 1447f62bae50SIngo Molnar if (apic->disable_esr) { 1448f62bae50SIngo Molnar /* 1449f62bae50SIngo Molnar * Something untraceable is creating bad interrupts on 1450f62bae50SIngo Molnar * secondary quads ... for the moment, just leave the 1451f62bae50SIngo Molnar * ESR disabled - we can't do anything useful with the 1452f62bae50SIngo Molnar * errors anyway - mbligh 1453f62bae50SIngo Molnar */ 1454f62bae50SIngo Molnar pr_info("Leaving ESR disabled.\n"); 1455f62bae50SIngo Molnar return; 1456f62bae50SIngo Molnar } 1457f62bae50SIngo Molnar 1458f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 1459f62bae50SIngo Molnar if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1460f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1461f62bae50SIngo Molnar oldvalue = apic_read(APIC_ESR); 1462f62bae50SIngo Molnar 1463f62bae50SIngo Molnar /* enables sending errors */ 1464f62bae50SIngo Molnar value = ERROR_APIC_VECTOR; 1465f62bae50SIngo Molnar apic_write(APIC_LVTERR, value); 1466f62bae50SIngo Molnar 1467f62bae50SIngo Molnar /* 1468f62bae50SIngo Molnar * spec says clear errors after enabling vector. 1469f62bae50SIngo Molnar */ 1470f62bae50SIngo Molnar if (maxlvt > 3) 1471f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1472f62bae50SIngo Molnar value = apic_read(APIC_ESR); 1473f62bae50SIngo Molnar if (value != oldvalue) 1474f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "ESR value before enabling " 1475f62bae50SIngo Molnar "vector: 0x%08x after: 0x%08x\n", 1476f62bae50SIngo Molnar oldvalue, value); 1477f62bae50SIngo Molnar } 1478f62bae50SIngo Molnar 1479cc8bf191SThomas Gleixner #define APIC_IR_REGS APIC_ISR_NR 1480cc8bf191SThomas Gleixner #define APIC_IR_BITS (APIC_IR_REGS * 32) 1481cc8bf191SThomas Gleixner #define APIC_IR_MAPSIZE (APIC_IR_BITS / BITS_PER_LONG) 14829b217f33SDou Liyang 1483cc8bf191SThomas Gleixner union apic_ir { 1484cc8bf191SThomas Gleixner unsigned long map[APIC_IR_MAPSIZE]; 1485cc8bf191SThomas Gleixner u32 regs[APIC_IR_REGS]; 1486cc8bf191SThomas Gleixner }; 1487cc8bf191SThomas Gleixner 1488cc8bf191SThomas Gleixner static bool apic_check_and_ack(union apic_ir *irr, union apic_ir *isr) 1489cc8bf191SThomas Gleixner { 1490cc8bf191SThomas Gleixner int i, bit; 1491cc8bf191SThomas Gleixner 1492cc8bf191SThomas Gleixner /* Read the IRRs */ 1493cc8bf191SThomas Gleixner for (i = 0; i < APIC_IR_REGS; i++) 1494cc8bf191SThomas Gleixner irr->regs[i] = apic_read(APIC_IRR + i * 0x10); 1495cc8bf191SThomas Gleixner 1496cc8bf191SThomas Gleixner /* Read the ISRs */ 1497cc8bf191SThomas Gleixner for (i = 0; i < APIC_IR_REGS; i++) 1498cc8bf191SThomas Gleixner isr->regs[i] = apic_read(APIC_ISR + i * 0x10); 1499cc8bf191SThomas Gleixner 1500cc8bf191SThomas Gleixner /* 1501cc8bf191SThomas Gleixner * If the ISR map is not empty. ACK the APIC and run another round 1502cc8bf191SThomas Gleixner * to verify whether a pending IRR has been unblocked and turned 1503cc8bf191SThomas Gleixner * into a ISR. 1504cc8bf191SThomas Gleixner */ 1505cc8bf191SThomas Gleixner if (!bitmap_empty(isr->map, APIC_IR_BITS)) { 1506cc8bf191SThomas Gleixner /* 1507cc8bf191SThomas Gleixner * There can be multiple ISR bits set when a high priority 1508cc8bf191SThomas Gleixner * interrupt preempted a lower priority one. Issue an ACK 1509cc8bf191SThomas Gleixner * per set bit. 1510cc8bf191SThomas Gleixner */ 1511cc8bf191SThomas Gleixner for_each_set_bit(bit, isr->map, APIC_IR_BITS) 1512cc8bf191SThomas Gleixner ack_APIC_irq(); 1513cc8bf191SThomas Gleixner return true; 1514cc8bf191SThomas Gleixner } 1515cc8bf191SThomas Gleixner 1516cc8bf191SThomas Gleixner return !bitmap_empty(irr->map, APIC_IR_BITS); 1517cc8bf191SThomas Gleixner } 1518cc8bf191SThomas Gleixner 15199b217f33SDou Liyang /* 15209b217f33SDou Liyang * After a crash, we no longer service the interrupts and a pending 15219b217f33SDou Liyang * interrupt from previous kernel might still have ISR bit set. 15229b217f33SDou Liyang * 1523cc8bf191SThomas Gleixner * Most probably by now the CPU has serviced that pending interrupt and it 1524cc8bf191SThomas Gleixner * might not have done the ack_APIC_irq() because it thought, interrupt 1525cc8bf191SThomas Gleixner * came from i8259 as ExtInt. LAPIC did not get EOI so it does not clear 1526cc8bf191SThomas Gleixner * the ISR bit and cpu thinks it has already serivced the interrupt. Hence 1527cc8bf191SThomas Gleixner * a vector might get locked. It was noticed for timer irq (vector 1528cc8bf191SThomas Gleixner * 0x31). Issue an extra EOI to clear ISR. 1529cc8bf191SThomas Gleixner * 1530cc8bf191SThomas Gleixner * If there are pending IRR bits they turn into ISR bits after a higher 1531cc8bf191SThomas Gleixner * priority ISR bit has been acked. 15329b217f33SDou Liyang */ 1533cc8bf191SThomas Gleixner static void apic_pending_intr_clear(void) 1534cc8bf191SThomas Gleixner { 1535cc8bf191SThomas Gleixner union apic_ir irr, isr; 1536cc8bf191SThomas Gleixner unsigned int i; 15379b217f33SDou Liyang 1538cc8bf191SThomas Gleixner /* 512 loops are way oversized and give the APIC a chance to obey. */ 1539cc8bf191SThomas Gleixner for (i = 0; i < 512; i++) { 1540cc8bf191SThomas Gleixner if (!apic_check_and_ack(&irr, &isr)) 1541cc8bf191SThomas Gleixner return; 15429b217f33SDou Liyang } 1543cc8bf191SThomas Gleixner /* Dump the IRR/ISR content if that failed */ 1544cc8bf191SThomas Gleixner pr_warn("APIC: Stale IRR: %256pb ISR: %256pb\n", irr.map, isr.map); 15459b217f33SDou Liyang } 15469b217f33SDou Liyang 1547f62bae50SIngo Molnar /** 1548f62bae50SIngo Molnar * setup_local_APIC - setup the local APIC 15490aa002feSTejun Heo * 1550543113d2SDou Liyang * Used to setup local APIC while initializing BSP or bringing up APs. 15510aa002feSTejun Heo * Always called with preemption disabled. 1552f62bae50SIngo Molnar */ 1553b753a2b7SDou Liyang static void setup_local_APIC(void) 1554f62bae50SIngo Molnar { 15550aa002feSTejun Heo int cpu = smp_processor_id(); 15569b217f33SDou Liyang unsigned int value; 15578c3ba8d0SKerstin Jonsson 1558f62bae50SIngo Molnar if (disable_apic) { 15597167d08eSHenrik Kretzschmar disable_ioapic_support(); 1560f62bae50SIngo Molnar return; 1561f62bae50SIngo Molnar } 1562f62bae50SIngo Molnar 15632640da4cSThomas Gleixner /* 15642640da4cSThomas Gleixner * If this comes from kexec/kcrash the APIC might be enabled in 15652640da4cSThomas Gleixner * SPIV. Soft disable it before doing further initialization. 15662640da4cSThomas Gleixner */ 15672640da4cSThomas Gleixner value = apic_read(APIC_SPIV); 15682640da4cSThomas Gleixner value &= ~APIC_SPIV_APIC_ENABLED; 15692640da4cSThomas Gleixner apic_write(APIC_SPIV, value); 15702640da4cSThomas Gleixner 1571f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1572f62bae50SIngo Molnar /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1573f62bae50SIngo Molnar if (lapic_is_integrated() && apic->disable_esr) { 1574f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1575f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1576f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1577f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1578f62bae50SIngo Molnar } 1579f62bae50SIngo Molnar #endif 1580f62bae50SIngo Molnar /* 1581f62bae50SIngo Molnar * Double-check whether this APIC is really registered. 1582f62bae50SIngo Molnar * This is meaningless in clustered apic mode, so we skip it. 1583f62bae50SIngo Molnar */ 1584c2777f98SDaniel Walker BUG_ON(!apic->apic_id_registered()); 1585f62bae50SIngo Molnar 1586f62bae50SIngo Molnar /* 1587f62bae50SIngo Molnar * Intel recommends to set DFR, LDR and TPR before enabling 1588f62bae50SIngo Molnar * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1589f62bae50SIngo Molnar * document number 292116). So here it goes... 1590f62bae50SIngo Molnar */ 1591f62bae50SIngo Molnar apic->init_apic_ldr(); 1592f62bae50SIngo Molnar 15936f802c4bSTejun Heo #ifdef CONFIG_X86_32 1594*8c44963bSThomas Gleixner if (apic->dest_mode_logical) { 1595fe6f85caSJan Beulich int logical_apicid, ldr_apicid; 1596fe6f85caSJan Beulich 15976f802c4bSTejun Heo /* 1598acb8bc09STejun Heo * APIC LDR is initialized. If logical_apicid mapping was 1599fe6f85caSJan Beulich * initialized during get_smp_config(), make sure it matches 1600fe6f85caSJan Beulich * the actual value. 16016f802c4bSTejun Heo */ 16028f156168SDou Liyang logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu); 16038f156168SDou Liyang ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 1604fe6f85caSJan Beulich if (logical_apicid != BAD_APICID) 1605fe6f85caSJan Beulich WARN_ON(logical_apicid != ldr_apicid); 1606fe6f85caSJan Beulich /* Always use the value from LDR. */ 16078f156168SDou Liyang early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid; 1608fe6f85caSJan Beulich } 16096f802c4bSTejun Heo #endif 16106f802c4bSTejun Heo 1611f62bae50SIngo Molnar /* 1612229b969bSAndy Lutomirski * Set Task Priority to 'accept all except vectors 0-31'. An APIC 1613229b969bSAndy Lutomirski * vector in the 16-31 range could be delivered if TPR == 0, but we 1614229b969bSAndy Lutomirski * would think it's an exception and terrible things will happen. We 1615229b969bSAndy Lutomirski * never change this later on. 1616f62bae50SIngo Molnar */ 1617f62bae50SIngo Molnar value = apic_read(APIC_TASKPRI); 1618f62bae50SIngo Molnar value &= ~APIC_TPRI_MASK; 1619229b969bSAndy Lutomirski value |= 0x10; 1620f62bae50SIngo Molnar apic_write(APIC_TASKPRI, value); 1621f62bae50SIngo Molnar 1622cc8bf191SThomas Gleixner /* Clear eventually stale ISR/IRR bits */ 16239b217f33SDou Liyang apic_pending_intr_clear(); 1624f62bae50SIngo Molnar 1625f62bae50SIngo Molnar /* 1626f62bae50SIngo Molnar * Now that we are all set up, enable the APIC 1627f62bae50SIngo Molnar */ 1628f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 1629f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 1630f62bae50SIngo Molnar /* 1631f62bae50SIngo Molnar * Enable APIC 1632f62bae50SIngo Molnar */ 1633f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 1634f62bae50SIngo Molnar 1635f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1636f62bae50SIngo Molnar /* 1637f62bae50SIngo Molnar * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1638f62bae50SIngo Molnar * certain networking cards. If high frequency interrupts are 1639f62bae50SIngo Molnar * happening on a particular IOAPIC pin, plus the IOAPIC routing 1640f62bae50SIngo Molnar * entry is masked/unmasked at a high rate as well then sooner or 1641f62bae50SIngo Molnar * later IOAPIC line gets 'stuck', no more interrupts are received 1642f62bae50SIngo Molnar * from the device. If focus CPU is disabled then the hang goes 1643f62bae50SIngo Molnar * away, oh well :-( 1644f62bae50SIngo Molnar * 1645f62bae50SIngo Molnar * [ This bug can be reproduced easily with a level-triggered 1646f62bae50SIngo Molnar * PCI Ne2000 networking cards and PII/PIII processors, dual 1647f62bae50SIngo Molnar * BX chipset. ] 1648f62bae50SIngo Molnar */ 1649f62bae50SIngo Molnar /* 1650f62bae50SIngo Molnar * Actually disabling the focus CPU check just makes the hang less 1651f62bae50SIngo Molnar * frequent as it makes the interrupt distributon model be more 1652f62bae50SIngo Molnar * like LRU than MRU (the short-term load is more even across CPUs). 1653f62bae50SIngo Molnar */ 1654f62bae50SIngo Molnar 1655f62bae50SIngo Molnar /* 1656f62bae50SIngo Molnar * - enable focus processor (bit==0) 1657f62bae50SIngo Molnar * - 64bit mode always use processor focus 1658f62bae50SIngo Molnar * so no need to set it 1659f62bae50SIngo Molnar */ 1660f62bae50SIngo Molnar value &= ~APIC_SPIV_FOCUS_DISABLED; 1661f62bae50SIngo Molnar #endif 1662f62bae50SIngo Molnar 1663f62bae50SIngo Molnar /* 1664f62bae50SIngo Molnar * Set spurious IRQ vector 1665f62bae50SIngo Molnar */ 1666f62bae50SIngo Molnar value |= SPURIOUS_APIC_VECTOR; 1667f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 1668f62bae50SIngo Molnar 166939c89dffSThomas Gleixner perf_events_lapic_init(); 167039c89dffSThomas Gleixner 1671f62bae50SIngo Molnar /* 1672f62bae50SIngo Molnar * Set up LVT0, LVT1: 1673f62bae50SIngo Molnar * 1674a1652bb8SJean Delvare * set up through-local-APIC on the boot CPU's LINT0. This is not 1675f62bae50SIngo Molnar * strictly necessary in pure symmetric-IO mode, but sometimes 1676f62bae50SIngo Molnar * we delegate interrupts to the 8259A. 1677f62bae50SIngo Molnar */ 1678f62bae50SIngo Molnar /* 1679f62bae50SIngo Molnar * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1680f62bae50SIngo Molnar */ 1681f62bae50SIngo Molnar value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1682bee3204eSBaoquan He if (!cpu && (pic_mode || !value || skip_ioapic_setup)) { 1683f62bae50SIngo Molnar value = APIC_DM_EXTINT; 16840aa002feSTejun Heo apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1685f62bae50SIngo Molnar } else { 1686f62bae50SIngo Molnar value = APIC_DM_EXTINT | APIC_LVT_MASKED; 16870aa002feSTejun Heo apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1688f62bae50SIngo Molnar } 1689f62bae50SIngo Molnar apic_write(APIC_LVT0, value); 1690f62bae50SIngo Molnar 1691f62bae50SIngo Molnar /* 1692b7c4948eSHidehiro Kawai * Only the BSP sees the LINT1 NMI signal by default. This can be 1693b7c4948eSHidehiro Kawai * modified by apic_extnmi= boot option. 1694f62bae50SIngo Molnar */ 1695b7c4948eSHidehiro Kawai if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) || 1696b7c4948eSHidehiro Kawai apic_extnmi == APIC_EXTNMI_ALL) 1697f62bae50SIngo Molnar value = APIC_DM_NMI; 1698f62bae50SIngo Molnar else 1699f62bae50SIngo Molnar value = APIC_DM_NMI | APIC_LVT_MASKED; 1700ae41a2a4SDou Liyang 1701ae41a2a4SDou Liyang /* Is 82489DX ? */ 1702ae41a2a4SDou Liyang if (!lapic_is_integrated()) 1703f62bae50SIngo Molnar value |= APIC_LVT_LEVEL_TRIGGER; 1704f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 1705f62bae50SIngo Molnar 1706638bee71SH. Peter Anvin #ifdef CONFIG_X86_MCE_INTEL 1707638bee71SH. Peter Anvin /* Recheck CMCI information after local APIC is up on CPU #0 */ 17080aa002feSTejun Heo if (!cpu) 1709638bee71SH. Peter Anvin cmci_recheck(); 1710638bee71SH. Peter Anvin #endif 1711f62bae50SIngo Molnar } 1712f62bae50SIngo Molnar 171305f7e46dSThomas Gleixner static void end_local_APIC_setup(void) 1714f62bae50SIngo Molnar { 1715f62bae50SIngo Molnar lapic_setup_esr(); 1716f62bae50SIngo Molnar 1717f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1718f62bae50SIngo Molnar { 1719f62bae50SIngo Molnar unsigned int value; 1720f62bae50SIngo Molnar /* Disable the local apic timer */ 1721f62bae50SIngo Molnar value = apic_read(APIC_LVTT); 1722f62bae50SIngo Molnar value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1723f62bae50SIngo Molnar apic_write(APIC_LVTT, value); 1724f62bae50SIngo Molnar } 1725f62bae50SIngo Molnar #endif 1726f62bae50SIngo Molnar 1727f62bae50SIngo Molnar apic_pm_activate(); 17282fb270f3SJan Beulich } 17292fb270f3SJan Beulich 17307f7fbf45SKenji Kaneshige /* 173105f7e46dSThomas Gleixner * APIC setup function for application processors. Called from smpboot.c 17327f7fbf45SKenji Kaneshige */ 173305f7e46dSThomas Gleixner void apic_ap_setup(void) 173405f7e46dSThomas Gleixner { 173505f7e46dSThomas Gleixner setup_local_APIC(); 173605f7e46dSThomas Gleixner end_local_APIC_setup(); 1737f62bae50SIngo Molnar } 1738f62bae50SIngo Molnar 1739f62bae50SIngo Molnar #ifdef CONFIG_X86_X2APIC 1740bfb05070SThomas Gleixner int x2apic_mode; 174112e189d3SThomas Gleixner 174212e189d3SThomas Gleixner enum { 174312e189d3SThomas Gleixner X2APIC_OFF, 174412e189d3SThomas Gleixner X2APIC_ON, 174512e189d3SThomas Gleixner X2APIC_DISABLED, 174612e189d3SThomas Gleixner }; 174712e189d3SThomas Gleixner static int x2apic_state; 174812e189d3SThomas Gleixner 1749d786ad32SDenys Vlasenko static void __x2apic_disable(void) 175044e25ff9SThomas Gleixner { 175144e25ff9SThomas Gleixner u64 msr; 175244e25ff9SThomas Gleixner 175393984fbdSBorislav Petkov if (!boot_cpu_has(X86_FEATURE_APIC)) 1754659006bfSThomas Gleixner return; 1755659006bfSThomas Gleixner 175644e25ff9SThomas Gleixner rdmsrl(MSR_IA32_APICBASE, msr); 175744e25ff9SThomas Gleixner if (!(msr & X2APIC_ENABLE)) 175844e25ff9SThomas Gleixner return; 175944e25ff9SThomas Gleixner /* Disable xapic and x2apic first and then reenable xapic mode */ 176044e25ff9SThomas Gleixner wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); 176144e25ff9SThomas Gleixner wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); 176244e25ff9SThomas Gleixner printk_once(KERN_INFO "x2apic disabled\n"); 176344e25ff9SThomas Gleixner } 176444e25ff9SThomas Gleixner 1765d786ad32SDenys Vlasenko static void __x2apic_enable(void) 1766659006bfSThomas Gleixner { 1767659006bfSThomas Gleixner u64 msr; 1768659006bfSThomas Gleixner 1769659006bfSThomas Gleixner rdmsrl(MSR_IA32_APICBASE, msr); 1770659006bfSThomas Gleixner if (msr & X2APIC_ENABLE) 1771659006bfSThomas Gleixner return; 1772659006bfSThomas Gleixner wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); 1773659006bfSThomas Gleixner printk_once(KERN_INFO "x2apic enabled\n"); 1774659006bfSThomas Gleixner } 1775659006bfSThomas Gleixner 1776bfb05070SThomas Gleixner static int __init setup_nox2apic(char *str) 1777bfb05070SThomas Gleixner { 1778bfb05070SThomas Gleixner if (x2apic_enabled()) { 1779bfb05070SThomas Gleixner int apicid = native_apic_msr_read(APIC_ID); 1780bfb05070SThomas Gleixner 1781bfb05070SThomas Gleixner if (apicid >= 255) { 17828d3bcc44SKefeng Wang pr_warn("Apicid: %08x, cannot enforce nox2apic\n", 1783bfb05070SThomas Gleixner apicid); 1784bfb05070SThomas Gleixner return 0; 1785bfb05070SThomas Gleixner } 17868d3bcc44SKefeng Wang pr_warn("x2apic already enabled.\n"); 178744e25ff9SThomas Gleixner __x2apic_disable(); 178844e25ff9SThomas Gleixner } 1789bfb05070SThomas Gleixner setup_clear_cpu_cap(X86_FEATURE_X2APIC); 179012e189d3SThomas Gleixner x2apic_state = X2APIC_DISABLED; 179144e25ff9SThomas Gleixner x2apic_mode = 0; 1792bfb05070SThomas Gleixner return 0; 1793bfb05070SThomas Gleixner } 1794bfb05070SThomas Gleixner early_param("nox2apic", setup_nox2apic); 1795bfb05070SThomas Gleixner 1796659006bfSThomas Gleixner /* Called from cpu_init() to enable x2apic on (secondary) cpus */ 1797659006bfSThomas Gleixner void x2apic_setup(void) 1798659006bfSThomas Gleixner { 1799659006bfSThomas Gleixner /* 1800659006bfSThomas Gleixner * If x2apic is not in ON state, disable it if already enabled 1801659006bfSThomas Gleixner * from BIOS. 1802659006bfSThomas Gleixner */ 1803659006bfSThomas Gleixner if (x2apic_state != X2APIC_ON) { 1804659006bfSThomas Gleixner __x2apic_disable(); 1805659006bfSThomas Gleixner return; 1806659006bfSThomas Gleixner } 1807659006bfSThomas Gleixner __x2apic_enable(); 1808659006bfSThomas Gleixner } 1809659006bfSThomas Gleixner 181044e25ff9SThomas Gleixner static __init void x2apic_disable(void) 1811fb209bd8SYinghai Lu { 1812a57e456aSThomas Gleixner u32 x2apic_id, state = x2apic_state; 1813fb209bd8SYinghai Lu 1814a57e456aSThomas Gleixner x2apic_mode = 0; 1815a57e456aSThomas Gleixner x2apic_state = X2APIC_DISABLED; 1816a57e456aSThomas Gleixner 1817a57e456aSThomas Gleixner if (state != X2APIC_ON) 1818a57e456aSThomas Gleixner return; 1819fb209bd8SYinghai Lu 18206d2d49d2SThomas Gleixner x2apic_id = read_apic_id(); 1821fb209bd8SYinghai Lu if (x2apic_id >= 255) 1822fb209bd8SYinghai Lu panic("Cannot disable x2apic, id: %08x\n", x2apic_id); 1823fb209bd8SYinghai Lu 182444e25ff9SThomas Gleixner __x2apic_disable(); 1825fb209bd8SYinghai Lu register_lapic_address(mp_lapic_addr); 1826fb209bd8SYinghai Lu } 1827fb209bd8SYinghai Lu 1828659006bfSThomas Gleixner static __init void x2apic_enable(void) 1829f62bae50SIngo Molnar { 1830659006bfSThomas Gleixner if (x2apic_state != X2APIC_OFF) 1831f62bae50SIngo Molnar return; 1832f62bae50SIngo Molnar 1833659006bfSThomas Gleixner x2apic_mode = 1; 183412e189d3SThomas Gleixner x2apic_state = X2APIC_ON; 1835659006bfSThomas Gleixner __x2apic_enable(); 1836f62bae50SIngo Molnar } 1837d524165cSThomas Gleixner 183862e61633SThomas Gleixner static __init void try_to_enable_x2apic(int remap_mode) 183907806c50SJiang Liu { 1840659006bfSThomas Gleixner if (x2apic_state == X2APIC_DISABLED) 184107806c50SJiang Liu return; 184207806c50SJiang Liu 184362e61633SThomas Gleixner if (remap_mode != IRQ_REMAP_X2APIC_MODE) { 184426573a97SDavid Woodhouse /* 184526573a97SDavid Woodhouse * Using X2APIC without IR is not architecturally supported 184626573a97SDavid Woodhouse * on bare metal but may be supported in guests. 184707806c50SJiang Liu */ 184826573a97SDavid Woodhouse if (!x86_init.hyper.x2apic_available()) { 184962e61633SThomas Gleixner pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); 185044e25ff9SThomas Gleixner x2apic_disable(); 185107806c50SJiang Liu return; 185207806c50SJiang Liu } 185307806c50SJiang Liu 185407806c50SJiang Liu /* 185526573a97SDavid Woodhouse * Without IR, all CPUs can be addressed by IOAPIC/MSI only 185626573a97SDavid Woodhouse * in physical mode, and CPUs with an APIC ID that cannnot 185726573a97SDavid Woodhouse * be addressed must not be brought online. 185807806c50SJiang Liu */ 185926573a97SDavid Woodhouse x2apic_set_max_apicid(255); 186055eae7deSThomas Gleixner x2apic_phys = 1; 186107806c50SJiang Liu } 1862659006bfSThomas Gleixner x2apic_enable(); 186355eae7deSThomas Gleixner } 186455eae7deSThomas Gleixner 186555eae7deSThomas Gleixner void __init check_x2apic(void) 186655eae7deSThomas Gleixner { 186755eae7deSThomas Gleixner if (x2apic_enabled()) { 186855eae7deSThomas Gleixner pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); 186955eae7deSThomas Gleixner x2apic_mode = 1; 187012e189d3SThomas Gleixner x2apic_state = X2APIC_ON; 187162436a4dSBorislav Petkov } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) { 187212e189d3SThomas Gleixner x2apic_state = X2APIC_DISABLED; 187355eae7deSThomas Gleixner } 187455eae7deSThomas Gleixner } 187555eae7deSThomas Gleixner #else /* CONFIG_X86_X2APIC */ 187655eae7deSThomas Gleixner static int __init validate_x2apic(void) 187755eae7deSThomas Gleixner { 187855eae7deSThomas Gleixner if (!apic_is_x2apic_enabled()) 187955eae7deSThomas Gleixner return 0; 188055eae7deSThomas Gleixner /* 188155eae7deSThomas Gleixner * Checkme: Can we simply turn off x2apic here instead of panic? 188255eae7deSThomas Gleixner */ 188355eae7deSThomas Gleixner panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n"); 188455eae7deSThomas Gleixner } 188555eae7deSThomas Gleixner early_initcall(validate_x2apic); 188655eae7deSThomas Gleixner 188762e61633SThomas Gleixner static inline void try_to_enable_x2apic(int remap_mode) { } 1888659006bfSThomas Gleixner static inline void __x2apic_enable(void) { } 188955eae7deSThomas Gleixner #endif /* !CONFIG_X86_X2APIC */ 189055eae7deSThomas Gleixner 1891ce69a784SGleb Natapov void __init enable_IR_x2apic(void) 1892ce69a784SGleb Natapov { 1893ce69a784SGleb Natapov unsigned long flags; 189407806c50SJiang Liu int ret, ir_stat; 1895b7f42ab2SYinghai Lu 189611277aabSDou Liyang if (skip_ioapic_setup) { 189711277aabSDou Liyang pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); 18982e63ad4bSWanpeng Li return; 189911277aabSDou Liyang } 19002e63ad4bSWanpeng Li 190107806c50SJiang Liu ir_stat = irq_remapping_prepare(); 190207806c50SJiang Liu if (ir_stat < 0 && !x2apic_supported()) 1903e670761fSYinghai Lu return; 1904ce69a784SGleb Natapov 190531dce14aSSuresh Siddha ret = save_ioapic_entries(); 1906f62bae50SIngo Molnar if (ret) { 1907f62bae50SIngo Molnar pr_info("Saving IO-APIC state failed: %d\n", ret); 1908fb209bd8SYinghai Lu return; 1909f62bae50SIngo Molnar } 1910f62bae50SIngo Molnar 191105c3dc2cSSuresh Siddha local_irq_save(flags); 1912b81bb373SJacob Pan legacy_pic->mask_all(); 191331dce14aSSuresh Siddha mask_ioapic_entries(); 191405c3dc2cSSuresh Siddha 19156a6256f9SAdam Buchbinder /* If irq_remapping_prepare() succeeded, try to enable it */ 191607806c50SJiang Liu if (ir_stat >= 0) 191711277aabSDou Liyang ir_stat = irq_remapping_enable(); 191807806c50SJiang Liu /* ir_stat contains the remap mode or an error code */ 191907806c50SJiang Liu try_to_enable_x2apic(ir_stat); 1920a31bc327SYinghai Lu 192107806c50SJiang Liu if (ir_stat < 0) 192231dce14aSSuresh Siddha restore_ioapic_entries(); 1923b81bb373SJacob Pan legacy_pic->restore_mask(); 1924f62bae50SIngo Molnar local_irq_restore(flags); 1925f62bae50SIngo Molnar } 192693758238SWeidong Han 1927f62bae50SIngo Molnar #ifdef CONFIG_X86_64 1928f62bae50SIngo Molnar /* 1929f62bae50SIngo Molnar * Detect and enable local APICs on non-SMP boards. 1930f62bae50SIngo Molnar * Original code written by Keir Fraser. 1931f62bae50SIngo Molnar * On AMD64 we trust the BIOS - if it says no APIC it is likely 1932f62bae50SIngo Molnar * not correctly set up (usually the APIC timer won't work etc.) 1933f62bae50SIngo Molnar */ 1934f62bae50SIngo Molnar static int __init detect_init_APIC(void) 1935f62bae50SIngo Molnar { 193693984fbdSBorislav Petkov if (!boot_cpu_has(X86_FEATURE_APIC)) { 1937f62bae50SIngo Molnar pr_info("No local APIC present\n"); 1938f62bae50SIngo Molnar return -1; 1939f62bae50SIngo Molnar } 1940f62bae50SIngo Molnar 1941f62bae50SIngo Molnar mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1942f62bae50SIngo Molnar return 0; 1943f62bae50SIngo Molnar } 1944f62bae50SIngo Molnar #else 19455a7ae78fSThomas Gleixner 194625874a29SHenrik Kretzschmar static int __init apic_verify(void) 19475a7ae78fSThomas Gleixner { 19485a7ae78fSThomas Gleixner u32 features, h, l; 19495a7ae78fSThomas Gleixner 19505a7ae78fSThomas Gleixner /* 19515a7ae78fSThomas Gleixner * The APIC feature bit should now be enabled 19525a7ae78fSThomas Gleixner * in `cpuid' 19535a7ae78fSThomas Gleixner */ 19545a7ae78fSThomas Gleixner features = cpuid_edx(1); 19555a7ae78fSThomas Gleixner if (!(features & (1 << X86_FEATURE_APIC))) { 19568d3bcc44SKefeng Wang pr_warn("Could not enable APIC!\n"); 19575a7ae78fSThomas Gleixner return -1; 19585a7ae78fSThomas Gleixner } 19595a7ae78fSThomas Gleixner set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 19605a7ae78fSThomas Gleixner mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 19615a7ae78fSThomas Gleixner 19625a7ae78fSThomas Gleixner /* The BIOS may have set up the APIC at some other address */ 1963cbf2829bSBryan O'Donoghue if (boot_cpu_data.x86 >= 6) { 19645a7ae78fSThomas Gleixner rdmsr(MSR_IA32_APICBASE, l, h); 19655a7ae78fSThomas Gleixner if (l & MSR_IA32_APICBASE_ENABLE) 19665a7ae78fSThomas Gleixner mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1967cbf2829bSBryan O'Donoghue } 19685a7ae78fSThomas Gleixner 19695a7ae78fSThomas Gleixner pr_info("Found and enabled local APIC!\n"); 19705a7ae78fSThomas Gleixner return 0; 19715a7ae78fSThomas Gleixner } 19725a7ae78fSThomas Gleixner 197325874a29SHenrik Kretzschmar int __init apic_force_enable(unsigned long addr) 19745a7ae78fSThomas Gleixner { 19755a7ae78fSThomas Gleixner u32 h, l; 19765a7ae78fSThomas Gleixner 19775a7ae78fSThomas Gleixner if (disable_apic) 19785a7ae78fSThomas Gleixner return -1; 19795a7ae78fSThomas Gleixner 19805a7ae78fSThomas Gleixner /* 19815a7ae78fSThomas Gleixner * Some BIOSes disable the local APIC in the APIC_BASE 19825a7ae78fSThomas Gleixner * MSR. This can only be done in software for Intel P6 or later 19835a7ae78fSThomas Gleixner * and AMD K7 (Model > 1) or later. 19845a7ae78fSThomas Gleixner */ 1985cbf2829bSBryan O'Donoghue if (boot_cpu_data.x86 >= 6) { 19865a7ae78fSThomas Gleixner rdmsr(MSR_IA32_APICBASE, l, h); 19875a7ae78fSThomas Gleixner if (!(l & MSR_IA32_APICBASE_ENABLE)) { 19885a7ae78fSThomas Gleixner pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 19895a7ae78fSThomas Gleixner l &= ~MSR_IA32_APICBASE_BASE; 1990a906fdaaSThomas Gleixner l |= MSR_IA32_APICBASE_ENABLE | addr; 19915a7ae78fSThomas Gleixner wrmsr(MSR_IA32_APICBASE, l, h); 19925a7ae78fSThomas Gleixner enabled_via_apicbase = 1; 19935a7ae78fSThomas Gleixner } 1994cbf2829bSBryan O'Donoghue } 19955a7ae78fSThomas Gleixner return apic_verify(); 19965a7ae78fSThomas Gleixner } 19975a7ae78fSThomas Gleixner 1998f62bae50SIngo Molnar /* 1999f62bae50SIngo Molnar * Detect and initialize APIC 2000f62bae50SIngo Molnar */ 2001f62bae50SIngo Molnar static int __init detect_init_APIC(void) 2002f62bae50SIngo Molnar { 2003f62bae50SIngo Molnar /* Disabled by kernel option? */ 2004f62bae50SIngo Molnar if (disable_apic) 2005f62bae50SIngo Molnar return -1; 2006f62bae50SIngo Molnar 2007f62bae50SIngo Molnar switch (boot_cpu_data.x86_vendor) { 2008f62bae50SIngo Molnar case X86_VENDOR_AMD: 2009f62bae50SIngo Molnar if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 2010f62bae50SIngo Molnar (boot_cpu_data.x86 >= 15)) 2011f62bae50SIngo Molnar break; 2012f62bae50SIngo Molnar goto no_apic; 2013da33dfefSPu Wen case X86_VENDOR_HYGON: 2014da33dfefSPu Wen break; 2015f62bae50SIngo Molnar case X86_VENDOR_INTEL: 2016f62bae50SIngo Molnar if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 201793984fbdSBorislav Petkov (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC))) 2018f62bae50SIngo Molnar break; 2019f62bae50SIngo Molnar goto no_apic; 2020f62bae50SIngo Molnar default: 2021f62bae50SIngo Molnar goto no_apic; 2022f62bae50SIngo Molnar } 2023f62bae50SIngo Molnar 202493984fbdSBorislav Petkov if (!boot_cpu_has(X86_FEATURE_APIC)) { 2025f62bae50SIngo Molnar /* 2026f62bae50SIngo Molnar * Over-ride BIOS and try to enable the local APIC only if 2027f62bae50SIngo Molnar * "lapic" specified. 2028f62bae50SIngo Molnar */ 2029f62bae50SIngo Molnar if (!force_enable_local_apic) { 2030f62bae50SIngo Molnar pr_info("Local APIC disabled by BIOS -- " 2031f62bae50SIngo Molnar "you can enable it with \"lapic\"\n"); 2032f62bae50SIngo Molnar return -1; 2033f62bae50SIngo Molnar } 2034a906fdaaSThomas Gleixner if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) 20355a7ae78fSThomas Gleixner return -1; 20365a7ae78fSThomas Gleixner } else { 20375a7ae78fSThomas Gleixner if (apic_verify()) 2038f62bae50SIngo Molnar return -1; 2039f62bae50SIngo Molnar } 2040f62bae50SIngo Molnar 2041f62bae50SIngo Molnar apic_pm_activate(); 2042f62bae50SIngo Molnar 2043f62bae50SIngo Molnar return 0; 2044f62bae50SIngo Molnar 2045f62bae50SIngo Molnar no_apic: 2046f62bae50SIngo Molnar pr_info("No local APIC present or hardware disabled\n"); 2047f62bae50SIngo Molnar return -1; 2048f62bae50SIngo Molnar } 2049f62bae50SIngo Molnar #endif 2050f62bae50SIngo Molnar 2051f62bae50SIngo Molnar /** 2052f62bae50SIngo Molnar * init_apic_mappings - initialize APIC mappings 2053f62bae50SIngo Molnar */ 2054f62bae50SIngo Molnar void __init init_apic_mappings(void) 2055f62bae50SIngo Molnar { 20564401da61SYinghai Lu unsigned int new_apicid; 20574401da61SYinghai Lu 2058c84cb373SThomas Gleixner if (apic_validate_deadline_timer()) 2059de308d18SBorislav Petkov pr_info("TSC deadline timer available\n"); 2060bd9240a1SPeter Zijlstra 2061fc1edaf9SSuresh Siddha if (x2apic_mode) { 2062f62bae50SIngo Molnar boot_cpu_physical_apicid = read_apic_id(); 2063f62bae50SIngo Molnar return; 2064f62bae50SIngo Molnar } 2065f62bae50SIngo Molnar 20664797f6b0SYinghai Lu /* If no local APIC can be found return early */ 2067f62bae50SIngo Molnar if (!smp_found_config && detect_init_APIC()) { 20684797f6b0SYinghai Lu /* lets NOP'ify apic operations */ 20694797f6b0SYinghai Lu pr_info("APIC: disable apic facility\n"); 20704797f6b0SYinghai Lu apic_disable(); 20714797f6b0SYinghai Lu } else { 2072f62bae50SIngo Molnar apic_phys = mp_lapic_addr; 2073f62bae50SIngo Molnar 20744401da61SYinghai Lu /* 20755ba039a5SDou Liyang * If the system has ACPI MADT tables or MP info, the LAPIC 20765ba039a5SDou Liyang * address is already registered. 20774401da61SYinghai Lu */ 20785989cd6aSEric W. Biederman if (!acpi_lapic && !smp_found_config) 2079326a2e6bSYinghai Lu register_lapic_address(apic_phys); 2080cec6be6dSCyrill Gorcunov } 2081f62bae50SIngo Molnar 2082f62bae50SIngo Molnar /* 2083f62bae50SIngo Molnar * Fetch the APIC ID of the BSP in case we have a 2084f62bae50SIngo Molnar * default configuration (or the MP table is broken). 2085f62bae50SIngo Molnar */ 20864401da61SYinghai Lu new_apicid = read_apic_id(); 20874401da61SYinghai Lu if (boot_cpu_physical_apicid != new_apicid) { 20884401da61SYinghai Lu boot_cpu_physical_apicid = new_apicid; 2089103428e5SCyrill Gorcunov /* 2090103428e5SCyrill Gorcunov * yeah -- we lie about apic_version 2091103428e5SCyrill Gorcunov * in case if apic was disabled via boot option 2092103428e5SCyrill Gorcunov * but it's not a problem for SMP compiled kernel 20934f45ed9fSDou Liyang * since apic_intr_mode_select is prepared for such 20944f45ed9fSDou Liyang * a case and disable smp mode 2095103428e5SCyrill Gorcunov */ 2096cff9ab2bSDenys Vlasenko boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 209708306ce6SCyrill Gorcunov } 2098f62bae50SIngo Molnar } 2099f62bae50SIngo Molnar 2100c0104d38SYinghai Lu void __init register_lapic_address(unsigned long address) 2101c0104d38SYinghai Lu { 2102c0104d38SYinghai Lu mp_lapic_addr = address; 2103c0104d38SYinghai Lu 21040450193bSYinghai Lu if (!x2apic_mode) { 2105c0104d38SYinghai Lu set_fixmap_nocache(FIX_APIC_BASE, address); 2106f1157141SYinghai Lu apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 21076de42119SBaoquan He APIC_BASE, address); 21080450193bSYinghai Lu } 2109c0104d38SYinghai Lu if (boot_cpu_physical_apicid == -1U) { 2110c0104d38SYinghai Lu boot_cpu_physical_apicid = read_apic_id(); 2111cff9ab2bSDenys Vlasenko boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 2112c0104d38SYinghai Lu } 2113c0104d38SYinghai Lu } 2114c0104d38SYinghai Lu 2115f62bae50SIngo Molnar /* 2116f62bae50SIngo Molnar * Local APIC interrupts 2117f62bae50SIngo Molnar */ 2118f62bae50SIngo Molnar 2119633260faSThomas Gleixner /** 2120fa5e5c40SThomas Gleixner * spurious_interrupt - Catch all for interrupts raised on unused vectors 2121633260faSThomas Gleixner * @regs: Pointer to pt_regs on stack 2122fa5e5c40SThomas Gleixner * @vector: The vector number 2123633260faSThomas Gleixner * 2124633260faSThomas Gleixner * This is invoked from ASM entry code to catch all interrupts which 2125633260faSThomas Gleixner * trigger on an entry which is routed to the common_spurious idtentry 2126633260faSThomas Gleixner * point. 2127633260faSThomas Gleixner * 2128db0338eeSThomas Gleixner * Also called from sysvec_spurious_apic_interrupt(). 2129f62bae50SIngo Molnar */ 2130fa5e5c40SThomas Gleixner DEFINE_IDTENTRY_IRQ(spurious_interrupt) 2131f62bae50SIngo Molnar { 2132f62bae50SIngo Molnar u32 v; 2133f62bae50SIngo Molnar 213461069de7SThomas Gleixner trace_spurious_apic_entry(vector); 213561069de7SThomas Gleixner 2136f62bae50SIngo Molnar inc_irq_stat(irq_spurious_count); 2137f62bae50SIngo Molnar 2138f8a8fe61SThomas Gleixner /* 2139f8a8fe61SThomas Gleixner * If this is a spurious interrupt then do not acknowledge 2140f8a8fe61SThomas Gleixner */ 2141f8a8fe61SThomas Gleixner if (vector == SPURIOUS_APIC_VECTOR) { 2142f8a8fe61SThomas Gleixner /* See SDM vol 3 */ 2143f8a8fe61SThomas Gleixner pr_info("Spurious APIC interrupt (vector 0xFF) on CPU#%d, should never happen.\n", 2144f8a8fe61SThomas Gleixner smp_processor_id()); 2145f8a8fe61SThomas Gleixner goto out; 2146f8a8fe61SThomas Gleixner } 2147eddc0e92SSeiji Aguchi 2148f8a8fe61SThomas Gleixner /* 2149f8a8fe61SThomas Gleixner * If it is a vectored one, verify it's set in the ISR. If set, 2150f8a8fe61SThomas Gleixner * acknowledge it. 2151f8a8fe61SThomas Gleixner */ 2152f8a8fe61SThomas Gleixner v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); 2153f8a8fe61SThomas Gleixner if (v & (1 << (vector & 0x1f))) { 2154f8a8fe61SThomas Gleixner pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Acked\n", 2155f8a8fe61SThomas Gleixner vector, smp_processor_id()); 2156f8a8fe61SThomas Gleixner ack_APIC_irq(); 2157f8a8fe61SThomas Gleixner } else { 2158f8a8fe61SThomas Gleixner pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Not pending!\n", 2159f8a8fe61SThomas Gleixner vector, smp_processor_id()); 2160f8a8fe61SThomas Gleixner } 2161f8a8fe61SThomas Gleixner out: 21622414e021SJan Beulich trace_spurious_apic_exit(vector); 2163f62bae50SIngo Molnar } 2164f62bae50SIngo Molnar 2165db0338eeSThomas Gleixner DEFINE_IDTENTRY_SYSVEC(sysvec_spurious_apic_interrupt) 2166633260faSThomas Gleixner { 2167fa5e5c40SThomas Gleixner __spurious_interrupt(regs, SPURIOUS_APIC_VECTOR); 2168f62bae50SIngo Molnar } 2169f62bae50SIngo Molnar 2170f62bae50SIngo Molnar /* 2171f62bae50SIngo Molnar * This interrupt should never happen with our APIC/SMP architecture 2172f62bae50SIngo Molnar */ 2173db0338eeSThomas Gleixner DEFINE_IDTENTRY_SYSVEC(sysvec_error_interrupt) 2174f62bae50SIngo Molnar { 21752b398bd9SYouquan Song static const char * const error_interrupt_reason[] = { 21762b398bd9SYouquan Song "Send CS error", /* APIC Error Bit 0 */ 21772b398bd9SYouquan Song "Receive CS error", /* APIC Error Bit 1 */ 21782b398bd9SYouquan Song "Send accept error", /* APIC Error Bit 2 */ 21792b398bd9SYouquan Song "Receive accept error", /* APIC Error Bit 3 */ 21802b398bd9SYouquan Song "Redirectable IPI", /* APIC Error Bit 4 */ 21812b398bd9SYouquan Song "Send illegal vector", /* APIC Error Bit 5 */ 21822b398bd9SYouquan Song "Received illegal vector", /* APIC Error Bit 6 */ 21832b398bd9SYouquan Song "Illegal register address", /* APIC Error Bit 7 */ 21842b398bd9SYouquan Song }; 218561069de7SThomas Gleixner u32 v, i = 0; 218661069de7SThomas Gleixner 218761069de7SThomas Gleixner trace_error_apic_entry(ERROR_APIC_VECTOR); 2188f62bae50SIngo Molnar 2189f62bae50SIngo Molnar /* First tickle the hardware, only then report what went on. -- REW */ 2190023de4a0SMaciej W. Rozycki if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ 2191f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 219260283df7SRichard Weinberger v = apic_read(APIC_ESR); 2193f62bae50SIngo Molnar ack_APIC_irq(); 2194f62bae50SIngo Molnar atomic_inc(&irq_err_count); 2195f62bae50SIngo Molnar 219660283df7SRichard Weinberger apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", 219760283df7SRichard Weinberger smp_processor_id(), v); 21982b398bd9SYouquan Song 219960283df7SRichard Weinberger v &= 0xff; 220060283df7SRichard Weinberger while (v) { 220160283df7SRichard Weinberger if (v & 0x1) 22022b398bd9SYouquan Song apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); 22032b398bd9SYouquan Song i++; 220460283df7SRichard Weinberger v >>= 1; 22054b8073e4SPeter Senna Tschudin } 22062b398bd9SYouquan Song 22072b398bd9SYouquan Song apic_printk(APIC_DEBUG, KERN_CONT "\n"); 22082b398bd9SYouquan Song 2209cf910e83SSeiji Aguchi trace_error_apic_exit(ERROR_APIC_VECTOR); 2210f62bae50SIngo Molnar } 2211f62bae50SIngo Molnar 2212f62bae50SIngo Molnar /** 2213f62bae50SIngo Molnar * connect_bsp_APIC - attach the APIC to the interrupt system 2214f62bae50SIngo Molnar */ 221505f7e46dSThomas Gleixner static void __init connect_bsp_APIC(void) 2216f62bae50SIngo Molnar { 2217f62bae50SIngo Molnar #ifdef CONFIG_X86_32 2218f62bae50SIngo Molnar if (pic_mode) { 2219f62bae50SIngo Molnar /* 2220f62bae50SIngo Molnar * Do not trust the local APIC being empty at bootup. 2221f62bae50SIngo Molnar */ 2222f62bae50SIngo Molnar clear_local_APIC(); 2223f62bae50SIngo Molnar /* 2224f62bae50SIngo Molnar * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 2225f62bae50SIngo Molnar * local APIC to INT and NMI lines. 2226f62bae50SIngo Molnar */ 2227f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "leaving PIC mode, " 2228f62bae50SIngo Molnar "enabling APIC mode.\n"); 2229c0eaa453SCyrill Gorcunov imcr_pic_to_apic(); 2230f62bae50SIngo Molnar } 2231f62bae50SIngo Molnar #endif 2232f62bae50SIngo Molnar } 2233f62bae50SIngo Molnar 2234f62bae50SIngo Molnar /** 2235f62bae50SIngo Molnar * disconnect_bsp_APIC - detach the APIC from the interrupt system 2236f62bae50SIngo Molnar * @virt_wire_setup: indicates, whether virtual wire mode is selected 2237f62bae50SIngo Molnar * 2238f62bae50SIngo Molnar * Virtual wire mode is necessary to deliver legacy interrupts even when the 2239f62bae50SIngo Molnar * APIC is disabled. 2240f62bae50SIngo Molnar */ 2241f62bae50SIngo Molnar void disconnect_bsp_APIC(int virt_wire_setup) 2242f62bae50SIngo Molnar { 2243f62bae50SIngo Molnar unsigned int value; 2244f62bae50SIngo Molnar 2245f62bae50SIngo Molnar #ifdef CONFIG_X86_32 2246f62bae50SIngo Molnar if (pic_mode) { 2247f62bae50SIngo Molnar /* 2248f62bae50SIngo Molnar * Put the board back into PIC mode (has an effect only on 2249f62bae50SIngo Molnar * certain older boards). Note that APIC interrupts, including 2250f62bae50SIngo Molnar * IPIs, won't work beyond this point! The only exception are 2251f62bae50SIngo Molnar * INIT IPIs. 2252f62bae50SIngo Molnar */ 2253f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "disabling APIC mode, " 2254f62bae50SIngo Molnar "entering PIC mode.\n"); 2255c0eaa453SCyrill Gorcunov imcr_apic_to_pic(); 2256f62bae50SIngo Molnar return; 2257f62bae50SIngo Molnar } 2258f62bae50SIngo Molnar #endif 2259f62bae50SIngo Molnar 2260f62bae50SIngo Molnar /* Go back to Virtual Wire compatibility mode */ 2261f62bae50SIngo Molnar 2262f62bae50SIngo Molnar /* For the spurious interrupt use vector F, and enable it */ 2263f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 2264f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 2265f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 2266f62bae50SIngo Molnar value |= 0xf; 2267f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 2268f62bae50SIngo Molnar 2269f62bae50SIngo Molnar if (!virt_wire_setup) { 2270f62bae50SIngo Molnar /* 2271f62bae50SIngo Molnar * For LVT0 make it edge triggered, active high, 2272f62bae50SIngo Molnar * external and enabled 2273f62bae50SIngo Molnar */ 2274f62bae50SIngo Molnar value = apic_read(APIC_LVT0); 2275f62bae50SIngo Molnar value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2276f62bae50SIngo Molnar APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2277f62bae50SIngo Molnar APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2278f62bae50SIngo Molnar value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2279f62bae50SIngo Molnar value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 2280f62bae50SIngo Molnar apic_write(APIC_LVT0, value); 2281f62bae50SIngo Molnar } else { 2282f62bae50SIngo Molnar /* Disable LVT0 */ 2283f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_LVT_MASKED); 2284f62bae50SIngo Molnar } 2285f62bae50SIngo Molnar 2286f62bae50SIngo Molnar /* 2287f62bae50SIngo Molnar * For LVT1 make it edge triggered, active high, 2288f62bae50SIngo Molnar * nmi and enabled 2289f62bae50SIngo Molnar */ 2290f62bae50SIngo Molnar value = apic_read(APIC_LVT1); 2291f62bae50SIngo Molnar value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2292f62bae50SIngo Molnar APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2293f62bae50SIngo Molnar APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2294f62bae50SIngo Molnar value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2295f62bae50SIngo Molnar value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 2296f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 2297f62bae50SIngo Molnar } 2298f62bae50SIngo Molnar 22998f54969dSGu Zheng /* 23008f54969dSGu Zheng * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated 23018f54969dSGu Zheng * contiguously, it equals to current allocated max logical CPU ID plus 1. 230212bf98b9SDou Liyang * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range, 230312bf98b9SDou Liyang * so the maximum of nr_logical_cpuids is nr_cpu_ids. 23048f54969dSGu Zheng * 23058f54969dSGu Zheng * NOTE: Reserve 0 for BSP. 23068f54969dSGu Zheng */ 23078f54969dSGu Zheng static int nr_logical_cpuids = 1; 23088f54969dSGu Zheng 23098f54969dSGu Zheng /* 23108f54969dSGu Zheng * Used to store mapping between logical CPU IDs and APIC IDs. 23118f54969dSGu Zheng */ 23128f54969dSGu Zheng static int cpuid_to_apicid[] = { 23138f54969dSGu Zheng [0 ... NR_CPUS - 1] = -1, 23148f54969dSGu Zheng }; 23158f54969dSGu Zheng 2316d0055f35SVlastimil Babka #ifdef CONFIG_SMP 23176a4d2657SThomas Gleixner /** 23186a4d2657SThomas Gleixner * apic_id_is_primary_thread - Check whether APIC ID belongs to a primary thread 231944eb5a7eSYi Wang * @apicid: APIC ID to check 23206a4d2657SThomas Gleixner */ 23216a4d2657SThomas Gleixner bool apic_id_is_primary_thread(unsigned int apicid) 23226a4d2657SThomas Gleixner { 23236a4d2657SThomas Gleixner u32 mask; 23246a4d2657SThomas Gleixner 23256a4d2657SThomas Gleixner if (smp_num_siblings == 1) 23266a4d2657SThomas Gleixner return true; 23276a4d2657SThomas Gleixner /* Isolate the SMT bit(s) in the APICID and check for 0 */ 23286a4d2657SThomas Gleixner mask = (1U << (fls(smp_num_siblings) - 1)) - 1; 23296a4d2657SThomas Gleixner return !(apicid & mask); 23306a4d2657SThomas Gleixner } 2331d0055f35SVlastimil Babka #endif 23326a4d2657SThomas Gleixner 23338f54969dSGu Zheng /* 23348f54969dSGu Zheng * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids 23358f54969dSGu Zheng * and cpuid_to_apicid[] synchronized. 23368f54969dSGu Zheng */ 23378f54969dSGu Zheng static int allocate_logical_cpuid(int apicid) 23388f54969dSGu Zheng { 23398f54969dSGu Zheng int i; 23408f54969dSGu Zheng 23418f54969dSGu Zheng /* 23428f54969dSGu Zheng * cpuid <-> apicid mapping is persistent, so when a cpu is up, 23438f54969dSGu Zheng * check if the kernel has allocated a cpuid for it. 23448f54969dSGu Zheng */ 23458f54969dSGu Zheng for (i = 0; i < nr_logical_cpuids; i++) { 23468f54969dSGu Zheng if (cpuid_to_apicid[i] == apicid) 23478f54969dSGu Zheng return i; 23488f54969dSGu Zheng } 23498f54969dSGu Zheng 23508f54969dSGu Zheng /* Allocate a new cpuid. */ 23518f54969dSGu Zheng if (nr_logical_cpuids >= nr_cpu_ids) { 23529b130ad5SAlexey Dobriyan WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. " 23538f54969dSGu Zheng "Processor %d/0x%x and the rest are ignored.\n", 2354bb3f0a52SDou Liyang nr_cpu_ids, nr_logical_cpuids, apicid); 2355bb3f0a52SDou Liyang return -EINVAL; 23568f54969dSGu Zheng } 23578f54969dSGu Zheng 23588f54969dSGu Zheng cpuid_to_apicid[nr_logical_cpuids] = apicid; 23598f54969dSGu Zheng return nr_logical_cpuids++; 23608f54969dSGu Zheng } 23618f54969dSGu Zheng 23622b85b3d2SDou Liyang int generic_processor_info(int apicid, int version) 2363f62bae50SIngo Molnar { 236414cb6dcfSVivek Goyal int cpu, max = nr_cpu_ids; 236514cb6dcfSVivek Goyal bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, 236614cb6dcfSVivek Goyal phys_cpu_present_map); 236714cb6dcfSVivek Goyal 236814cb6dcfSVivek Goyal /* 2369151e0c7dSHATAYAMA Daisuke * boot_cpu_physical_apicid is designed to have the apicid 2370151e0c7dSHATAYAMA Daisuke * returned by read_apic_id(), i.e, the apicid of the 2371151e0c7dSHATAYAMA Daisuke * currently booting-up processor. However, on some platforms, 23725b4d1dbcSH. Peter Anvin * it is temporarily modified by the apicid reported as BSP 2373151e0c7dSHATAYAMA Daisuke * through MP table. Concretely: 2374151e0c7dSHATAYAMA Daisuke * 2375151e0c7dSHATAYAMA Daisuke * - arch/x86/kernel/mpparse.c: MP_processor_info() 2376151e0c7dSHATAYAMA Daisuke * - arch/x86/mm/amdtopology.c: amd_numa_init() 2377151e0c7dSHATAYAMA Daisuke * 2378151e0c7dSHATAYAMA Daisuke * This function is executed with the modified 2379151e0c7dSHATAYAMA Daisuke * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel 2380151e0c7dSHATAYAMA Daisuke * parameter doesn't work to disable APs on kdump 2nd kernel. 2381151e0c7dSHATAYAMA Daisuke * 2382151e0c7dSHATAYAMA Daisuke * Since fixing handling of boot_cpu_physical_apicid requires 2383151e0c7dSHATAYAMA Daisuke * another discussion and tests on each platform, we leave it 2384151e0c7dSHATAYAMA Daisuke * for now and here we use read_apic_id() directly in this 2385e2329b42SDou Liyang * function, generic_processor_info(). 2386151e0c7dSHATAYAMA Daisuke */ 2387151e0c7dSHATAYAMA Daisuke if (disabled_cpu_apicid != BAD_APICID && 2388151e0c7dSHATAYAMA Daisuke disabled_cpu_apicid != read_apic_id() && 2389151e0c7dSHATAYAMA Daisuke disabled_cpu_apicid == apicid) { 2390151e0c7dSHATAYAMA Daisuke int thiscpu = num_processors + disabled_cpus; 2391151e0c7dSHATAYAMA Daisuke 23928d3bcc44SKefeng Wang pr_warn("APIC: Disabling requested cpu." 23938d3bcc44SKefeng Wang " Processor %d/0x%x ignored.\n", thiscpu, apicid); 2394151e0c7dSHATAYAMA Daisuke 2395151e0c7dSHATAYAMA Daisuke disabled_cpus++; 2396151e0c7dSHATAYAMA Daisuke return -ENODEV; 2397151e0c7dSHATAYAMA Daisuke } 2398151e0c7dSHATAYAMA Daisuke 2399151e0c7dSHATAYAMA Daisuke /* 240014cb6dcfSVivek Goyal * If boot cpu has not been detected yet, then only allow upto 240114cb6dcfSVivek Goyal * nr_cpu_ids - 1 processors and keep one slot free for boot cpu 240214cb6dcfSVivek Goyal */ 240314cb6dcfSVivek Goyal if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && 240414cb6dcfSVivek Goyal apicid != boot_cpu_physical_apicid) { 240514cb6dcfSVivek Goyal int thiscpu = max + disabled_cpus - 1; 240614cb6dcfSVivek Goyal 24078d3bcc44SKefeng Wang pr_warn("APIC: NR_CPUS/possible_cpus limit of %i almost" 240814cb6dcfSVivek Goyal " reached. Keeping one slot for boot cpu." 240914cb6dcfSVivek Goyal " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 241014cb6dcfSVivek Goyal 241114cb6dcfSVivek Goyal disabled_cpus++; 24127e1f85f9SJiang Liu return -ENODEV; 241314cb6dcfSVivek Goyal } 2414f62bae50SIngo Molnar 2415f62bae50SIngo Molnar if (num_processors >= nr_cpu_ids) { 2416f62bae50SIngo Molnar int thiscpu = max + disabled_cpus; 2417f62bae50SIngo Molnar 24188d3bcc44SKefeng Wang pr_warn("APIC: NR_CPUS/possible_cpus limit of %i reached. " 24198d3bcc44SKefeng Wang "Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2420f62bae50SIngo Molnar 2421f62bae50SIngo Molnar disabled_cpus++; 24227e1f85f9SJiang Liu return -EINVAL; 2423f62bae50SIngo Molnar } 2424f62bae50SIngo Molnar 2425f62bae50SIngo Molnar if (apicid == boot_cpu_physical_apicid) { 2426f62bae50SIngo Molnar /* 2427f62bae50SIngo Molnar * x86_bios_cpu_apicid is required to have processors listed 2428f62bae50SIngo Molnar * in same order as logical cpu numbers. Hence the first 2429f62bae50SIngo Molnar * entry is BSP, and so on. 2430e5fea868SYinghai Lu * boot_cpu_init() already hold bit 0 in cpu_present_mask 2431e5fea868SYinghai Lu * for BSP. 2432f62bae50SIngo Molnar */ 2433f62bae50SIngo Molnar cpu = 0; 24348f54969dSGu Zheng 24358f54969dSGu Zheng /* Logical cpuid 0 is reserved for BSP. */ 24368f54969dSGu Zheng cpuid_to_apicid[0] = apicid; 24378f54969dSGu Zheng } else { 24388f54969dSGu Zheng cpu = allocate_logical_cpuid(apicid); 24398f54969dSGu Zheng if (cpu < 0) { 24408f54969dSGu Zheng disabled_cpus++; 24418f54969dSGu Zheng return -EINVAL; 24428f54969dSGu Zheng } 24438f54969dSGu Zheng } 2444e5fea868SYinghai Lu 2445e5fea868SYinghai Lu /* 2446e5fea868SYinghai Lu * Validate version 2447e5fea868SYinghai Lu */ 2448e5fea868SYinghai Lu if (version == 0x0) { 24498d3bcc44SKefeng Wang pr_warn("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", 2450e5fea868SYinghai Lu cpu, apicid); 2451e5fea868SYinghai Lu version = 0x10; 2452f62bae50SIngo Molnar } 2453e5fea868SYinghai Lu 2454cff9ab2bSDenys Vlasenko if (version != boot_cpu_apic_version) { 24558d3bcc44SKefeng Wang pr_warn("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", 2456cff9ab2bSDenys Vlasenko boot_cpu_apic_version, cpu, version); 2457e5fea868SYinghai Lu } 2458e5fea868SYinghai Lu 2459f62bae50SIngo Molnar if (apicid > max_physical_apicid) 2460f62bae50SIngo Molnar max_physical_apicid = apicid; 2461f62bae50SIngo Molnar 2462f62bae50SIngo Molnar #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 2463f62bae50SIngo Molnar early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 2464f62bae50SIngo Molnar early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 2465f62bae50SIngo Molnar #endif 2466acb8bc09STejun Heo #ifdef CONFIG_X86_32 2467acb8bc09STejun Heo early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 2468acb8bc09STejun Heo apic->x86_32_early_logical_apicid(cpu); 2469acb8bc09STejun Heo #endif 2470f62bae50SIngo Molnar set_cpu_possible(cpu, true); 2471f7c28833SGu Zheng physid_set(apicid, phys_cpu_present_map); 2472f62bae50SIngo Molnar set_cpu_present(cpu, true); 24732b85b3d2SDou Liyang num_processors++; 24747e1f85f9SJiang Liu 24757e1f85f9SJiang Liu return cpu; 2476f62bae50SIngo Molnar } 2477f62bae50SIngo Molnar 2478f62bae50SIngo Molnar int hard_smp_processor_id(void) 2479f62bae50SIngo Molnar { 2480f62bae50SIngo Molnar return read_apic_id(); 2481f62bae50SIngo Molnar } 2482f62bae50SIngo Molnar 2483f62bae50SIngo Molnar /* 24841551df64SMichael S. Tsirkin * Override the generic EOI implementation with an optimized version. 24851551df64SMichael S. Tsirkin * Only called during early boot when only one CPU is active and with 24861551df64SMichael S. Tsirkin * interrupts disabled, so we know this does not race with actual APIC driver 24871551df64SMichael S. Tsirkin * use. 24881551df64SMichael S. Tsirkin */ 24891551df64SMichael S. Tsirkin void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) 24901551df64SMichael S. Tsirkin { 24911551df64SMichael S. Tsirkin struct apic **drv; 24921551df64SMichael S. Tsirkin 24931551df64SMichael S. Tsirkin for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { 24941551df64SMichael S. Tsirkin /* Should happen once for each apic */ 24951551df64SMichael S. Tsirkin WARN_ON((*drv)->eoi_write == eoi_write); 24968ca22552SWanpeng Li (*drv)->native_eoi_write = (*drv)->eoi_write; 24971551df64SMichael S. Tsirkin (*drv)->eoi_write = eoi_write; 24981551df64SMichael S. Tsirkin } 24991551df64SMichael S. Tsirkin } 25001551df64SMichael S. Tsirkin 2501374aab33SThomas Gleixner static void __init apic_bsp_up_setup(void) 250205f7e46dSThomas Gleixner { 2503374aab33SThomas Gleixner #ifdef CONFIG_X86_64 25045d64d209SDou Liyang apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid)); 2505374aab33SThomas Gleixner #else 250605f7e46dSThomas Gleixner /* 2507374aab33SThomas Gleixner * Hack: In case of kdump, after a crash, kernel might be booting 2508374aab33SThomas Gleixner * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 2509374aab33SThomas Gleixner * might be zero if read from MP tables. Get it from LAPIC. 251005f7e46dSThomas Gleixner */ 2511374aab33SThomas Gleixner # ifdef CONFIG_CRASH_DUMP 2512374aab33SThomas Gleixner boot_cpu_physical_apicid = read_apic_id(); 2513374aab33SThomas Gleixner # endif 2514374aab33SThomas Gleixner #endif 2515374aab33SThomas Gleixner physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 251605f7e46dSThomas Gleixner } 251705f7e46dSThomas Gleixner 251805f7e46dSThomas Gleixner /** 251905f7e46dSThomas Gleixner * apic_bsp_setup - Setup function for local apic and io-apic 2520374aab33SThomas Gleixner * @upmode: Force UP mode (for APIC_init_uniprocessor) 252105f7e46dSThomas Gleixner */ 2522748b170cSThomas Gleixner static void __init apic_bsp_setup(bool upmode) 252305f7e46dSThomas Gleixner { 252405f7e46dSThomas Gleixner connect_bsp_APIC(); 2525374aab33SThomas Gleixner if (upmode) 2526374aab33SThomas Gleixner apic_bsp_up_setup(); 252705f7e46dSThomas Gleixner setup_local_APIC(); 252805f7e46dSThomas Gleixner 252905f7e46dSThomas Gleixner enable_IO_APIC(); 2530374aab33SThomas Gleixner end_local_APIC_setup(); 2531374aab33SThomas Gleixner irq_remap_enable_fault_handling(); 253205f7e46dSThomas Gleixner setup_IO_APIC(); 2533e714a91fSThomas Gleixner } 2534e714a91fSThomas Gleixner 253530b8b006SThomas Gleixner #ifdef CONFIG_UP_LATE_INIT 253630b8b006SThomas Gleixner void __init up_late_init(void) 253730b8b006SThomas Gleixner { 25380c759131SDou Liyang if (apic_intr_mode == APIC_PIC) 25390c759131SDou Liyang return; 25400c759131SDou Liyang 25410c759131SDou Liyang /* Setup local timer */ 25420c759131SDou Liyang x86_init.timers.setup_percpu_clockev(); 254330b8b006SThomas Gleixner } 254430b8b006SThomas Gleixner #endif 254530b8b006SThomas Gleixner 2546e714a91fSThomas Gleixner /* 2547f62bae50SIngo Molnar * Power management 2548f62bae50SIngo Molnar */ 2549f62bae50SIngo Molnar #ifdef CONFIG_PM 2550f62bae50SIngo Molnar 2551f62bae50SIngo Molnar static struct { 2552f62bae50SIngo Molnar /* 2553f62bae50SIngo Molnar * 'active' is true if the local APIC was enabled by us and 2554f62bae50SIngo Molnar * not the BIOS; this signifies that we are also responsible 2555f62bae50SIngo Molnar * for disabling it before entering apm/acpi suspend 2556f62bae50SIngo Molnar */ 2557f62bae50SIngo Molnar int active; 2558f62bae50SIngo Molnar /* r/w apic fields */ 2559f62bae50SIngo Molnar unsigned int apic_id; 2560f62bae50SIngo Molnar unsigned int apic_taskpri; 2561f62bae50SIngo Molnar unsigned int apic_ldr; 2562f62bae50SIngo Molnar unsigned int apic_dfr; 2563f62bae50SIngo Molnar unsigned int apic_spiv; 2564f62bae50SIngo Molnar unsigned int apic_lvtt; 2565f62bae50SIngo Molnar unsigned int apic_lvtpc; 2566f62bae50SIngo Molnar unsigned int apic_lvt0; 2567f62bae50SIngo Molnar unsigned int apic_lvt1; 2568f62bae50SIngo Molnar unsigned int apic_lvterr; 2569f62bae50SIngo Molnar unsigned int apic_tmict; 2570f62bae50SIngo Molnar unsigned int apic_tdcr; 2571f62bae50SIngo Molnar unsigned int apic_thmr; 257242baa258SJuergen Gross unsigned int apic_cmci; 2573f62bae50SIngo Molnar } apic_pm_state; 2574f62bae50SIngo Molnar 2575f3c6ea1bSRafael J. Wysocki static int lapic_suspend(void) 2576f62bae50SIngo Molnar { 2577f62bae50SIngo Molnar unsigned long flags; 2578f62bae50SIngo Molnar int maxlvt; 2579f62bae50SIngo Molnar 2580f62bae50SIngo Molnar if (!apic_pm_state.active) 2581f62bae50SIngo Molnar return 0; 2582f62bae50SIngo Molnar 2583f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 2584f62bae50SIngo Molnar 2585f62bae50SIngo Molnar apic_pm_state.apic_id = apic_read(APIC_ID); 2586f62bae50SIngo Molnar apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2587f62bae50SIngo Molnar apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2588f62bae50SIngo Molnar apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2589f62bae50SIngo Molnar apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2590f62bae50SIngo Molnar apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2591f62bae50SIngo Molnar if (maxlvt >= 4) 2592f62bae50SIngo Molnar apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2593f62bae50SIngo Molnar apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2594f62bae50SIngo Molnar apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2595f62bae50SIngo Molnar apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2596f62bae50SIngo Molnar apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2597f62bae50SIngo Molnar apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 25984efc0670SAndi Kleen #ifdef CONFIG_X86_THERMAL_VECTOR 2599f62bae50SIngo Molnar if (maxlvt >= 5) 2600f62bae50SIngo Molnar apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2601f62bae50SIngo Molnar #endif 260242baa258SJuergen Gross #ifdef CONFIG_X86_MCE_INTEL 260342baa258SJuergen Gross if (maxlvt >= 6) 260442baa258SJuergen Gross apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI); 260542baa258SJuergen Gross #endif 2606f62bae50SIngo Molnar 2607f62bae50SIngo Molnar local_irq_save(flags); 26080f378d73STony W Wang-oc 26090f378d73STony W Wang-oc /* 26100f378d73STony W Wang-oc * Mask IOAPIC before disabling the local APIC to prevent stale IRR 26110f378d73STony W Wang-oc * entries on some implementations. 26120f378d73STony W Wang-oc */ 26130f378d73STony W Wang-oc mask_ioapic_entries(); 26140f378d73STony W Wang-oc 2615f62bae50SIngo Molnar disable_local_APIC(); 2616fc1edaf9SSuresh Siddha 261795a02e97SSuresh Siddha irq_remapping_disable(); 2618fc1edaf9SSuresh Siddha 2619f62bae50SIngo Molnar local_irq_restore(flags); 2620f62bae50SIngo Molnar return 0; 2621f62bae50SIngo Molnar } 2622f62bae50SIngo Molnar 2623f3c6ea1bSRafael J. Wysocki static void lapic_resume(void) 2624f62bae50SIngo Molnar { 2625f62bae50SIngo Molnar unsigned int l, h; 2626f62bae50SIngo Molnar unsigned long flags; 262731dce14aSSuresh Siddha int maxlvt; 2628b24696bcSFenghua Yu 2629f62bae50SIngo Molnar if (!apic_pm_state.active) 2630f3c6ea1bSRafael J. Wysocki return; 2631f62bae50SIngo Molnar 2632b24696bcSFenghua Yu local_irq_save(flags); 2633336224baSJoerg Roedel 263431dce14aSSuresh Siddha /* 263531dce14aSSuresh Siddha * IO-APIC and PIC have their own resume routines. 263631dce14aSSuresh Siddha * We just mask them here to make sure the interrupt 263731dce14aSSuresh Siddha * subsystem is completely quiet while we enable x2apic 263831dce14aSSuresh Siddha * and interrupt-remapping. 263931dce14aSSuresh Siddha */ 264031dce14aSSuresh Siddha mask_ioapic_entries(); 2641b81bb373SJacob Pan legacy_pic->mask_all(); 2642f62bae50SIngo Molnar 2643659006bfSThomas Gleixner if (x2apic_mode) { 2644659006bfSThomas Gleixner __x2apic_enable(); 2645659006bfSThomas Gleixner } else { 2646f62bae50SIngo Molnar /* 2647f62bae50SIngo Molnar * Make sure the APICBASE points to the right address 2648f62bae50SIngo Molnar * 2649f62bae50SIngo Molnar * FIXME! This will be wrong if we ever support suspend on 2650f62bae50SIngo Molnar * SMP! We'll need to do this as part of the CPU restore! 2651f62bae50SIngo Molnar */ 2652cbf2829bSBryan O'Donoghue if (boot_cpu_data.x86 >= 6) { 2653f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, l, h); 2654f62bae50SIngo Molnar l &= ~MSR_IA32_APICBASE_BASE; 2655f62bae50SIngo Molnar l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2656f62bae50SIngo Molnar wrmsr(MSR_IA32_APICBASE, l, h); 2657f62bae50SIngo Molnar } 2658cbf2829bSBryan O'Donoghue } 2659f62bae50SIngo Molnar 2660b24696bcSFenghua Yu maxlvt = lapic_get_maxlvt(); 2661f62bae50SIngo Molnar apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2662f62bae50SIngo Molnar apic_write(APIC_ID, apic_pm_state.apic_id); 2663f62bae50SIngo Molnar apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2664f62bae50SIngo Molnar apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2665f62bae50SIngo Molnar apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2666f62bae50SIngo Molnar apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2667f62bae50SIngo Molnar apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2668f62bae50SIngo Molnar apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 266942baa258SJuergen Gross #ifdef CONFIG_X86_THERMAL_VECTOR 2670f62bae50SIngo Molnar if (maxlvt >= 5) 2671f62bae50SIngo Molnar apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2672f62bae50SIngo Molnar #endif 267342baa258SJuergen Gross #ifdef CONFIG_X86_MCE_INTEL 267442baa258SJuergen Gross if (maxlvt >= 6) 267542baa258SJuergen Gross apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci); 267642baa258SJuergen Gross #endif 2677f62bae50SIngo Molnar if (maxlvt >= 4) 2678f62bae50SIngo Molnar apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2679f62bae50SIngo Molnar apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2680f62bae50SIngo Molnar apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2681f62bae50SIngo Molnar apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2682f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 2683f62bae50SIngo Molnar apic_read(APIC_ESR); 2684f62bae50SIngo Molnar apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2685f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 2686f62bae50SIngo Molnar apic_read(APIC_ESR); 2687f62bae50SIngo Molnar 268895a02e97SSuresh Siddha irq_remapping_reenable(x2apic_mode); 268931dce14aSSuresh Siddha 2690f62bae50SIngo Molnar local_irq_restore(flags); 2691f62bae50SIngo Molnar } 2692f62bae50SIngo Molnar 2693f62bae50SIngo Molnar /* 2694f62bae50SIngo Molnar * This device has no shutdown method - fully functioning local APICs 2695f62bae50SIngo Molnar * are needed on every CPU up until machine_halt/restart/poweroff. 2696f62bae50SIngo Molnar */ 2697f62bae50SIngo Molnar 2698f3c6ea1bSRafael J. Wysocki static struct syscore_ops lapic_syscore_ops = { 2699f62bae50SIngo Molnar .resume = lapic_resume, 2700f62bae50SIngo Molnar .suspend = lapic_suspend, 2701f62bae50SIngo Molnar }; 2702f62bae50SIngo Molnar 2703148f9bb8SPaul Gortmaker static void apic_pm_activate(void) 2704f62bae50SIngo Molnar { 2705f62bae50SIngo Molnar apic_pm_state.active = 1; 2706f62bae50SIngo Molnar } 2707f62bae50SIngo Molnar 2708f62bae50SIngo Molnar static int __init init_lapic_sysfs(void) 2709f62bae50SIngo Molnar { 2710f62bae50SIngo Molnar /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 271193984fbdSBorislav Petkov if (boot_cpu_has(X86_FEATURE_APIC)) 2712f3c6ea1bSRafael J. Wysocki register_syscore_ops(&lapic_syscore_ops); 2713f62bae50SIngo Molnar 2714f3c6ea1bSRafael J. Wysocki return 0; 2715f62bae50SIngo Molnar } 2716b24696bcSFenghua Yu 2717b24696bcSFenghua Yu /* local apic needs to resume before other devices access its registers. */ 2718b24696bcSFenghua Yu core_initcall(init_lapic_sysfs); 2719f62bae50SIngo Molnar 2720f62bae50SIngo Molnar #else /* CONFIG_PM */ 2721f62bae50SIngo Molnar 2722f62bae50SIngo Molnar static void apic_pm_activate(void) { } 2723f62bae50SIngo Molnar 2724f62bae50SIngo Molnar #endif /* CONFIG_PM */ 2725f62bae50SIngo Molnar 2726f62bae50SIngo Molnar #ifdef CONFIG_X86_64 2727e0e42142SYinghai Lu 2728148f9bb8SPaul Gortmaker static int multi_checked; 2729148f9bb8SPaul Gortmaker static int multi; 2730e0e42142SYinghai Lu 2731148f9bb8SPaul Gortmaker static int set_multi(const struct dmi_system_id *d) 2732e0e42142SYinghai Lu { 2733e0e42142SYinghai Lu if (multi) 2734e0e42142SYinghai Lu return 0; 27356f0aced6SCyrill Gorcunov pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2736e0e42142SYinghai Lu multi = 1; 2737e0e42142SYinghai Lu return 0; 2738e0e42142SYinghai Lu } 2739e0e42142SYinghai Lu 2740148f9bb8SPaul Gortmaker static const struct dmi_system_id multi_dmi_table[] = { 2741e0e42142SYinghai Lu { 2742e0e42142SYinghai Lu .callback = set_multi, 2743e0e42142SYinghai Lu .ident = "IBM System Summit2", 2744e0e42142SYinghai Lu .matches = { 2745e0e42142SYinghai Lu DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2746e0e42142SYinghai Lu DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2747e0e42142SYinghai Lu }, 2748e0e42142SYinghai Lu }, 2749e0e42142SYinghai Lu {} 2750e0e42142SYinghai Lu }; 2751e0e42142SYinghai Lu 2752148f9bb8SPaul Gortmaker static void dmi_check_multi(void) 2753e0e42142SYinghai Lu { 2754e0e42142SYinghai Lu if (multi_checked) 2755e0e42142SYinghai Lu return; 2756e0e42142SYinghai Lu 2757e0e42142SYinghai Lu dmi_check_system(multi_dmi_table); 2758e0e42142SYinghai Lu multi_checked = 1; 2759e0e42142SYinghai Lu } 2760f62bae50SIngo Molnar 2761f62bae50SIngo Molnar /* 2762e0e42142SYinghai Lu * apic_is_clustered_box() -- Check if we can expect good TSC 2763e0e42142SYinghai Lu * 2764e0e42142SYinghai Lu * Thus far, the major user of this is IBM's Summit2 series: 2765e0e42142SYinghai Lu * Clustered boxes may have unsynced TSC problems if they are 2766e0e42142SYinghai Lu * multi-chassis. 2767e0e42142SYinghai Lu * Use DMI to check them 2768f62bae50SIngo Molnar */ 2769148f9bb8SPaul Gortmaker int apic_is_clustered_box(void) 2770e0e42142SYinghai Lu { 2771e0e42142SYinghai Lu dmi_check_multi(); 2772411cf9eeSOren Twaig return multi; 2773f62bae50SIngo Molnar } 2774f62bae50SIngo Molnar #endif 2775f62bae50SIngo Molnar 2776f62bae50SIngo Molnar /* 2777f62bae50SIngo Molnar * APIC command line parameters 2778f62bae50SIngo Molnar */ 2779f62bae50SIngo Molnar static int __init setup_disableapic(char *arg) 2780f62bae50SIngo Molnar { 2781f62bae50SIngo Molnar disable_apic = 1; 2782f62bae50SIngo Molnar setup_clear_cpu_cap(X86_FEATURE_APIC); 2783f62bae50SIngo Molnar return 0; 2784f62bae50SIngo Molnar } 2785f62bae50SIngo Molnar early_param("disableapic", setup_disableapic); 2786f62bae50SIngo Molnar 2787f62bae50SIngo Molnar /* same as disableapic, for compatibility */ 2788f62bae50SIngo Molnar static int __init setup_nolapic(char *arg) 2789f62bae50SIngo Molnar { 2790f62bae50SIngo Molnar return setup_disableapic(arg); 2791f62bae50SIngo Molnar } 2792f62bae50SIngo Molnar early_param("nolapic", setup_nolapic); 2793f62bae50SIngo Molnar 2794f62bae50SIngo Molnar static int __init parse_lapic_timer_c2_ok(char *arg) 2795f62bae50SIngo Molnar { 2796f62bae50SIngo Molnar local_apic_timer_c2_ok = 1; 2797f62bae50SIngo Molnar return 0; 2798f62bae50SIngo Molnar } 2799f62bae50SIngo Molnar early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2800f62bae50SIngo Molnar 2801f62bae50SIngo Molnar static int __init parse_disable_apic_timer(char *arg) 2802f62bae50SIngo Molnar { 2803f62bae50SIngo Molnar disable_apic_timer = 1; 2804f62bae50SIngo Molnar return 0; 2805f62bae50SIngo Molnar } 2806f62bae50SIngo Molnar early_param("noapictimer", parse_disable_apic_timer); 2807f62bae50SIngo Molnar 2808f62bae50SIngo Molnar static int __init parse_nolapic_timer(char *arg) 2809f62bae50SIngo Molnar { 2810f62bae50SIngo Molnar disable_apic_timer = 1; 2811f62bae50SIngo Molnar return 0; 2812f62bae50SIngo Molnar } 2813f62bae50SIngo Molnar early_param("nolapic_timer", parse_nolapic_timer); 2814f62bae50SIngo Molnar 2815f62bae50SIngo Molnar static int __init apic_set_verbosity(char *arg) 2816f62bae50SIngo Molnar { 2817f62bae50SIngo Molnar if (!arg) { 2818f62bae50SIngo Molnar #ifdef CONFIG_X86_64 2819f62bae50SIngo Molnar skip_ioapic_setup = 0; 2820f62bae50SIngo Molnar return 0; 2821f62bae50SIngo Molnar #endif 2822f62bae50SIngo Molnar return -EINVAL; 2823f62bae50SIngo Molnar } 2824f62bae50SIngo Molnar 2825f62bae50SIngo Molnar if (strcmp("debug", arg) == 0) 2826f62bae50SIngo Molnar apic_verbosity = APIC_DEBUG; 2827f62bae50SIngo Molnar else if (strcmp("verbose", arg) == 0) 2828f62bae50SIngo Molnar apic_verbosity = APIC_VERBOSE; 28294fcab669SDou Liyang #ifdef CONFIG_X86_64 2830f62bae50SIngo Molnar else { 28318d3bcc44SKefeng Wang pr_warn("APIC Verbosity level %s not recognised" 2832f62bae50SIngo Molnar " use apic=verbose or apic=debug\n", arg); 2833f62bae50SIngo Molnar return -EINVAL; 2834f62bae50SIngo Molnar } 28354fcab669SDou Liyang #endif 2836f62bae50SIngo Molnar 2837f62bae50SIngo Molnar return 0; 2838f62bae50SIngo Molnar } 2839f62bae50SIngo Molnar early_param("apic", apic_set_verbosity); 2840f62bae50SIngo Molnar 2841f62bae50SIngo Molnar static int __init lapic_insert_resource(void) 2842f62bae50SIngo Molnar { 2843f62bae50SIngo Molnar if (!apic_phys) 2844f62bae50SIngo Molnar return -1; 2845f62bae50SIngo Molnar 2846f62bae50SIngo Molnar /* Put local APIC into the resource map. */ 2847f62bae50SIngo Molnar lapic_resource.start = apic_phys; 2848f62bae50SIngo Molnar lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2849f62bae50SIngo Molnar insert_resource(&iomem_resource, &lapic_resource); 2850f62bae50SIngo Molnar 2851f62bae50SIngo Molnar return 0; 2852f62bae50SIngo Molnar } 2853f62bae50SIngo Molnar 2854f62bae50SIngo Molnar /* 28551506c8dcSIngo Molnar * need call insert after e820__reserve_resources() 2856f62bae50SIngo Molnar * that is using request_resource 2857f62bae50SIngo Molnar */ 2858f62bae50SIngo Molnar late_initcall(lapic_insert_resource); 2859151e0c7dSHATAYAMA Daisuke 2860151e0c7dSHATAYAMA Daisuke static int __init apic_set_disabled_cpu_apicid(char *arg) 2861151e0c7dSHATAYAMA Daisuke { 2862151e0c7dSHATAYAMA Daisuke if (!arg || !get_option(&arg, &disabled_cpu_apicid)) 2863151e0c7dSHATAYAMA Daisuke return -EINVAL; 2864151e0c7dSHATAYAMA Daisuke 2865151e0c7dSHATAYAMA Daisuke return 0; 2866151e0c7dSHATAYAMA Daisuke } 2867151e0c7dSHATAYAMA Daisuke early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); 2868b7c4948eSHidehiro Kawai 2869b7c4948eSHidehiro Kawai static int __init apic_set_extnmi(char *arg) 2870b7c4948eSHidehiro Kawai { 2871b7c4948eSHidehiro Kawai if (!arg) 2872b7c4948eSHidehiro Kawai return -EINVAL; 2873b7c4948eSHidehiro Kawai 2874b7c4948eSHidehiro Kawai if (!strncmp("all", arg, 3)) 2875b7c4948eSHidehiro Kawai apic_extnmi = APIC_EXTNMI_ALL; 2876b7c4948eSHidehiro Kawai else if (!strncmp("none", arg, 4)) 2877b7c4948eSHidehiro Kawai apic_extnmi = APIC_EXTNMI_NONE; 2878b7c4948eSHidehiro Kawai else if (!strncmp("bsp", arg, 3)) 2879b7c4948eSHidehiro Kawai apic_extnmi = APIC_EXTNMI_BSP; 2880b7c4948eSHidehiro Kawai else { 2881b7c4948eSHidehiro Kawai pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg); 2882b7c4948eSHidehiro Kawai return -EINVAL; 2883b7c4948eSHidehiro Kawai } 2884b7c4948eSHidehiro Kawai 2885b7c4948eSHidehiro Kawai return 0; 2886b7c4948eSHidehiro Kawai } 2887b7c4948eSHidehiro Kawai early_param("apic_extnmi", apic_set_extnmi); 2888