1457c8996SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2f62bae50SIngo Molnar /* 3f62bae50SIngo Molnar * Local APIC handling, local APIC timers 4f62bae50SIngo Molnar * 5f62bae50SIngo Molnar * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6f62bae50SIngo Molnar * 7f62bae50SIngo Molnar * Fixes 8f62bae50SIngo Molnar * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 9f62bae50SIngo Molnar * thanks to Eric Gilmore 10f62bae50SIngo Molnar * and Rolf G. Tews 11f62bae50SIngo Molnar * for testing these extensively. 12f62bae50SIngo Molnar * Maciej W. Rozycki : Various updates and fixes. 13f62bae50SIngo Molnar * Mikael Pettersson : Power Management for UP-APIC. 14f62bae50SIngo Molnar * Pavel Machek and 15f62bae50SIngo Molnar * Mikael Pettersson : PM converted to driver model. 16f62bae50SIngo Molnar */ 17f62bae50SIngo Molnar 18cdd6c482SIngo Molnar #include <linux/perf_event.h> 19f62bae50SIngo Molnar #include <linux/kernel_stat.h> 20f62bae50SIngo Molnar #include <linux/mc146818rtc.h> 21f62bae50SIngo Molnar #include <linux/acpi_pmtmr.h> 22f62bae50SIngo Molnar #include <linux/clockchips.h> 23f62bae50SIngo Molnar #include <linux/interrupt.h> 2457c8a661SMike Rapoport #include <linux/memblock.h> 25f62bae50SIngo Molnar #include <linux/ftrace.h> 26f62bae50SIngo Molnar #include <linux/ioport.h> 27186f4360SPaul Gortmaker #include <linux/export.h> 28f3c6ea1bSRafael J. Wysocki #include <linux/syscore_ops.h> 29f62bae50SIngo Molnar #include <linux/delay.h> 30f62bae50SIngo Molnar #include <linux/timex.h> 31334955efSRalf Baechle #include <linux/i8253.h> 32f62bae50SIngo Molnar #include <linux/dmar.h> 33f62bae50SIngo Molnar #include <linux/init.h> 34f62bae50SIngo Molnar #include <linux/cpu.h> 35f62bae50SIngo Molnar #include <linux/dmi.h> 36f62bae50SIngo Molnar #include <linux/smp.h> 37f62bae50SIngo Molnar #include <linux/mm.h> 38f62bae50SIngo Molnar 3983ab8514SSteven Rostedt (Red Hat) #include <asm/trace/irq_vectors.h> 408a8f422dSSuresh Siddha #include <asm/irq_remapping.h> 41fb6a0408SMaciej W. Rozycki #include <asm/pc-conf-reg.h> 42cdd6c482SIngo Molnar #include <asm/perf_event.h> 43736decacSThomas Gleixner #include <asm/x86_init.h> 4460063497SArun Sharma #include <linux/atomic.h> 4525a068b8SDave Hansen #include <asm/barrier.h> 46f62bae50SIngo Molnar #include <asm/mpspec.h> 47f62bae50SIngo Molnar #include <asm/i8259.h> 48f62bae50SIngo Molnar #include <asm/proto.h> 49ad3bc25aSBorislav Petkov #include <asm/traps.h> 50f62bae50SIngo Molnar #include <asm/apic.h> 5113c01139SIngo Molnar #include <asm/acpi.h> 527167d08eSHenrik Kretzschmar #include <asm/io_apic.h> 53f62bae50SIngo Molnar #include <asm/desc.h> 54f62bae50SIngo Molnar #include <asm/hpet.h> 55f62bae50SIngo Molnar #include <asm/mtrr.h> 5616f871bcSRalf Baechle #include <asm/time.h> 57f62bae50SIngo Molnar #include <asm/smp.h> 58638bee71SH. Peter Anvin #include <asm/mce.h> 598c3ba8d0SKerstin Jonsson #include <asm/tsc.h> 602904ed8dSSheng Yang #include <asm/hypervisor.h> 61bd9240a1SPeter Zijlstra #include <asm/cpu_device_id.h> 62bd9240a1SPeter Zijlstra #include <asm/intel-family.h> 63447ae316SNicolai Stange #include <asm/irq_regs.h> 64b8d1d163SDaniel Sneddon #include <asm/cpu.h> 65f62bae50SIngo Molnar 66*79c9a17cSThomas Gleixner #include "local.h" 67*79c9a17cSThomas Gleixner 68f62bae50SIngo Molnar unsigned int num_processors; 69f62bae50SIngo Molnar 70148f9bb8SPaul Gortmaker unsigned disabled_cpus; 71f62bae50SIngo Molnar 72f62bae50SIngo Molnar /* Processor that is doing the boot up */ 736444b40eSSean Christopherson unsigned int boot_cpu_physical_apicid __ro_after_init = -1U; 74cc08e04cSDavid Rientjes EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); 75f62bae50SIngo Molnar 766444b40eSSean Christopherson u8 boot_cpu_apic_version __ro_after_init; 77cff9ab2bSDenys Vlasenko 78f62bae50SIngo Molnar /* 79f62bae50SIngo Molnar * Bitmask of physically existing CPUs: 80f62bae50SIngo Molnar */ 81f62bae50SIngo Molnar physid_mask_t phys_cpu_present_map; 82f62bae50SIngo Molnar 83f62bae50SIngo Molnar /* 84151e0c7dSHATAYAMA Daisuke * Processor to be disabled specified by kernel parameter 85151e0c7dSHATAYAMA Daisuke * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to 86151e0c7dSHATAYAMA Daisuke * avoid undefined behaviour caused by sending INIT from AP to BSP. 87151e0c7dSHATAYAMA Daisuke */ 886444b40eSSean Christopherson static unsigned int disabled_cpu_apicid __ro_after_init = BAD_APICID; 89151e0c7dSHATAYAMA Daisuke 90151e0c7dSHATAYAMA Daisuke /* 91b7c4948eSHidehiro Kawai * This variable controls which CPUs receive external NMIs. By default, 92b7c4948eSHidehiro Kawai * external NMIs are delivered only to the BSP. 93b7c4948eSHidehiro Kawai */ 946444b40eSSean Christopherson static int apic_extnmi __ro_after_init = APIC_EXTNMI_BSP; 95b7c4948eSHidehiro Kawai 96b7c4948eSHidehiro Kawai /* 97ab0f59c6SDavid Woodhouse * Hypervisor supports 15 bits of APIC ID in MSI Extended Destination ID 98ab0f59c6SDavid Woodhouse */ 99ab0f59c6SDavid Woodhouse static bool virt_ext_dest_id __ro_after_init; 100ab0f59c6SDavid Woodhouse 101bea629d5SThomas Gleixner /* For parallel bootup. */ 102bea629d5SThomas Gleixner unsigned long apic_mmio_base __ro_after_init; 103bea629d5SThomas Gleixner 10478c32000SThomas Gleixner static inline bool apic_accessible(void) 10578c32000SThomas Gleixner { 10678c32000SThomas Gleixner return x2apic_mode || apic_mmio_base; 10778c32000SThomas Gleixner } 10878c32000SThomas Gleixner 109ab0f59c6SDavid Woodhouse /* 110f62bae50SIngo Molnar * Map cpu index to physical APIC ID 111f62bae50SIngo Molnar */ 1120816b0f0SVlad Zolotarov DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); 1133e9e57faSVitaly Kuznetsov DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX); 114f62bae50SIngo Molnar EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 1153e9e57faSVitaly Kuznetsov EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); 116f62bae50SIngo Molnar 117f62bae50SIngo Molnar #ifdef CONFIG_X86_32 118f62bae50SIngo Molnar /* Local APIC was disabled by the BIOS and enabled by the kernel */ 1196444b40eSSean Christopherson static int enabled_via_apicbase __ro_after_init; 120f62bae50SIngo Molnar 121c0eaa453SCyrill Gorcunov /* 122c0eaa453SCyrill Gorcunov * Handle interrupt mode configuration register (IMCR). 123c0eaa453SCyrill Gorcunov * This register controls whether the interrupt signals 124c0eaa453SCyrill Gorcunov * that reach the BSP come from the master PIC or from the 125c0eaa453SCyrill Gorcunov * local APIC. Before entering Symmetric I/O Mode, either 126c0eaa453SCyrill Gorcunov * the BIOS or the operating system must switch out of 127c0eaa453SCyrill Gorcunov * PIC Mode by changing the IMCR. 128c0eaa453SCyrill Gorcunov */ 1295cda395fSAlexander van Heukelum static inline void imcr_pic_to_apic(void) 130c0eaa453SCyrill Gorcunov { 131c0eaa453SCyrill Gorcunov /* NMI and 8259 INTR go through APIC */ 132fb6a0408SMaciej W. Rozycki pc_conf_set(PC_CONF_MPS_IMCR, 0x01); 133c0eaa453SCyrill Gorcunov } 134c0eaa453SCyrill Gorcunov 1355cda395fSAlexander van Heukelum static inline void imcr_apic_to_pic(void) 136c0eaa453SCyrill Gorcunov { 137c0eaa453SCyrill Gorcunov /* NMI and 8259 INTR go directly to BSP */ 138fb6a0408SMaciej W. Rozycki pc_conf_set(PC_CONF_MPS_IMCR, 0x00); 139c0eaa453SCyrill Gorcunov } 140f62bae50SIngo Molnar #endif 141f62bae50SIngo Molnar 142279f1461SSuresh Siddha /* 143279f1461SSuresh Siddha * Knob to control our willingness to enable the local APIC. 144279f1461SSuresh Siddha * 145279f1461SSuresh Siddha * +1=force-enable 146279f1461SSuresh Siddha */ 147279f1461SSuresh Siddha static int force_enable_local_apic __initdata; 148dc9788f4SDavid Rientjes 149279f1461SSuresh Siddha /* 150279f1461SSuresh Siddha * APIC command line parameters 151279f1461SSuresh Siddha */ 152279f1461SSuresh Siddha static int __init parse_lapic(char *arg) 153279f1461SSuresh Siddha { 15497f2645fSMasahiro Yamada if (IS_ENABLED(CONFIG_X86_32) && !arg) 155279f1461SSuresh Siddha force_enable_local_apic = 1; 15627cf9298SMathias Krause else if (arg && !strncmp(arg, "notscdeadline", 13)) 157279f1461SSuresh Siddha setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 158279f1461SSuresh Siddha return 0; 159279f1461SSuresh Siddha } 160279f1461SSuresh Siddha early_param("lapic", parse_lapic); 161279f1461SSuresh Siddha 162f62bae50SIngo Molnar #ifdef CONFIG_X86_64 163f62bae50SIngo Molnar static int apic_calibrate_pmtmr __initdata; 164f62bae50SIngo Molnar static __init int setup_apicpmtimer(char *s) 165f62bae50SIngo Molnar { 166f62bae50SIngo Molnar apic_calibrate_pmtmr = 1; 167f62bae50SIngo Molnar notsc_setup(NULL); 16812441ccdSRandy Dunlap return 1; 169f62bae50SIngo Molnar } 170f62bae50SIngo Molnar __setup("apicpmtimer", setup_apicpmtimer); 171f62bae50SIngo Molnar #endif 172f62bae50SIngo Molnar 17381287ad6SThomas Gleixner static unsigned long mp_lapic_addr __ro_after_init; 17449062454SThomas Gleixner bool apic_is_disabled __ro_after_init; 175f62bae50SIngo Molnar /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 17625874a29SHenrik Kretzschmar static int disable_apic_timer __initdata; 177f62bae50SIngo Molnar /* Local APIC timer works in C2 */ 1786444b40eSSean Christopherson int local_apic_timer_c2_ok __ro_after_init; 179f62bae50SIngo Molnar EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 180f62bae50SIngo Molnar 181f62bae50SIngo Molnar /* 182f62bae50SIngo Molnar * Debug level, exported for io_apic.c 183f62bae50SIngo Molnar */ 1846444b40eSSean Christopherson int apic_verbosity __ro_after_init; 185f62bae50SIngo Molnar 1866444b40eSSean Christopherson int pic_mode __ro_after_init; 187f62bae50SIngo Molnar 188f62bae50SIngo Molnar /* Have we found an MP table */ 1896444b40eSSean Christopherson int smp_found_config __ro_after_init; 190f62bae50SIngo Molnar 191f62bae50SIngo Molnar static struct resource lapic_resource = { 192f62bae50SIngo Molnar .name = "Local APIC", 193f62bae50SIngo Molnar .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 194f62bae50SIngo Molnar }; 195f62bae50SIngo Molnar 19652ae346bSDaniel Drake unsigned int lapic_timer_period = 0; 197f62bae50SIngo Molnar 198f62bae50SIngo Molnar static void apic_pm_activate(void); 199f62bae50SIngo Molnar 200f62bae50SIngo Molnar /* 201f62bae50SIngo Molnar * Get the LAPIC version 202f62bae50SIngo Molnar */ 203f62bae50SIngo Molnar static inline int lapic_get_version(void) 204f62bae50SIngo Molnar { 205f62bae50SIngo Molnar return GET_APIC_VERSION(apic_read(APIC_LVR)); 206f62bae50SIngo Molnar } 207f62bae50SIngo Molnar 208f62bae50SIngo Molnar /* 209f62bae50SIngo Molnar * Check, if the APIC is integrated or a separate chip 210f62bae50SIngo Molnar */ 211f62bae50SIngo Molnar static inline int lapic_is_integrated(void) 212f62bae50SIngo Molnar { 213f62bae50SIngo Molnar return APIC_INTEGRATED(lapic_get_version()); 214f62bae50SIngo Molnar } 215f62bae50SIngo Molnar 216f62bae50SIngo Molnar /* 217f62bae50SIngo Molnar * Check, whether this is a modern or a first generation APIC 218f62bae50SIngo Molnar */ 219f62bae50SIngo Molnar static int modern_apic(void) 220f62bae50SIngo Molnar { 221f62bae50SIngo Molnar /* AMD systems use old APIC versions, so check the CPU */ 222f62bae50SIngo Molnar if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 223f62bae50SIngo Molnar boot_cpu_data.x86 >= 0xf) 224f62bae50SIngo Molnar return 1; 225da33dfefSPu Wen 226da33dfefSPu Wen /* Hygon systems use modern APIC */ 227da33dfefSPu Wen if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 228da33dfefSPu Wen return 1; 229da33dfefSPu Wen 230f62bae50SIngo Molnar return lapic_get_version() >= 0x14; 231f62bae50SIngo Molnar } 232f62bae50SIngo Molnar 23308306ce6SCyrill Gorcunov /* 234a933c618SCyrill Gorcunov * right after this call apic become NOOP driven 235a933c618SCyrill Gorcunov * so apic->write/read doesn't do anything 23608306ce6SCyrill Gorcunov */ 23725874a29SHenrik Kretzschmar static void __init apic_disable(void) 23808306ce6SCyrill Gorcunov { 239f88f2b4fSCyrill Gorcunov pr_info("APIC: switched to apic NOOP\n"); 240a933c618SCyrill Gorcunov apic = &apic_noop; 24108306ce6SCyrill Gorcunov } 24208306ce6SCyrill Gorcunov 243f62bae50SIngo Molnar void native_apic_wait_icr_idle(void) 244f62bae50SIngo Molnar { 245f62bae50SIngo Molnar while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 246f62bae50SIngo Molnar cpu_relax(); 247f62bae50SIngo Molnar } 248f62bae50SIngo Molnar 249f62bae50SIngo Molnar u32 native_safe_apic_wait_icr_idle(void) 250f62bae50SIngo Molnar { 251f62bae50SIngo Molnar u32 send_status; 252f62bae50SIngo Molnar int timeout; 253f62bae50SIngo Molnar 254f62bae50SIngo Molnar timeout = 0; 255f62bae50SIngo Molnar do { 256f62bae50SIngo Molnar send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 257f62bae50SIngo Molnar if (!send_status) 258f62bae50SIngo Molnar break; 259b49d7d87SFernando Luis Vazquez Cao inc_irq_stat(icr_read_retry_count); 260f62bae50SIngo Molnar udelay(100); 261f62bae50SIngo Molnar } while (timeout++ < 1000); 262f62bae50SIngo Molnar 263f62bae50SIngo Molnar return send_status; 264f62bae50SIngo Molnar } 265f62bae50SIngo Molnar 266f62bae50SIngo Molnar void native_apic_icr_write(u32 low, u32 id) 267f62bae50SIngo Molnar { 268ea7bdc65SJan Kiszka unsigned long flags; 269ea7bdc65SJan Kiszka 270ea7bdc65SJan Kiszka local_irq_save(flags); 271bf348f66SSuravee Suthikulpanit apic_write(APIC_ICR2, SET_XAPIC_DEST_FIELD(id)); 272f62bae50SIngo Molnar apic_write(APIC_ICR, low); 273ea7bdc65SJan Kiszka local_irq_restore(flags); 274f62bae50SIngo Molnar } 275f62bae50SIngo Molnar 276f62bae50SIngo Molnar u64 native_apic_icr_read(void) 277f62bae50SIngo Molnar { 278f62bae50SIngo Molnar u32 icr1, icr2; 279f62bae50SIngo Molnar 280f62bae50SIngo Molnar icr2 = apic_read(APIC_ICR2); 281f62bae50SIngo Molnar icr1 = apic_read(APIC_ICR); 282f62bae50SIngo Molnar 283f62bae50SIngo Molnar return icr1 | ((u64)icr2 << 32); 284f62bae50SIngo Molnar } 285f62bae50SIngo Molnar 286f62bae50SIngo Molnar #ifdef CONFIG_X86_32 287f62bae50SIngo Molnar /** 288f62bae50SIngo Molnar * get_physical_broadcast - Get number of physical broadcast IDs 289f62bae50SIngo Molnar */ 290f62bae50SIngo Molnar int get_physical_broadcast(void) 291f62bae50SIngo Molnar { 292f62bae50SIngo Molnar return modern_apic() ? 0xff : 0xf; 293f62bae50SIngo Molnar } 294f62bae50SIngo Molnar #endif 295f62bae50SIngo Molnar 296f62bae50SIngo Molnar /** 297f62bae50SIngo Molnar * lapic_get_maxlvt - get the maximum number of local vector table entries 298f62bae50SIngo Molnar */ 299f62bae50SIngo Molnar int lapic_get_maxlvt(void) 300f62bae50SIngo Molnar { 301f62bae50SIngo Molnar /* 302f62bae50SIngo Molnar * - we always have APIC integrated on 64bit mode 303f62bae50SIngo Molnar * - 82489DXs do not report # of LVT entries 304f62bae50SIngo Molnar */ 305ae41a2a4SDou Liyang return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2; 306f62bae50SIngo Molnar } 307f62bae50SIngo Molnar 308f62bae50SIngo Molnar /* 309f62bae50SIngo Molnar * Local APIC timer 310f62bae50SIngo Molnar */ 311f62bae50SIngo Molnar 312f62bae50SIngo Molnar /* Clock divisor */ 313f62bae50SIngo Molnar #define APIC_DIVISOR 16 3141a9e4c56SNicolai Stange #define TSC_DIVISOR 8 315f62bae50SIngo Molnar 316daf3af47SThomas Gleixner /* i82489DX specific */ 317daf3af47SThomas Gleixner #define I82489DX_BASE_DIVIDER (((0x2) << 18)) 318daf3af47SThomas Gleixner 319f62bae50SIngo Molnar /* 320f62bae50SIngo Molnar * This function sets up the local APIC timer, with a timeout of 321f62bae50SIngo Molnar * 'clocks' APIC bus clock. During calibration we actually call 322f62bae50SIngo Molnar * this function twice on the boot CPU, once with a bogus timeout 323f62bae50SIngo Molnar * value, second time for real. The other (noncalibrating) CPUs 324f62bae50SIngo Molnar * call this function only once, with the real, calibrated value. 325f62bae50SIngo Molnar * 326f62bae50SIngo Molnar * We do reads before writes even if unnecessary, to get around the 327f62bae50SIngo Molnar * P5 APIC double write bug. 328f62bae50SIngo Molnar */ 329f62bae50SIngo Molnar static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 330f62bae50SIngo Molnar { 331f62bae50SIngo Molnar unsigned int lvtt_value, tmp_value; 332f62bae50SIngo Molnar 333f62bae50SIngo Molnar lvtt_value = LOCAL_TIMER_VECTOR; 334f62bae50SIngo Molnar if (!oneshot) 335f62bae50SIngo Molnar lvtt_value |= APIC_LVT_TIMER_PERIODIC; 336279f1461SSuresh Siddha else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 337279f1461SSuresh Siddha lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; 338279f1461SSuresh Siddha 339daf3af47SThomas Gleixner /* 340daf3af47SThomas Gleixner * The i82489DX APIC uses bit 18 and 19 for the base divider. This 341daf3af47SThomas Gleixner * overlaps with bit 18 on integrated APICs, but is not documented 342daf3af47SThomas Gleixner * in the SDM. No problem though. i82489DX equipped systems do not 343daf3af47SThomas Gleixner * have TSC deadline timer. 344daf3af47SThomas Gleixner */ 345f62bae50SIngo Molnar if (!lapic_is_integrated()) 346daf3af47SThomas Gleixner lvtt_value |= I82489DX_BASE_DIVIDER; 347f62bae50SIngo Molnar 348f62bae50SIngo Molnar if (!irqen) 349f62bae50SIngo Molnar lvtt_value |= APIC_LVT_MASKED; 350f62bae50SIngo Molnar 351f62bae50SIngo Molnar apic_write(APIC_LVTT, lvtt_value); 352f62bae50SIngo Molnar 353279f1461SSuresh Siddha if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { 3545d7c631dSShaohua Li /* 3555d7c631dSShaohua Li * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, 3565d7c631dSShaohua Li * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. 3575d7c631dSShaohua Li * According to Intel, MFENCE can do the serialization here. 3585d7c631dSShaohua Li */ 3595d7c631dSShaohua Li asm volatile("mfence" : : : "memory"); 360279f1461SSuresh Siddha return; 361279f1461SSuresh Siddha } 362279f1461SSuresh Siddha 363f62bae50SIngo Molnar /* 364f62bae50SIngo Molnar * Divide PICLK by 16 365f62bae50SIngo Molnar */ 366f62bae50SIngo Molnar tmp_value = apic_read(APIC_TDCR); 367f62bae50SIngo Molnar apic_write(APIC_TDCR, 368f62bae50SIngo Molnar (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 369f62bae50SIngo Molnar APIC_TDR_DIV_16); 370f62bae50SIngo Molnar 371f62bae50SIngo Molnar if (!oneshot) 372f62bae50SIngo Molnar apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 373f62bae50SIngo Molnar } 374f62bae50SIngo Molnar 375f62bae50SIngo Molnar /* 376a68c439bSRobert Richter * Setup extended LVT, AMD specific 377f62bae50SIngo Molnar * 378a68c439bSRobert Richter * Software should use the LVT offsets the BIOS provides. The offsets 379a68c439bSRobert Richter * are determined by the subsystems using it like those for MCE 380a68c439bSRobert Richter * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 381a68c439bSRobert Richter * are supported. Beginning with family 10h at least 4 offsets are 382a68c439bSRobert Richter * available. 383f62bae50SIngo Molnar * 384a68c439bSRobert Richter * Since the offsets must be consistent for all cores, we keep track 385a68c439bSRobert Richter * of the LVT offsets in software and reserve the offset for the same 386a68c439bSRobert Richter * vector also to be used on other cores. An offset is freed by 387a68c439bSRobert Richter * setting the entry to APIC_EILVT_MASKED. 388a68c439bSRobert Richter * 389a68c439bSRobert Richter * If the BIOS is right, there should be no conflicts. Otherwise a 390a68c439bSRobert Richter * "[Firmware Bug]: ..." error message is generated. However, if 391a68c439bSRobert Richter * software does not properly determines the offsets, it is not 392a68c439bSRobert Richter * necessarily a BIOS bug. 393f62bae50SIngo Molnar */ 394f62bae50SIngo Molnar 395a68c439bSRobert Richter static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 396f62bae50SIngo Molnar 397a68c439bSRobert Richter static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 398a68c439bSRobert Richter { 399a68c439bSRobert Richter return (old & APIC_EILVT_MASKED) 400a68c439bSRobert Richter || (new == APIC_EILVT_MASKED) 401a68c439bSRobert Richter || ((new & ~APIC_EILVT_MASKED) == old); 402a68c439bSRobert Richter } 403a68c439bSRobert Richter 404a68c439bSRobert Richter static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 405a68c439bSRobert Richter { 4068abc3122SRobert Richter unsigned int rsvd, vector; 407a68c439bSRobert Richter 408a68c439bSRobert Richter if (offset >= APIC_EILVT_NR_MAX) 409a68c439bSRobert Richter return ~0; 410a68c439bSRobert Richter 4118abc3122SRobert Richter rsvd = atomic_read(&eilvt_offsets[offset]); 412a68c439bSRobert Richter do { 4138abc3122SRobert Richter vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ 4148abc3122SRobert Richter if (vector && !eilvt_entry_is_changeable(vector, new)) 415a68c439bSRobert Richter /* may not change if vectors are different */ 416a68c439bSRobert Richter return rsvd; 417f96fb2dfSUros Bizjak } while (!atomic_try_cmpxchg(&eilvt_offsets[offset], &rsvd, new)); 418a68c439bSRobert Richter 419f96fb2dfSUros Bizjak rsvd = new & ~APIC_EILVT_MASKED; 4208abc3122SRobert Richter if (rsvd && rsvd != vector) 4218abc3122SRobert Richter pr_info("LVT offset %d assigned for vector 0x%02x\n", 4228abc3122SRobert Richter offset, rsvd); 4238abc3122SRobert Richter 424a68c439bSRobert Richter return new; 425a68c439bSRobert Richter } 426a68c439bSRobert Richter 427a68c439bSRobert Richter /* 428a68c439bSRobert Richter * If mask=1, the LVT entry does not generate interrupts while mask=0 429cbf74ceaSRobert Richter * enables the vector. See also the BKDGs. Must be called with 430cbf74ceaSRobert Richter * preemption disabled. 431a68c439bSRobert Richter */ 432a68c439bSRobert Richter 43327afdf20SRobert Richter int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 434a68c439bSRobert Richter { 435a68c439bSRobert Richter unsigned long reg = APIC_EILVTn(offset); 436a68c439bSRobert Richter unsigned int new, old, reserved; 437a68c439bSRobert Richter 438a68c439bSRobert Richter new = (mask << 16) | (msg_type << 8) | vector; 439a68c439bSRobert Richter old = apic_read(reg); 440a68c439bSRobert Richter reserved = reserve_eilvt_offset(offset, new); 441a68c439bSRobert Richter 442a68c439bSRobert Richter if (reserved != new) { 443eb48c9cbSRobert Richter pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 444eb48c9cbSRobert Richter "vector 0x%x, but the register is already in use for " 445eb48c9cbSRobert Richter "vector 0x%x on another cpu\n", 446eb48c9cbSRobert Richter smp_processor_id(), reg, offset, new, reserved); 447a68c439bSRobert Richter return -EINVAL; 448a68c439bSRobert Richter } 449a68c439bSRobert Richter 450a68c439bSRobert Richter if (!eilvt_entry_is_changeable(old, new)) { 451eb48c9cbSRobert Richter pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 452eb48c9cbSRobert Richter "vector 0x%x, but the register is already in use for " 453eb48c9cbSRobert Richter "vector 0x%x on this cpu\n", 454eb48c9cbSRobert Richter smp_processor_id(), reg, offset, new, old); 455a68c439bSRobert Richter return -EBUSY; 456a68c439bSRobert Richter } 457a68c439bSRobert Richter 458a68c439bSRobert Richter apic_write(reg, new); 459a68c439bSRobert Richter 460a68c439bSRobert Richter return 0; 461f62bae50SIngo Molnar } 46227afdf20SRobert Richter EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 463f62bae50SIngo Molnar 464f62bae50SIngo Molnar /* 465f62bae50SIngo Molnar * Program the next event, relative to now 466f62bae50SIngo Molnar */ 467f62bae50SIngo Molnar static int lapic_next_event(unsigned long delta, 468f62bae50SIngo Molnar struct clock_event_device *evt) 469f62bae50SIngo Molnar { 470f62bae50SIngo Molnar apic_write(APIC_TMICT, delta); 471f62bae50SIngo Molnar return 0; 472f62bae50SIngo Molnar } 473f62bae50SIngo Molnar 474279f1461SSuresh Siddha static int lapic_next_deadline(unsigned long delta, 475279f1461SSuresh Siddha struct clock_event_device *evt) 476279f1461SSuresh Siddha { 477279f1461SSuresh Siddha u64 tsc; 478279f1461SSuresh Siddha 47925a068b8SDave Hansen /* This MSR is special and need a special fence: */ 48025a068b8SDave Hansen weak_wrmsr_fence(); 48125a068b8SDave Hansen 4824ea1636bSAndy Lutomirski tsc = rdtsc(); 483279f1461SSuresh Siddha wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); 484279f1461SSuresh Siddha return 0; 485279f1461SSuresh Siddha } 486279f1461SSuresh Siddha 487b23d8e52SViresh Kumar static int lapic_timer_shutdown(struct clock_event_device *evt) 488f62bae50SIngo Molnar { 489f62bae50SIngo Molnar unsigned int v; 490f62bae50SIngo Molnar 491f62bae50SIngo Molnar /* Lapic used as dummy for broadcast ? */ 492f62bae50SIngo Molnar if (evt->features & CLOCK_EVT_FEAT_DUMMY) 493b23d8e52SViresh Kumar return 0; 494f62bae50SIngo Molnar 495f62bae50SIngo Molnar v = apic_read(APIC_LVTT); 496f62bae50SIngo Molnar v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 497f62bae50SIngo Molnar apic_write(APIC_LVTT, v); 4986f9b4100SAndreas Herrmann apic_write(APIC_TMICT, 0); 499b23d8e52SViresh Kumar return 0; 500f62bae50SIngo Molnar } 501f62bae50SIngo Molnar 502b23d8e52SViresh Kumar static inline int 503b23d8e52SViresh Kumar lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot) 504b23d8e52SViresh Kumar { 505b23d8e52SViresh Kumar /* Lapic used as dummy for broadcast ? */ 506b23d8e52SViresh Kumar if (evt->features & CLOCK_EVT_FEAT_DUMMY) 507b23d8e52SViresh Kumar return 0; 508b23d8e52SViresh Kumar 50952ae346bSDaniel Drake __setup_APIC_LVTT(lapic_timer_period, oneshot, 1); 510b23d8e52SViresh Kumar return 0; 511b23d8e52SViresh Kumar } 512b23d8e52SViresh Kumar 513b23d8e52SViresh Kumar static int lapic_timer_set_periodic(struct clock_event_device *evt) 514b23d8e52SViresh Kumar { 515b23d8e52SViresh Kumar return lapic_timer_set_periodic_oneshot(evt, false); 516b23d8e52SViresh Kumar } 517b23d8e52SViresh Kumar 518b23d8e52SViresh Kumar static int lapic_timer_set_oneshot(struct clock_event_device *evt) 519b23d8e52SViresh Kumar { 520b23d8e52SViresh Kumar return lapic_timer_set_periodic_oneshot(evt, true); 521f62bae50SIngo Molnar } 522f62bae50SIngo Molnar 523f62bae50SIngo Molnar /* 524f62bae50SIngo Molnar * Local APIC timer broadcast function 525f62bae50SIngo Molnar */ 526f62bae50SIngo Molnar static void lapic_timer_broadcast(const struct cpumask *mask) 527f62bae50SIngo Molnar { 528f62bae50SIngo Molnar #ifdef CONFIG_SMP 529f62bae50SIngo Molnar apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 530f62bae50SIngo Molnar #endif 531f62bae50SIngo Molnar } 532f62bae50SIngo Molnar 53325874a29SHenrik Kretzschmar 53425874a29SHenrik Kretzschmar /* 53525874a29SHenrik Kretzschmar * The local apic timer can be used for any function which is CPU local. 53625874a29SHenrik Kretzschmar */ 53725874a29SHenrik Kretzschmar static struct clock_event_device lapic_clockevent = { 53825874a29SHenrik Kretzschmar .name = "lapic", 539b23d8e52SViresh Kumar .features = CLOCK_EVT_FEAT_PERIODIC | 540b23d8e52SViresh Kumar CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP 541b23d8e52SViresh Kumar | CLOCK_EVT_FEAT_DUMMY, 54225874a29SHenrik Kretzschmar .shift = 32, 543b23d8e52SViresh Kumar .set_state_shutdown = lapic_timer_shutdown, 544b23d8e52SViresh Kumar .set_state_periodic = lapic_timer_set_periodic, 545b23d8e52SViresh Kumar .set_state_oneshot = lapic_timer_set_oneshot, 546914122c3SFrederic Weisbecker .set_state_oneshot_stopped = lapic_timer_shutdown, 54725874a29SHenrik Kretzschmar .set_next_event = lapic_next_event, 54825874a29SHenrik Kretzschmar .broadcast = lapic_timer_broadcast, 54925874a29SHenrik Kretzschmar .rating = 100, 55025874a29SHenrik Kretzschmar .irq = -1, 55125874a29SHenrik Kretzschmar }; 55225874a29SHenrik Kretzschmar static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 55325874a29SHenrik Kretzschmar 554c84cb373SThomas Gleixner static const struct x86_cpu_id deadline_match[] __initconst = { 55566abf238SBorislav Petkov X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(HASWELL_X, X86_STEPPINGS(0x2, 0x2), 0x3a), /* EP */ 55666abf238SBorislav Petkov X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(HASWELL_X, X86_STEPPINGS(0x4, 0x4), 0x0f), /* EX */ 55766abf238SBorislav Petkov 558adefe55eSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL( BROADWELL_X, 0x0b000020), 55966abf238SBorislav Petkov 56066abf238SBorislav Petkov X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x2, 0x2), 0x00000011), 56166abf238SBorislav Petkov X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x3, 0x3), 0x0700000e), 56266abf238SBorislav Petkov X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x4, 0x4), 0x0f00000c), 56366abf238SBorislav Petkov X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x5, 0x5), 0x0e000003), 56466abf238SBorislav Petkov 56566abf238SBorislav Petkov X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x3, 0x3), 0x01000136), 56666abf238SBorislav Petkov X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x4, 0x4), 0x02000014), 56766abf238SBorislav Petkov X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x5, 0xf), 0), 568bd9240a1SPeter Zijlstra 569adefe55eSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL( HASWELL, 0x22), 570adefe55eSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL( HASWELL_L, 0x20), 571adefe55eSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL( HASWELL_G, 0x17), 572bd9240a1SPeter Zijlstra 573adefe55eSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL( BROADWELL, 0x25), 574adefe55eSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL( BROADWELL_G, 0x17), 575bd9240a1SPeter Zijlstra 576adefe55eSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL( SKYLAKE_L, 0xb2), 577adefe55eSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL( SKYLAKE, 0xb2), 578bd9240a1SPeter Zijlstra 579adefe55eSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL( KABYLAKE_L, 0x52), 580adefe55eSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL( KABYLAKE, 0x52), 581bd9240a1SPeter Zijlstra 582bd9240a1SPeter Zijlstra {}, 583bd9240a1SPeter Zijlstra }; 584bd9240a1SPeter Zijlstra 585c84cb373SThomas Gleixner static __init bool apic_validate_deadline_timer(void) 586bd9240a1SPeter Zijlstra { 587594a30fbSHans de Goede const struct x86_cpu_id *m; 588bd9240a1SPeter Zijlstra u32 rev; 589bd9240a1SPeter Zijlstra 590c84cb373SThomas Gleixner if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 591c84cb373SThomas Gleixner return false; 592c84cb373SThomas Gleixner if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) 593c84cb373SThomas Gleixner return true; 594594a30fbSHans de Goede 595594a30fbSHans de Goede m = x86_match_cpu(deadline_match); 596bd9240a1SPeter Zijlstra if (!m) 597c84cb373SThomas Gleixner return true; 598bd9240a1SPeter Zijlstra 599bd9240a1SPeter Zijlstra rev = (u32)m->driver_data; 600bd9240a1SPeter Zijlstra 601bd9240a1SPeter Zijlstra if (boot_cpu_data.microcode >= rev) 602c84cb373SThomas Gleixner return true; 603bd9240a1SPeter Zijlstra 604bd9240a1SPeter Zijlstra setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 605bd9240a1SPeter Zijlstra pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; " 606bd9240a1SPeter Zijlstra "please update microcode to version: 0x%x (or later)\n", rev); 607c84cb373SThomas Gleixner return false; 608bd9240a1SPeter Zijlstra } 609bd9240a1SPeter Zijlstra 610f62bae50SIngo Molnar /* 611421f91d2SUwe Kleine-König * Setup the local APIC timer for this CPU. Copy the initialized values 612f62bae50SIngo Molnar * of the boot CPU and register the clock event in the framework. 613f62bae50SIngo Molnar */ 614148f9bb8SPaul Gortmaker static void setup_APIC_timer(void) 615f62bae50SIngo Molnar { 61689cbc767SChristoph Lameter struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 617f62bae50SIngo Molnar 618349c004eSChristoph Lameter if (this_cpu_has(X86_FEATURE_ARAT)) { 619db954b58SVenkatesh Pallipadi lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 620d9f6e12fSIngo Molnar /* Make LAPIC timer preferable over percpu HPET */ 621db954b58SVenkatesh Pallipadi lapic_clockevent.rating = 150; 622db954b58SVenkatesh Pallipadi } 623db954b58SVenkatesh Pallipadi 624f62bae50SIngo Molnar memcpy(levt, &lapic_clockevent, sizeof(*levt)); 625f62bae50SIngo Molnar levt->cpumask = cpumask_of(smp_processor_id()); 626f62bae50SIngo Molnar 627279f1461SSuresh Siddha if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 628c6e9f42bSPeter Zijlstra levt->name = "lapic-deadline"; 629279f1461SSuresh Siddha levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | 630279f1461SSuresh Siddha CLOCK_EVT_FEAT_DUMMY); 631279f1461SSuresh Siddha levt->set_next_event = lapic_next_deadline; 632279f1461SSuresh Siddha clockevents_config_and_register(levt, 6331a9e4c56SNicolai Stange tsc_khz * (1000 / TSC_DIVISOR), 634279f1461SSuresh Siddha 0xF, ~0UL); 635279f1461SSuresh Siddha } else 636f62bae50SIngo Molnar clockevents_register_device(levt); 637f62bae50SIngo Molnar } 638f62bae50SIngo Molnar 639f62bae50SIngo Molnar /* 6406731b0d6SNicolai Stange * Install the updated TSC frequency from recalibration at the TSC 6416731b0d6SNicolai Stange * deadline clockevent devices. 6426731b0d6SNicolai Stange */ 6436731b0d6SNicolai Stange static void __lapic_update_tsc_freq(void *info) 6446731b0d6SNicolai Stange { 6456731b0d6SNicolai Stange struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 6466731b0d6SNicolai Stange 6476731b0d6SNicolai Stange if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 6486731b0d6SNicolai Stange return; 6496731b0d6SNicolai Stange 6506731b0d6SNicolai Stange clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR)); 6516731b0d6SNicolai Stange } 6526731b0d6SNicolai Stange 6536731b0d6SNicolai Stange void lapic_update_tsc_freq(void) 6546731b0d6SNicolai Stange { 6556731b0d6SNicolai Stange /* 6566731b0d6SNicolai Stange * The clockevent device's ->mult and ->shift can both be 6576731b0d6SNicolai Stange * changed. In order to avoid races, schedule the frequency 6586731b0d6SNicolai Stange * update code on each CPU. 6596731b0d6SNicolai Stange */ 6606731b0d6SNicolai Stange on_each_cpu(__lapic_update_tsc_freq, NULL, 0); 6616731b0d6SNicolai Stange } 6626731b0d6SNicolai Stange 6636731b0d6SNicolai Stange /* 664f62bae50SIngo Molnar * In this functions we calibrate APIC bus clocks to the external timer. 665f62bae50SIngo Molnar * 666f62bae50SIngo Molnar * We want to do the calibration only once since we want to have local timer 667d9f6e12fSIngo Molnar * irqs synchronous. CPUs connected by the same APIC bus have the very same bus 668f62bae50SIngo Molnar * frequency. 669f62bae50SIngo Molnar * 670f62bae50SIngo Molnar * This was previously done by reading the PIT/HPET and waiting for a wrap 671f62bae50SIngo Molnar * around to find out, that a tick has elapsed. I have a box, where the PIT 672f62bae50SIngo Molnar * readout is broken, so it never gets out of the wait loop again. This was 673f62bae50SIngo Molnar * also reported by others. 674f62bae50SIngo Molnar * 675f62bae50SIngo Molnar * Monitoring the jiffies value is inaccurate and the clockevents 676f62bae50SIngo Molnar * infrastructure allows us to do a simple substitution of the interrupt 677f62bae50SIngo Molnar * handler. 678f62bae50SIngo Molnar * 679f62bae50SIngo Molnar * The calibration routine also uses the pm_timer when possible, as the PIT 680f62bae50SIngo Molnar * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 681f62bae50SIngo Molnar * back to normal later in the boot process). 682f62bae50SIngo Molnar */ 683f62bae50SIngo Molnar 684f62bae50SIngo Molnar #define LAPIC_CAL_LOOPS (HZ/10) 685f62bae50SIngo Molnar 686f62bae50SIngo Molnar static __initdata int lapic_cal_loops = -1; 687f62bae50SIngo Molnar static __initdata long lapic_cal_t1, lapic_cal_t2; 688f62bae50SIngo Molnar static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 689f62bae50SIngo Molnar static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 690f62bae50SIngo Molnar static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 691f62bae50SIngo Molnar 692f62bae50SIngo Molnar /* 693f897e60aSThomas Gleixner * Temporary interrupt handler and polled calibration function. 694f62bae50SIngo Molnar */ 695f62bae50SIngo Molnar static void __init lapic_cal_handler(struct clock_event_device *dev) 696f62bae50SIngo Molnar { 697f62bae50SIngo Molnar unsigned long long tsc = 0; 698f62bae50SIngo Molnar long tapic = apic_read(APIC_TMCCT); 699f62bae50SIngo Molnar unsigned long pm = acpi_pm_read_early(); 700f62bae50SIngo Molnar 70159e21e3dSBorislav Petkov if (boot_cpu_has(X86_FEATURE_TSC)) 7024ea1636bSAndy Lutomirski tsc = rdtsc(); 703f62bae50SIngo Molnar 704f62bae50SIngo Molnar switch (lapic_cal_loops++) { 705f62bae50SIngo Molnar case 0: 706f62bae50SIngo Molnar lapic_cal_t1 = tapic; 707f62bae50SIngo Molnar lapic_cal_tsc1 = tsc; 708f62bae50SIngo Molnar lapic_cal_pm1 = pm; 709f62bae50SIngo Molnar lapic_cal_j1 = jiffies; 710f62bae50SIngo Molnar break; 711f62bae50SIngo Molnar 712f62bae50SIngo Molnar case LAPIC_CAL_LOOPS: 713f62bae50SIngo Molnar lapic_cal_t2 = tapic; 714f62bae50SIngo Molnar lapic_cal_tsc2 = tsc; 715f62bae50SIngo Molnar if (pm < lapic_cal_pm1) 716f62bae50SIngo Molnar pm += ACPI_PM_OVRRUN; 717f62bae50SIngo Molnar lapic_cal_pm2 = pm; 718f62bae50SIngo Molnar lapic_cal_j2 = jiffies; 719f62bae50SIngo Molnar break; 720f62bae50SIngo Molnar } 721f62bae50SIngo Molnar } 722f62bae50SIngo Molnar 723f62bae50SIngo Molnar static int __init 724f62bae50SIngo Molnar calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 725f62bae50SIngo Molnar { 726f62bae50SIngo Molnar const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 727f62bae50SIngo Molnar const long pm_thresh = pm_100ms / 100; 728f62bae50SIngo Molnar unsigned long mult; 729f62bae50SIngo Molnar u64 res; 730f62bae50SIngo Molnar 731f62bae50SIngo Molnar #ifndef CONFIG_X86_PM_TIMER 732f62bae50SIngo Molnar return -1; 733f62bae50SIngo Molnar #endif 734f62bae50SIngo Molnar 735f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 736f62bae50SIngo Molnar 737f62bae50SIngo Molnar /* Check, if the PM timer is available */ 738f62bae50SIngo Molnar if (!deltapm) 739f62bae50SIngo Molnar return -1; 740f62bae50SIngo Molnar 741f62bae50SIngo Molnar mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 742f62bae50SIngo Molnar 743f62bae50SIngo Molnar if (deltapm > (pm_100ms - pm_thresh) && 744f62bae50SIngo Molnar deltapm < (pm_100ms + pm_thresh)) { 745f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 746f62bae50SIngo Molnar return 0; 747f62bae50SIngo Molnar } 748f62bae50SIngo Molnar 749f62bae50SIngo Molnar res = (((u64)deltapm) * mult) >> 22; 750f62bae50SIngo Molnar do_div(res, 1000000); 7518d3bcc44SKefeng Wang pr_warn("APIC calibration not consistent " 752f62bae50SIngo Molnar "with PM-Timer: %ldms instead of 100ms\n", (long)res); 753f62bae50SIngo Molnar 754f62bae50SIngo Molnar /* Correct the lapic counter value */ 755f62bae50SIngo Molnar res = (((u64)(*delta)) * pm_100ms); 756f62bae50SIngo Molnar do_div(res, deltapm); 757f62bae50SIngo Molnar pr_info("APIC delta adjusted to PM-Timer: " 758f62bae50SIngo Molnar "%lu (%ld)\n", (unsigned long)res, *delta); 759f62bae50SIngo Molnar *delta = (long)res; 760f62bae50SIngo Molnar 761f62bae50SIngo Molnar /* Correct the tsc counter value */ 76259e21e3dSBorislav Petkov if (boot_cpu_has(X86_FEATURE_TSC)) { 763f62bae50SIngo Molnar res = (((u64)(*deltatsc)) * pm_100ms); 764f62bae50SIngo Molnar do_div(res, deltapm); 765f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 766f62bae50SIngo Molnar "PM-Timer: %lu (%ld)\n", 767f62bae50SIngo Molnar (unsigned long)res, *deltatsc); 768f62bae50SIngo Molnar *deltatsc = (long)res; 769f62bae50SIngo Molnar } 770f62bae50SIngo Molnar 771f62bae50SIngo Molnar return 0; 772f62bae50SIngo Molnar } 773f62bae50SIngo Molnar 7746eb4f082SJacob Pan static int __init lapic_init_clockevent(void) 7756eb4f082SJacob Pan { 77652ae346bSDaniel Drake if (!lapic_timer_period) 7776eb4f082SJacob Pan return -1; 7786eb4f082SJacob Pan 7796eb4f082SJacob Pan /* Calculate the scaled math multiplication factor */ 78052ae346bSDaniel Drake lapic_clockevent.mult = div_sc(lapic_timer_period/APIC_DIVISOR, 7816eb4f082SJacob Pan TICK_NSEC, lapic_clockevent.shift); 7826eb4f082SJacob Pan lapic_clockevent.max_delta_ns = 7836eb4f082SJacob Pan clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 7846eb4f082SJacob Pan lapic_clockevent.max_delta_ticks = 0x7FFFFFFF; 7856eb4f082SJacob Pan lapic_clockevent.min_delta_ns = 7866eb4f082SJacob Pan clockevent_delta2ns(0xF, &lapic_clockevent); 7876eb4f082SJacob Pan lapic_clockevent.min_delta_ticks = 0xF; 7886eb4f082SJacob Pan 7896eb4f082SJacob Pan return 0; 7906eb4f082SJacob Pan } 7916eb4f082SJacob Pan 792c8c40767SThomas Gleixner bool __init apic_needs_pit(void) 793c8c40767SThomas Gleixner { 794c8c40767SThomas Gleixner /* 795c8c40767SThomas Gleixner * If the frequencies are not known, PIT is required for both TSC 796c8c40767SThomas Gleixner * and apic timer calibration. 797c8c40767SThomas Gleixner */ 798c8c40767SThomas Gleixner if (!tsc_khz || !cpu_khz) 799c8c40767SThomas Gleixner return true; 800c8c40767SThomas Gleixner 80197992387SThomas Gleixner /* Is there an APIC at all or is it disabled? */ 80249062454SThomas Gleixner if (!boot_cpu_has(X86_FEATURE_APIC) || apic_is_disabled) 80397992387SThomas Gleixner return true; 80497992387SThomas Gleixner 80597992387SThomas Gleixner /* 80697992387SThomas Gleixner * If interrupt delivery mode is legacy PIC or virtual wire without 80797992387SThomas Gleixner * configuration, the local APIC timer wont be set up. Make sure 80897992387SThomas Gleixner * that the PIT is initialized. 80997992387SThomas Gleixner */ 81097992387SThomas Gleixner if (apic_intr_mode == APIC_PIC || 81197992387SThomas Gleixner apic_intr_mode == APIC_VIRTUAL_WIRE_NO_CONFIG) 812c8c40767SThomas Gleixner return true; 813c8c40767SThomas Gleixner 814afa8b475SJan Stancek /* Virt guests may lack ARAT, but still have DEADLINE */ 815afa8b475SJan Stancek if (!boot_cpu_has(X86_FEATURE_ARAT)) 816afa8b475SJan Stancek return true; 817afa8b475SJan Stancek 818c8c40767SThomas Gleixner /* Deadline timer is based on TSC so no further PIT action required */ 819c8c40767SThomas Gleixner if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 820c8c40767SThomas Gleixner return false; 821c8c40767SThomas Gleixner 822c8c40767SThomas Gleixner /* APIC timer disabled? */ 823c8c40767SThomas Gleixner if (disable_apic_timer) 824c8c40767SThomas Gleixner return true; 825c8c40767SThomas Gleixner /* 826c8c40767SThomas Gleixner * The APIC timer frequency is known already, no PIT calibration 827c8c40767SThomas Gleixner * required. If unknown, let the PIT be initialized. 828c8c40767SThomas Gleixner */ 829c8c40767SThomas Gleixner return lapic_timer_period == 0; 830c8c40767SThomas Gleixner } 831c8c40767SThomas Gleixner 832f62bae50SIngo Molnar static int __init calibrate_APIC_clock(void) 833f62bae50SIngo Molnar { 83489cbc767SChristoph Lameter struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 835f897e60aSThomas Gleixner u64 tsc_perj = 0, tsc_start = 0; 836f897e60aSThomas Gleixner unsigned long jif_start; 837f62bae50SIngo Molnar unsigned long deltaj; 838f62bae50SIngo Molnar long delta, deltatsc; 839f62bae50SIngo Molnar int pm_referenced = 0; 840f62bae50SIngo Molnar 8416eb4f082SJacob Pan if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 8426eb4f082SJacob Pan return 0; 8436eb4f082SJacob Pan 8446eb4f082SJacob Pan /* 8456eb4f082SJacob Pan * Check if lapic timer has already been calibrated by platform 8466eb4f082SJacob Pan * specific routine, such as tsc calibration code. If so just fill 8471ade93efSJacob Pan * in the clockevent structure and return. 8481ade93efSJacob Pan */ 8496eb4f082SJacob Pan if (!lapic_init_clockevent()) { 8501ade93efSJacob Pan apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", 85152ae346bSDaniel Drake lapic_timer_period); 8526eb4f082SJacob Pan /* 8536eb4f082SJacob Pan * Direct calibration methods must have an always running 8546eb4f082SJacob Pan * local APIC timer, no need for broadcast timer. 8556eb4f082SJacob Pan */ 8561ade93efSJacob Pan lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 8571ade93efSJacob Pan return 0; 8581ade93efSJacob Pan } 8591ade93efSJacob Pan 860279f1461SSuresh Siddha apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 861279f1461SSuresh Siddha "calibrating APIC timer ...\n"); 862279f1461SSuresh Siddha 863f897e60aSThomas Gleixner /* 864f897e60aSThomas Gleixner * There are platforms w/o global clockevent devices. Instead of 865f897e60aSThomas Gleixner * making the calibration conditional on that, use a polling based 866f897e60aSThomas Gleixner * approach everywhere. 867f897e60aSThomas Gleixner */ 868f62bae50SIngo Molnar local_irq_disable(); 869f62bae50SIngo Molnar 870f62bae50SIngo Molnar /* 871f62bae50SIngo Molnar * Setup the APIC counter to maximum. There is no way the lapic 872f62bae50SIngo Molnar * can underflow in the 100ms detection time frame 873f62bae50SIngo Molnar */ 874f62bae50SIngo Molnar __setup_APIC_LVTT(0xffffffff, 0, 0); 875f62bae50SIngo Molnar 876f897e60aSThomas Gleixner /* 877f897e60aSThomas Gleixner * Methods to terminate the calibration loop: 878f897e60aSThomas Gleixner * 1) Global clockevent if available (jiffies) 879f897e60aSThomas Gleixner * 2) TSC if available and frequency is known 880f897e60aSThomas Gleixner */ 881f897e60aSThomas Gleixner jif_start = READ_ONCE(jiffies); 882f897e60aSThomas Gleixner 883f897e60aSThomas Gleixner if (tsc_khz) { 884f897e60aSThomas Gleixner tsc_start = rdtsc(); 885f897e60aSThomas Gleixner tsc_perj = div_u64((u64)tsc_khz * 1000, HZ); 886f897e60aSThomas Gleixner } 887f897e60aSThomas Gleixner 888f897e60aSThomas Gleixner /* 889f897e60aSThomas Gleixner * Enable interrupts so the tick can fire, if a global 890f897e60aSThomas Gleixner * clockevent device is available 891f897e60aSThomas Gleixner */ 892f62bae50SIngo Molnar local_irq_enable(); 893f62bae50SIngo Molnar 894f897e60aSThomas Gleixner while (lapic_cal_loops <= LAPIC_CAL_LOOPS) { 895f897e60aSThomas Gleixner /* Wait for a tick to elapse */ 896f897e60aSThomas Gleixner while (1) { 897f897e60aSThomas Gleixner if (tsc_khz) { 898f897e60aSThomas Gleixner u64 tsc_now = rdtsc(); 899f897e60aSThomas Gleixner if ((tsc_now - tsc_start) >= tsc_perj) { 900f897e60aSThomas Gleixner tsc_start += tsc_perj; 901f897e60aSThomas Gleixner break; 902f897e60aSThomas Gleixner } 903f897e60aSThomas Gleixner } else { 904f897e60aSThomas Gleixner unsigned long jif_now = READ_ONCE(jiffies); 905f897e60aSThomas Gleixner 906f897e60aSThomas Gleixner if (time_after(jif_now, jif_start)) { 907f897e60aSThomas Gleixner jif_start = jif_now; 908f897e60aSThomas Gleixner break; 909f897e60aSThomas Gleixner } 910f897e60aSThomas Gleixner } 911f62bae50SIngo Molnar cpu_relax(); 912f897e60aSThomas Gleixner } 913f897e60aSThomas Gleixner 914f897e60aSThomas Gleixner /* Invoke the calibration routine */ 915f897e60aSThomas Gleixner local_irq_disable(); 916f897e60aSThomas Gleixner lapic_cal_handler(NULL); 917f897e60aSThomas Gleixner local_irq_enable(); 918f897e60aSThomas Gleixner } 919f62bae50SIngo Molnar 920f62bae50SIngo Molnar local_irq_disable(); 921f62bae50SIngo Molnar 922f62bae50SIngo Molnar /* Build delta t1-t2 as apic timer counts down */ 923f62bae50SIngo Molnar delta = lapic_cal_t1 - lapic_cal_t2; 924f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 925f62bae50SIngo Molnar 926f62bae50SIngo Molnar deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 927f62bae50SIngo Molnar 928f62bae50SIngo Molnar /* we trust the PM based calibration if possible */ 929f62bae50SIngo Molnar pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 930f62bae50SIngo Molnar &delta, &deltatsc); 931f62bae50SIngo Molnar 93252ae346bSDaniel Drake lapic_timer_period = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 9336eb4f082SJacob Pan lapic_init_clockevent(); 934f62bae50SIngo Molnar 935f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 936411462f6SThomas Gleixner apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 937f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 93852ae346bSDaniel Drake lapic_timer_period); 939f62bae50SIngo Molnar 94059e21e3dSBorislav Petkov if (boot_cpu_has(X86_FEATURE_TSC)) { 941f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 942f62bae50SIngo Molnar "%ld.%04ld MHz.\n", 943f62bae50SIngo Molnar (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 944f62bae50SIngo Molnar (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 945f62bae50SIngo Molnar } 946f62bae50SIngo Molnar 947f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 948f62bae50SIngo Molnar "%u.%04u MHz.\n", 94952ae346bSDaniel Drake lapic_timer_period / (1000000 / HZ), 95052ae346bSDaniel Drake lapic_timer_period % (1000000 / HZ)); 951f62bae50SIngo Molnar 952f62bae50SIngo Molnar /* 953f62bae50SIngo Molnar * Do a sanity check on the APIC calibration result 954f62bae50SIngo Molnar */ 95552ae346bSDaniel Drake if (lapic_timer_period < (1000000 / HZ)) { 956f62bae50SIngo Molnar local_irq_enable(); 9578d3bcc44SKefeng Wang pr_warn("APIC frequency too slow, disabling apic timer\n"); 958f62bae50SIngo Molnar return -1; 959f62bae50SIngo Molnar } 960f62bae50SIngo Molnar 961f62bae50SIngo Molnar levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 962f62bae50SIngo Molnar 963f62bae50SIngo Molnar /* 964f897e60aSThomas Gleixner * PM timer calibration failed or not turned on so lets try APIC 965f897e60aSThomas Gleixner * timer based calibration, if a global clockevent device is 966f897e60aSThomas Gleixner * available. 967f62bae50SIngo Molnar */ 968f897e60aSThomas Gleixner if (!pm_referenced && global_clock_event) { 969f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 970f62bae50SIngo Molnar 971f62bae50SIngo Molnar /* 972f62bae50SIngo Molnar * Setup the apic timer manually 973f62bae50SIngo Molnar */ 974f62bae50SIngo Molnar levt->event_handler = lapic_cal_handler; 975b23d8e52SViresh Kumar lapic_timer_set_periodic(levt); 976f62bae50SIngo Molnar lapic_cal_loops = -1; 977f62bae50SIngo Molnar 978f62bae50SIngo Molnar /* Let the interrupts run */ 979f62bae50SIngo Molnar local_irq_enable(); 980f62bae50SIngo Molnar 981f62bae50SIngo Molnar while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 982f62bae50SIngo Molnar cpu_relax(); 983f62bae50SIngo Molnar 984f62bae50SIngo Molnar /* Stop the lapic timer */ 985c948c260SThomas Gleixner local_irq_disable(); 986b23d8e52SViresh Kumar lapic_timer_shutdown(levt); 987f62bae50SIngo Molnar 988f62bae50SIngo Molnar /* Jiffies delta */ 989f62bae50SIngo Molnar deltaj = lapic_cal_j2 - lapic_cal_j1; 990f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 991f62bae50SIngo Molnar 992f62bae50SIngo Molnar /* Check, if the jiffies result is consistent */ 993f62bae50SIngo Molnar if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 994f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 995f62bae50SIngo Molnar else 996f62bae50SIngo Molnar levt->features |= CLOCK_EVT_FEAT_DUMMY; 997c948c260SThomas Gleixner } 998f62bae50SIngo Molnar local_irq_enable(); 999f62bae50SIngo Molnar 1000f62bae50SIngo Molnar if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 10018d3bcc44SKefeng Wang pr_warn("APIC timer disabled due to verification failure\n"); 1002f62bae50SIngo Molnar return -1; 1003f62bae50SIngo Molnar } 1004f62bae50SIngo Molnar 1005f62bae50SIngo Molnar return 0; 1006f62bae50SIngo Molnar } 1007f62bae50SIngo Molnar 1008f62bae50SIngo Molnar /* 1009f62bae50SIngo Molnar * Setup the boot APIC 1010f62bae50SIngo Molnar * 1011f62bae50SIngo Molnar * Calibrate and verify the result. 1012f62bae50SIngo Molnar */ 1013f62bae50SIngo Molnar void __init setup_boot_APIC_clock(void) 1014f62bae50SIngo Molnar { 1015f62bae50SIngo Molnar /* 1016f62bae50SIngo Molnar * The local apic timer can be disabled via the kernel 1017f62bae50SIngo Molnar * commandline or from the CPU detection code. Register the lapic 1018f62bae50SIngo Molnar * timer as a dummy clock event source on SMP systems, so the 1019f62bae50SIngo Molnar * broadcast mechanism is used. On UP systems simply ignore it. 1020f62bae50SIngo Molnar */ 1021f62bae50SIngo Molnar if (disable_apic_timer) { 1022f62bae50SIngo Molnar pr_info("Disabling APIC timer\n"); 1023f62bae50SIngo Molnar /* No broadcast on UP ! */ 1024f62bae50SIngo Molnar if (num_possible_cpus() > 1) { 1025f62bae50SIngo Molnar lapic_clockevent.mult = 1; 1026f62bae50SIngo Molnar setup_APIC_timer(); 1027f62bae50SIngo Molnar } 1028f62bae50SIngo Molnar return; 1029f62bae50SIngo Molnar } 1030f62bae50SIngo Molnar 1031f62bae50SIngo Molnar if (calibrate_APIC_clock()) { 1032f62bae50SIngo Molnar /* No broadcast on UP ! */ 1033f62bae50SIngo Molnar if (num_possible_cpus() > 1) 1034f62bae50SIngo Molnar setup_APIC_timer(); 1035f62bae50SIngo Molnar return; 1036f62bae50SIngo Molnar } 1037f62bae50SIngo Molnar 1038f62bae50SIngo Molnar /* 1039f62bae50SIngo Molnar * If nmi_watchdog is set to IO_APIC, we need the 1040f62bae50SIngo Molnar * PIT/HPET going. Otherwise register lapic as a dummy 1041f62bae50SIngo Molnar * device. 1042f62bae50SIngo Molnar */ 1043f62bae50SIngo Molnar lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 1044f62bae50SIngo Molnar 1045f62bae50SIngo Molnar /* Setup the lapic or request the broadcast */ 1046f62bae50SIngo Molnar setup_APIC_timer(); 104707c94a38SBorislav Petkov amd_e400_c1e_apic_setup(); 1048f62bae50SIngo Molnar } 1049f62bae50SIngo Molnar 1050148f9bb8SPaul Gortmaker void setup_secondary_APIC_clock(void) 1051f62bae50SIngo Molnar { 1052f62bae50SIngo Molnar setup_APIC_timer(); 105307c94a38SBorislav Petkov amd_e400_c1e_apic_setup(); 1054f62bae50SIngo Molnar } 1055f62bae50SIngo Molnar 1056f62bae50SIngo Molnar /* 1057f62bae50SIngo Molnar * The guts of the apic timer interrupt 1058f62bae50SIngo Molnar */ 1059f62bae50SIngo Molnar static void local_apic_timer_interrupt(void) 1060f62bae50SIngo Molnar { 10613bec6defSThomas Gleixner struct clock_event_device *evt = this_cpu_ptr(&lapic_events); 1062f62bae50SIngo Molnar 1063f62bae50SIngo Molnar /* 1064f62bae50SIngo Molnar * Normally we should not be here till LAPIC has been initialized but 1065f62bae50SIngo Molnar * in some cases like kdump, its possible that there is a pending LAPIC 1066f62bae50SIngo Molnar * timer interrupt from previous kernel's context and is delivered in 1067f62bae50SIngo Molnar * new kernel the moment interrupts are enabled. 1068f62bae50SIngo Molnar * 1069f62bae50SIngo Molnar * Interrupts are enabled early and LAPIC is setup much later, hence 1070f62bae50SIngo Molnar * its possible that when we get here evt->event_handler is NULL. 1071f62bae50SIngo Molnar * Check for event_handler being NULL and discard the interrupt as 1072f62bae50SIngo Molnar * spurious. 1073f62bae50SIngo Molnar */ 1074f62bae50SIngo Molnar if (!evt->event_handler) { 10758d3bcc44SKefeng Wang pr_warn("Spurious LAPIC timer interrupt on cpu %d\n", 10763bec6defSThomas Gleixner smp_processor_id()); 1077f62bae50SIngo Molnar /* Switch it off */ 1078b23d8e52SViresh Kumar lapic_timer_shutdown(evt); 1079f62bae50SIngo Molnar return; 1080f62bae50SIngo Molnar } 1081f62bae50SIngo Molnar 1082f62bae50SIngo Molnar /* 1083f62bae50SIngo Molnar * the NMI deadlock-detector uses this. 1084f62bae50SIngo Molnar */ 1085f62bae50SIngo Molnar inc_irq_stat(apic_timer_irqs); 1086f62bae50SIngo Molnar 1087f62bae50SIngo Molnar evt->event_handler(evt); 1088f62bae50SIngo Molnar } 1089f62bae50SIngo Molnar 1090f62bae50SIngo Molnar /* 1091f62bae50SIngo Molnar * Local APIC timer interrupt. This is the most natural way for doing 1092f62bae50SIngo Molnar * local interrupts, but local timer interrupts can be emulated by 1093f62bae50SIngo Molnar * broadcast interrupts too. [in case the hw doesn't support APIC timers] 1094f62bae50SIngo Molnar * 1095f62bae50SIngo Molnar * [ if a single-CPU system runs an SMP kernel then we call the local 1096f62bae50SIngo Molnar * interrupt as well. Thus we cannot inline the local irq ... ] 1097f62bae50SIngo Molnar */ 1098db0338eeSThomas Gleixner DEFINE_IDTENTRY_SYSVEC(sysvec_apic_timer_interrupt) 1099f62bae50SIngo Molnar { 1100f62bae50SIngo Molnar struct pt_regs *old_regs = set_irq_regs(regs); 1101f62bae50SIngo Molnar 1102db0338eeSThomas Gleixner ack_APIC_irq(); 1103cf910e83SSeiji Aguchi trace_local_timer_entry(LOCAL_TIMER_VECTOR); 1104cf910e83SSeiji Aguchi local_apic_timer_interrupt(); 1105cf910e83SSeiji Aguchi trace_local_timer_exit(LOCAL_TIMER_VECTOR); 1106f62bae50SIngo Molnar 1107f62bae50SIngo Molnar set_irq_regs(old_regs); 1108f62bae50SIngo Molnar } 1109f62bae50SIngo Molnar 1110f62bae50SIngo Molnar /* 1111f62bae50SIngo Molnar * Local APIC start and shutdown 1112f62bae50SIngo Molnar */ 1113f62bae50SIngo Molnar 1114f62bae50SIngo Molnar /** 1115f62bae50SIngo Molnar * clear_local_APIC - shutdown the local APIC 1116f62bae50SIngo Molnar * 1117f62bae50SIngo Molnar * This is called, when a CPU is disabled and before rebooting, so the state of 1118f62bae50SIngo Molnar * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 1119f62bae50SIngo Molnar * leftovers during boot. 1120f62bae50SIngo Molnar */ 1121f62bae50SIngo Molnar void clear_local_APIC(void) 1122f62bae50SIngo Molnar { 1123f62bae50SIngo Molnar int maxlvt; 1124f62bae50SIngo Molnar u32 v; 1125f62bae50SIngo Molnar 112678c32000SThomas Gleixner if (!apic_accessible()) 1127f62bae50SIngo Molnar return; 1128f62bae50SIngo Molnar 1129f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 1130f62bae50SIngo Molnar /* 1131f62bae50SIngo Molnar * Masking an LVT entry can trigger a local APIC error 1132f62bae50SIngo Molnar * if the vector is zero. Mask LVTERR first to prevent this. 1133f62bae50SIngo Molnar */ 1134f62bae50SIngo Molnar if (maxlvt >= 3) { 1135f62bae50SIngo Molnar v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 1136f62bae50SIngo Molnar apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 1137f62bae50SIngo Molnar } 1138f62bae50SIngo Molnar /* 1139f62bae50SIngo Molnar * Careful: we have to set masks only first to deassert 1140f62bae50SIngo Molnar * any level-triggered sources. 1141f62bae50SIngo Molnar */ 1142f62bae50SIngo Molnar v = apic_read(APIC_LVTT); 1143f62bae50SIngo Molnar apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 1144f62bae50SIngo Molnar v = apic_read(APIC_LVT0); 1145f62bae50SIngo Molnar apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 1146f62bae50SIngo Molnar v = apic_read(APIC_LVT1); 1147f62bae50SIngo Molnar apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 1148f62bae50SIngo Molnar if (maxlvt >= 4) { 1149f62bae50SIngo Molnar v = apic_read(APIC_LVTPC); 1150f62bae50SIngo Molnar apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 1151f62bae50SIngo Molnar } 1152f62bae50SIngo Molnar 1153f62bae50SIngo Molnar /* lets not touch this if we didn't frob it */ 11544efc0670SAndi Kleen #ifdef CONFIG_X86_THERMAL_VECTOR 1155f62bae50SIngo Molnar if (maxlvt >= 5) { 1156f62bae50SIngo Molnar v = apic_read(APIC_LVTTHMR); 1157f62bae50SIngo Molnar apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 1158f62bae50SIngo Molnar } 1159f62bae50SIngo Molnar #endif 1160638bee71SH. Peter Anvin #ifdef CONFIG_X86_MCE_INTEL 1161638bee71SH. Peter Anvin if (maxlvt >= 6) { 1162638bee71SH. Peter Anvin v = apic_read(APIC_LVTCMCI); 1163638bee71SH. Peter Anvin if (!(v & APIC_LVT_MASKED)) 1164638bee71SH. Peter Anvin apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 1165638bee71SH. Peter Anvin } 1166638bee71SH. Peter Anvin #endif 1167638bee71SH. Peter Anvin 1168f62bae50SIngo Molnar /* 1169f62bae50SIngo Molnar * Clean APIC state for other OSs: 1170f62bae50SIngo Molnar */ 1171f62bae50SIngo Molnar apic_write(APIC_LVTT, APIC_LVT_MASKED); 1172f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_LVT_MASKED); 1173f62bae50SIngo Molnar apic_write(APIC_LVT1, APIC_LVT_MASKED); 1174f62bae50SIngo Molnar if (maxlvt >= 3) 1175f62bae50SIngo Molnar apic_write(APIC_LVTERR, APIC_LVT_MASKED); 1176f62bae50SIngo Molnar if (maxlvt >= 4) 1177f62bae50SIngo Molnar apic_write(APIC_LVTPC, APIC_LVT_MASKED); 1178f62bae50SIngo Molnar 1179f62bae50SIngo Molnar /* Integrated APIC (!82489DX) ? */ 1180f62bae50SIngo Molnar if (lapic_is_integrated()) { 1181f62bae50SIngo Molnar if (maxlvt > 3) 1182f62bae50SIngo Molnar /* Clear ESR due to Pentium errata 3AP and 11AP */ 1183f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1184f62bae50SIngo Molnar apic_read(APIC_ESR); 1185f62bae50SIngo Molnar } 1186f62bae50SIngo Molnar } 1187f62bae50SIngo Molnar 1188f62bae50SIngo Molnar /** 118960dcaad5SThomas Gleixner * apic_soft_disable - Clears and software disables the local APIC on hotplug 119060dcaad5SThomas Gleixner * 119160dcaad5SThomas Gleixner * Contrary to disable_local_APIC() this does not touch the enable bit in 119260dcaad5SThomas Gleixner * MSR_IA32_APICBASE. Clearing that bit on systems based on the 3 wire APIC 119360dcaad5SThomas Gleixner * bus would require a hardware reset as the APIC would lose track of bus 119460dcaad5SThomas Gleixner * arbitration. On systems with FSB delivery APICBASE could be disabled, 119560dcaad5SThomas Gleixner * but it has to be guaranteed that no interrupt is sent to the APIC while 119660dcaad5SThomas Gleixner * in that state and it's not clear from the SDM whether it still responds 119760dcaad5SThomas Gleixner * to INIT/SIPI messages. Stay on the safe side and use software disable. 119860dcaad5SThomas Gleixner */ 119960dcaad5SThomas Gleixner void apic_soft_disable(void) 120060dcaad5SThomas Gleixner { 120160dcaad5SThomas Gleixner u32 value; 120260dcaad5SThomas Gleixner 120360dcaad5SThomas Gleixner clear_local_APIC(); 120460dcaad5SThomas Gleixner 120560dcaad5SThomas Gleixner /* Soft disable APIC (implies clearing of registers for 82489DX!). */ 120660dcaad5SThomas Gleixner value = apic_read(APIC_SPIV); 120760dcaad5SThomas Gleixner value &= ~APIC_SPIV_APIC_ENABLED; 120860dcaad5SThomas Gleixner apic_write(APIC_SPIV, value); 120960dcaad5SThomas Gleixner } 121060dcaad5SThomas Gleixner 121160dcaad5SThomas Gleixner /** 1212f62bae50SIngo Molnar * disable_local_APIC - clear and disable the local APIC 1213f62bae50SIngo Molnar */ 1214f62bae50SIngo Molnar void disable_local_APIC(void) 1215f62bae50SIngo Molnar { 121678c32000SThomas Gleixner if (!apic_accessible()) 1217f62bae50SIngo Molnar return; 1218f62bae50SIngo Molnar 121960dcaad5SThomas Gleixner apic_soft_disable(); 1220f62bae50SIngo Molnar 1221f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1222f62bae50SIngo Molnar /* 1223f62bae50SIngo Molnar * When LAPIC was disabled by the BIOS and enabled by the kernel, 1224f62bae50SIngo Molnar * restore the disabled state. 1225f62bae50SIngo Molnar */ 1226f62bae50SIngo Molnar if (enabled_via_apicbase) { 1227f62bae50SIngo Molnar unsigned int l, h; 1228f62bae50SIngo Molnar 1229f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, l, h); 1230f62bae50SIngo Molnar l &= ~MSR_IA32_APICBASE_ENABLE; 1231f62bae50SIngo Molnar wrmsr(MSR_IA32_APICBASE, l, h); 1232f62bae50SIngo Molnar } 1233f62bae50SIngo Molnar #endif 1234f62bae50SIngo Molnar } 1235f62bae50SIngo Molnar 1236f62bae50SIngo Molnar /* 1237f62bae50SIngo Molnar * If Linux enabled the LAPIC against the BIOS default disable it down before 1238f62bae50SIngo Molnar * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 1239f62bae50SIngo Molnar * not power-off. Additionally clear all LVT entries before disable_local_APIC 1240f62bae50SIngo Molnar * for the case where Linux didn't enable the LAPIC. 1241f62bae50SIngo Molnar */ 1242f62bae50SIngo Molnar void lapic_shutdown(void) 1243f62bae50SIngo Molnar { 1244f62bae50SIngo Molnar unsigned long flags; 1245f62bae50SIngo Molnar 124693984fbdSBorislav Petkov if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) 1247f62bae50SIngo Molnar return; 1248f62bae50SIngo Molnar 1249f62bae50SIngo Molnar local_irq_save(flags); 1250f62bae50SIngo Molnar 1251f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1252f62bae50SIngo Molnar if (!enabled_via_apicbase) 1253f62bae50SIngo Molnar clear_local_APIC(); 1254f62bae50SIngo Molnar else 1255f62bae50SIngo Molnar #endif 1256f62bae50SIngo Molnar disable_local_APIC(); 1257f62bae50SIngo Molnar 1258f62bae50SIngo Molnar 1259f62bae50SIngo Molnar local_irq_restore(flags); 1260f62bae50SIngo Molnar } 1261f62bae50SIngo Molnar 1262f62bae50SIngo Molnar /** 1263f62bae50SIngo Molnar * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1264f62bae50SIngo Molnar */ 1265f62bae50SIngo Molnar void __init sync_Arb_IDs(void) 1266f62bae50SIngo Molnar { 1267f62bae50SIngo Molnar /* 1268f62bae50SIngo Molnar * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1269f62bae50SIngo Molnar * needed on AMD. 1270f62bae50SIngo Molnar */ 1271f62bae50SIngo Molnar if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1272f62bae50SIngo Molnar return; 1273f62bae50SIngo Molnar 1274f62bae50SIngo Molnar /* 1275f62bae50SIngo Molnar * Wait for idle. 1276f62bae50SIngo Molnar */ 1277f62bae50SIngo Molnar apic_wait_icr_idle(); 1278f62bae50SIngo Molnar 1279f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1280f62bae50SIngo Molnar apic_write(APIC_ICR, APIC_DEST_ALLINC | 1281f62bae50SIngo Molnar APIC_INT_LEVELTRIG | APIC_DM_INIT); 1282f62bae50SIngo Molnar } 1283f62bae50SIngo Molnar 12846444b40eSSean Christopherson enum apic_intr_mode_id apic_intr_mode __ro_after_init; 12850114a8e8SDou Liyang 128697992387SThomas Gleixner static int __init __apic_intr_mode_select(void) 1287f62bae50SIngo Molnar { 12880114a8e8SDou Liyang /* Check kernel option */ 128949062454SThomas Gleixner if (apic_is_disabled) { 12900114a8e8SDou Liyang pr_info("APIC disabled via kernel command line\n"); 12910114a8e8SDou Liyang return APIC_PIC; 12920114a8e8SDou Liyang } 1293f62bae50SIngo Molnar 12940114a8e8SDou Liyang /* Check BIOS */ 12950114a8e8SDou Liyang #ifdef CONFIG_X86_64 12960114a8e8SDou Liyang /* On 64-bit, the APIC must be integrated, Check local APIC only */ 12970114a8e8SDou Liyang if (!boot_cpu_has(X86_FEATURE_APIC)) { 129849062454SThomas Gleixner apic_is_disabled = true; 12990114a8e8SDou Liyang pr_info("APIC disabled by BIOS\n"); 13000114a8e8SDou Liyang return APIC_PIC; 13010114a8e8SDou Liyang } 13020114a8e8SDou Liyang #else 13030114a8e8SDou Liyang /* On 32-bit, the APIC may be integrated APIC or 82489DX */ 1304f62bae50SIngo Molnar 13050114a8e8SDou Liyang /* Neither 82489DX nor integrated APIC ? */ 13060114a8e8SDou Liyang if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) { 130749062454SThomas Gleixner apic_is_disabled = true; 13080114a8e8SDou Liyang return APIC_PIC; 13090114a8e8SDou Liyang } 1310f62bae50SIngo Molnar 13110114a8e8SDou Liyang /* If the BIOS pretends there is an integrated APIC ? */ 13120114a8e8SDou Liyang if (!boot_cpu_has(X86_FEATURE_APIC) && 13130114a8e8SDou Liyang APIC_INTEGRATED(boot_cpu_apic_version)) { 131449062454SThomas Gleixner apic_is_disabled = true; 1315d10a9044SThomas Gleixner pr_err(FW_BUG "Local APIC not detected, force emulation\n"); 13160114a8e8SDou Liyang return APIC_PIC; 13170114a8e8SDou Liyang } 1318f62bae50SIngo Molnar #endif 1319f62bae50SIngo Molnar 13200114a8e8SDou Liyang /* Check MP table or ACPI MADT configuration */ 13210114a8e8SDou Liyang if (!smp_found_config) { 13220114a8e8SDou Liyang disable_ioapic_support(); 13233e730dadSDou Liyang if (!acpi_lapic) { 13240114a8e8SDou Liyang pr_info("APIC: ACPI MADT or MP tables are not detected\n"); 13253e730dadSDou Liyang return APIC_VIRTUAL_WIRE_NO_CONFIG; 13263e730dadSDou Liyang } 13270114a8e8SDou Liyang return APIC_VIRTUAL_WIRE; 13280114a8e8SDou Liyang } 13290114a8e8SDou Liyang 13303e730dadSDou Liyang #ifdef CONFIG_SMP 13313e730dadSDou Liyang /* If SMP should be disabled, then really disable it! */ 13323e730dadSDou Liyang if (!setup_max_cpus) { 13333e730dadSDou Liyang pr_info("APIC: SMP mode deactivated\n"); 13343e730dadSDou Liyang return APIC_SYMMETRIC_IO_NO_ROUTING; 13353e730dadSDou Liyang } 13363e730dadSDou Liyang #endif 13373e730dadSDou Liyang 13380114a8e8SDou Liyang return APIC_SYMMETRIC_IO; 13390114a8e8SDou Liyang } 13400114a8e8SDou Liyang 134197992387SThomas Gleixner /* Select the interrupt delivery mode for the BSP */ 134297992387SThomas Gleixner void __init apic_intr_mode_select(void) 134397992387SThomas Gleixner { 134497992387SThomas Gleixner apic_intr_mode = __apic_intr_mode_select(); 134597992387SThomas Gleixner } 134697992387SThomas Gleixner 1347fc90ccfdSVille Syrjälä /* 1348fc90ccfdSVille Syrjälä * An initial setup of the virtual wire mode. 1349fc90ccfdSVille Syrjälä */ 1350fc90ccfdSVille Syrjälä void __init init_bsp_APIC(void) 1351fc90ccfdSVille Syrjälä { 1352fc90ccfdSVille Syrjälä unsigned int value; 1353fc90ccfdSVille Syrjälä 1354fc90ccfdSVille Syrjälä /* 1355fc90ccfdSVille Syrjälä * Don't do the setup now if we have a SMP BIOS as the 1356fc90ccfdSVille Syrjälä * through-I/O-APIC virtual wire mode might be active. 1357fc90ccfdSVille Syrjälä */ 1358fc90ccfdSVille Syrjälä if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC)) 1359fc90ccfdSVille Syrjälä return; 1360fc90ccfdSVille Syrjälä 1361fc90ccfdSVille Syrjälä /* 1362fc90ccfdSVille Syrjälä * Do not trust the local APIC being empty at bootup. 1363fc90ccfdSVille Syrjälä */ 1364fc90ccfdSVille Syrjälä clear_local_APIC(); 1365fc90ccfdSVille Syrjälä 1366fc90ccfdSVille Syrjälä /* 1367fc90ccfdSVille Syrjälä * Enable APIC. 1368fc90ccfdSVille Syrjälä */ 1369fc90ccfdSVille Syrjälä value = apic_read(APIC_SPIV); 1370fc90ccfdSVille Syrjälä value &= ~APIC_VECTOR_MASK; 1371fc90ccfdSVille Syrjälä value |= APIC_SPIV_APIC_ENABLED; 1372fc90ccfdSVille Syrjälä 1373fc90ccfdSVille Syrjälä #ifdef CONFIG_X86_32 1374fc90ccfdSVille Syrjälä /* This bit is reserved on P4/Xeon and should be cleared */ 1375fc90ccfdSVille Syrjälä if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1376fc90ccfdSVille Syrjälä (boot_cpu_data.x86 == 15)) 1377fc90ccfdSVille Syrjälä value &= ~APIC_SPIV_FOCUS_DISABLED; 1378fc90ccfdSVille Syrjälä else 1379fc90ccfdSVille Syrjälä #endif 1380fc90ccfdSVille Syrjälä value |= APIC_SPIV_FOCUS_DISABLED; 1381fc90ccfdSVille Syrjälä value |= SPURIOUS_APIC_VECTOR; 1382fc90ccfdSVille Syrjälä apic_write(APIC_SPIV, value); 1383fc90ccfdSVille Syrjälä 1384fc90ccfdSVille Syrjälä /* 1385fc90ccfdSVille Syrjälä * Set up the virtual wire mode. 1386fc90ccfdSVille Syrjälä */ 1387fc90ccfdSVille Syrjälä apic_write(APIC_LVT0, APIC_DM_EXTINT); 1388fc90ccfdSVille Syrjälä value = APIC_DM_NMI; 1389fc90ccfdSVille Syrjälä if (!lapic_is_integrated()) /* 82489DX */ 1390fc90ccfdSVille Syrjälä value |= APIC_LVT_LEVEL_TRIGGER; 1391fc90ccfdSVille Syrjälä if (apic_extnmi == APIC_EXTNMI_NONE) 1392fc90ccfdSVille Syrjälä value |= APIC_LVT_MASKED; 1393fc90ccfdSVille Syrjälä apic_write(APIC_LVT1, value); 1394fc90ccfdSVille Syrjälä } 1395fc90ccfdSVille Syrjälä 1396748b170cSThomas Gleixner static void __init apic_bsp_setup(bool upmode); 1397748b170cSThomas Gleixner 13984b1669e8SDou Liyang /* Init the interrupt delivery mode for the BSP */ 13994b1669e8SDou Liyang void __init apic_intr_mode_init(void) 14004b1669e8SDou Liyang { 14010c759131SDou Liyang bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT); 14023e730dadSDou Liyang 14034f45ed9fSDou Liyang switch (apic_intr_mode) { 14044b1669e8SDou Liyang case APIC_PIC: 14054b1669e8SDou Liyang pr_info("APIC: Keep in PIC mode(8259)\n"); 14064b1669e8SDou Liyang return; 14074b1669e8SDou Liyang case APIC_VIRTUAL_WIRE: 14084b1669e8SDou Liyang pr_info("APIC: Switch to virtual wire mode setup\n"); 14093e730dadSDou Liyang break; 14103e730dadSDou Liyang case APIC_VIRTUAL_WIRE_NO_CONFIG: 14113e730dadSDou Liyang pr_info("APIC: Switch to virtual wire mode setup with no configuration\n"); 14123e730dadSDou Liyang upmode = true; 14133e730dadSDou Liyang break; 14144b1669e8SDou Liyang case APIC_SYMMETRIC_IO: 141579761ce8SColin Ian King pr_info("APIC: Switch to symmetric I/O mode setup\n"); 14163e730dadSDou Liyang break; 14173e730dadSDou Liyang case APIC_SYMMETRIC_IO_NO_ROUTING: 141879761ce8SColin Ian King pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n"); 14193e730dadSDou Liyang break; 14204b1669e8SDou Liyang } 14213e730dadSDou Liyang 14227a116a2dSKuppuswamy Sathyanarayanan default_setup_apic_routing(); 14237a116a2dSKuppuswamy Sathyanarayanan 1424bb733e43SThomas Gleixner if (x86_platform.apic_post_init) 1425bb733e43SThomas Gleixner x86_platform.apic_post_init(); 1426bb733e43SThomas Gleixner 14273e730dadSDou Liyang apic_bsp_setup(upmode); 1428f62bae50SIngo Molnar } 1429f62bae50SIngo Molnar 1430148f9bb8SPaul Gortmaker static void lapic_setup_esr(void) 1431f62bae50SIngo Molnar { 1432f62bae50SIngo Molnar unsigned int oldvalue, value, maxlvt; 1433f62bae50SIngo Molnar 1434f62bae50SIngo Molnar if (!lapic_is_integrated()) { 1435f62bae50SIngo Molnar pr_info("No ESR for 82489DX.\n"); 1436f62bae50SIngo Molnar return; 1437f62bae50SIngo Molnar } 1438f62bae50SIngo Molnar 1439f62bae50SIngo Molnar if (apic->disable_esr) { 1440f62bae50SIngo Molnar /* 1441f62bae50SIngo Molnar * Something untraceable is creating bad interrupts on 1442f62bae50SIngo Molnar * secondary quads ... for the moment, just leave the 1443f62bae50SIngo Molnar * ESR disabled - we can't do anything useful with the 1444f62bae50SIngo Molnar * errors anyway - mbligh 1445f62bae50SIngo Molnar */ 1446f62bae50SIngo Molnar pr_info("Leaving ESR disabled.\n"); 1447f62bae50SIngo Molnar return; 1448f62bae50SIngo Molnar } 1449f62bae50SIngo Molnar 1450f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 1451f62bae50SIngo Molnar if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1452f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1453f62bae50SIngo Molnar oldvalue = apic_read(APIC_ESR); 1454f62bae50SIngo Molnar 1455f62bae50SIngo Molnar /* enables sending errors */ 1456f62bae50SIngo Molnar value = ERROR_APIC_VECTOR; 1457f62bae50SIngo Molnar apic_write(APIC_LVTERR, value); 1458f62bae50SIngo Molnar 1459f62bae50SIngo Molnar /* 1460f62bae50SIngo Molnar * spec says clear errors after enabling vector. 1461f62bae50SIngo Molnar */ 1462f62bae50SIngo Molnar if (maxlvt > 3) 1463f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1464f62bae50SIngo Molnar value = apic_read(APIC_ESR); 1465f62bae50SIngo Molnar if (value != oldvalue) 1466f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "ESR value before enabling " 1467f62bae50SIngo Molnar "vector: 0x%08x after: 0x%08x\n", 1468f62bae50SIngo Molnar oldvalue, value); 1469f62bae50SIngo Molnar } 1470f62bae50SIngo Molnar 1471cc8bf191SThomas Gleixner #define APIC_IR_REGS APIC_ISR_NR 1472cc8bf191SThomas Gleixner #define APIC_IR_BITS (APIC_IR_REGS * 32) 1473cc8bf191SThomas Gleixner #define APIC_IR_MAPSIZE (APIC_IR_BITS / BITS_PER_LONG) 14749b217f33SDou Liyang 1475cc8bf191SThomas Gleixner union apic_ir { 1476cc8bf191SThomas Gleixner unsigned long map[APIC_IR_MAPSIZE]; 1477cc8bf191SThomas Gleixner u32 regs[APIC_IR_REGS]; 1478cc8bf191SThomas Gleixner }; 1479cc8bf191SThomas Gleixner 1480cc8bf191SThomas Gleixner static bool apic_check_and_ack(union apic_ir *irr, union apic_ir *isr) 1481cc8bf191SThomas Gleixner { 1482cc8bf191SThomas Gleixner int i, bit; 1483cc8bf191SThomas Gleixner 1484cc8bf191SThomas Gleixner /* Read the IRRs */ 1485cc8bf191SThomas Gleixner for (i = 0; i < APIC_IR_REGS; i++) 1486cc8bf191SThomas Gleixner irr->regs[i] = apic_read(APIC_IRR + i * 0x10); 1487cc8bf191SThomas Gleixner 1488cc8bf191SThomas Gleixner /* Read the ISRs */ 1489cc8bf191SThomas Gleixner for (i = 0; i < APIC_IR_REGS; i++) 1490cc8bf191SThomas Gleixner isr->regs[i] = apic_read(APIC_ISR + i * 0x10); 1491cc8bf191SThomas Gleixner 1492cc8bf191SThomas Gleixner /* 1493cc8bf191SThomas Gleixner * If the ISR map is not empty. ACK the APIC and run another round 1494cc8bf191SThomas Gleixner * to verify whether a pending IRR has been unblocked and turned 1495cc8bf191SThomas Gleixner * into a ISR. 1496cc8bf191SThomas Gleixner */ 1497cc8bf191SThomas Gleixner if (!bitmap_empty(isr->map, APIC_IR_BITS)) { 1498cc8bf191SThomas Gleixner /* 1499cc8bf191SThomas Gleixner * There can be multiple ISR bits set when a high priority 1500cc8bf191SThomas Gleixner * interrupt preempted a lower priority one. Issue an ACK 1501cc8bf191SThomas Gleixner * per set bit. 1502cc8bf191SThomas Gleixner */ 1503cc8bf191SThomas Gleixner for_each_set_bit(bit, isr->map, APIC_IR_BITS) 1504cc8bf191SThomas Gleixner ack_APIC_irq(); 1505cc8bf191SThomas Gleixner return true; 1506cc8bf191SThomas Gleixner } 1507cc8bf191SThomas Gleixner 1508cc8bf191SThomas Gleixner return !bitmap_empty(irr->map, APIC_IR_BITS); 1509cc8bf191SThomas Gleixner } 1510cc8bf191SThomas Gleixner 15119b217f33SDou Liyang /* 15129b217f33SDou Liyang * After a crash, we no longer service the interrupts and a pending 15139b217f33SDou Liyang * interrupt from previous kernel might still have ISR bit set. 15149b217f33SDou Liyang * 1515cc8bf191SThomas Gleixner * Most probably by now the CPU has serviced that pending interrupt and it 1516cc8bf191SThomas Gleixner * might not have done the ack_APIC_irq() because it thought, interrupt 1517cc8bf191SThomas Gleixner * came from i8259 as ExtInt. LAPIC did not get EOI so it does not clear 1518d9f6e12fSIngo Molnar * the ISR bit and cpu thinks it has already serviced the interrupt. Hence 1519cc8bf191SThomas Gleixner * a vector might get locked. It was noticed for timer irq (vector 1520cc8bf191SThomas Gleixner * 0x31). Issue an extra EOI to clear ISR. 1521cc8bf191SThomas Gleixner * 1522cc8bf191SThomas Gleixner * If there are pending IRR bits they turn into ISR bits after a higher 1523cc8bf191SThomas Gleixner * priority ISR bit has been acked. 15249b217f33SDou Liyang */ 1525cc8bf191SThomas Gleixner static void apic_pending_intr_clear(void) 1526cc8bf191SThomas Gleixner { 1527cc8bf191SThomas Gleixner union apic_ir irr, isr; 1528cc8bf191SThomas Gleixner unsigned int i; 15299b217f33SDou Liyang 1530cc8bf191SThomas Gleixner /* 512 loops are way oversized and give the APIC a chance to obey. */ 1531cc8bf191SThomas Gleixner for (i = 0; i < 512; i++) { 1532cc8bf191SThomas Gleixner if (!apic_check_and_ack(&irr, &isr)) 1533cc8bf191SThomas Gleixner return; 15349b217f33SDou Liyang } 1535cc8bf191SThomas Gleixner /* Dump the IRR/ISR content if that failed */ 1536cc8bf191SThomas Gleixner pr_warn("APIC: Stale IRR: %256pb ISR: %256pb\n", irr.map, isr.map); 15379b217f33SDou Liyang } 15389b217f33SDou Liyang 1539f62bae50SIngo Molnar /** 1540f62bae50SIngo Molnar * setup_local_APIC - setup the local APIC 15410aa002feSTejun Heo * 1542543113d2SDou Liyang * Used to setup local APIC while initializing BSP or bringing up APs. 15430aa002feSTejun Heo * Always called with preemption disabled. 1544f62bae50SIngo Molnar */ 1545b753a2b7SDou Liyang static void setup_local_APIC(void) 1546f62bae50SIngo Molnar { 15470aa002feSTejun Heo int cpu = smp_processor_id(); 15489b217f33SDou Liyang unsigned int value; 15498c3ba8d0SKerstin Jonsson 155049062454SThomas Gleixner if (apic_is_disabled) { 15517167d08eSHenrik Kretzschmar disable_ioapic_support(); 1552f62bae50SIngo Molnar return; 1553f62bae50SIngo Molnar } 1554f62bae50SIngo Molnar 15552640da4cSThomas Gleixner /* 15562640da4cSThomas Gleixner * If this comes from kexec/kcrash the APIC might be enabled in 15572640da4cSThomas Gleixner * SPIV. Soft disable it before doing further initialization. 15582640da4cSThomas Gleixner */ 15592640da4cSThomas Gleixner value = apic_read(APIC_SPIV); 15602640da4cSThomas Gleixner value &= ~APIC_SPIV_APIC_ENABLED; 15612640da4cSThomas Gleixner apic_write(APIC_SPIV, value); 15622640da4cSThomas Gleixner 1563f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1564f62bae50SIngo Molnar /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1565f62bae50SIngo Molnar if (lapic_is_integrated() && apic->disable_esr) { 1566f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1567f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1568f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1569f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1570f62bae50SIngo Molnar } 1571f62bae50SIngo Molnar #endif 1572f62bae50SIngo Molnar /* 1573f62bae50SIngo Molnar * Double-check whether this APIC is really registered. 1574f62bae50SIngo Molnar * This is meaningless in clustered apic mode, so we skip it. 1575f62bae50SIngo Molnar */ 1576c2777f98SDaniel Walker BUG_ON(!apic->apic_id_registered()); 1577f62bae50SIngo Molnar 1578f62bae50SIngo Molnar /* 1579f62bae50SIngo Molnar * Intel recommends to set DFR, LDR and TPR before enabling 1580f62bae50SIngo Molnar * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1581f62bae50SIngo Molnar * document number 292116). So here it goes... 1582f62bae50SIngo Molnar */ 1583f62bae50SIngo Molnar apic->init_apic_ldr(); 1584f62bae50SIngo Molnar 1585f62bae50SIngo Molnar /* 1586229b969bSAndy Lutomirski * Set Task Priority to 'accept all except vectors 0-31'. An APIC 1587229b969bSAndy Lutomirski * vector in the 16-31 range could be delivered if TPR == 0, but we 1588229b969bSAndy Lutomirski * would think it's an exception and terrible things will happen. We 1589229b969bSAndy Lutomirski * never change this later on. 1590f62bae50SIngo Molnar */ 1591f62bae50SIngo Molnar value = apic_read(APIC_TASKPRI); 1592f62bae50SIngo Molnar value &= ~APIC_TPRI_MASK; 1593229b969bSAndy Lutomirski value |= 0x10; 1594f62bae50SIngo Molnar apic_write(APIC_TASKPRI, value); 1595f62bae50SIngo Molnar 1596cc8bf191SThomas Gleixner /* Clear eventually stale ISR/IRR bits */ 15979b217f33SDou Liyang apic_pending_intr_clear(); 1598f62bae50SIngo Molnar 1599f62bae50SIngo Molnar /* 1600f62bae50SIngo Molnar * Now that we are all set up, enable the APIC 1601f62bae50SIngo Molnar */ 1602f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 1603f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 1604f62bae50SIngo Molnar /* 1605f62bae50SIngo Molnar * Enable APIC 1606f62bae50SIngo Molnar */ 1607f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 1608f62bae50SIngo Molnar 1609f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1610f62bae50SIngo Molnar /* 1611f62bae50SIngo Molnar * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1612f62bae50SIngo Molnar * certain networking cards. If high frequency interrupts are 1613f62bae50SIngo Molnar * happening on a particular IOAPIC pin, plus the IOAPIC routing 1614f62bae50SIngo Molnar * entry is masked/unmasked at a high rate as well then sooner or 1615f62bae50SIngo Molnar * later IOAPIC line gets 'stuck', no more interrupts are received 1616f62bae50SIngo Molnar * from the device. If focus CPU is disabled then the hang goes 1617f62bae50SIngo Molnar * away, oh well :-( 1618f62bae50SIngo Molnar * 1619f62bae50SIngo Molnar * [ This bug can be reproduced easily with a level-triggered 1620f62bae50SIngo Molnar * PCI Ne2000 networking cards and PII/PIII processors, dual 1621f62bae50SIngo Molnar * BX chipset. ] 1622f62bae50SIngo Molnar */ 1623f62bae50SIngo Molnar /* 1624f62bae50SIngo Molnar * Actually disabling the focus CPU check just makes the hang less 1625d9f6e12fSIngo Molnar * frequent as it makes the interrupt distribution model be more 1626f62bae50SIngo Molnar * like LRU than MRU (the short-term load is more even across CPUs). 1627f62bae50SIngo Molnar */ 1628f62bae50SIngo Molnar 1629f62bae50SIngo Molnar /* 1630f62bae50SIngo Molnar * - enable focus processor (bit==0) 1631f62bae50SIngo Molnar * - 64bit mode always use processor focus 1632f62bae50SIngo Molnar * so no need to set it 1633f62bae50SIngo Molnar */ 1634f62bae50SIngo Molnar value &= ~APIC_SPIV_FOCUS_DISABLED; 1635f62bae50SIngo Molnar #endif 1636f62bae50SIngo Molnar 1637f62bae50SIngo Molnar /* 1638f62bae50SIngo Molnar * Set spurious IRQ vector 1639f62bae50SIngo Molnar */ 1640f62bae50SIngo Molnar value |= SPURIOUS_APIC_VECTOR; 1641f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 1642f62bae50SIngo Molnar 164339c89dffSThomas Gleixner perf_events_lapic_init(); 164439c89dffSThomas Gleixner 1645f62bae50SIngo Molnar /* 1646f62bae50SIngo Molnar * Set up LVT0, LVT1: 1647f62bae50SIngo Molnar * 1648a1652bb8SJean Delvare * set up through-local-APIC on the boot CPU's LINT0. This is not 1649f62bae50SIngo Molnar * strictly necessary in pure symmetric-IO mode, but sometimes 1650f62bae50SIngo Molnar * we delegate interrupts to the 8259A. 1651f62bae50SIngo Molnar */ 1652f62bae50SIngo Molnar /* 1653f62bae50SIngo Molnar * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1654f62bae50SIngo Molnar */ 1655f62bae50SIngo Molnar value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1656ecf600f8SThomas Gleixner if (!cpu && (pic_mode || !value || ioapic_is_disabled)) { 1657f62bae50SIngo Molnar value = APIC_DM_EXTINT; 16580aa002feSTejun Heo apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1659f62bae50SIngo Molnar } else { 1660f62bae50SIngo Molnar value = APIC_DM_EXTINT | APIC_LVT_MASKED; 16610aa002feSTejun Heo apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1662f62bae50SIngo Molnar } 1663f62bae50SIngo Molnar apic_write(APIC_LVT0, value); 1664f62bae50SIngo Molnar 1665f62bae50SIngo Molnar /* 1666b7c4948eSHidehiro Kawai * Only the BSP sees the LINT1 NMI signal by default. This can be 1667b7c4948eSHidehiro Kawai * modified by apic_extnmi= boot option. 1668f62bae50SIngo Molnar */ 1669b7c4948eSHidehiro Kawai if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) || 1670b7c4948eSHidehiro Kawai apic_extnmi == APIC_EXTNMI_ALL) 1671f62bae50SIngo Molnar value = APIC_DM_NMI; 1672f62bae50SIngo Molnar else 1673f62bae50SIngo Molnar value = APIC_DM_NMI | APIC_LVT_MASKED; 1674ae41a2a4SDou Liyang 1675ae41a2a4SDou Liyang /* Is 82489DX ? */ 1676ae41a2a4SDou Liyang if (!lapic_is_integrated()) 1677f62bae50SIngo Molnar value |= APIC_LVT_LEVEL_TRIGGER; 1678f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 1679f62bae50SIngo Molnar 1680638bee71SH. Peter Anvin #ifdef CONFIG_X86_MCE_INTEL 1681638bee71SH. Peter Anvin /* Recheck CMCI information after local APIC is up on CPU #0 */ 16820aa002feSTejun Heo if (!cpu) 1683638bee71SH. Peter Anvin cmci_recheck(); 1684638bee71SH. Peter Anvin #endif 1685f62bae50SIngo Molnar } 1686f62bae50SIngo Molnar 168705f7e46dSThomas Gleixner static void end_local_APIC_setup(void) 1688f62bae50SIngo Molnar { 1689f62bae50SIngo Molnar lapic_setup_esr(); 1690f62bae50SIngo Molnar 1691f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1692f62bae50SIngo Molnar { 1693f62bae50SIngo Molnar unsigned int value; 1694f62bae50SIngo Molnar /* Disable the local apic timer */ 1695f62bae50SIngo Molnar value = apic_read(APIC_LVTT); 1696f62bae50SIngo Molnar value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1697f62bae50SIngo Molnar apic_write(APIC_LVTT, value); 1698f62bae50SIngo Molnar } 1699f62bae50SIngo Molnar #endif 1700f62bae50SIngo Molnar 1701f62bae50SIngo Molnar apic_pm_activate(); 17022fb270f3SJan Beulich } 17032fb270f3SJan Beulich 17047f7fbf45SKenji Kaneshige /* 170505f7e46dSThomas Gleixner * APIC setup function for application processors. Called from smpboot.c 17067f7fbf45SKenji Kaneshige */ 170705f7e46dSThomas Gleixner void apic_ap_setup(void) 170805f7e46dSThomas Gleixner { 170905f7e46dSThomas Gleixner setup_local_APIC(); 171005f7e46dSThomas Gleixner end_local_APIC_setup(); 1711f62bae50SIngo Molnar } 1712f62bae50SIngo Molnar 1713d63107faSThomas Gleixner static __init void cpu_set_boot_apic(void); 1714d63107faSThomas Gleixner 1715d10a9044SThomas Gleixner static __init void apic_read_boot_cpu_id(bool x2apic) 1716d10a9044SThomas Gleixner { 1717d10a9044SThomas Gleixner /* 1718d10a9044SThomas Gleixner * This can be invoked from check_x2apic() before the APIC has been 1719d10a9044SThomas Gleixner * selected. But that code knows for sure that the BIOS enabled 1720d10a9044SThomas Gleixner * X2APIC. 1721d10a9044SThomas Gleixner */ 1722d10a9044SThomas Gleixner if (x2apic) { 1723d10a9044SThomas Gleixner boot_cpu_physical_apicid = native_apic_msr_read(APIC_ID); 1724d10a9044SThomas Gleixner boot_cpu_apic_version = GET_APIC_VERSION(native_apic_msr_read(APIC_LVR)); 1725d10a9044SThomas Gleixner } else { 1726d10a9044SThomas Gleixner boot_cpu_physical_apicid = read_apic_id(); 1727d10a9044SThomas Gleixner boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 1728d10a9044SThomas Gleixner } 1729d63107faSThomas Gleixner cpu_set_boot_apic(); 1730d10a9044SThomas Gleixner } 1731d10a9044SThomas Gleixner 1732f62bae50SIngo Molnar #ifdef CONFIG_X86_X2APIC 1733bfb05070SThomas Gleixner int x2apic_mode; 1734db7d8e47SSean Christopherson EXPORT_SYMBOL_GPL(x2apic_mode); 173512e189d3SThomas Gleixner 173612e189d3SThomas Gleixner enum { 173712e189d3SThomas Gleixner X2APIC_OFF, 173812e189d3SThomas Gleixner X2APIC_DISABLED, 1739b8d1d163SDaniel Sneddon /* All states below here have X2APIC enabled */ 1740b8d1d163SDaniel Sneddon X2APIC_ON, 1741b8d1d163SDaniel Sneddon X2APIC_ON_LOCKED 174212e189d3SThomas Gleixner }; 174312e189d3SThomas Gleixner static int x2apic_state; 174412e189d3SThomas Gleixner 1745b8d1d163SDaniel Sneddon static bool x2apic_hw_locked(void) 1746b8d1d163SDaniel Sneddon { 1747b8d1d163SDaniel Sneddon u64 ia32_cap; 1748b8d1d163SDaniel Sneddon u64 msr; 1749b8d1d163SDaniel Sneddon 1750b8d1d163SDaniel Sneddon ia32_cap = x86_read_arch_cap_msr(); 1751b8d1d163SDaniel Sneddon if (ia32_cap & ARCH_CAP_XAPIC_DISABLE) { 1752b8d1d163SDaniel Sneddon rdmsrl(MSR_IA32_XAPIC_DISABLE_STATUS, msr); 1753b8d1d163SDaniel Sneddon return (msr & LEGACY_XAPIC_DISABLED); 1754b8d1d163SDaniel Sneddon } 1755b8d1d163SDaniel Sneddon return false; 1756b8d1d163SDaniel Sneddon } 1757b8d1d163SDaniel Sneddon 1758d786ad32SDenys Vlasenko static void __x2apic_disable(void) 175944e25ff9SThomas Gleixner { 176044e25ff9SThomas Gleixner u64 msr; 176144e25ff9SThomas Gleixner 176293984fbdSBorislav Petkov if (!boot_cpu_has(X86_FEATURE_APIC)) 1763659006bfSThomas Gleixner return; 1764659006bfSThomas Gleixner 176544e25ff9SThomas Gleixner rdmsrl(MSR_IA32_APICBASE, msr); 176644e25ff9SThomas Gleixner if (!(msr & X2APIC_ENABLE)) 176744e25ff9SThomas Gleixner return; 176844e25ff9SThomas Gleixner /* Disable xapic and x2apic first and then reenable xapic mode */ 176944e25ff9SThomas Gleixner wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); 177044e25ff9SThomas Gleixner wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); 177144e25ff9SThomas Gleixner printk_once(KERN_INFO "x2apic disabled\n"); 177244e25ff9SThomas Gleixner } 177344e25ff9SThomas Gleixner 1774d786ad32SDenys Vlasenko static void __x2apic_enable(void) 1775659006bfSThomas Gleixner { 1776659006bfSThomas Gleixner u64 msr; 1777659006bfSThomas Gleixner 1778659006bfSThomas Gleixner rdmsrl(MSR_IA32_APICBASE, msr); 1779659006bfSThomas Gleixner if (msr & X2APIC_ENABLE) 1780659006bfSThomas Gleixner return; 1781659006bfSThomas Gleixner wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); 1782659006bfSThomas Gleixner printk_once(KERN_INFO "x2apic enabled\n"); 1783659006bfSThomas Gleixner } 1784659006bfSThomas Gleixner 1785bfb05070SThomas Gleixner static int __init setup_nox2apic(char *str) 1786bfb05070SThomas Gleixner { 1787bfb05070SThomas Gleixner if (x2apic_enabled()) { 1788bfb05070SThomas Gleixner int apicid = native_apic_msr_read(APIC_ID); 1789bfb05070SThomas Gleixner 1790bfb05070SThomas Gleixner if (apicid >= 255) { 17918d3bcc44SKefeng Wang pr_warn("Apicid: %08x, cannot enforce nox2apic\n", 1792bfb05070SThomas Gleixner apicid); 1793bfb05070SThomas Gleixner return 0; 1794bfb05070SThomas Gleixner } 1795b8d1d163SDaniel Sneddon if (x2apic_hw_locked()) { 1796b8d1d163SDaniel Sneddon pr_warn("APIC locked in x2apic mode, can't disable\n"); 1797b8d1d163SDaniel Sneddon return 0; 1798b8d1d163SDaniel Sneddon } 17998d3bcc44SKefeng Wang pr_warn("x2apic already enabled.\n"); 180044e25ff9SThomas Gleixner __x2apic_disable(); 180144e25ff9SThomas Gleixner } 1802bfb05070SThomas Gleixner setup_clear_cpu_cap(X86_FEATURE_X2APIC); 180312e189d3SThomas Gleixner x2apic_state = X2APIC_DISABLED; 180444e25ff9SThomas Gleixner x2apic_mode = 0; 1805bfb05070SThomas Gleixner return 0; 1806bfb05070SThomas Gleixner } 1807bfb05070SThomas Gleixner early_param("nox2apic", setup_nox2apic); 1808bfb05070SThomas Gleixner 1809659006bfSThomas Gleixner /* Called from cpu_init() to enable x2apic on (secondary) cpus */ 1810659006bfSThomas Gleixner void x2apic_setup(void) 1811659006bfSThomas Gleixner { 1812659006bfSThomas Gleixner /* 1813b8d1d163SDaniel Sneddon * Try to make the AP's APIC state match that of the BSP, but if the 1814b8d1d163SDaniel Sneddon * BSP is unlocked and the AP is locked then there is a state mismatch. 1815b8d1d163SDaniel Sneddon * Warn about the mismatch in case a GP fault occurs due to a locked AP 1816b8d1d163SDaniel Sneddon * trying to be turned off. 1817b8d1d163SDaniel Sneddon */ 1818b8d1d163SDaniel Sneddon if (x2apic_state != X2APIC_ON_LOCKED && x2apic_hw_locked()) 1819b8d1d163SDaniel Sneddon pr_warn("x2apic lock mismatch between BSP and AP.\n"); 1820b8d1d163SDaniel Sneddon /* 1821b8d1d163SDaniel Sneddon * If x2apic is not in ON or LOCKED state, disable it if already enabled 1822659006bfSThomas Gleixner * from BIOS. 1823659006bfSThomas Gleixner */ 1824b8d1d163SDaniel Sneddon if (x2apic_state < X2APIC_ON) { 1825659006bfSThomas Gleixner __x2apic_disable(); 1826659006bfSThomas Gleixner return; 1827659006bfSThomas Gleixner } 1828659006bfSThomas Gleixner __x2apic_enable(); 1829659006bfSThomas Gleixner } 1830659006bfSThomas Gleixner 18315a88f354SThomas Gleixner static __init void apic_set_fixmap(void); 18325a88f354SThomas Gleixner 183344e25ff9SThomas Gleixner static __init void x2apic_disable(void) 1834fb209bd8SYinghai Lu { 1835a57e456aSThomas Gleixner u32 x2apic_id, state = x2apic_state; 1836fb209bd8SYinghai Lu 1837a57e456aSThomas Gleixner x2apic_mode = 0; 1838a57e456aSThomas Gleixner x2apic_state = X2APIC_DISABLED; 1839a57e456aSThomas Gleixner 1840a57e456aSThomas Gleixner if (state != X2APIC_ON) 1841a57e456aSThomas Gleixner return; 1842fb209bd8SYinghai Lu 18436d2d49d2SThomas Gleixner x2apic_id = read_apic_id(); 1844fb209bd8SYinghai Lu if (x2apic_id >= 255) 1845fb209bd8SYinghai Lu panic("Cannot disable x2apic, id: %08x\n", x2apic_id); 1846fb209bd8SYinghai Lu 1847b8d1d163SDaniel Sneddon if (x2apic_hw_locked()) { 1848b8d1d163SDaniel Sneddon pr_warn("Cannot disable locked x2apic, id: %08x\n", x2apic_id); 1849b8d1d163SDaniel Sneddon return; 1850b8d1d163SDaniel Sneddon } 1851b8d1d163SDaniel Sneddon 185244e25ff9SThomas Gleixner __x2apic_disable(); 18535a88f354SThomas Gleixner apic_set_fixmap(); 1854fb209bd8SYinghai Lu } 1855fb209bd8SYinghai Lu 1856659006bfSThomas Gleixner static __init void x2apic_enable(void) 1857f62bae50SIngo Molnar { 1858659006bfSThomas Gleixner if (x2apic_state != X2APIC_OFF) 1859f62bae50SIngo Molnar return; 1860f62bae50SIngo Molnar 1861659006bfSThomas Gleixner x2apic_mode = 1; 186212e189d3SThomas Gleixner x2apic_state = X2APIC_ON; 1863659006bfSThomas Gleixner __x2apic_enable(); 1864f62bae50SIngo Molnar } 1865d524165cSThomas Gleixner 186662e61633SThomas Gleixner static __init void try_to_enable_x2apic(int remap_mode) 186707806c50SJiang Liu { 1868659006bfSThomas Gleixner if (x2apic_state == X2APIC_DISABLED) 186907806c50SJiang Liu return; 187007806c50SJiang Liu 187162e61633SThomas Gleixner if (remap_mode != IRQ_REMAP_X2APIC_MODE) { 1872ab0f59c6SDavid Woodhouse u32 apic_limit = 255; 1873ab0f59c6SDavid Woodhouse 187426573a97SDavid Woodhouse /* 187526573a97SDavid Woodhouse * Using X2APIC without IR is not architecturally supported 187626573a97SDavid Woodhouse * on bare metal but may be supported in guests. 187707806c50SJiang Liu */ 187826573a97SDavid Woodhouse if (!x86_init.hyper.x2apic_available()) { 187962e61633SThomas Gleixner pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); 188044e25ff9SThomas Gleixner x2apic_disable(); 188107806c50SJiang Liu return; 188207806c50SJiang Liu } 188307806c50SJiang Liu 188407806c50SJiang Liu /* 1885ab0f59c6SDavid Woodhouse * If the hypervisor supports extended destination ID in 1886ab0f59c6SDavid Woodhouse * MSI, that increases the maximum APIC ID that can be 1887ab0f59c6SDavid Woodhouse * used for non-remapped IRQ domains. 1888ab0f59c6SDavid Woodhouse */ 1889ab0f59c6SDavid Woodhouse if (x86_init.hyper.msi_ext_dest_id()) { 1890ab0f59c6SDavid Woodhouse virt_ext_dest_id = 1; 1891ab0f59c6SDavid Woodhouse apic_limit = 32767; 1892ab0f59c6SDavid Woodhouse } 1893ab0f59c6SDavid Woodhouse 1894ab0f59c6SDavid Woodhouse /* 189526573a97SDavid Woodhouse * Without IR, all CPUs can be addressed by IOAPIC/MSI only 1896d9f6e12fSIngo Molnar * in physical mode, and CPUs with an APIC ID that cannot 189726573a97SDavid Woodhouse * be addressed must not be brought online. 189807806c50SJiang Liu */ 1899ab0f59c6SDavid Woodhouse x2apic_set_max_apicid(apic_limit); 190055eae7deSThomas Gleixner x2apic_phys = 1; 190107806c50SJiang Liu } 1902659006bfSThomas Gleixner x2apic_enable(); 190355eae7deSThomas Gleixner } 190455eae7deSThomas Gleixner 190555eae7deSThomas Gleixner void __init check_x2apic(void) 190655eae7deSThomas Gleixner { 190755eae7deSThomas Gleixner if (x2apic_enabled()) { 190855eae7deSThomas Gleixner pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); 190955eae7deSThomas Gleixner x2apic_mode = 1; 1910b8d1d163SDaniel Sneddon if (x2apic_hw_locked()) 1911b8d1d163SDaniel Sneddon x2apic_state = X2APIC_ON_LOCKED; 1912b8d1d163SDaniel Sneddon else 191312e189d3SThomas Gleixner x2apic_state = X2APIC_ON; 1914d10a9044SThomas Gleixner apic_read_boot_cpu_id(true); 191562436a4dSBorislav Petkov } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) { 191612e189d3SThomas Gleixner x2apic_state = X2APIC_DISABLED; 191755eae7deSThomas Gleixner } 191855eae7deSThomas Gleixner } 191955eae7deSThomas Gleixner #else /* CONFIG_X86_X2APIC */ 1920e3998434SMateusz Jończyk void __init check_x2apic(void) 192155eae7deSThomas Gleixner { 192255eae7deSThomas Gleixner if (!apic_is_x2apic_enabled()) 1923e3998434SMateusz Jończyk return; 192455eae7deSThomas Gleixner /* 1925e3998434SMateusz Jończyk * Checkme: Can we simply turn off x2APIC here instead of disabling the APIC? 192655eae7deSThomas Gleixner */ 1927e3998434SMateusz Jończyk pr_err("Kernel does not support x2APIC, please recompile with CONFIG_X86_X2APIC.\n"); 1928e3998434SMateusz Jończyk pr_err("Disabling APIC, expect reduced performance and functionality.\n"); 1929e3998434SMateusz Jończyk 193049062454SThomas Gleixner apic_is_disabled = true; 1931e3998434SMateusz Jończyk setup_clear_cpu_cap(X86_FEATURE_APIC); 193255eae7deSThomas Gleixner } 193355eae7deSThomas Gleixner 193462e61633SThomas Gleixner static inline void try_to_enable_x2apic(int remap_mode) { } 1935659006bfSThomas Gleixner static inline void __x2apic_enable(void) { } 193655eae7deSThomas Gleixner #endif /* !CONFIG_X86_X2APIC */ 193755eae7deSThomas Gleixner 1938ce69a784SGleb Natapov void __init enable_IR_x2apic(void) 1939ce69a784SGleb Natapov { 1940ce69a784SGleb Natapov unsigned long flags; 194107806c50SJiang Liu int ret, ir_stat; 1942b7f42ab2SYinghai Lu 1943ecf600f8SThomas Gleixner if (ioapic_is_disabled) { 194411277aabSDou Liyang pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); 19452e63ad4bSWanpeng Li return; 194611277aabSDou Liyang } 19472e63ad4bSWanpeng Li 194807806c50SJiang Liu ir_stat = irq_remapping_prepare(); 194907806c50SJiang Liu if (ir_stat < 0 && !x2apic_supported()) 1950e670761fSYinghai Lu return; 1951ce69a784SGleb Natapov 195231dce14aSSuresh Siddha ret = save_ioapic_entries(); 1953f62bae50SIngo Molnar if (ret) { 1954f62bae50SIngo Molnar pr_info("Saving IO-APIC state failed: %d\n", ret); 1955fb209bd8SYinghai Lu return; 1956f62bae50SIngo Molnar } 1957f62bae50SIngo Molnar 195805c3dc2cSSuresh Siddha local_irq_save(flags); 1959b81bb373SJacob Pan legacy_pic->mask_all(); 196031dce14aSSuresh Siddha mask_ioapic_entries(); 196105c3dc2cSSuresh Siddha 19626a6256f9SAdam Buchbinder /* If irq_remapping_prepare() succeeded, try to enable it */ 196307806c50SJiang Liu if (ir_stat >= 0) 196411277aabSDou Liyang ir_stat = irq_remapping_enable(); 196507806c50SJiang Liu /* ir_stat contains the remap mode or an error code */ 196607806c50SJiang Liu try_to_enable_x2apic(ir_stat); 1967a31bc327SYinghai Lu 196807806c50SJiang Liu if (ir_stat < 0) 196931dce14aSSuresh Siddha restore_ioapic_entries(); 1970b81bb373SJacob Pan legacy_pic->restore_mask(); 1971f62bae50SIngo Molnar local_irq_restore(flags); 1972f62bae50SIngo Molnar } 197393758238SWeidong Han 1974f62bae50SIngo Molnar #ifdef CONFIG_X86_64 1975f62bae50SIngo Molnar /* 1976f62bae50SIngo Molnar * Detect and enable local APICs on non-SMP boards. 1977f62bae50SIngo Molnar * Original code written by Keir Fraser. 1978f62bae50SIngo Molnar * On AMD64 we trust the BIOS - if it says no APIC it is likely 1979f62bae50SIngo Molnar * not correctly set up (usually the APIC timer won't work etc.) 1980f62bae50SIngo Molnar */ 19811751adedSThomas Gleixner static bool __init detect_init_APIC(void) 1982f62bae50SIngo Molnar { 198393984fbdSBorislav Petkov if (!boot_cpu_has(X86_FEATURE_APIC)) { 1984f62bae50SIngo Molnar pr_info("No local APIC present\n"); 19851751adedSThomas Gleixner return false; 1986f62bae50SIngo Molnar } 1987f62bae50SIngo Molnar 198881287ad6SThomas Gleixner register_lapic_address(APIC_DEFAULT_PHYS_BASE); 19891751adedSThomas Gleixner return true; 1990f62bae50SIngo Molnar } 1991f62bae50SIngo Molnar #else 19925a7ae78fSThomas Gleixner 199381287ad6SThomas Gleixner static bool __init apic_verify(unsigned long addr) 19945a7ae78fSThomas Gleixner { 19955a7ae78fSThomas Gleixner u32 features, h, l; 19965a7ae78fSThomas Gleixner 19975a7ae78fSThomas Gleixner /* 19985a7ae78fSThomas Gleixner * The APIC feature bit should now be enabled 19995a7ae78fSThomas Gleixner * in `cpuid' 20005a7ae78fSThomas Gleixner */ 20015a7ae78fSThomas Gleixner features = cpuid_edx(1); 20025a7ae78fSThomas Gleixner if (!(features & (1 << X86_FEATURE_APIC))) { 20038d3bcc44SKefeng Wang pr_warn("Could not enable APIC!\n"); 20041751adedSThomas Gleixner return false; 20055a7ae78fSThomas Gleixner } 20065a7ae78fSThomas Gleixner set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 20075a7ae78fSThomas Gleixner 20085a7ae78fSThomas Gleixner /* The BIOS may have set up the APIC at some other address */ 2009cbf2829bSBryan O'Donoghue if (boot_cpu_data.x86 >= 6) { 20105a7ae78fSThomas Gleixner rdmsr(MSR_IA32_APICBASE, l, h); 20115a7ae78fSThomas Gleixner if (l & MSR_IA32_APICBASE_ENABLE) 201281287ad6SThomas Gleixner addr = l & MSR_IA32_APICBASE_BASE; 2013cbf2829bSBryan O'Donoghue } 20145a7ae78fSThomas Gleixner 201581287ad6SThomas Gleixner register_lapic_address(addr); 20165a7ae78fSThomas Gleixner pr_info("Found and enabled local APIC!\n"); 20171751adedSThomas Gleixner return true; 20185a7ae78fSThomas Gleixner } 20195a7ae78fSThomas Gleixner 20201751adedSThomas Gleixner bool __init apic_force_enable(unsigned long addr) 20215a7ae78fSThomas Gleixner { 20225a7ae78fSThomas Gleixner u32 h, l; 20235a7ae78fSThomas Gleixner 202449062454SThomas Gleixner if (apic_is_disabled) 20251751adedSThomas Gleixner return false; 20265a7ae78fSThomas Gleixner 20275a7ae78fSThomas Gleixner /* 20285a7ae78fSThomas Gleixner * Some BIOSes disable the local APIC in the APIC_BASE 20295a7ae78fSThomas Gleixner * MSR. This can only be done in software for Intel P6 or later 20305a7ae78fSThomas Gleixner * and AMD K7 (Model > 1) or later. 20315a7ae78fSThomas Gleixner */ 2032cbf2829bSBryan O'Donoghue if (boot_cpu_data.x86 >= 6) { 20335a7ae78fSThomas Gleixner rdmsr(MSR_IA32_APICBASE, l, h); 20345a7ae78fSThomas Gleixner if (!(l & MSR_IA32_APICBASE_ENABLE)) { 20355a7ae78fSThomas Gleixner pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 20365a7ae78fSThomas Gleixner l &= ~MSR_IA32_APICBASE_BASE; 2037a906fdaaSThomas Gleixner l |= MSR_IA32_APICBASE_ENABLE | addr; 20385a7ae78fSThomas Gleixner wrmsr(MSR_IA32_APICBASE, l, h); 20395a7ae78fSThomas Gleixner enabled_via_apicbase = 1; 20405a7ae78fSThomas Gleixner } 2041cbf2829bSBryan O'Donoghue } 204281287ad6SThomas Gleixner return apic_verify(addr); 20435a7ae78fSThomas Gleixner } 20445a7ae78fSThomas Gleixner 2045f62bae50SIngo Molnar /* 2046f62bae50SIngo Molnar * Detect and initialize APIC 2047f62bae50SIngo Molnar */ 20481751adedSThomas Gleixner static bool __init detect_init_APIC(void) 2049f62bae50SIngo Molnar { 2050f62bae50SIngo Molnar /* Disabled by kernel option? */ 205149062454SThomas Gleixner if (apic_is_disabled) 20521751adedSThomas Gleixner return false; 2053f62bae50SIngo Molnar 2054f62bae50SIngo Molnar switch (boot_cpu_data.x86_vendor) { 2055f62bae50SIngo Molnar case X86_VENDOR_AMD: 2056f62bae50SIngo Molnar if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 2057f62bae50SIngo Molnar (boot_cpu_data.x86 >= 15)) 2058f62bae50SIngo Molnar break; 2059f62bae50SIngo Molnar goto no_apic; 2060da33dfefSPu Wen case X86_VENDOR_HYGON: 2061da33dfefSPu Wen break; 2062f62bae50SIngo Molnar case X86_VENDOR_INTEL: 2063f62bae50SIngo Molnar if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 206493984fbdSBorislav Petkov (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC))) 2065f62bae50SIngo Molnar break; 2066f62bae50SIngo Molnar goto no_apic; 2067f62bae50SIngo Molnar default: 2068f62bae50SIngo Molnar goto no_apic; 2069f62bae50SIngo Molnar } 2070f62bae50SIngo Molnar 207193984fbdSBorislav Petkov if (!boot_cpu_has(X86_FEATURE_APIC)) { 2072f62bae50SIngo Molnar /* 2073f62bae50SIngo Molnar * Over-ride BIOS and try to enable the local APIC only if 2074f62bae50SIngo Molnar * "lapic" specified. 2075f62bae50SIngo Molnar */ 2076f62bae50SIngo Molnar if (!force_enable_local_apic) { 2077f62bae50SIngo Molnar pr_info("Local APIC disabled by BIOS -- " 2078f62bae50SIngo Molnar "you can enable it with \"lapic\"\n"); 20791751adedSThomas Gleixner return false; 2080f62bae50SIngo Molnar } 20811751adedSThomas Gleixner if (!apic_force_enable(APIC_DEFAULT_PHYS_BASE)) 20821751adedSThomas Gleixner return false; 20835a7ae78fSThomas Gleixner } else { 208481287ad6SThomas Gleixner if (!apic_verify(APIC_DEFAULT_PHYS_BASE)) 20851751adedSThomas Gleixner return false; 2086f62bae50SIngo Molnar } 2087f62bae50SIngo Molnar 2088f62bae50SIngo Molnar apic_pm_activate(); 2089f62bae50SIngo Molnar 20901751adedSThomas Gleixner return true; 2091f62bae50SIngo Molnar 2092f62bae50SIngo Molnar no_apic: 2093f62bae50SIngo Molnar pr_info("No local APIC present or hardware disabled\n"); 20941751adedSThomas Gleixner return false; 2095f62bae50SIngo Molnar } 2096f62bae50SIngo Molnar #endif 2097f62bae50SIngo Molnar 2098f62bae50SIngo Molnar /** 2099f62bae50SIngo Molnar * init_apic_mappings - initialize APIC mappings 2100f62bae50SIngo Molnar */ 2101f62bae50SIngo Molnar void __init init_apic_mappings(void) 2102f62bae50SIngo Molnar { 2103c84cb373SThomas Gleixner if (apic_validate_deadline_timer()) 2104de308d18SBorislav Petkov pr_info("TSC deadline timer available\n"); 2105bd9240a1SPeter Zijlstra 2106d10a9044SThomas Gleixner if (x2apic_mode) 2107f62bae50SIngo Molnar return; 2108f62bae50SIngo Molnar 2109e8122513SThomas Gleixner if (!smp_found_config) { 2110e8122513SThomas Gleixner if (!detect_init_APIC()) { 21114797f6b0SYinghai Lu pr_info("APIC: disable apic facility\n"); 21124797f6b0SYinghai Lu apic_disable(); 2113cec6be6dSCyrill Gorcunov } 2114e8122513SThomas Gleixner num_processors = 1; 2115e8122513SThomas Gleixner } 2116f62bae50SIngo Molnar } 2117f62bae50SIngo Molnar 21185a88f354SThomas Gleixner static __init void apic_set_fixmap(void) 21195a88f354SThomas Gleixner { 21205a88f354SThomas Gleixner set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); 212178c32000SThomas Gleixner apic_mmio_base = APIC_BASE; 21225a88f354SThomas Gleixner apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 21235a88f354SThomas Gleixner apic_mmio_base, mp_lapic_addr); 21245a88f354SThomas Gleixner apic_read_boot_cpu_id(false); 21255a88f354SThomas Gleixner } 21265a88f354SThomas Gleixner 2127c0104d38SYinghai Lu void __init register_lapic_address(unsigned long address) 2128c0104d38SYinghai Lu { 212981287ad6SThomas Gleixner /* This should only happen once */ 213081287ad6SThomas Gleixner WARN_ON_ONCE(mp_lapic_addr); 2131c0104d38SYinghai Lu mp_lapic_addr = address; 2132c0104d38SYinghai Lu 21335a88f354SThomas Gleixner if (!x2apic_mode) 21345a88f354SThomas Gleixner apic_set_fixmap(); 2135c0104d38SYinghai Lu } 2136c0104d38SYinghai Lu 2137f62bae50SIngo Molnar /* 2138f62bae50SIngo Molnar * Local APIC interrupts 2139f62bae50SIngo Molnar */ 2140f62bae50SIngo Molnar 21413c5e0267SThomas Gleixner /* 21423c5e0267SThomas Gleixner * Common handling code for spurious_interrupt and spurious_vector entry 21433c5e0267SThomas Gleixner * points below. No point in allowing the compiler to inline it twice. 2144f62bae50SIngo Molnar */ 21453c5e0267SThomas Gleixner static noinline void handle_spurious_interrupt(u8 vector) 2146f62bae50SIngo Molnar { 2147f62bae50SIngo Molnar u32 v; 2148f62bae50SIngo Molnar 214961069de7SThomas Gleixner trace_spurious_apic_entry(vector); 215061069de7SThomas Gleixner 2151f62bae50SIngo Molnar inc_irq_stat(irq_spurious_count); 2152f62bae50SIngo Molnar 2153f8a8fe61SThomas Gleixner /* 2154f8a8fe61SThomas Gleixner * If this is a spurious interrupt then do not acknowledge 2155f8a8fe61SThomas Gleixner */ 2156f8a8fe61SThomas Gleixner if (vector == SPURIOUS_APIC_VECTOR) { 2157f8a8fe61SThomas Gleixner /* See SDM vol 3 */ 2158f8a8fe61SThomas Gleixner pr_info("Spurious APIC interrupt (vector 0xFF) on CPU#%d, should never happen.\n", 2159f8a8fe61SThomas Gleixner smp_processor_id()); 2160f8a8fe61SThomas Gleixner goto out; 2161f8a8fe61SThomas Gleixner } 2162eddc0e92SSeiji Aguchi 2163f8a8fe61SThomas Gleixner /* 2164f8a8fe61SThomas Gleixner * If it is a vectored one, verify it's set in the ISR. If set, 2165f8a8fe61SThomas Gleixner * acknowledge it. 2166f8a8fe61SThomas Gleixner */ 2167f8a8fe61SThomas Gleixner v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); 2168f8a8fe61SThomas Gleixner if (v & (1 << (vector & 0x1f))) { 2169f8a8fe61SThomas Gleixner pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Acked\n", 2170f8a8fe61SThomas Gleixner vector, smp_processor_id()); 2171f8a8fe61SThomas Gleixner ack_APIC_irq(); 2172f8a8fe61SThomas Gleixner } else { 2173f8a8fe61SThomas Gleixner pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Not pending!\n", 2174f8a8fe61SThomas Gleixner vector, smp_processor_id()); 2175f8a8fe61SThomas Gleixner } 2176f8a8fe61SThomas Gleixner out: 21772414e021SJan Beulich trace_spurious_apic_exit(vector); 2178f62bae50SIngo Molnar } 2179f62bae50SIngo Molnar 21803c5e0267SThomas Gleixner /** 21813c5e0267SThomas Gleixner * spurious_interrupt - Catch all for interrupts raised on unused vectors 21823c5e0267SThomas Gleixner * @regs: Pointer to pt_regs on stack 21833c5e0267SThomas Gleixner * @vector: The vector number 21843c5e0267SThomas Gleixner * 21853c5e0267SThomas Gleixner * This is invoked from ASM entry code to catch all interrupts which 21863c5e0267SThomas Gleixner * trigger on an entry which is routed to the common_spurious idtentry 21873c5e0267SThomas Gleixner * point. 21883c5e0267SThomas Gleixner */ 21893c5e0267SThomas Gleixner DEFINE_IDTENTRY_IRQ(spurious_interrupt) 21903c5e0267SThomas Gleixner { 21913c5e0267SThomas Gleixner handle_spurious_interrupt(vector); 21923c5e0267SThomas Gleixner } 21933c5e0267SThomas Gleixner 2194db0338eeSThomas Gleixner DEFINE_IDTENTRY_SYSVEC(sysvec_spurious_apic_interrupt) 2195633260faSThomas Gleixner { 21963c5e0267SThomas Gleixner handle_spurious_interrupt(SPURIOUS_APIC_VECTOR); 2197f62bae50SIngo Molnar } 2198f62bae50SIngo Molnar 2199f62bae50SIngo Molnar /* 2200f62bae50SIngo Molnar * This interrupt should never happen with our APIC/SMP architecture 2201f62bae50SIngo Molnar */ 2202db0338eeSThomas Gleixner DEFINE_IDTENTRY_SYSVEC(sysvec_error_interrupt) 2203f62bae50SIngo Molnar { 22042b398bd9SYouquan Song static const char * const error_interrupt_reason[] = { 22052b398bd9SYouquan Song "Send CS error", /* APIC Error Bit 0 */ 22062b398bd9SYouquan Song "Receive CS error", /* APIC Error Bit 1 */ 22072b398bd9SYouquan Song "Send accept error", /* APIC Error Bit 2 */ 22082b398bd9SYouquan Song "Receive accept error", /* APIC Error Bit 3 */ 22092b398bd9SYouquan Song "Redirectable IPI", /* APIC Error Bit 4 */ 22102b398bd9SYouquan Song "Send illegal vector", /* APIC Error Bit 5 */ 22112b398bd9SYouquan Song "Received illegal vector", /* APIC Error Bit 6 */ 22122b398bd9SYouquan Song "Illegal register address", /* APIC Error Bit 7 */ 22132b398bd9SYouquan Song }; 221461069de7SThomas Gleixner u32 v, i = 0; 221561069de7SThomas Gleixner 221661069de7SThomas Gleixner trace_error_apic_entry(ERROR_APIC_VECTOR); 2217f62bae50SIngo Molnar 2218f62bae50SIngo Molnar /* First tickle the hardware, only then report what went on. -- REW */ 2219023de4a0SMaciej W. Rozycki if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ 2220f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 222160283df7SRichard Weinberger v = apic_read(APIC_ESR); 2222f62bae50SIngo Molnar ack_APIC_irq(); 2223f62bae50SIngo Molnar atomic_inc(&irq_err_count); 2224f62bae50SIngo Molnar 222560283df7SRichard Weinberger apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", 222660283df7SRichard Weinberger smp_processor_id(), v); 22272b398bd9SYouquan Song 222860283df7SRichard Weinberger v &= 0xff; 222960283df7SRichard Weinberger while (v) { 223060283df7SRichard Weinberger if (v & 0x1) 22312b398bd9SYouquan Song apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); 22322b398bd9SYouquan Song i++; 223360283df7SRichard Weinberger v >>= 1; 22344b8073e4SPeter Senna Tschudin } 22352b398bd9SYouquan Song 22362b398bd9SYouquan Song apic_printk(APIC_DEBUG, KERN_CONT "\n"); 22372b398bd9SYouquan Song 2238cf910e83SSeiji Aguchi trace_error_apic_exit(ERROR_APIC_VECTOR); 2239f62bae50SIngo Molnar } 2240f62bae50SIngo Molnar 2241f62bae50SIngo Molnar /** 2242f62bae50SIngo Molnar * connect_bsp_APIC - attach the APIC to the interrupt system 2243f62bae50SIngo Molnar */ 224405f7e46dSThomas Gleixner static void __init connect_bsp_APIC(void) 2245f62bae50SIngo Molnar { 2246f62bae50SIngo Molnar #ifdef CONFIG_X86_32 2247f62bae50SIngo Molnar if (pic_mode) { 2248f62bae50SIngo Molnar /* 2249f62bae50SIngo Molnar * Do not trust the local APIC being empty at bootup. 2250f62bae50SIngo Molnar */ 2251f62bae50SIngo Molnar clear_local_APIC(); 2252f62bae50SIngo Molnar /* 2253f62bae50SIngo Molnar * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 2254f62bae50SIngo Molnar * local APIC to INT and NMI lines. 2255f62bae50SIngo Molnar */ 2256f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "leaving PIC mode, " 2257f62bae50SIngo Molnar "enabling APIC mode.\n"); 2258c0eaa453SCyrill Gorcunov imcr_pic_to_apic(); 2259f62bae50SIngo Molnar } 2260f62bae50SIngo Molnar #endif 2261f62bae50SIngo Molnar } 2262f62bae50SIngo Molnar 2263f62bae50SIngo Molnar /** 2264f62bae50SIngo Molnar * disconnect_bsp_APIC - detach the APIC from the interrupt system 2265f62bae50SIngo Molnar * @virt_wire_setup: indicates, whether virtual wire mode is selected 2266f62bae50SIngo Molnar * 2267f62bae50SIngo Molnar * Virtual wire mode is necessary to deliver legacy interrupts even when the 2268f62bae50SIngo Molnar * APIC is disabled. 2269f62bae50SIngo Molnar */ 2270f62bae50SIngo Molnar void disconnect_bsp_APIC(int virt_wire_setup) 2271f62bae50SIngo Molnar { 2272f62bae50SIngo Molnar unsigned int value; 2273f62bae50SIngo Molnar 2274f62bae50SIngo Molnar #ifdef CONFIG_X86_32 2275f62bae50SIngo Molnar if (pic_mode) { 2276f62bae50SIngo Molnar /* 2277f62bae50SIngo Molnar * Put the board back into PIC mode (has an effect only on 2278f62bae50SIngo Molnar * certain older boards). Note that APIC interrupts, including 2279f62bae50SIngo Molnar * IPIs, won't work beyond this point! The only exception are 2280f62bae50SIngo Molnar * INIT IPIs. 2281f62bae50SIngo Molnar */ 2282f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "disabling APIC mode, " 2283f62bae50SIngo Molnar "entering PIC mode.\n"); 2284c0eaa453SCyrill Gorcunov imcr_apic_to_pic(); 2285f62bae50SIngo Molnar return; 2286f62bae50SIngo Molnar } 2287f62bae50SIngo Molnar #endif 2288f62bae50SIngo Molnar 2289f62bae50SIngo Molnar /* Go back to Virtual Wire compatibility mode */ 2290f62bae50SIngo Molnar 2291f62bae50SIngo Molnar /* For the spurious interrupt use vector F, and enable it */ 2292f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 2293f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 2294f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 2295f62bae50SIngo Molnar value |= 0xf; 2296f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 2297f62bae50SIngo Molnar 2298f62bae50SIngo Molnar if (!virt_wire_setup) { 2299f62bae50SIngo Molnar /* 2300f62bae50SIngo Molnar * For LVT0 make it edge triggered, active high, 2301f62bae50SIngo Molnar * external and enabled 2302f62bae50SIngo Molnar */ 2303f62bae50SIngo Molnar value = apic_read(APIC_LVT0); 2304f62bae50SIngo Molnar value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2305f62bae50SIngo Molnar APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2306f62bae50SIngo Molnar APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2307f62bae50SIngo Molnar value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2308f62bae50SIngo Molnar value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 2309f62bae50SIngo Molnar apic_write(APIC_LVT0, value); 2310f62bae50SIngo Molnar } else { 2311f62bae50SIngo Molnar /* Disable LVT0 */ 2312f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_LVT_MASKED); 2313f62bae50SIngo Molnar } 2314f62bae50SIngo Molnar 2315f62bae50SIngo Molnar /* 2316f62bae50SIngo Molnar * For LVT1 make it edge triggered, active high, 2317f62bae50SIngo Molnar * nmi and enabled 2318f62bae50SIngo Molnar */ 2319f62bae50SIngo Molnar value = apic_read(APIC_LVT1); 2320f62bae50SIngo Molnar value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2321f62bae50SIngo Molnar APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2322f62bae50SIngo Molnar APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2323f62bae50SIngo Molnar value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2324f62bae50SIngo Molnar value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 2325f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 2326f62bae50SIngo Molnar } 2327f62bae50SIngo Molnar 23288f54969dSGu Zheng /* 23298f54969dSGu Zheng * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated 23308f54969dSGu Zheng * contiguously, it equals to current allocated max logical CPU ID plus 1. 233112bf98b9SDou Liyang * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range, 233212bf98b9SDou Liyang * so the maximum of nr_logical_cpuids is nr_cpu_ids. 23338f54969dSGu Zheng * 23348f54969dSGu Zheng * NOTE: Reserve 0 for BSP. 23358f54969dSGu Zheng */ 23368f54969dSGu Zheng static int nr_logical_cpuids = 1; 23378f54969dSGu Zheng 23388f54969dSGu Zheng /* 23398f54969dSGu Zheng * Used to store mapping between logical CPU IDs and APIC IDs. 23408f54969dSGu Zheng */ 23417e75178aSDavid Woodhouse int cpuid_to_apicid[] = { 23428f54969dSGu Zheng [0 ... NR_CPUS - 1] = -1, 23438f54969dSGu Zheng }; 23448f54969dSGu Zheng 2345dd926880SJohan Hovold bool arch_match_cpu_phys_id(int cpu, u64 phys_id) 2346dd926880SJohan Hovold { 2347dd926880SJohan Hovold return phys_id == cpuid_to_apicid[cpu]; 2348dd926880SJohan Hovold } 2349dd926880SJohan Hovold 2350d0055f35SVlastimil Babka #ifdef CONFIG_SMP 2351f54d4434SThomas Gleixner static void cpu_mark_primary_thread(unsigned int cpu, unsigned int apicid) 23526a4d2657SThomas Gleixner { 23536a4d2657SThomas Gleixner /* Isolate the SMT bit(s) in the APICID and check for 0 */ 2354f54d4434SThomas Gleixner u32 mask = (1U << (fls(smp_num_siblings) - 1)) - 1; 2355f54d4434SThomas Gleixner 2356f54d4434SThomas Gleixner if (smp_num_siblings == 1 || !(apicid & mask)) 2357f54d4434SThomas Gleixner cpumask_set_cpu(cpu, &__cpu_primary_thread_mask); 23586a4d2657SThomas Gleixner } 23595da80b28SThomas Gleixner 23605da80b28SThomas Gleixner /* 23615da80b28SThomas Gleixner * Due to the utter mess of CPUID evaluation smp_num_siblings is not valid 23625da80b28SThomas Gleixner * during early boot. Initialize the primary thread mask before SMP 23635da80b28SThomas Gleixner * bringup. 23645da80b28SThomas Gleixner */ 23655da80b28SThomas Gleixner static int __init smp_init_primary_thread_mask(void) 23665da80b28SThomas Gleixner { 23675da80b28SThomas Gleixner unsigned int cpu; 23685da80b28SThomas Gleixner 23695da80b28SThomas Gleixner for (cpu = 0; cpu < nr_logical_cpuids; cpu++) 23705da80b28SThomas Gleixner cpu_mark_primary_thread(cpu, cpuid_to_apicid[cpu]); 23715da80b28SThomas Gleixner return 0; 23725da80b28SThomas Gleixner } 23735da80b28SThomas Gleixner early_initcall(smp_init_primary_thread_mask); 2374f54d4434SThomas Gleixner #else 2375f54d4434SThomas Gleixner static inline void cpu_mark_primary_thread(unsigned int cpu, unsigned int apicid) { } 2376d0055f35SVlastimil Babka #endif 23776a4d2657SThomas Gleixner 23788f54969dSGu Zheng /* 23798f54969dSGu Zheng * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids 23808f54969dSGu Zheng * and cpuid_to_apicid[] synchronized. 23818f54969dSGu Zheng */ 23828f54969dSGu Zheng static int allocate_logical_cpuid(int apicid) 23838f54969dSGu Zheng { 23848f54969dSGu Zheng int i; 23858f54969dSGu Zheng 23868f54969dSGu Zheng /* 23878f54969dSGu Zheng * cpuid <-> apicid mapping is persistent, so when a cpu is up, 23888f54969dSGu Zheng * check if the kernel has allocated a cpuid for it. 23898f54969dSGu Zheng */ 23908f54969dSGu Zheng for (i = 0; i < nr_logical_cpuids; i++) { 23918f54969dSGu Zheng if (cpuid_to_apicid[i] == apicid) 23928f54969dSGu Zheng return i; 23938f54969dSGu Zheng } 23948f54969dSGu Zheng 23958f54969dSGu Zheng /* Allocate a new cpuid. */ 23968f54969dSGu Zheng if (nr_logical_cpuids >= nr_cpu_ids) { 23979b130ad5SAlexey Dobriyan WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. " 23988f54969dSGu Zheng "Processor %d/0x%x and the rest are ignored.\n", 2399bb3f0a52SDou Liyang nr_cpu_ids, nr_logical_cpuids, apicid); 2400bb3f0a52SDou Liyang return -EINVAL; 24018f54969dSGu Zheng } 24028f54969dSGu Zheng 24038f54969dSGu Zheng cpuid_to_apicid[nr_logical_cpuids] = apicid; 24048f54969dSGu Zheng return nr_logical_cpuids++; 24058f54969dSGu Zheng } 24068f54969dSGu Zheng 2407249ada2cSThomas Gleixner static void cpu_update_apic(int cpu, int apicid) 2408f62bae50SIngo Molnar { 2409f62bae50SIngo Molnar #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 2410f62bae50SIngo Molnar early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 2411f62bae50SIngo Molnar #endif 2412f62bae50SIngo Molnar set_cpu_possible(cpu, true); 2413f7c28833SGu Zheng physid_set(apicid, phys_cpu_present_map); 2414f62bae50SIngo Molnar set_cpu_present(cpu, true); 24152b85b3d2SDou Liyang num_processors++; 24167e1f85f9SJiang Liu 24175da80b28SThomas Gleixner if (system_state != SYSTEM_BOOTING) 2418f54d4434SThomas Gleixner cpu_mark_primary_thread(cpu, apicid); 2419d63107faSThomas Gleixner } 2420f54d4434SThomas Gleixner 2421d63107faSThomas Gleixner static __init void cpu_set_boot_apic(void) 2422d63107faSThomas Gleixner { 2423d63107faSThomas Gleixner cpuid_to_apicid[0] = boot_cpu_physical_apicid; 2424249ada2cSThomas Gleixner cpu_update_apic(0, boot_cpu_physical_apicid); 2425*79c9a17cSThomas Gleixner x86_32_probe_bigsmp_early(); 2426d63107faSThomas Gleixner } 2427d63107faSThomas Gleixner 2428249ada2cSThomas Gleixner int generic_processor_info(int apicid) 2429d63107faSThomas Gleixner { 2430d63107faSThomas Gleixner int cpu, max = nr_cpu_ids; 2431d63107faSThomas Gleixner 2432d63107faSThomas Gleixner /* The boot CPU must be set before MADT/MPTABLE parsing happens */ 2433d63107faSThomas Gleixner if (cpuid_to_apicid[0] == BAD_APICID) 2434d63107faSThomas Gleixner panic("Boot CPU APIC not registered yet\n"); 2435d63107faSThomas Gleixner 2436d63107faSThomas Gleixner if (apicid == boot_cpu_physical_apicid) 2437d63107faSThomas Gleixner return 0; 2438d63107faSThomas Gleixner 2439d63107faSThomas Gleixner if (disabled_cpu_apicid == apicid) { 2440d63107faSThomas Gleixner int thiscpu = num_processors + disabled_cpus; 2441d63107faSThomas Gleixner 2442d63107faSThomas Gleixner pr_warn("APIC: Disabling requested cpu. Processor %d/0x%x ignored.\n", 2443d63107faSThomas Gleixner thiscpu, apicid); 2444d63107faSThomas Gleixner 2445d63107faSThomas Gleixner disabled_cpus++; 2446d63107faSThomas Gleixner return -ENODEV; 2447d63107faSThomas Gleixner } 2448d63107faSThomas Gleixner 2449d63107faSThomas Gleixner if (num_processors >= nr_cpu_ids) { 2450d63107faSThomas Gleixner int thiscpu = max + disabled_cpus; 2451d63107faSThomas Gleixner 2452d63107faSThomas Gleixner pr_warn("APIC: NR_CPUS/possible_cpus limit of %i reached. " 2453d63107faSThomas Gleixner "Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2454d63107faSThomas Gleixner 2455d63107faSThomas Gleixner disabled_cpus++; 2456d63107faSThomas Gleixner return -EINVAL; 2457d63107faSThomas Gleixner } 2458d63107faSThomas Gleixner 2459d63107faSThomas Gleixner cpu = allocate_logical_cpuid(apicid); 2460d63107faSThomas Gleixner if (cpu < 0) { 2461d63107faSThomas Gleixner disabled_cpus++; 2462d63107faSThomas Gleixner return -EINVAL; 2463d63107faSThomas Gleixner } 2464d63107faSThomas Gleixner 2465249ada2cSThomas Gleixner cpu_update_apic(cpu, apicid); 24667e1f85f9SJiang Liu return cpu; 2467f62bae50SIngo Molnar } 2468f62bae50SIngo Molnar 2469d63107faSThomas Gleixner 2470f598181aSDavid Woodhouse void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg, 2471f598181aSDavid Woodhouse bool dmar) 2472f598181aSDavid Woodhouse { 24736285aa50SThomas Gleixner memset(msg, 0, sizeof(*msg)); 2474f598181aSDavid Woodhouse 24756285aa50SThomas Gleixner msg->arch_addr_lo.base_address = X86_MSI_BASE_ADDRESS_LOW; 24766285aa50SThomas Gleixner msg->arch_addr_lo.dest_mode_logical = apic->dest_mode_logical; 24776285aa50SThomas Gleixner msg->arch_addr_lo.destid_0_7 = cfg->dest_apicid & 0xFF; 2478f598181aSDavid Woodhouse 24796285aa50SThomas Gleixner msg->arch_data.delivery_mode = APIC_DELIVERY_MODE_FIXED; 24806285aa50SThomas Gleixner msg->arch_data.vector = cfg->vector; 2481f598181aSDavid Woodhouse 24826285aa50SThomas Gleixner msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH; 2483f598181aSDavid Woodhouse /* 2484f598181aSDavid Woodhouse * Only the IOMMU itself can use the trick of putting destination 2485f598181aSDavid Woodhouse * APIC ID into the high bits of the address. Anything else would 2486f598181aSDavid Woodhouse * just be writing to memory if it tried that, and needs IR to 2487ab0f59c6SDavid Woodhouse * address APICs which can't be addressed in the normal 32-bit 2488ab0f59c6SDavid Woodhouse * address range at 0xFFExxxxx. That is typically just 8 bits, but 2489ab0f59c6SDavid Woodhouse * some hypervisors allow the extended destination ID field in bits 2490ab0f59c6SDavid Woodhouse * 5-11 to be used, giving support for 15 bits of APIC IDs in total. 2491f598181aSDavid Woodhouse */ 2492f598181aSDavid Woodhouse if (dmar) 24936285aa50SThomas Gleixner msg->arch_addr_hi.destid_8_31 = cfg->dest_apicid >> 8; 2494ab0f59c6SDavid Woodhouse else if (virt_ext_dest_id && cfg->dest_apicid < 0x8000) 2495ab0f59c6SDavid Woodhouse msg->arch_addr_lo.virt_destid_8_14 = cfg->dest_apicid >> 8; 2496f598181aSDavid Woodhouse else 24976285aa50SThomas Gleixner WARN_ON_ONCE(cfg->dest_apicid > 0xFF); 2498f598181aSDavid Woodhouse } 2499f598181aSDavid Woodhouse 25006285aa50SThomas Gleixner u32 x86_msi_msg_get_destid(struct msi_msg *msg, bool extid) 25016285aa50SThomas Gleixner { 25026285aa50SThomas Gleixner u32 dest = msg->arch_addr_lo.destid_0_7; 25036285aa50SThomas Gleixner 25046285aa50SThomas Gleixner if (extid) 25056285aa50SThomas Gleixner dest |= msg->arch_addr_hi.destid_8_31 << 8; 25066285aa50SThomas Gleixner return dest; 25076285aa50SThomas Gleixner } 25086285aa50SThomas Gleixner EXPORT_SYMBOL_GPL(x86_msi_msg_get_destid); 25096285aa50SThomas Gleixner 2510f39642d0SKuppuswamy Sathyanarayanan #ifdef CONFIG_X86_64 2511f39642d0SKuppuswamy Sathyanarayanan void __init acpi_wake_cpu_handler_update(wakeup_cpu_handler handler) 2512f39642d0SKuppuswamy Sathyanarayanan { 2513f39642d0SKuppuswamy Sathyanarayanan struct apic **drv; 2514f39642d0SKuppuswamy Sathyanarayanan 2515f39642d0SKuppuswamy Sathyanarayanan for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) 2516f39642d0SKuppuswamy Sathyanarayanan (*drv)->wakeup_secondary_cpu_64 = handler; 2517f39642d0SKuppuswamy Sathyanarayanan } 2518f39642d0SKuppuswamy Sathyanarayanan #endif 2519f39642d0SKuppuswamy Sathyanarayanan 2520f62bae50SIngo Molnar /* 25211551df64SMichael S. Tsirkin * Override the generic EOI implementation with an optimized version. 25221551df64SMichael S. Tsirkin * Only called during early boot when only one CPU is active and with 25231551df64SMichael S. Tsirkin * interrupts disabled, so we know this does not race with actual APIC driver 25241551df64SMichael S. Tsirkin * use. 25251551df64SMichael S. Tsirkin */ 25261551df64SMichael S. Tsirkin void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) 25271551df64SMichael S. Tsirkin { 25281551df64SMichael S. Tsirkin struct apic **drv; 25291551df64SMichael S. Tsirkin 25301551df64SMichael S. Tsirkin for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { 25311551df64SMichael S. Tsirkin /* Should happen once for each apic */ 25321551df64SMichael S. Tsirkin WARN_ON((*drv)->eoi_write == eoi_write); 25338ca22552SWanpeng Li (*drv)->native_eoi_write = (*drv)->eoi_write; 25341551df64SMichael S. Tsirkin (*drv)->eoi_write = eoi_write; 25351551df64SMichael S. Tsirkin } 25361551df64SMichael S. Tsirkin } 25371551df64SMichael S. Tsirkin 2538374aab33SThomas Gleixner static void __init apic_bsp_up_setup(void) 253905f7e46dSThomas Gleixner { 2540374aab33SThomas Gleixner #ifdef CONFIG_X86_64 25415d64d209SDou Liyang apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid)); 2542374aab33SThomas Gleixner #endif 2543374aab33SThomas Gleixner physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 254405f7e46dSThomas Gleixner } 254505f7e46dSThomas Gleixner 254605f7e46dSThomas Gleixner /** 254705f7e46dSThomas Gleixner * apic_bsp_setup - Setup function for local apic and io-apic 2548374aab33SThomas Gleixner * @upmode: Force UP mode (for APIC_init_uniprocessor) 254905f7e46dSThomas Gleixner */ 2550748b170cSThomas Gleixner static void __init apic_bsp_setup(bool upmode) 255105f7e46dSThomas Gleixner { 255205f7e46dSThomas Gleixner connect_bsp_APIC(); 2553374aab33SThomas Gleixner if (upmode) 2554374aab33SThomas Gleixner apic_bsp_up_setup(); 255505f7e46dSThomas Gleixner setup_local_APIC(); 255605f7e46dSThomas Gleixner 255705f7e46dSThomas Gleixner enable_IO_APIC(); 2558374aab33SThomas Gleixner end_local_APIC_setup(); 2559374aab33SThomas Gleixner irq_remap_enable_fault_handling(); 256005f7e46dSThomas Gleixner setup_IO_APIC(); 25617d65f9e8SThomas Gleixner lapic_update_legacy_vectors(); 2562e714a91fSThomas Gleixner } 2563e714a91fSThomas Gleixner 256430b8b006SThomas Gleixner #ifdef CONFIG_UP_LATE_INIT 256530b8b006SThomas Gleixner void __init up_late_init(void) 256630b8b006SThomas Gleixner { 25670c759131SDou Liyang if (apic_intr_mode == APIC_PIC) 25680c759131SDou Liyang return; 25690c759131SDou Liyang 25700c759131SDou Liyang /* Setup local timer */ 25710c759131SDou Liyang x86_init.timers.setup_percpu_clockev(); 257230b8b006SThomas Gleixner } 257330b8b006SThomas Gleixner #endif 257430b8b006SThomas Gleixner 2575e714a91fSThomas Gleixner /* 2576f62bae50SIngo Molnar * Power management 2577f62bae50SIngo Molnar */ 2578f62bae50SIngo Molnar #ifdef CONFIG_PM 2579f62bae50SIngo Molnar 2580f62bae50SIngo Molnar static struct { 2581f62bae50SIngo Molnar /* 2582f62bae50SIngo Molnar * 'active' is true if the local APIC was enabled by us and 2583f62bae50SIngo Molnar * not the BIOS; this signifies that we are also responsible 2584f62bae50SIngo Molnar * for disabling it before entering apm/acpi suspend 2585f62bae50SIngo Molnar */ 2586f62bae50SIngo Molnar int active; 2587f62bae50SIngo Molnar /* r/w apic fields */ 2588f62bae50SIngo Molnar unsigned int apic_id; 2589f62bae50SIngo Molnar unsigned int apic_taskpri; 2590f62bae50SIngo Molnar unsigned int apic_ldr; 2591f62bae50SIngo Molnar unsigned int apic_dfr; 2592f62bae50SIngo Molnar unsigned int apic_spiv; 2593f62bae50SIngo Molnar unsigned int apic_lvtt; 2594f62bae50SIngo Molnar unsigned int apic_lvtpc; 2595f62bae50SIngo Molnar unsigned int apic_lvt0; 2596f62bae50SIngo Molnar unsigned int apic_lvt1; 2597f62bae50SIngo Molnar unsigned int apic_lvterr; 2598f62bae50SIngo Molnar unsigned int apic_tmict; 2599f62bae50SIngo Molnar unsigned int apic_tdcr; 2600f62bae50SIngo Molnar unsigned int apic_thmr; 260142baa258SJuergen Gross unsigned int apic_cmci; 2602f62bae50SIngo Molnar } apic_pm_state; 2603f62bae50SIngo Molnar 2604f3c6ea1bSRafael J. Wysocki static int lapic_suspend(void) 2605f62bae50SIngo Molnar { 2606f62bae50SIngo Molnar unsigned long flags; 2607f62bae50SIngo Molnar int maxlvt; 2608f62bae50SIngo Molnar 2609f62bae50SIngo Molnar if (!apic_pm_state.active) 2610f62bae50SIngo Molnar return 0; 2611f62bae50SIngo Molnar 2612f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 2613f62bae50SIngo Molnar 2614f62bae50SIngo Molnar apic_pm_state.apic_id = apic_read(APIC_ID); 2615f62bae50SIngo Molnar apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2616f62bae50SIngo Molnar apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2617f62bae50SIngo Molnar apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2618f62bae50SIngo Molnar apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2619f62bae50SIngo Molnar apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2620f62bae50SIngo Molnar if (maxlvt >= 4) 2621f62bae50SIngo Molnar apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2622f62bae50SIngo Molnar apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2623f62bae50SIngo Molnar apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2624f62bae50SIngo Molnar apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2625f62bae50SIngo Molnar apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2626f62bae50SIngo Molnar apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 26274efc0670SAndi Kleen #ifdef CONFIG_X86_THERMAL_VECTOR 2628f62bae50SIngo Molnar if (maxlvt >= 5) 2629f62bae50SIngo Molnar apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2630f62bae50SIngo Molnar #endif 263142baa258SJuergen Gross #ifdef CONFIG_X86_MCE_INTEL 263242baa258SJuergen Gross if (maxlvt >= 6) 263342baa258SJuergen Gross apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI); 263442baa258SJuergen Gross #endif 2635f62bae50SIngo Molnar 2636f62bae50SIngo Molnar local_irq_save(flags); 26370f378d73STony W Wang-oc 26380f378d73STony W Wang-oc /* 26390f378d73STony W Wang-oc * Mask IOAPIC before disabling the local APIC to prevent stale IRR 26400f378d73STony W Wang-oc * entries on some implementations. 26410f378d73STony W Wang-oc */ 26420f378d73STony W Wang-oc mask_ioapic_entries(); 26430f378d73STony W Wang-oc 2644f62bae50SIngo Molnar disable_local_APIC(); 2645fc1edaf9SSuresh Siddha 264695a02e97SSuresh Siddha irq_remapping_disable(); 2647fc1edaf9SSuresh Siddha 2648f62bae50SIngo Molnar local_irq_restore(flags); 2649f62bae50SIngo Molnar return 0; 2650f62bae50SIngo Molnar } 2651f62bae50SIngo Molnar 2652f3c6ea1bSRafael J. Wysocki static void lapic_resume(void) 2653f62bae50SIngo Molnar { 2654f62bae50SIngo Molnar unsigned int l, h; 2655f62bae50SIngo Molnar unsigned long flags; 265631dce14aSSuresh Siddha int maxlvt; 2657b24696bcSFenghua Yu 2658f62bae50SIngo Molnar if (!apic_pm_state.active) 2659f3c6ea1bSRafael J. Wysocki return; 2660f62bae50SIngo Molnar 2661b24696bcSFenghua Yu local_irq_save(flags); 2662336224baSJoerg Roedel 266331dce14aSSuresh Siddha /* 266431dce14aSSuresh Siddha * IO-APIC and PIC have their own resume routines. 266531dce14aSSuresh Siddha * We just mask them here to make sure the interrupt 266631dce14aSSuresh Siddha * subsystem is completely quiet while we enable x2apic 266731dce14aSSuresh Siddha * and interrupt-remapping. 266831dce14aSSuresh Siddha */ 266931dce14aSSuresh Siddha mask_ioapic_entries(); 2670b81bb373SJacob Pan legacy_pic->mask_all(); 2671f62bae50SIngo Molnar 2672659006bfSThomas Gleixner if (x2apic_mode) { 2673659006bfSThomas Gleixner __x2apic_enable(); 2674659006bfSThomas Gleixner } else { 2675f62bae50SIngo Molnar /* 2676f62bae50SIngo Molnar * Make sure the APICBASE points to the right address 2677f62bae50SIngo Molnar * 2678f62bae50SIngo Molnar * FIXME! This will be wrong if we ever support suspend on 2679f62bae50SIngo Molnar * SMP! We'll need to do this as part of the CPU restore! 2680f62bae50SIngo Molnar */ 2681cbf2829bSBryan O'Donoghue if (boot_cpu_data.x86 >= 6) { 2682f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, l, h); 2683f62bae50SIngo Molnar l &= ~MSR_IA32_APICBASE_BASE; 2684f62bae50SIngo Molnar l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2685f62bae50SIngo Molnar wrmsr(MSR_IA32_APICBASE, l, h); 2686f62bae50SIngo Molnar } 2687cbf2829bSBryan O'Donoghue } 2688f62bae50SIngo Molnar 2689b24696bcSFenghua Yu maxlvt = lapic_get_maxlvt(); 2690f62bae50SIngo Molnar apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2691f62bae50SIngo Molnar apic_write(APIC_ID, apic_pm_state.apic_id); 2692f62bae50SIngo Molnar apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2693f62bae50SIngo Molnar apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2694f62bae50SIngo Molnar apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2695f62bae50SIngo Molnar apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2696f62bae50SIngo Molnar apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2697f62bae50SIngo Molnar apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 269842baa258SJuergen Gross #ifdef CONFIG_X86_THERMAL_VECTOR 2699f62bae50SIngo Molnar if (maxlvt >= 5) 2700f62bae50SIngo Molnar apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2701f62bae50SIngo Molnar #endif 270242baa258SJuergen Gross #ifdef CONFIG_X86_MCE_INTEL 270342baa258SJuergen Gross if (maxlvt >= 6) 270442baa258SJuergen Gross apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci); 270542baa258SJuergen Gross #endif 2706f62bae50SIngo Molnar if (maxlvt >= 4) 2707f62bae50SIngo Molnar apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2708f62bae50SIngo Molnar apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2709f62bae50SIngo Molnar apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2710f62bae50SIngo Molnar apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2711f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 2712f62bae50SIngo Molnar apic_read(APIC_ESR); 2713f62bae50SIngo Molnar apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2714f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 2715f62bae50SIngo Molnar apic_read(APIC_ESR); 2716f62bae50SIngo Molnar 271795a02e97SSuresh Siddha irq_remapping_reenable(x2apic_mode); 271831dce14aSSuresh Siddha 2719f62bae50SIngo Molnar local_irq_restore(flags); 2720f62bae50SIngo Molnar } 2721f62bae50SIngo Molnar 2722f62bae50SIngo Molnar /* 2723f62bae50SIngo Molnar * This device has no shutdown method - fully functioning local APICs 2724f62bae50SIngo Molnar * are needed on every CPU up until machine_halt/restart/poweroff. 2725f62bae50SIngo Molnar */ 2726f62bae50SIngo Molnar 2727f3c6ea1bSRafael J. Wysocki static struct syscore_ops lapic_syscore_ops = { 2728f62bae50SIngo Molnar .resume = lapic_resume, 2729f62bae50SIngo Molnar .suspend = lapic_suspend, 2730f62bae50SIngo Molnar }; 2731f62bae50SIngo Molnar 2732148f9bb8SPaul Gortmaker static void apic_pm_activate(void) 2733f62bae50SIngo Molnar { 2734f62bae50SIngo Molnar apic_pm_state.active = 1; 2735f62bae50SIngo Molnar } 2736f62bae50SIngo Molnar 2737f62bae50SIngo Molnar static int __init init_lapic_sysfs(void) 2738f62bae50SIngo Molnar { 2739f62bae50SIngo Molnar /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 274093984fbdSBorislav Petkov if (boot_cpu_has(X86_FEATURE_APIC)) 2741f3c6ea1bSRafael J. Wysocki register_syscore_ops(&lapic_syscore_ops); 2742f62bae50SIngo Molnar 2743f3c6ea1bSRafael J. Wysocki return 0; 2744f62bae50SIngo Molnar } 2745b24696bcSFenghua Yu 2746b24696bcSFenghua Yu /* local apic needs to resume before other devices access its registers. */ 2747b24696bcSFenghua Yu core_initcall(init_lapic_sysfs); 2748f62bae50SIngo Molnar 2749f62bae50SIngo Molnar #else /* CONFIG_PM */ 2750f62bae50SIngo Molnar 2751f62bae50SIngo Molnar static void apic_pm_activate(void) { } 2752f62bae50SIngo Molnar 2753f62bae50SIngo Molnar #endif /* CONFIG_PM */ 2754f62bae50SIngo Molnar 2755f62bae50SIngo Molnar #ifdef CONFIG_X86_64 2756e0e42142SYinghai Lu 2757148f9bb8SPaul Gortmaker static int multi_checked; 2758148f9bb8SPaul Gortmaker static int multi; 2759e0e42142SYinghai Lu 2760148f9bb8SPaul Gortmaker static int set_multi(const struct dmi_system_id *d) 2761e0e42142SYinghai Lu { 2762e0e42142SYinghai Lu if (multi) 2763e0e42142SYinghai Lu return 0; 27646f0aced6SCyrill Gorcunov pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2765e0e42142SYinghai Lu multi = 1; 2766e0e42142SYinghai Lu return 0; 2767e0e42142SYinghai Lu } 2768e0e42142SYinghai Lu 2769148f9bb8SPaul Gortmaker static const struct dmi_system_id multi_dmi_table[] = { 2770e0e42142SYinghai Lu { 2771e0e42142SYinghai Lu .callback = set_multi, 2772e0e42142SYinghai Lu .ident = "IBM System Summit2", 2773e0e42142SYinghai Lu .matches = { 2774e0e42142SYinghai Lu DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2775e0e42142SYinghai Lu DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2776e0e42142SYinghai Lu }, 2777e0e42142SYinghai Lu }, 2778e0e42142SYinghai Lu {} 2779e0e42142SYinghai Lu }; 2780e0e42142SYinghai Lu 2781148f9bb8SPaul Gortmaker static void dmi_check_multi(void) 2782e0e42142SYinghai Lu { 2783e0e42142SYinghai Lu if (multi_checked) 2784e0e42142SYinghai Lu return; 2785e0e42142SYinghai Lu 2786e0e42142SYinghai Lu dmi_check_system(multi_dmi_table); 2787e0e42142SYinghai Lu multi_checked = 1; 2788e0e42142SYinghai Lu } 2789f62bae50SIngo Molnar 2790f62bae50SIngo Molnar /* 2791e0e42142SYinghai Lu * apic_is_clustered_box() -- Check if we can expect good TSC 2792e0e42142SYinghai Lu * 2793e0e42142SYinghai Lu * Thus far, the major user of this is IBM's Summit2 series: 2794e0e42142SYinghai Lu * Clustered boxes may have unsynced TSC problems if they are 2795e0e42142SYinghai Lu * multi-chassis. 2796e0e42142SYinghai Lu * Use DMI to check them 2797f62bae50SIngo Molnar */ 2798148f9bb8SPaul Gortmaker int apic_is_clustered_box(void) 2799e0e42142SYinghai Lu { 2800e0e42142SYinghai Lu dmi_check_multi(); 2801411cf9eeSOren Twaig return multi; 2802f62bae50SIngo Molnar } 2803f62bae50SIngo Molnar #endif 2804f62bae50SIngo Molnar 2805f62bae50SIngo Molnar /* 2806f62bae50SIngo Molnar * APIC command line parameters 2807f62bae50SIngo Molnar */ 2808f62bae50SIngo Molnar static int __init setup_disableapic(char *arg) 2809f62bae50SIngo Molnar { 281049062454SThomas Gleixner apic_is_disabled = true; 2811f62bae50SIngo Molnar setup_clear_cpu_cap(X86_FEATURE_APIC); 2812f62bae50SIngo Molnar return 0; 2813f62bae50SIngo Molnar } 2814f62bae50SIngo Molnar early_param("disableapic", setup_disableapic); 2815f62bae50SIngo Molnar 2816f62bae50SIngo Molnar /* same as disableapic, for compatibility */ 2817f62bae50SIngo Molnar static int __init setup_nolapic(char *arg) 2818f62bae50SIngo Molnar { 2819f62bae50SIngo Molnar return setup_disableapic(arg); 2820f62bae50SIngo Molnar } 2821f62bae50SIngo Molnar early_param("nolapic", setup_nolapic); 2822f62bae50SIngo Molnar 2823f62bae50SIngo Molnar static int __init parse_lapic_timer_c2_ok(char *arg) 2824f62bae50SIngo Molnar { 2825f62bae50SIngo Molnar local_apic_timer_c2_ok = 1; 2826f62bae50SIngo Molnar return 0; 2827f62bae50SIngo Molnar } 2828f62bae50SIngo Molnar early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2829f62bae50SIngo Molnar 2830f62bae50SIngo Molnar static int __init parse_disable_apic_timer(char *arg) 2831f62bae50SIngo Molnar { 2832f62bae50SIngo Molnar disable_apic_timer = 1; 2833f62bae50SIngo Molnar return 0; 2834f62bae50SIngo Molnar } 2835f62bae50SIngo Molnar early_param("noapictimer", parse_disable_apic_timer); 2836f62bae50SIngo Molnar 2837f62bae50SIngo Molnar static int __init parse_nolapic_timer(char *arg) 2838f62bae50SIngo Molnar { 2839f62bae50SIngo Molnar disable_apic_timer = 1; 2840f62bae50SIngo Molnar return 0; 2841f62bae50SIngo Molnar } 2842f62bae50SIngo Molnar early_param("nolapic_timer", parse_nolapic_timer); 2843f62bae50SIngo Molnar 2844f62bae50SIngo Molnar static int __init apic_set_verbosity(char *arg) 2845f62bae50SIngo Molnar { 2846f62bae50SIngo Molnar if (!arg) { 2847ecf600f8SThomas Gleixner if (IS_ENABLED(CONFIG_X86_32)) 2848f62bae50SIngo Molnar return -EINVAL; 2849ecf600f8SThomas Gleixner 2850ecf600f8SThomas Gleixner ioapic_is_disabled = false; 2851ecf600f8SThomas Gleixner return 0; 2852f62bae50SIngo Molnar } 2853f62bae50SIngo Molnar 2854f62bae50SIngo Molnar if (strcmp("debug", arg) == 0) 2855f62bae50SIngo Molnar apic_verbosity = APIC_DEBUG; 2856f62bae50SIngo Molnar else if (strcmp("verbose", arg) == 0) 2857f62bae50SIngo Molnar apic_verbosity = APIC_VERBOSE; 28584fcab669SDou Liyang #ifdef CONFIG_X86_64 2859f62bae50SIngo Molnar else { 28608d3bcc44SKefeng Wang pr_warn("APIC Verbosity level %s not recognised" 2861f62bae50SIngo Molnar " use apic=verbose or apic=debug\n", arg); 2862f62bae50SIngo Molnar return -EINVAL; 2863f62bae50SIngo Molnar } 28644fcab669SDou Liyang #endif 2865f62bae50SIngo Molnar 2866f62bae50SIngo Molnar return 0; 2867f62bae50SIngo Molnar } 2868f62bae50SIngo Molnar early_param("apic", apic_set_verbosity); 2869f62bae50SIngo Molnar 2870f62bae50SIngo Molnar static int __init lapic_insert_resource(void) 2871f62bae50SIngo Molnar { 287278c32000SThomas Gleixner if (!apic_mmio_base) 2873f62bae50SIngo Molnar return -1; 2874f62bae50SIngo Molnar 2875f62bae50SIngo Molnar /* Put local APIC into the resource map. */ 287678c32000SThomas Gleixner lapic_resource.start = apic_mmio_base; 2877f62bae50SIngo Molnar lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2878f62bae50SIngo Molnar insert_resource(&iomem_resource, &lapic_resource); 2879f62bae50SIngo Molnar 2880f62bae50SIngo Molnar return 0; 2881f62bae50SIngo Molnar } 2882f62bae50SIngo Molnar 2883f62bae50SIngo Molnar /* 28841506c8dcSIngo Molnar * need call insert after e820__reserve_resources() 2885f62bae50SIngo Molnar * that is using request_resource 2886f62bae50SIngo Molnar */ 2887f62bae50SIngo Molnar late_initcall(lapic_insert_resource); 2888151e0c7dSHATAYAMA Daisuke 2889151e0c7dSHATAYAMA Daisuke static int __init apic_set_disabled_cpu_apicid(char *arg) 2890151e0c7dSHATAYAMA Daisuke { 2891151e0c7dSHATAYAMA Daisuke if (!arg || !get_option(&arg, &disabled_cpu_apicid)) 2892151e0c7dSHATAYAMA Daisuke return -EINVAL; 2893151e0c7dSHATAYAMA Daisuke 2894151e0c7dSHATAYAMA Daisuke return 0; 2895151e0c7dSHATAYAMA Daisuke } 2896151e0c7dSHATAYAMA Daisuke early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); 2897b7c4948eSHidehiro Kawai 2898b7c4948eSHidehiro Kawai static int __init apic_set_extnmi(char *arg) 2899b7c4948eSHidehiro Kawai { 2900b7c4948eSHidehiro Kawai if (!arg) 2901b7c4948eSHidehiro Kawai return -EINVAL; 2902b7c4948eSHidehiro Kawai 2903b7c4948eSHidehiro Kawai if (!strncmp("all", arg, 3)) 2904b7c4948eSHidehiro Kawai apic_extnmi = APIC_EXTNMI_ALL; 2905b7c4948eSHidehiro Kawai else if (!strncmp("none", arg, 4)) 2906b7c4948eSHidehiro Kawai apic_extnmi = APIC_EXTNMI_NONE; 2907b7c4948eSHidehiro Kawai else if (!strncmp("bsp", arg, 3)) 2908b7c4948eSHidehiro Kawai apic_extnmi = APIC_EXTNMI_BSP; 2909b7c4948eSHidehiro Kawai else { 2910b7c4948eSHidehiro Kawai pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg); 2911b7c4948eSHidehiro Kawai return -EINVAL; 2912b7c4948eSHidehiro Kawai } 2913b7c4948eSHidehiro Kawai 2914b7c4948eSHidehiro Kawai return 0; 2915b7c4948eSHidehiro Kawai } 2916b7c4948eSHidehiro Kawai early_param("apic_extnmi", apic_set_extnmi); 2917