1f62bae50SIngo Molnar /* 2f62bae50SIngo Molnar * Local APIC handling, local APIC timers 3f62bae50SIngo Molnar * 4f62bae50SIngo Molnar * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 5f62bae50SIngo Molnar * 6f62bae50SIngo Molnar * Fixes 7f62bae50SIngo Molnar * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8f62bae50SIngo Molnar * thanks to Eric Gilmore 9f62bae50SIngo Molnar * and Rolf G. Tews 10f62bae50SIngo Molnar * for testing these extensively. 11f62bae50SIngo Molnar * Maciej W. Rozycki : Various updates and fixes. 12f62bae50SIngo Molnar * Mikael Pettersson : Power Management for UP-APIC. 13f62bae50SIngo Molnar * Pavel Machek and 14f62bae50SIngo Molnar * Mikael Pettersson : PM converted to driver model. 15f62bae50SIngo Molnar */ 16f62bae50SIngo Molnar 17cdd6c482SIngo Molnar #include <linux/perf_event.h> 18f62bae50SIngo Molnar #include <linux/kernel_stat.h> 19f62bae50SIngo Molnar #include <linux/mc146818rtc.h> 20f62bae50SIngo Molnar #include <linux/acpi_pmtmr.h> 21f62bae50SIngo Molnar #include <linux/clockchips.h> 22f62bae50SIngo Molnar #include <linux/interrupt.h> 23f62bae50SIngo Molnar #include <linux/bootmem.h> 24f62bae50SIngo Molnar #include <linux/ftrace.h> 25f62bae50SIngo Molnar #include <linux/ioport.h> 26f62bae50SIngo Molnar #include <linux/module.h> 27f62bae50SIngo Molnar #include <linux/sysdev.h> 28f62bae50SIngo Molnar #include <linux/delay.h> 29f62bae50SIngo Molnar #include <linux/timex.h> 30f62bae50SIngo Molnar #include <linux/dmar.h> 31f62bae50SIngo Molnar #include <linux/init.h> 32f62bae50SIngo Molnar #include <linux/cpu.h> 33f62bae50SIngo Molnar #include <linux/dmi.h> 34f62bae50SIngo Molnar #include <linux/nmi.h> 35f62bae50SIngo Molnar #include <linux/smp.h> 36f62bae50SIngo Molnar #include <linux/mm.h> 37f62bae50SIngo Molnar 38cdd6c482SIngo Molnar #include <asm/perf_event.h> 39736decacSThomas Gleixner #include <asm/x86_init.h> 40f62bae50SIngo Molnar #include <asm/pgalloc.h> 41f62bae50SIngo Molnar #include <asm/atomic.h> 42f62bae50SIngo Molnar #include <asm/mpspec.h> 43f62bae50SIngo Molnar #include <asm/i8253.h> 44f62bae50SIngo Molnar #include <asm/i8259.h> 45f62bae50SIngo Molnar #include <asm/proto.h> 46f62bae50SIngo Molnar #include <asm/apic.h> 47f62bae50SIngo Molnar #include <asm/desc.h> 48f62bae50SIngo Molnar #include <asm/hpet.h> 49f62bae50SIngo Molnar #include <asm/idle.h> 50f62bae50SIngo Molnar #include <asm/mtrr.h> 51f62bae50SIngo Molnar #include <asm/smp.h> 52638bee71SH. Peter Anvin #include <asm/mce.h> 53ce69a784SGleb Natapov #include <asm/kvm_para.h> 548c3ba8d0SKerstin Jonsson #include <asm/tsc.h> 55f62bae50SIngo Molnar 56f62bae50SIngo Molnar unsigned int num_processors; 57f62bae50SIngo Molnar 58f62bae50SIngo Molnar unsigned disabled_cpus __cpuinitdata; 59f62bae50SIngo Molnar 60f62bae50SIngo Molnar /* Processor that is doing the boot up */ 61f62bae50SIngo Molnar unsigned int boot_cpu_physical_apicid = -1U; 62f62bae50SIngo Molnar 63f62bae50SIngo Molnar /* 64f62bae50SIngo Molnar * The highest APIC ID seen during enumeration. 65f62bae50SIngo Molnar */ 66f62bae50SIngo Molnar unsigned int max_physical_apicid; 67f62bae50SIngo Molnar 68f62bae50SIngo Molnar /* 69f62bae50SIngo Molnar * Bitmask of physically existing CPUs: 70f62bae50SIngo Molnar */ 71f62bae50SIngo Molnar physid_mask_t phys_cpu_present_map; 72f62bae50SIngo Molnar 73f62bae50SIngo Molnar /* 74f62bae50SIngo Molnar * Map cpu index to physical APIC ID 75f62bae50SIngo Molnar */ 76f62bae50SIngo Molnar DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID); 77f62bae50SIngo Molnar DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID); 78f62bae50SIngo Molnar EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 79f62bae50SIngo Molnar EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 80f62bae50SIngo Molnar 81f62bae50SIngo Molnar #ifdef CONFIG_X86_32 82f62bae50SIngo Molnar /* 83f62bae50SIngo Molnar * Knob to control our willingness to enable the local APIC. 84f62bae50SIngo Molnar * 85f62bae50SIngo Molnar * +1=force-enable 86f62bae50SIngo Molnar */ 87f62bae50SIngo Molnar static int force_enable_local_apic; 88f62bae50SIngo Molnar /* 89f62bae50SIngo Molnar * APIC command line parameters 90f62bae50SIngo Molnar */ 91f62bae50SIngo Molnar static int __init parse_lapic(char *arg) 92f62bae50SIngo Molnar { 93f62bae50SIngo Molnar force_enable_local_apic = 1; 94f62bae50SIngo Molnar return 0; 95f62bae50SIngo Molnar } 96f62bae50SIngo Molnar early_param("lapic", parse_lapic); 97f62bae50SIngo Molnar /* Local APIC was disabled by the BIOS and enabled by the kernel */ 98f62bae50SIngo Molnar static int enabled_via_apicbase; 99f62bae50SIngo Molnar 100c0eaa453SCyrill Gorcunov /* 101c0eaa453SCyrill Gorcunov * Handle interrupt mode configuration register (IMCR). 102c0eaa453SCyrill Gorcunov * This register controls whether the interrupt signals 103c0eaa453SCyrill Gorcunov * that reach the BSP come from the master PIC or from the 104c0eaa453SCyrill Gorcunov * local APIC. Before entering Symmetric I/O Mode, either 105c0eaa453SCyrill Gorcunov * the BIOS or the operating system must switch out of 106c0eaa453SCyrill Gorcunov * PIC Mode by changing the IMCR. 107c0eaa453SCyrill Gorcunov */ 1085cda395fSAlexander van Heukelum static inline void imcr_pic_to_apic(void) 109c0eaa453SCyrill Gorcunov { 110c0eaa453SCyrill Gorcunov /* select IMCR register */ 111c0eaa453SCyrill Gorcunov outb(0x70, 0x22); 112c0eaa453SCyrill Gorcunov /* NMI and 8259 INTR go through APIC */ 113c0eaa453SCyrill Gorcunov outb(0x01, 0x23); 114c0eaa453SCyrill Gorcunov } 115c0eaa453SCyrill Gorcunov 1165cda395fSAlexander van Heukelum static inline void imcr_apic_to_pic(void) 117c0eaa453SCyrill Gorcunov { 118c0eaa453SCyrill Gorcunov /* select IMCR register */ 119c0eaa453SCyrill Gorcunov outb(0x70, 0x22); 120c0eaa453SCyrill Gorcunov /* NMI and 8259 INTR go directly to BSP */ 121c0eaa453SCyrill Gorcunov outb(0x00, 0x23); 122c0eaa453SCyrill Gorcunov } 123f62bae50SIngo Molnar #endif 124f62bae50SIngo Molnar 125f62bae50SIngo Molnar #ifdef CONFIG_X86_64 126f62bae50SIngo Molnar static int apic_calibrate_pmtmr __initdata; 127f62bae50SIngo Molnar static __init int setup_apicpmtimer(char *s) 128f62bae50SIngo Molnar { 129f62bae50SIngo Molnar apic_calibrate_pmtmr = 1; 130f62bae50SIngo Molnar notsc_setup(NULL); 131f62bae50SIngo Molnar return 0; 132f62bae50SIngo Molnar } 133f62bae50SIngo Molnar __setup("apicpmtimer", setup_apicpmtimer); 134f62bae50SIngo Molnar #endif 135f62bae50SIngo Molnar 136fc1edaf9SSuresh Siddha int x2apic_mode; 137f62bae50SIngo Molnar #ifdef CONFIG_X86_X2APIC 138f62bae50SIngo Molnar /* x2apic enabled before OS handover */ 139f62bae50SIngo Molnar static int x2apic_preenabled; 140f62bae50SIngo Molnar static __init int setup_nox2apic(char *str) 141f62bae50SIngo Molnar { 14239d83a5dSSuresh Siddha if (x2apic_enabled()) { 14339d83a5dSSuresh Siddha pr_warning("Bios already enabled x2apic, " 14439d83a5dSSuresh Siddha "can't enforce nox2apic"); 14539d83a5dSSuresh Siddha return 0; 14639d83a5dSSuresh Siddha } 14739d83a5dSSuresh Siddha 148f62bae50SIngo Molnar setup_clear_cpu_cap(X86_FEATURE_X2APIC); 149f62bae50SIngo Molnar return 0; 150f62bae50SIngo Molnar } 151f62bae50SIngo Molnar early_param("nox2apic", setup_nox2apic); 152f62bae50SIngo Molnar #endif 153f62bae50SIngo Molnar 154f62bae50SIngo Molnar unsigned long mp_lapic_addr; 155f62bae50SIngo Molnar int disable_apic; 156f62bae50SIngo Molnar /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 157f62bae50SIngo Molnar static int disable_apic_timer __cpuinitdata; 158f62bae50SIngo Molnar /* Local APIC timer works in C2 */ 159f62bae50SIngo Molnar int local_apic_timer_c2_ok; 160f62bae50SIngo Molnar EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 161f62bae50SIngo Molnar 162f62bae50SIngo Molnar int first_system_vector = 0xfe; 163f62bae50SIngo Molnar 164f62bae50SIngo Molnar /* 165f62bae50SIngo Molnar * Debug level, exported for io_apic.c 166f62bae50SIngo Molnar */ 167f62bae50SIngo Molnar unsigned int apic_verbosity; 168f62bae50SIngo Molnar 169f62bae50SIngo Molnar int pic_mode; 170f62bae50SIngo Molnar 171f62bae50SIngo Molnar /* Have we found an MP table */ 172f62bae50SIngo Molnar int smp_found_config; 173f62bae50SIngo Molnar 174f62bae50SIngo Molnar static struct resource lapic_resource = { 175f62bae50SIngo Molnar .name = "Local APIC", 176f62bae50SIngo Molnar .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 177f62bae50SIngo Molnar }; 178f62bae50SIngo Molnar 179f62bae50SIngo Molnar static unsigned int calibration_result; 180f62bae50SIngo Molnar 181f62bae50SIngo Molnar static int lapic_next_event(unsigned long delta, 182f62bae50SIngo Molnar struct clock_event_device *evt); 183f62bae50SIngo Molnar static void lapic_timer_setup(enum clock_event_mode mode, 184f62bae50SIngo Molnar struct clock_event_device *evt); 185f62bae50SIngo Molnar static void lapic_timer_broadcast(const struct cpumask *mask); 186f62bae50SIngo Molnar static void apic_pm_activate(void); 187f62bae50SIngo Molnar 188f62bae50SIngo Molnar /* 189f62bae50SIngo Molnar * The local apic timer can be used for any function which is CPU local. 190f62bae50SIngo Molnar */ 191f62bae50SIngo Molnar static struct clock_event_device lapic_clockevent = { 192f62bae50SIngo Molnar .name = "lapic", 193f62bae50SIngo Molnar .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT 194f62bae50SIngo Molnar | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, 195f62bae50SIngo Molnar .shift = 32, 196f62bae50SIngo Molnar .set_mode = lapic_timer_setup, 197f62bae50SIngo Molnar .set_next_event = lapic_next_event, 198f62bae50SIngo Molnar .broadcast = lapic_timer_broadcast, 199f62bae50SIngo Molnar .rating = 100, 200f62bae50SIngo Molnar .irq = -1, 201f62bae50SIngo Molnar }; 202f62bae50SIngo Molnar static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 203f62bae50SIngo Molnar 204f62bae50SIngo Molnar static unsigned long apic_phys; 205f62bae50SIngo Molnar 206f62bae50SIngo Molnar /* 207f62bae50SIngo Molnar * Get the LAPIC version 208f62bae50SIngo Molnar */ 209f62bae50SIngo Molnar static inline int lapic_get_version(void) 210f62bae50SIngo Molnar { 211f62bae50SIngo Molnar return GET_APIC_VERSION(apic_read(APIC_LVR)); 212f62bae50SIngo Molnar } 213f62bae50SIngo Molnar 214f62bae50SIngo Molnar /* 215f62bae50SIngo Molnar * Check, if the APIC is integrated or a separate chip 216f62bae50SIngo Molnar */ 217f62bae50SIngo Molnar static inline int lapic_is_integrated(void) 218f62bae50SIngo Molnar { 219f62bae50SIngo Molnar #ifdef CONFIG_X86_64 220f62bae50SIngo Molnar return 1; 221f62bae50SIngo Molnar #else 222f62bae50SIngo Molnar return APIC_INTEGRATED(lapic_get_version()); 223f62bae50SIngo Molnar #endif 224f62bae50SIngo Molnar } 225f62bae50SIngo Molnar 226f62bae50SIngo Molnar /* 227f62bae50SIngo Molnar * Check, whether this is a modern or a first generation APIC 228f62bae50SIngo Molnar */ 229f62bae50SIngo Molnar static int modern_apic(void) 230f62bae50SIngo Molnar { 231f62bae50SIngo Molnar /* AMD systems use old APIC versions, so check the CPU */ 232f62bae50SIngo Molnar if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 233f62bae50SIngo Molnar boot_cpu_data.x86 >= 0xf) 234f62bae50SIngo Molnar return 1; 235f62bae50SIngo Molnar return lapic_get_version() >= 0x14; 236f62bae50SIngo Molnar } 237f62bae50SIngo Molnar 23808306ce6SCyrill Gorcunov /* 239a933c618SCyrill Gorcunov * right after this call apic become NOOP driven 240a933c618SCyrill Gorcunov * so apic->write/read doesn't do anything 24108306ce6SCyrill Gorcunov */ 24208306ce6SCyrill Gorcunov void apic_disable(void) 24308306ce6SCyrill Gorcunov { 244f88f2b4fSCyrill Gorcunov pr_info("APIC: switched to apic NOOP\n"); 245a933c618SCyrill Gorcunov apic = &apic_noop; 24608306ce6SCyrill Gorcunov } 24708306ce6SCyrill Gorcunov 248f62bae50SIngo Molnar void native_apic_wait_icr_idle(void) 249f62bae50SIngo Molnar { 250f62bae50SIngo Molnar while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 251f62bae50SIngo Molnar cpu_relax(); 252f62bae50SIngo Molnar } 253f62bae50SIngo Molnar 254f62bae50SIngo Molnar u32 native_safe_apic_wait_icr_idle(void) 255f62bae50SIngo Molnar { 256f62bae50SIngo Molnar u32 send_status; 257f62bae50SIngo Molnar int timeout; 258f62bae50SIngo Molnar 259f62bae50SIngo Molnar timeout = 0; 260f62bae50SIngo Molnar do { 261f62bae50SIngo Molnar send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 262f62bae50SIngo Molnar if (!send_status) 263f62bae50SIngo Molnar break; 264f62bae50SIngo Molnar udelay(100); 265f62bae50SIngo Molnar } while (timeout++ < 1000); 266f62bae50SIngo Molnar 267f62bae50SIngo Molnar return send_status; 268f62bae50SIngo Molnar } 269f62bae50SIngo Molnar 270f62bae50SIngo Molnar void native_apic_icr_write(u32 low, u32 id) 271f62bae50SIngo Molnar { 272f62bae50SIngo Molnar apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 273f62bae50SIngo Molnar apic_write(APIC_ICR, low); 274f62bae50SIngo Molnar } 275f62bae50SIngo Molnar 276f62bae50SIngo Molnar u64 native_apic_icr_read(void) 277f62bae50SIngo Molnar { 278f62bae50SIngo Molnar u32 icr1, icr2; 279f62bae50SIngo Molnar 280f62bae50SIngo Molnar icr2 = apic_read(APIC_ICR2); 281f62bae50SIngo Molnar icr1 = apic_read(APIC_ICR); 282f62bae50SIngo Molnar 283f62bae50SIngo Molnar return icr1 | ((u64)icr2 << 32); 284f62bae50SIngo Molnar } 285f62bae50SIngo Molnar 286f62bae50SIngo Molnar /** 287f62bae50SIngo Molnar * enable_NMI_through_LVT0 - enable NMI through local vector table 0 288f62bae50SIngo Molnar */ 289f62bae50SIngo Molnar void __cpuinit enable_NMI_through_LVT0(void) 290f62bae50SIngo Molnar { 291f62bae50SIngo Molnar unsigned int v; 292f62bae50SIngo Molnar 293f62bae50SIngo Molnar /* unmask and set to NMI */ 294f62bae50SIngo Molnar v = APIC_DM_NMI; 295f62bae50SIngo Molnar 296f62bae50SIngo Molnar /* Level triggered for 82489DX (32bit mode) */ 297f62bae50SIngo Molnar if (!lapic_is_integrated()) 298f62bae50SIngo Molnar v |= APIC_LVT_LEVEL_TRIGGER; 299f62bae50SIngo Molnar 300f62bae50SIngo Molnar apic_write(APIC_LVT0, v); 301f62bae50SIngo Molnar } 302f62bae50SIngo Molnar 303f62bae50SIngo Molnar #ifdef CONFIG_X86_32 304f62bae50SIngo Molnar /** 305f62bae50SIngo Molnar * get_physical_broadcast - Get number of physical broadcast IDs 306f62bae50SIngo Molnar */ 307f62bae50SIngo Molnar int get_physical_broadcast(void) 308f62bae50SIngo Molnar { 309f62bae50SIngo Molnar return modern_apic() ? 0xff : 0xf; 310f62bae50SIngo Molnar } 311f62bae50SIngo Molnar #endif 312f62bae50SIngo Molnar 313f62bae50SIngo Molnar /** 314f62bae50SIngo Molnar * lapic_get_maxlvt - get the maximum number of local vector table entries 315f62bae50SIngo Molnar */ 316f62bae50SIngo Molnar int lapic_get_maxlvt(void) 317f62bae50SIngo Molnar { 318f62bae50SIngo Molnar unsigned int v; 319f62bae50SIngo Molnar 320f62bae50SIngo Molnar v = apic_read(APIC_LVR); 321f62bae50SIngo Molnar /* 322f62bae50SIngo Molnar * - we always have APIC integrated on 64bit mode 323f62bae50SIngo Molnar * - 82489DXs do not report # of LVT entries 324f62bae50SIngo Molnar */ 325f62bae50SIngo Molnar return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; 326f62bae50SIngo Molnar } 327f62bae50SIngo Molnar 328f62bae50SIngo Molnar /* 329f62bae50SIngo Molnar * Local APIC timer 330f62bae50SIngo Molnar */ 331f62bae50SIngo Molnar 332f62bae50SIngo Molnar /* Clock divisor */ 333f62bae50SIngo Molnar #define APIC_DIVISOR 16 334f62bae50SIngo Molnar 335f62bae50SIngo Molnar /* 336f62bae50SIngo Molnar * This function sets up the local APIC timer, with a timeout of 337f62bae50SIngo Molnar * 'clocks' APIC bus clock. During calibration we actually call 338f62bae50SIngo Molnar * this function twice on the boot CPU, once with a bogus timeout 339f62bae50SIngo Molnar * value, second time for real. The other (noncalibrating) CPUs 340f62bae50SIngo Molnar * call this function only once, with the real, calibrated value. 341f62bae50SIngo Molnar * 342f62bae50SIngo Molnar * We do reads before writes even if unnecessary, to get around the 343f62bae50SIngo Molnar * P5 APIC double write bug. 344f62bae50SIngo Molnar */ 345f62bae50SIngo Molnar static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 346f62bae50SIngo Molnar { 347f62bae50SIngo Molnar unsigned int lvtt_value, tmp_value; 348f62bae50SIngo Molnar 349f62bae50SIngo Molnar lvtt_value = LOCAL_TIMER_VECTOR; 350f62bae50SIngo Molnar if (!oneshot) 351f62bae50SIngo Molnar lvtt_value |= APIC_LVT_TIMER_PERIODIC; 352f62bae50SIngo Molnar if (!lapic_is_integrated()) 353f62bae50SIngo Molnar lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 354f62bae50SIngo Molnar 355f62bae50SIngo Molnar if (!irqen) 356f62bae50SIngo Molnar lvtt_value |= APIC_LVT_MASKED; 357f62bae50SIngo Molnar 358f62bae50SIngo Molnar apic_write(APIC_LVTT, lvtt_value); 359f62bae50SIngo Molnar 360f62bae50SIngo Molnar /* 361f62bae50SIngo Molnar * Divide PICLK by 16 362f62bae50SIngo Molnar */ 363f62bae50SIngo Molnar tmp_value = apic_read(APIC_TDCR); 364f62bae50SIngo Molnar apic_write(APIC_TDCR, 365f62bae50SIngo Molnar (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 366f62bae50SIngo Molnar APIC_TDR_DIV_16); 367f62bae50SIngo Molnar 368f62bae50SIngo Molnar if (!oneshot) 369f62bae50SIngo Molnar apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 370f62bae50SIngo Molnar } 371f62bae50SIngo Molnar 372f62bae50SIngo Molnar /* 373f62bae50SIngo Molnar * Setup extended LVT, AMD specific (K8, family 10h) 374f62bae50SIngo Molnar * 375f62bae50SIngo Molnar * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and 376f62bae50SIngo Molnar * MCE interrupts are supported. Thus MCE offset must be set to 0. 377f62bae50SIngo Molnar * 378f62bae50SIngo Molnar * If mask=1, the LVT entry does not generate interrupts while mask=0 379f62bae50SIngo Molnar * enables the vector. See also the BKDGs. 380f62bae50SIngo Molnar */ 381f62bae50SIngo Molnar 382f62bae50SIngo Molnar #define APIC_EILVT_LVTOFF_MCE 0 383f62bae50SIngo Molnar #define APIC_EILVT_LVTOFF_IBS 1 384f62bae50SIngo Molnar 385f62bae50SIngo Molnar static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) 386f62bae50SIngo Molnar { 38797a52714SAndreas Herrmann unsigned long reg = (lvt_off << 4) + APIC_EILVTn(0); 388f62bae50SIngo Molnar unsigned int v = (mask << 16) | (msg_type << 8) | vector; 389f62bae50SIngo Molnar 390f62bae50SIngo Molnar apic_write(reg, v); 391f62bae50SIngo Molnar } 392f62bae50SIngo Molnar 393f62bae50SIngo Molnar u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) 394f62bae50SIngo Molnar { 395f62bae50SIngo Molnar setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); 396f62bae50SIngo Molnar return APIC_EILVT_LVTOFF_MCE; 397f62bae50SIngo Molnar } 398f62bae50SIngo Molnar 399f62bae50SIngo Molnar u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) 400f62bae50SIngo Molnar { 401f62bae50SIngo Molnar setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); 402f62bae50SIngo Molnar return APIC_EILVT_LVTOFF_IBS; 403f62bae50SIngo Molnar } 404f62bae50SIngo Molnar EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs); 405f62bae50SIngo Molnar 406f62bae50SIngo Molnar /* 407f62bae50SIngo Molnar * Program the next event, relative to now 408f62bae50SIngo Molnar */ 409f62bae50SIngo Molnar static int lapic_next_event(unsigned long delta, 410f62bae50SIngo Molnar struct clock_event_device *evt) 411f62bae50SIngo Molnar { 412f62bae50SIngo Molnar apic_write(APIC_TMICT, delta); 413f62bae50SIngo Molnar return 0; 414f62bae50SIngo Molnar } 415f62bae50SIngo Molnar 416f62bae50SIngo Molnar /* 417f62bae50SIngo Molnar * Setup the lapic timer in periodic or oneshot mode 418f62bae50SIngo Molnar */ 419f62bae50SIngo Molnar static void lapic_timer_setup(enum clock_event_mode mode, 420f62bae50SIngo Molnar struct clock_event_device *evt) 421f62bae50SIngo Molnar { 422f62bae50SIngo Molnar unsigned long flags; 423f62bae50SIngo Molnar unsigned int v; 424f62bae50SIngo Molnar 425f62bae50SIngo Molnar /* Lapic used as dummy for broadcast ? */ 426f62bae50SIngo Molnar if (evt->features & CLOCK_EVT_FEAT_DUMMY) 427f62bae50SIngo Molnar return; 428f62bae50SIngo Molnar 429f62bae50SIngo Molnar local_irq_save(flags); 430f62bae50SIngo Molnar 431f62bae50SIngo Molnar switch (mode) { 432f62bae50SIngo Molnar case CLOCK_EVT_MODE_PERIODIC: 433f62bae50SIngo Molnar case CLOCK_EVT_MODE_ONESHOT: 434f62bae50SIngo Molnar __setup_APIC_LVTT(calibration_result, 435f62bae50SIngo Molnar mode != CLOCK_EVT_MODE_PERIODIC, 1); 436f62bae50SIngo Molnar break; 437f62bae50SIngo Molnar case CLOCK_EVT_MODE_UNUSED: 438f62bae50SIngo Molnar case CLOCK_EVT_MODE_SHUTDOWN: 439f62bae50SIngo Molnar v = apic_read(APIC_LVTT); 440f62bae50SIngo Molnar v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 441f62bae50SIngo Molnar apic_write(APIC_LVTT, v); 4426f9b4100SAndreas Herrmann apic_write(APIC_TMICT, 0); 443f62bae50SIngo Molnar break; 444f62bae50SIngo Molnar case CLOCK_EVT_MODE_RESUME: 445f62bae50SIngo Molnar /* Nothing to do here */ 446f62bae50SIngo Molnar break; 447f62bae50SIngo Molnar } 448f62bae50SIngo Molnar 449f62bae50SIngo Molnar local_irq_restore(flags); 450f62bae50SIngo Molnar } 451f62bae50SIngo Molnar 452f62bae50SIngo Molnar /* 453f62bae50SIngo Molnar * Local APIC timer broadcast function 454f62bae50SIngo Molnar */ 455f62bae50SIngo Molnar static void lapic_timer_broadcast(const struct cpumask *mask) 456f62bae50SIngo Molnar { 457f62bae50SIngo Molnar #ifdef CONFIG_SMP 458f62bae50SIngo Molnar apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 459f62bae50SIngo Molnar #endif 460f62bae50SIngo Molnar } 461f62bae50SIngo Molnar 462f62bae50SIngo Molnar /* 463f62bae50SIngo Molnar * Setup the local APIC timer for this CPU. Copy the initilized values 464f62bae50SIngo Molnar * of the boot CPU and register the clock event in the framework. 465f62bae50SIngo Molnar */ 466f62bae50SIngo Molnar static void __cpuinit setup_APIC_timer(void) 467f62bae50SIngo Molnar { 468f62bae50SIngo Molnar struct clock_event_device *levt = &__get_cpu_var(lapic_events); 469f62bae50SIngo Molnar 470db954b58SVenkatesh Pallipadi if (cpu_has(¤t_cpu_data, X86_FEATURE_ARAT)) { 471db954b58SVenkatesh Pallipadi lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 472db954b58SVenkatesh Pallipadi /* Make LAPIC timer preferrable over percpu HPET */ 473db954b58SVenkatesh Pallipadi lapic_clockevent.rating = 150; 474db954b58SVenkatesh Pallipadi } 475db954b58SVenkatesh Pallipadi 476f62bae50SIngo Molnar memcpy(levt, &lapic_clockevent, sizeof(*levt)); 477f62bae50SIngo Molnar levt->cpumask = cpumask_of(smp_processor_id()); 478f62bae50SIngo Molnar 479f62bae50SIngo Molnar clockevents_register_device(levt); 480f62bae50SIngo Molnar } 481f62bae50SIngo Molnar 482f62bae50SIngo Molnar /* 483f62bae50SIngo Molnar * In this functions we calibrate APIC bus clocks to the external timer. 484f62bae50SIngo Molnar * 485f62bae50SIngo Molnar * We want to do the calibration only once since we want to have local timer 486f62bae50SIngo Molnar * irqs syncron. CPUs connected by the same APIC bus have the very same bus 487f62bae50SIngo Molnar * frequency. 488f62bae50SIngo Molnar * 489f62bae50SIngo Molnar * This was previously done by reading the PIT/HPET and waiting for a wrap 490f62bae50SIngo Molnar * around to find out, that a tick has elapsed. I have a box, where the PIT 491f62bae50SIngo Molnar * readout is broken, so it never gets out of the wait loop again. This was 492f62bae50SIngo Molnar * also reported by others. 493f62bae50SIngo Molnar * 494f62bae50SIngo Molnar * Monitoring the jiffies value is inaccurate and the clockevents 495f62bae50SIngo Molnar * infrastructure allows us to do a simple substitution of the interrupt 496f62bae50SIngo Molnar * handler. 497f62bae50SIngo Molnar * 498f62bae50SIngo Molnar * The calibration routine also uses the pm_timer when possible, as the PIT 499f62bae50SIngo Molnar * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 500f62bae50SIngo Molnar * back to normal later in the boot process). 501f62bae50SIngo Molnar */ 502f62bae50SIngo Molnar 503f62bae50SIngo Molnar #define LAPIC_CAL_LOOPS (HZ/10) 504f62bae50SIngo Molnar 505f62bae50SIngo Molnar static __initdata int lapic_cal_loops = -1; 506f62bae50SIngo Molnar static __initdata long lapic_cal_t1, lapic_cal_t2; 507f62bae50SIngo Molnar static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 508f62bae50SIngo Molnar static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 509f62bae50SIngo Molnar static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 510f62bae50SIngo Molnar 511f62bae50SIngo Molnar /* 512f62bae50SIngo Molnar * Temporary interrupt handler. 513f62bae50SIngo Molnar */ 514f62bae50SIngo Molnar static void __init lapic_cal_handler(struct clock_event_device *dev) 515f62bae50SIngo Molnar { 516f62bae50SIngo Molnar unsigned long long tsc = 0; 517f62bae50SIngo Molnar long tapic = apic_read(APIC_TMCCT); 518f62bae50SIngo Molnar unsigned long pm = acpi_pm_read_early(); 519f62bae50SIngo Molnar 520f62bae50SIngo Molnar if (cpu_has_tsc) 521f62bae50SIngo Molnar rdtscll(tsc); 522f62bae50SIngo Molnar 523f62bae50SIngo Molnar switch (lapic_cal_loops++) { 524f62bae50SIngo Molnar case 0: 525f62bae50SIngo Molnar lapic_cal_t1 = tapic; 526f62bae50SIngo Molnar lapic_cal_tsc1 = tsc; 527f62bae50SIngo Molnar lapic_cal_pm1 = pm; 528f62bae50SIngo Molnar lapic_cal_j1 = jiffies; 529f62bae50SIngo Molnar break; 530f62bae50SIngo Molnar 531f62bae50SIngo Molnar case LAPIC_CAL_LOOPS: 532f62bae50SIngo Molnar lapic_cal_t2 = tapic; 533f62bae50SIngo Molnar lapic_cal_tsc2 = tsc; 534f62bae50SIngo Molnar if (pm < lapic_cal_pm1) 535f62bae50SIngo Molnar pm += ACPI_PM_OVRRUN; 536f62bae50SIngo Molnar lapic_cal_pm2 = pm; 537f62bae50SIngo Molnar lapic_cal_j2 = jiffies; 538f62bae50SIngo Molnar break; 539f62bae50SIngo Molnar } 540f62bae50SIngo Molnar } 541f62bae50SIngo Molnar 542f62bae50SIngo Molnar static int __init 543f62bae50SIngo Molnar calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 544f62bae50SIngo Molnar { 545f62bae50SIngo Molnar const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 546f62bae50SIngo Molnar const long pm_thresh = pm_100ms / 100; 547f62bae50SIngo Molnar unsigned long mult; 548f62bae50SIngo Molnar u64 res; 549f62bae50SIngo Molnar 550f62bae50SIngo Molnar #ifndef CONFIG_X86_PM_TIMER 551f62bae50SIngo Molnar return -1; 552f62bae50SIngo Molnar #endif 553f62bae50SIngo Molnar 554f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 555f62bae50SIngo Molnar 556f62bae50SIngo Molnar /* Check, if the PM timer is available */ 557f62bae50SIngo Molnar if (!deltapm) 558f62bae50SIngo Molnar return -1; 559f62bae50SIngo Molnar 560f62bae50SIngo Molnar mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 561f62bae50SIngo Molnar 562f62bae50SIngo Molnar if (deltapm > (pm_100ms - pm_thresh) && 563f62bae50SIngo Molnar deltapm < (pm_100ms + pm_thresh)) { 564f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 565f62bae50SIngo Molnar return 0; 566f62bae50SIngo Molnar } 567f62bae50SIngo Molnar 568f62bae50SIngo Molnar res = (((u64)deltapm) * mult) >> 22; 569f62bae50SIngo Molnar do_div(res, 1000000); 570f62bae50SIngo Molnar pr_warning("APIC calibration not consistent " 571f62bae50SIngo Molnar "with PM-Timer: %ldms instead of 100ms\n",(long)res); 572f62bae50SIngo Molnar 573f62bae50SIngo Molnar /* Correct the lapic counter value */ 574f62bae50SIngo Molnar res = (((u64)(*delta)) * pm_100ms); 575f62bae50SIngo Molnar do_div(res, deltapm); 576f62bae50SIngo Molnar pr_info("APIC delta adjusted to PM-Timer: " 577f62bae50SIngo Molnar "%lu (%ld)\n", (unsigned long)res, *delta); 578f62bae50SIngo Molnar *delta = (long)res; 579f62bae50SIngo Molnar 580f62bae50SIngo Molnar /* Correct the tsc counter value */ 581f62bae50SIngo Molnar if (cpu_has_tsc) { 582f62bae50SIngo Molnar res = (((u64)(*deltatsc)) * pm_100ms); 583f62bae50SIngo Molnar do_div(res, deltapm); 584f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 585f62bae50SIngo Molnar "PM-Timer: %lu (%ld)\n", 586f62bae50SIngo Molnar (unsigned long)res, *deltatsc); 587f62bae50SIngo Molnar *deltatsc = (long)res; 588f62bae50SIngo Molnar } 589f62bae50SIngo Molnar 590f62bae50SIngo Molnar return 0; 591f62bae50SIngo Molnar } 592f62bae50SIngo Molnar 593f62bae50SIngo Molnar static int __init calibrate_APIC_clock(void) 594f62bae50SIngo Molnar { 595f62bae50SIngo Molnar struct clock_event_device *levt = &__get_cpu_var(lapic_events); 596f62bae50SIngo Molnar void (*real_handler)(struct clock_event_device *dev); 597f62bae50SIngo Molnar unsigned long deltaj; 598f62bae50SIngo Molnar long delta, deltatsc; 599f62bae50SIngo Molnar int pm_referenced = 0; 600f62bae50SIngo Molnar 601f62bae50SIngo Molnar local_irq_disable(); 602f62bae50SIngo Molnar 603f62bae50SIngo Molnar /* Replace the global interrupt handler */ 604f62bae50SIngo Molnar real_handler = global_clock_event->event_handler; 605f62bae50SIngo Molnar global_clock_event->event_handler = lapic_cal_handler; 606f62bae50SIngo Molnar 607f62bae50SIngo Molnar /* 608f62bae50SIngo Molnar * Setup the APIC counter to maximum. There is no way the lapic 609f62bae50SIngo Molnar * can underflow in the 100ms detection time frame 610f62bae50SIngo Molnar */ 611f62bae50SIngo Molnar __setup_APIC_LVTT(0xffffffff, 0, 0); 612f62bae50SIngo Molnar 613f62bae50SIngo Molnar /* Let the interrupts run */ 614f62bae50SIngo Molnar local_irq_enable(); 615f62bae50SIngo Molnar 616f62bae50SIngo Molnar while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 617f62bae50SIngo Molnar cpu_relax(); 618f62bae50SIngo Molnar 619f62bae50SIngo Molnar local_irq_disable(); 620f62bae50SIngo Molnar 621f62bae50SIngo Molnar /* Restore the real event handler */ 622f62bae50SIngo Molnar global_clock_event->event_handler = real_handler; 623f62bae50SIngo Molnar 624f62bae50SIngo Molnar /* Build delta t1-t2 as apic timer counts down */ 625f62bae50SIngo Molnar delta = lapic_cal_t1 - lapic_cal_t2; 626f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 627f62bae50SIngo Molnar 628f62bae50SIngo Molnar deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 629f62bae50SIngo Molnar 630f62bae50SIngo Molnar /* we trust the PM based calibration if possible */ 631f62bae50SIngo Molnar pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 632f62bae50SIngo Molnar &delta, &deltatsc); 633f62bae50SIngo Molnar 634f62bae50SIngo Molnar /* Calculate the scaled math multiplication factor */ 635f62bae50SIngo Molnar lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 636f62bae50SIngo Molnar lapic_clockevent.shift); 637f62bae50SIngo Molnar lapic_clockevent.max_delta_ns = 638f62bae50SIngo Molnar clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); 639f62bae50SIngo Molnar lapic_clockevent.min_delta_ns = 640f62bae50SIngo Molnar clockevent_delta2ns(0xF, &lapic_clockevent); 641f62bae50SIngo Molnar 642f62bae50SIngo Molnar calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 643f62bae50SIngo Molnar 644f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 645411462f6SThomas Gleixner apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 646f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 647f62bae50SIngo Molnar calibration_result); 648f62bae50SIngo Molnar 649f62bae50SIngo Molnar if (cpu_has_tsc) { 650f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 651f62bae50SIngo Molnar "%ld.%04ld MHz.\n", 652f62bae50SIngo Molnar (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 653f62bae50SIngo Molnar (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 654f62bae50SIngo Molnar } 655f62bae50SIngo Molnar 656f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 657f62bae50SIngo Molnar "%u.%04u MHz.\n", 658f62bae50SIngo Molnar calibration_result / (1000000 / HZ), 659f62bae50SIngo Molnar calibration_result % (1000000 / HZ)); 660f62bae50SIngo Molnar 661f62bae50SIngo Molnar /* 662f62bae50SIngo Molnar * Do a sanity check on the APIC calibration result 663f62bae50SIngo Molnar */ 664f62bae50SIngo Molnar if (calibration_result < (1000000 / HZ)) { 665f62bae50SIngo Molnar local_irq_enable(); 666f62bae50SIngo Molnar pr_warning("APIC frequency too slow, disabling apic timer\n"); 667f62bae50SIngo Molnar return -1; 668f62bae50SIngo Molnar } 669f62bae50SIngo Molnar 670f62bae50SIngo Molnar levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 671f62bae50SIngo Molnar 672f62bae50SIngo Molnar /* 673f62bae50SIngo Molnar * PM timer calibration failed or not turned on 674f62bae50SIngo Molnar * so lets try APIC timer based calibration 675f62bae50SIngo Molnar */ 676f62bae50SIngo Molnar if (!pm_referenced) { 677f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 678f62bae50SIngo Molnar 679f62bae50SIngo Molnar /* 680f62bae50SIngo Molnar * Setup the apic timer manually 681f62bae50SIngo Molnar */ 682f62bae50SIngo Molnar levt->event_handler = lapic_cal_handler; 683f62bae50SIngo Molnar lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); 684f62bae50SIngo Molnar lapic_cal_loops = -1; 685f62bae50SIngo Molnar 686f62bae50SIngo Molnar /* Let the interrupts run */ 687f62bae50SIngo Molnar local_irq_enable(); 688f62bae50SIngo Molnar 689f62bae50SIngo Molnar while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 690f62bae50SIngo Molnar cpu_relax(); 691f62bae50SIngo Molnar 692f62bae50SIngo Molnar /* Stop the lapic timer */ 693f62bae50SIngo Molnar lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); 694f62bae50SIngo Molnar 695f62bae50SIngo Molnar /* Jiffies delta */ 696f62bae50SIngo Molnar deltaj = lapic_cal_j2 - lapic_cal_j1; 697f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 698f62bae50SIngo Molnar 699f62bae50SIngo Molnar /* Check, if the jiffies result is consistent */ 700f62bae50SIngo Molnar if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 701f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 702f62bae50SIngo Molnar else 703f62bae50SIngo Molnar levt->features |= CLOCK_EVT_FEAT_DUMMY; 704f62bae50SIngo Molnar } else 705f62bae50SIngo Molnar local_irq_enable(); 706f62bae50SIngo Molnar 707f62bae50SIngo Molnar if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 708f62bae50SIngo Molnar pr_warning("APIC timer disabled due to verification failure\n"); 709f62bae50SIngo Molnar return -1; 710f62bae50SIngo Molnar } 711f62bae50SIngo Molnar 712f62bae50SIngo Molnar return 0; 713f62bae50SIngo Molnar } 714f62bae50SIngo Molnar 715f62bae50SIngo Molnar /* 716f62bae50SIngo Molnar * Setup the boot APIC 717f62bae50SIngo Molnar * 718f62bae50SIngo Molnar * Calibrate and verify the result. 719f62bae50SIngo Molnar */ 720f62bae50SIngo Molnar void __init setup_boot_APIC_clock(void) 721f62bae50SIngo Molnar { 722f62bae50SIngo Molnar /* 723f62bae50SIngo Molnar * The local apic timer can be disabled via the kernel 724f62bae50SIngo Molnar * commandline or from the CPU detection code. Register the lapic 725f62bae50SIngo Molnar * timer as a dummy clock event source on SMP systems, so the 726f62bae50SIngo Molnar * broadcast mechanism is used. On UP systems simply ignore it. 727f62bae50SIngo Molnar */ 728f62bae50SIngo Molnar if (disable_apic_timer) { 729f62bae50SIngo Molnar pr_info("Disabling APIC timer\n"); 730f62bae50SIngo Molnar /* No broadcast on UP ! */ 731f62bae50SIngo Molnar if (num_possible_cpus() > 1) { 732f62bae50SIngo Molnar lapic_clockevent.mult = 1; 733f62bae50SIngo Molnar setup_APIC_timer(); 734f62bae50SIngo Molnar } 735f62bae50SIngo Molnar return; 736f62bae50SIngo Molnar } 737f62bae50SIngo Molnar 738f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 739f62bae50SIngo Molnar "calibrating APIC timer ...\n"); 740f62bae50SIngo Molnar 741f62bae50SIngo Molnar if (calibrate_APIC_clock()) { 742f62bae50SIngo Molnar /* No broadcast on UP ! */ 743f62bae50SIngo Molnar if (num_possible_cpus() > 1) 744f62bae50SIngo Molnar setup_APIC_timer(); 745f62bae50SIngo Molnar return; 746f62bae50SIngo Molnar } 747f62bae50SIngo Molnar 748f62bae50SIngo Molnar /* 749f62bae50SIngo Molnar * If nmi_watchdog is set to IO_APIC, we need the 750f62bae50SIngo Molnar * PIT/HPET going. Otherwise register lapic as a dummy 751f62bae50SIngo Molnar * device. 752f62bae50SIngo Molnar */ 753f62bae50SIngo Molnar if (nmi_watchdog != NMI_IO_APIC) 754f62bae50SIngo Molnar lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 755f62bae50SIngo Molnar else 756f62bae50SIngo Molnar pr_warning("APIC timer registered as dummy," 757f62bae50SIngo Molnar " due to nmi_watchdog=%d!\n", nmi_watchdog); 758f62bae50SIngo Molnar 759f62bae50SIngo Molnar /* Setup the lapic or request the broadcast */ 760f62bae50SIngo Molnar setup_APIC_timer(); 761f62bae50SIngo Molnar } 762f62bae50SIngo Molnar 763f62bae50SIngo Molnar void __cpuinit setup_secondary_APIC_clock(void) 764f62bae50SIngo Molnar { 765f62bae50SIngo Molnar setup_APIC_timer(); 766f62bae50SIngo Molnar } 767f62bae50SIngo Molnar 768f62bae50SIngo Molnar /* 769f62bae50SIngo Molnar * The guts of the apic timer interrupt 770f62bae50SIngo Molnar */ 771f62bae50SIngo Molnar static void local_apic_timer_interrupt(void) 772f62bae50SIngo Molnar { 773f62bae50SIngo Molnar int cpu = smp_processor_id(); 774f62bae50SIngo Molnar struct clock_event_device *evt = &per_cpu(lapic_events, cpu); 775f62bae50SIngo Molnar 776f62bae50SIngo Molnar /* 777f62bae50SIngo Molnar * Normally we should not be here till LAPIC has been initialized but 778f62bae50SIngo Molnar * in some cases like kdump, its possible that there is a pending LAPIC 779f62bae50SIngo Molnar * timer interrupt from previous kernel's context and is delivered in 780f62bae50SIngo Molnar * new kernel the moment interrupts are enabled. 781f62bae50SIngo Molnar * 782f62bae50SIngo Molnar * Interrupts are enabled early and LAPIC is setup much later, hence 783f62bae50SIngo Molnar * its possible that when we get here evt->event_handler is NULL. 784f62bae50SIngo Molnar * Check for event_handler being NULL and discard the interrupt as 785f62bae50SIngo Molnar * spurious. 786f62bae50SIngo Molnar */ 787f62bae50SIngo Molnar if (!evt->event_handler) { 788f62bae50SIngo Molnar pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); 789f62bae50SIngo Molnar /* Switch it off */ 790f62bae50SIngo Molnar lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); 791f62bae50SIngo Molnar return; 792f62bae50SIngo Molnar } 793f62bae50SIngo Molnar 794f62bae50SIngo Molnar /* 795f62bae50SIngo Molnar * the NMI deadlock-detector uses this. 796f62bae50SIngo Molnar */ 797f62bae50SIngo Molnar inc_irq_stat(apic_timer_irqs); 798f62bae50SIngo Molnar 799f62bae50SIngo Molnar evt->event_handler(evt); 800f62bae50SIngo Molnar } 801f62bae50SIngo Molnar 802f62bae50SIngo Molnar /* 803f62bae50SIngo Molnar * Local APIC timer interrupt. This is the most natural way for doing 804f62bae50SIngo Molnar * local interrupts, but local timer interrupts can be emulated by 805f62bae50SIngo Molnar * broadcast interrupts too. [in case the hw doesn't support APIC timers] 806f62bae50SIngo Molnar * 807f62bae50SIngo Molnar * [ if a single-CPU system runs an SMP kernel then we call the local 808f62bae50SIngo Molnar * interrupt as well. Thus we cannot inline the local irq ... ] 809f62bae50SIngo Molnar */ 810f62bae50SIngo Molnar void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 811f62bae50SIngo Molnar { 812f62bae50SIngo Molnar struct pt_regs *old_regs = set_irq_regs(regs); 813f62bae50SIngo Molnar 814f62bae50SIngo Molnar /* 815f62bae50SIngo Molnar * NOTE! We'd better ACK the irq immediately, 816f62bae50SIngo Molnar * because timer handling can be slow. 817f62bae50SIngo Molnar */ 818f62bae50SIngo Molnar ack_APIC_irq(); 819f62bae50SIngo Molnar /* 820f62bae50SIngo Molnar * update_process_times() expects us to have done irq_enter(). 821f62bae50SIngo Molnar * Besides, if we don't timer interrupts ignore the global 822f62bae50SIngo Molnar * interrupt lock, which is the WrongThing (tm) to do. 823f62bae50SIngo Molnar */ 824f62bae50SIngo Molnar exit_idle(); 825f62bae50SIngo Molnar irq_enter(); 826f62bae50SIngo Molnar local_apic_timer_interrupt(); 827f62bae50SIngo Molnar irq_exit(); 828f62bae50SIngo Molnar 829f62bae50SIngo Molnar set_irq_regs(old_regs); 830f62bae50SIngo Molnar } 831f62bae50SIngo Molnar 832f62bae50SIngo Molnar int setup_profiling_timer(unsigned int multiplier) 833f62bae50SIngo Molnar { 834f62bae50SIngo Molnar return -EINVAL; 835f62bae50SIngo Molnar } 836f62bae50SIngo Molnar 837f62bae50SIngo Molnar /* 838f62bae50SIngo Molnar * Local APIC start and shutdown 839f62bae50SIngo Molnar */ 840f62bae50SIngo Molnar 841f62bae50SIngo Molnar /** 842f62bae50SIngo Molnar * clear_local_APIC - shutdown the local APIC 843f62bae50SIngo Molnar * 844f62bae50SIngo Molnar * This is called, when a CPU is disabled and before rebooting, so the state of 845f62bae50SIngo Molnar * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 846f62bae50SIngo Molnar * leftovers during boot. 847f62bae50SIngo Molnar */ 848f62bae50SIngo Molnar void clear_local_APIC(void) 849f62bae50SIngo Molnar { 850f62bae50SIngo Molnar int maxlvt; 851f62bae50SIngo Molnar u32 v; 852f62bae50SIngo Molnar 853f62bae50SIngo Molnar /* APIC hasn't been mapped yet */ 854fc1edaf9SSuresh Siddha if (!x2apic_mode && !apic_phys) 855f62bae50SIngo Molnar return; 856f62bae50SIngo Molnar 857f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 858f62bae50SIngo Molnar /* 859f62bae50SIngo Molnar * Masking an LVT entry can trigger a local APIC error 860f62bae50SIngo Molnar * if the vector is zero. Mask LVTERR first to prevent this. 861f62bae50SIngo Molnar */ 862f62bae50SIngo Molnar if (maxlvt >= 3) { 863f62bae50SIngo Molnar v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 864f62bae50SIngo Molnar apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 865f62bae50SIngo Molnar } 866f62bae50SIngo Molnar /* 867f62bae50SIngo Molnar * Careful: we have to set masks only first to deassert 868f62bae50SIngo Molnar * any level-triggered sources. 869f62bae50SIngo Molnar */ 870f62bae50SIngo Molnar v = apic_read(APIC_LVTT); 871f62bae50SIngo Molnar apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 872f62bae50SIngo Molnar v = apic_read(APIC_LVT0); 873f62bae50SIngo Molnar apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 874f62bae50SIngo Molnar v = apic_read(APIC_LVT1); 875f62bae50SIngo Molnar apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 876f62bae50SIngo Molnar if (maxlvt >= 4) { 877f62bae50SIngo Molnar v = apic_read(APIC_LVTPC); 878f62bae50SIngo Molnar apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 879f62bae50SIngo Molnar } 880f62bae50SIngo Molnar 881f62bae50SIngo Molnar /* lets not touch this if we didn't frob it */ 8824efc0670SAndi Kleen #ifdef CONFIG_X86_THERMAL_VECTOR 883f62bae50SIngo Molnar if (maxlvt >= 5) { 884f62bae50SIngo Molnar v = apic_read(APIC_LVTTHMR); 885f62bae50SIngo Molnar apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 886f62bae50SIngo Molnar } 887f62bae50SIngo Molnar #endif 888638bee71SH. Peter Anvin #ifdef CONFIG_X86_MCE_INTEL 889638bee71SH. Peter Anvin if (maxlvt >= 6) { 890638bee71SH. Peter Anvin v = apic_read(APIC_LVTCMCI); 891638bee71SH. Peter Anvin if (!(v & APIC_LVT_MASKED)) 892638bee71SH. Peter Anvin apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 893638bee71SH. Peter Anvin } 894638bee71SH. Peter Anvin #endif 895638bee71SH. Peter Anvin 896f62bae50SIngo Molnar /* 897f62bae50SIngo Molnar * Clean APIC state for other OSs: 898f62bae50SIngo Molnar */ 899f62bae50SIngo Molnar apic_write(APIC_LVTT, APIC_LVT_MASKED); 900f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_LVT_MASKED); 901f62bae50SIngo Molnar apic_write(APIC_LVT1, APIC_LVT_MASKED); 902f62bae50SIngo Molnar if (maxlvt >= 3) 903f62bae50SIngo Molnar apic_write(APIC_LVTERR, APIC_LVT_MASKED); 904f62bae50SIngo Molnar if (maxlvt >= 4) 905f62bae50SIngo Molnar apic_write(APIC_LVTPC, APIC_LVT_MASKED); 906f62bae50SIngo Molnar 907f62bae50SIngo Molnar /* Integrated APIC (!82489DX) ? */ 908f62bae50SIngo Molnar if (lapic_is_integrated()) { 909f62bae50SIngo Molnar if (maxlvt > 3) 910f62bae50SIngo Molnar /* Clear ESR due to Pentium errata 3AP and 11AP */ 911f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 912f62bae50SIngo Molnar apic_read(APIC_ESR); 913f62bae50SIngo Molnar } 914f62bae50SIngo Molnar } 915f62bae50SIngo Molnar 916f62bae50SIngo Molnar /** 917f62bae50SIngo Molnar * disable_local_APIC - clear and disable the local APIC 918f62bae50SIngo Molnar */ 919f62bae50SIngo Molnar void disable_local_APIC(void) 920f62bae50SIngo Molnar { 921f62bae50SIngo Molnar unsigned int value; 922f62bae50SIngo Molnar 923f62bae50SIngo Molnar /* APIC hasn't been mapped yet */ 924fd19dce7SYinghai Lu if (!x2apic_mode && !apic_phys) 925f62bae50SIngo Molnar return; 926f62bae50SIngo Molnar 927f62bae50SIngo Molnar clear_local_APIC(); 928f62bae50SIngo Molnar 929f62bae50SIngo Molnar /* 930f62bae50SIngo Molnar * Disable APIC (implies clearing of registers 931f62bae50SIngo Molnar * for 82489DX!). 932f62bae50SIngo Molnar */ 933f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 934f62bae50SIngo Molnar value &= ~APIC_SPIV_APIC_ENABLED; 935f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 936f62bae50SIngo Molnar 937f62bae50SIngo Molnar #ifdef CONFIG_X86_32 938f62bae50SIngo Molnar /* 939f62bae50SIngo Molnar * When LAPIC was disabled by the BIOS and enabled by the kernel, 940f62bae50SIngo Molnar * restore the disabled state. 941f62bae50SIngo Molnar */ 942f62bae50SIngo Molnar if (enabled_via_apicbase) { 943f62bae50SIngo Molnar unsigned int l, h; 944f62bae50SIngo Molnar 945f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, l, h); 946f62bae50SIngo Molnar l &= ~MSR_IA32_APICBASE_ENABLE; 947f62bae50SIngo Molnar wrmsr(MSR_IA32_APICBASE, l, h); 948f62bae50SIngo Molnar } 949f62bae50SIngo Molnar #endif 950f62bae50SIngo Molnar } 951f62bae50SIngo Molnar 952f62bae50SIngo Molnar /* 953f62bae50SIngo Molnar * If Linux enabled the LAPIC against the BIOS default disable it down before 954f62bae50SIngo Molnar * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 955f62bae50SIngo Molnar * not power-off. Additionally clear all LVT entries before disable_local_APIC 956f62bae50SIngo Molnar * for the case where Linux didn't enable the LAPIC. 957f62bae50SIngo Molnar */ 958f62bae50SIngo Molnar void lapic_shutdown(void) 959f62bae50SIngo Molnar { 960f62bae50SIngo Molnar unsigned long flags; 961f62bae50SIngo Molnar 9628312136fSCyrill Gorcunov if (!cpu_has_apic && !apic_from_smp_config()) 963f62bae50SIngo Molnar return; 964f62bae50SIngo Molnar 965f62bae50SIngo Molnar local_irq_save(flags); 966f62bae50SIngo Molnar 967f62bae50SIngo Molnar #ifdef CONFIG_X86_32 968f62bae50SIngo Molnar if (!enabled_via_apicbase) 969f62bae50SIngo Molnar clear_local_APIC(); 970f62bae50SIngo Molnar else 971f62bae50SIngo Molnar #endif 972f62bae50SIngo Molnar disable_local_APIC(); 973f62bae50SIngo Molnar 974f62bae50SIngo Molnar 975f62bae50SIngo Molnar local_irq_restore(flags); 976f62bae50SIngo Molnar } 977f62bae50SIngo Molnar 978f62bae50SIngo Molnar /* 979f62bae50SIngo Molnar * This is to verify that we're looking at a real local APIC. 980f62bae50SIngo Molnar * Check these against your board if the CPUs aren't getting 981f62bae50SIngo Molnar * started for no apparent reason. 982f62bae50SIngo Molnar */ 983f62bae50SIngo Molnar int __init verify_local_APIC(void) 984f62bae50SIngo Molnar { 985f62bae50SIngo Molnar unsigned int reg0, reg1; 986f62bae50SIngo Molnar 987f62bae50SIngo Molnar /* 988f62bae50SIngo Molnar * The version register is read-only in a real APIC. 989f62bae50SIngo Molnar */ 990f62bae50SIngo Molnar reg0 = apic_read(APIC_LVR); 991f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); 992f62bae50SIngo Molnar apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); 993f62bae50SIngo Molnar reg1 = apic_read(APIC_LVR); 994f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); 995f62bae50SIngo Molnar 996f62bae50SIngo Molnar /* 997f62bae50SIngo Molnar * The two version reads above should print the same 998f62bae50SIngo Molnar * numbers. If the second one is different, then we 999f62bae50SIngo Molnar * poke at a non-APIC. 1000f62bae50SIngo Molnar */ 1001f62bae50SIngo Molnar if (reg1 != reg0) 1002f62bae50SIngo Molnar return 0; 1003f62bae50SIngo Molnar 1004f62bae50SIngo Molnar /* 1005f62bae50SIngo Molnar * Check if the version looks reasonably. 1006f62bae50SIngo Molnar */ 1007f62bae50SIngo Molnar reg1 = GET_APIC_VERSION(reg0); 1008f62bae50SIngo Molnar if (reg1 == 0x00 || reg1 == 0xff) 1009f62bae50SIngo Molnar return 0; 1010f62bae50SIngo Molnar reg1 = lapic_get_maxlvt(); 1011f62bae50SIngo Molnar if (reg1 < 0x02 || reg1 == 0xff) 1012f62bae50SIngo Molnar return 0; 1013f62bae50SIngo Molnar 1014f62bae50SIngo Molnar /* 1015f62bae50SIngo Molnar * The ID register is read/write in a real APIC. 1016f62bae50SIngo Molnar */ 1017f62bae50SIngo Molnar reg0 = apic_read(APIC_ID); 1018f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); 1019f62bae50SIngo Molnar apic_write(APIC_ID, reg0 ^ apic->apic_id_mask); 1020f62bae50SIngo Molnar reg1 = apic_read(APIC_ID); 1021f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); 1022f62bae50SIngo Molnar apic_write(APIC_ID, reg0); 1023f62bae50SIngo Molnar if (reg1 != (reg0 ^ apic->apic_id_mask)) 1024f62bae50SIngo Molnar return 0; 1025f62bae50SIngo Molnar 1026f62bae50SIngo Molnar /* 1027f62bae50SIngo Molnar * The next two are just to see if we have sane values. 1028f62bae50SIngo Molnar * They're only really relevant if we're in Virtual Wire 1029f62bae50SIngo Molnar * compatibility mode, but most boxes are anymore. 1030f62bae50SIngo Molnar */ 1031f62bae50SIngo Molnar reg0 = apic_read(APIC_LVT0); 1032f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); 1033f62bae50SIngo Molnar reg1 = apic_read(APIC_LVT1); 1034f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); 1035f62bae50SIngo Molnar 1036f62bae50SIngo Molnar return 1; 1037f62bae50SIngo Molnar } 1038f62bae50SIngo Molnar 1039f62bae50SIngo Molnar /** 1040f62bae50SIngo Molnar * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1041f62bae50SIngo Molnar */ 1042f62bae50SIngo Molnar void __init sync_Arb_IDs(void) 1043f62bae50SIngo Molnar { 1044f62bae50SIngo Molnar /* 1045f62bae50SIngo Molnar * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1046f62bae50SIngo Molnar * needed on AMD. 1047f62bae50SIngo Molnar */ 1048f62bae50SIngo Molnar if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1049f62bae50SIngo Molnar return; 1050f62bae50SIngo Molnar 1051f62bae50SIngo Molnar /* 1052f62bae50SIngo Molnar * Wait for idle. 1053f62bae50SIngo Molnar */ 1054f62bae50SIngo Molnar apic_wait_icr_idle(); 1055f62bae50SIngo Molnar 1056f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1057f62bae50SIngo Molnar apic_write(APIC_ICR, APIC_DEST_ALLINC | 1058f62bae50SIngo Molnar APIC_INT_LEVELTRIG | APIC_DM_INIT); 1059f62bae50SIngo Molnar } 1060f62bae50SIngo Molnar 1061f62bae50SIngo Molnar /* 1062f62bae50SIngo Molnar * An initial setup of the virtual wire mode. 1063f62bae50SIngo Molnar */ 1064f62bae50SIngo Molnar void __init init_bsp_APIC(void) 1065f62bae50SIngo Molnar { 1066f62bae50SIngo Molnar unsigned int value; 1067f62bae50SIngo Molnar 1068f62bae50SIngo Molnar /* 1069f62bae50SIngo Molnar * Don't do the setup now if we have a SMP BIOS as the 1070f62bae50SIngo Molnar * through-I/O-APIC virtual wire mode might be active. 1071f62bae50SIngo Molnar */ 1072f62bae50SIngo Molnar if (smp_found_config || !cpu_has_apic) 1073f62bae50SIngo Molnar return; 1074f62bae50SIngo Molnar 1075f62bae50SIngo Molnar /* 1076f62bae50SIngo Molnar * Do not trust the local APIC being empty at bootup. 1077f62bae50SIngo Molnar */ 1078f62bae50SIngo Molnar clear_local_APIC(); 1079f62bae50SIngo Molnar 1080f62bae50SIngo Molnar /* 1081f62bae50SIngo Molnar * Enable APIC. 1082f62bae50SIngo Molnar */ 1083f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 1084f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 1085f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 1086f62bae50SIngo Molnar 1087f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1088f62bae50SIngo Molnar /* This bit is reserved on P4/Xeon and should be cleared */ 1089f62bae50SIngo Molnar if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1090f62bae50SIngo Molnar (boot_cpu_data.x86 == 15)) 1091f62bae50SIngo Molnar value &= ~APIC_SPIV_FOCUS_DISABLED; 1092f62bae50SIngo Molnar else 1093f62bae50SIngo Molnar #endif 1094f62bae50SIngo Molnar value |= APIC_SPIV_FOCUS_DISABLED; 1095f62bae50SIngo Molnar value |= SPURIOUS_APIC_VECTOR; 1096f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 1097f62bae50SIngo Molnar 1098f62bae50SIngo Molnar /* 1099f62bae50SIngo Molnar * Set up the virtual wire mode. 1100f62bae50SIngo Molnar */ 1101f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_DM_EXTINT); 1102f62bae50SIngo Molnar value = APIC_DM_NMI; 1103f62bae50SIngo Molnar if (!lapic_is_integrated()) /* 82489DX */ 1104f62bae50SIngo Molnar value |= APIC_LVT_LEVEL_TRIGGER; 1105f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 1106f62bae50SIngo Molnar } 1107f62bae50SIngo Molnar 1108f62bae50SIngo Molnar static void __cpuinit lapic_setup_esr(void) 1109f62bae50SIngo Molnar { 1110f62bae50SIngo Molnar unsigned int oldvalue, value, maxlvt; 1111f62bae50SIngo Molnar 1112f62bae50SIngo Molnar if (!lapic_is_integrated()) { 1113f62bae50SIngo Molnar pr_info("No ESR for 82489DX.\n"); 1114f62bae50SIngo Molnar return; 1115f62bae50SIngo Molnar } 1116f62bae50SIngo Molnar 1117f62bae50SIngo Molnar if (apic->disable_esr) { 1118f62bae50SIngo Molnar /* 1119f62bae50SIngo Molnar * Something untraceable is creating bad interrupts on 1120f62bae50SIngo Molnar * secondary quads ... for the moment, just leave the 1121f62bae50SIngo Molnar * ESR disabled - we can't do anything useful with the 1122f62bae50SIngo Molnar * errors anyway - mbligh 1123f62bae50SIngo Molnar */ 1124f62bae50SIngo Molnar pr_info("Leaving ESR disabled.\n"); 1125f62bae50SIngo Molnar return; 1126f62bae50SIngo Molnar } 1127f62bae50SIngo Molnar 1128f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 1129f62bae50SIngo Molnar if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1130f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1131f62bae50SIngo Molnar oldvalue = apic_read(APIC_ESR); 1132f62bae50SIngo Molnar 1133f62bae50SIngo Molnar /* enables sending errors */ 1134f62bae50SIngo Molnar value = ERROR_APIC_VECTOR; 1135f62bae50SIngo Molnar apic_write(APIC_LVTERR, value); 1136f62bae50SIngo Molnar 1137f62bae50SIngo Molnar /* 1138f62bae50SIngo Molnar * spec says clear errors after enabling vector. 1139f62bae50SIngo Molnar */ 1140f62bae50SIngo Molnar if (maxlvt > 3) 1141f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1142f62bae50SIngo Molnar value = apic_read(APIC_ESR); 1143f62bae50SIngo Molnar if (value != oldvalue) 1144f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "ESR value before enabling " 1145f62bae50SIngo Molnar "vector: 0x%08x after: 0x%08x\n", 1146f62bae50SIngo Molnar oldvalue, value); 1147f62bae50SIngo Molnar } 1148f62bae50SIngo Molnar 1149f62bae50SIngo Molnar 1150f62bae50SIngo Molnar /** 1151f62bae50SIngo Molnar * setup_local_APIC - setup the local APIC 1152f62bae50SIngo Molnar */ 1153f62bae50SIngo Molnar void __cpuinit setup_local_APIC(void) 1154f62bae50SIngo Molnar { 11558c3ba8d0SKerstin Jonsson unsigned int value, queued; 11568c3ba8d0SKerstin Jonsson int i, j, acked = 0; 11578c3ba8d0SKerstin Jonsson unsigned long long tsc = 0, ntsc; 11588c3ba8d0SKerstin Jonsson long long max_loops = cpu_khz; 11598c3ba8d0SKerstin Jonsson 11608c3ba8d0SKerstin Jonsson if (cpu_has_tsc) 11618c3ba8d0SKerstin Jonsson rdtscll(tsc); 1162f62bae50SIngo Molnar 1163f62bae50SIngo Molnar if (disable_apic) { 1164f62bae50SIngo Molnar arch_disable_smp_support(); 1165f62bae50SIngo Molnar return; 1166f62bae50SIngo Molnar } 1167f62bae50SIngo Molnar 1168f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1169f62bae50SIngo Molnar /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1170f62bae50SIngo Molnar if (lapic_is_integrated() && apic->disable_esr) { 1171f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1172f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1173f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1174f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1175f62bae50SIngo Molnar } 1176f62bae50SIngo Molnar #endif 1177cdd6c482SIngo Molnar perf_events_lapic_init(); 1178f62bae50SIngo Molnar 1179f62bae50SIngo Molnar preempt_disable(); 1180f62bae50SIngo Molnar 1181f62bae50SIngo Molnar /* 1182f62bae50SIngo Molnar * Double-check whether this APIC is really registered. 1183f62bae50SIngo Molnar * This is meaningless in clustered apic mode, so we skip it. 1184f62bae50SIngo Molnar */ 1185c2777f98SDaniel Walker BUG_ON(!apic->apic_id_registered()); 1186f62bae50SIngo Molnar 1187f62bae50SIngo Molnar /* 1188f62bae50SIngo Molnar * Intel recommends to set DFR, LDR and TPR before enabling 1189f62bae50SIngo Molnar * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1190f62bae50SIngo Molnar * document number 292116). So here it goes... 1191f62bae50SIngo Molnar */ 1192f62bae50SIngo Molnar apic->init_apic_ldr(); 1193f62bae50SIngo Molnar 1194f62bae50SIngo Molnar /* 1195f62bae50SIngo Molnar * Set Task Priority to 'accept all'. We never change this 1196f62bae50SIngo Molnar * later on. 1197f62bae50SIngo Molnar */ 1198f62bae50SIngo Molnar value = apic_read(APIC_TASKPRI); 1199f62bae50SIngo Molnar value &= ~APIC_TPRI_MASK; 1200f62bae50SIngo Molnar apic_write(APIC_TASKPRI, value); 1201f62bae50SIngo Molnar 1202f62bae50SIngo Molnar /* 1203f62bae50SIngo Molnar * After a crash, we no longer service the interrupts and a pending 1204f62bae50SIngo Molnar * interrupt from previous kernel might still have ISR bit set. 1205f62bae50SIngo Molnar * 1206f62bae50SIngo Molnar * Most probably by now CPU has serviced that pending interrupt and 1207f62bae50SIngo Molnar * it might not have done the ack_APIC_irq() because it thought, 1208f62bae50SIngo Molnar * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1209f62bae50SIngo Molnar * does not clear the ISR bit and cpu thinks it has already serivced 1210f62bae50SIngo Molnar * the interrupt. Hence a vector might get locked. It was noticed 1211f62bae50SIngo Molnar * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1212f62bae50SIngo Molnar */ 12138c3ba8d0SKerstin Jonsson do { 12148c3ba8d0SKerstin Jonsson queued = 0; 12158c3ba8d0SKerstin Jonsson for (i = APIC_ISR_NR - 1; i >= 0; i--) 12168c3ba8d0SKerstin Jonsson queued |= apic_read(APIC_IRR + i*0x10); 12178c3ba8d0SKerstin Jonsson 1218f62bae50SIngo Molnar for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1219f62bae50SIngo Molnar value = apic_read(APIC_ISR + i*0x10); 1220f62bae50SIngo Molnar for (j = 31; j >= 0; j--) { 12218c3ba8d0SKerstin Jonsson if (value & (1<<j)) { 1222f62bae50SIngo Molnar ack_APIC_irq(); 12238c3ba8d0SKerstin Jonsson acked++; 1224f62bae50SIngo Molnar } 1225f62bae50SIngo Molnar } 12268c3ba8d0SKerstin Jonsson } 12278c3ba8d0SKerstin Jonsson if (acked > 256) { 12288c3ba8d0SKerstin Jonsson printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", 12298c3ba8d0SKerstin Jonsson acked); 12308c3ba8d0SKerstin Jonsson break; 12318c3ba8d0SKerstin Jonsson } 12328c3ba8d0SKerstin Jonsson if (cpu_has_tsc) { 12338c3ba8d0SKerstin Jonsson rdtscll(ntsc); 12348c3ba8d0SKerstin Jonsson max_loops = (cpu_khz << 10) - (ntsc - tsc); 12358c3ba8d0SKerstin Jonsson } else 12368c3ba8d0SKerstin Jonsson max_loops--; 12378c3ba8d0SKerstin Jonsson } while (queued && max_loops > 0); 12388c3ba8d0SKerstin Jonsson WARN_ON(max_loops <= 0); 1239f62bae50SIngo Molnar 1240f62bae50SIngo Molnar /* 1241f62bae50SIngo Molnar * Now that we are all set up, enable the APIC 1242f62bae50SIngo Molnar */ 1243f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 1244f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 1245f62bae50SIngo Molnar /* 1246f62bae50SIngo Molnar * Enable APIC 1247f62bae50SIngo Molnar */ 1248f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 1249f62bae50SIngo Molnar 1250f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1251f62bae50SIngo Molnar /* 1252f62bae50SIngo Molnar * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1253f62bae50SIngo Molnar * certain networking cards. If high frequency interrupts are 1254f62bae50SIngo Molnar * happening on a particular IOAPIC pin, plus the IOAPIC routing 1255f62bae50SIngo Molnar * entry is masked/unmasked at a high rate as well then sooner or 1256f62bae50SIngo Molnar * later IOAPIC line gets 'stuck', no more interrupts are received 1257f62bae50SIngo Molnar * from the device. If focus CPU is disabled then the hang goes 1258f62bae50SIngo Molnar * away, oh well :-( 1259f62bae50SIngo Molnar * 1260f62bae50SIngo Molnar * [ This bug can be reproduced easily with a level-triggered 1261f62bae50SIngo Molnar * PCI Ne2000 networking cards and PII/PIII processors, dual 1262f62bae50SIngo Molnar * BX chipset. ] 1263f62bae50SIngo Molnar */ 1264f62bae50SIngo Molnar /* 1265f62bae50SIngo Molnar * Actually disabling the focus CPU check just makes the hang less 1266f62bae50SIngo Molnar * frequent as it makes the interrupt distributon model be more 1267f62bae50SIngo Molnar * like LRU than MRU (the short-term load is more even across CPUs). 1268f62bae50SIngo Molnar * See also the comment in end_level_ioapic_irq(). --macro 1269f62bae50SIngo Molnar */ 1270f62bae50SIngo Molnar 1271f62bae50SIngo Molnar /* 1272f62bae50SIngo Molnar * - enable focus processor (bit==0) 1273f62bae50SIngo Molnar * - 64bit mode always use processor focus 1274f62bae50SIngo Molnar * so no need to set it 1275f62bae50SIngo Molnar */ 1276f62bae50SIngo Molnar value &= ~APIC_SPIV_FOCUS_DISABLED; 1277f62bae50SIngo Molnar #endif 1278f62bae50SIngo Molnar 1279f62bae50SIngo Molnar /* 1280f62bae50SIngo Molnar * Set spurious IRQ vector 1281f62bae50SIngo Molnar */ 1282f62bae50SIngo Molnar value |= SPURIOUS_APIC_VECTOR; 1283f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 1284f62bae50SIngo Molnar 1285f62bae50SIngo Molnar /* 1286f62bae50SIngo Molnar * Set up LVT0, LVT1: 1287f62bae50SIngo Molnar * 1288f62bae50SIngo Molnar * set up through-local-APIC on the BP's LINT0. This is not 1289f62bae50SIngo Molnar * strictly necessary in pure symmetric-IO mode, but sometimes 1290f62bae50SIngo Molnar * we delegate interrupts to the 8259A. 1291f62bae50SIngo Molnar */ 1292f62bae50SIngo Molnar /* 1293f62bae50SIngo Molnar * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1294f62bae50SIngo Molnar */ 1295f62bae50SIngo Molnar value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1296f62bae50SIngo Molnar if (!smp_processor_id() && (pic_mode || !value)) { 1297f62bae50SIngo Molnar value = APIC_DM_EXTINT; 1298f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", 1299f62bae50SIngo Molnar smp_processor_id()); 1300f62bae50SIngo Molnar } else { 1301f62bae50SIngo Molnar value = APIC_DM_EXTINT | APIC_LVT_MASKED; 1302f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", 1303f62bae50SIngo Molnar smp_processor_id()); 1304f62bae50SIngo Molnar } 1305f62bae50SIngo Molnar apic_write(APIC_LVT0, value); 1306f62bae50SIngo Molnar 1307f62bae50SIngo Molnar /* 1308f62bae50SIngo Molnar * only the BP should see the LINT1 NMI signal, obviously. 1309f62bae50SIngo Molnar */ 1310f62bae50SIngo Molnar if (!smp_processor_id()) 1311f62bae50SIngo Molnar value = APIC_DM_NMI; 1312f62bae50SIngo Molnar else 1313f62bae50SIngo Molnar value = APIC_DM_NMI | APIC_LVT_MASKED; 1314f62bae50SIngo Molnar if (!lapic_is_integrated()) /* 82489DX */ 1315f62bae50SIngo Molnar value |= APIC_LVT_LEVEL_TRIGGER; 1316f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 1317f62bae50SIngo Molnar 1318f62bae50SIngo Molnar preempt_enable(); 1319638bee71SH. Peter Anvin 1320638bee71SH. Peter Anvin #ifdef CONFIG_X86_MCE_INTEL 1321638bee71SH. Peter Anvin /* Recheck CMCI information after local APIC is up on CPU #0 */ 1322638bee71SH. Peter Anvin if (smp_processor_id() == 0) 1323638bee71SH. Peter Anvin cmci_recheck(); 1324638bee71SH. Peter Anvin #endif 1325f62bae50SIngo Molnar } 1326f62bae50SIngo Molnar 1327f62bae50SIngo Molnar void __cpuinit end_local_APIC_setup(void) 1328f62bae50SIngo Molnar { 1329f62bae50SIngo Molnar lapic_setup_esr(); 1330f62bae50SIngo Molnar 1331f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1332f62bae50SIngo Molnar { 1333f62bae50SIngo Molnar unsigned int value; 1334f62bae50SIngo Molnar /* Disable the local apic timer */ 1335f62bae50SIngo Molnar value = apic_read(APIC_LVTT); 1336f62bae50SIngo Molnar value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1337f62bae50SIngo Molnar apic_write(APIC_LVTT, value); 1338f62bae50SIngo Molnar } 1339f62bae50SIngo Molnar #endif 1340f62bae50SIngo Molnar 1341f62bae50SIngo Molnar setup_apic_nmi_watchdog(NULL); 1342f62bae50SIngo Molnar apic_pm_activate(); 1343f62bae50SIngo Molnar } 1344f62bae50SIngo Molnar 1345f62bae50SIngo Molnar #ifdef CONFIG_X86_X2APIC 1346f62bae50SIngo Molnar void check_x2apic(void) 1347f62bae50SIngo Molnar { 1348ef1f87aaSSuresh Siddha if (x2apic_enabled()) { 1349f62bae50SIngo Molnar pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); 1350fc1edaf9SSuresh Siddha x2apic_preenabled = x2apic_mode = 1; 1351f62bae50SIngo Molnar } 1352f62bae50SIngo Molnar } 1353f62bae50SIngo Molnar 1354f62bae50SIngo Molnar void enable_x2apic(void) 1355f62bae50SIngo Molnar { 1356f62bae50SIngo Molnar int msr, msr2; 1357f62bae50SIngo Molnar 1358fc1edaf9SSuresh Siddha if (!x2apic_mode) 1359f62bae50SIngo Molnar return; 1360f62bae50SIngo Molnar 1361f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, msr, msr2); 1362f62bae50SIngo Molnar if (!(msr & X2APIC_ENABLE)) { 1363450b1e8dSMike Travis printk_once(KERN_INFO "Enabling x2apic\n"); 1364f62bae50SIngo Molnar wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); 1365f62bae50SIngo Molnar } 1366f62bae50SIngo Molnar } 136793758238SWeidong Han #endif /* CONFIG_X86_X2APIC */ 1368f62bae50SIngo Molnar 1369ce69a784SGleb Natapov int __init enable_IR(void) 1370f62bae50SIngo Molnar { 1371f62bae50SIngo Molnar #ifdef CONFIG_INTR_REMAP 137293758238SWeidong Han if (!intr_remapping_supported()) { 137393758238SWeidong Han pr_debug("intr-remapping not supported\n"); 1374ce69a784SGleb Natapov return 0; 137593758238SWeidong Han } 137693758238SWeidong Han 137793758238SWeidong Han if (!x2apic_preenabled && skip_ioapic_setup) { 137893758238SWeidong Han pr_info("Skipped enabling intr-remap because of skipping " 137993758238SWeidong Han "io-apic setup\n"); 1380ce69a784SGleb Natapov return 0; 1381f62bae50SIngo Molnar } 1382f62bae50SIngo Molnar 1383ce69a784SGleb Natapov if (enable_intr_remapping(x2apic_supported())) 1384ce69a784SGleb Natapov return 0; 1385ce69a784SGleb Natapov 1386ce69a784SGleb Natapov pr_info("Enabled Interrupt-remapping\n"); 1387ce69a784SGleb Natapov 1388ce69a784SGleb Natapov return 1; 1389ce69a784SGleb Natapov 1390ce69a784SGleb Natapov #endif 1391ce69a784SGleb Natapov return 0; 1392ce69a784SGleb Natapov } 1393ce69a784SGleb Natapov 1394ce69a784SGleb Natapov void __init enable_IR_x2apic(void) 1395ce69a784SGleb Natapov { 1396ce69a784SGleb Natapov unsigned long flags; 1397ce69a784SGleb Natapov struct IO_APIC_route_entry **ioapic_entries = NULL; 1398ce69a784SGleb Natapov int ret, x2apic_enabled = 0; 1399e670761fSYinghai Lu int dmar_table_init_ret; 1400b7f42ab2SYinghai Lu 1401b7f42ab2SYinghai Lu dmar_table_init_ret = dmar_table_init(); 1402e670761fSYinghai Lu if (dmar_table_init_ret && !x2apic_supported()) 1403e670761fSYinghai Lu return; 1404ce69a784SGleb Natapov 1405b24696bcSFenghua Yu ioapic_entries = alloc_ioapic_entries(); 1406b24696bcSFenghua Yu if (!ioapic_entries) { 1407ce69a784SGleb Natapov pr_err("Allocate ioapic_entries failed\n"); 1408ce69a784SGleb Natapov goto out; 1409b24696bcSFenghua Yu } 1410b24696bcSFenghua Yu 1411b24696bcSFenghua Yu ret = save_IO_APIC_setup(ioapic_entries); 1412f62bae50SIngo Molnar if (ret) { 1413f62bae50SIngo Molnar pr_info("Saving IO-APIC state failed: %d\n", ret); 1414ce69a784SGleb Natapov goto out; 1415f62bae50SIngo Molnar } 1416f62bae50SIngo Molnar 141705c3dc2cSSuresh Siddha local_irq_save(flags); 1418b81bb373SJacob Pan legacy_pic->mask_all(); 1419ce69a784SGleb Natapov mask_IO_APIC_setup(ioapic_entries); 142005c3dc2cSSuresh Siddha 1421b7f42ab2SYinghai Lu if (dmar_table_init_ret) 1422b7f42ab2SYinghai Lu ret = 0; 1423b7f42ab2SYinghai Lu else 1424ce69a784SGleb Natapov ret = enable_IR(); 1425b7f42ab2SYinghai Lu 1426ce69a784SGleb Natapov if (!ret) { 1427ce69a784SGleb Natapov /* IR is required if there is APIC ID > 255 even when running 1428ce69a784SGleb Natapov * under KVM 1429ce69a784SGleb Natapov */ 1430ce69a784SGleb Natapov if (max_physical_apicid > 255 || !kvm_para_available()) 1431ce69a784SGleb Natapov goto nox2apic; 1432ce69a784SGleb Natapov /* 1433ce69a784SGleb Natapov * without IR all CPUs can be addressed by IOAPIC/MSI 1434ce69a784SGleb Natapov * only in physical mode 1435ce69a784SGleb Natapov */ 1436ce69a784SGleb Natapov x2apic_force_phys(); 1437ce69a784SGleb Natapov } 1438f62bae50SIngo Molnar 1439ce69a784SGleb Natapov x2apic_enabled = 1; 144093758238SWeidong Han 1441fc1edaf9SSuresh Siddha if (x2apic_supported() && !x2apic_mode) { 1442fc1edaf9SSuresh Siddha x2apic_mode = 1; 1443f62bae50SIngo Molnar enable_x2apic(); 144493758238SWeidong Han pr_info("Enabled x2apic\n"); 1445f62bae50SIngo Molnar } 1446f62bae50SIngo Molnar 1447ce69a784SGleb Natapov nox2apic: 1448ce69a784SGleb Natapov if (!ret) /* IR enabling failed */ 1449b24696bcSFenghua Yu restore_IO_APIC_setup(ioapic_entries); 1450b81bb373SJacob Pan legacy_pic->restore_mask(); 1451f62bae50SIngo Molnar local_irq_restore(flags); 1452f62bae50SIngo Molnar 1453ce69a784SGleb Natapov out: 1454b24696bcSFenghua Yu if (ioapic_entries) 1455b24696bcSFenghua Yu free_ioapic_entries(ioapic_entries); 145693758238SWeidong Han 1457ce69a784SGleb Natapov if (x2apic_enabled) 145893758238SWeidong Han return; 145993758238SWeidong Han 146093758238SWeidong Han if (x2apic_preenabled) 1461ce69a784SGleb Natapov panic("x2apic: enabled by BIOS but kernel init failed."); 146293758238SWeidong Han else if (cpu_has_x2apic) 1463ce69a784SGleb Natapov pr_info("Not enabling x2apic, Intr-remapping init failed.\n"); 1464f62bae50SIngo Molnar } 146593758238SWeidong Han 1466f62bae50SIngo Molnar #ifdef CONFIG_X86_64 1467f62bae50SIngo Molnar /* 1468f62bae50SIngo Molnar * Detect and enable local APICs on non-SMP boards. 1469f62bae50SIngo Molnar * Original code written by Keir Fraser. 1470f62bae50SIngo Molnar * On AMD64 we trust the BIOS - if it says no APIC it is likely 1471f62bae50SIngo Molnar * not correctly set up (usually the APIC timer won't work etc.) 1472f62bae50SIngo Molnar */ 1473f62bae50SIngo Molnar static int __init detect_init_APIC(void) 1474f62bae50SIngo Molnar { 1475f62bae50SIngo Molnar if (!cpu_has_apic) { 1476f62bae50SIngo Molnar pr_info("No local APIC present\n"); 1477f62bae50SIngo Molnar return -1; 1478f62bae50SIngo Molnar } 1479f62bae50SIngo Molnar 1480f62bae50SIngo Molnar mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1481f62bae50SIngo Molnar return 0; 1482f62bae50SIngo Molnar } 1483f62bae50SIngo Molnar #else 1484f62bae50SIngo Molnar /* 1485f62bae50SIngo Molnar * Detect and initialize APIC 1486f62bae50SIngo Molnar */ 1487f62bae50SIngo Molnar static int __init detect_init_APIC(void) 1488f62bae50SIngo Molnar { 1489f62bae50SIngo Molnar u32 h, l, features; 1490f62bae50SIngo Molnar 1491f62bae50SIngo Molnar /* Disabled by kernel option? */ 1492f62bae50SIngo Molnar if (disable_apic) 1493f62bae50SIngo Molnar return -1; 1494f62bae50SIngo Molnar 1495f62bae50SIngo Molnar switch (boot_cpu_data.x86_vendor) { 1496f62bae50SIngo Molnar case X86_VENDOR_AMD: 1497f62bae50SIngo Molnar if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1498f62bae50SIngo Molnar (boot_cpu_data.x86 >= 15)) 1499f62bae50SIngo Molnar break; 1500f62bae50SIngo Molnar goto no_apic; 1501f62bae50SIngo Molnar case X86_VENDOR_INTEL: 1502f62bae50SIngo Molnar if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1503f62bae50SIngo Molnar (boot_cpu_data.x86 == 5 && cpu_has_apic)) 1504f62bae50SIngo Molnar break; 1505f62bae50SIngo Molnar goto no_apic; 1506f62bae50SIngo Molnar default: 1507f62bae50SIngo Molnar goto no_apic; 1508f62bae50SIngo Molnar } 1509f62bae50SIngo Molnar 1510f62bae50SIngo Molnar if (!cpu_has_apic) { 1511f62bae50SIngo Molnar /* 1512f62bae50SIngo Molnar * Over-ride BIOS and try to enable the local APIC only if 1513f62bae50SIngo Molnar * "lapic" specified. 1514f62bae50SIngo Molnar */ 1515f62bae50SIngo Molnar if (!force_enable_local_apic) { 1516f62bae50SIngo Molnar pr_info("Local APIC disabled by BIOS -- " 1517f62bae50SIngo Molnar "you can enable it with \"lapic\"\n"); 1518f62bae50SIngo Molnar return -1; 1519f62bae50SIngo Molnar } 1520f62bae50SIngo Molnar /* 1521f62bae50SIngo Molnar * Some BIOSes disable the local APIC in the APIC_BASE 1522f62bae50SIngo Molnar * MSR. This can only be done in software for Intel P6 or later 1523f62bae50SIngo Molnar * and AMD K7 (Model > 1) or later. 1524f62bae50SIngo Molnar */ 1525f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, l, h); 1526f62bae50SIngo Molnar if (!(l & MSR_IA32_APICBASE_ENABLE)) { 1527f62bae50SIngo Molnar pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 1528f62bae50SIngo Molnar l &= ~MSR_IA32_APICBASE_BASE; 1529f62bae50SIngo Molnar l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; 1530f62bae50SIngo Molnar wrmsr(MSR_IA32_APICBASE, l, h); 1531f62bae50SIngo Molnar enabled_via_apicbase = 1; 1532f62bae50SIngo Molnar } 1533f62bae50SIngo Molnar } 1534f62bae50SIngo Molnar /* 1535f62bae50SIngo Molnar * The APIC feature bit should now be enabled 1536f62bae50SIngo Molnar * in `cpuid' 1537f62bae50SIngo Molnar */ 1538f62bae50SIngo Molnar features = cpuid_edx(1); 1539f62bae50SIngo Molnar if (!(features & (1 << X86_FEATURE_APIC))) { 1540f62bae50SIngo Molnar pr_warning("Could not enable APIC!\n"); 1541f62bae50SIngo Molnar return -1; 1542f62bae50SIngo Molnar } 1543f62bae50SIngo Molnar set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1544f62bae50SIngo Molnar mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1545f62bae50SIngo Molnar 1546f62bae50SIngo Molnar /* The BIOS may have set up the APIC at some other address */ 1547f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, l, h); 1548f62bae50SIngo Molnar if (l & MSR_IA32_APICBASE_ENABLE) 1549f62bae50SIngo Molnar mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1550f62bae50SIngo Molnar 1551f62bae50SIngo Molnar pr_info("Found and enabled local APIC!\n"); 1552f62bae50SIngo Molnar 1553f62bae50SIngo Molnar apic_pm_activate(); 1554f62bae50SIngo Molnar 1555f62bae50SIngo Molnar return 0; 1556f62bae50SIngo Molnar 1557f62bae50SIngo Molnar no_apic: 1558f62bae50SIngo Molnar pr_info("No local APIC present or hardware disabled\n"); 1559f62bae50SIngo Molnar return -1; 1560f62bae50SIngo Molnar } 1561f62bae50SIngo Molnar #endif 1562f62bae50SIngo Molnar 1563f62bae50SIngo Molnar #ifdef CONFIG_X86_64 1564f62bae50SIngo Molnar void __init early_init_lapic_mapping(void) 1565f62bae50SIngo Molnar { 1566f62bae50SIngo Molnar /* 1567f62bae50SIngo Molnar * If no local APIC can be found then go out 1568f62bae50SIngo Molnar * : it means there is no mpatable and MADT 1569f62bae50SIngo Molnar */ 1570f62bae50SIngo Molnar if (!smp_found_config) 1571f62bae50SIngo Molnar return; 1572f62bae50SIngo Molnar 1573d3a247bfSCyrill Gorcunov set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); 1574f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 1575d3a247bfSCyrill Gorcunov APIC_BASE, mp_lapic_addr); 1576f62bae50SIngo Molnar 1577f62bae50SIngo Molnar /* 1578f62bae50SIngo Molnar * Fetch the APIC ID of the BSP in case we have a 1579f62bae50SIngo Molnar * default configuration (or the MP table is broken). 1580f62bae50SIngo Molnar */ 1581f62bae50SIngo Molnar boot_cpu_physical_apicid = read_apic_id(); 1582f62bae50SIngo Molnar } 1583f62bae50SIngo Molnar #endif 1584f62bae50SIngo Molnar 1585f62bae50SIngo Molnar /** 1586f62bae50SIngo Molnar * init_apic_mappings - initialize APIC mappings 1587f62bae50SIngo Molnar */ 1588f62bae50SIngo Molnar void __init init_apic_mappings(void) 1589f62bae50SIngo Molnar { 15904401da61SYinghai Lu unsigned int new_apicid; 15914401da61SYinghai Lu 1592fc1edaf9SSuresh Siddha if (x2apic_mode) { 1593f62bae50SIngo Molnar boot_cpu_physical_apicid = read_apic_id(); 1594f62bae50SIngo Molnar return; 1595f62bae50SIngo Molnar } 1596f62bae50SIngo Molnar 15974797f6b0SYinghai Lu /* If no local APIC can be found return early */ 1598f62bae50SIngo Molnar if (!smp_found_config && detect_init_APIC()) { 15994797f6b0SYinghai Lu /* lets NOP'ify apic operations */ 16004797f6b0SYinghai Lu pr_info("APIC: disable apic facility\n"); 16014797f6b0SYinghai Lu apic_disable(); 16024797f6b0SYinghai Lu } else { 1603f62bae50SIngo Molnar apic_phys = mp_lapic_addr; 1604f62bae50SIngo Molnar 16054401da61SYinghai Lu /* 16064401da61SYinghai Lu * acpi lapic path already maps that address in 16074401da61SYinghai Lu * acpi_register_lapic_address() 16084401da61SYinghai Lu */ 16095989cd6aSEric W. Biederman if (!acpi_lapic && !smp_found_config) 1610f62bae50SIngo Molnar set_fixmap_nocache(FIX_APIC_BASE, apic_phys); 16114401da61SYinghai Lu 1612f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", 1613f62bae50SIngo Molnar APIC_BASE, apic_phys); 1614cec6be6dSCyrill Gorcunov } 1615f62bae50SIngo Molnar 1616f62bae50SIngo Molnar /* 1617f62bae50SIngo Molnar * Fetch the APIC ID of the BSP in case we have a 1618f62bae50SIngo Molnar * default configuration (or the MP table is broken). 1619f62bae50SIngo Molnar */ 16204401da61SYinghai Lu new_apicid = read_apic_id(); 16214401da61SYinghai Lu if (boot_cpu_physical_apicid != new_apicid) { 16224401da61SYinghai Lu boot_cpu_physical_apicid = new_apicid; 1623103428e5SCyrill Gorcunov /* 1624103428e5SCyrill Gorcunov * yeah -- we lie about apic_version 1625103428e5SCyrill Gorcunov * in case if apic was disabled via boot option 1626103428e5SCyrill Gorcunov * but it's not a problem for SMP compiled kernel 1627103428e5SCyrill Gorcunov * since smp_sanity_check is prepared for such a case 1628103428e5SCyrill Gorcunov * and disable smp mode 1629103428e5SCyrill Gorcunov */ 16304401da61SYinghai Lu apic_version[new_apicid] = 16314401da61SYinghai Lu GET_APIC_VERSION(apic_read(APIC_LVR)); 163208306ce6SCyrill Gorcunov } 1633f62bae50SIngo Molnar } 1634f62bae50SIngo Molnar 1635f62bae50SIngo Molnar /* 1636f62bae50SIngo Molnar * This initializes the IO-APIC and APIC hardware if this is 1637f62bae50SIngo Molnar * a UP kernel. 1638f62bae50SIngo Molnar */ 1639f62bae50SIngo Molnar int apic_version[MAX_APICS]; 1640f62bae50SIngo Molnar 1641f62bae50SIngo Molnar int __init APIC_init_uniprocessor(void) 1642f62bae50SIngo Molnar { 1643f62bae50SIngo Molnar if (disable_apic) { 1644f62bae50SIngo Molnar pr_info("Apic disabled\n"); 1645f62bae50SIngo Molnar return -1; 1646f62bae50SIngo Molnar } 1647f62bae50SIngo Molnar #ifdef CONFIG_X86_64 1648f62bae50SIngo Molnar if (!cpu_has_apic) { 1649f62bae50SIngo Molnar disable_apic = 1; 1650f62bae50SIngo Molnar pr_info("Apic disabled by BIOS\n"); 1651f62bae50SIngo Molnar return -1; 1652f62bae50SIngo Molnar } 1653f62bae50SIngo Molnar #else 1654f62bae50SIngo Molnar if (!smp_found_config && !cpu_has_apic) 1655f62bae50SIngo Molnar return -1; 1656f62bae50SIngo Molnar 1657f62bae50SIngo Molnar /* 1658f62bae50SIngo Molnar * Complain if the BIOS pretends there is one. 1659f62bae50SIngo Molnar */ 1660f62bae50SIngo Molnar if (!cpu_has_apic && 1661f62bae50SIngo Molnar APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 1662f62bae50SIngo Molnar pr_err("BIOS bug, local APIC 0x%x not detected!...\n", 1663f62bae50SIngo Molnar boot_cpu_physical_apicid); 1664f62bae50SIngo Molnar return -1; 1665f62bae50SIngo Molnar } 1666f62bae50SIngo Molnar #endif 1667f62bae50SIngo Molnar 1668472a474cSSuresh Siddha #ifndef CONFIG_SMP 1669f62bae50SIngo Molnar enable_IR_x2apic(); 1670f62bae50SIngo Molnar default_setup_apic_routing(); 1671472a474cSSuresh Siddha #endif 1672f62bae50SIngo Molnar 1673f62bae50SIngo Molnar verify_local_APIC(); 1674f62bae50SIngo Molnar connect_bsp_APIC(); 1675f62bae50SIngo Molnar 1676f62bae50SIngo Molnar #ifdef CONFIG_X86_64 1677f62bae50SIngo Molnar apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); 1678f62bae50SIngo Molnar #else 1679f62bae50SIngo Molnar /* 1680f62bae50SIngo Molnar * Hack: In case of kdump, after a crash, kernel might be booting 1681f62bae50SIngo Molnar * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 1682f62bae50SIngo Molnar * might be zero if read from MP tables. Get it from LAPIC. 1683f62bae50SIngo Molnar */ 1684f62bae50SIngo Molnar # ifdef CONFIG_CRASH_DUMP 1685f62bae50SIngo Molnar boot_cpu_physical_apicid = read_apic_id(); 1686f62bae50SIngo Molnar # endif 1687f62bae50SIngo Molnar #endif 1688f62bae50SIngo Molnar physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1689f62bae50SIngo Molnar setup_local_APIC(); 1690f62bae50SIngo Molnar 1691f62bae50SIngo Molnar #ifdef CONFIG_X86_IO_APIC 1692f62bae50SIngo Molnar /* 1693f62bae50SIngo Molnar * Now enable IO-APICs, actually call clear_IO_APIC 1694f62bae50SIngo Molnar * We need clear_IO_APIC before enabling error vector 1695f62bae50SIngo Molnar */ 1696f62bae50SIngo Molnar if (!skip_ioapic_setup && nr_ioapics) 1697f62bae50SIngo Molnar enable_IO_APIC(); 1698f62bae50SIngo Molnar #endif 1699f62bae50SIngo Molnar 1700f62bae50SIngo Molnar end_local_APIC_setup(); 1701f62bae50SIngo Molnar 1702f62bae50SIngo Molnar #ifdef CONFIG_X86_IO_APIC 1703f62bae50SIngo Molnar if (smp_found_config && !skip_ioapic_setup && nr_ioapics) 1704f62bae50SIngo Molnar setup_IO_APIC(); 1705f62bae50SIngo Molnar else { 1706f62bae50SIngo Molnar nr_ioapics = 0; 1707f62bae50SIngo Molnar localise_nmi_watchdog(); 1708f62bae50SIngo Molnar } 1709f62bae50SIngo Molnar #else 1710f62bae50SIngo Molnar localise_nmi_watchdog(); 1711f62bae50SIngo Molnar #endif 1712f62bae50SIngo Molnar 1713736decacSThomas Gleixner x86_init.timers.setup_percpu_clockev(); 1714f62bae50SIngo Molnar #ifdef CONFIG_X86_64 1715f62bae50SIngo Molnar check_nmi_watchdog(); 1716f62bae50SIngo Molnar #endif 1717f62bae50SIngo Molnar 1718f62bae50SIngo Molnar return 0; 1719f62bae50SIngo Molnar } 1720f62bae50SIngo Molnar 1721f62bae50SIngo Molnar /* 1722f62bae50SIngo Molnar * Local APIC interrupts 1723f62bae50SIngo Molnar */ 1724f62bae50SIngo Molnar 1725f62bae50SIngo Molnar /* 1726f62bae50SIngo Molnar * This interrupt should _never_ happen with our APIC/SMP architecture 1727f62bae50SIngo Molnar */ 1728f62bae50SIngo Molnar void smp_spurious_interrupt(struct pt_regs *regs) 1729f62bae50SIngo Molnar { 1730f62bae50SIngo Molnar u32 v; 1731f62bae50SIngo Molnar 1732f62bae50SIngo Molnar exit_idle(); 1733f62bae50SIngo Molnar irq_enter(); 1734f62bae50SIngo Molnar /* 1735f62bae50SIngo Molnar * Check if this really is a spurious interrupt and ACK it 1736f62bae50SIngo Molnar * if it is a vectored one. Just in case... 1737f62bae50SIngo Molnar * Spurious interrupts should not be ACKed. 1738f62bae50SIngo Molnar */ 1739f62bae50SIngo Molnar v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); 1740f62bae50SIngo Molnar if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) 1741f62bae50SIngo Molnar ack_APIC_irq(); 1742f62bae50SIngo Molnar 1743f62bae50SIngo Molnar inc_irq_stat(irq_spurious_count); 1744f62bae50SIngo Molnar 1745f62bae50SIngo Molnar /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 1746f62bae50SIngo Molnar pr_info("spurious APIC interrupt on CPU#%d, " 1747f62bae50SIngo Molnar "should never happen.\n", smp_processor_id()); 1748f62bae50SIngo Molnar irq_exit(); 1749f62bae50SIngo Molnar } 1750f62bae50SIngo Molnar 1751f62bae50SIngo Molnar /* 1752f62bae50SIngo Molnar * This interrupt should never happen with our APIC/SMP architecture 1753f62bae50SIngo Molnar */ 1754f62bae50SIngo Molnar void smp_error_interrupt(struct pt_regs *regs) 1755f62bae50SIngo Molnar { 1756f62bae50SIngo Molnar u32 v, v1; 1757f62bae50SIngo Molnar 1758f62bae50SIngo Molnar exit_idle(); 1759f62bae50SIngo Molnar irq_enter(); 1760f62bae50SIngo Molnar /* First tickle the hardware, only then report what went on. -- REW */ 1761f62bae50SIngo Molnar v = apic_read(APIC_ESR); 1762f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1763f62bae50SIngo Molnar v1 = apic_read(APIC_ESR); 1764f62bae50SIngo Molnar ack_APIC_irq(); 1765f62bae50SIngo Molnar atomic_inc(&irq_err_count); 1766f62bae50SIngo Molnar 1767f62bae50SIngo Molnar /* 1768f62bae50SIngo Molnar * Here is what the APIC error bits mean: 1769f62bae50SIngo Molnar * 0: Send CS error 1770f62bae50SIngo Molnar * 1: Receive CS error 1771f62bae50SIngo Molnar * 2: Send accept error 1772f62bae50SIngo Molnar * 3: Receive accept error 1773f62bae50SIngo Molnar * 4: Reserved 1774f62bae50SIngo Molnar * 5: Send illegal vector 1775f62bae50SIngo Molnar * 6: Received illegal vector 1776f62bae50SIngo Molnar * 7: Illegal register address 1777f62bae50SIngo Molnar */ 1778f62bae50SIngo Molnar pr_debug("APIC error on CPU%d: %02x(%02x)\n", 1779f62bae50SIngo Molnar smp_processor_id(), v , v1); 1780f62bae50SIngo Molnar irq_exit(); 1781f62bae50SIngo Molnar } 1782f62bae50SIngo Molnar 1783f62bae50SIngo Molnar /** 1784f62bae50SIngo Molnar * connect_bsp_APIC - attach the APIC to the interrupt system 1785f62bae50SIngo Molnar */ 1786f62bae50SIngo Molnar void __init connect_bsp_APIC(void) 1787f62bae50SIngo Molnar { 1788f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1789f62bae50SIngo Molnar if (pic_mode) { 1790f62bae50SIngo Molnar /* 1791f62bae50SIngo Molnar * Do not trust the local APIC being empty at bootup. 1792f62bae50SIngo Molnar */ 1793f62bae50SIngo Molnar clear_local_APIC(); 1794f62bae50SIngo Molnar /* 1795f62bae50SIngo Molnar * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 1796f62bae50SIngo Molnar * local APIC to INT and NMI lines. 1797f62bae50SIngo Molnar */ 1798f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "leaving PIC mode, " 1799f62bae50SIngo Molnar "enabling APIC mode.\n"); 1800c0eaa453SCyrill Gorcunov imcr_pic_to_apic(); 1801f62bae50SIngo Molnar } 1802f62bae50SIngo Molnar #endif 1803f62bae50SIngo Molnar if (apic->enable_apic_mode) 1804f62bae50SIngo Molnar apic->enable_apic_mode(); 1805f62bae50SIngo Molnar } 1806f62bae50SIngo Molnar 1807f62bae50SIngo Molnar /** 1808f62bae50SIngo Molnar * disconnect_bsp_APIC - detach the APIC from the interrupt system 1809f62bae50SIngo Molnar * @virt_wire_setup: indicates, whether virtual wire mode is selected 1810f62bae50SIngo Molnar * 1811f62bae50SIngo Molnar * Virtual wire mode is necessary to deliver legacy interrupts even when the 1812f62bae50SIngo Molnar * APIC is disabled. 1813f62bae50SIngo Molnar */ 1814f62bae50SIngo Molnar void disconnect_bsp_APIC(int virt_wire_setup) 1815f62bae50SIngo Molnar { 1816f62bae50SIngo Molnar unsigned int value; 1817f62bae50SIngo Molnar 1818f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1819f62bae50SIngo Molnar if (pic_mode) { 1820f62bae50SIngo Molnar /* 1821f62bae50SIngo Molnar * Put the board back into PIC mode (has an effect only on 1822f62bae50SIngo Molnar * certain older boards). Note that APIC interrupts, including 1823f62bae50SIngo Molnar * IPIs, won't work beyond this point! The only exception are 1824f62bae50SIngo Molnar * INIT IPIs. 1825f62bae50SIngo Molnar */ 1826f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "disabling APIC mode, " 1827f62bae50SIngo Molnar "entering PIC mode.\n"); 1828c0eaa453SCyrill Gorcunov imcr_apic_to_pic(); 1829f62bae50SIngo Molnar return; 1830f62bae50SIngo Molnar } 1831f62bae50SIngo Molnar #endif 1832f62bae50SIngo Molnar 1833f62bae50SIngo Molnar /* Go back to Virtual Wire compatibility mode */ 1834f62bae50SIngo Molnar 1835f62bae50SIngo Molnar /* For the spurious interrupt use vector F, and enable it */ 1836f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 1837f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 1838f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 1839f62bae50SIngo Molnar value |= 0xf; 1840f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 1841f62bae50SIngo Molnar 1842f62bae50SIngo Molnar if (!virt_wire_setup) { 1843f62bae50SIngo Molnar /* 1844f62bae50SIngo Molnar * For LVT0 make it edge triggered, active high, 1845f62bae50SIngo Molnar * external and enabled 1846f62bae50SIngo Molnar */ 1847f62bae50SIngo Molnar value = apic_read(APIC_LVT0); 1848f62bae50SIngo Molnar value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1849f62bae50SIngo Molnar APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1850f62bae50SIngo Molnar APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1851f62bae50SIngo Molnar value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1852f62bae50SIngo Molnar value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 1853f62bae50SIngo Molnar apic_write(APIC_LVT0, value); 1854f62bae50SIngo Molnar } else { 1855f62bae50SIngo Molnar /* Disable LVT0 */ 1856f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_LVT_MASKED); 1857f62bae50SIngo Molnar } 1858f62bae50SIngo Molnar 1859f62bae50SIngo Molnar /* 1860f62bae50SIngo Molnar * For LVT1 make it edge triggered, active high, 1861f62bae50SIngo Molnar * nmi and enabled 1862f62bae50SIngo Molnar */ 1863f62bae50SIngo Molnar value = apic_read(APIC_LVT1); 1864f62bae50SIngo Molnar value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1865f62bae50SIngo Molnar APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1866f62bae50SIngo Molnar APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1867f62bae50SIngo Molnar value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1868f62bae50SIngo Molnar value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 1869f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 1870f62bae50SIngo Molnar } 1871f62bae50SIngo Molnar 1872f62bae50SIngo Molnar void __cpuinit generic_processor_info(int apicid, int version) 1873f62bae50SIngo Molnar { 1874f62bae50SIngo Molnar int cpu; 1875f62bae50SIngo Molnar 1876f62bae50SIngo Molnar /* 1877f62bae50SIngo Molnar * Validate version 1878f62bae50SIngo Molnar */ 1879f62bae50SIngo Molnar if (version == 0x0) { 1880f62bae50SIngo Molnar pr_warning("BIOS bug, APIC version is 0 for CPU#%d! " 1881f62bae50SIngo Molnar "fixing up to 0x10. (tell your hw vendor)\n", 1882f62bae50SIngo Molnar version); 1883f62bae50SIngo Molnar version = 0x10; 1884f62bae50SIngo Molnar } 1885f62bae50SIngo Molnar apic_version[apicid] = version; 1886f62bae50SIngo Molnar 1887f62bae50SIngo Molnar if (num_processors >= nr_cpu_ids) { 1888f62bae50SIngo Molnar int max = nr_cpu_ids; 1889f62bae50SIngo Molnar int thiscpu = max + disabled_cpus; 1890f62bae50SIngo Molnar 1891f62bae50SIngo Molnar pr_warning( 1892f62bae50SIngo Molnar "ACPI: NR_CPUS/possible_cpus limit of %i reached." 1893f62bae50SIngo Molnar " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 1894f62bae50SIngo Molnar 1895f62bae50SIngo Molnar disabled_cpus++; 1896f62bae50SIngo Molnar return; 1897f62bae50SIngo Molnar } 1898f62bae50SIngo Molnar 1899f62bae50SIngo Molnar num_processors++; 1900f62bae50SIngo Molnar cpu = cpumask_next_zero(-1, cpu_present_mask); 1901f62bae50SIngo Molnar 1902f62bae50SIngo Molnar if (version != apic_version[boot_cpu_physical_apicid]) 1903f62bae50SIngo Molnar WARN_ONCE(1, 1904f62bae50SIngo Molnar "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n", 1905f62bae50SIngo Molnar apic_version[boot_cpu_physical_apicid], cpu, version); 1906f62bae50SIngo Molnar 1907f62bae50SIngo Molnar physid_set(apicid, phys_cpu_present_map); 1908f62bae50SIngo Molnar if (apicid == boot_cpu_physical_apicid) { 1909f62bae50SIngo Molnar /* 1910f62bae50SIngo Molnar * x86_bios_cpu_apicid is required to have processors listed 1911f62bae50SIngo Molnar * in same order as logical cpu numbers. Hence the first 1912f62bae50SIngo Molnar * entry is BSP, and so on. 1913f62bae50SIngo Molnar */ 1914f62bae50SIngo Molnar cpu = 0; 1915f62bae50SIngo Molnar } 1916f62bae50SIngo Molnar if (apicid > max_physical_apicid) 1917f62bae50SIngo Molnar max_physical_apicid = apicid; 1918f62bae50SIngo Molnar 1919f62bae50SIngo Molnar #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 1920f62bae50SIngo Molnar early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 1921f62bae50SIngo Molnar early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 1922f62bae50SIngo Molnar #endif 1923f62bae50SIngo Molnar 1924f62bae50SIngo Molnar set_cpu_possible(cpu, true); 1925f62bae50SIngo Molnar set_cpu_present(cpu, true); 1926f62bae50SIngo Molnar } 1927f62bae50SIngo Molnar 1928f62bae50SIngo Molnar int hard_smp_processor_id(void) 1929f62bae50SIngo Molnar { 1930f62bae50SIngo Molnar return read_apic_id(); 1931f62bae50SIngo Molnar } 1932f62bae50SIngo Molnar 1933f62bae50SIngo Molnar void default_init_apic_ldr(void) 1934f62bae50SIngo Molnar { 1935f62bae50SIngo Molnar unsigned long val; 1936f62bae50SIngo Molnar 1937f62bae50SIngo Molnar apic_write(APIC_DFR, APIC_DFR_VALUE); 1938f62bae50SIngo Molnar val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; 1939f62bae50SIngo Molnar val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); 1940f62bae50SIngo Molnar apic_write(APIC_LDR, val); 1941f62bae50SIngo Molnar } 1942f62bae50SIngo Molnar 1943f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1944f62bae50SIngo Molnar int default_apicid_to_node(int logical_apicid) 1945f62bae50SIngo Molnar { 1946f62bae50SIngo Molnar #ifdef CONFIG_SMP 1947f62bae50SIngo Molnar return apicid_2_node[hard_smp_processor_id()]; 1948f62bae50SIngo Molnar #else 1949f62bae50SIngo Molnar return 0; 1950f62bae50SIngo Molnar #endif 1951f62bae50SIngo Molnar } 1952f62bae50SIngo Molnar #endif 1953f62bae50SIngo Molnar 1954f62bae50SIngo Molnar /* 1955f62bae50SIngo Molnar * Power management 1956f62bae50SIngo Molnar */ 1957f62bae50SIngo Molnar #ifdef CONFIG_PM 1958f62bae50SIngo Molnar 1959f62bae50SIngo Molnar static struct { 1960f62bae50SIngo Molnar /* 1961f62bae50SIngo Molnar * 'active' is true if the local APIC was enabled by us and 1962f62bae50SIngo Molnar * not the BIOS; this signifies that we are also responsible 1963f62bae50SIngo Molnar * for disabling it before entering apm/acpi suspend 1964f62bae50SIngo Molnar */ 1965f62bae50SIngo Molnar int active; 1966f62bae50SIngo Molnar /* r/w apic fields */ 1967f62bae50SIngo Molnar unsigned int apic_id; 1968f62bae50SIngo Molnar unsigned int apic_taskpri; 1969f62bae50SIngo Molnar unsigned int apic_ldr; 1970f62bae50SIngo Molnar unsigned int apic_dfr; 1971f62bae50SIngo Molnar unsigned int apic_spiv; 1972f62bae50SIngo Molnar unsigned int apic_lvtt; 1973f62bae50SIngo Molnar unsigned int apic_lvtpc; 1974f62bae50SIngo Molnar unsigned int apic_lvt0; 1975f62bae50SIngo Molnar unsigned int apic_lvt1; 1976f62bae50SIngo Molnar unsigned int apic_lvterr; 1977f62bae50SIngo Molnar unsigned int apic_tmict; 1978f62bae50SIngo Molnar unsigned int apic_tdcr; 1979f62bae50SIngo Molnar unsigned int apic_thmr; 1980f62bae50SIngo Molnar } apic_pm_state; 1981f62bae50SIngo Molnar 1982f62bae50SIngo Molnar static int lapic_suspend(struct sys_device *dev, pm_message_t state) 1983f62bae50SIngo Molnar { 1984f62bae50SIngo Molnar unsigned long flags; 1985f62bae50SIngo Molnar int maxlvt; 1986f62bae50SIngo Molnar 1987f62bae50SIngo Molnar if (!apic_pm_state.active) 1988f62bae50SIngo Molnar return 0; 1989f62bae50SIngo Molnar 1990f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 1991f62bae50SIngo Molnar 1992f62bae50SIngo Molnar apic_pm_state.apic_id = apic_read(APIC_ID); 1993f62bae50SIngo Molnar apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 1994f62bae50SIngo Molnar apic_pm_state.apic_ldr = apic_read(APIC_LDR); 1995f62bae50SIngo Molnar apic_pm_state.apic_dfr = apic_read(APIC_DFR); 1996f62bae50SIngo Molnar apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 1997f62bae50SIngo Molnar apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 1998f62bae50SIngo Molnar if (maxlvt >= 4) 1999f62bae50SIngo Molnar apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2000f62bae50SIngo Molnar apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2001f62bae50SIngo Molnar apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2002f62bae50SIngo Molnar apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2003f62bae50SIngo Molnar apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2004f62bae50SIngo Molnar apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 20054efc0670SAndi Kleen #ifdef CONFIG_X86_THERMAL_VECTOR 2006f62bae50SIngo Molnar if (maxlvt >= 5) 2007f62bae50SIngo Molnar apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2008f62bae50SIngo Molnar #endif 2009f62bae50SIngo Molnar 2010f62bae50SIngo Molnar local_irq_save(flags); 2011f62bae50SIngo Molnar disable_local_APIC(); 2012fc1edaf9SSuresh Siddha 2013b24696bcSFenghua Yu if (intr_remapping_enabled) 2014b24696bcSFenghua Yu disable_intr_remapping(); 2015fc1edaf9SSuresh Siddha 2016f62bae50SIngo Molnar local_irq_restore(flags); 2017f62bae50SIngo Molnar return 0; 2018f62bae50SIngo Molnar } 2019f62bae50SIngo Molnar 2020f62bae50SIngo Molnar static int lapic_resume(struct sys_device *dev) 2021f62bae50SIngo Molnar { 2022f62bae50SIngo Molnar unsigned int l, h; 2023f62bae50SIngo Molnar unsigned long flags; 2024f62bae50SIngo Molnar int maxlvt; 20253d58829bSJiri Slaby int ret = 0; 2026b24696bcSFenghua Yu struct IO_APIC_route_entry **ioapic_entries = NULL; 2027b24696bcSFenghua Yu 2028f62bae50SIngo Molnar if (!apic_pm_state.active) 2029f62bae50SIngo Molnar return 0; 2030f62bae50SIngo Molnar 2031b24696bcSFenghua Yu local_irq_save(flags); 20329a2755c3SWeidong Han if (intr_remapping_enabled) { 2033b24696bcSFenghua Yu ioapic_entries = alloc_ioapic_entries(); 2034b24696bcSFenghua Yu if (!ioapic_entries) { 2035b24696bcSFenghua Yu WARN(1, "Alloc ioapic_entries in lapic resume failed."); 20363d58829bSJiri Slaby ret = -ENOMEM; 20373d58829bSJiri Slaby goto restore; 2038b24696bcSFenghua Yu } 2039b24696bcSFenghua Yu 2040b24696bcSFenghua Yu ret = save_IO_APIC_setup(ioapic_entries); 2041b24696bcSFenghua Yu if (ret) { 2042b24696bcSFenghua Yu WARN(1, "Saving IO-APIC state failed: %d\n", ret); 2043b24696bcSFenghua Yu free_ioapic_entries(ioapic_entries); 20443d58829bSJiri Slaby goto restore; 2045b24696bcSFenghua Yu } 2046b24696bcSFenghua Yu 2047b24696bcSFenghua Yu mask_IO_APIC_setup(ioapic_entries); 2048b81bb373SJacob Pan legacy_pic->mask_all(); 2049b24696bcSFenghua Yu } 2050f62bae50SIngo Molnar 2051fc1edaf9SSuresh Siddha if (x2apic_mode) 2052f62bae50SIngo Molnar enable_x2apic(); 2053cf6567feSSuresh Siddha else { 2054f62bae50SIngo Molnar /* 2055f62bae50SIngo Molnar * Make sure the APICBASE points to the right address 2056f62bae50SIngo Molnar * 2057f62bae50SIngo Molnar * FIXME! This will be wrong if we ever support suspend on 2058f62bae50SIngo Molnar * SMP! We'll need to do this as part of the CPU restore! 2059f62bae50SIngo Molnar */ 2060f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, l, h); 2061f62bae50SIngo Molnar l &= ~MSR_IA32_APICBASE_BASE; 2062f62bae50SIngo Molnar l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2063f62bae50SIngo Molnar wrmsr(MSR_IA32_APICBASE, l, h); 2064f62bae50SIngo Molnar } 2065f62bae50SIngo Molnar 2066b24696bcSFenghua Yu maxlvt = lapic_get_maxlvt(); 2067f62bae50SIngo Molnar apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2068f62bae50SIngo Molnar apic_write(APIC_ID, apic_pm_state.apic_id); 2069f62bae50SIngo Molnar apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2070f62bae50SIngo Molnar apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2071f62bae50SIngo Molnar apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2072f62bae50SIngo Molnar apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2073f62bae50SIngo Molnar apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2074f62bae50SIngo Molnar apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2075f62bae50SIngo Molnar #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) 2076f62bae50SIngo Molnar if (maxlvt >= 5) 2077f62bae50SIngo Molnar apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2078f62bae50SIngo Molnar #endif 2079f62bae50SIngo Molnar if (maxlvt >= 4) 2080f62bae50SIngo Molnar apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2081f62bae50SIngo Molnar apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2082f62bae50SIngo Molnar apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2083f62bae50SIngo Molnar apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2084f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 2085f62bae50SIngo Molnar apic_read(APIC_ESR); 2086f62bae50SIngo Molnar apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2087f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 2088f62bae50SIngo Molnar apic_read(APIC_ESR); 2089f62bae50SIngo Molnar 20909a2755c3SWeidong Han if (intr_remapping_enabled) { 2091fc1edaf9SSuresh Siddha reenable_intr_remapping(x2apic_mode); 2092b81bb373SJacob Pan legacy_pic->restore_mask(); 2093b24696bcSFenghua Yu restore_IO_APIC_setup(ioapic_entries); 2094b24696bcSFenghua Yu free_ioapic_entries(ioapic_entries); 2095b24696bcSFenghua Yu } 20963d58829bSJiri Slaby restore: 2097f62bae50SIngo Molnar local_irq_restore(flags); 2098f62bae50SIngo Molnar 20993d58829bSJiri Slaby return ret; 2100f62bae50SIngo Molnar } 2101f62bae50SIngo Molnar 2102f62bae50SIngo Molnar /* 2103f62bae50SIngo Molnar * This device has no shutdown method - fully functioning local APICs 2104f62bae50SIngo Molnar * are needed on every CPU up until machine_halt/restart/poweroff. 2105f62bae50SIngo Molnar */ 2106f62bae50SIngo Molnar 2107f62bae50SIngo Molnar static struct sysdev_class lapic_sysclass = { 2108f62bae50SIngo Molnar .name = "lapic", 2109f62bae50SIngo Molnar .resume = lapic_resume, 2110f62bae50SIngo Molnar .suspend = lapic_suspend, 2111f62bae50SIngo Molnar }; 2112f62bae50SIngo Molnar 2113f62bae50SIngo Molnar static struct sys_device device_lapic = { 2114f62bae50SIngo Molnar .id = 0, 2115f62bae50SIngo Molnar .cls = &lapic_sysclass, 2116f62bae50SIngo Molnar }; 2117f62bae50SIngo Molnar 2118f62bae50SIngo Molnar static void __cpuinit apic_pm_activate(void) 2119f62bae50SIngo Molnar { 2120f62bae50SIngo Molnar apic_pm_state.active = 1; 2121f62bae50SIngo Molnar } 2122f62bae50SIngo Molnar 2123f62bae50SIngo Molnar static int __init init_lapic_sysfs(void) 2124f62bae50SIngo Molnar { 2125f62bae50SIngo Molnar int error; 2126f62bae50SIngo Molnar 2127f62bae50SIngo Molnar if (!cpu_has_apic) 2128f62bae50SIngo Molnar return 0; 2129f62bae50SIngo Molnar /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2130f62bae50SIngo Molnar 2131f62bae50SIngo Molnar error = sysdev_class_register(&lapic_sysclass); 2132f62bae50SIngo Molnar if (!error) 2133f62bae50SIngo Molnar error = sysdev_register(&device_lapic); 2134f62bae50SIngo Molnar return error; 2135f62bae50SIngo Molnar } 2136b24696bcSFenghua Yu 2137b24696bcSFenghua Yu /* local apic needs to resume before other devices access its registers. */ 2138b24696bcSFenghua Yu core_initcall(init_lapic_sysfs); 2139f62bae50SIngo Molnar 2140f62bae50SIngo Molnar #else /* CONFIG_PM */ 2141f62bae50SIngo Molnar 2142f62bae50SIngo Molnar static void apic_pm_activate(void) { } 2143f62bae50SIngo Molnar 2144f62bae50SIngo Molnar #endif /* CONFIG_PM */ 2145f62bae50SIngo Molnar 2146f62bae50SIngo Molnar #ifdef CONFIG_X86_64 2147e0e42142SYinghai Lu 2148e0e42142SYinghai Lu static int __cpuinit apic_cluster_num(void) 2149f62bae50SIngo Molnar { 2150f62bae50SIngo Molnar int i, clusters, zeros; 2151f62bae50SIngo Molnar unsigned id; 2152f62bae50SIngo Molnar u16 *bios_cpu_apicid; 2153f62bae50SIngo Molnar DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); 2154f62bae50SIngo Molnar 2155f62bae50SIngo Molnar bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); 2156f62bae50SIngo Molnar bitmap_zero(clustermap, NUM_APIC_CLUSTERS); 2157f62bae50SIngo Molnar 2158f62bae50SIngo Molnar for (i = 0; i < nr_cpu_ids; i++) { 2159f62bae50SIngo Molnar /* are we being called early in kernel startup? */ 2160f62bae50SIngo Molnar if (bios_cpu_apicid) { 2161f62bae50SIngo Molnar id = bios_cpu_apicid[i]; 2162f62bae50SIngo Molnar } else if (i < nr_cpu_ids) { 2163f62bae50SIngo Molnar if (cpu_present(i)) 2164f62bae50SIngo Molnar id = per_cpu(x86_bios_cpu_apicid, i); 2165f62bae50SIngo Molnar else 2166f62bae50SIngo Molnar continue; 2167f62bae50SIngo Molnar } else 2168f62bae50SIngo Molnar break; 2169f62bae50SIngo Molnar 2170f62bae50SIngo Molnar if (id != BAD_APICID) 2171f62bae50SIngo Molnar __set_bit(APIC_CLUSTERID(id), clustermap); 2172f62bae50SIngo Molnar } 2173f62bae50SIngo Molnar 2174f62bae50SIngo Molnar /* Problem: Partially populated chassis may not have CPUs in some of 2175f62bae50SIngo Molnar * the APIC clusters they have been allocated. Only present CPUs have 2176f62bae50SIngo Molnar * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. 2177f62bae50SIngo Molnar * Since clusters are allocated sequentially, count zeros only if 2178f62bae50SIngo Molnar * they are bounded by ones. 2179f62bae50SIngo Molnar */ 2180f62bae50SIngo Molnar clusters = 0; 2181f62bae50SIngo Molnar zeros = 0; 2182f62bae50SIngo Molnar for (i = 0; i < NUM_APIC_CLUSTERS; i++) { 2183f62bae50SIngo Molnar if (test_bit(i, clustermap)) { 2184f62bae50SIngo Molnar clusters += 1 + zeros; 2185f62bae50SIngo Molnar zeros = 0; 2186f62bae50SIngo Molnar } else 2187f62bae50SIngo Molnar ++zeros; 2188f62bae50SIngo Molnar } 2189f62bae50SIngo Molnar 2190e0e42142SYinghai Lu return clusters; 2191e0e42142SYinghai Lu } 2192e0e42142SYinghai Lu 2193e0e42142SYinghai Lu static int __cpuinitdata multi_checked; 2194e0e42142SYinghai Lu static int __cpuinitdata multi; 2195e0e42142SYinghai Lu 2196e0e42142SYinghai Lu static int __cpuinit set_multi(const struct dmi_system_id *d) 2197e0e42142SYinghai Lu { 2198e0e42142SYinghai Lu if (multi) 2199e0e42142SYinghai Lu return 0; 22006f0aced6SCyrill Gorcunov pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2201e0e42142SYinghai Lu multi = 1; 2202e0e42142SYinghai Lu return 0; 2203e0e42142SYinghai Lu } 2204e0e42142SYinghai Lu 2205e0e42142SYinghai Lu static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = { 2206e0e42142SYinghai Lu { 2207e0e42142SYinghai Lu .callback = set_multi, 2208e0e42142SYinghai Lu .ident = "IBM System Summit2", 2209e0e42142SYinghai Lu .matches = { 2210e0e42142SYinghai Lu DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2211e0e42142SYinghai Lu DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2212e0e42142SYinghai Lu }, 2213e0e42142SYinghai Lu }, 2214e0e42142SYinghai Lu {} 2215e0e42142SYinghai Lu }; 2216e0e42142SYinghai Lu 2217e0e42142SYinghai Lu static void __cpuinit dmi_check_multi(void) 2218e0e42142SYinghai Lu { 2219e0e42142SYinghai Lu if (multi_checked) 2220e0e42142SYinghai Lu return; 2221e0e42142SYinghai Lu 2222e0e42142SYinghai Lu dmi_check_system(multi_dmi_table); 2223e0e42142SYinghai Lu multi_checked = 1; 2224e0e42142SYinghai Lu } 2225f62bae50SIngo Molnar 2226f62bae50SIngo Molnar /* 2227e0e42142SYinghai Lu * apic_is_clustered_box() -- Check if we can expect good TSC 2228e0e42142SYinghai Lu * 2229e0e42142SYinghai Lu * Thus far, the major user of this is IBM's Summit2 series: 2230e0e42142SYinghai Lu * Clustered boxes may have unsynced TSC problems if they are 2231e0e42142SYinghai Lu * multi-chassis. 2232e0e42142SYinghai Lu * Use DMI to check them 2233f62bae50SIngo Molnar */ 2234e0e42142SYinghai Lu __cpuinit int apic_is_clustered_box(void) 2235e0e42142SYinghai Lu { 2236e0e42142SYinghai Lu dmi_check_multi(); 2237e0e42142SYinghai Lu if (multi) 2238e0e42142SYinghai Lu return 1; 2239e0e42142SYinghai Lu 2240e0e42142SYinghai Lu if (!is_vsmp_box()) 2241e0e42142SYinghai Lu return 0; 2242e0e42142SYinghai Lu 2243e0e42142SYinghai Lu /* 2244e0e42142SYinghai Lu * ScaleMP vSMPowered boxes have one cluster per board and TSCs are 2245e0e42142SYinghai Lu * not guaranteed to be synced between boards 2246e0e42142SYinghai Lu */ 2247e0e42142SYinghai Lu if (apic_cluster_num() > 1) 2248e0e42142SYinghai Lu return 1; 2249e0e42142SYinghai Lu 2250e0e42142SYinghai Lu return 0; 2251f62bae50SIngo Molnar } 2252f62bae50SIngo Molnar #endif 2253f62bae50SIngo Molnar 2254f62bae50SIngo Molnar /* 2255f62bae50SIngo Molnar * APIC command line parameters 2256f62bae50SIngo Molnar */ 2257f62bae50SIngo Molnar static int __init setup_disableapic(char *arg) 2258f62bae50SIngo Molnar { 2259f62bae50SIngo Molnar disable_apic = 1; 2260f62bae50SIngo Molnar setup_clear_cpu_cap(X86_FEATURE_APIC); 2261f62bae50SIngo Molnar return 0; 2262f62bae50SIngo Molnar } 2263f62bae50SIngo Molnar early_param("disableapic", setup_disableapic); 2264f62bae50SIngo Molnar 2265f62bae50SIngo Molnar /* same as disableapic, for compatibility */ 2266f62bae50SIngo Molnar static int __init setup_nolapic(char *arg) 2267f62bae50SIngo Molnar { 2268f62bae50SIngo Molnar return setup_disableapic(arg); 2269f62bae50SIngo Molnar } 2270f62bae50SIngo Molnar early_param("nolapic", setup_nolapic); 2271f62bae50SIngo Molnar 2272f62bae50SIngo Molnar static int __init parse_lapic_timer_c2_ok(char *arg) 2273f62bae50SIngo Molnar { 2274f62bae50SIngo Molnar local_apic_timer_c2_ok = 1; 2275f62bae50SIngo Molnar return 0; 2276f62bae50SIngo Molnar } 2277f62bae50SIngo Molnar early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2278f62bae50SIngo Molnar 2279f62bae50SIngo Molnar static int __init parse_disable_apic_timer(char *arg) 2280f62bae50SIngo Molnar { 2281f62bae50SIngo Molnar disable_apic_timer = 1; 2282f62bae50SIngo Molnar return 0; 2283f62bae50SIngo Molnar } 2284f62bae50SIngo Molnar early_param("noapictimer", parse_disable_apic_timer); 2285f62bae50SIngo Molnar 2286f62bae50SIngo Molnar static int __init parse_nolapic_timer(char *arg) 2287f62bae50SIngo Molnar { 2288f62bae50SIngo Molnar disable_apic_timer = 1; 2289f62bae50SIngo Molnar return 0; 2290f62bae50SIngo Molnar } 2291f62bae50SIngo Molnar early_param("nolapic_timer", parse_nolapic_timer); 2292f62bae50SIngo Molnar 2293f62bae50SIngo Molnar static int __init apic_set_verbosity(char *arg) 2294f62bae50SIngo Molnar { 2295f62bae50SIngo Molnar if (!arg) { 2296f62bae50SIngo Molnar #ifdef CONFIG_X86_64 2297f62bae50SIngo Molnar skip_ioapic_setup = 0; 2298f62bae50SIngo Molnar return 0; 2299f62bae50SIngo Molnar #endif 2300f62bae50SIngo Molnar return -EINVAL; 2301f62bae50SIngo Molnar } 2302f62bae50SIngo Molnar 2303f62bae50SIngo Molnar if (strcmp("debug", arg) == 0) 2304f62bae50SIngo Molnar apic_verbosity = APIC_DEBUG; 2305f62bae50SIngo Molnar else if (strcmp("verbose", arg) == 0) 2306f62bae50SIngo Molnar apic_verbosity = APIC_VERBOSE; 2307f62bae50SIngo Molnar else { 2308f62bae50SIngo Molnar pr_warning("APIC Verbosity level %s not recognised" 2309f62bae50SIngo Molnar " use apic=verbose or apic=debug\n", arg); 2310f62bae50SIngo Molnar return -EINVAL; 2311f62bae50SIngo Molnar } 2312f62bae50SIngo Molnar 2313f62bae50SIngo Molnar return 0; 2314f62bae50SIngo Molnar } 2315f62bae50SIngo Molnar early_param("apic", apic_set_verbosity); 2316f62bae50SIngo Molnar 2317f62bae50SIngo Molnar static int __init lapic_insert_resource(void) 2318f62bae50SIngo Molnar { 2319f62bae50SIngo Molnar if (!apic_phys) 2320f62bae50SIngo Molnar return -1; 2321f62bae50SIngo Molnar 2322f62bae50SIngo Molnar /* Put local APIC into the resource map. */ 2323f62bae50SIngo Molnar lapic_resource.start = apic_phys; 2324f62bae50SIngo Molnar lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2325f62bae50SIngo Molnar insert_resource(&iomem_resource, &lapic_resource); 2326f62bae50SIngo Molnar 2327f62bae50SIngo Molnar return 0; 2328f62bae50SIngo Molnar } 2329f62bae50SIngo Molnar 2330f62bae50SIngo Molnar /* 2331f62bae50SIngo Molnar * need call insert after e820_reserve_resources() 2332f62bae50SIngo Molnar * that is using request_resource 2333f62bae50SIngo Molnar */ 2334f62bae50SIngo Molnar late_initcall(lapic_insert_resource); 2335