1457c8996SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2f62bae50SIngo Molnar /* 3f62bae50SIngo Molnar * Local APIC handling, local APIC timers 4f62bae50SIngo Molnar * 5f62bae50SIngo Molnar * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6f62bae50SIngo Molnar * 7f62bae50SIngo Molnar * Fixes 8f62bae50SIngo Molnar * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 9f62bae50SIngo Molnar * thanks to Eric Gilmore 10f62bae50SIngo Molnar * and Rolf G. Tews 11f62bae50SIngo Molnar * for testing these extensively. 12f62bae50SIngo Molnar * Maciej W. Rozycki : Various updates and fixes. 13f62bae50SIngo Molnar * Mikael Pettersson : Power Management for UP-APIC. 14f62bae50SIngo Molnar * Pavel Machek and 15f62bae50SIngo Molnar * Mikael Pettersson : PM converted to driver model. 16f62bae50SIngo Molnar */ 17f62bae50SIngo Molnar 18cdd6c482SIngo Molnar #include <linux/perf_event.h> 19f62bae50SIngo Molnar #include <linux/kernel_stat.h> 20f62bae50SIngo Molnar #include <linux/mc146818rtc.h> 21f62bae50SIngo Molnar #include <linux/acpi_pmtmr.h> 22f62bae50SIngo Molnar #include <linux/clockchips.h> 23f62bae50SIngo Molnar #include <linux/interrupt.h> 2457c8a661SMike Rapoport #include <linux/memblock.h> 25f62bae50SIngo Molnar #include <linux/ftrace.h> 26f62bae50SIngo Molnar #include <linux/ioport.h> 27186f4360SPaul Gortmaker #include <linux/export.h> 28f3c6ea1bSRafael J. Wysocki #include <linux/syscore_ops.h> 29f62bae50SIngo Molnar #include <linux/delay.h> 30f62bae50SIngo Molnar #include <linux/timex.h> 31334955efSRalf Baechle #include <linux/i8253.h> 32f62bae50SIngo Molnar #include <linux/dmar.h> 33f62bae50SIngo Molnar #include <linux/init.h> 34f62bae50SIngo Molnar #include <linux/cpu.h> 35f62bae50SIngo Molnar #include <linux/dmi.h> 36f62bae50SIngo Molnar #include <linux/smp.h> 37f62bae50SIngo Molnar #include <linux/mm.h> 38f62bae50SIngo Molnar 3983ab8514SSteven Rostedt (Red Hat) #include <asm/trace/irq_vectors.h> 408a8f422dSSuresh Siddha #include <asm/irq_remapping.h> 41fb6a0408SMaciej W. Rozycki #include <asm/pc-conf-reg.h> 42cdd6c482SIngo Molnar #include <asm/perf_event.h> 43736decacSThomas Gleixner #include <asm/x86_init.h> 4460063497SArun Sharma #include <linux/atomic.h> 4525a068b8SDave Hansen #include <asm/barrier.h> 46f62bae50SIngo Molnar #include <asm/mpspec.h> 47f62bae50SIngo Molnar #include <asm/i8259.h> 48f62bae50SIngo Molnar #include <asm/proto.h> 49ad3bc25aSBorislav Petkov #include <asm/traps.h> 50f62bae50SIngo Molnar #include <asm/apic.h> 5113c01139SIngo Molnar #include <asm/acpi.h> 527167d08eSHenrik Kretzschmar #include <asm/io_apic.h> 53f62bae50SIngo Molnar #include <asm/desc.h> 54f62bae50SIngo Molnar #include <asm/hpet.h> 55f62bae50SIngo Molnar #include <asm/mtrr.h> 5616f871bcSRalf Baechle #include <asm/time.h> 57f62bae50SIngo Molnar #include <asm/smp.h> 58638bee71SH. Peter Anvin #include <asm/mce.h> 598c3ba8d0SKerstin Jonsson #include <asm/tsc.h> 602904ed8dSSheng Yang #include <asm/hypervisor.h> 61bd9240a1SPeter Zijlstra #include <asm/cpu_device_id.h> 62bd9240a1SPeter Zijlstra #include <asm/intel-family.h> 63447ae316SNicolai Stange #include <asm/irq_regs.h> 64b8d1d163SDaniel Sneddon #include <asm/cpu.h> 65f62bae50SIngo Molnar 66f62bae50SIngo Molnar unsigned int num_processors; 67f62bae50SIngo Molnar 68148f9bb8SPaul Gortmaker unsigned disabled_cpus; 69f62bae50SIngo Molnar 70f62bae50SIngo Molnar /* Processor that is doing the boot up */ 716444b40eSSean Christopherson unsigned int boot_cpu_physical_apicid __ro_after_init = -1U; 72cc08e04cSDavid Rientjes EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); 73f62bae50SIngo Molnar 746444b40eSSean Christopherson u8 boot_cpu_apic_version __ro_after_init; 75cff9ab2bSDenys Vlasenko 76f62bae50SIngo Molnar /* 77f62bae50SIngo Molnar * The highest APIC ID seen during enumeration. 78f62bae50SIngo Molnar */ 79a491cc90SJiang Liu static unsigned int max_physical_apicid; 80f62bae50SIngo Molnar 81f62bae50SIngo Molnar /* 82f62bae50SIngo Molnar * Bitmask of physically existing CPUs: 83f62bae50SIngo Molnar */ 84f62bae50SIngo Molnar physid_mask_t phys_cpu_present_map; 85f62bae50SIngo Molnar 86f62bae50SIngo Molnar /* 87151e0c7dSHATAYAMA Daisuke * Processor to be disabled specified by kernel parameter 88151e0c7dSHATAYAMA Daisuke * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to 89151e0c7dSHATAYAMA Daisuke * avoid undefined behaviour caused by sending INIT from AP to BSP. 90151e0c7dSHATAYAMA Daisuke */ 916444b40eSSean Christopherson static unsigned int disabled_cpu_apicid __ro_after_init = BAD_APICID; 92151e0c7dSHATAYAMA Daisuke 93151e0c7dSHATAYAMA Daisuke /* 94b7c4948eSHidehiro Kawai * This variable controls which CPUs receive external NMIs. By default, 95b7c4948eSHidehiro Kawai * external NMIs are delivered only to the BSP. 96b7c4948eSHidehiro Kawai */ 976444b40eSSean Christopherson static int apic_extnmi __ro_after_init = APIC_EXTNMI_BSP; 98b7c4948eSHidehiro Kawai 99b7c4948eSHidehiro Kawai /* 100ab0f59c6SDavid Woodhouse * Hypervisor supports 15 bits of APIC ID in MSI Extended Destination ID 101ab0f59c6SDavid Woodhouse */ 102ab0f59c6SDavid Woodhouse static bool virt_ext_dest_id __ro_after_init; 103ab0f59c6SDavid Woodhouse 104bea629d5SThomas Gleixner /* For parallel bootup. */ 105bea629d5SThomas Gleixner unsigned long apic_mmio_base __ro_after_init; 106bea629d5SThomas Gleixner 107ab0f59c6SDavid Woodhouse /* 108f62bae50SIngo Molnar * Map cpu index to physical APIC ID 109f62bae50SIngo Molnar */ 1100816b0f0SVlad Zolotarov DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); 1110816b0f0SVlad Zolotarov DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); 1123e9e57faSVitaly Kuznetsov DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX); 113f62bae50SIngo Molnar EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 114f62bae50SIngo Molnar EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 1153e9e57faSVitaly Kuznetsov EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); 116f62bae50SIngo Molnar 117f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1184c321ff8STejun Heo 1194c321ff8STejun Heo /* 1204c321ff8STejun Heo * On x86_32, the mapping between cpu and logical apicid may vary 1214c321ff8STejun Heo * depending on apic in use. The following early percpu variable is 1224c321ff8STejun Heo * used for the mapping. This is where the behaviors of x86_64 and 32 1234c321ff8STejun Heo * actually diverge. Let's keep it ugly for now. 1244c321ff8STejun Heo */ 1250816b0f0SVlad Zolotarov DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); 1264c321ff8STejun Heo 127f62bae50SIngo Molnar /* Local APIC was disabled by the BIOS and enabled by the kernel */ 1286444b40eSSean Christopherson static int enabled_via_apicbase __ro_after_init; 129f62bae50SIngo Molnar 130c0eaa453SCyrill Gorcunov /* 131c0eaa453SCyrill Gorcunov * Handle interrupt mode configuration register (IMCR). 132c0eaa453SCyrill Gorcunov * This register controls whether the interrupt signals 133c0eaa453SCyrill Gorcunov * that reach the BSP come from the master PIC or from the 134c0eaa453SCyrill Gorcunov * local APIC. Before entering Symmetric I/O Mode, either 135c0eaa453SCyrill Gorcunov * the BIOS or the operating system must switch out of 136c0eaa453SCyrill Gorcunov * PIC Mode by changing the IMCR. 137c0eaa453SCyrill Gorcunov */ 1385cda395fSAlexander van Heukelum static inline void imcr_pic_to_apic(void) 139c0eaa453SCyrill Gorcunov { 140c0eaa453SCyrill Gorcunov /* NMI and 8259 INTR go through APIC */ 141fb6a0408SMaciej W. Rozycki pc_conf_set(PC_CONF_MPS_IMCR, 0x01); 142c0eaa453SCyrill Gorcunov } 143c0eaa453SCyrill Gorcunov 1445cda395fSAlexander van Heukelum static inline void imcr_apic_to_pic(void) 145c0eaa453SCyrill Gorcunov { 146c0eaa453SCyrill Gorcunov /* NMI and 8259 INTR go directly to BSP */ 147fb6a0408SMaciej W. Rozycki pc_conf_set(PC_CONF_MPS_IMCR, 0x00); 148c0eaa453SCyrill Gorcunov } 149f62bae50SIngo Molnar #endif 150f62bae50SIngo Molnar 151279f1461SSuresh Siddha /* 152279f1461SSuresh Siddha * Knob to control our willingness to enable the local APIC. 153279f1461SSuresh Siddha * 154279f1461SSuresh Siddha * +1=force-enable 155279f1461SSuresh Siddha */ 156279f1461SSuresh Siddha static int force_enable_local_apic __initdata; 157dc9788f4SDavid Rientjes 158279f1461SSuresh Siddha /* 159279f1461SSuresh Siddha * APIC command line parameters 160279f1461SSuresh Siddha */ 161279f1461SSuresh Siddha static int __init parse_lapic(char *arg) 162279f1461SSuresh Siddha { 16397f2645fSMasahiro Yamada if (IS_ENABLED(CONFIG_X86_32) && !arg) 164279f1461SSuresh Siddha force_enable_local_apic = 1; 16527cf9298SMathias Krause else if (arg && !strncmp(arg, "notscdeadline", 13)) 166279f1461SSuresh Siddha setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 167279f1461SSuresh Siddha return 0; 168279f1461SSuresh Siddha } 169279f1461SSuresh Siddha early_param("lapic", parse_lapic); 170279f1461SSuresh Siddha 171f62bae50SIngo Molnar #ifdef CONFIG_X86_64 172f62bae50SIngo Molnar static int apic_calibrate_pmtmr __initdata; 173f62bae50SIngo Molnar static __init int setup_apicpmtimer(char *s) 174f62bae50SIngo Molnar { 175f62bae50SIngo Molnar apic_calibrate_pmtmr = 1; 176f62bae50SIngo Molnar notsc_setup(NULL); 17712441ccdSRandy Dunlap return 1; 178f62bae50SIngo Molnar } 179f62bae50SIngo Molnar __setup("apicpmtimer", setup_apicpmtimer); 180f62bae50SIngo Molnar #endif 181f62bae50SIngo Molnar 1826444b40eSSean Christopherson unsigned long mp_lapic_addr __ro_after_init; 183*49062454SThomas Gleixner bool apic_is_disabled __ro_after_init; 184f62bae50SIngo Molnar /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 18525874a29SHenrik Kretzschmar static int disable_apic_timer __initdata; 186f62bae50SIngo Molnar /* Local APIC timer works in C2 */ 1876444b40eSSean Christopherson int local_apic_timer_c2_ok __ro_after_init; 188f62bae50SIngo Molnar EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 189f62bae50SIngo Molnar 190f62bae50SIngo Molnar /* 191f62bae50SIngo Molnar * Debug level, exported for io_apic.c 192f62bae50SIngo Molnar */ 1936444b40eSSean Christopherson int apic_verbosity __ro_after_init; 194f62bae50SIngo Molnar 1956444b40eSSean Christopherson int pic_mode __ro_after_init; 196f62bae50SIngo Molnar 197f62bae50SIngo Molnar /* Have we found an MP table */ 1986444b40eSSean Christopherson int smp_found_config __ro_after_init; 199f62bae50SIngo Molnar 200f62bae50SIngo Molnar static struct resource lapic_resource = { 201f62bae50SIngo Molnar .name = "Local APIC", 202f62bae50SIngo Molnar .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 203f62bae50SIngo Molnar }; 204f62bae50SIngo Molnar 20552ae346bSDaniel Drake unsigned int lapic_timer_period = 0; 206f62bae50SIngo Molnar 207f62bae50SIngo Molnar static void apic_pm_activate(void); 208f62bae50SIngo Molnar 2096444b40eSSean Christopherson static unsigned long apic_phys __ro_after_init; 210f62bae50SIngo Molnar 211f62bae50SIngo Molnar /* 212f62bae50SIngo Molnar * Get the LAPIC version 213f62bae50SIngo Molnar */ 214f62bae50SIngo Molnar static inline int lapic_get_version(void) 215f62bae50SIngo Molnar { 216f62bae50SIngo Molnar return GET_APIC_VERSION(apic_read(APIC_LVR)); 217f62bae50SIngo Molnar } 218f62bae50SIngo Molnar 219f62bae50SIngo Molnar /* 220f62bae50SIngo Molnar * Check, if the APIC is integrated or a separate chip 221f62bae50SIngo Molnar */ 222f62bae50SIngo Molnar static inline int lapic_is_integrated(void) 223f62bae50SIngo Molnar { 224f62bae50SIngo Molnar return APIC_INTEGRATED(lapic_get_version()); 225f62bae50SIngo Molnar } 226f62bae50SIngo Molnar 227f62bae50SIngo Molnar /* 228f62bae50SIngo Molnar * Check, whether this is a modern or a first generation APIC 229f62bae50SIngo Molnar */ 230f62bae50SIngo Molnar static int modern_apic(void) 231f62bae50SIngo Molnar { 232f62bae50SIngo Molnar /* AMD systems use old APIC versions, so check the CPU */ 233f62bae50SIngo Molnar if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 234f62bae50SIngo Molnar boot_cpu_data.x86 >= 0xf) 235f62bae50SIngo Molnar return 1; 236da33dfefSPu Wen 237da33dfefSPu Wen /* Hygon systems use modern APIC */ 238da33dfefSPu Wen if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 239da33dfefSPu Wen return 1; 240da33dfefSPu Wen 241f62bae50SIngo Molnar return lapic_get_version() >= 0x14; 242f62bae50SIngo Molnar } 243f62bae50SIngo Molnar 24408306ce6SCyrill Gorcunov /* 245a933c618SCyrill Gorcunov * right after this call apic become NOOP driven 246a933c618SCyrill Gorcunov * so apic->write/read doesn't do anything 24708306ce6SCyrill Gorcunov */ 24825874a29SHenrik Kretzschmar static void __init apic_disable(void) 24908306ce6SCyrill Gorcunov { 250f88f2b4fSCyrill Gorcunov pr_info("APIC: switched to apic NOOP\n"); 251a933c618SCyrill Gorcunov apic = &apic_noop; 25208306ce6SCyrill Gorcunov } 25308306ce6SCyrill Gorcunov 254f62bae50SIngo Molnar void native_apic_wait_icr_idle(void) 255f62bae50SIngo Molnar { 256f62bae50SIngo Molnar while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 257f62bae50SIngo Molnar cpu_relax(); 258f62bae50SIngo Molnar } 259f62bae50SIngo Molnar 260f62bae50SIngo Molnar u32 native_safe_apic_wait_icr_idle(void) 261f62bae50SIngo Molnar { 262f62bae50SIngo Molnar u32 send_status; 263f62bae50SIngo Molnar int timeout; 264f62bae50SIngo Molnar 265f62bae50SIngo Molnar timeout = 0; 266f62bae50SIngo Molnar do { 267f62bae50SIngo Molnar send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 268f62bae50SIngo Molnar if (!send_status) 269f62bae50SIngo Molnar break; 270b49d7d87SFernando Luis Vazquez Cao inc_irq_stat(icr_read_retry_count); 271f62bae50SIngo Molnar udelay(100); 272f62bae50SIngo Molnar } while (timeout++ < 1000); 273f62bae50SIngo Molnar 274f62bae50SIngo Molnar return send_status; 275f62bae50SIngo Molnar } 276f62bae50SIngo Molnar 277f62bae50SIngo Molnar void native_apic_icr_write(u32 low, u32 id) 278f62bae50SIngo Molnar { 279ea7bdc65SJan Kiszka unsigned long flags; 280ea7bdc65SJan Kiszka 281ea7bdc65SJan Kiszka local_irq_save(flags); 282bf348f66SSuravee Suthikulpanit apic_write(APIC_ICR2, SET_XAPIC_DEST_FIELD(id)); 283f62bae50SIngo Molnar apic_write(APIC_ICR, low); 284ea7bdc65SJan Kiszka local_irq_restore(flags); 285f62bae50SIngo Molnar } 286f62bae50SIngo Molnar 287f62bae50SIngo Molnar u64 native_apic_icr_read(void) 288f62bae50SIngo Molnar { 289f62bae50SIngo Molnar u32 icr1, icr2; 290f62bae50SIngo Molnar 291f62bae50SIngo Molnar icr2 = apic_read(APIC_ICR2); 292f62bae50SIngo Molnar icr1 = apic_read(APIC_ICR); 293f62bae50SIngo Molnar 294f62bae50SIngo Molnar return icr1 | ((u64)icr2 << 32); 295f62bae50SIngo Molnar } 296f62bae50SIngo Molnar 297f62bae50SIngo Molnar #ifdef CONFIG_X86_32 298f62bae50SIngo Molnar /** 299f62bae50SIngo Molnar * get_physical_broadcast - Get number of physical broadcast IDs 300f62bae50SIngo Molnar */ 301f62bae50SIngo Molnar int get_physical_broadcast(void) 302f62bae50SIngo Molnar { 303f62bae50SIngo Molnar return modern_apic() ? 0xff : 0xf; 304f62bae50SIngo Molnar } 305f62bae50SIngo Molnar #endif 306f62bae50SIngo Molnar 307f62bae50SIngo Molnar /** 308f62bae50SIngo Molnar * lapic_get_maxlvt - get the maximum number of local vector table entries 309f62bae50SIngo Molnar */ 310f62bae50SIngo Molnar int lapic_get_maxlvt(void) 311f62bae50SIngo Molnar { 312f62bae50SIngo Molnar /* 313f62bae50SIngo Molnar * - we always have APIC integrated on 64bit mode 314f62bae50SIngo Molnar * - 82489DXs do not report # of LVT entries 315f62bae50SIngo Molnar */ 316ae41a2a4SDou Liyang return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2; 317f62bae50SIngo Molnar } 318f62bae50SIngo Molnar 319f62bae50SIngo Molnar /* 320f62bae50SIngo Molnar * Local APIC timer 321f62bae50SIngo Molnar */ 322f62bae50SIngo Molnar 323f62bae50SIngo Molnar /* Clock divisor */ 324f62bae50SIngo Molnar #define APIC_DIVISOR 16 3251a9e4c56SNicolai Stange #define TSC_DIVISOR 8 326f62bae50SIngo Molnar 327daf3af47SThomas Gleixner /* i82489DX specific */ 328daf3af47SThomas Gleixner #define I82489DX_BASE_DIVIDER (((0x2) << 18)) 329daf3af47SThomas Gleixner 330f62bae50SIngo Molnar /* 331f62bae50SIngo Molnar * This function sets up the local APIC timer, with a timeout of 332f62bae50SIngo Molnar * 'clocks' APIC bus clock. During calibration we actually call 333f62bae50SIngo Molnar * this function twice on the boot CPU, once with a bogus timeout 334f62bae50SIngo Molnar * value, second time for real. The other (noncalibrating) CPUs 335f62bae50SIngo Molnar * call this function only once, with the real, calibrated value. 336f62bae50SIngo Molnar * 337f62bae50SIngo Molnar * We do reads before writes even if unnecessary, to get around the 338f62bae50SIngo Molnar * P5 APIC double write bug. 339f62bae50SIngo Molnar */ 340f62bae50SIngo Molnar static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 341f62bae50SIngo Molnar { 342f62bae50SIngo Molnar unsigned int lvtt_value, tmp_value; 343f62bae50SIngo Molnar 344f62bae50SIngo Molnar lvtt_value = LOCAL_TIMER_VECTOR; 345f62bae50SIngo Molnar if (!oneshot) 346f62bae50SIngo Molnar lvtt_value |= APIC_LVT_TIMER_PERIODIC; 347279f1461SSuresh Siddha else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 348279f1461SSuresh Siddha lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; 349279f1461SSuresh Siddha 350daf3af47SThomas Gleixner /* 351daf3af47SThomas Gleixner * The i82489DX APIC uses bit 18 and 19 for the base divider. This 352daf3af47SThomas Gleixner * overlaps with bit 18 on integrated APICs, but is not documented 353daf3af47SThomas Gleixner * in the SDM. No problem though. i82489DX equipped systems do not 354daf3af47SThomas Gleixner * have TSC deadline timer. 355daf3af47SThomas Gleixner */ 356f62bae50SIngo Molnar if (!lapic_is_integrated()) 357daf3af47SThomas Gleixner lvtt_value |= I82489DX_BASE_DIVIDER; 358f62bae50SIngo Molnar 359f62bae50SIngo Molnar if (!irqen) 360f62bae50SIngo Molnar lvtt_value |= APIC_LVT_MASKED; 361f62bae50SIngo Molnar 362f62bae50SIngo Molnar apic_write(APIC_LVTT, lvtt_value); 363f62bae50SIngo Molnar 364279f1461SSuresh Siddha if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { 3655d7c631dSShaohua Li /* 3665d7c631dSShaohua Li * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, 3675d7c631dSShaohua Li * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. 3685d7c631dSShaohua Li * According to Intel, MFENCE can do the serialization here. 3695d7c631dSShaohua Li */ 3705d7c631dSShaohua Li asm volatile("mfence" : : : "memory"); 371279f1461SSuresh Siddha return; 372279f1461SSuresh Siddha } 373279f1461SSuresh Siddha 374f62bae50SIngo Molnar /* 375f62bae50SIngo Molnar * Divide PICLK by 16 376f62bae50SIngo Molnar */ 377f62bae50SIngo Molnar tmp_value = apic_read(APIC_TDCR); 378f62bae50SIngo Molnar apic_write(APIC_TDCR, 379f62bae50SIngo Molnar (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 380f62bae50SIngo Molnar APIC_TDR_DIV_16); 381f62bae50SIngo Molnar 382f62bae50SIngo Molnar if (!oneshot) 383f62bae50SIngo Molnar apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 384f62bae50SIngo Molnar } 385f62bae50SIngo Molnar 386f62bae50SIngo Molnar /* 387a68c439bSRobert Richter * Setup extended LVT, AMD specific 388f62bae50SIngo Molnar * 389a68c439bSRobert Richter * Software should use the LVT offsets the BIOS provides. The offsets 390a68c439bSRobert Richter * are determined by the subsystems using it like those for MCE 391a68c439bSRobert Richter * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 392a68c439bSRobert Richter * are supported. Beginning with family 10h at least 4 offsets are 393a68c439bSRobert Richter * available. 394f62bae50SIngo Molnar * 395a68c439bSRobert Richter * Since the offsets must be consistent for all cores, we keep track 396a68c439bSRobert Richter * of the LVT offsets in software and reserve the offset for the same 397a68c439bSRobert Richter * vector also to be used on other cores. An offset is freed by 398a68c439bSRobert Richter * setting the entry to APIC_EILVT_MASKED. 399a68c439bSRobert Richter * 400a68c439bSRobert Richter * If the BIOS is right, there should be no conflicts. Otherwise a 401a68c439bSRobert Richter * "[Firmware Bug]: ..." error message is generated. However, if 402a68c439bSRobert Richter * software does not properly determines the offsets, it is not 403a68c439bSRobert Richter * necessarily a BIOS bug. 404f62bae50SIngo Molnar */ 405f62bae50SIngo Molnar 406a68c439bSRobert Richter static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 407f62bae50SIngo Molnar 408a68c439bSRobert Richter static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 409a68c439bSRobert Richter { 410a68c439bSRobert Richter return (old & APIC_EILVT_MASKED) 411a68c439bSRobert Richter || (new == APIC_EILVT_MASKED) 412a68c439bSRobert Richter || ((new & ~APIC_EILVT_MASKED) == old); 413a68c439bSRobert Richter } 414a68c439bSRobert Richter 415a68c439bSRobert Richter static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 416a68c439bSRobert Richter { 4178abc3122SRobert Richter unsigned int rsvd, vector; 418a68c439bSRobert Richter 419a68c439bSRobert Richter if (offset >= APIC_EILVT_NR_MAX) 420a68c439bSRobert Richter return ~0; 421a68c439bSRobert Richter 4228abc3122SRobert Richter rsvd = atomic_read(&eilvt_offsets[offset]); 423a68c439bSRobert Richter do { 4248abc3122SRobert Richter vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ 4258abc3122SRobert Richter if (vector && !eilvt_entry_is_changeable(vector, new)) 426a68c439bSRobert Richter /* may not change if vectors are different */ 427a68c439bSRobert Richter return rsvd; 428f96fb2dfSUros Bizjak } while (!atomic_try_cmpxchg(&eilvt_offsets[offset], &rsvd, new)); 429a68c439bSRobert Richter 430f96fb2dfSUros Bizjak rsvd = new & ~APIC_EILVT_MASKED; 4318abc3122SRobert Richter if (rsvd && rsvd != vector) 4328abc3122SRobert Richter pr_info("LVT offset %d assigned for vector 0x%02x\n", 4338abc3122SRobert Richter offset, rsvd); 4348abc3122SRobert Richter 435a68c439bSRobert Richter return new; 436a68c439bSRobert Richter } 437a68c439bSRobert Richter 438a68c439bSRobert Richter /* 439a68c439bSRobert Richter * If mask=1, the LVT entry does not generate interrupts while mask=0 440cbf74ceaSRobert Richter * enables the vector. See also the BKDGs. Must be called with 441cbf74ceaSRobert Richter * preemption disabled. 442a68c439bSRobert Richter */ 443a68c439bSRobert Richter 44427afdf20SRobert Richter int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 445a68c439bSRobert Richter { 446a68c439bSRobert Richter unsigned long reg = APIC_EILVTn(offset); 447a68c439bSRobert Richter unsigned int new, old, reserved; 448a68c439bSRobert Richter 449a68c439bSRobert Richter new = (mask << 16) | (msg_type << 8) | vector; 450a68c439bSRobert Richter old = apic_read(reg); 451a68c439bSRobert Richter reserved = reserve_eilvt_offset(offset, new); 452a68c439bSRobert Richter 453a68c439bSRobert Richter if (reserved != new) { 454eb48c9cbSRobert Richter pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 455eb48c9cbSRobert Richter "vector 0x%x, but the register is already in use for " 456eb48c9cbSRobert Richter "vector 0x%x on another cpu\n", 457eb48c9cbSRobert Richter smp_processor_id(), reg, offset, new, reserved); 458a68c439bSRobert Richter return -EINVAL; 459a68c439bSRobert Richter } 460a68c439bSRobert Richter 461a68c439bSRobert Richter if (!eilvt_entry_is_changeable(old, new)) { 462eb48c9cbSRobert Richter pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 463eb48c9cbSRobert Richter "vector 0x%x, but the register is already in use for " 464eb48c9cbSRobert Richter "vector 0x%x on this cpu\n", 465eb48c9cbSRobert Richter smp_processor_id(), reg, offset, new, old); 466a68c439bSRobert Richter return -EBUSY; 467a68c439bSRobert Richter } 468a68c439bSRobert Richter 469a68c439bSRobert Richter apic_write(reg, new); 470a68c439bSRobert Richter 471a68c439bSRobert Richter return 0; 472f62bae50SIngo Molnar } 47327afdf20SRobert Richter EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 474f62bae50SIngo Molnar 475f62bae50SIngo Molnar /* 476f62bae50SIngo Molnar * Program the next event, relative to now 477f62bae50SIngo Molnar */ 478f62bae50SIngo Molnar static int lapic_next_event(unsigned long delta, 479f62bae50SIngo Molnar struct clock_event_device *evt) 480f62bae50SIngo Molnar { 481f62bae50SIngo Molnar apic_write(APIC_TMICT, delta); 482f62bae50SIngo Molnar return 0; 483f62bae50SIngo Molnar } 484f62bae50SIngo Molnar 485279f1461SSuresh Siddha static int lapic_next_deadline(unsigned long delta, 486279f1461SSuresh Siddha struct clock_event_device *evt) 487279f1461SSuresh Siddha { 488279f1461SSuresh Siddha u64 tsc; 489279f1461SSuresh Siddha 49025a068b8SDave Hansen /* This MSR is special and need a special fence: */ 49125a068b8SDave Hansen weak_wrmsr_fence(); 49225a068b8SDave Hansen 4934ea1636bSAndy Lutomirski tsc = rdtsc(); 494279f1461SSuresh Siddha wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); 495279f1461SSuresh Siddha return 0; 496279f1461SSuresh Siddha } 497279f1461SSuresh Siddha 498b23d8e52SViresh Kumar static int lapic_timer_shutdown(struct clock_event_device *evt) 499f62bae50SIngo Molnar { 500f62bae50SIngo Molnar unsigned int v; 501f62bae50SIngo Molnar 502f62bae50SIngo Molnar /* Lapic used as dummy for broadcast ? */ 503f62bae50SIngo Molnar if (evt->features & CLOCK_EVT_FEAT_DUMMY) 504b23d8e52SViresh Kumar return 0; 505f62bae50SIngo Molnar 506f62bae50SIngo Molnar v = apic_read(APIC_LVTT); 507f62bae50SIngo Molnar v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 508f62bae50SIngo Molnar apic_write(APIC_LVTT, v); 5096f9b4100SAndreas Herrmann apic_write(APIC_TMICT, 0); 510b23d8e52SViresh Kumar return 0; 511f62bae50SIngo Molnar } 512f62bae50SIngo Molnar 513b23d8e52SViresh Kumar static inline int 514b23d8e52SViresh Kumar lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot) 515b23d8e52SViresh Kumar { 516b23d8e52SViresh Kumar /* Lapic used as dummy for broadcast ? */ 517b23d8e52SViresh Kumar if (evt->features & CLOCK_EVT_FEAT_DUMMY) 518b23d8e52SViresh Kumar return 0; 519b23d8e52SViresh Kumar 52052ae346bSDaniel Drake __setup_APIC_LVTT(lapic_timer_period, oneshot, 1); 521b23d8e52SViresh Kumar return 0; 522b23d8e52SViresh Kumar } 523b23d8e52SViresh Kumar 524b23d8e52SViresh Kumar static int lapic_timer_set_periodic(struct clock_event_device *evt) 525b23d8e52SViresh Kumar { 526b23d8e52SViresh Kumar return lapic_timer_set_periodic_oneshot(evt, false); 527b23d8e52SViresh Kumar } 528b23d8e52SViresh Kumar 529b23d8e52SViresh Kumar static int lapic_timer_set_oneshot(struct clock_event_device *evt) 530b23d8e52SViresh Kumar { 531b23d8e52SViresh Kumar return lapic_timer_set_periodic_oneshot(evt, true); 532f62bae50SIngo Molnar } 533f62bae50SIngo Molnar 534f62bae50SIngo Molnar /* 535f62bae50SIngo Molnar * Local APIC timer broadcast function 536f62bae50SIngo Molnar */ 537f62bae50SIngo Molnar static void lapic_timer_broadcast(const struct cpumask *mask) 538f62bae50SIngo Molnar { 539f62bae50SIngo Molnar #ifdef CONFIG_SMP 540f62bae50SIngo Molnar apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 541f62bae50SIngo Molnar #endif 542f62bae50SIngo Molnar } 543f62bae50SIngo Molnar 54425874a29SHenrik Kretzschmar 54525874a29SHenrik Kretzschmar /* 54625874a29SHenrik Kretzschmar * The local apic timer can be used for any function which is CPU local. 54725874a29SHenrik Kretzschmar */ 54825874a29SHenrik Kretzschmar static struct clock_event_device lapic_clockevent = { 54925874a29SHenrik Kretzschmar .name = "lapic", 550b23d8e52SViresh Kumar .features = CLOCK_EVT_FEAT_PERIODIC | 551b23d8e52SViresh Kumar CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP 552b23d8e52SViresh Kumar | CLOCK_EVT_FEAT_DUMMY, 55325874a29SHenrik Kretzschmar .shift = 32, 554b23d8e52SViresh Kumar .set_state_shutdown = lapic_timer_shutdown, 555b23d8e52SViresh Kumar .set_state_periodic = lapic_timer_set_periodic, 556b23d8e52SViresh Kumar .set_state_oneshot = lapic_timer_set_oneshot, 557914122c3SFrederic Weisbecker .set_state_oneshot_stopped = lapic_timer_shutdown, 55825874a29SHenrik Kretzschmar .set_next_event = lapic_next_event, 55925874a29SHenrik Kretzschmar .broadcast = lapic_timer_broadcast, 56025874a29SHenrik Kretzschmar .rating = 100, 56125874a29SHenrik Kretzschmar .irq = -1, 56225874a29SHenrik Kretzschmar }; 56325874a29SHenrik Kretzschmar static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 56425874a29SHenrik Kretzschmar 565c84cb373SThomas Gleixner static const struct x86_cpu_id deadline_match[] __initconst = { 56666abf238SBorislav Petkov X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(HASWELL_X, X86_STEPPINGS(0x2, 0x2), 0x3a), /* EP */ 56766abf238SBorislav Petkov X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(HASWELL_X, X86_STEPPINGS(0x4, 0x4), 0x0f), /* EX */ 56866abf238SBorislav Petkov 569adefe55eSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL( BROADWELL_X, 0x0b000020), 57066abf238SBorislav Petkov 57166abf238SBorislav Petkov X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x2, 0x2), 0x00000011), 57266abf238SBorislav Petkov X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x3, 0x3), 0x0700000e), 57366abf238SBorislav Petkov X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x4, 0x4), 0x0f00000c), 57466abf238SBorislav Petkov X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x5, 0x5), 0x0e000003), 57566abf238SBorislav Petkov 57666abf238SBorislav Petkov X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x3, 0x3), 0x01000136), 57766abf238SBorislav Petkov X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x4, 0x4), 0x02000014), 57866abf238SBorislav Petkov X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x5, 0xf), 0), 579bd9240a1SPeter Zijlstra 580adefe55eSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL( HASWELL, 0x22), 581adefe55eSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL( HASWELL_L, 0x20), 582adefe55eSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL( HASWELL_G, 0x17), 583bd9240a1SPeter Zijlstra 584adefe55eSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL( BROADWELL, 0x25), 585adefe55eSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL( BROADWELL_G, 0x17), 586bd9240a1SPeter Zijlstra 587adefe55eSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL( SKYLAKE_L, 0xb2), 588adefe55eSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL( SKYLAKE, 0xb2), 589bd9240a1SPeter Zijlstra 590adefe55eSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL( KABYLAKE_L, 0x52), 591adefe55eSThomas Gleixner X86_MATCH_INTEL_FAM6_MODEL( KABYLAKE, 0x52), 592bd9240a1SPeter Zijlstra 593bd9240a1SPeter Zijlstra {}, 594bd9240a1SPeter Zijlstra }; 595bd9240a1SPeter Zijlstra 596c84cb373SThomas Gleixner static __init bool apic_validate_deadline_timer(void) 597bd9240a1SPeter Zijlstra { 598594a30fbSHans de Goede const struct x86_cpu_id *m; 599bd9240a1SPeter Zijlstra u32 rev; 600bd9240a1SPeter Zijlstra 601c84cb373SThomas Gleixner if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 602c84cb373SThomas Gleixner return false; 603c84cb373SThomas Gleixner if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) 604c84cb373SThomas Gleixner return true; 605594a30fbSHans de Goede 606594a30fbSHans de Goede m = x86_match_cpu(deadline_match); 607bd9240a1SPeter Zijlstra if (!m) 608c84cb373SThomas Gleixner return true; 609bd9240a1SPeter Zijlstra 610bd9240a1SPeter Zijlstra rev = (u32)m->driver_data; 611bd9240a1SPeter Zijlstra 612bd9240a1SPeter Zijlstra if (boot_cpu_data.microcode >= rev) 613c84cb373SThomas Gleixner return true; 614bd9240a1SPeter Zijlstra 615bd9240a1SPeter Zijlstra setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 616bd9240a1SPeter Zijlstra pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; " 617bd9240a1SPeter Zijlstra "please update microcode to version: 0x%x (or later)\n", rev); 618c84cb373SThomas Gleixner return false; 619bd9240a1SPeter Zijlstra } 620bd9240a1SPeter Zijlstra 621f62bae50SIngo Molnar /* 622421f91d2SUwe Kleine-König * Setup the local APIC timer for this CPU. Copy the initialized values 623f62bae50SIngo Molnar * of the boot CPU and register the clock event in the framework. 624f62bae50SIngo Molnar */ 625148f9bb8SPaul Gortmaker static void setup_APIC_timer(void) 626f62bae50SIngo Molnar { 62789cbc767SChristoph Lameter struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 628f62bae50SIngo Molnar 629349c004eSChristoph Lameter if (this_cpu_has(X86_FEATURE_ARAT)) { 630db954b58SVenkatesh Pallipadi lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 631d9f6e12fSIngo Molnar /* Make LAPIC timer preferable over percpu HPET */ 632db954b58SVenkatesh Pallipadi lapic_clockevent.rating = 150; 633db954b58SVenkatesh Pallipadi } 634db954b58SVenkatesh Pallipadi 635f62bae50SIngo Molnar memcpy(levt, &lapic_clockevent, sizeof(*levt)); 636f62bae50SIngo Molnar levt->cpumask = cpumask_of(smp_processor_id()); 637f62bae50SIngo Molnar 638279f1461SSuresh Siddha if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 639c6e9f42bSPeter Zijlstra levt->name = "lapic-deadline"; 640279f1461SSuresh Siddha levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | 641279f1461SSuresh Siddha CLOCK_EVT_FEAT_DUMMY); 642279f1461SSuresh Siddha levt->set_next_event = lapic_next_deadline; 643279f1461SSuresh Siddha clockevents_config_and_register(levt, 6441a9e4c56SNicolai Stange tsc_khz * (1000 / TSC_DIVISOR), 645279f1461SSuresh Siddha 0xF, ~0UL); 646279f1461SSuresh Siddha } else 647f62bae50SIngo Molnar clockevents_register_device(levt); 648f62bae50SIngo Molnar } 649f62bae50SIngo Molnar 650f62bae50SIngo Molnar /* 6516731b0d6SNicolai Stange * Install the updated TSC frequency from recalibration at the TSC 6526731b0d6SNicolai Stange * deadline clockevent devices. 6536731b0d6SNicolai Stange */ 6546731b0d6SNicolai Stange static void __lapic_update_tsc_freq(void *info) 6556731b0d6SNicolai Stange { 6566731b0d6SNicolai Stange struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 6576731b0d6SNicolai Stange 6586731b0d6SNicolai Stange if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 6596731b0d6SNicolai Stange return; 6606731b0d6SNicolai Stange 6616731b0d6SNicolai Stange clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR)); 6626731b0d6SNicolai Stange } 6636731b0d6SNicolai Stange 6646731b0d6SNicolai Stange void lapic_update_tsc_freq(void) 6656731b0d6SNicolai Stange { 6666731b0d6SNicolai Stange /* 6676731b0d6SNicolai Stange * The clockevent device's ->mult and ->shift can both be 6686731b0d6SNicolai Stange * changed. In order to avoid races, schedule the frequency 6696731b0d6SNicolai Stange * update code on each CPU. 6706731b0d6SNicolai Stange */ 6716731b0d6SNicolai Stange on_each_cpu(__lapic_update_tsc_freq, NULL, 0); 6726731b0d6SNicolai Stange } 6736731b0d6SNicolai Stange 6746731b0d6SNicolai Stange /* 675f62bae50SIngo Molnar * In this functions we calibrate APIC bus clocks to the external timer. 676f62bae50SIngo Molnar * 677f62bae50SIngo Molnar * We want to do the calibration only once since we want to have local timer 678d9f6e12fSIngo Molnar * irqs synchronous. CPUs connected by the same APIC bus have the very same bus 679f62bae50SIngo Molnar * frequency. 680f62bae50SIngo Molnar * 681f62bae50SIngo Molnar * This was previously done by reading the PIT/HPET and waiting for a wrap 682f62bae50SIngo Molnar * around to find out, that a tick has elapsed. I have a box, where the PIT 683f62bae50SIngo Molnar * readout is broken, so it never gets out of the wait loop again. This was 684f62bae50SIngo Molnar * also reported by others. 685f62bae50SIngo Molnar * 686f62bae50SIngo Molnar * Monitoring the jiffies value is inaccurate and the clockevents 687f62bae50SIngo Molnar * infrastructure allows us to do a simple substitution of the interrupt 688f62bae50SIngo Molnar * handler. 689f62bae50SIngo Molnar * 690f62bae50SIngo Molnar * The calibration routine also uses the pm_timer when possible, as the PIT 691f62bae50SIngo Molnar * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 692f62bae50SIngo Molnar * back to normal later in the boot process). 693f62bae50SIngo Molnar */ 694f62bae50SIngo Molnar 695f62bae50SIngo Molnar #define LAPIC_CAL_LOOPS (HZ/10) 696f62bae50SIngo Molnar 697f62bae50SIngo Molnar static __initdata int lapic_cal_loops = -1; 698f62bae50SIngo Molnar static __initdata long lapic_cal_t1, lapic_cal_t2; 699f62bae50SIngo Molnar static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 700f62bae50SIngo Molnar static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 701f62bae50SIngo Molnar static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 702f62bae50SIngo Molnar 703f62bae50SIngo Molnar /* 704f897e60aSThomas Gleixner * Temporary interrupt handler and polled calibration function. 705f62bae50SIngo Molnar */ 706f62bae50SIngo Molnar static void __init lapic_cal_handler(struct clock_event_device *dev) 707f62bae50SIngo Molnar { 708f62bae50SIngo Molnar unsigned long long tsc = 0; 709f62bae50SIngo Molnar long tapic = apic_read(APIC_TMCCT); 710f62bae50SIngo Molnar unsigned long pm = acpi_pm_read_early(); 711f62bae50SIngo Molnar 71259e21e3dSBorislav Petkov if (boot_cpu_has(X86_FEATURE_TSC)) 7134ea1636bSAndy Lutomirski tsc = rdtsc(); 714f62bae50SIngo Molnar 715f62bae50SIngo Molnar switch (lapic_cal_loops++) { 716f62bae50SIngo Molnar case 0: 717f62bae50SIngo Molnar lapic_cal_t1 = tapic; 718f62bae50SIngo Molnar lapic_cal_tsc1 = tsc; 719f62bae50SIngo Molnar lapic_cal_pm1 = pm; 720f62bae50SIngo Molnar lapic_cal_j1 = jiffies; 721f62bae50SIngo Molnar break; 722f62bae50SIngo Molnar 723f62bae50SIngo Molnar case LAPIC_CAL_LOOPS: 724f62bae50SIngo Molnar lapic_cal_t2 = tapic; 725f62bae50SIngo Molnar lapic_cal_tsc2 = tsc; 726f62bae50SIngo Molnar if (pm < lapic_cal_pm1) 727f62bae50SIngo Molnar pm += ACPI_PM_OVRRUN; 728f62bae50SIngo Molnar lapic_cal_pm2 = pm; 729f62bae50SIngo Molnar lapic_cal_j2 = jiffies; 730f62bae50SIngo Molnar break; 731f62bae50SIngo Molnar } 732f62bae50SIngo Molnar } 733f62bae50SIngo Molnar 734f62bae50SIngo Molnar static int __init 735f62bae50SIngo Molnar calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 736f62bae50SIngo Molnar { 737f62bae50SIngo Molnar const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 738f62bae50SIngo Molnar const long pm_thresh = pm_100ms / 100; 739f62bae50SIngo Molnar unsigned long mult; 740f62bae50SIngo Molnar u64 res; 741f62bae50SIngo Molnar 742f62bae50SIngo Molnar #ifndef CONFIG_X86_PM_TIMER 743f62bae50SIngo Molnar return -1; 744f62bae50SIngo Molnar #endif 745f62bae50SIngo Molnar 746f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 747f62bae50SIngo Molnar 748f62bae50SIngo Molnar /* Check, if the PM timer is available */ 749f62bae50SIngo Molnar if (!deltapm) 750f62bae50SIngo Molnar return -1; 751f62bae50SIngo Molnar 752f62bae50SIngo Molnar mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 753f62bae50SIngo Molnar 754f62bae50SIngo Molnar if (deltapm > (pm_100ms - pm_thresh) && 755f62bae50SIngo Molnar deltapm < (pm_100ms + pm_thresh)) { 756f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 757f62bae50SIngo Molnar return 0; 758f62bae50SIngo Molnar } 759f62bae50SIngo Molnar 760f62bae50SIngo Molnar res = (((u64)deltapm) * mult) >> 22; 761f62bae50SIngo Molnar do_div(res, 1000000); 7628d3bcc44SKefeng Wang pr_warn("APIC calibration not consistent " 763f62bae50SIngo Molnar "with PM-Timer: %ldms instead of 100ms\n", (long)res); 764f62bae50SIngo Molnar 765f62bae50SIngo Molnar /* Correct the lapic counter value */ 766f62bae50SIngo Molnar res = (((u64)(*delta)) * pm_100ms); 767f62bae50SIngo Molnar do_div(res, deltapm); 768f62bae50SIngo Molnar pr_info("APIC delta adjusted to PM-Timer: " 769f62bae50SIngo Molnar "%lu (%ld)\n", (unsigned long)res, *delta); 770f62bae50SIngo Molnar *delta = (long)res; 771f62bae50SIngo Molnar 772f62bae50SIngo Molnar /* Correct the tsc counter value */ 77359e21e3dSBorislav Petkov if (boot_cpu_has(X86_FEATURE_TSC)) { 774f62bae50SIngo Molnar res = (((u64)(*deltatsc)) * pm_100ms); 775f62bae50SIngo Molnar do_div(res, deltapm); 776f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 777f62bae50SIngo Molnar "PM-Timer: %lu (%ld)\n", 778f62bae50SIngo Molnar (unsigned long)res, *deltatsc); 779f62bae50SIngo Molnar *deltatsc = (long)res; 780f62bae50SIngo Molnar } 781f62bae50SIngo Molnar 782f62bae50SIngo Molnar return 0; 783f62bae50SIngo Molnar } 784f62bae50SIngo Molnar 7856eb4f082SJacob Pan static int __init lapic_init_clockevent(void) 7866eb4f082SJacob Pan { 78752ae346bSDaniel Drake if (!lapic_timer_period) 7886eb4f082SJacob Pan return -1; 7896eb4f082SJacob Pan 7906eb4f082SJacob Pan /* Calculate the scaled math multiplication factor */ 79152ae346bSDaniel Drake lapic_clockevent.mult = div_sc(lapic_timer_period/APIC_DIVISOR, 7926eb4f082SJacob Pan TICK_NSEC, lapic_clockevent.shift); 7936eb4f082SJacob Pan lapic_clockevent.max_delta_ns = 7946eb4f082SJacob Pan clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 7956eb4f082SJacob Pan lapic_clockevent.max_delta_ticks = 0x7FFFFFFF; 7966eb4f082SJacob Pan lapic_clockevent.min_delta_ns = 7976eb4f082SJacob Pan clockevent_delta2ns(0xF, &lapic_clockevent); 7986eb4f082SJacob Pan lapic_clockevent.min_delta_ticks = 0xF; 7996eb4f082SJacob Pan 8006eb4f082SJacob Pan return 0; 8016eb4f082SJacob Pan } 8026eb4f082SJacob Pan 803c8c40767SThomas Gleixner bool __init apic_needs_pit(void) 804c8c40767SThomas Gleixner { 805c8c40767SThomas Gleixner /* 806c8c40767SThomas Gleixner * If the frequencies are not known, PIT is required for both TSC 807c8c40767SThomas Gleixner * and apic timer calibration. 808c8c40767SThomas Gleixner */ 809c8c40767SThomas Gleixner if (!tsc_khz || !cpu_khz) 810c8c40767SThomas Gleixner return true; 811c8c40767SThomas Gleixner 81297992387SThomas Gleixner /* Is there an APIC at all or is it disabled? */ 813*49062454SThomas Gleixner if (!boot_cpu_has(X86_FEATURE_APIC) || apic_is_disabled) 81497992387SThomas Gleixner return true; 81597992387SThomas Gleixner 81697992387SThomas Gleixner /* 81797992387SThomas Gleixner * If interrupt delivery mode is legacy PIC or virtual wire without 81897992387SThomas Gleixner * configuration, the local APIC timer wont be set up. Make sure 81997992387SThomas Gleixner * that the PIT is initialized. 82097992387SThomas Gleixner */ 82197992387SThomas Gleixner if (apic_intr_mode == APIC_PIC || 82297992387SThomas Gleixner apic_intr_mode == APIC_VIRTUAL_WIRE_NO_CONFIG) 823c8c40767SThomas Gleixner return true; 824c8c40767SThomas Gleixner 825afa8b475SJan Stancek /* Virt guests may lack ARAT, but still have DEADLINE */ 826afa8b475SJan Stancek if (!boot_cpu_has(X86_FEATURE_ARAT)) 827afa8b475SJan Stancek return true; 828afa8b475SJan Stancek 829c8c40767SThomas Gleixner /* Deadline timer is based on TSC so no further PIT action required */ 830c8c40767SThomas Gleixner if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 831c8c40767SThomas Gleixner return false; 832c8c40767SThomas Gleixner 833c8c40767SThomas Gleixner /* APIC timer disabled? */ 834c8c40767SThomas Gleixner if (disable_apic_timer) 835c8c40767SThomas Gleixner return true; 836c8c40767SThomas Gleixner /* 837c8c40767SThomas Gleixner * The APIC timer frequency is known already, no PIT calibration 838c8c40767SThomas Gleixner * required. If unknown, let the PIT be initialized. 839c8c40767SThomas Gleixner */ 840c8c40767SThomas Gleixner return lapic_timer_period == 0; 841c8c40767SThomas Gleixner } 842c8c40767SThomas Gleixner 843f62bae50SIngo Molnar static int __init calibrate_APIC_clock(void) 844f62bae50SIngo Molnar { 84589cbc767SChristoph Lameter struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 846f897e60aSThomas Gleixner u64 tsc_perj = 0, tsc_start = 0; 847f897e60aSThomas Gleixner unsigned long jif_start; 848f62bae50SIngo Molnar unsigned long deltaj; 849f62bae50SIngo Molnar long delta, deltatsc; 850f62bae50SIngo Molnar int pm_referenced = 0; 851f62bae50SIngo Molnar 8526eb4f082SJacob Pan if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 8536eb4f082SJacob Pan return 0; 8546eb4f082SJacob Pan 8556eb4f082SJacob Pan /* 8566eb4f082SJacob Pan * Check if lapic timer has already been calibrated by platform 8576eb4f082SJacob Pan * specific routine, such as tsc calibration code. If so just fill 8581ade93efSJacob Pan * in the clockevent structure and return. 8591ade93efSJacob Pan */ 8606eb4f082SJacob Pan if (!lapic_init_clockevent()) { 8611ade93efSJacob Pan apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", 86252ae346bSDaniel Drake lapic_timer_period); 8636eb4f082SJacob Pan /* 8646eb4f082SJacob Pan * Direct calibration methods must have an always running 8656eb4f082SJacob Pan * local APIC timer, no need for broadcast timer. 8666eb4f082SJacob Pan */ 8671ade93efSJacob Pan lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 8681ade93efSJacob Pan return 0; 8691ade93efSJacob Pan } 8701ade93efSJacob Pan 871279f1461SSuresh Siddha apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 872279f1461SSuresh Siddha "calibrating APIC timer ...\n"); 873279f1461SSuresh Siddha 874f897e60aSThomas Gleixner /* 875f897e60aSThomas Gleixner * There are platforms w/o global clockevent devices. Instead of 876f897e60aSThomas Gleixner * making the calibration conditional on that, use a polling based 877f897e60aSThomas Gleixner * approach everywhere. 878f897e60aSThomas Gleixner */ 879f62bae50SIngo Molnar local_irq_disable(); 880f62bae50SIngo Molnar 881f62bae50SIngo Molnar /* 882f62bae50SIngo Molnar * Setup the APIC counter to maximum. There is no way the lapic 883f62bae50SIngo Molnar * can underflow in the 100ms detection time frame 884f62bae50SIngo Molnar */ 885f62bae50SIngo Molnar __setup_APIC_LVTT(0xffffffff, 0, 0); 886f62bae50SIngo Molnar 887f897e60aSThomas Gleixner /* 888f897e60aSThomas Gleixner * Methods to terminate the calibration loop: 889f897e60aSThomas Gleixner * 1) Global clockevent if available (jiffies) 890f897e60aSThomas Gleixner * 2) TSC if available and frequency is known 891f897e60aSThomas Gleixner */ 892f897e60aSThomas Gleixner jif_start = READ_ONCE(jiffies); 893f897e60aSThomas Gleixner 894f897e60aSThomas Gleixner if (tsc_khz) { 895f897e60aSThomas Gleixner tsc_start = rdtsc(); 896f897e60aSThomas Gleixner tsc_perj = div_u64((u64)tsc_khz * 1000, HZ); 897f897e60aSThomas Gleixner } 898f897e60aSThomas Gleixner 899f897e60aSThomas Gleixner /* 900f897e60aSThomas Gleixner * Enable interrupts so the tick can fire, if a global 901f897e60aSThomas Gleixner * clockevent device is available 902f897e60aSThomas Gleixner */ 903f62bae50SIngo Molnar local_irq_enable(); 904f62bae50SIngo Molnar 905f897e60aSThomas Gleixner while (lapic_cal_loops <= LAPIC_CAL_LOOPS) { 906f897e60aSThomas Gleixner /* Wait for a tick to elapse */ 907f897e60aSThomas Gleixner while (1) { 908f897e60aSThomas Gleixner if (tsc_khz) { 909f897e60aSThomas Gleixner u64 tsc_now = rdtsc(); 910f897e60aSThomas Gleixner if ((tsc_now - tsc_start) >= tsc_perj) { 911f897e60aSThomas Gleixner tsc_start += tsc_perj; 912f897e60aSThomas Gleixner break; 913f897e60aSThomas Gleixner } 914f897e60aSThomas Gleixner } else { 915f897e60aSThomas Gleixner unsigned long jif_now = READ_ONCE(jiffies); 916f897e60aSThomas Gleixner 917f897e60aSThomas Gleixner if (time_after(jif_now, jif_start)) { 918f897e60aSThomas Gleixner jif_start = jif_now; 919f897e60aSThomas Gleixner break; 920f897e60aSThomas Gleixner } 921f897e60aSThomas Gleixner } 922f62bae50SIngo Molnar cpu_relax(); 923f897e60aSThomas Gleixner } 924f897e60aSThomas Gleixner 925f897e60aSThomas Gleixner /* Invoke the calibration routine */ 926f897e60aSThomas Gleixner local_irq_disable(); 927f897e60aSThomas Gleixner lapic_cal_handler(NULL); 928f897e60aSThomas Gleixner local_irq_enable(); 929f897e60aSThomas Gleixner } 930f62bae50SIngo Molnar 931f62bae50SIngo Molnar local_irq_disable(); 932f62bae50SIngo Molnar 933f62bae50SIngo Molnar /* Build delta t1-t2 as apic timer counts down */ 934f62bae50SIngo Molnar delta = lapic_cal_t1 - lapic_cal_t2; 935f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 936f62bae50SIngo Molnar 937f62bae50SIngo Molnar deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 938f62bae50SIngo Molnar 939f62bae50SIngo Molnar /* we trust the PM based calibration if possible */ 940f62bae50SIngo Molnar pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 941f62bae50SIngo Molnar &delta, &deltatsc); 942f62bae50SIngo Molnar 94352ae346bSDaniel Drake lapic_timer_period = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 9446eb4f082SJacob Pan lapic_init_clockevent(); 945f62bae50SIngo Molnar 946f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 947411462f6SThomas Gleixner apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 948f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 94952ae346bSDaniel Drake lapic_timer_period); 950f62bae50SIngo Molnar 95159e21e3dSBorislav Petkov if (boot_cpu_has(X86_FEATURE_TSC)) { 952f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 953f62bae50SIngo Molnar "%ld.%04ld MHz.\n", 954f62bae50SIngo Molnar (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 955f62bae50SIngo Molnar (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 956f62bae50SIngo Molnar } 957f62bae50SIngo Molnar 958f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 959f62bae50SIngo Molnar "%u.%04u MHz.\n", 96052ae346bSDaniel Drake lapic_timer_period / (1000000 / HZ), 96152ae346bSDaniel Drake lapic_timer_period % (1000000 / HZ)); 962f62bae50SIngo Molnar 963f62bae50SIngo Molnar /* 964f62bae50SIngo Molnar * Do a sanity check on the APIC calibration result 965f62bae50SIngo Molnar */ 96652ae346bSDaniel Drake if (lapic_timer_period < (1000000 / HZ)) { 967f62bae50SIngo Molnar local_irq_enable(); 9688d3bcc44SKefeng Wang pr_warn("APIC frequency too slow, disabling apic timer\n"); 969f62bae50SIngo Molnar return -1; 970f62bae50SIngo Molnar } 971f62bae50SIngo Molnar 972f62bae50SIngo Molnar levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 973f62bae50SIngo Molnar 974f62bae50SIngo Molnar /* 975f897e60aSThomas Gleixner * PM timer calibration failed or not turned on so lets try APIC 976f897e60aSThomas Gleixner * timer based calibration, if a global clockevent device is 977f897e60aSThomas Gleixner * available. 978f62bae50SIngo Molnar */ 979f897e60aSThomas Gleixner if (!pm_referenced && global_clock_event) { 980f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 981f62bae50SIngo Molnar 982f62bae50SIngo Molnar /* 983f62bae50SIngo Molnar * Setup the apic timer manually 984f62bae50SIngo Molnar */ 985f62bae50SIngo Molnar levt->event_handler = lapic_cal_handler; 986b23d8e52SViresh Kumar lapic_timer_set_periodic(levt); 987f62bae50SIngo Molnar lapic_cal_loops = -1; 988f62bae50SIngo Molnar 989f62bae50SIngo Molnar /* Let the interrupts run */ 990f62bae50SIngo Molnar local_irq_enable(); 991f62bae50SIngo Molnar 992f62bae50SIngo Molnar while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 993f62bae50SIngo Molnar cpu_relax(); 994f62bae50SIngo Molnar 995f62bae50SIngo Molnar /* Stop the lapic timer */ 996c948c260SThomas Gleixner local_irq_disable(); 997b23d8e52SViresh Kumar lapic_timer_shutdown(levt); 998f62bae50SIngo Molnar 999f62bae50SIngo Molnar /* Jiffies delta */ 1000f62bae50SIngo Molnar deltaj = lapic_cal_j2 - lapic_cal_j1; 1001f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 1002f62bae50SIngo Molnar 1003f62bae50SIngo Molnar /* Check, if the jiffies result is consistent */ 1004f62bae50SIngo Molnar if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 1005f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 1006f62bae50SIngo Molnar else 1007f62bae50SIngo Molnar levt->features |= CLOCK_EVT_FEAT_DUMMY; 1008c948c260SThomas Gleixner } 1009f62bae50SIngo Molnar local_irq_enable(); 1010f62bae50SIngo Molnar 1011f62bae50SIngo Molnar if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 10128d3bcc44SKefeng Wang pr_warn("APIC timer disabled due to verification failure\n"); 1013f62bae50SIngo Molnar return -1; 1014f62bae50SIngo Molnar } 1015f62bae50SIngo Molnar 1016f62bae50SIngo Molnar return 0; 1017f62bae50SIngo Molnar } 1018f62bae50SIngo Molnar 1019f62bae50SIngo Molnar /* 1020f62bae50SIngo Molnar * Setup the boot APIC 1021f62bae50SIngo Molnar * 1022f62bae50SIngo Molnar * Calibrate and verify the result. 1023f62bae50SIngo Molnar */ 1024f62bae50SIngo Molnar void __init setup_boot_APIC_clock(void) 1025f62bae50SIngo Molnar { 1026f62bae50SIngo Molnar /* 1027f62bae50SIngo Molnar * The local apic timer can be disabled via the kernel 1028f62bae50SIngo Molnar * commandline or from the CPU detection code. Register the lapic 1029f62bae50SIngo Molnar * timer as a dummy clock event source on SMP systems, so the 1030f62bae50SIngo Molnar * broadcast mechanism is used. On UP systems simply ignore it. 1031f62bae50SIngo Molnar */ 1032f62bae50SIngo Molnar if (disable_apic_timer) { 1033f62bae50SIngo Molnar pr_info("Disabling APIC timer\n"); 1034f62bae50SIngo Molnar /* No broadcast on UP ! */ 1035f62bae50SIngo Molnar if (num_possible_cpus() > 1) { 1036f62bae50SIngo Molnar lapic_clockevent.mult = 1; 1037f62bae50SIngo Molnar setup_APIC_timer(); 1038f62bae50SIngo Molnar } 1039f62bae50SIngo Molnar return; 1040f62bae50SIngo Molnar } 1041f62bae50SIngo Molnar 1042f62bae50SIngo Molnar if (calibrate_APIC_clock()) { 1043f62bae50SIngo Molnar /* No broadcast on UP ! */ 1044f62bae50SIngo Molnar if (num_possible_cpus() > 1) 1045f62bae50SIngo Molnar setup_APIC_timer(); 1046f62bae50SIngo Molnar return; 1047f62bae50SIngo Molnar } 1048f62bae50SIngo Molnar 1049f62bae50SIngo Molnar /* 1050f62bae50SIngo Molnar * If nmi_watchdog is set to IO_APIC, we need the 1051f62bae50SIngo Molnar * PIT/HPET going. Otherwise register lapic as a dummy 1052f62bae50SIngo Molnar * device. 1053f62bae50SIngo Molnar */ 1054f62bae50SIngo Molnar lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 1055f62bae50SIngo Molnar 1056f62bae50SIngo Molnar /* Setup the lapic or request the broadcast */ 1057f62bae50SIngo Molnar setup_APIC_timer(); 105807c94a38SBorislav Petkov amd_e400_c1e_apic_setup(); 1059f62bae50SIngo Molnar } 1060f62bae50SIngo Molnar 1061148f9bb8SPaul Gortmaker void setup_secondary_APIC_clock(void) 1062f62bae50SIngo Molnar { 1063f62bae50SIngo Molnar setup_APIC_timer(); 106407c94a38SBorislav Petkov amd_e400_c1e_apic_setup(); 1065f62bae50SIngo Molnar } 1066f62bae50SIngo Molnar 1067f62bae50SIngo Molnar /* 1068f62bae50SIngo Molnar * The guts of the apic timer interrupt 1069f62bae50SIngo Molnar */ 1070f62bae50SIngo Molnar static void local_apic_timer_interrupt(void) 1071f62bae50SIngo Molnar { 10723bec6defSThomas Gleixner struct clock_event_device *evt = this_cpu_ptr(&lapic_events); 1073f62bae50SIngo Molnar 1074f62bae50SIngo Molnar /* 1075f62bae50SIngo Molnar * Normally we should not be here till LAPIC has been initialized but 1076f62bae50SIngo Molnar * in some cases like kdump, its possible that there is a pending LAPIC 1077f62bae50SIngo Molnar * timer interrupt from previous kernel's context and is delivered in 1078f62bae50SIngo Molnar * new kernel the moment interrupts are enabled. 1079f62bae50SIngo Molnar * 1080f62bae50SIngo Molnar * Interrupts are enabled early and LAPIC is setup much later, hence 1081f62bae50SIngo Molnar * its possible that when we get here evt->event_handler is NULL. 1082f62bae50SIngo Molnar * Check for event_handler being NULL and discard the interrupt as 1083f62bae50SIngo Molnar * spurious. 1084f62bae50SIngo Molnar */ 1085f62bae50SIngo Molnar if (!evt->event_handler) { 10868d3bcc44SKefeng Wang pr_warn("Spurious LAPIC timer interrupt on cpu %d\n", 10873bec6defSThomas Gleixner smp_processor_id()); 1088f62bae50SIngo Molnar /* Switch it off */ 1089b23d8e52SViresh Kumar lapic_timer_shutdown(evt); 1090f62bae50SIngo Molnar return; 1091f62bae50SIngo Molnar } 1092f62bae50SIngo Molnar 1093f62bae50SIngo Molnar /* 1094f62bae50SIngo Molnar * the NMI deadlock-detector uses this. 1095f62bae50SIngo Molnar */ 1096f62bae50SIngo Molnar inc_irq_stat(apic_timer_irqs); 1097f62bae50SIngo Molnar 1098f62bae50SIngo Molnar evt->event_handler(evt); 1099f62bae50SIngo Molnar } 1100f62bae50SIngo Molnar 1101f62bae50SIngo Molnar /* 1102f62bae50SIngo Molnar * Local APIC timer interrupt. This is the most natural way for doing 1103f62bae50SIngo Molnar * local interrupts, but local timer interrupts can be emulated by 1104f62bae50SIngo Molnar * broadcast interrupts too. [in case the hw doesn't support APIC timers] 1105f62bae50SIngo Molnar * 1106f62bae50SIngo Molnar * [ if a single-CPU system runs an SMP kernel then we call the local 1107f62bae50SIngo Molnar * interrupt as well. Thus we cannot inline the local irq ... ] 1108f62bae50SIngo Molnar */ 1109db0338eeSThomas Gleixner DEFINE_IDTENTRY_SYSVEC(sysvec_apic_timer_interrupt) 1110f62bae50SIngo Molnar { 1111f62bae50SIngo Molnar struct pt_regs *old_regs = set_irq_regs(regs); 1112f62bae50SIngo Molnar 1113db0338eeSThomas Gleixner ack_APIC_irq(); 1114cf910e83SSeiji Aguchi trace_local_timer_entry(LOCAL_TIMER_VECTOR); 1115cf910e83SSeiji Aguchi local_apic_timer_interrupt(); 1116cf910e83SSeiji Aguchi trace_local_timer_exit(LOCAL_TIMER_VECTOR); 1117f62bae50SIngo Molnar 1118f62bae50SIngo Molnar set_irq_regs(old_regs); 1119f62bae50SIngo Molnar } 1120f62bae50SIngo Molnar 1121f62bae50SIngo Molnar /* 1122f62bae50SIngo Molnar * Local APIC start and shutdown 1123f62bae50SIngo Molnar */ 1124f62bae50SIngo Molnar 1125f62bae50SIngo Molnar /** 1126f62bae50SIngo Molnar * clear_local_APIC - shutdown the local APIC 1127f62bae50SIngo Molnar * 1128f62bae50SIngo Molnar * This is called, when a CPU is disabled and before rebooting, so the state of 1129f62bae50SIngo Molnar * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 1130f62bae50SIngo Molnar * leftovers during boot. 1131f62bae50SIngo Molnar */ 1132f62bae50SIngo Molnar void clear_local_APIC(void) 1133f62bae50SIngo Molnar { 1134f62bae50SIngo Molnar int maxlvt; 1135f62bae50SIngo Molnar u32 v; 1136f62bae50SIngo Molnar 1137f62bae50SIngo Molnar /* APIC hasn't been mapped yet */ 1138fc1edaf9SSuresh Siddha if (!x2apic_mode && !apic_phys) 1139f62bae50SIngo Molnar return; 1140f62bae50SIngo Molnar 1141f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 1142f62bae50SIngo Molnar /* 1143f62bae50SIngo Molnar * Masking an LVT entry can trigger a local APIC error 1144f62bae50SIngo Molnar * if the vector is zero. Mask LVTERR first to prevent this. 1145f62bae50SIngo Molnar */ 1146f62bae50SIngo Molnar if (maxlvt >= 3) { 1147f62bae50SIngo Molnar v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 1148f62bae50SIngo Molnar apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 1149f62bae50SIngo Molnar } 1150f62bae50SIngo Molnar /* 1151f62bae50SIngo Molnar * Careful: we have to set masks only first to deassert 1152f62bae50SIngo Molnar * any level-triggered sources. 1153f62bae50SIngo Molnar */ 1154f62bae50SIngo Molnar v = apic_read(APIC_LVTT); 1155f62bae50SIngo Molnar apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 1156f62bae50SIngo Molnar v = apic_read(APIC_LVT0); 1157f62bae50SIngo Molnar apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 1158f62bae50SIngo Molnar v = apic_read(APIC_LVT1); 1159f62bae50SIngo Molnar apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 1160f62bae50SIngo Molnar if (maxlvt >= 4) { 1161f62bae50SIngo Molnar v = apic_read(APIC_LVTPC); 1162f62bae50SIngo Molnar apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 1163f62bae50SIngo Molnar } 1164f62bae50SIngo Molnar 1165f62bae50SIngo Molnar /* lets not touch this if we didn't frob it */ 11664efc0670SAndi Kleen #ifdef CONFIG_X86_THERMAL_VECTOR 1167f62bae50SIngo Molnar if (maxlvt >= 5) { 1168f62bae50SIngo Molnar v = apic_read(APIC_LVTTHMR); 1169f62bae50SIngo Molnar apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 1170f62bae50SIngo Molnar } 1171f62bae50SIngo Molnar #endif 1172638bee71SH. Peter Anvin #ifdef CONFIG_X86_MCE_INTEL 1173638bee71SH. Peter Anvin if (maxlvt >= 6) { 1174638bee71SH. Peter Anvin v = apic_read(APIC_LVTCMCI); 1175638bee71SH. Peter Anvin if (!(v & APIC_LVT_MASKED)) 1176638bee71SH. Peter Anvin apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 1177638bee71SH. Peter Anvin } 1178638bee71SH. Peter Anvin #endif 1179638bee71SH. Peter Anvin 1180f62bae50SIngo Molnar /* 1181f62bae50SIngo Molnar * Clean APIC state for other OSs: 1182f62bae50SIngo Molnar */ 1183f62bae50SIngo Molnar apic_write(APIC_LVTT, APIC_LVT_MASKED); 1184f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_LVT_MASKED); 1185f62bae50SIngo Molnar apic_write(APIC_LVT1, APIC_LVT_MASKED); 1186f62bae50SIngo Molnar if (maxlvt >= 3) 1187f62bae50SIngo Molnar apic_write(APIC_LVTERR, APIC_LVT_MASKED); 1188f62bae50SIngo Molnar if (maxlvt >= 4) 1189f62bae50SIngo Molnar apic_write(APIC_LVTPC, APIC_LVT_MASKED); 1190f62bae50SIngo Molnar 1191f62bae50SIngo Molnar /* Integrated APIC (!82489DX) ? */ 1192f62bae50SIngo Molnar if (lapic_is_integrated()) { 1193f62bae50SIngo Molnar if (maxlvt > 3) 1194f62bae50SIngo Molnar /* Clear ESR due to Pentium errata 3AP and 11AP */ 1195f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1196f62bae50SIngo Molnar apic_read(APIC_ESR); 1197f62bae50SIngo Molnar } 1198f62bae50SIngo Molnar } 1199f62bae50SIngo Molnar 1200f62bae50SIngo Molnar /** 120160dcaad5SThomas Gleixner * apic_soft_disable - Clears and software disables the local APIC on hotplug 120260dcaad5SThomas Gleixner * 120360dcaad5SThomas Gleixner * Contrary to disable_local_APIC() this does not touch the enable bit in 120460dcaad5SThomas Gleixner * MSR_IA32_APICBASE. Clearing that bit on systems based on the 3 wire APIC 120560dcaad5SThomas Gleixner * bus would require a hardware reset as the APIC would lose track of bus 120660dcaad5SThomas Gleixner * arbitration. On systems with FSB delivery APICBASE could be disabled, 120760dcaad5SThomas Gleixner * but it has to be guaranteed that no interrupt is sent to the APIC while 120860dcaad5SThomas Gleixner * in that state and it's not clear from the SDM whether it still responds 120960dcaad5SThomas Gleixner * to INIT/SIPI messages. Stay on the safe side and use software disable. 121060dcaad5SThomas Gleixner */ 121160dcaad5SThomas Gleixner void apic_soft_disable(void) 121260dcaad5SThomas Gleixner { 121360dcaad5SThomas Gleixner u32 value; 121460dcaad5SThomas Gleixner 121560dcaad5SThomas Gleixner clear_local_APIC(); 121660dcaad5SThomas Gleixner 121760dcaad5SThomas Gleixner /* Soft disable APIC (implies clearing of registers for 82489DX!). */ 121860dcaad5SThomas Gleixner value = apic_read(APIC_SPIV); 121960dcaad5SThomas Gleixner value &= ~APIC_SPIV_APIC_ENABLED; 122060dcaad5SThomas Gleixner apic_write(APIC_SPIV, value); 122160dcaad5SThomas Gleixner } 122260dcaad5SThomas Gleixner 122360dcaad5SThomas Gleixner /** 1224f62bae50SIngo Molnar * disable_local_APIC - clear and disable the local APIC 1225f62bae50SIngo Molnar */ 1226f62bae50SIngo Molnar void disable_local_APIC(void) 1227f62bae50SIngo Molnar { 1228f62bae50SIngo Molnar /* APIC hasn't been mapped yet */ 1229fd19dce7SYinghai Lu if (!x2apic_mode && !apic_phys) 1230f62bae50SIngo Molnar return; 1231f62bae50SIngo Molnar 123260dcaad5SThomas Gleixner apic_soft_disable(); 1233f62bae50SIngo Molnar 1234f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1235f62bae50SIngo Molnar /* 1236f62bae50SIngo Molnar * When LAPIC was disabled by the BIOS and enabled by the kernel, 1237f62bae50SIngo Molnar * restore the disabled state. 1238f62bae50SIngo Molnar */ 1239f62bae50SIngo Molnar if (enabled_via_apicbase) { 1240f62bae50SIngo Molnar unsigned int l, h; 1241f62bae50SIngo Molnar 1242f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, l, h); 1243f62bae50SIngo Molnar l &= ~MSR_IA32_APICBASE_ENABLE; 1244f62bae50SIngo Molnar wrmsr(MSR_IA32_APICBASE, l, h); 1245f62bae50SIngo Molnar } 1246f62bae50SIngo Molnar #endif 1247f62bae50SIngo Molnar } 1248f62bae50SIngo Molnar 1249f62bae50SIngo Molnar /* 1250f62bae50SIngo Molnar * If Linux enabled the LAPIC against the BIOS default disable it down before 1251f62bae50SIngo Molnar * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 1252f62bae50SIngo Molnar * not power-off. Additionally clear all LVT entries before disable_local_APIC 1253f62bae50SIngo Molnar * for the case where Linux didn't enable the LAPIC. 1254f62bae50SIngo Molnar */ 1255f62bae50SIngo Molnar void lapic_shutdown(void) 1256f62bae50SIngo Molnar { 1257f62bae50SIngo Molnar unsigned long flags; 1258f62bae50SIngo Molnar 125993984fbdSBorislav Petkov if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) 1260f62bae50SIngo Molnar return; 1261f62bae50SIngo Molnar 1262f62bae50SIngo Molnar local_irq_save(flags); 1263f62bae50SIngo Molnar 1264f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1265f62bae50SIngo Molnar if (!enabled_via_apicbase) 1266f62bae50SIngo Molnar clear_local_APIC(); 1267f62bae50SIngo Molnar else 1268f62bae50SIngo Molnar #endif 1269f62bae50SIngo Molnar disable_local_APIC(); 1270f62bae50SIngo Molnar 1271f62bae50SIngo Molnar 1272f62bae50SIngo Molnar local_irq_restore(flags); 1273f62bae50SIngo Molnar } 1274f62bae50SIngo Molnar 1275f62bae50SIngo Molnar /** 1276f62bae50SIngo Molnar * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1277f62bae50SIngo Molnar */ 1278f62bae50SIngo Molnar void __init sync_Arb_IDs(void) 1279f62bae50SIngo Molnar { 1280f62bae50SIngo Molnar /* 1281f62bae50SIngo Molnar * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1282f62bae50SIngo Molnar * needed on AMD. 1283f62bae50SIngo Molnar */ 1284f62bae50SIngo Molnar if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1285f62bae50SIngo Molnar return; 1286f62bae50SIngo Molnar 1287f62bae50SIngo Molnar /* 1288f62bae50SIngo Molnar * Wait for idle. 1289f62bae50SIngo Molnar */ 1290f62bae50SIngo Molnar apic_wait_icr_idle(); 1291f62bae50SIngo Molnar 1292f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1293f62bae50SIngo Molnar apic_write(APIC_ICR, APIC_DEST_ALLINC | 1294f62bae50SIngo Molnar APIC_INT_LEVELTRIG | APIC_DM_INIT); 1295f62bae50SIngo Molnar } 1296f62bae50SIngo Molnar 12976444b40eSSean Christopherson enum apic_intr_mode_id apic_intr_mode __ro_after_init; 12980114a8e8SDou Liyang 129997992387SThomas Gleixner static int __init __apic_intr_mode_select(void) 1300f62bae50SIngo Molnar { 13010114a8e8SDou Liyang /* Check kernel option */ 1302*49062454SThomas Gleixner if (apic_is_disabled) { 13030114a8e8SDou Liyang pr_info("APIC disabled via kernel command line\n"); 13040114a8e8SDou Liyang return APIC_PIC; 13050114a8e8SDou Liyang } 1306f62bae50SIngo Molnar 13070114a8e8SDou Liyang /* Check BIOS */ 13080114a8e8SDou Liyang #ifdef CONFIG_X86_64 13090114a8e8SDou Liyang /* On 64-bit, the APIC must be integrated, Check local APIC only */ 13100114a8e8SDou Liyang if (!boot_cpu_has(X86_FEATURE_APIC)) { 1311*49062454SThomas Gleixner apic_is_disabled = true; 13120114a8e8SDou Liyang pr_info("APIC disabled by BIOS\n"); 13130114a8e8SDou Liyang return APIC_PIC; 13140114a8e8SDou Liyang } 13150114a8e8SDou Liyang #else 13160114a8e8SDou Liyang /* On 32-bit, the APIC may be integrated APIC or 82489DX */ 1317f62bae50SIngo Molnar 13180114a8e8SDou Liyang /* Neither 82489DX nor integrated APIC ? */ 13190114a8e8SDou Liyang if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) { 1320*49062454SThomas Gleixner apic_is_disabled = true; 13210114a8e8SDou Liyang return APIC_PIC; 13220114a8e8SDou Liyang } 1323f62bae50SIngo Molnar 13240114a8e8SDou Liyang /* If the BIOS pretends there is an integrated APIC ? */ 13250114a8e8SDou Liyang if (!boot_cpu_has(X86_FEATURE_APIC) && 13260114a8e8SDou Liyang APIC_INTEGRATED(boot_cpu_apic_version)) { 1327*49062454SThomas Gleixner apic_is_disabled = true; 13280114a8e8SDou Liyang pr_err(FW_BUG "Local APIC %d not detected, force emulation\n", 13290114a8e8SDou Liyang boot_cpu_physical_apicid); 13300114a8e8SDou Liyang return APIC_PIC; 13310114a8e8SDou Liyang } 1332f62bae50SIngo Molnar #endif 1333f62bae50SIngo Molnar 13340114a8e8SDou Liyang /* Check MP table or ACPI MADT configuration */ 13350114a8e8SDou Liyang if (!smp_found_config) { 13360114a8e8SDou Liyang disable_ioapic_support(); 13373e730dadSDou Liyang if (!acpi_lapic) { 13380114a8e8SDou Liyang pr_info("APIC: ACPI MADT or MP tables are not detected\n"); 13393e730dadSDou Liyang return APIC_VIRTUAL_WIRE_NO_CONFIG; 13403e730dadSDou Liyang } 13410114a8e8SDou Liyang return APIC_VIRTUAL_WIRE; 13420114a8e8SDou Liyang } 13430114a8e8SDou Liyang 13443e730dadSDou Liyang #ifdef CONFIG_SMP 13453e730dadSDou Liyang /* If SMP should be disabled, then really disable it! */ 13463e730dadSDou Liyang if (!setup_max_cpus) { 13473e730dadSDou Liyang pr_info("APIC: SMP mode deactivated\n"); 13483e730dadSDou Liyang return APIC_SYMMETRIC_IO_NO_ROUTING; 13493e730dadSDou Liyang } 13503e730dadSDou Liyang 13513e730dadSDou Liyang if (read_apic_id() != boot_cpu_physical_apicid) { 13523e730dadSDou Liyang panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 13533e730dadSDou Liyang read_apic_id(), boot_cpu_physical_apicid); 13543e730dadSDou Liyang /* Or can we switch back to PIC here? */ 13553e730dadSDou Liyang } 13563e730dadSDou Liyang #endif 13573e730dadSDou Liyang 13580114a8e8SDou Liyang return APIC_SYMMETRIC_IO; 13590114a8e8SDou Liyang } 13600114a8e8SDou Liyang 136197992387SThomas Gleixner /* Select the interrupt delivery mode for the BSP */ 136297992387SThomas Gleixner void __init apic_intr_mode_select(void) 136397992387SThomas Gleixner { 136497992387SThomas Gleixner apic_intr_mode = __apic_intr_mode_select(); 136597992387SThomas Gleixner } 136697992387SThomas Gleixner 1367fc90ccfdSVille Syrjälä /* 1368fc90ccfdSVille Syrjälä * An initial setup of the virtual wire mode. 1369fc90ccfdSVille Syrjälä */ 1370fc90ccfdSVille Syrjälä void __init init_bsp_APIC(void) 1371fc90ccfdSVille Syrjälä { 1372fc90ccfdSVille Syrjälä unsigned int value; 1373fc90ccfdSVille Syrjälä 1374fc90ccfdSVille Syrjälä /* 1375fc90ccfdSVille Syrjälä * Don't do the setup now if we have a SMP BIOS as the 1376fc90ccfdSVille Syrjälä * through-I/O-APIC virtual wire mode might be active. 1377fc90ccfdSVille Syrjälä */ 1378fc90ccfdSVille Syrjälä if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC)) 1379fc90ccfdSVille Syrjälä return; 1380fc90ccfdSVille Syrjälä 1381fc90ccfdSVille Syrjälä /* 1382fc90ccfdSVille Syrjälä * Do not trust the local APIC being empty at bootup. 1383fc90ccfdSVille Syrjälä */ 1384fc90ccfdSVille Syrjälä clear_local_APIC(); 1385fc90ccfdSVille Syrjälä 1386fc90ccfdSVille Syrjälä /* 1387fc90ccfdSVille Syrjälä * Enable APIC. 1388fc90ccfdSVille Syrjälä */ 1389fc90ccfdSVille Syrjälä value = apic_read(APIC_SPIV); 1390fc90ccfdSVille Syrjälä value &= ~APIC_VECTOR_MASK; 1391fc90ccfdSVille Syrjälä value |= APIC_SPIV_APIC_ENABLED; 1392fc90ccfdSVille Syrjälä 1393fc90ccfdSVille Syrjälä #ifdef CONFIG_X86_32 1394fc90ccfdSVille Syrjälä /* This bit is reserved on P4/Xeon and should be cleared */ 1395fc90ccfdSVille Syrjälä if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1396fc90ccfdSVille Syrjälä (boot_cpu_data.x86 == 15)) 1397fc90ccfdSVille Syrjälä value &= ~APIC_SPIV_FOCUS_DISABLED; 1398fc90ccfdSVille Syrjälä else 1399fc90ccfdSVille Syrjälä #endif 1400fc90ccfdSVille Syrjälä value |= APIC_SPIV_FOCUS_DISABLED; 1401fc90ccfdSVille Syrjälä value |= SPURIOUS_APIC_VECTOR; 1402fc90ccfdSVille Syrjälä apic_write(APIC_SPIV, value); 1403fc90ccfdSVille Syrjälä 1404fc90ccfdSVille Syrjälä /* 1405fc90ccfdSVille Syrjälä * Set up the virtual wire mode. 1406fc90ccfdSVille Syrjälä */ 1407fc90ccfdSVille Syrjälä apic_write(APIC_LVT0, APIC_DM_EXTINT); 1408fc90ccfdSVille Syrjälä value = APIC_DM_NMI; 1409fc90ccfdSVille Syrjälä if (!lapic_is_integrated()) /* 82489DX */ 1410fc90ccfdSVille Syrjälä value |= APIC_LVT_LEVEL_TRIGGER; 1411fc90ccfdSVille Syrjälä if (apic_extnmi == APIC_EXTNMI_NONE) 1412fc90ccfdSVille Syrjälä value |= APIC_LVT_MASKED; 1413fc90ccfdSVille Syrjälä apic_write(APIC_LVT1, value); 1414fc90ccfdSVille Syrjälä } 1415fc90ccfdSVille Syrjälä 1416748b170cSThomas Gleixner static void __init apic_bsp_setup(bool upmode); 1417748b170cSThomas Gleixner 14184b1669e8SDou Liyang /* Init the interrupt delivery mode for the BSP */ 14194b1669e8SDou Liyang void __init apic_intr_mode_init(void) 14204b1669e8SDou Liyang { 14210c759131SDou Liyang bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT); 14223e730dadSDou Liyang 14234f45ed9fSDou Liyang switch (apic_intr_mode) { 14244b1669e8SDou Liyang case APIC_PIC: 14254b1669e8SDou Liyang pr_info("APIC: Keep in PIC mode(8259)\n"); 14264b1669e8SDou Liyang return; 14274b1669e8SDou Liyang case APIC_VIRTUAL_WIRE: 14284b1669e8SDou Liyang pr_info("APIC: Switch to virtual wire mode setup\n"); 14293e730dadSDou Liyang break; 14303e730dadSDou Liyang case APIC_VIRTUAL_WIRE_NO_CONFIG: 14313e730dadSDou Liyang pr_info("APIC: Switch to virtual wire mode setup with no configuration\n"); 14323e730dadSDou Liyang upmode = true; 14333e730dadSDou Liyang break; 14344b1669e8SDou Liyang case APIC_SYMMETRIC_IO: 143579761ce8SColin Ian King pr_info("APIC: Switch to symmetric I/O mode setup\n"); 14363e730dadSDou Liyang break; 14373e730dadSDou Liyang case APIC_SYMMETRIC_IO_NO_ROUTING: 143879761ce8SColin Ian King pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n"); 14393e730dadSDou Liyang break; 14404b1669e8SDou Liyang } 14413e730dadSDou Liyang 14427a116a2dSKuppuswamy Sathyanarayanan default_setup_apic_routing(); 14437a116a2dSKuppuswamy Sathyanarayanan 1444bb733e43SThomas Gleixner if (x86_platform.apic_post_init) 1445bb733e43SThomas Gleixner x86_platform.apic_post_init(); 1446bb733e43SThomas Gleixner 14473e730dadSDou Liyang apic_bsp_setup(upmode); 1448f62bae50SIngo Molnar } 1449f62bae50SIngo Molnar 1450148f9bb8SPaul Gortmaker static void lapic_setup_esr(void) 1451f62bae50SIngo Molnar { 1452f62bae50SIngo Molnar unsigned int oldvalue, value, maxlvt; 1453f62bae50SIngo Molnar 1454f62bae50SIngo Molnar if (!lapic_is_integrated()) { 1455f62bae50SIngo Molnar pr_info("No ESR for 82489DX.\n"); 1456f62bae50SIngo Molnar return; 1457f62bae50SIngo Molnar } 1458f62bae50SIngo Molnar 1459f62bae50SIngo Molnar if (apic->disable_esr) { 1460f62bae50SIngo Molnar /* 1461f62bae50SIngo Molnar * Something untraceable is creating bad interrupts on 1462f62bae50SIngo Molnar * secondary quads ... for the moment, just leave the 1463f62bae50SIngo Molnar * ESR disabled - we can't do anything useful with the 1464f62bae50SIngo Molnar * errors anyway - mbligh 1465f62bae50SIngo Molnar */ 1466f62bae50SIngo Molnar pr_info("Leaving ESR disabled.\n"); 1467f62bae50SIngo Molnar return; 1468f62bae50SIngo Molnar } 1469f62bae50SIngo Molnar 1470f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 1471f62bae50SIngo Molnar if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1472f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1473f62bae50SIngo Molnar oldvalue = apic_read(APIC_ESR); 1474f62bae50SIngo Molnar 1475f62bae50SIngo Molnar /* enables sending errors */ 1476f62bae50SIngo Molnar value = ERROR_APIC_VECTOR; 1477f62bae50SIngo Molnar apic_write(APIC_LVTERR, value); 1478f62bae50SIngo Molnar 1479f62bae50SIngo Molnar /* 1480f62bae50SIngo Molnar * spec says clear errors after enabling vector. 1481f62bae50SIngo Molnar */ 1482f62bae50SIngo Molnar if (maxlvt > 3) 1483f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1484f62bae50SIngo Molnar value = apic_read(APIC_ESR); 1485f62bae50SIngo Molnar if (value != oldvalue) 1486f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "ESR value before enabling " 1487f62bae50SIngo Molnar "vector: 0x%08x after: 0x%08x\n", 1488f62bae50SIngo Molnar oldvalue, value); 1489f62bae50SIngo Molnar } 1490f62bae50SIngo Molnar 1491cc8bf191SThomas Gleixner #define APIC_IR_REGS APIC_ISR_NR 1492cc8bf191SThomas Gleixner #define APIC_IR_BITS (APIC_IR_REGS * 32) 1493cc8bf191SThomas Gleixner #define APIC_IR_MAPSIZE (APIC_IR_BITS / BITS_PER_LONG) 14949b217f33SDou Liyang 1495cc8bf191SThomas Gleixner union apic_ir { 1496cc8bf191SThomas Gleixner unsigned long map[APIC_IR_MAPSIZE]; 1497cc8bf191SThomas Gleixner u32 regs[APIC_IR_REGS]; 1498cc8bf191SThomas Gleixner }; 1499cc8bf191SThomas Gleixner 1500cc8bf191SThomas Gleixner static bool apic_check_and_ack(union apic_ir *irr, union apic_ir *isr) 1501cc8bf191SThomas Gleixner { 1502cc8bf191SThomas Gleixner int i, bit; 1503cc8bf191SThomas Gleixner 1504cc8bf191SThomas Gleixner /* Read the IRRs */ 1505cc8bf191SThomas Gleixner for (i = 0; i < APIC_IR_REGS; i++) 1506cc8bf191SThomas Gleixner irr->regs[i] = apic_read(APIC_IRR + i * 0x10); 1507cc8bf191SThomas Gleixner 1508cc8bf191SThomas Gleixner /* Read the ISRs */ 1509cc8bf191SThomas Gleixner for (i = 0; i < APIC_IR_REGS; i++) 1510cc8bf191SThomas Gleixner isr->regs[i] = apic_read(APIC_ISR + i * 0x10); 1511cc8bf191SThomas Gleixner 1512cc8bf191SThomas Gleixner /* 1513cc8bf191SThomas Gleixner * If the ISR map is not empty. ACK the APIC and run another round 1514cc8bf191SThomas Gleixner * to verify whether a pending IRR has been unblocked and turned 1515cc8bf191SThomas Gleixner * into a ISR. 1516cc8bf191SThomas Gleixner */ 1517cc8bf191SThomas Gleixner if (!bitmap_empty(isr->map, APIC_IR_BITS)) { 1518cc8bf191SThomas Gleixner /* 1519cc8bf191SThomas Gleixner * There can be multiple ISR bits set when a high priority 1520cc8bf191SThomas Gleixner * interrupt preempted a lower priority one. Issue an ACK 1521cc8bf191SThomas Gleixner * per set bit. 1522cc8bf191SThomas Gleixner */ 1523cc8bf191SThomas Gleixner for_each_set_bit(bit, isr->map, APIC_IR_BITS) 1524cc8bf191SThomas Gleixner ack_APIC_irq(); 1525cc8bf191SThomas Gleixner return true; 1526cc8bf191SThomas Gleixner } 1527cc8bf191SThomas Gleixner 1528cc8bf191SThomas Gleixner return !bitmap_empty(irr->map, APIC_IR_BITS); 1529cc8bf191SThomas Gleixner } 1530cc8bf191SThomas Gleixner 15319b217f33SDou Liyang /* 15329b217f33SDou Liyang * After a crash, we no longer service the interrupts and a pending 15339b217f33SDou Liyang * interrupt from previous kernel might still have ISR bit set. 15349b217f33SDou Liyang * 1535cc8bf191SThomas Gleixner * Most probably by now the CPU has serviced that pending interrupt and it 1536cc8bf191SThomas Gleixner * might not have done the ack_APIC_irq() because it thought, interrupt 1537cc8bf191SThomas Gleixner * came from i8259 as ExtInt. LAPIC did not get EOI so it does not clear 1538d9f6e12fSIngo Molnar * the ISR bit and cpu thinks it has already serviced the interrupt. Hence 1539cc8bf191SThomas Gleixner * a vector might get locked. It was noticed for timer irq (vector 1540cc8bf191SThomas Gleixner * 0x31). Issue an extra EOI to clear ISR. 1541cc8bf191SThomas Gleixner * 1542cc8bf191SThomas Gleixner * If there are pending IRR bits they turn into ISR bits after a higher 1543cc8bf191SThomas Gleixner * priority ISR bit has been acked. 15449b217f33SDou Liyang */ 1545cc8bf191SThomas Gleixner static void apic_pending_intr_clear(void) 1546cc8bf191SThomas Gleixner { 1547cc8bf191SThomas Gleixner union apic_ir irr, isr; 1548cc8bf191SThomas Gleixner unsigned int i; 15499b217f33SDou Liyang 1550cc8bf191SThomas Gleixner /* 512 loops are way oversized and give the APIC a chance to obey. */ 1551cc8bf191SThomas Gleixner for (i = 0; i < 512; i++) { 1552cc8bf191SThomas Gleixner if (!apic_check_and_ack(&irr, &isr)) 1553cc8bf191SThomas Gleixner return; 15549b217f33SDou Liyang } 1555cc8bf191SThomas Gleixner /* Dump the IRR/ISR content if that failed */ 1556cc8bf191SThomas Gleixner pr_warn("APIC: Stale IRR: %256pb ISR: %256pb\n", irr.map, isr.map); 15579b217f33SDou Liyang } 15589b217f33SDou Liyang 1559f62bae50SIngo Molnar /** 1560f62bae50SIngo Molnar * setup_local_APIC - setup the local APIC 15610aa002feSTejun Heo * 1562543113d2SDou Liyang * Used to setup local APIC while initializing BSP or bringing up APs. 15630aa002feSTejun Heo * Always called with preemption disabled. 1564f62bae50SIngo Molnar */ 1565b753a2b7SDou Liyang static void setup_local_APIC(void) 1566f62bae50SIngo Molnar { 15670aa002feSTejun Heo int cpu = smp_processor_id(); 15689b217f33SDou Liyang unsigned int value; 15698c3ba8d0SKerstin Jonsson 1570*49062454SThomas Gleixner if (apic_is_disabled) { 15717167d08eSHenrik Kretzschmar disable_ioapic_support(); 1572f62bae50SIngo Molnar return; 1573f62bae50SIngo Molnar } 1574f62bae50SIngo Molnar 15752640da4cSThomas Gleixner /* 15762640da4cSThomas Gleixner * If this comes from kexec/kcrash the APIC might be enabled in 15772640da4cSThomas Gleixner * SPIV. Soft disable it before doing further initialization. 15782640da4cSThomas Gleixner */ 15792640da4cSThomas Gleixner value = apic_read(APIC_SPIV); 15802640da4cSThomas Gleixner value &= ~APIC_SPIV_APIC_ENABLED; 15812640da4cSThomas Gleixner apic_write(APIC_SPIV, value); 15822640da4cSThomas Gleixner 1583f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1584f62bae50SIngo Molnar /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1585f62bae50SIngo Molnar if (lapic_is_integrated() && apic->disable_esr) { 1586f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1587f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1588f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1589f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1590f62bae50SIngo Molnar } 1591f62bae50SIngo Molnar #endif 1592f62bae50SIngo Molnar /* 1593f62bae50SIngo Molnar * Double-check whether this APIC is really registered. 1594f62bae50SIngo Molnar * This is meaningless in clustered apic mode, so we skip it. 1595f62bae50SIngo Molnar */ 1596c2777f98SDaniel Walker BUG_ON(!apic->apic_id_registered()); 1597f62bae50SIngo Molnar 1598f62bae50SIngo Molnar /* 1599f62bae50SIngo Molnar * Intel recommends to set DFR, LDR and TPR before enabling 1600f62bae50SIngo Molnar * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1601f62bae50SIngo Molnar * document number 292116). So here it goes... 1602f62bae50SIngo Molnar */ 1603f62bae50SIngo Molnar apic->init_apic_ldr(); 1604f62bae50SIngo Molnar 16056f802c4bSTejun Heo #ifdef CONFIG_X86_32 16068c44963bSThomas Gleixner if (apic->dest_mode_logical) { 1607fe6f85caSJan Beulich int logical_apicid, ldr_apicid; 1608fe6f85caSJan Beulich 16096f802c4bSTejun Heo /* 1610acb8bc09STejun Heo * APIC LDR is initialized. If logical_apicid mapping was 1611fe6f85caSJan Beulich * initialized during get_smp_config(), make sure it matches 1612fe6f85caSJan Beulich * the actual value. 16136f802c4bSTejun Heo */ 16148f156168SDou Liyang logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu); 16158f156168SDou Liyang ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 1616fe6f85caSJan Beulich if (logical_apicid != BAD_APICID) 1617fe6f85caSJan Beulich WARN_ON(logical_apicid != ldr_apicid); 1618fe6f85caSJan Beulich /* Always use the value from LDR. */ 16198f156168SDou Liyang early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid; 1620fe6f85caSJan Beulich } 16216f802c4bSTejun Heo #endif 16226f802c4bSTejun Heo 1623f62bae50SIngo Molnar /* 1624229b969bSAndy Lutomirski * Set Task Priority to 'accept all except vectors 0-31'. An APIC 1625229b969bSAndy Lutomirski * vector in the 16-31 range could be delivered if TPR == 0, but we 1626229b969bSAndy Lutomirski * would think it's an exception and terrible things will happen. We 1627229b969bSAndy Lutomirski * never change this later on. 1628f62bae50SIngo Molnar */ 1629f62bae50SIngo Molnar value = apic_read(APIC_TASKPRI); 1630f62bae50SIngo Molnar value &= ~APIC_TPRI_MASK; 1631229b969bSAndy Lutomirski value |= 0x10; 1632f62bae50SIngo Molnar apic_write(APIC_TASKPRI, value); 1633f62bae50SIngo Molnar 1634cc8bf191SThomas Gleixner /* Clear eventually stale ISR/IRR bits */ 16359b217f33SDou Liyang apic_pending_intr_clear(); 1636f62bae50SIngo Molnar 1637f62bae50SIngo Molnar /* 1638f62bae50SIngo Molnar * Now that we are all set up, enable the APIC 1639f62bae50SIngo Molnar */ 1640f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 1641f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 1642f62bae50SIngo Molnar /* 1643f62bae50SIngo Molnar * Enable APIC 1644f62bae50SIngo Molnar */ 1645f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 1646f62bae50SIngo Molnar 1647f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1648f62bae50SIngo Molnar /* 1649f62bae50SIngo Molnar * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1650f62bae50SIngo Molnar * certain networking cards. If high frequency interrupts are 1651f62bae50SIngo Molnar * happening on a particular IOAPIC pin, plus the IOAPIC routing 1652f62bae50SIngo Molnar * entry is masked/unmasked at a high rate as well then sooner or 1653f62bae50SIngo Molnar * later IOAPIC line gets 'stuck', no more interrupts are received 1654f62bae50SIngo Molnar * from the device. If focus CPU is disabled then the hang goes 1655f62bae50SIngo Molnar * away, oh well :-( 1656f62bae50SIngo Molnar * 1657f62bae50SIngo Molnar * [ This bug can be reproduced easily with a level-triggered 1658f62bae50SIngo Molnar * PCI Ne2000 networking cards and PII/PIII processors, dual 1659f62bae50SIngo Molnar * BX chipset. ] 1660f62bae50SIngo Molnar */ 1661f62bae50SIngo Molnar /* 1662f62bae50SIngo Molnar * Actually disabling the focus CPU check just makes the hang less 1663d9f6e12fSIngo Molnar * frequent as it makes the interrupt distribution model be more 1664f62bae50SIngo Molnar * like LRU than MRU (the short-term load is more even across CPUs). 1665f62bae50SIngo Molnar */ 1666f62bae50SIngo Molnar 1667f62bae50SIngo Molnar /* 1668f62bae50SIngo Molnar * - enable focus processor (bit==0) 1669f62bae50SIngo Molnar * - 64bit mode always use processor focus 1670f62bae50SIngo Molnar * so no need to set it 1671f62bae50SIngo Molnar */ 1672f62bae50SIngo Molnar value &= ~APIC_SPIV_FOCUS_DISABLED; 1673f62bae50SIngo Molnar #endif 1674f62bae50SIngo Molnar 1675f62bae50SIngo Molnar /* 1676f62bae50SIngo Molnar * Set spurious IRQ vector 1677f62bae50SIngo Molnar */ 1678f62bae50SIngo Molnar value |= SPURIOUS_APIC_VECTOR; 1679f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 1680f62bae50SIngo Molnar 168139c89dffSThomas Gleixner perf_events_lapic_init(); 168239c89dffSThomas Gleixner 1683f62bae50SIngo Molnar /* 1684f62bae50SIngo Molnar * Set up LVT0, LVT1: 1685f62bae50SIngo Molnar * 1686a1652bb8SJean Delvare * set up through-local-APIC on the boot CPU's LINT0. This is not 1687f62bae50SIngo Molnar * strictly necessary in pure symmetric-IO mode, but sometimes 1688f62bae50SIngo Molnar * we delegate interrupts to the 8259A. 1689f62bae50SIngo Molnar */ 1690f62bae50SIngo Molnar /* 1691f62bae50SIngo Molnar * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1692f62bae50SIngo Molnar */ 1693f62bae50SIngo Molnar value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1694bee3204eSBaoquan He if (!cpu && (pic_mode || !value || skip_ioapic_setup)) { 1695f62bae50SIngo Molnar value = APIC_DM_EXTINT; 16960aa002feSTejun Heo apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1697f62bae50SIngo Molnar } else { 1698f62bae50SIngo Molnar value = APIC_DM_EXTINT | APIC_LVT_MASKED; 16990aa002feSTejun Heo apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1700f62bae50SIngo Molnar } 1701f62bae50SIngo Molnar apic_write(APIC_LVT0, value); 1702f62bae50SIngo Molnar 1703f62bae50SIngo Molnar /* 1704b7c4948eSHidehiro Kawai * Only the BSP sees the LINT1 NMI signal by default. This can be 1705b7c4948eSHidehiro Kawai * modified by apic_extnmi= boot option. 1706f62bae50SIngo Molnar */ 1707b7c4948eSHidehiro Kawai if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) || 1708b7c4948eSHidehiro Kawai apic_extnmi == APIC_EXTNMI_ALL) 1709f62bae50SIngo Molnar value = APIC_DM_NMI; 1710f62bae50SIngo Molnar else 1711f62bae50SIngo Molnar value = APIC_DM_NMI | APIC_LVT_MASKED; 1712ae41a2a4SDou Liyang 1713ae41a2a4SDou Liyang /* Is 82489DX ? */ 1714ae41a2a4SDou Liyang if (!lapic_is_integrated()) 1715f62bae50SIngo Molnar value |= APIC_LVT_LEVEL_TRIGGER; 1716f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 1717f62bae50SIngo Molnar 1718638bee71SH. Peter Anvin #ifdef CONFIG_X86_MCE_INTEL 1719638bee71SH. Peter Anvin /* Recheck CMCI information after local APIC is up on CPU #0 */ 17200aa002feSTejun Heo if (!cpu) 1721638bee71SH. Peter Anvin cmci_recheck(); 1722638bee71SH. Peter Anvin #endif 1723f62bae50SIngo Molnar } 1724f62bae50SIngo Molnar 172505f7e46dSThomas Gleixner static void end_local_APIC_setup(void) 1726f62bae50SIngo Molnar { 1727f62bae50SIngo Molnar lapic_setup_esr(); 1728f62bae50SIngo Molnar 1729f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1730f62bae50SIngo Molnar { 1731f62bae50SIngo Molnar unsigned int value; 1732f62bae50SIngo Molnar /* Disable the local apic timer */ 1733f62bae50SIngo Molnar value = apic_read(APIC_LVTT); 1734f62bae50SIngo Molnar value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1735f62bae50SIngo Molnar apic_write(APIC_LVTT, value); 1736f62bae50SIngo Molnar } 1737f62bae50SIngo Molnar #endif 1738f62bae50SIngo Molnar 1739f62bae50SIngo Molnar apic_pm_activate(); 17402fb270f3SJan Beulich } 17412fb270f3SJan Beulich 17427f7fbf45SKenji Kaneshige /* 174305f7e46dSThomas Gleixner * APIC setup function for application processors. Called from smpboot.c 17447f7fbf45SKenji Kaneshige */ 174505f7e46dSThomas Gleixner void apic_ap_setup(void) 174605f7e46dSThomas Gleixner { 174705f7e46dSThomas Gleixner setup_local_APIC(); 174805f7e46dSThomas Gleixner end_local_APIC_setup(); 1749f62bae50SIngo Molnar } 1750f62bae50SIngo Molnar 1751f62bae50SIngo Molnar #ifdef CONFIG_X86_X2APIC 1752bfb05070SThomas Gleixner int x2apic_mode; 1753db7d8e47SSean Christopherson EXPORT_SYMBOL_GPL(x2apic_mode); 175412e189d3SThomas Gleixner 175512e189d3SThomas Gleixner enum { 175612e189d3SThomas Gleixner X2APIC_OFF, 175712e189d3SThomas Gleixner X2APIC_DISABLED, 1758b8d1d163SDaniel Sneddon /* All states below here have X2APIC enabled */ 1759b8d1d163SDaniel Sneddon X2APIC_ON, 1760b8d1d163SDaniel Sneddon X2APIC_ON_LOCKED 176112e189d3SThomas Gleixner }; 176212e189d3SThomas Gleixner static int x2apic_state; 176312e189d3SThomas Gleixner 1764b8d1d163SDaniel Sneddon static bool x2apic_hw_locked(void) 1765b8d1d163SDaniel Sneddon { 1766b8d1d163SDaniel Sneddon u64 ia32_cap; 1767b8d1d163SDaniel Sneddon u64 msr; 1768b8d1d163SDaniel Sneddon 1769b8d1d163SDaniel Sneddon ia32_cap = x86_read_arch_cap_msr(); 1770b8d1d163SDaniel Sneddon if (ia32_cap & ARCH_CAP_XAPIC_DISABLE) { 1771b8d1d163SDaniel Sneddon rdmsrl(MSR_IA32_XAPIC_DISABLE_STATUS, msr); 1772b8d1d163SDaniel Sneddon return (msr & LEGACY_XAPIC_DISABLED); 1773b8d1d163SDaniel Sneddon } 1774b8d1d163SDaniel Sneddon return false; 1775b8d1d163SDaniel Sneddon } 1776b8d1d163SDaniel Sneddon 1777d786ad32SDenys Vlasenko static void __x2apic_disable(void) 177844e25ff9SThomas Gleixner { 177944e25ff9SThomas Gleixner u64 msr; 178044e25ff9SThomas Gleixner 178193984fbdSBorislav Petkov if (!boot_cpu_has(X86_FEATURE_APIC)) 1782659006bfSThomas Gleixner return; 1783659006bfSThomas Gleixner 178444e25ff9SThomas Gleixner rdmsrl(MSR_IA32_APICBASE, msr); 178544e25ff9SThomas Gleixner if (!(msr & X2APIC_ENABLE)) 178644e25ff9SThomas Gleixner return; 178744e25ff9SThomas Gleixner /* Disable xapic and x2apic first and then reenable xapic mode */ 178844e25ff9SThomas Gleixner wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); 178944e25ff9SThomas Gleixner wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); 179044e25ff9SThomas Gleixner printk_once(KERN_INFO "x2apic disabled\n"); 179144e25ff9SThomas Gleixner } 179244e25ff9SThomas Gleixner 1793d786ad32SDenys Vlasenko static void __x2apic_enable(void) 1794659006bfSThomas Gleixner { 1795659006bfSThomas Gleixner u64 msr; 1796659006bfSThomas Gleixner 1797659006bfSThomas Gleixner rdmsrl(MSR_IA32_APICBASE, msr); 1798659006bfSThomas Gleixner if (msr & X2APIC_ENABLE) 1799659006bfSThomas Gleixner return; 1800659006bfSThomas Gleixner wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); 1801659006bfSThomas Gleixner printk_once(KERN_INFO "x2apic enabled\n"); 1802659006bfSThomas Gleixner } 1803659006bfSThomas Gleixner 1804bfb05070SThomas Gleixner static int __init setup_nox2apic(char *str) 1805bfb05070SThomas Gleixner { 1806bfb05070SThomas Gleixner if (x2apic_enabled()) { 1807bfb05070SThomas Gleixner int apicid = native_apic_msr_read(APIC_ID); 1808bfb05070SThomas Gleixner 1809bfb05070SThomas Gleixner if (apicid >= 255) { 18108d3bcc44SKefeng Wang pr_warn("Apicid: %08x, cannot enforce nox2apic\n", 1811bfb05070SThomas Gleixner apicid); 1812bfb05070SThomas Gleixner return 0; 1813bfb05070SThomas Gleixner } 1814b8d1d163SDaniel Sneddon if (x2apic_hw_locked()) { 1815b8d1d163SDaniel Sneddon pr_warn("APIC locked in x2apic mode, can't disable\n"); 1816b8d1d163SDaniel Sneddon return 0; 1817b8d1d163SDaniel Sneddon } 18188d3bcc44SKefeng Wang pr_warn("x2apic already enabled.\n"); 181944e25ff9SThomas Gleixner __x2apic_disable(); 182044e25ff9SThomas Gleixner } 1821bfb05070SThomas Gleixner setup_clear_cpu_cap(X86_FEATURE_X2APIC); 182212e189d3SThomas Gleixner x2apic_state = X2APIC_DISABLED; 182344e25ff9SThomas Gleixner x2apic_mode = 0; 1824bfb05070SThomas Gleixner return 0; 1825bfb05070SThomas Gleixner } 1826bfb05070SThomas Gleixner early_param("nox2apic", setup_nox2apic); 1827bfb05070SThomas Gleixner 1828659006bfSThomas Gleixner /* Called from cpu_init() to enable x2apic on (secondary) cpus */ 1829659006bfSThomas Gleixner void x2apic_setup(void) 1830659006bfSThomas Gleixner { 1831659006bfSThomas Gleixner /* 1832b8d1d163SDaniel Sneddon * Try to make the AP's APIC state match that of the BSP, but if the 1833b8d1d163SDaniel Sneddon * BSP is unlocked and the AP is locked then there is a state mismatch. 1834b8d1d163SDaniel Sneddon * Warn about the mismatch in case a GP fault occurs due to a locked AP 1835b8d1d163SDaniel Sneddon * trying to be turned off. 1836b8d1d163SDaniel Sneddon */ 1837b8d1d163SDaniel Sneddon if (x2apic_state != X2APIC_ON_LOCKED && x2apic_hw_locked()) 1838b8d1d163SDaniel Sneddon pr_warn("x2apic lock mismatch between BSP and AP.\n"); 1839b8d1d163SDaniel Sneddon /* 1840b8d1d163SDaniel Sneddon * If x2apic is not in ON or LOCKED state, disable it if already enabled 1841659006bfSThomas Gleixner * from BIOS. 1842659006bfSThomas Gleixner */ 1843b8d1d163SDaniel Sneddon if (x2apic_state < X2APIC_ON) { 1844659006bfSThomas Gleixner __x2apic_disable(); 1845659006bfSThomas Gleixner return; 1846659006bfSThomas Gleixner } 1847659006bfSThomas Gleixner __x2apic_enable(); 1848659006bfSThomas Gleixner } 1849659006bfSThomas Gleixner 185044e25ff9SThomas Gleixner static __init void x2apic_disable(void) 1851fb209bd8SYinghai Lu { 1852a57e456aSThomas Gleixner u32 x2apic_id, state = x2apic_state; 1853fb209bd8SYinghai Lu 1854a57e456aSThomas Gleixner x2apic_mode = 0; 1855a57e456aSThomas Gleixner x2apic_state = X2APIC_DISABLED; 1856a57e456aSThomas Gleixner 1857a57e456aSThomas Gleixner if (state != X2APIC_ON) 1858a57e456aSThomas Gleixner return; 1859fb209bd8SYinghai Lu 18606d2d49d2SThomas Gleixner x2apic_id = read_apic_id(); 1861fb209bd8SYinghai Lu if (x2apic_id >= 255) 1862fb209bd8SYinghai Lu panic("Cannot disable x2apic, id: %08x\n", x2apic_id); 1863fb209bd8SYinghai Lu 1864b8d1d163SDaniel Sneddon if (x2apic_hw_locked()) { 1865b8d1d163SDaniel Sneddon pr_warn("Cannot disable locked x2apic, id: %08x\n", x2apic_id); 1866b8d1d163SDaniel Sneddon return; 1867b8d1d163SDaniel Sneddon } 1868b8d1d163SDaniel Sneddon 186944e25ff9SThomas Gleixner __x2apic_disable(); 1870fb209bd8SYinghai Lu register_lapic_address(mp_lapic_addr); 1871fb209bd8SYinghai Lu } 1872fb209bd8SYinghai Lu 1873659006bfSThomas Gleixner static __init void x2apic_enable(void) 1874f62bae50SIngo Molnar { 1875659006bfSThomas Gleixner if (x2apic_state != X2APIC_OFF) 1876f62bae50SIngo Molnar return; 1877f62bae50SIngo Molnar 1878659006bfSThomas Gleixner x2apic_mode = 1; 187912e189d3SThomas Gleixner x2apic_state = X2APIC_ON; 1880659006bfSThomas Gleixner __x2apic_enable(); 1881f62bae50SIngo Molnar } 1882d524165cSThomas Gleixner 188362e61633SThomas Gleixner static __init void try_to_enable_x2apic(int remap_mode) 188407806c50SJiang Liu { 1885659006bfSThomas Gleixner if (x2apic_state == X2APIC_DISABLED) 188607806c50SJiang Liu return; 188707806c50SJiang Liu 188862e61633SThomas Gleixner if (remap_mode != IRQ_REMAP_X2APIC_MODE) { 1889ab0f59c6SDavid Woodhouse u32 apic_limit = 255; 1890ab0f59c6SDavid Woodhouse 189126573a97SDavid Woodhouse /* 189226573a97SDavid Woodhouse * Using X2APIC without IR is not architecturally supported 189326573a97SDavid Woodhouse * on bare metal but may be supported in guests. 189407806c50SJiang Liu */ 189526573a97SDavid Woodhouse if (!x86_init.hyper.x2apic_available()) { 189662e61633SThomas Gleixner pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); 189744e25ff9SThomas Gleixner x2apic_disable(); 189807806c50SJiang Liu return; 189907806c50SJiang Liu } 190007806c50SJiang Liu 190107806c50SJiang Liu /* 1902ab0f59c6SDavid Woodhouse * If the hypervisor supports extended destination ID in 1903ab0f59c6SDavid Woodhouse * MSI, that increases the maximum APIC ID that can be 1904ab0f59c6SDavid Woodhouse * used for non-remapped IRQ domains. 1905ab0f59c6SDavid Woodhouse */ 1906ab0f59c6SDavid Woodhouse if (x86_init.hyper.msi_ext_dest_id()) { 1907ab0f59c6SDavid Woodhouse virt_ext_dest_id = 1; 1908ab0f59c6SDavid Woodhouse apic_limit = 32767; 1909ab0f59c6SDavid Woodhouse } 1910ab0f59c6SDavid Woodhouse 1911ab0f59c6SDavid Woodhouse /* 191226573a97SDavid Woodhouse * Without IR, all CPUs can be addressed by IOAPIC/MSI only 1913d9f6e12fSIngo Molnar * in physical mode, and CPUs with an APIC ID that cannot 191426573a97SDavid Woodhouse * be addressed must not be brought online. 191507806c50SJiang Liu */ 1916ab0f59c6SDavid Woodhouse x2apic_set_max_apicid(apic_limit); 191755eae7deSThomas Gleixner x2apic_phys = 1; 191807806c50SJiang Liu } 1919659006bfSThomas Gleixner x2apic_enable(); 192055eae7deSThomas Gleixner } 192155eae7deSThomas Gleixner 192255eae7deSThomas Gleixner void __init check_x2apic(void) 192355eae7deSThomas Gleixner { 192455eae7deSThomas Gleixner if (x2apic_enabled()) { 192555eae7deSThomas Gleixner pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); 192655eae7deSThomas Gleixner x2apic_mode = 1; 1927b8d1d163SDaniel Sneddon if (x2apic_hw_locked()) 1928b8d1d163SDaniel Sneddon x2apic_state = X2APIC_ON_LOCKED; 1929b8d1d163SDaniel Sneddon else 193012e189d3SThomas Gleixner x2apic_state = X2APIC_ON; 193162436a4dSBorislav Petkov } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) { 193212e189d3SThomas Gleixner x2apic_state = X2APIC_DISABLED; 193355eae7deSThomas Gleixner } 193455eae7deSThomas Gleixner } 193555eae7deSThomas Gleixner #else /* CONFIG_X86_X2APIC */ 1936e3998434SMateusz Jończyk void __init check_x2apic(void) 193755eae7deSThomas Gleixner { 193855eae7deSThomas Gleixner if (!apic_is_x2apic_enabled()) 1939e3998434SMateusz Jończyk return; 194055eae7deSThomas Gleixner /* 1941e3998434SMateusz Jończyk * Checkme: Can we simply turn off x2APIC here instead of disabling the APIC? 194255eae7deSThomas Gleixner */ 1943e3998434SMateusz Jończyk pr_err("Kernel does not support x2APIC, please recompile with CONFIG_X86_X2APIC.\n"); 1944e3998434SMateusz Jończyk pr_err("Disabling APIC, expect reduced performance and functionality.\n"); 1945e3998434SMateusz Jończyk 1946*49062454SThomas Gleixner apic_is_disabled = true; 1947e3998434SMateusz Jończyk setup_clear_cpu_cap(X86_FEATURE_APIC); 194855eae7deSThomas Gleixner } 194955eae7deSThomas Gleixner 195062e61633SThomas Gleixner static inline void try_to_enable_x2apic(int remap_mode) { } 1951659006bfSThomas Gleixner static inline void __x2apic_enable(void) { } 195255eae7deSThomas Gleixner #endif /* !CONFIG_X86_X2APIC */ 195355eae7deSThomas Gleixner 1954ce69a784SGleb Natapov void __init enable_IR_x2apic(void) 1955ce69a784SGleb Natapov { 1956ce69a784SGleb Natapov unsigned long flags; 195707806c50SJiang Liu int ret, ir_stat; 1958b7f42ab2SYinghai Lu 195911277aabSDou Liyang if (skip_ioapic_setup) { 196011277aabSDou Liyang pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); 19612e63ad4bSWanpeng Li return; 196211277aabSDou Liyang } 19632e63ad4bSWanpeng Li 196407806c50SJiang Liu ir_stat = irq_remapping_prepare(); 196507806c50SJiang Liu if (ir_stat < 0 && !x2apic_supported()) 1966e670761fSYinghai Lu return; 1967ce69a784SGleb Natapov 196831dce14aSSuresh Siddha ret = save_ioapic_entries(); 1969f62bae50SIngo Molnar if (ret) { 1970f62bae50SIngo Molnar pr_info("Saving IO-APIC state failed: %d\n", ret); 1971fb209bd8SYinghai Lu return; 1972f62bae50SIngo Molnar } 1973f62bae50SIngo Molnar 197405c3dc2cSSuresh Siddha local_irq_save(flags); 1975b81bb373SJacob Pan legacy_pic->mask_all(); 197631dce14aSSuresh Siddha mask_ioapic_entries(); 197705c3dc2cSSuresh Siddha 19786a6256f9SAdam Buchbinder /* If irq_remapping_prepare() succeeded, try to enable it */ 197907806c50SJiang Liu if (ir_stat >= 0) 198011277aabSDou Liyang ir_stat = irq_remapping_enable(); 198107806c50SJiang Liu /* ir_stat contains the remap mode or an error code */ 198207806c50SJiang Liu try_to_enable_x2apic(ir_stat); 1983a31bc327SYinghai Lu 198407806c50SJiang Liu if (ir_stat < 0) 198531dce14aSSuresh Siddha restore_ioapic_entries(); 1986b81bb373SJacob Pan legacy_pic->restore_mask(); 1987f62bae50SIngo Molnar local_irq_restore(flags); 1988f62bae50SIngo Molnar } 198993758238SWeidong Han 1990f62bae50SIngo Molnar #ifdef CONFIG_X86_64 1991f62bae50SIngo Molnar /* 1992f62bae50SIngo Molnar * Detect and enable local APICs on non-SMP boards. 1993f62bae50SIngo Molnar * Original code written by Keir Fraser. 1994f62bae50SIngo Molnar * On AMD64 we trust the BIOS - if it says no APIC it is likely 1995f62bae50SIngo Molnar * not correctly set up (usually the APIC timer won't work etc.) 1996f62bae50SIngo Molnar */ 1997f62bae50SIngo Molnar static int __init detect_init_APIC(void) 1998f62bae50SIngo Molnar { 199993984fbdSBorislav Petkov if (!boot_cpu_has(X86_FEATURE_APIC)) { 2000f62bae50SIngo Molnar pr_info("No local APIC present\n"); 2001f62bae50SIngo Molnar return -1; 2002f62bae50SIngo Molnar } 2003f62bae50SIngo Molnar 2004f62bae50SIngo Molnar mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 2005f62bae50SIngo Molnar return 0; 2006f62bae50SIngo Molnar } 2007f62bae50SIngo Molnar #else 20085a7ae78fSThomas Gleixner 200925874a29SHenrik Kretzschmar static int __init apic_verify(void) 20105a7ae78fSThomas Gleixner { 20115a7ae78fSThomas Gleixner u32 features, h, l; 20125a7ae78fSThomas Gleixner 20135a7ae78fSThomas Gleixner /* 20145a7ae78fSThomas Gleixner * The APIC feature bit should now be enabled 20155a7ae78fSThomas Gleixner * in `cpuid' 20165a7ae78fSThomas Gleixner */ 20175a7ae78fSThomas Gleixner features = cpuid_edx(1); 20185a7ae78fSThomas Gleixner if (!(features & (1 << X86_FEATURE_APIC))) { 20198d3bcc44SKefeng Wang pr_warn("Could not enable APIC!\n"); 20205a7ae78fSThomas Gleixner return -1; 20215a7ae78fSThomas Gleixner } 20225a7ae78fSThomas Gleixner set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 20235a7ae78fSThomas Gleixner mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 20245a7ae78fSThomas Gleixner 20255a7ae78fSThomas Gleixner /* The BIOS may have set up the APIC at some other address */ 2026cbf2829bSBryan O'Donoghue if (boot_cpu_data.x86 >= 6) { 20275a7ae78fSThomas Gleixner rdmsr(MSR_IA32_APICBASE, l, h); 20285a7ae78fSThomas Gleixner if (l & MSR_IA32_APICBASE_ENABLE) 20295a7ae78fSThomas Gleixner mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 2030cbf2829bSBryan O'Donoghue } 20315a7ae78fSThomas Gleixner 20325a7ae78fSThomas Gleixner pr_info("Found and enabled local APIC!\n"); 20335a7ae78fSThomas Gleixner return 0; 20345a7ae78fSThomas Gleixner } 20355a7ae78fSThomas Gleixner 203625874a29SHenrik Kretzschmar int __init apic_force_enable(unsigned long addr) 20375a7ae78fSThomas Gleixner { 20385a7ae78fSThomas Gleixner u32 h, l; 20395a7ae78fSThomas Gleixner 2040*49062454SThomas Gleixner if (apic_is_disabled) 20415a7ae78fSThomas Gleixner return -1; 20425a7ae78fSThomas Gleixner 20435a7ae78fSThomas Gleixner /* 20445a7ae78fSThomas Gleixner * Some BIOSes disable the local APIC in the APIC_BASE 20455a7ae78fSThomas Gleixner * MSR. This can only be done in software for Intel P6 or later 20465a7ae78fSThomas Gleixner * and AMD K7 (Model > 1) or later. 20475a7ae78fSThomas Gleixner */ 2048cbf2829bSBryan O'Donoghue if (boot_cpu_data.x86 >= 6) { 20495a7ae78fSThomas Gleixner rdmsr(MSR_IA32_APICBASE, l, h); 20505a7ae78fSThomas Gleixner if (!(l & MSR_IA32_APICBASE_ENABLE)) { 20515a7ae78fSThomas Gleixner pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 20525a7ae78fSThomas Gleixner l &= ~MSR_IA32_APICBASE_BASE; 2053a906fdaaSThomas Gleixner l |= MSR_IA32_APICBASE_ENABLE | addr; 20545a7ae78fSThomas Gleixner wrmsr(MSR_IA32_APICBASE, l, h); 20555a7ae78fSThomas Gleixner enabled_via_apicbase = 1; 20565a7ae78fSThomas Gleixner } 2057cbf2829bSBryan O'Donoghue } 20585a7ae78fSThomas Gleixner return apic_verify(); 20595a7ae78fSThomas Gleixner } 20605a7ae78fSThomas Gleixner 2061f62bae50SIngo Molnar /* 2062f62bae50SIngo Molnar * Detect and initialize APIC 2063f62bae50SIngo Molnar */ 2064f62bae50SIngo Molnar static int __init detect_init_APIC(void) 2065f62bae50SIngo Molnar { 2066f62bae50SIngo Molnar /* Disabled by kernel option? */ 2067*49062454SThomas Gleixner if (apic_is_disabled) 2068f62bae50SIngo Molnar return -1; 2069f62bae50SIngo Molnar 2070f62bae50SIngo Molnar switch (boot_cpu_data.x86_vendor) { 2071f62bae50SIngo Molnar case X86_VENDOR_AMD: 2072f62bae50SIngo Molnar if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 2073f62bae50SIngo Molnar (boot_cpu_data.x86 >= 15)) 2074f62bae50SIngo Molnar break; 2075f62bae50SIngo Molnar goto no_apic; 2076da33dfefSPu Wen case X86_VENDOR_HYGON: 2077da33dfefSPu Wen break; 2078f62bae50SIngo Molnar case X86_VENDOR_INTEL: 2079f62bae50SIngo Molnar if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 208093984fbdSBorislav Petkov (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC))) 2081f62bae50SIngo Molnar break; 2082f62bae50SIngo Molnar goto no_apic; 2083f62bae50SIngo Molnar default: 2084f62bae50SIngo Molnar goto no_apic; 2085f62bae50SIngo Molnar } 2086f62bae50SIngo Molnar 208793984fbdSBorislav Petkov if (!boot_cpu_has(X86_FEATURE_APIC)) { 2088f62bae50SIngo Molnar /* 2089f62bae50SIngo Molnar * Over-ride BIOS and try to enable the local APIC only if 2090f62bae50SIngo Molnar * "lapic" specified. 2091f62bae50SIngo Molnar */ 2092f62bae50SIngo Molnar if (!force_enable_local_apic) { 2093f62bae50SIngo Molnar pr_info("Local APIC disabled by BIOS -- " 2094f62bae50SIngo Molnar "you can enable it with \"lapic\"\n"); 2095f62bae50SIngo Molnar return -1; 2096f62bae50SIngo Molnar } 2097a906fdaaSThomas Gleixner if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) 20985a7ae78fSThomas Gleixner return -1; 20995a7ae78fSThomas Gleixner } else { 21005a7ae78fSThomas Gleixner if (apic_verify()) 2101f62bae50SIngo Molnar return -1; 2102f62bae50SIngo Molnar } 2103f62bae50SIngo Molnar 2104f62bae50SIngo Molnar apic_pm_activate(); 2105f62bae50SIngo Molnar 2106f62bae50SIngo Molnar return 0; 2107f62bae50SIngo Molnar 2108f62bae50SIngo Molnar no_apic: 2109f62bae50SIngo Molnar pr_info("No local APIC present or hardware disabled\n"); 2110f62bae50SIngo Molnar return -1; 2111f62bae50SIngo Molnar } 2112f62bae50SIngo Molnar #endif 2113f62bae50SIngo Molnar 2114f62bae50SIngo Molnar /** 2115f62bae50SIngo Molnar * init_apic_mappings - initialize APIC mappings 2116f62bae50SIngo Molnar */ 2117f62bae50SIngo Molnar void __init init_apic_mappings(void) 2118f62bae50SIngo Molnar { 21194401da61SYinghai Lu unsigned int new_apicid; 21204401da61SYinghai Lu 2121c84cb373SThomas Gleixner if (apic_validate_deadline_timer()) 2122de308d18SBorislav Petkov pr_info("TSC deadline timer available\n"); 2123bd9240a1SPeter Zijlstra 2124fc1edaf9SSuresh Siddha if (x2apic_mode) { 2125f62bae50SIngo Molnar boot_cpu_physical_apicid = read_apic_id(); 2126f62bae50SIngo Molnar return; 2127f62bae50SIngo Molnar } 2128f62bae50SIngo Molnar 21294797f6b0SYinghai Lu /* If no local APIC can be found return early */ 2130f62bae50SIngo Molnar if (!smp_found_config && detect_init_APIC()) { 21314797f6b0SYinghai Lu /* lets NOP'ify apic operations */ 21324797f6b0SYinghai Lu pr_info("APIC: disable apic facility\n"); 21334797f6b0SYinghai Lu apic_disable(); 21344797f6b0SYinghai Lu } else { 2135f62bae50SIngo Molnar apic_phys = mp_lapic_addr; 2136f62bae50SIngo Molnar 21374401da61SYinghai Lu /* 21385ba039a5SDou Liyang * If the system has ACPI MADT tables or MP info, the LAPIC 21395ba039a5SDou Liyang * address is already registered. 21404401da61SYinghai Lu */ 21415989cd6aSEric W. Biederman if (!acpi_lapic && !smp_found_config) 2142326a2e6bSYinghai Lu register_lapic_address(apic_phys); 2143cec6be6dSCyrill Gorcunov } 2144f62bae50SIngo Molnar 2145f62bae50SIngo Molnar /* 2146f62bae50SIngo Molnar * Fetch the APIC ID of the BSP in case we have a 2147f62bae50SIngo Molnar * default configuration (or the MP table is broken). 2148f62bae50SIngo Molnar */ 21494401da61SYinghai Lu new_apicid = read_apic_id(); 21504401da61SYinghai Lu if (boot_cpu_physical_apicid != new_apicid) { 21514401da61SYinghai Lu boot_cpu_physical_apicid = new_apicid; 2152103428e5SCyrill Gorcunov /* 2153103428e5SCyrill Gorcunov * yeah -- we lie about apic_version 2154103428e5SCyrill Gorcunov * in case if apic was disabled via boot option 2155103428e5SCyrill Gorcunov * but it's not a problem for SMP compiled kernel 21564f45ed9fSDou Liyang * since apic_intr_mode_select is prepared for such 21574f45ed9fSDou Liyang * a case and disable smp mode 2158103428e5SCyrill Gorcunov */ 2159cff9ab2bSDenys Vlasenko boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 216008306ce6SCyrill Gorcunov } 2161f62bae50SIngo Molnar } 2162f62bae50SIngo Molnar 2163c0104d38SYinghai Lu void __init register_lapic_address(unsigned long address) 2164c0104d38SYinghai Lu { 2165c0104d38SYinghai Lu mp_lapic_addr = address; 2166c0104d38SYinghai Lu 21670450193bSYinghai Lu if (!x2apic_mode) { 2168c0104d38SYinghai Lu set_fixmap_nocache(FIX_APIC_BASE, address); 2169bea629d5SThomas Gleixner apic_mmio_base = APIC_BASE; 2170f1157141SYinghai Lu apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 21716de42119SBaoquan He APIC_BASE, address); 21720450193bSYinghai Lu } 2173c0104d38SYinghai Lu if (boot_cpu_physical_apicid == -1U) { 2174c0104d38SYinghai Lu boot_cpu_physical_apicid = read_apic_id(); 2175cff9ab2bSDenys Vlasenko boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 2176c0104d38SYinghai Lu } 2177c0104d38SYinghai Lu } 2178c0104d38SYinghai Lu 2179f62bae50SIngo Molnar /* 2180f62bae50SIngo Molnar * Local APIC interrupts 2181f62bae50SIngo Molnar */ 2182f62bae50SIngo Molnar 21833c5e0267SThomas Gleixner /* 21843c5e0267SThomas Gleixner * Common handling code for spurious_interrupt and spurious_vector entry 21853c5e0267SThomas Gleixner * points below. No point in allowing the compiler to inline it twice. 2186f62bae50SIngo Molnar */ 21873c5e0267SThomas Gleixner static noinline void handle_spurious_interrupt(u8 vector) 2188f62bae50SIngo Molnar { 2189f62bae50SIngo Molnar u32 v; 2190f62bae50SIngo Molnar 219161069de7SThomas Gleixner trace_spurious_apic_entry(vector); 219261069de7SThomas Gleixner 2193f62bae50SIngo Molnar inc_irq_stat(irq_spurious_count); 2194f62bae50SIngo Molnar 2195f8a8fe61SThomas Gleixner /* 2196f8a8fe61SThomas Gleixner * If this is a spurious interrupt then do not acknowledge 2197f8a8fe61SThomas Gleixner */ 2198f8a8fe61SThomas Gleixner if (vector == SPURIOUS_APIC_VECTOR) { 2199f8a8fe61SThomas Gleixner /* See SDM vol 3 */ 2200f8a8fe61SThomas Gleixner pr_info("Spurious APIC interrupt (vector 0xFF) on CPU#%d, should never happen.\n", 2201f8a8fe61SThomas Gleixner smp_processor_id()); 2202f8a8fe61SThomas Gleixner goto out; 2203f8a8fe61SThomas Gleixner } 2204eddc0e92SSeiji Aguchi 2205f8a8fe61SThomas Gleixner /* 2206f8a8fe61SThomas Gleixner * If it is a vectored one, verify it's set in the ISR. If set, 2207f8a8fe61SThomas Gleixner * acknowledge it. 2208f8a8fe61SThomas Gleixner */ 2209f8a8fe61SThomas Gleixner v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); 2210f8a8fe61SThomas Gleixner if (v & (1 << (vector & 0x1f))) { 2211f8a8fe61SThomas Gleixner pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Acked\n", 2212f8a8fe61SThomas Gleixner vector, smp_processor_id()); 2213f8a8fe61SThomas Gleixner ack_APIC_irq(); 2214f8a8fe61SThomas Gleixner } else { 2215f8a8fe61SThomas Gleixner pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Not pending!\n", 2216f8a8fe61SThomas Gleixner vector, smp_processor_id()); 2217f8a8fe61SThomas Gleixner } 2218f8a8fe61SThomas Gleixner out: 22192414e021SJan Beulich trace_spurious_apic_exit(vector); 2220f62bae50SIngo Molnar } 2221f62bae50SIngo Molnar 22223c5e0267SThomas Gleixner /** 22233c5e0267SThomas Gleixner * spurious_interrupt - Catch all for interrupts raised on unused vectors 22243c5e0267SThomas Gleixner * @regs: Pointer to pt_regs on stack 22253c5e0267SThomas Gleixner * @vector: The vector number 22263c5e0267SThomas Gleixner * 22273c5e0267SThomas Gleixner * This is invoked from ASM entry code to catch all interrupts which 22283c5e0267SThomas Gleixner * trigger on an entry which is routed to the common_spurious idtentry 22293c5e0267SThomas Gleixner * point. 22303c5e0267SThomas Gleixner */ 22313c5e0267SThomas Gleixner DEFINE_IDTENTRY_IRQ(spurious_interrupt) 22323c5e0267SThomas Gleixner { 22333c5e0267SThomas Gleixner handle_spurious_interrupt(vector); 22343c5e0267SThomas Gleixner } 22353c5e0267SThomas Gleixner 2236db0338eeSThomas Gleixner DEFINE_IDTENTRY_SYSVEC(sysvec_spurious_apic_interrupt) 2237633260faSThomas Gleixner { 22383c5e0267SThomas Gleixner handle_spurious_interrupt(SPURIOUS_APIC_VECTOR); 2239f62bae50SIngo Molnar } 2240f62bae50SIngo Molnar 2241f62bae50SIngo Molnar /* 2242f62bae50SIngo Molnar * This interrupt should never happen with our APIC/SMP architecture 2243f62bae50SIngo Molnar */ 2244db0338eeSThomas Gleixner DEFINE_IDTENTRY_SYSVEC(sysvec_error_interrupt) 2245f62bae50SIngo Molnar { 22462b398bd9SYouquan Song static const char * const error_interrupt_reason[] = { 22472b398bd9SYouquan Song "Send CS error", /* APIC Error Bit 0 */ 22482b398bd9SYouquan Song "Receive CS error", /* APIC Error Bit 1 */ 22492b398bd9SYouquan Song "Send accept error", /* APIC Error Bit 2 */ 22502b398bd9SYouquan Song "Receive accept error", /* APIC Error Bit 3 */ 22512b398bd9SYouquan Song "Redirectable IPI", /* APIC Error Bit 4 */ 22522b398bd9SYouquan Song "Send illegal vector", /* APIC Error Bit 5 */ 22532b398bd9SYouquan Song "Received illegal vector", /* APIC Error Bit 6 */ 22542b398bd9SYouquan Song "Illegal register address", /* APIC Error Bit 7 */ 22552b398bd9SYouquan Song }; 225661069de7SThomas Gleixner u32 v, i = 0; 225761069de7SThomas Gleixner 225861069de7SThomas Gleixner trace_error_apic_entry(ERROR_APIC_VECTOR); 2259f62bae50SIngo Molnar 2260f62bae50SIngo Molnar /* First tickle the hardware, only then report what went on. -- REW */ 2261023de4a0SMaciej W. Rozycki if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ 2262f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 226360283df7SRichard Weinberger v = apic_read(APIC_ESR); 2264f62bae50SIngo Molnar ack_APIC_irq(); 2265f62bae50SIngo Molnar atomic_inc(&irq_err_count); 2266f62bae50SIngo Molnar 226760283df7SRichard Weinberger apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", 226860283df7SRichard Weinberger smp_processor_id(), v); 22692b398bd9SYouquan Song 227060283df7SRichard Weinberger v &= 0xff; 227160283df7SRichard Weinberger while (v) { 227260283df7SRichard Weinberger if (v & 0x1) 22732b398bd9SYouquan Song apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); 22742b398bd9SYouquan Song i++; 227560283df7SRichard Weinberger v >>= 1; 22764b8073e4SPeter Senna Tschudin } 22772b398bd9SYouquan Song 22782b398bd9SYouquan Song apic_printk(APIC_DEBUG, KERN_CONT "\n"); 22792b398bd9SYouquan Song 2280cf910e83SSeiji Aguchi trace_error_apic_exit(ERROR_APIC_VECTOR); 2281f62bae50SIngo Molnar } 2282f62bae50SIngo Molnar 2283f62bae50SIngo Molnar /** 2284f62bae50SIngo Molnar * connect_bsp_APIC - attach the APIC to the interrupt system 2285f62bae50SIngo Molnar */ 228605f7e46dSThomas Gleixner static void __init connect_bsp_APIC(void) 2287f62bae50SIngo Molnar { 2288f62bae50SIngo Molnar #ifdef CONFIG_X86_32 2289f62bae50SIngo Molnar if (pic_mode) { 2290f62bae50SIngo Molnar /* 2291f62bae50SIngo Molnar * Do not trust the local APIC being empty at bootup. 2292f62bae50SIngo Molnar */ 2293f62bae50SIngo Molnar clear_local_APIC(); 2294f62bae50SIngo Molnar /* 2295f62bae50SIngo Molnar * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 2296f62bae50SIngo Molnar * local APIC to INT and NMI lines. 2297f62bae50SIngo Molnar */ 2298f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "leaving PIC mode, " 2299f62bae50SIngo Molnar "enabling APIC mode.\n"); 2300c0eaa453SCyrill Gorcunov imcr_pic_to_apic(); 2301f62bae50SIngo Molnar } 2302f62bae50SIngo Molnar #endif 2303f62bae50SIngo Molnar } 2304f62bae50SIngo Molnar 2305f62bae50SIngo Molnar /** 2306f62bae50SIngo Molnar * disconnect_bsp_APIC - detach the APIC from the interrupt system 2307f62bae50SIngo Molnar * @virt_wire_setup: indicates, whether virtual wire mode is selected 2308f62bae50SIngo Molnar * 2309f62bae50SIngo Molnar * Virtual wire mode is necessary to deliver legacy interrupts even when the 2310f62bae50SIngo Molnar * APIC is disabled. 2311f62bae50SIngo Molnar */ 2312f62bae50SIngo Molnar void disconnect_bsp_APIC(int virt_wire_setup) 2313f62bae50SIngo Molnar { 2314f62bae50SIngo Molnar unsigned int value; 2315f62bae50SIngo Molnar 2316f62bae50SIngo Molnar #ifdef CONFIG_X86_32 2317f62bae50SIngo Molnar if (pic_mode) { 2318f62bae50SIngo Molnar /* 2319f62bae50SIngo Molnar * Put the board back into PIC mode (has an effect only on 2320f62bae50SIngo Molnar * certain older boards). Note that APIC interrupts, including 2321f62bae50SIngo Molnar * IPIs, won't work beyond this point! The only exception are 2322f62bae50SIngo Molnar * INIT IPIs. 2323f62bae50SIngo Molnar */ 2324f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "disabling APIC mode, " 2325f62bae50SIngo Molnar "entering PIC mode.\n"); 2326c0eaa453SCyrill Gorcunov imcr_apic_to_pic(); 2327f62bae50SIngo Molnar return; 2328f62bae50SIngo Molnar } 2329f62bae50SIngo Molnar #endif 2330f62bae50SIngo Molnar 2331f62bae50SIngo Molnar /* Go back to Virtual Wire compatibility mode */ 2332f62bae50SIngo Molnar 2333f62bae50SIngo Molnar /* For the spurious interrupt use vector F, and enable it */ 2334f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 2335f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 2336f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 2337f62bae50SIngo Molnar value |= 0xf; 2338f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 2339f62bae50SIngo Molnar 2340f62bae50SIngo Molnar if (!virt_wire_setup) { 2341f62bae50SIngo Molnar /* 2342f62bae50SIngo Molnar * For LVT0 make it edge triggered, active high, 2343f62bae50SIngo Molnar * external and enabled 2344f62bae50SIngo Molnar */ 2345f62bae50SIngo Molnar value = apic_read(APIC_LVT0); 2346f62bae50SIngo Molnar value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2347f62bae50SIngo Molnar APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2348f62bae50SIngo Molnar APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2349f62bae50SIngo Molnar value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2350f62bae50SIngo Molnar value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 2351f62bae50SIngo Molnar apic_write(APIC_LVT0, value); 2352f62bae50SIngo Molnar } else { 2353f62bae50SIngo Molnar /* Disable LVT0 */ 2354f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_LVT_MASKED); 2355f62bae50SIngo Molnar } 2356f62bae50SIngo Molnar 2357f62bae50SIngo Molnar /* 2358f62bae50SIngo Molnar * For LVT1 make it edge triggered, active high, 2359f62bae50SIngo Molnar * nmi and enabled 2360f62bae50SIngo Molnar */ 2361f62bae50SIngo Molnar value = apic_read(APIC_LVT1); 2362f62bae50SIngo Molnar value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2363f62bae50SIngo Molnar APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2364f62bae50SIngo Molnar APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2365f62bae50SIngo Molnar value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2366f62bae50SIngo Molnar value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 2367f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 2368f62bae50SIngo Molnar } 2369f62bae50SIngo Molnar 23708f54969dSGu Zheng /* 23718f54969dSGu Zheng * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated 23728f54969dSGu Zheng * contiguously, it equals to current allocated max logical CPU ID plus 1. 237312bf98b9SDou Liyang * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range, 237412bf98b9SDou Liyang * so the maximum of nr_logical_cpuids is nr_cpu_ids. 23758f54969dSGu Zheng * 23768f54969dSGu Zheng * NOTE: Reserve 0 for BSP. 23778f54969dSGu Zheng */ 23788f54969dSGu Zheng static int nr_logical_cpuids = 1; 23798f54969dSGu Zheng 23808f54969dSGu Zheng /* 23818f54969dSGu Zheng * Used to store mapping between logical CPU IDs and APIC IDs. 23828f54969dSGu Zheng */ 23837e75178aSDavid Woodhouse int cpuid_to_apicid[] = { 23848f54969dSGu Zheng [0 ... NR_CPUS - 1] = -1, 23858f54969dSGu Zheng }; 23868f54969dSGu Zheng 2387dd926880SJohan Hovold bool arch_match_cpu_phys_id(int cpu, u64 phys_id) 2388dd926880SJohan Hovold { 2389dd926880SJohan Hovold return phys_id == cpuid_to_apicid[cpu]; 2390dd926880SJohan Hovold } 2391dd926880SJohan Hovold 2392d0055f35SVlastimil Babka #ifdef CONFIG_SMP 2393f54d4434SThomas Gleixner static void cpu_mark_primary_thread(unsigned int cpu, unsigned int apicid) 23946a4d2657SThomas Gleixner { 23956a4d2657SThomas Gleixner /* Isolate the SMT bit(s) in the APICID and check for 0 */ 2396f54d4434SThomas Gleixner u32 mask = (1U << (fls(smp_num_siblings) - 1)) - 1; 2397f54d4434SThomas Gleixner 2398f54d4434SThomas Gleixner if (smp_num_siblings == 1 || !(apicid & mask)) 2399f54d4434SThomas Gleixner cpumask_set_cpu(cpu, &__cpu_primary_thread_mask); 24006a4d2657SThomas Gleixner } 24015da80b28SThomas Gleixner 24025da80b28SThomas Gleixner /* 24035da80b28SThomas Gleixner * Due to the utter mess of CPUID evaluation smp_num_siblings is not valid 24045da80b28SThomas Gleixner * during early boot. Initialize the primary thread mask before SMP 24055da80b28SThomas Gleixner * bringup. 24065da80b28SThomas Gleixner */ 24075da80b28SThomas Gleixner static int __init smp_init_primary_thread_mask(void) 24085da80b28SThomas Gleixner { 24095da80b28SThomas Gleixner unsigned int cpu; 24105da80b28SThomas Gleixner 24115da80b28SThomas Gleixner for (cpu = 0; cpu < nr_logical_cpuids; cpu++) 24125da80b28SThomas Gleixner cpu_mark_primary_thread(cpu, cpuid_to_apicid[cpu]); 24135da80b28SThomas Gleixner return 0; 24145da80b28SThomas Gleixner } 24155da80b28SThomas Gleixner early_initcall(smp_init_primary_thread_mask); 2416f54d4434SThomas Gleixner #else 2417f54d4434SThomas Gleixner static inline void cpu_mark_primary_thread(unsigned int cpu, unsigned int apicid) { } 2418d0055f35SVlastimil Babka #endif 24196a4d2657SThomas Gleixner 24208f54969dSGu Zheng /* 24218f54969dSGu Zheng * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids 24228f54969dSGu Zheng * and cpuid_to_apicid[] synchronized. 24238f54969dSGu Zheng */ 24248f54969dSGu Zheng static int allocate_logical_cpuid(int apicid) 24258f54969dSGu Zheng { 24268f54969dSGu Zheng int i; 24278f54969dSGu Zheng 24288f54969dSGu Zheng /* 24298f54969dSGu Zheng * cpuid <-> apicid mapping is persistent, so when a cpu is up, 24308f54969dSGu Zheng * check if the kernel has allocated a cpuid for it. 24318f54969dSGu Zheng */ 24328f54969dSGu Zheng for (i = 0; i < nr_logical_cpuids; i++) { 24338f54969dSGu Zheng if (cpuid_to_apicid[i] == apicid) 24348f54969dSGu Zheng return i; 24358f54969dSGu Zheng } 24368f54969dSGu Zheng 24378f54969dSGu Zheng /* Allocate a new cpuid. */ 24388f54969dSGu Zheng if (nr_logical_cpuids >= nr_cpu_ids) { 24399b130ad5SAlexey Dobriyan WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. " 24408f54969dSGu Zheng "Processor %d/0x%x and the rest are ignored.\n", 2441bb3f0a52SDou Liyang nr_cpu_ids, nr_logical_cpuids, apicid); 2442bb3f0a52SDou Liyang return -EINVAL; 24438f54969dSGu Zheng } 24448f54969dSGu Zheng 24458f54969dSGu Zheng cpuid_to_apicid[nr_logical_cpuids] = apicid; 24468f54969dSGu Zheng return nr_logical_cpuids++; 24478f54969dSGu Zheng } 24488f54969dSGu Zheng 24492b85b3d2SDou Liyang int generic_processor_info(int apicid, int version) 2450f62bae50SIngo Molnar { 245114cb6dcfSVivek Goyal int cpu, max = nr_cpu_ids; 245214cb6dcfSVivek Goyal bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, 245314cb6dcfSVivek Goyal phys_cpu_present_map); 245414cb6dcfSVivek Goyal 245514cb6dcfSVivek Goyal /* 2456151e0c7dSHATAYAMA Daisuke * boot_cpu_physical_apicid is designed to have the apicid 2457151e0c7dSHATAYAMA Daisuke * returned by read_apic_id(), i.e, the apicid of the 2458151e0c7dSHATAYAMA Daisuke * currently booting-up processor. However, on some platforms, 24595b4d1dbcSH. Peter Anvin * it is temporarily modified by the apicid reported as BSP 2460151e0c7dSHATAYAMA Daisuke * through MP table. Concretely: 2461151e0c7dSHATAYAMA Daisuke * 2462151e0c7dSHATAYAMA Daisuke * - arch/x86/kernel/mpparse.c: MP_processor_info() 2463151e0c7dSHATAYAMA Daisuke * - arch/x86/mm/amdtopology.c: amd_numa_init() 2464151e0c7dSHATAYAMA Daisuke * 2465151e0c7dSHATAYAMA Daisuke * This function is executed with the modified 2466151e0c7dSHATAYAMA Daisuke * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel 2467151e0c7dSHATAYAMA Daisuke * parameter doesn't work to disable APs on kdump 2nd kernel. 2468151e0c7dSHATAYAMA Daisuke * 2469151e0c7dSHATAYAMA Daisuke * Since fixing handling of boot_cpu_physical_apicid requires 2470151e0c7dSHATAYAMA Daisuke * another discussion and tests on each platform, we leave it 2471151e0c7dSHATAYAMA Daisuke * for now and here we use read_apic_id() directly in this 2472e2329b42SDou Liyang * function, generic_processor_info(). 2473151e0c7dSHATAYAMA Daisuke */ 2474151e0c7dSHATAYAMA Daisuke if (disabled_cpu_apicid != BAD_APICID && 2475151e0c7dSHATAYAMA Daisuke disabled_cpu_apicid != read_apic_id() && 2476151e0c7dSHATAYAMA Daisuke disabled_cpu_apicid == apicid) { 2477151e0c7dSHATAYAMA Daisuke int thiscpu = num_processors + disabled_cpus; 2478151e0c7dSHATAYAMA Daisuke 24798d3bcc44SKefeng Wang pr_warn("APIC: Disabling requested cpu." 24808d3bcc44SKefeng Wang " Processor %d/0x%x ignored.\n", thiscpu, apicid); 2481151e0c7dSHATAYAMA Daisuke 2482151e0c7dSHATAYAMA Daisuke disabled_cpus++; 2483151e0c7dSHATAYAMA Daisuke return -ENODEV; 2484151e0c7dSHATAYAMA Daisuke } 2485151e0c7dSHATAYAMA Daisuke 2486151e0c7dSHATAYAMA Daisuke /* 248714cb6dcfSVivek Goyal * If boot cpu has not been detected yet, then only allow upto 248814cb6dcfSVivek Goyal * nr_cpu_ids - 1 processors and keep one slot free for boot cpu 248914cb6dcfSVivek Goyal */ 249014cb6dcfSVivek Goyal if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && 249114cb6dcfSVivek Goyal apicid != boot_cpu_physical_apicid) { 249214cb6dcfSVivek Goyal int thiscpu = max + disabled_cpus - 1; 249314cb6dcfSVivek Goyal 24948d3bcc44SKefeng Wang pr_warn("APIC: NR_CPUS/possible_cpus limit of %i almost" 249514cb6dcfSVivek Goyal " reached. Keeping one slot for boot cpu." 249614cb6dcfSVivek Goyal " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 249714cb6dcfSVivek Goyal 249814cb6dcfSVivek Goyal disabled_cpus++; 24997e1f85f9SJiang Liu return -ENODEV; 250014cb6dcfSVivek Goyal } 2501f62bae50SIngo Molnar 2502f62bae50SIngo Molnar if (num_processors >= nr_cpu_ids) { 2503f62bae50SIngo Molnar int thiscpu = max + disabled_cpus; 2504f62bae50SIngo Molnar 25058d3bcc44SKefeng Wang pr_warn("APIC: NR_CPUS/possible_cpus limit of %i reached. " 25068d3bcc44SKefeng Wang "Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2507f62bae50SIngo Molnar 2508f62bae50SIngo Molnar disabled_cpus++; 25097e1f85f9SJiang Liu return -EINVAL; 2510f62bae50SIngo Molnar } 2511f62bae50SIngo Molnar 2512f62bae50SIngo Molnar if (apicid == boot_cpu_physical_apicid) { 2513f62bae50SIngo Molnar /* 2514f62bae50SIngo Molnar * x86_bios_cpu_apicid is required to have processors listed 2515f62bae50SIngo Molnar * in same order as logical cpu numbers. Hence the first 2516f62bae50SIngo Molnar * entry is BSP, and so on. 2517e5fea868SYinghai Lu * boot_cpu_init() already hold bit 0 in cpu_present_mask 2518e5fea868SYinghai Lu * for BSP. 2519f62bae50SIngo Molnar */ 2520f62bae50SIngo Molnar cpu = 0; 25218f54969dSGu Zheng 25228f54969dSGu Zheng /* Logical cpuid 0 is reserved for BSP. */ 25238f54969dSGu Zheng cpuid_to_apicid[0] = apicid; 25248f54969dSGu Zheng } else { 25258f54969dSGu Zheng cpu = allocate_logical_cpuid(apicid); 25268f54969dSGu Zheng if (cpu < 0) { 25278f54969dSGu Zheng disabled_cpus++; 25288f54969dSGu Zheng return -EINVAL; 25298f54969dSGu Zheng } 25308f54969dSGu Zheng } 2531e5fea868SYinghai Lu 2532e5fea868SYinghai Lu /* 2533e5fea868SYinghai Lu * Validate version 2534e5fea868SYinghai Lu */ 2535e5fea868SYinghai Lu if (version == 0x0) { 25368d3bcc44SKefeng Wang pr_warn("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", 2537e5fea868SYinghai Lu cpu, apicid); 2538e5fea868SYinghai Lu version = 0x10; 2539f62bae50SIngo Molnar } 2540e5fea868SYinghai Lu 2541cff9ab2bSDenys Vlasenko if (version != boot_cpu_apic_version) { 25428d3bcc44SKefeng Wang pr_warn("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", 2543cff9ab2bSDenys Vlasenko boot_cpu_apic_version, cpu, version); 2544e5fea868SYinghai Lu } 2545e5fea868SYinghai Lu 2546f62bae50SIngo Molnar if (apicid > max_physical_apicid) 2547f62bae50SIngo Molnar max_physical_apicid = apicid; 2548f62bae50SIngo Molnar 2549f62bae50SIngo Molnar #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 2550f62bae50SIngo Molnar early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 2551f62bae50SIngo Molnar early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 2552f62bae50SIngo Molnar #endif 2553acb8bc09STejun Heo #ifdef CONFIG_X86_32 2554acb8bc09STejun Heo early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 2555acb8bc09STejun Heo apic->x86_32_early_logical_apicid(cpu); 2556acb8bc09STejun Heo #endif 2557f62bae50SIngo Molnar set_cpu_possible(cpu, true); 2558f7c28833SGu Zheng physid_set(apicid, phys_cpu_present_map); 2559f62bae50SIngo Molnar set_cpu_present(cpu, true); 25602b85b3d2SDou Liyang num_processors++; 25617e1f85f9SJiang Liu 25625da80b28SThomas Gleixner if (system_state != SYSTEM_BOOTING) 2563f54d4434SThomas Gleixner cpu_mark_primary_thread(cpu, apicid); 2564f54d4434SThomas Gleixner 25657e1f85f9SJiang Liu return cpu; 2566f62bae50SIngo Molnar } 2567f62bae50SIngo Molnar 2568f62bae50SIngo Molnar int hard_smp_processor_id(void) 2569f62bae50SIngo Molnar { 2570f62bae50SIngo Molnar return read_apic_id(); 2571f62bae50SIngo Molnar } 2572f62bae50SIngo Molnar 2573f598181aSDavid Woodhouse void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg, 2574f598181aSDavid Woodhouse bool dmar) 2575f598181aSDavid Woodhouse { 25766285aa50SThomas Gleixner memset(msg, 0, sizeof(*msg)); 2577f598181aSDavid Woodhouse 25786285aa50SThomas Gleixner msg->arch_addr_lo.base_address = X86_MSI_BASE_ADDRESS_LOW; 25796285aa50SThomas Gleixner msg->arch_addr_lo.dest_mode_logical = apic->dest_mode_logical; 25806285aa50SThomas Gleixner msg->arch_addr_lo.destid_0_7 = cfg->dest_apicid & 0xFF; 2581f598181aSDavid Woodhouse 25826285aa50SThomas Gleixner msg->arch_data.delivery_mode = APIC_DELIVERY_MODE_FIXED; 25836285aa50SThomas Gleixner msg->arch_data.vector = cfg->vector; 2584f598181aSDavid Woodhouse 25856285aa50SThomas Gleixner msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH; 2586f598181aSDavid Woodhouse /* 2587f598181aSDavid Woodhouse * Only the IOMMU itself can use the trick of putting destination 2588f598181aSDavid Woodhouse * APIC ID into the high bits of the address. Anything else would 2589f598181aSDavid Woodhouse * just be writing to memory if it tried that, and needs IR to 2590ab0f59c6SDavid Woodhouse * address APICs which can't be addressed in the normal 32-bit 2591ab0f59c6SDavid Woodhouse * address range at 0xFFExxxxx. That is typically just 8 bits, but 2592ab0f59c6SDavid Woodhouse * some hypervisors allow the extended destination ID field in bits 2593ab0f59c6SDavid Woodhouse * 5-11 to be used, giving support for 15 bits of APIC IDs in total. 2594f598181aSDavid Woodhouse */ 2595f598181aSDavid Woodhouse if (dmar) 25966285aa50SThomas Gleixner msg->arch_addr_hi.destid_8_31 = cfg->dest_apicid >> 8; 2597ab0f59c6SDavid Woodhouse else if (virt_ext_dest_id && cfg->dest_apicid < 0x8000) 2598ab0f59c6SDavid Woodhouse msg->arch_addr_lo.virt_destid_8_14 = cfg->dest_apicid >> 8; 2599f598181aSDavid Woodhouse else 26006285aa50SThomas Gleixner WARN_ON_ONCE(cfg->dest_apicid > 0xFF); 2601f598181aSDavid Woodhouse } 2602f598181aSDavid Woodhouse 26036285aa50SThomas Gleixner u32 x86_msi_msg_get_destid(struct msi_msg *msg, bool extid) 26046285aa50SThomas Gleixner { 26056285aa50SThomas Gleixner u32 dest = msg->arch_addr_lo.destid_0_7; 26066285aa50SThomas Gleixner 26076285aa50SThomas Gleixner if (extid) 26086285aa50SThomas Gleixner dest |= msg->arch_addr_hi.destid_8_31 << 8; 26096285aa50SThomas Gleixner return dest; 26106285aa50SThomas Gleixner } 26116285aa50SThomas Gleixner EXPORT_SYMBOL_GPL(x86_msi_msg_get_destid); 26126285aa50SThomas Gleixner 2613f39642d0SKuppuswamy Sathyanarayanan #ifdef CONFIG_X86_64 2614f39642d0SKuppuswamy Sathyanarayanan void __init acpi_wake_cpu_handler_update(wakeup_cpu_handler handler) 2615f39642d0SKuppuswamy Sathyanarayanan { 2616f39642d0SKuppuswamy Sathyanarayanan struct apic **drv; 2617f39642d0SKuppuswamy Sathyanarayanan 2618f39642d0SKuppuswamy Sathyanarayanan for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) 2619f39642d0SKuppuswamy Sathyanarayanan (*drv)->wakeup_secondary_cpu_64 = handler; 2620f39642d0SKuppuswamy Sathyanarayanan } 2621f39642d0SKuppuswamy Sathyanarayanan #endif 2622f39642d0SKuppuswamy Sathyanarayanan 2623f62bae50SIngo Molnar /* 26241551df64SMichael S. Tsirkin * Override the generic EOI implementation with an optimized version. 26251551df64SMichael S. Tsirkin * Only called during early boot when only one CPU is active and with 26261551df64SMichael S. Tsirkin * interrupts disabled, so we know this does not race with actual APIC driver 26271551df64SMichael S. Tsirkin * use. 26281551df64SMichael S. Tsirkin */ 26291551df64SMichael S. Tsirkin void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) 26301551df64SMichael S. Tsirkin { 26311551df64SMichael S. Tsirkin struct apic **drv; 26321551df64SMichael S. Tsirkin 26331551df64SMichael S. Tsirkin for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { 26341551df64SMichael S. Tsirkin /* Should happen once for each apic */ 26351551df64SMichael S. Tsirkin WARN_ON((*drv)->eoi_write == eoi_write); 26368ca22552SWanpeng Li (*drv)->native_eoi_write = (*drv)->eoi_write; 26371551df64SMichael S. Tsirkin (*drv)->eoi_write = eoi_write; 26381551df64SMichael S. Tsirkin } 26391551df64SMichael S. Tsirkin } 26401551df64SMichael S. Tsirkin 2641374aab33SThomas Gleixner static void __init apic_bsp_up_setup(void) 264205f7e46dSThomas Gleixner { 2643374aab33SThomas Gleixner #ifdef CONFIG_X86_64 26445d64d209SDou Liyang apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid)); 2645374aab33SThomas Gleixner #else 264605f7e46dSThomas Gleixner /* 2647374aab33SThomas Gleixner * Hack: In case of kdump, after a crash, kernel might be booting 2648374aab33SThomas Gleixner * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 2649374aab33SThomas Gleixner * might be zero if read from MP tables. Get it from LAPIC. 265005f7e46dSThomas Gleixner */ 2651374aab33SThomas Gleixner # ifdef CONFIG_CRASH_DUMP 2652374aab33SThomas Gleixner boot_cpu_physical_apicid = read_apic_id(); 2653374aab33SThomas Gleixner # endif 2654374aab33SThomas Gleixner #endif 2655374aab33SThomas Gleixner physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 265605f7e46dSThomas Gleixner } 265705f7e46dSThomas Gleixner 265805f7e46dSThomas Gleixner /** 265905f7e46dSThomas Gleixner * apic_bsp_setup - Setup function for local apic and io-apic 2660374aab33SThomas Gleixner * @upmode: Force UP mode (for APIC_init_uniprocessor) 266105f7e46dSThomas Gleixner */ 2662748b170cSThomas Gleixner static void __init apic_bsp_setup(bool upmode) 266305f7e46dSThomas Gleixner { 266405f7e46dSThomas Gleixner connect_bsp_APIC(); 2665374aab33SThomas Gleixner if (upmode) 2666374aab33SThomas Gleixner apic_bsp_up_setup(); 266705f7e46dSThomas Gleixner setup_local_APIC(); 266805f7e46dSThomas Gleixner 266905f7e46dSThomas Gleixner enable_IO_APIC(); 2670374aab33SThomas Gleixner end_local_APIC_setup(); 2671374aab33SThomas Gleixner irq_remap_enable_fault_handling(); 267205f7e46dSThomas Gleixner setup_IO_APIC(); 26737d65f9e8SThomas Gleixner lapic_update_legacy_vectors(); 2674e714a91fSThomas Gleixner } 2675e714a91fSThomas Gleixner 267630b8b006SThomas Gleixner #ifdef CONFIG_UP_LATE_INIT 267730b8b006SThomas Gleixner void __init up_late_init(void) 267830b8b006SThomas Gleixner { 26790c759131SDou Liyang if (apic_intr_mode == APIC_PIC) 26800c759131SDou Liyang return; 26810c759131SDou Liyang 26820c759131SDou Liyang /* Setup local timer */ 26830c759131SDou Liyang x86_init.timers.setup_percpu_clockev(); 268430b8b006SThomas Gleixner } 268530b8b006SThomas Gleixner #endif 268630b8b006SThomas Gleixner 2687e714a91fSThomas Gleixner /* 2688f62bae50SIngo Molnar * Power management 2689f62bae50SIngo Molnar */ 2690f62bae50SIngo Molnar #ifdef CONFIG_PM 2691f62bae50SIngo Molnar 2692f62bae50SIngo Molnar static struct { 2693f62bae50SIngo Molnar /* 2694f62bae50SIngo Molnar * 'active' is true if the local APIC was enabled by us and 2695f62bae50SIngo Molnar * not the BIOS; this signifies that we are also responsible 2696f62bae50SIngo Molnar * for disabling it before entering apm/acpi suspend 2697f62bae50SIngo Molnar */ 2698f62bae50SIngo Molnar int active; 2699f62bae50SIngo Molnar /* r/w apic fields */ 2700f62bae50SIngo Molnar unsigned int apic_id; 2701f62bae50SIngo Molnar unsigned int apic_taskpri; 2702f62bae50SIngo Molnar unsigned int apic_ldr; 2703f62bae50SIngo Molnar unsigned int apic_dfr; 2704f62bae50SIngo Molnar unsigned int apic_spiv; 2705f62bae50SIngo Molnar unsigned int apic_lvtt; 2706f62bae50SIngo Molnar unsigned int apic_lvtpc; 2707f62bae50SIngo Molnar unsigned int apic_lvt0; 2708f62bae50SIngo Molnar unsigned int apic_lvt1; 2709f62bae50SIngo Molnar unsigned int apic_lvterr; 2710f62bae50SIngo Molnar unsigned int apic_tmict; 2711f62bae50SIngo Molnar unsigned int apic_tdcr; 2712f62bae50SIngo Molnar unsigned int apic_thmr; 271342baa258SJuergen Gross unsigned int apic_cmci; 2714f62bae50SIngo Molnar } apic_pm_state; 2715f62bae50SIngo Molnar 2716f3c6ea1bSRafael J. Wysocki static int lapic_suspend(void) 2717f62bae50SIngo Molnar { 2718f62bae50SIngo Molnar unsigned long flags; 2719f62bae50SIngo Molnar int maxlvt; 2720f62bae50SIngo Molnar 2721f62bae50SIngo Molnar if (!apic_pm_state.active) 2722f62bae50SIngo Molnar return 0; 2723f62bae50SIngo Molnar 2724f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 2725f62bae50SIngo Molnar 2726f62bae50SIngo Molnar apic_pm_state.apic_id = apic_read(APIC_ID); 2727f62bae50SIngo Molnar apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2728f62bae50SIngo Molnar apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2729f62bae50SIngo Molnar apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2730f62bae50SIngo Molnar apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2731f62bae50SIngo Molnar apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2732f62bae50SIngo Molnar if (maxlvt >= 4) 2733f62bae50SIngo Molnar apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2734f62bae50SIngo Molnar apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2735f62bae50SIngo Molnar apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2736f62bae50SIngo Molnar apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2737f62bae50SIngo Molnar apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2738f62bae50SIngo Molnar apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 27394efc0670SAndi Kleen #ifdef CONFIG_X86_THERMAL_VECTOR 2740f62bae50SIngo Molnar if (maxlvt >= 5) 2741f62bae50SIngo Molnar apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2742f62bae50SIngo Molnar #endif 274342baa258SJuergen Gross #ifdef CONFIG_X86_MCE_INTEL 274442baa258SJuergen Gross if (maxlvt >= 6) 274542baa258SJuergen Gross apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI); 274642baa258SJuergen Gross #endif 2747f62bae50SIngo Molnar 2748f62bae50SIngo Molnar local_irq_save(flags); 27490f378d73STony W Wang-oc 27500f378d73STony W Wang-oc /* 27510f378d73STony W Wang-oc * Mask IOAPIC before disabling the local APIC to prevent stale IRR 27520f378d73STony W Wang-oc * entries on some implementations. 27530f378d73STony W Wang-oc */ 27540f378d73STony W Wang-oc mask_ioapic_entries(); 27550f378d73STony W Wang-oc 2756f62bae50SIngo Molnar disable_local_APIC(); 2757fc1edaf9SSuresh Siddha 275895a02e97SSuresh Siddha irq_remapping_disable(); 2759fc1edaf9SSuresh Siddha 2760f62bae50SIngo Molnar local_irq_restore(flags); 2761f62bae50SIngo Molnar return 0; 2762f62bae50SIngo Molnar } 2763f62bae50SIngo Molnar 2764f3c6ea1bSRafael J. Wysocki static void lapic_resume(void) 2765f62bae50SIngo Molnar { 2766f62bae50SIngo Molnar unsigned int l, h; 2767f62bae50SIngo Molnar unsigned long flags; 276831dce14aSSuresh Siddha int maxlvt; 2769b24696bcSFenghua Yu 2770f62bae50SIngo Molnar if (!apic_pm_state.active) 2771f3c6ea1bSRafael J. Wysocki return; 2772f62bae50SIngo Molnar 2773b24696bcSFenghua Yu local_irq_save(flags); 2774336224baSJoerg Roedel 277531dce14aSSuresh Siddha /* 277631dce14aSSuresh Siddha * IO-APIC and PIC have their own resume routines. 277731dce14aSSuresh Siddha * We just mask them here to make sure the interrupt 277831dce14aSSuresh Siddha * subsystem is completely quiet while we enable x2apic 277931dce14aSSuresh Siddha * and interrupt-remapping. 278031dce14aSSuresh Siddha */ 278131dce14aSSuresh Siddha mask_ioapic_entries(); 2782b81bb373SJacob Pan legacy_pic->mask_all(); 2783f62bae50SIngo Molnar 2784659006bfSThomas Gleixner if (x2apic_mode) { 2785659006bfSThomas Gleixner __x2apic_enable(); 2786659006bfSThomas Gleixner } else { 2787f62bae50SIngo Molnar /* 2788f62bae50SIngo Molnar * Make sure the APICBASE points to the right address 2789f62bae50SIngo Molnar * 2790f62bae50SIngo Molnar * FIXME! This will be wrong if we ever support suspend on 2791f62bae50SIngo Molnar * SMP! We'll need to do this as part of the CPU restore! 2792f62bae50SIngo Molnar */ 2793cbf2829bSBryan O'Donoghue if (boot_cpu_data.x86 >= 6) { 2794f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, l, h); 2795f62bae50SIngo Molnar l &= ~MSR_IA32_APICBASE_BASE; 2796f62bae50SIngo Molnar l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2797f62bae50SIngo Molnar wrmsr(MSR_IA32_APICBASE, l, h); 2798f62bae50SIngo Molnar } 2799cbf2829bSBryan O'Donoghue } 2800f62bae50SIngo Molnar 2801b24696bcSFenghua Yu maxlvt = lapic_get_maxlvt(); 2802f62bae50SIngo Molnar apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2803f62bae50SIngo Molnar apic_write(APIC_ID, apic_pm_state.apic_id); 2804f62bae50SIngo Molnar apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2805f62bae50SIngo Molnar apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2806f62bae50SIngo Molnar apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2807f62bae50SIngo Molnar apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2808f62bae50SIngo Molnar apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2809f62bae50SIngo Molnar apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 281042baa258SJuergen Gross #ifdef CONFIG_X86_THERMAL_VECTOR 2811f62bae50SIngo Molnar if (maxlvt >= 5) 2812f62bae50SIngo Molnar apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2813f62bae50SIngo Molnar #endif 281442baa258SJuergen Gross #ifdef CONFIG_X86_MCE_INTEL 281542baa258SJuergen Gross if (maxlvt >= 6) 281642baa258SJuergen Gross apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci); 281742baa258SJuergen Gross #endif 2818f62bae50SIngo Molnar if (maxlvt >= 4) 2819f62bae50SIngo Molnar apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2820f62bae50SIngo Molnar apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2821f62bae50SIngo Molnar apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2822f62bae50SIngo Molnar apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2823f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 2824f62bae50SIngo Molnar apic_read(APIC_ESR); 2825f62bae50SIngo Molnar apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2826f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 2827f62bae50SIngo Molnar apic_read(APIC_ESR); 2828f62bae50SIngo Molnar 282995a02e97SSuresh Siddha irq_remapping_reenable(x2apic_mode); 283031dce14aSSuresh Siddha 2831f62bae50SIngo Molnar local_irq_restore(flags); 2832f62bae50SIngo Molnar } 2833f62bae50SIngo Molnar 2834f62bae50SIngo Molnar /* 2835f62bae50SIngo Molnar * This device has no shutdown method - fully functioning local APICs 2836f62bae50SIngo Molnar * are needed on every CPU up until machine_halt/restart/poweroff. 2837f62bae50SIngo Molnar */ 2838f62bae50SIngo Molnar 2839f3c6ea1bSRafael J. Wysocki static struct syscore_ops lapic_syscore_ops = { 2840f62bae50SIngo Molnar .resume = lapic_resume, 2841f62bae50SIngo Molnar .suspend = lapic_suspend, 2842f62bae50SIngo Molnar }; 2843f62bae50SIngo Molnar 2844148f9bb8SPaul Gortmaker static void apic_pm_activate(void) 2845f62bae50SIngo Molnar { 2846f62bae50SIngo Molnar apic_pm_state.active = 1; 2847f62bae50SIngo Molnar } 2848f62bae50SIngo Molnar 2849f62bae50SIngo Molnar static int __init init_lapic_sysfs(void) 2850f62bae50SIngo Molnar { 2851f62bae50SIngo Molnar /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 285293984fbdSBorislav Petkov if (boot_cpu_has(X86_FEATURE_APIC)) 2853f3c6ea1bSRafael J. Wysocki register_syscore_ops(&lapic_syscore_ops); 2854f62bae50SIngo Molnar 2855f3c6ea1bSRafael J. Wysocki return 0; 2856f62bae50SIngo Molnar } 2857b24696bcSFenghua Yu 2858b24696bcSFenghua Yu /* local apic needs to resume before other devices access its registers. */ 2859b24696bcSFenghua Yu core_initcall(init_lapic_sysfs); 2860f62bae50SIngo Molnar 2861f62bae50SIngo Molnar #else /* CONFIG_PM */ 2862f62bae50SIngo Molnar 2863f62bae50SIngo Molnar static void apic_pm_activate(void) { } 2864f62bae50SIngo Molnar 2865f62bae50SIngo Molnar #endif /* CONFIG_PM */ 2866f62bae50SIngo Molnar 2867f62bae50SIngo Molnar #ifdef CONFIG_X86_64 2868e0e42142SYinghai Lu 2869148f9bb8SPaul Gortmaker static int multi_checked; 2870148f9bb8SPaul Gortmaker static int multi; 2871e0e42142SYinghai Lu 2872148f9bb8SPaul Gortmaker static int set_multi(const struct dmi_system_id *d) 2873e0e42142SYinghai Lu { 2874e0e42142SYinghai Lu if (multi) 2875e0e42142SYinghai Lu return 0; 28766f0aced6SCyrill Gorcunov pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2877e0e42142SYinghai Lu multi = 1; 2878e0e42142SYinghai Lu return 0; 2879e0e42142SYinghai Lu } 2880e0e42142SYinghai Lu 2881148f9bb8SPaul Gortmaker static const struct dmi_system_id multi_dmi_table[] = { 2882e0e42142SYinghai Lu { 2883e0e42142SYinghai Lu .callback = set_multi, 2884e0e42142SYinghai Lu .ident = "IBM System Summit2", 2885e0e42142SYinghai Lu .matches = { 2886e0e42142SYinghai Lu DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2887e0e42142SYinghai Lu DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2888e0e42142SYinghai Lu }, 2889e0e42142SYinghai Lu }, 2890e0e42142SYinghai Lu {} 2891e0e42142SYinghai Lu }; 2892e0e42142SYinghai Lu 2893148f9bb8SPaul Gortmaker static void dmi_check_multi(void) 2894e0e42142SYinghai Lu { 2895e0e42142SYinghai Lu if (multi_checked) 2896e0e42142SYinghai Lu return; 2897e0e42142SYinghai Lu 2898e0e42142SYinghai Lu dmi_check_system(multi_dmi_table); 2899e0e42142SYinghai Lu multi_checked = 1; 2900e0e42142SYinghai Lu } 2901f62bae50SIngo Molnar 2902f62bae50SIngo Molnar /* 2903e0e42142SYinghai Lu * apic_is_clustered_box() -- Check if we can expect good TSC 2904e0e42142SYinghai Lu * 2905e0e42142SYinghai Lu * Thus far, the major user of this is IBM's Summit2 series: 2906e0e42142SYinghai Lu * Clustered boxes may have unsynced TSC problems if they are 2907e0e42142SYinghai Lu * multi-chassis. 2908e0e42142SYinghai Lu * Use DMI to check them 2909f62bae50SIngo Molnar */ 2910148f9bb8SPaul Gortmaker int apic_is_clustered_box(void) 2911e0e42142SYinghai Lu { 2912e0e42142SYinghai Lu dmi_check_multi(); 2913411cf9eeSOren Twaig return multi; 2914f62bae50SIngo Molnar } 2915f62bae50SIngo Molnar #endif 2916f62bae50SIngo Molnar 2917f62bae50SIngo Molnar /* 2918f62bae50SIngo Molnar * APIC command line parameters 2919f62bae50SIngo Molnar */ 2920f62bae50SIngo Molnar static int __init setup_disableapic(char *arg) 2921f62bae50SIngo Molnar { 2922*49062454SThomas Gleixner apic_is_disabled = true; 2923f62bae50SIngo Molnar setup_clear_cpu_cap(X86_FEATURE_APIC); 2924f62bae50SIngo Molnar return 0; 2925f62bae50SIngo Molnar } 2926f62bae50SIngo Molnar early_param("disableapic", setup_disableapic); 2927f62bae50SIngo Molnar 2928f62bae50SIngo Molnar /* same as disableapic, for compatibility */ 2929f62bae50SIngo Molnar static int __init setup_nolapic(char *arg) 2930f62bae50SIngo Molnar { 2931f62bae50SIngo Molnar return setup_disableapic(arg); 2932f62bae50SIngo Molnar } 2933f62bae50SIngo Molnar early_param("nolapic", setup_nolapic); 2934f62bae50SIngo Molnar 2935f62bae50SIngo Molnar static int __init parse_lapic_timer_c2_ok(char *arg) 2936f62bae50SIngo Molnar { 2937f62bae50SIngo Molnar local_apic_timer_c2_ok = 1; 2938f62bae50SIngo Molnar return 0; 2939f62bae50SIngo Molnar } 2940f62bae50SIngo Molnar early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2941f62bae50SIngo Molnar 2942f62bae50SIngo Molnar static int __init parse_disable_apic_timer(char *arg) 2943f62bae50SIngo Molnar { 2944f62bae50SIngo Molnar disable_apic_timer = 1; 2945f62bae50SIngo Molnar return 0; 2946f62bae50SIngo Molnar } 2947f62bae50SIngo Molnar early_param("noapictimer", parse_disable_apic_timer); 2948f62bae50SIngo Molnar 2949f62bae50SIngo Molnar static int __init parse_nolapic_timer(char *arg) 2950f62bae50SIngo Molnar { 2951f62bae50SIngo Molnar disable_apic_timer = 1; 2952f62bae50SIngo Molnar return 0; 2953f62bae50SIngo Molnar } 2954f62bae50SIngo Molnar early_param("nolapic_timer", parse_nolapic_timer); 2955f62bae50SIngo Molnar 2956f62bae50SIngo Molnar static int __init apic_set_verbosity(char *arg) 2957f62bae50SIngo Molnar { 2958f62bae50SIngo Molnar if (!arg) { 2959f62bae50SIngo Molnar #ifdef CONFIG_X86_64 2960f62bae50SIngo Molnar skip_ioapic_setup = 0; 2961f62bae50SIngo Molnar return 0; 2962f62bae50SIngo Molnar #endif 2963f62bae50SIngo Molnar return -EINVAL; 2964f62bae50SIngo Molnar } 2965f62bae50SIngo Molnar 2966f62bae50SIngo Molnar if (strcmp("debug", arg) == 0) 2967f62bae50SIngo Molnar apic_verbosity = APIC_DEBUG; 2968f62bae50SIngo Molnar else if (strcmp("verbose", arg) == 0) 2969f62bae50SIngo Molnar apic_verbosity = APIC_VERBOSE; 29704fcab669SDou Liyang #ifdef CONFIG_X86_64 2971f62bae50SIngo Molnar else { 29728d3bcc44SKefeng Wang pr_warn("APIC Verbosity level %s not recognised" 2973f62bae50SIngo Molnar " use apic=verbose or apic=debug\n", arg); 2974f62bae50SIngo Molnar return -EINVAL; 2975f62bae50SIngo Molnar } 29764fcab669SDou Liyang #endif 2977f62bae50SIngo Molnar 2978f62bae50SIngo Molnar return 0; 2979f62bae50SIngo Molnar } 2980f62bae50SIngo Molnar early_param("apic", apic_set_verbosity); 2981f62bae50SIngo Molnar 2982f62bae50SIngo Molnar static int __init lapic_insert_resource(void) 2983f62bae50SIngo Molnar { 2984f62bae50SIngo Molnar if (!apic_phys) 2985f62bae50SIngo Molnar return -1; 2986f62bae50SIngo Molnar 2987f62bae50SIngo Molnar /* Put local APIC into the resource map. */ 2988f62bae50SIngo Molnar lapic_resource.start = apic_phys; 2989f62bae50SIngo Molnar lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2990f62bae50SIngo Molnar insert_resource(&iomem_resource, &lapic_resource); 2991f62bae50SIngo Molnar 2992f62bae50SIngo Molnar return 0; 2993f62bae50SIngo Molnar } 2994f62bae50SIngo Molnar 2995f62bae50SIngo Molnar /* 29961506c8dcSIngo Molnar * need call insert after e820__reserve_resources() 2997f62bae50SIngo Molnar * that is using request_resource 2998f62bae50SIngo Molnar */ 2999f62bae50SIngo Molnar late_initcall(lapic_insert_resource); 3000151e0c7dSHATAYAMA Daisuke 3001151e0c7dSHATAYAMA Daisuke static int __init apic_set_disabled_cpu_apicid(char *arg) 3002151e0c7dSHATAYAMA Daisuke { 3003151e0c7dSHATAYAMA Daisuke if (!arg || !get_option(&arg, &disabled_cpu_apicid)) 3004151e0c7dSHATAYAMA Daisuke return -EINVAL; 3005151e0c7dSHATAYAMA Daisuke 3006151e0c7dSHATAYAMA Daisuke return 0; 3007151e0c7dSHATAYAMA Daisuke } 3008151e0c7dSHATAYAMA Daisuke early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); 3009b7c4948eSHidehiro Kawai 3010b7c4948eSHidehiro Kawai static int __init apic_set_extnmi(char *arg) 3011b7c4948eSHidehiro Kawai { 3012b7c4948eSHidehiro Kawai if (!arg) 3013b7c4948eSHidehiro Kawai return -EINVAL; 3014b7c4948eSHidehiro Kawai 3015b7c4948eSHidehiro Kawai if (!strncmp("all", arg, 3)) 3016b7c4948eSHidehiro Kawai apic_extnmi = APIC_EXTNMI_ALL; 3017b7c4948eSHidehiro Kawai else if (!strncmp("none", arg, 4)) 3018b7c4948eSHidehiro Kawai apic_extnmi = APIC_EXTNMI_NONE; 3019b7c4948eSHidehiro Kawai else if (!strncmp("bsp", arg, 3)) 3020b7c4948eSHidehiro Kawai apic_extnmi = APIC_EXTNMI_BSP; 3021b7c4948eSHidehiro Kawai else { 3022b7c4948eSHidehiro Kawai pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg); 3023b7c4948eSHidehiro Kawai return -EINVAL; 3024b7c4948eSHidehiro Kawai } 3025b7c4948eSHidehiro Kawai 3026b7c4948eSHidehiro Kawai return 0; 3027b7c4948eSHidehiro Kawai } 3028b7c4948eSHidehiro Kawai early_param("apic_extnmi", apic_set_extnmi); 3029