1f62bae50SIngo Molnar /* 2f62bae50SIngo Molnar * Local APIC handling, local APIC timers 3f62bae50SIngo Molnar * 4f62bae50SIngo Molnar * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 5f62bae50SIngo Molnar * 6f62bae50SIngo Molnar * Fixes 7f62bae50SIngo Molnar * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8f62bae50SIngo Molnar * thanks to Eric Gilmore 9f62bae50SIngo Molnar * and Rolf G. Tews 10f62bae50SIngo Molnar * for testing these extensively. 11f62bae50SIngo Molnar * Maciej W. Rozycki : Various updates and fixes. 12f62bae50SIngo Molnar * Mikael Pettersson : Power Management for UP-APIC. 13f62bae50SIngo Molnar * Pavel Machek and 14f62bae50SIngo Molnar * Mikael Pettersson : PM converted to driver model. 15f62bae50SIngo Molnar */ 16f62bae50SIngo Molnar 17f62bae50SIngo Molnar #include <linux/kernel_stat.h> 18f62bae50SIngo Molnar #include <linux/mc146818rtc.h> 19f62bae50SIngo Molnar #include <linux/acpi_pmtmr.h> 20f62bae50SIngo Molnar #include <linux/clockchips.h> 21f62bae50SIngo Molnar #include <linux/interrupt.h> 22f62bae50SIngo Molnar #include <linux/bootmem.h> 23f62bae50SIngo Molnar #include <linux/ftrace.h> 24f62bae50SIngo Molnar #include <linux/ioport.h> 25f62bae50SIngo Molnar #include <linux/module.h> 26f62bae50SIngo Molnar #include <linux/sysdev.h> 27f62bae50SIngo Molnar #include <linux/delay.h> 28f62bae50SIngo Molnar #include <linux/timex.h> 29f62bae50SIngo Molnar #include <linux/dmar.h> 30f62bae50SIngo Molnar #include <linux/init.h> 31f62bae50SIngo Molnar #include <linux/cpu.h> 32f62bae50SIngo Molnar #include <linux/dmi.h> 33f62bae50SIngo Molnar #include <linux/nmi.h> 34f62bae50SIngo Molnar #include <linux/smp.h> 35f62bae50SIngo Molnar #include <linux/mm.h> 36f62bae50SIngo Molnar 37f62bae50SIngo Molnar #include <asm/pgalloc.h> 38f62bae50SIngo Molnar #include <asm/atomic.h> 39f62bae50SIngo Molnar #include <asm/mpspec.h> 40f62bae50SIngo Molnar #include <asm/i8253.h> 41f62bae50SIngo Molnar #include <asm/i8259.h> 42f62bae50SIngo Molnar #include <asm/proto.h> 43f62bae50SIngo Molnar #include <asm/apic.h> 44f62bae50SIngo Molnar #include <asm/desc.h> 45f62bae50SIngo Molnar #include <asm/hpet.h> 46f62bae50SIngo Molnar #include <asm/idle.h> 47f62bae50SIngo Molnar #include <asm/mtrr.h> 48f62bae50SIngo Molnar #include <asm/smp.h> 49638bee71SH. Peter Anvin #include <asm/mce.h> 50f62bae50SIngo Molnar 51f62bae50SIngo Molnar unsigned int num_processors; 52f62bae50SIngo Molnar 53f62bae50SIngo Molnar unsigned disabled_cpus __cpuinitdata; 54f62bae50SIngo Molnar 55f62bae50SIngo Molnar /* Processor that is doing the boot up */ 56f62bae50SIngo Molnar unsigned int boot_cpu_physical_apicid = -1U; 57f62bae50SIngo Molnar 58f62bae50SIngo Molnar /* 59f62bae50SIngo Molnar * The highest APIC ID seen during enumeration. 60f62bae50SIngo Molnar * 61f62bae50SIngo Molnar * This determines the messaging protocol we can use: if all APIC IDs 62f62bae50SIngo Molnar * are in the 0 ... 7 range, then we can use logical addressing which 63f62bae50SIngo Molnar * has some performance advantages (better broadcasting). 64f62bae50SIngo Molnar * 65f62bae50SIngo Molnar * If there's an APIC ID above 8, we use physical addressing. 66f62bae50SIngo Molnar */ 67f62bae50SIngo Molnar unsigned int max_physical_apicid; 68f62bae50SIngo Molnar 69f62bae50SIngo Molnar /* 70f62bae50SIngo Molnar * Bitmask of physically existing CPUs: 71f62bae50SIngo Molnar */ 72f62bae50SIngo Molnar physid_mask_t phys_cpu_present_map; 73f62bae50SIngo Molnar 74f62bae50SIngo Molnar /* 75f62bae50SIngo Molnar * Map cpu index to physical APIC ID 76f62bae50SIngo Molnar */ 77f62bae50SIngo Molnar DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID); 78f62bae50SIngo Molnar DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID); 79f62bae50SIngo Molnar EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 80f62bae50SIngo Molnar EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 81f62bae50SIngo Molnar 82f62bae50SIngo Molnar #ifdef CONFIG_X86_32 83f62bae50SIngo Molnar /* 84f62bae50SIngo Molnar * Knob to control our willingness to enable the local APIC. 85f62bae50SIngo Molnar * 86f62bae50SIngo Molnar * +1=force-enable 87f62bae50SIngo Molnar */ 88f62bae50SIngo Molnar static int force_enable_local_apic; 89f62bae50SIngo Molnar /* 90f62bae50SIngo Molnar * APIC command line parameters 91f62bae50SIngo Molnar */ 92f62bae50SIngo Molnar static int __init parse_lapic(char *arg) 93f62bae50SIngo Molnar { 94f62bae50SIngo Molnar force_enable_local_apic = 1; 95f62bae50SIngo Molnar return 0; 96f62bae50SIngo Molnar } 97f62bae50SIngo Molnar early_param("lapic", parse_lapic); 98f62bae50SIngo Molnar /* Local APIC was disabled by the BIOS and enabled by the kernel */ 99f62bae50SIngo Molnar static int enabled_via_apicbase; 100f62bae50SIngo Molnar 101c0eaa453SCyrill Gorcunov /* 102c0eaa453SCyrill Gorcunov * Handle interrupt mode configuration register (IMCR). 103c0eaa453SCyrill Gorcunov * This register controls whether the interrupt signals 104c0eaa453SCyrill Gorcunov * that reach the BSP come from the master PIC or from the 105c0eaa453SCyrill Gorcunov * local APIC. Before entering Symmetric I/O Mode, either 106c0eaa453SCyrill Gorcunov * the BIOS or the operating system must switch out of 107c0eaa453SCyrill Gorcunov * PIC Mode by changing the IMCR. 108c0eaa453SCyrill Gorcunov */ 1095cda395fSAlexander van Heukelum static inline void imcr_pic_to_apic(void) 110c0eaa453SCyrill Gorcunov { 111c0eaa453SCyrill Gorcunov /* select IMCR register */ 112c0eaa453SCyrill Gorcunov outb(0x70, 0x22); 113c0eaa453SCyrill Gorcunov /* NMI and 8259 INTR go through APIC */ 114c0eaa453SCyrill Gorcunov outb(0x01, 0x23); 115c0eaa453SCyrill Gorcunov } 116c0eaa453SCyrill Gorcunov 1175cda395fSAlexander van Heukelum static inline void imcr_apic_to_pic(void) 118c0eaa453SCyrill Gorcunov { 119c0eaa453SCyrill Gorcunov /* select IMCR register */ 120c0eaa453SCyrill Gorcunov outb(0x70, 0x22); 121c0eaa453SCyrill Gorcunov /* NMI and 8259 INTR go directly to BSP */ 122c0eaa453SCyrill Gorcunov outb(0x00, 0x23); 123c0eaa453SCyrill Gorcunov } 124f62bae50SIngo Molnar #endif 125f62bae50SIngo Molnar 126f62bae50SIngo Molnar #ifdef CONFIG_X86_64 127f62bae50SIngo Molnar static int apic_calibrate_pmtmr __initdata; 128f62bae50SIngo Molnar static __init int setup_apicpmtimer(char *s) 129f62bae50SIngo Molnar { 130f62bae50SIngo Molnar apic_calibrate_pmtmr = 1; 131f62bae50SIngo Molnar notsc_setup(NULL); 132f62bae50SIngo Molnar return 0; 133f62bae50SIngo Molnar } 134f62bae50SIngo Molnar __setup("apicpmtimer", setup_apicpmtimer); 135f62bae50SIngo Molnar #endif 136f62bae50SIngo Molnar 137fc1edaf9SSuresh Siddha int x2apic_mode; 138f62bae50SIngo Molnar #ifdef CONFIG_X86_X2APIC 139f62bae50SIngo Molnar /* x2apic enabled before OS handover */ 140f62bae50SIngo Molnar static int x2apic_preenabled; 141f62bae50SIngo Molnar static int disable_x2apic; 142f62bae50SIngo Molnar static __init int setup_nox2apic(char *str) 143f62bae50SIngo Molnar { 14439d83a5dSSuresh Siddha if (x2apic_enabled()) { 14539d83a5dSSuresh Siddha pr_warning("Bios already enabled x2apic, " 14639d83a5dSSuresh Siddha "can't enforce nox2apic"); 14739d83a5dSSuresh Siddha return 0; 14839d83a5dSSuresh Siddha } 14939d83a5dSSuresh Siddha 150f62bae50SIngo Molnar disable_x2apic = 1; 151f62bae50SIngo Molnar setup_clear_cpu_cap(X86_FEATURE_X2APIC); 152f62bae50SIngo Molnar return 0; 153f62bae50SIngo Molnar } 154f62bae50SIngo Molnar early_param("nox2apic", setup_nox2apic); 155f62bae50SIngo Molnar #endif 156f62bae50SIngo Molnar 157f62bae50SIngo Molnar unsigned long mp_lapic_addr; 158f62bae50SIngo Molnar int disable_apic; 159f62bae50SIngo Molnar /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 160f62bae50SIngo Molnar static int disable_apic_timer __cpuinitdata; 161f62bae50SIngo Molnar /* Local APIC timer works in C2 */ 162f62bae50SIngo Molnar int local_apic_timer_c2_ok; 163f62bae50SIngo Molnar EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 164f62bae50SIngo Molnar 165f62bae50SIngo Molnar int first_system_vector = 0xfe; 166f62bae50SIngo Molnar 167f62bae50SIngo Molnar /* 168f62bae50SIngo Molnar * Debug level, exported for io_apic.c 169f62bae50SIngo Molnar */ 170f62bae50SIngo Molnar unsigned int apic_verbosity; 171f62bae50SIngo Molnar 172f62bae50SIngo Molnar int pic_mode; 173f62bae50SIngo Molnar 174f62bae50SIngo Molnar /* Have we found an MP table */ 175f62bae50SIngo Molnar int smp_found_config; 176f62bae50SIngo Molnar 177f62bae50SIngo Molnar static struct resource lapic_resource = { 178f62bae50SIngo Molnar .name = "Local APIC", 179f62bae50SIngo Molnar .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 180f62bae50SIngo Molnar }; 181f62bae50SIngo Molnar 182f62bae50SIngo Molnar static unsigned int calibration_result; 183f62bae50SIngo Molnar 184f62bae50SIngo Molnar static int lapic_next_event(unsigned long delta, 185f62bae50SIngo Molnar struct clock_event_device *evt); 186f62bae50SIngo Molnar static void lapic_timer_setup(enum clock_event_mode mode, 187f62bae50SIngo Molnar struct clock_event_device *evt); 188f62bae50SIngo Molnar static void lapic_timer_broadcast(const struct cpumask *mask); 189f62bae50SIngo Molnar static void apic_pm_activate(void); 190f62bae50SIngo Molnar 191f62bae50SIngo Molnar /* 192f62bae50SIngo Molnar * The local apic timer can be used for any function which is CPU local. 193f62bae50SIngo Molnar */ 194f62bae50SIngo Molnar static struct clock_event_device lapic_clockevent = { 195f62bae50SIngo Molnar .name = "lapic", 196f62bae50SIngo Molnar .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT 197f62bae50SIngo Molnar | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, 198f62bae50SIngo Molnar .shift = 32, 199f62bae50SIngo Molnar .set_mode = lapic_timer_setup, 200f62bae50SIngo Molnar .set_next_event = lapic_next_event, 201f62bae50SIngo Molnar .broadcast = lapic_timer_broadcast, 202f62bae50SIngo Molnar .rating = 100, 203f62bae50SIngo Molnar .irq = -1, 204f62bae50SIngo Molnar }; 205f62bae50SIngo Molnar static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 206f62bae50SIngo Molnar 207f62bae50SIngo Molnar static unsigned long apic_phys; 208f62bae50SIngo Molnar 209f62bae50SIngo Molnar /* 210f62bae50SIngo Molnar * Get the LAPIC version 211f62bae50SIngo Molnar */ 212f62bae50SIngo Molnar static inline int lapic_get_version(void) 213f62bae50SIngo Molnar { 214f62bae50SIngo Molnar return GET_APIC_VERSION(apic_read(APIC_LVR)); 215f62bae50SIngo Molnar } 216f62bae50SIngo Molnar 217f62bae50SIngo Molnar /* 218f62bae50SIngo Molnar * Check, if the APIC is integrated or a separate chip 219f62bae50SIngo Molnar */ 220f62bae50SIngo Molnar static inline int lapic_is_integrated(void) 221f62bae50SIngo Molnar { 222f62bae50SIngo Molnar #ifdef CONFIG_X86_64 223f62bae50SIngo Molnar return 1; 224f62bae50SIngo Molnar #else 225f62bae50SIngo Molnar return APIC_INTEGRATED(lapic_get_version()); 226f62bae50SIngo Molnar #endif 227f62bae50SIngo Molnar } 228f62bae50SIngo Molnar 229f62bae50SIngo Molnar /* 230f62bae50SIngo Molnar * Check, whether this is a modern or a first generation APIC 231f62bae50SIngo Molnar */ 232f62bae50SIngo Molnar static int modern_apic(void) 233f62bae50SIngo Molnar { 234f62bae50SIngo Molnar /* AMD systems use old APIC versions, so check the CPU */ 235f62bae50SIngo Molnar if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 236f62bae50SIngo Molnar boot_cpu_data.x86 >= 0xf) 237f62bae50SIngo Molnar return 1; 238f62bae50SIngo Molnar return lapic_get_version() >= 0x14; 239f62bae50SIngo Molnar } 240f62bae50SIngo Molnar 24108306ce6SCyrill Gorcunov /* 24208306ce6SCyrill Gorcunov * bare function to substitute write operation 24308306ce6SCyrill Gorcunov * and it's _that_ fast :) 24408306ce6SCyrill Gorcunov */ 2454797f6b0SYinghai Lu static void native_apic_write_dummy(u32 reg, u32 v) 24608306ce6SCyrill Gorcunov { 24708306ce6SCyrill Gorcunov WARN_ON_ONCE((cpu_has_apic || !disable_apic)); 24808306ce6SCyrill Gorcunov } 24908306ce6SCyrill Gorcunov 2504797f6b0SYinghai Lu static u32 native_apic_read_dummy(u32 reg) 2514797f6b0SYinghai Lu { 2524797f6b0SYinghai Lu WARN_ON_ONCE((cpu_has_apic || !disable_apic)); 2534797f6b0SYinghai Lu return 0; 2544797f6b0SYinghai Lu } 2554797f6b0SYinghai Lu 25608306ce6SCyrill Gorcunov /* 2574797f6b0SYinghai Lu * right after this call apic->write/read doesn't do anything 25808306ce6SCyrill Gorcunov * note that there is no restore operation it works one way 25908306ce6SCyrill Gorcunov */ 26008306ce6SCyrill Gorcunov void apic_disable(void) 26108306ce6SCyrill Gorcunov { 2624797f6b0SYinghai Lu apic->read = native_apic_read_dummy; 26308306ce6SCyrill Gorcunov apic->write = native_apic_write_dummy; 26408306ce6SCyrill Gorcunov } 26508306ce6SCyrill Gorcunov 266f62bae50SIngo Molnar void native_apic_wait_icr_idle(void) 267f62bae50SIngo Molnar { 268f62bae50SIngo Molnar while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 269f62bae50SIngo Molnar cpu_relax(); 270f62bae50SIngo Molnar } 271f62bae50SIngo Molnar 272f62bae50SIngo Molnar u32 native_safe_apic_wait_icr_idle(void) 273f62bae50SIngo Molnar { 274f62bae50SIngo Molnar u32 send_status; 275f62bae50SIngo Molnar int timeout; 276f62bae50SIngo Molnar 277f62bae50SIngo Molnar timeout = 0; 278f62bae50SIngo Molnar do { 279f62bae50SIngo Molnar send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 280f62bae50SIngo Molnar if (!send_status) 281f62bae50SIngo Molnar break; 282f62bae50SIngo Molnar udelay(100); 283f62bae50SIngo Molnar } while (timeout++ < 1000); 284f62bae50SIngo Molnar 285f62bae50SIngo Molnar return send_status; 286f62bae50SIngo Molnar } 287f62bae50SIngo Molnar 288f62bae50SIngo Molnar void native_apic_icr_write(u32 low, u32 id) 289f62bae50SIngo Molnar { 290f62bae50SIngo Molnar apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 291f62bae50SIngo Molnar apic_write(APIC_ICR, low); 292f62bae50SIngo Molnar } 293f62bae50SIngo Molnar 294f62bae50SIngo Molnar u64 native_apic_icr_read(void) 295f62bae50SIngo Molnar { 296f62bae50SIngo Molnar u32 icr1, icr2; 297f62bae50SIngo Molnar 298f62bae50SIngo Molnar icr2 = apic_read(APIC_ICR2); 299f62bae50SIngo Molnar icr1 = apic_read(APIC_ICR); 300f62bae50SIngo Molnar 301f62bae50SIngo Molnar return icr1 | ((u64)icr2 << 32); 302f62bae50SIngo Molnar } 303f62bae50SIngo Molnar 304f62bae50SIngo Molnar /** 305f62bae50SIngo Molnar * enable_NMI_through_LVT0 - enable NMI through local vector table 0 306f62bae50SIngo Molnar */ 307f62bae50SIngo Molnar void __cpuinit enable_NMI_through_LVT0(void) 308f62bae50SIngo Molnar { 309f62bae50SIngo Molnar unsigned int v; 310f62bae50SIngo Molnar 311f62bae50SIngo Molnar /* unmask and set to NMI */ 312f62bae50SIngo Molnar v = APIC_DM_NMI; 313f62bae50SIngo Molnar 314f62bae50SIngo Molnar /* Level triggered for 82489DX (32bit mode) */ 315f62bae50SIngo Molnar if (!lapic_is_integrated()) 316f62bae50SIngo Molnar v |= APIC_LVT_LEVEL_TRIGGER; 317f62bae50SIngo Molnar 318f62bae50SIngo Molnar apic_write(APIC_LVT0, v); 319f62bae50SIngo Molnar } 320f62bae50SIngo Molnar 321f62bae50SIngo Molnar #ifdef CONFIG_X86_32 322f62bae50SIngo Molnar /** 323f62bae50SIngo Molnar * get_physical_broadcast - Get number of physical broadcast IDs 324f62bae50SIngo Molnar */ 325f62bae50SIngo Molnar int get_physical_broadcast(void) 326f62bae50SIngo Molnar { 327f62bae50SIngo Molnar return modern_apic() ? 0xff : 0xf; 328f62bae50SIngo Molnar } 329f62bae50SIngo Molnar #endif 330f62bae50SIngo Molnar 331f62bae50SIngo Molnar /** 332f62bae50SIngo Molnar * lapic_get_maxlvt - get the maximum number of local vector table entries 333f62bae50SIngo Molnar */ 334f62bae50SIngo Molnar int lapic_get_maxlvt(void) 335f62bae50SIngo Molnar { 336f62bae50SIngo Molnar unsigned int v; 337f62bae50SIngo Molnar 338f62bae50SIngo Molnar v = apic_read(APIC_LVR); 339f62bae50SIngo Molnar /* 340f62bae50SIngo Molnar * - we always have APIC integrated on 64bit mode 341f62bae50SIngo Molnar * - 82489DXs do not report # of LVT entries 342f62bae50SIngo Molnar */ 343f62bae50SIngo Molnar return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; 344f62bae50SIngo Molnar } 345f62bae50SIngo Molnar 346f62bae50SIngo Molnar /* 347f62bae50SIngo Molnar * Local APIC timer 348f62bae50SIngo Molnar */ 349f62bae50SIngo Molnar 350f62bae50SIngo Molnar /* Clock divisor */ 351f62bae50SIngo Molnar #define APIC_DIVISOR 16 352f62bae50SIngo Molnar 353f62bae50SIngo Molnar /* 354f62bae50SIngo Molnar * This function sets up the local APIC timer, with a timeout of 355f62bae50SIngo Molnar * 'clocks' APIC bus clock. During calibration we actually call 356f62bae50SIngo Molnar * this function twice on the boot CPU, once with a bogus timeout 357f62bae50SIngo Molnar * value, second time for real. The other (noncalibrating) CPUs 358f62bae50SIngo Molnar * call this function only once, with the real, calibrated value. 359f62bae50SIngo Molnar * 360f62bae50SIngo Molnar * We do reads before writes even if unnecessary, to get around the 361f62bae50SIngo Molnar * P5 APIC double write bug. 362f62bae50SIngo Molnar */ 363f62bae50SIngo Molnar static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 364f62bae50SIngo Molnar { 365f62bae50SIngo Molnar unsigned int lvtt_value, tmp_value; 366f62bae50SIngo Molnar 367f62bae50SIngo Molnar lvtt_value = LOCAL_TIMER_VECTOR; 368f62bae50SIngo Molnar if (!oneshot) 369f62bae50SIngo Molnar lvtt_value |= APIC_LVT_TIMER_PERIODIC; 370f62bae50SIngo Molnar if (!lapic_is_integrated()) 371f62bae50SIngo Molnar lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 372f62bae50SIngo Molnar 373f62bae50SIngo Molnar if (!irqen) 374f62bae50SIngo Molnar lvtt_value |= APIC_LVT_MASKED; 375f62bae50SIngo Molnar 376f62bae50SIngo Molnar apic_write(APIC_LVTT, lvtt_value); 377f62bae50SIngo Molnar 378f62bae50SIngo Molnar /* 379f62bae50SIngo Molnar * Divide PICLK by 16 380f62bae50SIngo Molnar */ 381f62bae50SIngo Molnar tmp_value = apic_read(APIC_TDCR); 382f62bae50SIngo Molnar apic_write(APIC_TDCR, 383f62bae50SIngo Molnar (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 384f62bae50SIngo Molnar APIC_TDR_DIV_16); 385f62bae50SIngo Molnar 386f62bae50SIngo Molnar if (!oneshot) 387f62bae50SIngo Molnar apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 388f62bae50SIngo Molnar } 389f62bae50SIngo Molnar 390f62bae50SIngo Molnar /* 391f62bae50SIngo Molnar * Setup extended LVT, AMD specific (K8, family 10h) 392f62bae50SIngo Molnar * 393f62bae50SIngo Molnar * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and 394f62bae50SIngo Molnar * MCE interrupts are supported. Thus MCE offset must be set to 0. 395f62bae50SIngo Molnar * 396f62bae50SIngo Molnar * If mask=1, the LVT entry does not generate interrupts while mask=0 397f62bae50SIngo Molnar * enables the vector. See also the BKDGs. 398f62bae50SIngo Molnar */ 399f62bae50SIngo Molnar 400f62bae50SIngo Molnar #define APIC_EILVT_LVTOFF_MCE 0 401f62bae50SIngo Molnar #define APIC_EILVT_LVTOFF_IBS 1 402f62bae50SIngo Molnar 403f62bae50SIngo Molnar static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) 404f62bae50SIngo Molnar { 40597a52714SAndreas Herrmann unsigned long reg = (lvt_off << 4) + APIC_EILVTn(0); 406f62bae50SIngo Molnar unsigned int v = (mask << 16) | (msg_type << 8) | vector; 407f62bae50SIngo Molnar 408f62bae50SIngo Molnar apic_write(reg, v); 409f62bae50SIngo Molnar } 410f62bae50SIngo Molnar 411f62bae50SIngo Molnar u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) 412f62bae50SIngo Molnar { 413f62bae50SIngo Molnar setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); 414f62bae50SIngo Molnar return APIC_EILVT_LVTOFF_MCE; 415f62bae50SIngo Molnar } 416f62bae50SIngo Molnar 417f62bae50SIngo Molnar u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) 418f62bae50SIngo Molnar { 419f62bae50SIngo Molnar setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); 420f62bae50SIngo Molnar return APIC_EILVT_LVTOFF_IBS; 421f62bae50SIngo Molnar } 422f62bae50SIngo Molnar EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs); 423f62bae50SIngo Molnar 424f62bae50SIngo Molnar /* 425f62bae50SIngo Molnar * Program the next event, relative to now 426f62bae50SIngo Molnar */ 427f62bae50SIngo Molnar static int lapic_next_event(unsigned long delta, 428f62bae50SIngo Molnar struct clock_event_device *evt) 429f62bae50SIngo Molnar { 430f62bae50SIngo Molnar apic_write(APIC_TMICT, delta); 431f62bae50SIngo Molnar return 0; 432f62bae50SIngo Molnar } 433f62bae50SIngo Molnar 434f62bae50SIngo Molnar /* 435f62bae50SIngo Molnar * Setup the lapic timer in periodic or oneshot mode 436f62bae50SIngo Molnar */ 437f62bae50SIngo Molnar static void lapic_timer_setup(enum clock_event_mode mode, 438f62bae50SIngo Molnar struct clock_event_device *evt) 439f62bae50SIngo Molnar { 440f62bae50SIngo Molnar unsigned long flags; 441f62bae50SIngo Molnar unsigned int v; 442f62bae50SIngo Molnar 443f62bae50SIngo Molnar /* Lapic used as dummy for broadcast ? */ 444f62bae50SIngo Molnar if (evt->features & CLOCK_EVT_FEAT_DUMMY) 445f62bae50SIngo Molnar return; 446f62bae50SIngo Molnar 447f62bae50SIngo Molnar local_irq_save(flags); 448f62bae50SIngo Molnar 449f62bae50SIngo Molnar switch (mode) { 450f62bae50SIngo Molnar case CLOCK_EVT_MODE_PERIODIC: 451f62bae50SIngo Molnar case CLOCK_EVT_MODE_ONESHOT: 452f62bae50SIngo Molnar __setup_APIC_LVTT(calibration_result, 453f62bae50SIngo Molnar mode != CLOCK_EVT_MODE_PERIODIC, 1); 454f62bae50SIngo Molnar break; 455f62bae50SIngo Molnar case CLOCK_EVT_MODE_UNUSED: 456f62bae50SIngo Molnar case CLOCK_EVT_MODE_SHUTDOWN: 457f62bae50SIngo Molnar v = apic_read(APIC_LVTT); 458f62bae50SIngo Molnar v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 459f62bae50SIngo Molnar apic_write(APIC_LVTT, v); 460f62bae50SIngo Molnar apic_write(APIC_TMICT, 0xffffffff); 461f62bae50SIngo Molnar break; 462f62bae50SIngo Molnar case CLOCK_EVT_MODE_RESUME: 463f62bae50SIngo Molnar /* Nothing to do here */ 464f62bae50SIngo Molnar break; 465f62bae50SIngo Molnar } 466f62bae50SIngo Molnar 467f62bae50SIngo Molnar local_irq_restore(flags); 468f62bae50SIngo Molnar } 469f62bae50SIngo Molnar 470f62bae50SIngo Molnar /* 471f62bae50SIngo Molnar * Local APIC timer broadcast function 472f62bae50SIngo Molnar */ 473f62bae50SIngo Molnar static void lapic_timer_broadcast(const struct cpumask *mask) 474f62bae50SIngo Molnar { 475f62bae50SIngo Molnar #ifdef CONFIG_SMP 476f62bae50SIngo Molnar apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 477f62bae50SIngo Molnar #endif 478f62bae50SIngo Molnar } 479f62bae50SIngo Molnar 480f62bae50SIngo Molnar /* 481f62bae50SIngo Molnar * Setup the local APIC timer for this CPU. Copy the initilized values 482f62bae50SIngo Molnar * of the boot CPU and register the clock event in the framework. 483f62bae50SIngo Molnar */ 484f62bae50SIngo Molnar static void __cpuinit setup_APIC_timer(void) 485f62bae50SIngo Molnar { 486f62bae50SIngo Molnar struct clock_event_device *levt = &__get_cpu_var(lapic_events); 487f62bae50SIngo Molnar 488db954b58SVenkatesh Pallipadi if (cpu_has(¤t_cpu_data, X86_FEATURE_ARAT)) { 489db954b58SVenkatesh Pallipadi lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 490db954b58SVenkatesh Pallipadi /* Make LAPIC timer preferrable over percpu HPET */ 491db954b58SVenkatesh Pallipadi lapic_clockevent.rating = 150; 492db954b58SVenkatesh Pallipadi } 493db954b58SVenkatesh Pallipadi 494f62bae50SIngo Molnar memcpy(levt, &lapic_clockevent, sizeof(*levt)); 495f62bae50SIngo Molnar levt->cpumask = cpumask_of(smp_processor_id()); 496f62bae50SIngo Molnar 497f62bae50SIngo Molnar clockevents_register_device(levt); 498f62bae50SIngo Molnar } 499f62bae50SIngo Molnar 500f62bae50SIngo Molnar /* 501f62bae50SIngo Molnar * In this functions we calibrate APIC bus clocks to the external timer. 502f62bae50SIngo Molnar * 503f62bae50SIngo Molnar * We want to do the calibration only once since we want to have local timer 504f62bae50SIngo Molnar * irqs syncron. CPUs connected by the same APIC bus have the very same bus 505f62bae50SIngo Molnar * frequency. 506f62bae50SIngo Molnar * 507f62bae50SIngo Molnar * This was previously done by reading the PIT/HPET and waiting for a wrap 508f62bae50SIngo Molnar * around to find out, that a tick has elapsed. I have a box, where the PIT 509f62bae50SIngo Molnar * readout is broken, so it never gets out of the wait loop again. This was 510f62bae50SIngo Molnar * also reported by others. 511f62bae50SIngo Molnar * 512f62bae50SIngo Molnar * Monitoring the jiffies value is inaccurate and the clockevents 513f62bae50SIngo Molnar * infrastructure allows us to do a simple substitution of the interrupt 514f62bae50SIngo Molnar * handler. 515f62bae50SIngo Molnar * 516f62bae50SIngo Molnar * The calibration routine also uses the pm_timer when possible, as the PIT 517f62bae50SIngo Molnar * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 518f62bae50SIngo Molnar * back to normal later in the boot process). 519f62bae50SIngo Molnar */ 520f62bae50SIngo Molnar 521f62bae50SIngo Molnar #define LAPIC_CAL_LOOPS (HZ/10) 522f62bae50SIngo Molnar 523f62bae50SIngo Molnar static __initdata int lapic_cal_loops = -1; 524f62bae50SIngo Molnar static __initdata long lapic_cal_t1, lapic_cal_t2; 525f62bae50SIngo Molnar static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 526f62bae50SIngo Molnar static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 527f62bae50SIngo Molnar static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 528f62bae50SIngo Molnar 529f62bae50SIngo Molnar /* 530f62bae50SIngo Molnar * Temporary interrupt handler. 531f62bae50SIngo Molnar */ 532f62bae50SIngo Molnar static void __init lapic_cal_handler(struct clock_event_device *dev) 533f62bae50SIngo Molnar { 534f62bae50SIngo Molnar unsigned long long tsc = 0; 535f62bae50SIngo Molnar long tapic = apic_read(APIC_TMCCT); 536f62bae50SIngo Molnar unsigned long pm = acpi_pm_read_early(); 537f62bae50SIngo Molnar 538f62bae50SIngo Molnar if (cpu_has_tsc) 539f62bae50SIngo Molnar rdtscll(tsc); 540f62bae50SIngo Molnar 541f62bae50SIngo Molnar switch (lapic_cal_loops++) { 542f62bae50SIngo Molnar case 0: 543f62bae50SIngo Molnar lapic_cal_t1 = tapic; 544f62bae50SIngo Molnar lapic_cal_tsc1 = tsc; 545f62bae50SIngo Molnar lapic_cal_pm1 = pm; 546f62bae50SIngo Molnar lapic_cal_j1 = jiffies; 547f62bae50SIngo Molnar break; 548f62bae50SIngo Molnar 549f62bae50SIngo Molnar case LAPIC_CAL_LOOPS: 550f62bae50SIngo Molnar lapic_cal_t2 = tapic; 551f62bae50SIngo Molnar lapic_cal_tsc2 = tsc; 552f62bae50SIngo Molnar if (pm < lapic_cal_pm1) 553f62bae50SIngo Molnar pm += ACPI_PM_OVRRUN; 554f62bae50SIngo Molnar lapic_cal_pm2 = pm; 555f62bae50SIngo Molnar lapic_cal_j2 = jiffies; 556f62bae50SIngo Molnar break; 557f62bae50SIngo Molnar } 558f62bae50SIngo Molnar } 559f62bae50SIngo Molnar 560f62bae50SIngo Molnar static int __init 561f62bae50SIngo Molnar calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 562f62bae50SIngo Molnar { 563f62bae50SIngo Molnar const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 564f62bae50SIngo Molnar const long pm_thresh = pm_100ms / 100; 565f62bae50SIngo Molnar unsigned long mult; 566f62bae50SIngo Molnar u64 res; 567f62bae50SIngo Molnar 568f62bae50SIngo Molnar #ifndef CONFIG_X86_PM_TIMER 569f62bae50SIngo Molnar return -1; 570f62bae50SIngo Molnar #endif 571f62bae50SIngo Molnar 572f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 573f62bae50SIngo Molnar 574f62bae50SIngo Molnar /* Check, if the PM timer is available */ 575f62bae50SIngo Molnar if (!deltapm) 576f62bae50SIngo Molnar return -1; 577f62bae50SIngo Molnar 578f62bae50SIngo Molnar mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 579f62bae50SIngo Molnar 580f62bae50SIngo Molnar if (deltapm > (pm_100ms - pm_thresh) && 581f62bae50SIngo Molnar deltapm < (pm_100ms + pm_thresh)) { 582f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 583f62bae50SIngo Molnar return 0; 584f62bae50SIngo Molnar } 585f62bae50SIngo Molnar 586f62bae50SIngo Molnar res = (((u64)deltapm) * mult) >> 22; 587f62bae50SIngo Molnar do_div(res, 1000000); 588f62bae50SIngo Molnar pr_warning("APIC calibration not consistent " 589f62bae50SIngo Molnar "with PM-Timer: %ldms instead of 100ms\n",(long)res); 590f62bae50SIngo Molnar 591f62bae50SIngo Molnar /* Correct the lapic counter value */ 592f62bae50SIngo Molnar res = (((u64)(*delta)) * pm_100ms); 593f62bae50SIngo Molnar do_div(res, deltapm); 594f62bae50SIngo Molnar pr_info("APIC delta adjusted to PM-Timer: " 595f62bae50SIngo Molnar "%lu (%ld)\n", (unsigned long)res, *delta); 596f62bae50SIngo Molnar *delta = (long)res; 597f62bae50SIngo Molnar 598f62bae50SIngo Molnar /* Correct the tsc counter value */ 599f62bae50SIngo Molnar if (cpu_has_tsc) { 600f62bae50SIngo Molnar res = (((u64)(*deltatsc)) * pm_100ms); 601f62bae50SIngo Molnar do_div(res, deltapm); 602f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 603f62bae50SIngo Molnar "PM-Timer: %lu (%ld) \n", 604f62bae50SIngo Molnar (unsigned long)res, *deltatsc); 605f62bae50SIngo Molnar *deltatsc = (long)res; 606f62bae50SIngo Molnar } 607f62bae50SIngo Molnar 608f62bae50SIngo Molnar return 0; 609f62bae50SIngo Molnar } 610f62bae50SIngo Molnar 611f62bae50SIngo Molnar static int __init calibrate_APIC_clock(void) 612f62bae50SIngo Molnar { 613f62bae50SIngo Molnar struct clock_event_device *levt = &__get_cpu_var(lapic_events); 614f62bae50SIngo Molnar void (*real_handler)(struct clock_event_device *dev); 615f62bae50SIngo Molnar unsigned long deltaj; 616f62bae50SIngo Molnar long delta, deltatsc; 617f62bae50SIngo Molnar int pm_referenced = 0; 618f62bae50SIngo Molnar 619f62bae50SIngo Molnar local_irq_disable(); 620f62bae50SIngo Molnar 621f62bae50SIngo Molnar /* Replace the global interrupt handler */ 622f62bae50SIngo Molnar real_handler = global_clock_event->event_handler; 623f62bae50SIngo Molnar global_clock_event->event_handler = lapic_cal_handler; 624f62bae50SIngo Molnar 625f62bae50SIngo Molnar /* 626f62bae50SIngo Molnar * Setup the APIC counter to maximum. There is no way the lapic 627f62bae50SIngo Molnar * can underflow in the 100ms detection time frame 628f62bae50SIngo Molnar */ 629f62bae50SIngo Molnar __setup_APIC_LVTT(0xffffffff, 0, 0); 630f62bae50SIngo Molnar 631f62bae50SIngo Molnar /* Let the interrupts run */ 632f62bae50SIngo Molnar local_irq_enable(); 633f62bae50SIngo Molnar 634f62bae50SIngo Molnar while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 635f62bae50SIngo Molnar cpu_relax(); 636f62bae50SIngo Molnar 637f62bae50SIngo Molnar local_irq_disable(); 638f62bae50SIngo Molnar 639f62bae50SIngo Molnar /* Restore the real event handler */ 640f62bae50SIngo Molnar global_clock_event->event_handler = real_handler; 641f62bae50SIngo Molnar 642f62bae50SIngo Molnar /* Build delta t1-t2 as apic timer counts down */ 643f62bae50SIngo Molnar delta = lapic_cal_t1 - lapic_cal_t2; 644f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 645f62bae50SIngo Molnar 646f62bae50SIngo Molnar deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 647f62bae50SIngo Molnar 648f62bae50SIngo Molnar /* we trust the PM based calibration if possible */ 649f62bae50SIngo Molnar pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 650f62bae50SIngo Molnar &delta, &deltatsc); 651f62bae50SIngo Molnar 652f62bae50SIngo Molnar /* Calculate the scaled math multiplication factor */ 653f62bae50SIngo Molnar lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 654f62bae50SIngo Molnar lapic_clockevent.shift); 655f62bae50SIngo Molnar lapic_clockevent.max_delta_ns = 656f62bae50SIngo Molnar clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); 657f62bae50SIngo Molnar lapic_clockevent.min_delta_ns = 658f62bae50SIngo Molnar clockevent_delta2ns(0xF, &lapic_clockevent); 659f62bae50SIngo Molnar 660f62bae50SIngo Molnar calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 661f62bae50SIngo Molnar 662f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 663f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult); 664f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 665f62bae50SIngo Molnar calibration_result); 666f62bae50SIngo Molnar 667f62bae50SIngo Molnar if (cpu_has_tsc) { 668f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 669f62bae50SIngo Molnar "%ld.%04ld MHz.\n", 670f62bae50SIngo Molnar (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 671f62bae50SIngo Molnar (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 672f62bae50SIngo Molnar } 673f62bae50SIngo Molnar 674f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 675f62bae50SIngo Molnar "%u.%04u MHz.\n", 676f62bae50SIngo Molnar calibration_result / (1000000 / HZ), 677f62bae50SIngo Molnar calibration_result % (1000000 / HZ)); 678f62bae50SIngo Molnar 679f62bae50SIngo Molnar /* 680f62bae50SIngo Molnar * Do a sanity check on the APIC calibration result 681f62bae50SIngo Molnar */ 682f62bae50SIngo Molnar if (calibration_result < (1000000 / HZ)) { 683f62bae50SIngo Molnar local_irq_enable(); 684f62bae50SIngo Molnar pr_warning("APIC frequency too slow, disabling apic timer\n"); 685f62bae50SIngo Molnar return -1; 686f62bae50SIngo Molnar } 687f62bae50SIngo Molnar 688f62bae50SIngo Molnar levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 689f62bae50SIngo Molnar 690f62bae50SIngo Molnar /* 691f62bae50SIngo Molnar * PM timer calibration failed or not turned on 692f62bae50SIngo Molnar * so lets try APIC timer based calibration 693f62bae50SIngo Molnar */ 694f62bae50SIngo Molnar if (!pm_referenced) { 695f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 696f62bae50SIngo Molnar 697f62bae50SIngo Molnar /* 698f62bae50SIngo Molnar * Setup the apic timer manually 699f62bae50SIngo Molnar */ 700f62bae50SIngo Molnar levt->event_handler = lapic_cal_handler; 701f62bae50SIngo Molnar lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); 702f62bae50SIngo Molnar lapic_cal_loops = -1; 703f62bae50SIngo Molnar 704f62bae50SIngo Molnar /* Let the interrupts run */ 705f62bae50SIngo Molnar local_irq_enable(); 706f62bae50SIngo Molnar 707f62bae50SIngo Molnar while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 708f62bae50SIngo Molnar cpu_relax(); 709f62bae50SIngo Molnar 710f62bae50SIngo Molnar /* Stop the lapic timer */ 711f62bae50SIngo Molnar lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); 712f62bae50SIngo Molnar 713f62bae50SIngo Molnar /* Jiffies delta */ 714f62bae50SIngo Molnar deltaj = lapic_cal_j2 - lapic_cal_j1; 715f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 716f62bae50SIngo Molnar 717f62bae50SIngo Molnar /* Check, if the jiffies result is consistent */ 718f62bae50SIngo Molnar if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 719f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 720f62bae50SIngo Molnar else 721f62bae50SIngo Molnar levt->features |= CLOCK_EVT_FEAT_DUMMY; 722f62bae50SIngo Molnar } else 723f62bae50SIngo Molnar local_irq_enable(); 724f62bae50SIngo Molnar 725f62bae50SIngo Molnar if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 726f62bae50SIngo Molnar pr_warning("APIC timer disabled due to verification failure\n"); 727f62bae50SIngo Molnar return -1; 728f62bae50SIngo Molnar } 729f62bae50SIngo Molnar 730f62bae50SIngo Molnar return 0; 731f62bae50SIngo Molnar } 732f62bae50SIngo Molnar 733f62bae50SIngo Molnar /* 734f62bae50SIngo Molnar * Setup the boot APIC 735f62bae50SIngo Molnar * 736f62bae50SIngo Molnar * Calibrate and verify the result. 737f62bae50SIngo Molnar */ 738f62bae50SIngo Molnar void __init setup_boot_APIC_clock(void) 739f62bae50SIngo Molnar { 740f62bae50SIngo Molnar /* 741f62bae50SIngo Molnar * The local apic timer can be disabled via the kernel 742f62bae50SIngo Molnar * commandline or from the CPU detection code. Register the lapic 743f62bae50SIngo Molnar * timer as a dummy clock event source on SMP systems, so the 744f62bae50SIngo Molnar * broadcast mechanism is used. On UP systems simply ignore it. 745f62bae50SIngo Molnar */ 746f62bae50SIngo Molnar if (disable_apic_timer) { 747f62bae50SIngo Molnar pr_info("Disabling APIC timer\n"); 748f62bae50SIngo Molnar /* No broadcast on UP ! */ 749f62bae50SIngo Molnar if (num_possible_cpus() > 1) { 750f62bae50SIngo Molnar lapic_clockevent.mult = 1; 751f62bae50SIngo Molnar setup_APIC_timer(); 752f62bae50SIngo Molnar } 753f62bae50SIngo Molnar return; 754f62bae50SIngo Molnar } 755f62bae50SIngo Molnar 756f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 757f62bae50SIngo Molnar "calibrating APIC timer ...\n"); 758f62bae50SIngo Molnar 759f62bae50SIngo Molnar if (calibrate_APIC_clock()) { 760f62bae50SIngo Molnar /* No broadcast on UP ! */ 761f62bae50SIngo Molnar if (num_possible_cpus() > 1) 762f62bae50SIngo Molnar setup_APIC_timer(); 763f62bae50SIngo Molnar return; 764f62bae50SIngo Molnar } 765f62bae50SIngo Molnar 766f62bae50SIngo Molnar /* 767f62bae50SIngo Molnar * If nmi_watchdog is set to IO_APIC, we need the 768f62bae50SIngo Molnar * PIT/HPET going. Otherwise register lapic as a dummy 769f62bae50SIngo Molnar * device. 770f62bae50SIngo Molnar */ 771f62bae50SIngo Molnar if (nmi_watchdog != NMI_IO_APIC) 772f62bae50SIngo Molnar lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 773f62bae50SIngo Molnar else 774f62bae50SIngo Molnar pr_warning("APIC timer registered as dummy," 775f62bae50SIngo Molnar " due to nmi_watchdog=%d!\n", nmi_watchdog); 776f62bae50SIngo Molnar 777f62bae50SIngo Molnar /* Setup the lapic or request the broadcast */ 778f62bae50SIngo Molnar setup_APIC_timer(); 779f62bae50SIngo Molnar } 780f62bae50SIngo Molnar 781f62bae50SIngo Molnar void __cpuinit setup_secondary_APIC_clock(void) 782f62bae50SIngo Molnar { 783f62bae50SIngo Molnar setup_APIC_timer(); 784f62bae50SIngo Molnar } 785f62bae50SIngo Molnar 786f62bae50SIngo Molnar /* 787f62bae50SIngo Molnar * The guts of the apic timer interrupt 788f62bae50SIngo Molnar */ 789f62bae50SIngo Molnar static void local_apic_timer_interrupt(void) 790f62bae50SIngo Molnar { 791f62bae50SIngo Molnar int cpu = smp_processor_id(); 792f62bae50SIngo Molnar struct clock_event_device *evt = &per_cpu(lapic_events, cpu); 793f62bae50SIngo Molnar 794f62bae50SIngo Molnar /* 795f62bae50SIngo Molnar * Normally we should not be here till LAPIC has been initialized but 796f62bae50SIngo Molnar * in some cases like kdump, its possible that there is a pending LAPIC 797f62bae50SIngo Molnar * timer interrupt from previous kernel's context and is delivered in 798f62bae50SIngo Molnar * new kernel the moment interrupts are enabled. 799f62bae50SIngo Molnar * 800f62bae50SIngo Molnar * Interrupts are enabled early and LAPIC is setup much later, hence 801f62bae50SIngo Molnar * its possible that when we get here evt->event_handler is NULL. 802f62bae50SIngo Molnar * Check for event_handler being NULL and discard the interrupt as 803f62bae50SIngo Molnar * spurious. 804f62bae50SIngo Molnar */ 805f62bae50SIngo Molnar if (!evt->event_handler) { 806f62bae50SIngo Molnar pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); 807f62bae50SIngo Molnar /* Switch it off */ 808f62bae50SIngo Molnar lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); 809f62bae50SIngo Molnar return; 810f62bae50SIngo Molnar } 811f62bae50SIngo Molnar 812f62bae50SIngo Molnar /* 813f62bae50SIngo Molnar * the NMI deadlock-detector uses this. 814f62bae50SIngo Molnar */ 815f62bae50SIngo Molnar inc_irq_stat(apic_timer_irqs); 816f62bae50SIngo Molnar 817f62bae50SIngo Molnar evt->event_handler(evt); 818f62bae50SIngo Molnar } 819f62bae50SIngo Molnar 820f62bae50SIngo Molnar /* 821f62bae50SIngo Molnar * Local APIC timer interrupt. This is the most natural way for doing 822f62bae50SIngo Molnar * local interrupts, but local timer interrupts can be emulated by 823f62bae50SIngo Molnar * broadcast interrupts too. [in case the hw doesn't support APIC timers] 824f62bae50SIngo Molnar * 825f62bae50SIngo Molnar * [ if a single-CPU system runs an SMP kernel then we call the local 826f62bae50SIngo Molnar * interrupt as well. Thus we cannot inline the local irq ... ] 827f62bae50SIngo Molnar */ 828f62bae50SIngo Molnar void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 829f62bae50SIngo Molnar { 830f62bae50SIngo Molnar struct pt_regs *old_regs = set_irq_regs(regs); 831f62bae50SIngo Molnar 832f62bae50SIngo Molnar /* 833f62bae50SIngo Molnar * NOTE! We'd better ACK the irq immediately, 834f62bae50SIngo Molnar * because timer handling can be slow. 835f62bae50SIngo Molnar */ 836f62bae50SIngo Molnar ack_APIC_irq(); 837f62bae50SIngo Molnar /* 838f62bae50SIngo Molnar * update_process_times() expects us to have done irq_enter(). 839f62bae50SIngo Molnar * Besides, if we don't timer interrupts ignore the global 840f62bae50SIngo Molnar * interrupt lock, which is the WrongThing (tm) to do. 841f62bae50SIngo Molnar */ 842f62bae50SIngo Molnar exit_idle(); 843f62bae50SIngo Molnar irq_enter(); 844f62bae50SIngo Molnar local_apic_timer_interrupt(); 845f62bae50SIngo Molnar irq_exit(); 846f62bae50SIngo Molnar 847f62bae50SIngo Molnar set_irq_regs(old_regs); 848f62bae50SIngo Molnar } 849f62bae50SIngo Molnar 850f62bae50SIngo Molnar int setup_profiling_timer(unsigned int multiplier) 851f62bae50SIngo Molnar { 852f62bae50SIngo Molnar return -EINVAL; 853f62bae50SIngo Molnar } 854f62bae50SIngo Molnar 855f62bae50SIngo Molnar /* 856f62bae50SIngo Molnar * Local APIC start and shutdown 857f62bae50SIngo Molnar */ 858f62bae50SIngo Molnar 859f62bae50SIngo Molnar /** 860f62bae50SIngo Molnar * clear_local_APIC - shutdown the local APIC 861f62bae50SIngo Molnar * 862f62bae50SIngo Molnar * This is called, when a CPU is disabled and before rebooting, so the state of 863f62bae50SIngo Molnar * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 864f62bae50SIngo Molnar * leftovers during boot. 865f62bae50SIngo Molnar */ 866f62bae50SIngo Molnar void clear_local_APIC(void) 867f62bae50SIngo Molnar { 868f62bae50SIngo Molnar int maxlvt; 869f62bae50SIngo Molnar u32 v; 870f62bae50SIngo Molnar 871f62bae50SIngo Molnar /* APIC hasn't been mapped yet */ 872fc1edaf9SSuresh Siddha if (!x2apic_mode && !apic_phys) 873f62bae50SIngo Molnar return; 874f62bae50SIngo Molnar 875f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 876f62bae50SIngo Molnar /* 877f62bae50SIngo Molnar * Masking an LVT entry can trigger a local APIC error 878f62bae50SIngo Molnar * if the vector is zero. Mask LVTERR first to prevent this. 879f62bae50SIngo Molnar */ 880f62bae50SIngo Molnar if (maxlvt >= 3) { 881f62bae50SIngo Molnar v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 882f62bae50SIngo Molnar apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 883f62bae50SIngo Molnar } 884f62bae50SIngo Molnar /* 885f62bae50SIngo Molnar * Careful: we have to set masks only first to deassert 886f62bae50SIngo Molnar * any level-triggered sources. 887f62bae50SIngo Molnar */ 888f62bae50SIngo Molnar v = apic_read(APIC_LVTT); 889f62bae50SIngo Molnar apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 890f62bae50SIngo Molnar v = apic_read(APIC_LVT0); 891f62bae50SIngo Molnar apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 892f62bae50SIngo Molnar v = apic_read(APIC_LVT1); 893f62bae50SIngo Molnar apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 894f62bae50SIngo Molnar if (maxlvt >= 4) { 895f62bae50SIngo Molnar v = apic_read(APIC_LVTPC); 896f62bae50SIngo Molnar apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 897f62bae50SIngo Molnar } 898f62bae50SIngo Molnar 899f62bae50SIngo Molnar /* lets not touch this if we didn't frob it */ 900fc6fc7f1SIngo Molnar #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) 901f62bae50SIngo Molnar if (maxlvt >= 5) { 902f62bae50SIngo Molnar v = apic_read(APIC_LVTTHMR); 903f62bae50SIngo Molnar apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 904f62bae50SIngo Molnar } 905f62bae50SIngo Molnar #endif 906638bee71SH. Peter Anvin #ifdef CONFIG_X86_MCE_INTEL 907638bee71SH. Peter Anvin if (maxlvt >= 6) { 908638bee71SH. Peter Anvin v = apic_read(APIC_LVTCMCI); 909638bee71SH. Peter Anvin if (!(v & APIC_LVT_MASKED)) 910638bee71SH. Peter Anvin apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 911638bee71SH. Peter Anvin } 912638bee71SH. Peter Anvin #endif 913638bee71SH. Peter Anvin 914f62bae50SIngo Molnar /* 915f62bae50SIngo Molnar * Clean APIC state for other OSs: 916f62bae50SIngo Molnar */ 917f62bae50SIngo Molnar apic_write(APIC_LVTT, APIC_LVT_MASKED); 918f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_LVT_MASKED); 919f62bae50SIngo Molnar apic_write(APIC_LVT1, APIC_LVT_MASKED); 920f62bae50SIngo Molnar if (maxlvt >= 3) 921f62bae50SIngo Molnar apic_write(APIC_LVTERR, APIC_LVT_MASKED); 922f62bae50SIngo Molnar if (maxlvt >= 4) 923f62bae50SIngo Molnar apic_write(APIC_LVTPC, APIC_LVT_MASKED); 924f62bae50SIngo Molnar 925f62bae50SIngo Molnar /* Integrated APIC (!82489DX) ? */ 926f62bae50SIngo Molnar if (lapic_is_integrated()) { 927f62bae50SIngo Molnar if (maxlvt > 3) 928f62bae50SIngo Molnar /* Clear ESR due to Pentium errata 3AP and 11AP */ 929f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 930f62bae50SIngo Molnar apic_read(APIC_ESR); 931f62bae50SIngo Molnar } 932f62bae50SIngo Molnar } 933f62bae50SIngo Molnar 934f62bae50SIngo Molnar /** 935f62bae50SIngo Molnar * disable_local_APIC - clear and disable the local APIC 936f62bae50SIngo Molnar */ 937f62bae50SIngo Molnar void disable_local_APIC(void) 938f62bae50SIngo Molnar { 939f62bae50SIngo Molnar unsigned int value; 940f62bae50SIngo Molnar 941f62bae50SIngo Molnar /* APIC hasn't been mapped yet */ 942f62bae50SIngo Molnar if (!apic_phys) 943f62bae50SIngo Molnar return; 944f62bae50SIngo Molnar 945f62bae50SIngo Molnar clear_local_APIC(); 946f62bae50SIngo Molnar 947f62bae50SIngo Molnar /* 948f62bae50SIngo Molnar * Disable APIC (implies clearing of registers 949f62bae50SIngo Molnar * for 82489DX!). 950f62bae50SIngo Molnar */ 951f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 952f62bae50SIngo Molnar value &= ~APIC_SPIV_APIC_ENABLED; 953f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 954f62bae50SIngo Molnar 955f62bae50SIngo Molnar #ifdef CONFIG_X86_32 956f62bae50SIngo Molnar /* 957f62bae50SIngo Molnar * When LAPIC was disabled by the BIOS and enabled by the kernel, 958f62bae50SIngo Molnar * restore the disabled state. 959f62bae50SIngo Molnar */ 960f62bae50SIngo Molnar if (enabled_via_apicbase) { 961f62bae50SIngo Molnar unsigned int l, h; 962f62bae50SIngo Molnar 963f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, l, h); 964f62bae50SIngo Molnar l &= ~MSR_IA32_APICBASE_ENABLE; 965f62bae50SIngo Molnar wrmsr(MSR_IA32_APICBASE, l, h); 966f62bae50SIngo Molnar } 967f62bae50SIngo Molnar #endif 968f62bae50SIngo Molnar } 969f62bae50SIngo Molnar 970f62bae50SIngo Molnar /* 971f62bae50SIngo Molnar * If Linux enabled the LAPIC against the BIOS default disable it down before 972f62bae50SIngo Molnar * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 973f62bae50SIngo Molnar * not power-off. Additionally clear all LVT entries before disable_local_APIC 974f62bae50SIngo Molnar * for the case where Linux didn't enable the LAPIC. 975f62bae50SIngo Molnar */ 976f62bae50SIngo Molnar void lapic_shutdown(void) 977f62bae50SIngo Molnar { 978f62bae50SIngo Molnar unsigned long flags; 979f62bae50SIngo Molnar 980f62bae50SIngo Molnar if (!cpu_has_apic) 981f62bae50SIngo Molnar return; 982f62bae50SIngo Molnar 983f62bae50SIngo Molnar local_irq_save(flags); 984f62bae50SIngo Molnar 985f62bae50SIngo Molnar #ifdef CONFIG_X86_32 986f62bae50SIngo Molnar if (!enabled_via_apicbase) 987f62bae50SIngo Molnar clear_local_APIC(); 988f62bae50SIngo Molnar else 989f62bae50SIngo Molnar #endif 990f62bae50SIngo Molnar disable_local_APIC(); 991f62bae50SIngo Molnar 992f62bae50SIngo Molnar 993f62bae50SIngo Molnar local_irq_restore(flags); 994f62bae50SIngo Molnar } 995f62bae50SIngo Molnar 996f62bae50SIngo Molnar /* 997f62bae50SIngo Molnar * This is to verify that we're looking at a real local APIC. 998f62bae50SIngo Molnar * Check these against your board if the CPUs aren't getting 999f62bae50SIngo Molnar * started for no apparent reason. 1000f62bae50SIngo Molnar */ 1001f62bae50SIngo Molnar int __init verify_local_APIC(void) 1002f62bae50SIngo Molnar { 1003f62bae50SIngo Molnar unsigned int reg0, reg1; 1004f62bae50SIngo Molnar 1005f62bae50SIngo Molnar /* 1006f62bae50SIngo Molnar * The version register is read-only in a real APIC. 1007f62bae50SIngo Molnar */ 1008f62bae50SIngo Molnar reg0 = apic_read(APIC_LVR); 1009f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); 1010f62bae50SIngo Molnar apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); 1011f62bae50SIngo Molnar reg1 = apic_read(APIC_LVR); 1012f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); 1013f62bae50SIngo Molnar 1014f62bae50SIngo Molnar /* 1015f62bae50SIngo Molnar * The two version reads above should print the same 1016f62bae50SIngo Molnar * numbers. If the second one is different, then we 1017f62bae50SIngo Molnar * poke at a non-APIC. 1018f62bae50SIngo Molnar */ 1019f62bae50SIngo Molnar if (reg1 != reg0) 1020f62bae50SIngo Molnar return 0; 1021f62bae50SIngo Molnar 1022f62bae50SIngo Molnar /* 1023f62bae50SIngo Molnar * Check if the version looks reasonably. 1024f62bae50SIngo Molnar */ 1025f62bae50SIngo Molnar reg1 = GET_APIC_VERSION(reg0); 1026f62bae50SIngo Molnar if (reg1 == 0x00 || reg1 == 0xff) 1027f62bae50SIngo Molnar return 0; 1028f62bae50SIngo Molnar reg1 = lapic_get_maxlvt(); 1029f62bae50SIngo Molnar if (reg1 < 0x02 || reg1 == 0xff) 1030f62bae50SIngo Molnar return 0; 1031f62bae50SIngo Molnar 1032f62bae50SIngo Molnar /* 1033f62bae50SIngo Molnar * The ID register is read/write in a real APIC. 1034f62bae50SIngo Molnar */ 1035f62bae50SIngo Molnar reg0 = apic_read(APIC_ID); 1036f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); 1037f62bae50SIngo Molnar apic_write(APIC_ID, reg0 ^ apic->apic_id_mask); 1038f62bae50SIngo Molnar reg1 = apic_read(APIC_ID); 1039f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); 1040f62bae50SIngo Molnar apic_write(APIC_ID, reg0); 1041f62bae50SIngo Molnar if (reg1 != (reg0 ^ apic->apic_id_mask)) 1042f62bae50SIngo Molnar return 0; 1043f62bae50SIngo Molnar 1044f62bae50SIngo Molnar /* 1045f62bae50SIngo Molnar * The next two are just to see if we have sane values. 1046f62bae50SIngo Molnar * They're only really relevant if we're in Virtual Wire 1047f62bae50SIngo Molnar * compatibility mode, but most boxes are anymore. 1048f62bae50SIngo Molnar */ 1049f62bae50SIngo Molnar reg0 = apic_read(APIC_LVT0); 1050f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); 1051f62bae50SIngo Molnar reg1 = apic_read(APIC_LVT1); 1052f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); 1053f62bae50SIngo Molnar 1054f62bae50SIngo Molnar return 1; 1055f62bae50SIngo Molnar } 1056f62bae50SIngo Molnar 1057f62bae50SIngo Molnar /** 1058f62bae50SIngo Molnar * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1059f62bae50SIngo Molnar */ 1060f62bae50SIngo Molnar void __init sync_Arb_IDs(void) 1061f62bae50SIngo Molnar { 1062f62bae50SIngo Molnar /* 1063f62bae50SIngo Molnar * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1064f62bae50SIngo Molnar * needed on AMD. 1065f62bae50SIngo Molnar */ 1066f62bae50SIngo Molnar if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1067f62bae50SIngo Molnar return; 1068f62bae50SIngo Molnar 1069f62bae50SIngo Molnar /* 1070f62bae50SIngo Molnar * Wait for idle. 1071f62bae50SIngo Molnar */ 1072f62bae50SIngo Molnar apic_wait_icr_idle(); 1073f62bae50SIngo Molnar 1074f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1075f62bae50SIngo Molnar apic_write(APIC_ICR, APIC_DEST_ALLINC | 1076f62bae50SIngo Molnar APIC_INT_LEVELTRIG | APIC_DM_INIT); 1077f62bae50SIngo Molnar } 1078f62bae50SIngo Molnar 1079f62bae50SIngo Molnar /* 1080f62bae50SIngo Molnar * An initial setup of the virtual wire mode. 1081f62bae50SIngo Molnar */ 1082f62bae50SIngo Molnar void __init init_bsp_APIC(void) 1083f62bae50SIngo Molnar { 1084f62bae50SIngo Molnar unsigned int value; 1085f62bae50SIngo Molnar 1086f62bae50SIngo Molnar /* 1087f62bae50SIngo Molnar * Don't do the setup now if we have a SMP BIOS as the 1088f62bae50SIngo Molnar * through-I/O-APIC virtual wire mode might be active. 1089f62bae50SIngo Molnar */ 1090f62bae50SIngo Molnar if (smp_found_config || !cpu_has_apic) 1091f62bae50SIngo Molnar return; 1092f62bae50SIngo Molnar 1093f62bae50SIngo Molnar /* 1094f62bae50SIngo Molnar * Do not trust the local APIC being empty at bootup. 1095f62bae50SIngo Molnar */ 1096f62bae50SIngo Molnar clear_local_APIC(); 1097f62bae50SIngo Molnar 1098f62bae50SIngo Molnar /* 1099f62bae50SIngo Molnar * Enable APIC. 1100f62bae50SIngo Molnar */ 1101f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 1102f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 1103f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 1104f62bae50SIngo Molnar 1105f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1106f62bae50SIngo Molnar /* This bit is reserved on P4/Xeon and should be cleared */ 1107f62bae50SIngo Molnar if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1108f62bae50SIngo Molnar (boot_cpu_data.x86 == 15)) 1109f62bae50SIngo Molnar value &= ~APIC_SPIV_FOCUS_DISABLED; 1110f62bae50SIngo Molnar else 1111f62bae50SIngo Molnar #endif 1112f62bae50SIngo Molnar value |= APIC_SPIV_FOCUS_DISABLED; 1113f62bae50SIngo Molnar value |= SPURIOUS_APIC_VECTOR; 1114f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 1115f62bae50SIngo Molnar 1116f62bae50SIngo Molnar /* 1117f62bae50SIngo Molnar * Set up the virtual wire mode. 1118f62bae50SIngo Molnar */ 1119f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_DM_EXTINT); 1120f62bae50SIngo Molnar value = APIC_DM_NMI; 1121f62bae50SIngo Molnar if (!lapic_is_integrated()) /* 82489DX */ 1122f62bae50SIngo Molnar value |= APIC_LVT_LEVEL_TRIGGER; 1123f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 1124f62bae50SIngo Molnar } 1125f62bae50SIngo Molnar 1126f62bae50SIngo Molnar static void __cpuinit lapic_setup_esr(void) 1127f62bae50SIngo Molnar { 1128f62bae50SIngo Molnar unsigned int oldvalue, value, maxlvt; 1129f62bae50SIngo Molnar 1130f62bae50SIngo Molnar if (!lapic_is_integrated()) { 1131f62bae50SIngo Molnar pr_info("No ESR for 82489DX.\n"); 1132f62bae50SIngo Molnar return; 1133f62bae50SIngo Molnar } 1134f62bae50SIngo Molnar 1135f62bae50SIngo Molnar if (apic->disable_esr) { 1136f62bae50SIngo Molnar /* 1137f62bae50SIngo Molnar * Something untraceable is creating bad interrupts on 1138f62bae50SIngo Molnar * secondary quads ... for the moment, just leave the 1139f62bae50SIngo Molnar * ESR disabled - we can't do anything useful with the 1140f62bae50SIngo Molnar * errors anyway - mbligh 1141f62bae50SIngo Molnar */ 1142f62bae50SIngo Molnar pr_info("Leaving ESR disabled.\n"); 1143f62bae50SIngo Molnar return; 1144f62bae50SIngo Molnar } 1145f62bae50SIngo Molnar 1146f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 1147f62bae50SIngo Molnar if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1148f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1149f62bae50SIngo Molnar oldvalue = apic_read(APIC_ESR); 1150f62bae50SIngo Molnar 1151f62bae50SIngo Molnar /* enables sending errors */ 1152f62bae50SIngo Molnar value = ERROR_APIC_VECTOR; 1153f62bae50SIngo Molnar apic_write(APIC_LVTERR, value); 1154f62bae50SIngo Molnar 1155f62bae50SIngo Molnar /* 1156f62bae50SIngo Molnar * spec says clear errors after enabling vector. 1157f62bae50SIngo Molnar */ 1158f62bae50SIngo Molnar if (maxlvt > 3) 1159f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1160f62bae50SIngo Molnar value = apic_read(APIC_ESR); 1161f62bae50SIngo Molnar if (value != oldvalue) 1162f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "ESR value before enabling " 1163f62bae50SIngo Molnar "vector: 0x%08x after: 0x%08x\n", 1164f62bae50SIngo Molnar oldvalue, value); 1165f62bae50SIngo Molnar } 1166f62bae50SIngo Molnar 1167f62bae50SIngo Molnar 1168f62bae50SIngo Molnar /** 1169f62bae50SIngo Molnar * setup_local_APIC - setup the local APIC 1170f62bae50SIngo Molnar */ 1171f62bae50SIngo Molnar void __cpuinit setup_local_APIC(void) 1172f62bae50SIngo Molnar { 1173f62bae50SIngo Molnar unsigned int value; 1174f62bae50SIngo Molnar int i, j; 1175f62bae50SIngo Molnar 1176f62bae50SIngo Molnar if (disable_apic) { 1177f62bae50SIngo Molnar arch_disable_smp_support(); 1178f62bae50SIngo Molnar return; 1179f62bae50SIngo Molnar } 1180f62bae50SIngo Molnar 1181f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1182f62bae50SIngo Molnar /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1183f62bae50SIngo Molnar if (lapic_is_integrated() && apic->disable_esr) { 1184f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1185f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1186f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1187f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1188f62bae50SIngo Molnar } 1189f62bae50SIngo Molnar #endif 1190f62bae50SIngo Molnar 1191f62bae50SIngo Molnar preempt_disable(); 1192f62bae50SIngo Molnar 1193f62bae50SIngo Molnar /* 1194f62bae50SIngo Molnar * Double-check whether this APIC is really registered. 1195f62bae50SIngo Molnar * This is meaningless in clustered apic mode, so we skip it. 1196f62bae50SIngo Molnar */ 1197f62bae50SIngo Molnar if (!apic->apic_id_registered()) 1198f62bae50SIngo Molnar BUG(); 1199f62bae50SIngo Molnar 1200f62bae50SIngo Molnar /* 1201f62bae50SIngo Molnar * Intel recommends to set DFR, LDR and TPR before enabling 1202f62bae50SIngo Molnar * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1203f62bae50SIngo Molnar * document number 292116). So here it goes... 1204f62bae50SIngo Molnar */ 1205f62bae50SIngo Molnar apic->init_apic_ldr(); 1206f62bae50SIngo Molnar 1207f62bae50SIngo Molnar /* 1208f62bae50SIngo Molnar * Set Task Priority to 'accept all'. We never change this 1209f62bae50SIngo Molnar * later on. 1210f62bae50SIngo Molnar */ 1211f62bae50SIngo Molnar value = apic_read(APIC_TASKPRI); 1212f62bae50SIngo Molnar value &= ~APIC_TPRI_MASK; 1213f62bae50SIngo Molnar apic_write(APIC_TASKPRI, value); 1214f62bae50SIngo Molnar 1215f62bae50SIngo Molnar /* 1216f62bae50SIngo Molnar * After a crash, we no longer service the interrupts and a pending 1217f62bae50SIngo Molnar * interrupt from previous kernel might still have ISR bit set. 1218f62bae50SIngo Molnar * 1219f62bae50SIngo Molnar * Most probably by now CPU has serviced that pending interrupt and 1220f62bae50SIngo Molnar * it might not have done the ack_APIC_irq() because it thought, 1221f62bae50SIngo Molnar * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1222f62bae50SIngo Molnar * does not clear the ISR bit and cpu thinks it has already serivced 1223f62bae50SIngo Molnar * the interrupt. Hence a vector might get locked. It was noticed 1224f62bae50SIngo Molnar * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1225f62bae50SIngo Molnar */ 1226f62bae50SIngo Molnar for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1227f62bae50SIngo Molnar value = apic_read(APIC_ISR + i*0x10); 1228f62bae50SIngo Molnar for (j = 31; j >= 0; j--) { 1229f62bae50SIngo Molnar if (value & (1<<j)) 1230f62bae50SIngo Molnar ack_APIC_irq(); 1231f62bae50SIngo Molnar } 1232f62bae50SIngo Molnar } 1233f62bae50SIngo Molnar 1234f62bae50SIngo Molnar /* 1235f62bae50SIngo Molnar * Now that we are all set up, enable the APIC 1236f62bae50SIngo Molnar */ 1237f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 1238f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 1239f62bae50SIngo Molnar /* 1240f62bae50SIngo Molnar * Enable APIC 1241f62bae50SIngo Molnar */ 1242f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 1243f62bae50SIngo Molnar 1244f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1245f62bae50SIngo Molnar /* 1246f62bae50SIngo Molnar * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1247f62bae50SIngo Molnar * certain networking cards. If high frequency interrupts are 1248f62bae50SIngo Molnar * happening on a particular IOAPIC pin, plus the IOAPIC routing 1249f62bae50SIngo Molnar * entry is masked/unmasked at a high rate as well then sooner or 1250f62bae50SIngo Molnar * later IOAPIC line gets 'stuck', no more interrupts are received 1251f62bae50SIngo Molnar * from the device. If focus CPU is disabled then the hang goes 1252f62bae50SIngo Molnar * away, oh well :-( 1253f62bae50SIngo Molnar * 1254f62bae50SIngo Molnar * [ This bug can be reproduced easily with a level-triggered 1255f62bae50SIngo Molnar * PCI Ne2000 networking cards and PII/PIII processors, dual 1256f62bae50SIngo Molnar * BX chipset. ] 1257f62bae50SIngo Molnar */ 1258f62bae50SIngo Molnar /* 1259f62bae50SIngo Molnar * Actually disabling the focus CPU check just makes the hang less 1260f62bae50SIngo Molnar * frequent as it makes the interrupt distributon model be more 1261f62bae50SIngo Molnar * like LRU than MRU (the short-term load is more even across CPUs). 1262f62bae50SIngo Molnar * See also the comment in end_level_ioapic_irq(). --macro 1263f62bae50SIngo Molnar */ 1264f62bae50SIngo Molnar 1265f62bae50SIngo Molnar /* 1266f62bae50SIngo Molnar * - enable focus processor (bit==0) 1267f62bae50SIngo Molnar * - 64bit mode always use processor focus 1268f62bae50SIngo Molnar * so no need to set it 1269f62bae50SIngo Molnar */ 1270f62bae50SIngo Molnar value &= ~APIC_SPIV_FOCUS_DISABLED; 1271f62bae50SIngo Molnar #endif 1272f62bae50SIngo Molnar 1273f62bae50SIngo Molnar /* 1274f62bae50SIngo Molnar * Set spurious IRQ vector 1275f62bae50SIngo Molnar */ 1276f62bae50SIngo Molnar value |= SPURIOUS_APIC_VECTOR; 1277f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 1278f62bae50SIngo Molnar 1279f62bae50SIngo Molnar /* 1280f62bae50SIngo Molnar * Set up LVT0, LVT1: 1281f62bae50SIngo Molnar * 1282f62bae50SIngo Molnar * set up through-local-APIC on the BP's LINT0. This is not 1283f62bae50SIngo Molnar * strictly necessary in pure symmetric-IO mode, but sometimes 1284f62bae50SIngo Molnar * we delegate interrupts to the 8259A. 1285f62bae50SIngo Molnar */ 1286f62bae50SIngo Molnar /* 1287f62bae50SIngo Molnar * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1288f62bae50SIngo Molnar */ 1289f62bae50SIngo Molnar value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1290f62bae50SIngo Molnar if (!smp_processor_id() && (pic_mode || !value)) { 1291f62bae50SIngo Molnar value = APIC_DM_EXTINT; 1292f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", 1293f62bae50SIngo Molnar smp_processor_id()); 1294f62bae50SIngo Molnar } else { 1295f62bae50SIngo Molnar value = APIC_DM_EXTINT | APIC_LVT_MASKED; 1296f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", 1297f62bae50SIngo Molnar smp_processor_id()); 1298f62bae50SIngo Molnar } 1299f62bae50SIngo Molnar apic_write(APIC_LVT0, value); 1300f62bae50SIngo Molnar 1301f62bae50SIngo Molnar /* 1302f62bae50SIngo Molnar * only the BP should see the LINT1 NMI signal, obviously. 1303f62bae50SIngo Molnar */ 1304f62bae50SIngo Molnar if (!smp_processor_id()) 1305f62bae50SIngo Molnar value = APIC_DM_NMI; 1306f62bae50SIngo Molnar else 1307f62bae50SIngo Molnar value = APIC_DM_NMI | APIC_LVT_MASKED; 1308f62bae50SIngo Molnar if (!lapic_is_integrated()) /* 82489DX */ 1309f62bae50SIngo Molnar value |= APIC_LVT_LEVEL_TRIGGER; 1310f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 1311f62bae50SIngo Molnar 1312f62bae50SIngo Molnar preempt_enable(); 1313638bee71SH. Peter Anvin 1314638bee71SH. Peter Anvin #ifdef CONFIG_X86_MCE_INTEL 1315638bee71SH. Peter Anvin /* Recheck CMCI information after local APIC is up on CPU #0 */ 1316638bee71SH. Peter Anvin if (smp_processor_id() == 0) 1317638bee71SH. Peter Anvin cmci_recheck(); 1318638bee71SH. Peter Anvin #endif 1319f62bae50SIngo Molnar } 1320f62bae50SIngo Molnar 1321f62bae50SIngo Molnar void __cpuinit end_local_APIC_setup(void) 1322f62bae50SIngo Molnar { 1323f62bae50SIngo Molnar lapic_setup_esr(); 1324f62bae50SIngo Molnar 1325f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1326f62bae50SIngo Molnar { 1327f62bae50SIngo Molnar unsigned int value; 1328f62bae50SIngo Molnar /* Disable the local apic timer */ 1329f62bae50SIngo Molnar value = apic_read(APIC_LVTT); 1330f62bae50SIngo Molnar value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1331f62bae50SIngo Molnar apic_write(APIC_LVTT, value); 1332f62bae50SIngo Molnar } 1333f62bae50SIngo Molnar #endif 1334f62bae50SIngo Molnar 1335f62bae50SIngo Molnar setup_apic_nmi_watchdog(NULL); 1336f62bae50SIngo Molnar apic_pm_activate(); 1337f62bae50SIngo Molnar } 1338f62bae50SIngo Molnar 1339f62bae50SIngo Molnar #ifdef CONFIG_X86_X2APIC 1340f62bae50SIngo Molnar void check_x2apic(void) 1341f62bae50SIngo Molnar { 1342ef1f87aaSSuresh Siddha if (x2apic_enabled()) { 1343f62bae50SIngo Molnar pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); 1344fc1edaf9SSuresh Siddha x2apic_preenabled = x2apic_mode = 1; 1345f62bae50SIngo Molnar } 1346f62bae50SIngo Molnar } 1347f62bae50SIngo Molnar 1348f62bae50SIngo Molnar void enable_x2apic(void) 1349f62bae50SIngo Molnar { 1350f62bae50SIngo Molnar int msr, msr2; 1351f62bae50SIngo Molnar 1352fc1edaf9SSuresh Siddha if (!x2apic_mode) 1353f62bae50SIngo Molnar return; 1354f62bae50SIngo Molnar 1355f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, msr, msr2); 1356f62bae50SIngo Molnar if (!(msr & X2APIC_ENABLE)) { 1357f62bae50SIngo Molnar pr_info("Enabling x2apic\n"); 1358f62bae50SIngo Molnar wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); 1359f62bae50SIngo Molnar } 1360f62bae50SIngo Molnar } 136193758238SWeidong Han #endif /* CONFIG_X86_X2APIC */ 1362f62bae50SIngo Molnar 1363f62bae50SIngo Molnar void __init enable_IR_x2apic(void) 1364f62bae50SIngo Molnar { 1365f62bae50SIngo Molnar #ifdef CONFIG_INTR_REMAP 1366f62bae50SIngo Molnar int ret; 1367f62bae50SIngo Molnar unsigned long flags; 1368b24696bcSFenghua Yu struct IO_APIC_route_entry **ioapic_entries = NULL; 1369f62bae50SIngo Molnar 1370f62bae50SIngo Molnar ret = dmar_table_init(); 1371f62bae50SIngo Molnar if (ret) { 137293758238SWeidong Han pr_debug("dmar_table_init() failed with %d:\n", ret); 137393758238SWeidong Han goto ir_failed; 137493758238SWeidong Han } 1375f62bae50SIngo Molnar 137693758238SWeidong Han if (!intr_remapping_supported()) { 137793758238SWeidong Han pr_debug("intr-remapping not supported\n"); 137893758238SWeidong Han goto ir_failed; 137993758238SWeidong Han } 138093758238SWeidong Han 138193758238SWeidong Han 138293758238SWeidong Han if (!x2apic_preenabled && skip_ioapic_setup) { 138393758238SWeidong Han pr_info("Skipped enabling intr-remap because of skipping " 138493758238SWeidong Han "io-apic setup\n"); 1385f62bae50SIngo Molnar return; 1386f62bae50SIngo Molnar } 1387f62bae50SIngo Molnar 1388b24696bcSFenghua Yu ioapic_entries = alloc_ioapic_entries(); 1389b24696bcSFenghua Yu if (!ioapic_entries) { 1390b24696bcSFenghua Yu pr_info("Allocate ioapic_entries failed: %d\n", ret); 1391b24696bcSFenghua Yu goto end; 1392b24696bcSFenghua Yu } 1393b24696bcSFenghua Yu 1394b24696bcSFenghua Yu ret = save_IO_APIC_setup(ioapic_entries); 1395f62bae50SIngo Molnar if (ret) { 1396f62bae50SIngo Molnar pr_info("Saving IO-APIC state failed: %d\n", ret); 1397f62bae50SIngo Molnar goto end; 1398f62bae50SIngo Molnar } 1399f62bae50SIngo Molnar 140005c3dc2cSSuresh Siddha local_irq_save(flags); 1401b24696bcSFenghua Yu mask_IO_APIC_setup(ioapic_entries); 140205c3dc2cSSuresh Siddha mask_8259A(); 140305c3dc2cSSuresh Siddha 1404fc1edaf9SSuresh Siddha ret = enable_intr_remapping(x2apic_supported()); 1405f62bae50SIngo Molnar if (ret) 1406f62bae50SIngo Molnar goto end_restore; 1407f62bae50SIngo Molnar 140893758238SWeidong Han pr_info("Enabled Interrupt-remapping\n"); 140993758238SWeidong Han 1410fc1edaf9SSuresh Siddha if (x2apic_supported() && !x2apic_mode) { 1411fc1edaf9SSuresh Siddha x2apic_mode = 1; 1412f62bae50SIngo Molnar enable_x2apic(); 141393758238SWeidong Han pr_info("Enabled x2apic\n"); 1414f62bae50SIngo Molnar } 1415f62bae50SIngo Molnar 1416f62bae50SIngo Molnar end_restore: 1417f62bae50SIngo Molnar if (ret) 1418f62bae50SIngo Molnar /* 1419f62bae50SIngo Molnar * IR enabling failed 1420f62bae50SIngo Molnar */ 1421b24696bcSFenghua Yu restore_IO_APIC_setup(ioapic_entries); 1422f62bae50SIngo Molnar 1423f62bae50SIngo Molnar unmask_8259A(); 1424f62bae50SIngo Molnar local_irq_restore(flags); 1425f62bae50SIngo Molnar 142605c3dc2cSSuresh Siddha end: 1427b24696bcSFenghua Yu if (ioapic_entries) 1428b24696bcSFenghua Yu free_ioapic_entries(ioapic_entries); 142993758238SWeidong Han 143093758238SWeidong Han if (!ret) 143193758238SWeidong Han return; 143293758238SWeidong Han 143393758238SWeidong Han ir_failed: 143493758238SWeidong Han if (x2apic_preenabled) 143593758238SWeidong Han panic("x2apic enabled by bios. But IR enabling failed"); 143693758238SWeidong Han else if (cpu_has_x2apic) 143793758238SWeidong Han pr_info("Not enabling x2apic,Intr-remapping\n"); 1438f62bae50SIngo Molnar #else 1439f62bae50SIngo Molnar if (!cpu_has_x2apic) 1440f62bae50SIngo Molnar return; 1441f62bae50SIngo Molnar 1442f62bae50SIngo Molnar if (x2apic_preenabled) 1443f62bae50SIngo Molnar panic("x2apic enabled prior OS handover," 144493758238SWeidong Han " enable CONFIG_X86_X2APIC, CONFIG_INTR_REMAP"); 1445f62bae50SIngo Molnar #endif 1446f62bae50SIngo Molnar 1447f62bae50SIngo Molnar return; 1448f62bae50SIngo Molnar } 144993758238SWeidong Han 1450f62bae50SIngo Molnar 1451f62bae50SIngo Molnar #ifdef CONFIG_X86_64 1452f62bae50SIngo Molnar /* 1453f62bae50SIngo Molnar * Detect and enable local APICs on non-SMP boards. 1454f62bae50SIngo Molnar * Original code written by Keir Fraser. 1455f62bae50SIngo Molnar * On AMD64 we trust the BIOS - if it says no APIC it is likely 1456f62bae50SIngo Molnar * not correctly set up (usually the APIC timer won't work etc.) 1457f62bae50SIngo Molnar */ 1458f62bae50SIngo Molnar static int __init detect_init_APIC(void) 1459f62bae50SIngo Molnar { 1460f62bae50SIngo Molnar if (!cpu_has_apic) { 1461f62bae50SIngo Molnar pr_info("No local APIC present\n"); 1462f62bae50SIngo Molnar return -1; 1463f62bae50SIngo Molnar } 1464f62bae50SIngo Molnar 1465f62bae50SIngo Molnar mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1466f62bae50SIngo Molnar return 0; 1467f62bae50SIngo Molnar } 1468f62bae50SIngo Molnar #else 1469f62bae50SIngo Molnar /* 1470f62bae50SIngo Molnar * Detect and initialize APIC 1471f62bae50SIngo Molnar */ 1472f62bae50SIngo Molnar static int __init detect_init_APIC(void) 1473f62bae50SIngo Molnar { 1474f62bae50SIngo Molnar u32 h, l, features; 1475f62bae50SIngo Molnar 1476f62bae50SIngo Molnar /* Disabled by kernel option? */ 1477f62bae50SIngo Molnar if (disable_apic) 1478f62bae50SIngo Molnar return -1; 1479f62bae50SIngo Molnar 1480f62bae50SIngo Molnar switch (boot_cpu_data.x86_vendor) { 1481f62bae50SIngo Molnar case X86_VENDOR_AMD: 1482f62bae50SIngo Molnar if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1483f62bae50SIngo Molnar (boot_cpu_data.x86 >= 15)) 1484f62bae50SIngo Molnar break; 1485f62bae50SIngo Molnar goto no_apic; 1486f62bae50SIngo Molnar case X86_VENDOR_INTEL: 1487f62bae50SIngo Molnar if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1488f62bae50SIngo Molnar (boot_cpu_data.x86 == 5 && cpu_has_apic)) 1489f62bae50SIngo Molnar break; 1490f62bae50SIngo Molnar goto no_apic; 1491f62bae50SIngo Molnar default: 1492f62bae50SIngo Molnar goto no_apic; 1493f62bae50SIngo Molnar } 1494f62bae50SIngo Molnar 1495f62bae50SIngo Molnar if (!cpu_has_apic) { 1496f62bae50SIngo Molnar /* 1497f62bae50SIngo Molnar * Over-ride BIOS and try to enable the local APIC only if 1498f62bae50SIngo Molnar * "lapic" specified. 1499f62bae50SIngo Molnar */ 1500f62bae50SIngo Molnar if (!force_enable_local_apic) { 1501f62bae50SIngo Molnar pr_info("Local APIC disabled by BIOS -- " 1502f62bae50SIngo Molnar "you can enable it with \"lapic\"\n"); 1503f62bae50SIngo Molnar return -1; 1504f62bae50SIngo Molnar } 1505f62bae50SIngo Molnar /* 1506f62bae50SIngo Molnar * Some BIOSes disable the local APIC in the APIC_BASE 1507f62bae50SIngo Molnar * MSR. This can only be done in software for Intel P6 or later 1508f62bae50SIngo Molnar * and AMD K7 (Model > 1) or later. 1509f62bae50SIngo Molnar */ 1510f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, l, h); 1511f62bae50SIngo Molnar if (!(l & MSR_IA32_APICBASE_ENABLE)) { 1512f62bae50SIngo Molnar pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 1513f62bae50SIngo Molnar l &= ~MSR_IA32_APICBASE_BASE; 1514f62bae50SIngo Molnar l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; 1515f62bae50SIngo Molnar wrmsr(MSR_IA32_APICBASE, l, h); 1516f62bae50SIngo Molnar enabled_via_apicbase = 1; 1517f62bae50SIngo Molnar } 1518f62bae50SIngo Molnar } 1519f62bae50SIngo Molnar /* 1520f62bae50SIngo Molnar * The APIC feature bit should now be enabled 1521f62bae50SIngo Molnar * in `cpuid' 1522f62bae50SIngo Molnar */ 1523f62bae50SIngo Molnar features = cpuid_edx(1); 1524f62bae50SIngo Molnar if (!(features & (1 << X86_FEATURE_APIC))) { 1525f62bae50SIngo Molnar pr_warning("Could not enable APIC!\n"); 1526f62bae50SIngo Molnar return -1; 1527f62bae50SIngo Molnar } 1528f62bae50SIngo Molnar set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1529f62bae50SIngo Molnar mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1530f62bae50SIngo Molnar 1531f62bae50SIngo Molnar /* The BIOS may have set up the APIC at some other address */ 1532f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, l, h); 1533f62bae50SIngo Molnar if (l & MSR_IA32_APICBASE_ENABLE) 1534f62bae50SIngo Molnar mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1535f62bae50SIngo Molnar 1536f62bae50SIngo Molnar pr_info("Found and enabled local APIC!\n"); 1537f62bae50SIngo Molnar 1538f62bae50SIngo Molnar apic_pm_activate(); 1539f62bae50SIngo Molnar 1540f62bae50SIngo Molnar return 0; 1541f62bae50SIngo Molnar 1542f62bae50SIngo Molnar no_apic: 1543f62bae50SIngo Molnar pr_info("No local APIC present or hardware disabled\n"); 1544f62bae50SIngo Molnar return -1; 1545f62bae50SIngo Molnar } 1546f62bae50SIngo Molnar #endif 1547f62bae50SIngo Molnar 1548f62bae50SIngo Molnar #ifdef CONFIG_X86_64 1549f62bae50SIngo Molnar void __init early_init_lapic_mapping(void) 1550f62bae50SIngo Molnar { 1551f62bae50SIngo Molnar unsigned long phys_addr; 1552f62bae50SIngo Molnar 1553f62bae50SIngo Molnar /* 1554f62bae50SIngo Molnar * If no local APIC can be found then go out 1555f62bae50SIngo Molnar * : it means there is no mpatable and MADT 1556f62bae50SIngo Molnar */ 1557f62bae50SIngo Molnar if (!smp_found_config) 1558f62bae50SIngo Molnar return; 1559f62bae50SIngo Molnar 1560f62bae50SIngo Molnar phys_addr = mp_lapic_addr; 1561f62bae50SIngo Molnar 1562f62bae50SIngo Molnar set_fixmap_nocache(FIX_APIC_BASE, phys_addr); 1563f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 1564f62bae50SIngo Molnar APIC_BASE, phys_addr); 1565f62bae50SIngo Molnar 1566f62bae50SIngo Molnar /* 1567f62bae50SIngo Molnar * Fetch the APIC ID of the BSP in case we have a 1568f62bae50SIngo Molnar * default configuration (or the MP table is broken). 1569f62bae50SIngo Molnar */ 1570f62bae50SIngo Molnar boot_cpu_physical_apicid = read_apic_id(); 1571f62bae50SIngo Molnar } 1572f62bae50SIngo Molnar #endif 1573f62bae50SIngo Molnar 1574f62bae50SIngo Molnar /** 1575f62bae50SIngo Molnar * init_apic_mappings - initialize APIC mappings 1576f62bae50SIngo Molnar */ 1577f62bae50SIngo Molnar void __init init_apic_mappings(void) 1578f62bae50SIngo Molnar { 15794401da61SYinghai Lu unsigned int new_apicid; 15804401da61SYinghai Lu 1581fc1edaf9SSuresh Siddha if (x2apic_mode) { 1582f62bae50SIngo Molnar boot_cpu_physical_apicid = read_apic_id(); 1583f62bae50SIngo Molnar return; 1584f62bae50SIngo Molnar } 1585f62bae50SIngo Molnar 15864797f6b0SYinghai Lu /* If no local APIC can be found return early */ 1587f62bae50SIngo Molnar if (!smp_found_config && detect_init_APIC()) { 15884797f6b0SYinghai Lu /* lets NOP'ify apic operations */ 15894797f6b0SYinghai Lu pr_info("APIC: disable apic facility\n"); 15904797f6b0SYinghai Lu apic_disable(); 15914797f6b0SYinghai Lu } else { 1592f62bae50SIngo Molnar apic_phys = mp_lapic_addr; 1593f62bae50SIngo Molnar 15944401da61SYinghai Lu /* 15954401da61SYinghai Lu * acpi lapic path already maps that address in 15964401da61SYinghai Lu * acpi_register_lapic_address() 15974401da61SYinghai Lu */ 15984401da61SYinghai Lu if (!acpi_lapic) 1599f62bae50SIngo Molnar set_fixmap_nocache(FIX_APIC_BASE, apic_phys); 16004401da61SYinghai Lu 1601f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", 1602f62bae50SIngo Molnar APIC_BASE, apic_phys); 1603cec6be6dSCyrill Gorcunov } 1604cec6be6dSCyrill Gorcunov 1605f62bae50SIngo Molnar /* 1606f62bae50SIngo Molnar * Fetch the APIC ID of the BSP in case we have a 1607f62bae50SIngo Molnar * default configuration (or the MP table is broken). 1608f62bae50SIngo Molnar */ 16094401da61SYinghai Lu new_apicid = read_apic_id(); 16104401da61SYinghai Lu if (boot_cpu_physical_apicid != new_apicid) { 16114401da61SYinghai Lu boot_cpu_physical_apicid = new_apicid; 16124401da61SYinghai Lu apic_version[new_apicid] = 16134401da61SYinghai Lu GET_APIC_VERSION(apic_read(APIC_LVR)); 161408306ce6SCyrill Gorcunov } 1615f62bae50SIngo Molnar } 1616f62bae50SIngo Molnar 1617f62bae50SIngo Molnar /* 1618f62bae50SIngo Molnar * This initializes the IO-APIC and APIC hardware if this is 1619f62bae50SIngo Molnar * a UP kernel. 1620f62bae50SIngo Molnar */ 1621f62bae50SIngo Molnar int apic_version[MAX_APICS]; 1622f62bae50SIngo Molnar 1623f62bae50SIngo Molnar int __init APIC_init_uniprocessor(void) 1624f62bae50SIngo Molnar { 1625f62bae50SIngo Molnar if (disable_apic) { 1626f62bae50SIngo Molnar pr_info("Apic disabled\n"); 1627f62bae50SIngo Molnar return -1; 1628f62bae50SIngo Molnar } 1629f62bae50SIngo Molnar #ifdef CONFIG_X86_64 1630f62bae50SIngo Molnar if (!cpu_has_apic) { 1631f62bae50SIngo Molnar disable_apic = 1; 1632f62bae50SIngo Molnar pr_info("Apic disabled by BIOS\n"); 1633f62bae50SIngo Molnar return -1; 1634f62bae50SIngo Molnar } 1635f62bae50SIngo Molnar #else 1636f62bae50SIngo Molnar if (!smp_found_config && !cpu_has_apic) 1637f62bae50SIngo Molnar return -1; 1638f62bae50SIngo Molnar 1639f62bae50SIngo Molnar /* 1640f62bae50SIngo Molnar * Complain if the BIOS pretends there is one. 1641f62bae50SIngo Molnar */ 1642f62bae50SIngo Molnar if (!cpu_has_apic && 1643f62bae50SIngo Molnar APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 1644f62bae50SIngo Molnar pr_err("BIOS bug, local APIC 0x%x not detected!...\n", 1645f62bae50SIngo Molnar boot_cpu_physical_apicid); 1646f62bae50SIngo Molnar clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1647f62bae50SIngo Molnar return -1; 1648f62bae50SIngo Molnar } 1649f62bae50SIngo Molnar #endif 1650f62bae50SIngo Molnar 1651f62bae50SIngo Molnar enable_IR_x2apic(); 1652f62bae50SIngo Molnar #ifdef CONFIG_X86_64 1653f62bae50SIngo Molnar default_setup_apic_routing(); 1654f62bae50SIngo Molnar #endif 1655f62bae50SIngo Molnar 1656f62bae50SIngo Molnar verify_local_APIC(); 1657f62bae50SIngo Molnar connect_bsp_APIC(); 1658f62bae50SIngo Molnar 1659f62bae50SIngo Molnar #ifdef CONFIG_X86_64 1660f62bae50SIngo Molnar apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); 1661f62bae50SIngo Molnar #else 1662f62bae50SIngo Molnar /* 1663f62bae50SIngo Molnar * Hack: In case of kdump, after a crash, kernel might be booting 1664f62bae50SIngo Molnar * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 1665f62bae50SIngo Molnar * might be zero if read from MP tables. Get it from LAPIC. 1666f62bae50SIngo Molnar */ 1667f62bae50SIngo Molnar # ifdef CONFIG_CRASH_DUMP 1668f62bae50SIngo Molnar boot_cpu_physical_apicid = read_apic_id(); 1669f62bae50SIngo Molnar # endif 1670f62bae50SIngo Molnar #endif 1671f62bae50SIngo Molnar physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1672f62bae50SIngo Molnar setup_local_APIC(); 1673f62bae50SIngo Molnar 1674f62bae50SIngo Molnar #ifdef CONFIG_X86_IO_APIC 1675f62bae50SIngo Molnar /* 1676f62bae50SIngo Molnar * Now enable IO-APICs, actually call clear_IO_APIC 1677f62bae50SIngo Molnar * We need clear_IO_APIC before enabling error vector 1678f62bae50SIngo Molnar */ 1679f62bae50SIngo Molnar if (!skip_ioapic_setup && nr_ioapics) 1680f62bae50SIngo Molnar enable_IO_APIC(); 1681f62bae50SIngo Molnar #endif 1682f62bae50SIngo Molnar 1683f62bae50SIngo Molnar end_local_APIC_setup(); 1684f62bae50SIngo Molnar 1685f62bae50SIngo Molnar #ifdef CONFIG_X86_IO_APIC 1686f62bae50SIngo Molnar if (smp_found_config && !skip_ioapic_setup && nr_ioapics) 1687f62bae50SIngo Molnar setup_IO_APIC(); 1688f62bae50SIngo Molnar else { 1689f62bae50SIngo Molnar nr_ioapics = 0; 1690f62bae50SIngo Molnar localise_nmi_watchdog(); 1691f62bae50SIngo Molnar } 1692f62bae50SIngo Molnar #else 1693f62bae50SIngo Molnar localise_nmi_watchdog(); 1694f62bae50SIngo Molnar #endif 1695f62bae50SIngo Molnar 1696f62bae50SIngo Molnar setup_boot_clock(); 1697f62bae50SIngo Molnar #ifdef CONFIG_X86_64 1698f62bae50SIngo Molnar check_nmi_watchdog(); 1699f62bae50SIngo Molnar #endif 1700f62bae50SIngo Molnar 1701f62bae50SIngo Molnar return 0; 1702f62bae50SIngo Molnar } 1703f62bae50SIngo Molnar 1704f62bae50SIngo Molnar /* 1705f62bae50SIngo Molnar * Local APIC interrupts 1706f62bae50SIngo Molnar */ 1707f62bae50SIngo Molnar 1708f62bae50SIngo Molnar /* 1709f62bae50SIngo Molnar * This interrupt should _never_ happen with our APIC/SMP architecture 1710f62bae50SIngo Molnar */ 1711f62bae50SIngo Molnar void smp_spurious_interrupt(struct pt_regs *regs) 1712f62bae50SIngo Molnar { 1713f62bae50SIngo Molnar u32 v; 1714f62bae50SIngo Molnar 1715f62bae50SIngo Molnar exit_idle(); 1716f62bae50SIngo Molnar irq_enter(); 1717f62bae50SIngo Molnar /* 1718f62bae50SIngo Molnar * Check if this really is a spurious interrupt and ACK it 1719f62bae50SIngo Molnar * if it is a vectored one. Just in case... 1720f62bae50SIngo Molnar * Spurious interrupts should not be ACKed. 1721f62bae50SIngo Molnar */ 1722f62bae50SIngo Molnar v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); 1723f62bae50SIngo Molnar if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) 1724f62bae50SIngo Molnar ack_APIC_irq(); 1725f62bae50SIngo Molnar 1726f62bae50SIngo Molnar inc_irq_stat(irq_spurious_count); 1727f62bae50SIngo Molnar 1728f62bae50SIngo Molnar /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 1729f62bae50SIngo Molnar pr_info("spurious APIC interrupt on CPU#%d, " 1730f62bae50SIngo Molnar "should never happen.\n", smp_processor_id()); 1731f62bae50SIngo Molnar irq_exit(); 1732f62bae50SIngo Molnar } 1733f62bae50SIngo Molnar 1734f62bae50SIngo Molnar /* 1735f62bae50SIngo Molnar * This interrupt should never happen with our APIC/SMP architecture 1736f62bae50SIngo Molnar */ 1737f62bae50SIngo Molnar void smp_error_interrupt(struct pt_regs *regs) 1738f62bae50SIngo Molnar { 1739f62bae50SIngo Molnar u32 v, v1; 1740f62bae50SIngo Molnar 1741f62bae50SIngo Molnar exit_idle(); 1742f62bae50SIngo Molnar irq_enter(); 1743f62bae50SIngo Molnar /* First tickle the hardware, only then report what went on. -- REW */ 1744f62bae50SIngo Molnar v = apic_read(APIC_ESR); 1745f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1746f62bae50SIngo Molnar v1 = apic_read(APIC_ESR); 1747f62bae50SIngo Molnar ack_APIC_irq(); 1748f62bae50SIngo Molnar atomic_inc(&irq_err_count); 1749f62bae50SIngo Molnar 1750f62bae50SIngo Molnar /* 1751f62bae50SIngo Molnar * Here is what the APIC error bits mean: 1752f62bae50SIngo Molnar * 0: Send CS error 1753f62bae50SIngo Molnar * 1: Receive CS error 1754f62bae50SIngo Molnar * 2: Send accept error 1755f62bae50SIngo Molnar * 3: Receive accept error 1756f62bae50SIngo Molnar * 4: Reserved 1757f62bae50SIngo Molnar * 5: Send illegal vector 1758f62bae50SIngo Molnar * 6: Received illegal vector 1759f62bae50SIngo Molnar * 7: Illegal register address 1760f62bae50SIngo Molnar */ 1761f62bae50SIngo Molnar pr_debug("APIC error on CPU%d: %02x(%02x)\n", 1762f62bae50SIngo Molnar smp_processor_id(), v , v1); 1763f62bae50SIngo Molnar irq_exit(); 1764f62bae50SIngo Molnar } 1765f62bae50SIngo Molnar 1766f62bae50SIngo Molnar /** 1767f62bae50SIngo Molnar * connect_bsp_APIC - attach the APIC to the interrupt system 1768f62bae50SIngo Molnar */ 1769f62bae50SIngo Molnar void __init connect_bsp_APIC(void) 1770f62bae50SIngo Molnar { 1771f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1772f62bae50SIngo Molnar if (pic_mode) { 1773f62bae50SIngo Molnar /* 1774f62bae50SIngo Molnar * Do not trust the local APIC being empty at bootup. 1775f62bae50SIngo Molnar */ 1776f62bae50SIngo Molnar clear_local_APIC(); 1777f62bae50SIngo Molnar /* 1778f62bae50SIngo Molnar * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 1779f62bae50SIngo Molnar * local APIC to INT and NMI lines. 1780f62bae50SIngo Molnar */ 1781f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "leaving PIC mode, " 1782f62bae50SIngo Molnar "enabling APIC mode.\n"); 1783c0eaa453SCyrill Gorcunov imcr_pic_to_apic(); 1784f62bae50SIngo Molnar } 1785f62bae50SIngo Molnar #endif 1786f62bae50SIngo Molnar if (apic->enable_apic_mode) 1787f62bae50SIngo Molnar apic->enable_apic_mode(); 1788f62bae50SIngo Molnar } 1789f62bae50SIngo Molnar 1790f62bae50SIngo Molnar /** 1791f62bae50SIngo Molnar * disconnect_bsp_APIC - detach the APIC from the interrupt system 1792f62bae50SIngo Molnar * @virt_wire_setup: indicates, whether virtual wire mode is selected 1793f62bae50SIngo Molnar * 1794f62bae50SIngo Molnar * Virtual wire mode is necessary to deliver legacy interrupts even when the 1795f62bae50SIngo Molnar * APIC is disabled. 1796f62bae50SIngo Molnar */ 1797f62bae50SIngo Molnar void disconnect_bsp_APIC(int virt_wire_setup) 1798f62bae50SIngo Molnar { 1799f62bae50SIngo Molnar unsigned int value; 1800f62bae50SIngo Molnar 1801f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1802f62bae50SIngo Molnar if (pic_mode) { 1803f62bae50SIngo Molnar /* 1804f62bae50SIngo Molnar * Put the board back into PIC mode (has an effect only on 1805f62bae50SIngo Molnar * certain older boards). Note that APIC interrupts, including 1806f62bae50SIngo Molnar * IPIs, won't work beyond this point! The only exception are 1807f62bae50SIngo Molnar * INIT IPIs. 1808f62bae50SIngo Molnar */ 1809f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "disabling APIC mode, " 1810f62bae50SIngo Molnar "entering PIC mode.\n"); 1811c0eaa453SCyrill Gorcunov imcr_apic_to_pic(); 1812f62bae50SIngo Molnar return; 1813f62bae50SIngo Molnar } 1814f62bae50SIngo Molnar #endif 1815f62bae50SIngo Molnar 1816f62bae50SIngo Molnar /* Go back to Virtual Wire compatibility mode */ 1817f62bae50SIngo Molnar 1818f62bae50SIngo Molnar /* For the spurious interrupt use vector F, and enable it */ 1819f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 1820f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 1821f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 1822f62bae50SIngo Molnar value |= 0xf; 1823f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 1824f62bae50SIngo Molnar 1825f62bae50SIngo Molnar if (!virt_wire_setup) { 1826f62bae50SIngo Molnar /* 1827f62bae50SIngo Molnar * For LVT0 make it edge triggered, active high, 1828f62bae50SIngo Molnar * external and enabled 1829f62bae50SIngo Molnar */ 1830f62bae50SIngo Molnar value = apic_read(APIC_LVT0); 1831f62bae50SIngo Molnar value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1832f62bae50SIngo Molnar APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1833f62bae50SIngo Molnar APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1834f62bae50SIngo Molnar value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1835f62bae50SIngo Molnar value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 1836f62bae50SIngo Molnar apic_write(APIC_LVT0, value); 1837f62bae50SIngo Molnar } else { 1838f62bae50SIngo Molnar /* Disable LVT0 */ 1839f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_LVT_MASKED); 1840f62bae50SIngo Molnar } 1841f62bae50SIngo Molnar 1842f62bae50SIngo Molnar /* 1843f62bae50SIngo Molnar * For LVT1 make it edge triggered, active high, 1844f62bae50SIngo Molnar * nmi and enabled 1845f62bae50SIngo Molnar */ 1846f62bae50SIngo Molnar value = apic_read(APIC_LVT1); 1847f62bae50SIngo Molnar value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1848f62bae50SIngo Molnar APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1849f62bae50SIngo Molnar APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1850f62bae50SIngo Molnar value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1851f62bae50SIngo Molnar value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 1852f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 1853f62bae50SIngo Molnar } 1854f62bae50SIngo Molnar 1855f62bae50SIngo Molnar void __cpuinit generic_processor_info(int apicid, int version) 1856f62bae50SIngo Molnar { 1857f62bae50SIngo Molnar int cpu; 1858f62bae50SIngo Molnar 1859f62bae50SIngo Molnar /* 1860f62bae50SIngo Molnar * Validate version 1861f62bae50SIngo Molnar */ 1862f62bae50SIngo Molnar if (version == 0x0) { 1863f62bae50SIngo Molnar pr_warning("BIOS bug, APIC version is 0 for CPU#%d! " 1864f62bae50SIngo Molnar "fixing up to 0x10. (tell your hw vendor)\n", 1865f62bae50SIngo Molnar version); 1866f62bae50SIngo Molnar version = 0x10; 1867f62bae50SIngo Molnar } 1868f62bae50SIngo Molnar apic_version[apicid] = version; 1869f62bae50SIngo Molnar 1870f62bae50SIngo Molnar if (num_processors >= nr_cpu_ids) { 1871f62bae50SIngo Molnar int max = nr_cpu_ids; 1872f62bae50SIngo Molnar int thiscpu = max + disabled_cpus; 1873f62bae50SIngo Molnar 1874f62bae50SIngo Molnar pr_warning( 1875f62bae50SIngo Molnar "ACPI: NR_CPUS/possible_cpus limit of %i reached." 1876f62bae50SIngo Molnar " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 1877f62bae50SIngo Molnar 1878f62bae50SIngo Molnar disabled_cpus++; 1879f62bae50SIngo Molnar return; 1880f62bae50SIngo Molnar } 1881f62bae50SIngo Molnar 1882f62bae50SIngo Molnar num_processors++; 1883f62bae50SIngo Molnar cpu = cpumask_next_zero(-1, cpu_present_mask); 1884f62bae50SIngo Molnar 1885f62bae50SIngo Molnar if (version != apic_version[boot_cpu_physical_apicid]) 1886f62bae50SIngo Molnar WARN_ONCE(1, 1887f62bae50SIngo Molnar "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n", 1888f62bae50SIngo Molnar apic_version[boot_cpu_physical_apicid], cpu, version); 1889f62bae50SIngo Molnar 1890f62bae50SIngo Molnar physid_set(apicid, phys_cpu_present_map); 1891f62bae50SIngo Molnar if (apicid == boot_cpu_physical_apicid) { 1892f62bae50SIngo Molnar /* 1893f62bae50SIngo Molnar * x86_bios_cpu_apicid is required to have processors listed 1894f62bae50SIngo Molnar * in same order as logical cpu numbers. Hence the first 1895f62bae50SIngo Molnar * entry is BSP, and so on. 1896f62bae50SIngo Molnar */ 1897f62bae50SIngo Molnar cpu = 0; 1898f62bae50SIngo Molnar } 1899f62bae50SIngo Molnar if (apicid > max_physical_apicid) 1900f62bae50SIngo Molnar max_physical_apicid = apicid; 1901f62bae50SIngo Molnar 1902f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1903f62bae50SIngo Molnar /* 1904f62bae50SIngo Molnar * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y 1905f62bae50SIngo Molnar * but we need to work other dependencies like SMP_SUSPEND etc 1906f62bae50SIngo Molnar * before this can be done without some confusion. 1907f62bae50SIngo Molnar * if (CPU_HOTPLUG_ENABLED || num_processors > 8) 1908f62bae50SIngo Molnar * - Ashok Raj <ashok.raj@intel.com> 1909f62bae50SIngo Molnar */ 1910f62bae50SIngo Molnar if (max_physical_apicid >= 8) { 1911f62bae50SIngo Molnar switch (boot_cpu_data.x86_vendor) { 1912f62bae50SIngo Molnar case X86_VENDOR_INTEL: 1913f62bae50SIngo Molnar if (!APIC_XAPIC(version)) { 1914f62bae50SIngo Molnar def_to_bigsmp = 0; 1915f62bae50SIngo Molnar break; 1916f62bae50SIngo Molnar } 1917f62bae50SIngo Molnar /* If P4 and above fall through */ 1918f62bae50SIngo Molnar case X86_VENDOR_AMD: 1919f62bae50SIngo Molnar def_to_bigsmp = 1; 1920f62bae50SIngo Molnar } 1921f62bae50SIngo Molnar } 1922f62bae50SIngo Molnar #endif 1923f62bae50SIngo Molnar 1924f62bae50SIngo Molnar #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 1925f62bae50SIngo Molnar early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 1926f62bae50SIngo Molnar early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 1927f62bae50SIngo Molnar #endif 1928f62bae50SIngo Molnar 1929f62bae50SIngo Molnar set_cpu_possible(cpu, true); 1930f62bae50SIngo Molnar set_cpu_present(cpu, true); 1931f62bae50SIngo Molnar } 1932f62bae50SIngo Molnar 1933f62bae50SIngo Molnar int hard_smp_processor_id(void) 1934f62bae50SIngo Molnar { 1935f62bae50SIngo Molnar return read_apic_id(); 1936f62bae50SIngo Molnar } 1937f62bae50SIngo Molnar 1938f62bae50SIngo Molnar void default_init_apic_ldr(void) 1939f62bae50SIngo Molnar { 1940f62bae50SIngo Molnar unsigned long val; 1941f62bae50SIngo Molnar 1942f62bae50SIngo Molnar apic_write(APIC_DFR, APIC_DFR_VALUE); 1943f62bae50SIngo Molnar val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; 1944f62bae50SIngo Molnar val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); 1945f62bae50SIngo Molnar apic_write(APIC_LDR, val); 1946f62bae50SIngo Molnar } 1947f62bae50SIngo Molnar 1948f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1949f62bae50SIngo Molnar int default_apicid_to_node(int logical_apicid) 1950f62bae50SIngo Molnar { 1951f62bae50SIngo Molnar #ifdef CONFIG_SMP 1952f62bae50SIngo Molnar return apicid_2_node[hard_smp_processor_id()]; 1953f62bae50SIngo Molnar #else 1954f62bae50SIngo Molnar return 0; 1955f62bae50SIngo Molnar #endif 1956f62bae50SIngo Molnar } 1957f62bae50SIngo Molnar #endif 1958f62bae50SIngo Molnar 1959f62bae50SIngo Molnar /* 1960f62bae50SIngo Molnar * Power management 1961f62bae50SIngo Molnar */ 1962f62bae50SIngo Molnar #ifdef CONFIG_PM 1963f62bae50SIngo Molnar 1964f62bae50SIngo Molnar static struct { 1965f62bae50SIngo Molnar /* 1966f62bae50SIngo Molnar * 'active' is true if the local APIC was enabled by us and 1967f62bae50SIngo Molnar * not the BIOS; this signifies that we are also responsible 1968f62bae50SIngo Molnar * for disabling it before entering apm/acpi suspend 1969f62bae50SIngo Molnar */ 1970f62bae50SIngo Molnar int active; 1971f62bae50SIngo Molnar /* r/w apic fields */ 1972f62bae50SIngo Molnar unsigned int apic_id; 1973f62bae50SIngo Molnar unsigned int apic_taskpri; 1974f62bae50SIngo Molnar unsigned int apic_ldr; 1975f62bae50SIngo Molnar unsigned int apic_dfr; 1976f62bae50SIngo Molnar unsigned int apic_spiv; 1977f62bae50SIngo Molnar unsigned int apic_lvtt; 1978f62bae50SIngo Molnar unsigned int apic_lvtpc; 1979f62bae50SIngo Molnar unsigned int apic_lvt0; 1980f62bae50SIngo Molnar unsigned int apic_lvt1; 1981f62bae50SIngo Molnar unsigned int apic_lvterr; 1982f62bae50SIngo Molnar unsigned int apic_tmict; 1983f62bae50SIngo Molnar unsigned int apic_tdcr; 1984f62bae50SIngo Molnar unsigned int apic_thmr; 1985f62bae50SIngo Molnar } apic_pm_state; 1986f62bae50SIngo Molnar 1987f62bae50SIngo Molnar static int lapic_suspend(struct sys_device *dev, pm_message_t state) 1988f62bae50SIngo Molnar { 1989f62bae50SIngo Molnar unsigned long flags; 1990f62bae50SIngo Molnar int maxlvt; 1991f62bae50SIngo Molnar 1992f62bae50SIngo Molnar if (!apic_pm_state.active) 1993f62bae50SIngo Molnar return 0; 1994f62bae50SIngo Molnar 1995f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 1996f62bae50SIngo Molnar 1997f62bae50SIngo Molnar apic_pm_state.apic_id = apic_read(APIC_ID); 1998f62bae50SIngo Molnar apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 1999f62bae50SIngo Molnar apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2000f62bae50SIngo Molnar apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2001f62bae50SIngo Molnar apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2002f62bae50SIngo Molnar apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2003f62bae50SIngo Molnar if (maxlvt >= 4) 2004f62bae50SIngo Molnar apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2005f62bae50SIngo Molnar apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2006f62bae50SIngo Molnar apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2007f62bae50SIngo Molnar apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2008f62bae50SIngo Molnar apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2009f62bae50SIngo Molnar apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 2010f62bae50SIngo Molnar #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) 2011f62bae50SIngo Molnar if (maxlvt >= 5) 2012f62bae50SIngo Molnar apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2013f62bae50SIngo Molnar #endif 2014f62bae50SIngo Molnar 2015f62bae50SIngo Molnar local_irq_save(flags); 2016f62bae50SIngo Molnar disable_local_APIC(); 2017fc1edaf9SSuresh Siddha 2018b24696bcSFenghua Yu if (intr_remapping_enabled) 2019b24696bcSFenghua Yu disable_intr_remapping(); 2020fc1edaf9SSuresh Siddha 2021f62bae50SIngo Molnar local_irq_restore(flags); 2022f62bae50SIngo Molnar return 0; 2023f62bae50SIngo Molnar } 2024f62bae50SIngo Molnar 2025f62bae50SIngo Molnar static int lapic_resume(struct sys_device *dev) 2026f62bae50SIngo Molnar { 2027f62bae50SIngo Molnar unsigned int l, h; 2028f62bae50SIngo Molnar unsigned long flags; 2029f62bae50SIngo Molnar int maxlvt; 2030*3d58829bSJiri Slaby int ret = 0; 2031b24696bcSFenghua Yu struct IO_APIC_route_entry **ioapic_entries = NULL; 2032b24696bcSFenghua Yu 2033f62bae50SIngo Molnar if (!apic_pm_state.active) 2034f62bae50SIngo Molnar return 0; 2035f62bae50SIngo Molnar 2036b24696bcSFenghua Yu local_irq_save(flags); 20379a2755c3SWeidong Han if (intr_remapping_enabled) { 2038b24696bcSFenghua Yu ioapic_entries = alloc_ioapic_entries(); 2039b24696bcSFenghua Yu if (!ioapic_entries) { 2040b24696bcSFenghua Yu WARN(1, "Alloc ioapic_entries in lapic resume failed."); 2041*3d58829bSJiri Slaby ret = -ENOMEM; 2042*3d58829bSJiri Slaby goto restore; 2043b24696bcSFenghua Yu } 2044b24696bcSFenghua Yu 2045b24696bcSFenghua Yu ret = save_IO_APIC_setup(ioapic_entries); 2046b24696bcSFenghua Yu if (ret) { 2047b24696bcSFenghua Yu WARN(1, "Saving IO-APIC state failed: %d\n", ret); 2048b24696bcSFenghua Yu free_ioapic_entries(ioapic_entries); 2049*3d58829bSJiri Slaby goto restore; 2050b24696bcSFenghua Yu } 2051b24696bcSFenghua Yu 2052b24696bcSFenghua Yu mask_IO_APIC_setup(ioapic_entries); 2053b24696bcSFenghua Yu mask_8259A(); 2054b24696bcSFenghua Yu } 20559a2755c3SWeidong Han 2056fc1edaf9SSuresh Siddha if (x2apic_mode) 20579a2755c3SWeidong Han enable_x2apic(); 2058cf6567feSSuresh Siddha else { 2059f62bae50SIngo Molnar /* 2060f62bae50SIngo Molnar * Make sure the APICBASE points to the right address 2061f62bae50SIngo Molnar * 2062f62bae50SIngo Molnar * FIXME! This will be wrong if we ever support suspend on 2063f62bae50SIngo Molnar * SMP! We'll need to do this as part of the CPU restore! 2064f62bae50SIngo Molnar */ 2065f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, l, h); 2066f62bae50SIngo Molnar l &= ~MSR_IA32_APICBASE_BASE; 2067f62bae50SIngo Molnar l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2068f62bae50SIngo Molnar wrmsr(MSR_IA32_APICBASE, l, h); 2069f62bae50SIngo Molnar } 2070f62bae50SIngo Molnar 2071b24696bcSFenghua Yu maxlvt = lapic_get_maxlvt(); 2072f62bae50SIngo Molnar apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2073f62bae50SIngo Molnar apic_write(APIC_ID, apic_pm_state.apic_id); 2074f62bae50SIngo Molnar apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2075f62bae50SIngo Molnar apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2076f62bae50SIngo Molnar apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2077f62bae50SIngo Molnar apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2078f62bae50SIngo Molnar apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2079f62bae50SIngo Molnar apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2080f62bae50SIngo Molnar #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) 2081f62bae50SIngo Molnar if (maxlvt >= 5) 2082f62bae50SIngo Molnar apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2083f62bae50SIngo Molnar #endif 2084f62bae50SIngo Molnar if (maxlvt >= 4) 2085f62bae50SIngo Molnar apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2086f62bae50SIngo Molnar apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2087f62bae50SIngo Molnar apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2088f62bae50SIngo Molnar apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2089f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 2090f62bae50SIngo Molnar apic_read(APIC_ESR); 2091f62bae50SIngo Molnar apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2092f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 2093f62bae50SIngo Molnar apic_read(APIC_ESR); 2094f62bae50SIngo Molnar 20959a2755c3SWeidong Han if (intr_remapping_enabled) { 2096fc1edaf9SSuresh Siddha reenable_intr_remapping(x2apic_mode); 2097b24696bcSFenghua Yu unmask_8259A(); 2098b24696bcSFenghua Yu restore_IO_APIC_setup(ioapic_entries); 2099b24696bcSFenghua Yu free_ioapic_entries(ioapic_entries); 2100b24696bcSFenghua Yu } 2101*3d58829bSJiri Slaby restore: 2102f62bae50SIngo Molnar local_irq_restore(flags); 2103f62bae50SIngo Molnar 2104*3d58829bSJiri Slaby return ret; 2105f62bae50SIngo Molnar } 2106f62bae50SIngo Molnar 2107f62bae50SIngo Molnar /* 2108f62bae50SIngo Molnar * This device has no shutdown method - fully functioning local APICs 2109f62bae50SIngo Molnar * are needed on every CPU up until machine_halt/restart/poweroff. 2110f62bae50SIngo Molnar */ 2111f62bae50SIngo Molnar 2112f62bae50SIngo Molnar static struct sysdev_class lapic_sysclass = { 2113f62bae50SIngo Molnar .name = "lapic", 2114f62bae50SIngo Molnar .resume = lapic_resume, 2115f62bae50SIngo Molnar .suspend = lapic_suspend, 2116f62bae50SIngo Molnar }; 2117f62bae50SIngo Molnar 2118f62bae50SIngo Molnar static struct sys_device device_lapic = { 2119f62bae50SIngo Molnar .id = 0, 2120f62bae50SIngo Molnar .cls = &lapic_sysclass, 2121f62bae50SIngo Molnar }; 2122f62bae50SIngo Molnar 2123f62bae50SIngo Molnar static void __cpuinit apic_pm_activate(void) 2124f62bae50SIngo Molnar { 2125f62bae50SIngo Molnar apic_pm_state.active = 1; 2126f62bae50SIngo Molnar } 2127f62bae50SIngo Molnar 2128f62bae50SIngo Molnar static int __init init_lapic_sysfs(void) 2129f62bae50SIngo Molnar { 2130f62bae50SIngo Molnar int error; 2131f62bae50SIngo Molnar 2132f62bae50SIngo Molnar if (!cpu_has_apic) 2133f62bae50SIngo Molnar return 0; 2134f62bae50SIngo Molnar /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2135f62bae50SIngo Molnar 2136f62bae50SIngo Molnar error = sysdev_class_register(&lapic_sysclass); 2137f62bae50SIngo Molnar if (!error) 2138f62bae50SIngo Molnar error = sysdev_register(&device_lapic); 2139f62bae50SIngo Molnar return error; 2140f62bae50SIngo Molnar } 2141b24696bcSFenghua Yu 2142b24696bcSFenghua Yu /* local apic needs to resume before other devices access its registers. */ 2143b24696bcSFenghua Yu core_initcall(init_lapic_sysfs); 2144f62bae50SIngo Molnar 2145f62bae50SIngo Molnar #else /* CONFIG_PM */ 2146f62bae50SIngo Molnar 2147f62bae50SIngo Molnar static void apic_pm_activate(void) { } 2148f62bae50SIngo Molnar 2149f62bae50SIngo Molnar #endif /* CONFIG_PM */ 2150f62bae50SIngo Molnar 2151f62bae50SIngo Molnar #ifdef CONFIG_X86_64 2152e0e42142SYinghai Lu 2153e0e42142SYinghai Lu static int __cpuinit apic_cluster_num(void) 2154f62bae50SIngo Molnar { 2155f62bae50SIngo Molnar int i, clusters, zeros; 2156f62bae50SIngo Molnar unsigned id; 2157f62bae50SIngo Molnar u16 *bios_cpu_apicid; 2158f62bae50SIngo Molnar DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); 2159f62bae50SIngo Molnar 2160f62bae50SIngo Molnar bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); 2161f62bae50SIngo Molnar bitmap_zero(clustermap, NUM_APIC_CLUSTERS); 2162f62bae50SIngo Molnar 2163f62bae50SIngo Molnar for (i = 0; i < nr_cpu_ids; i++) { 2164f62bae50SIngo Molnar /* are we being called early in kernel startup? */ 2165f62bae50SIngo Molnar if (bios_cpu_apicid) { 2166f62bae50SIngo Molnar id = bios_cpu_apicid[i]; 2167f62bae50SIngo Molnar } else if (i < nr_cpu_ids) { 2168f62bae50SIngo Molnar if (cpu_present(i)) 2169f62bae50SIngo Molnar id = per_cpu(x86_bios_cpu_apicid, i); 2170f62bae50SIngo Molnar else 2171f62bae50SIngo Molnar continue; 2172f62bae50SIngo Molnar } else 2173f62bae50SIngo Molnar break; 2174f62bae50SIngo Molnar 2175f62bae50SIngo Molnar if (id != BAD_APICID) 2176f62bae50SIngo Molnar __set_bit(APIC_CLUSTERID(id), clustermap); 2177f62bae50SIngo Molnar } 2178f62bae50SIngo Molnar 2179f62bae50SIngo Molnar /* Problem: Partially populated chassis may not have CPUs in some of 2180f62bae50SIngo Molnar * the APIC clusters they have been allocated. Only present CPUs have 2181f62bae50SIngo Molnar * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. 2182f62bae50SIngo Molnar * Since clusters are allocated sequentially, count zeros only if 2183f62bae50SIngo Molnar * they are bounded by ones. 2184f62bae50SIngo Molnar */ 2185f62bae50SIngo Molnar clusters = 0; 2186f62bae50SIngo Molnar zeros = 0; 2187f62bae50SIngo Molnar for (i = 0; i < NUM_APIC_CLUSTERS; i++) { 2188f62bae50SIngo Molnar if (test_bit(i, clustermap)) { 2189f62bae50SIngo Molnar clusters += 1 + zeros; 2190f62bae50SIngo Molnar zeros = 0; 2191f62bae50SIngo Molnar } else 2192f62bae50SIngo Molnar ++zeros; 2193f62bae50SIngo Molnar } 2194f62bae50SIngo Molnar 2195e0e42142SYinghai Lu return clusters; 2196e0e42142SYinghai Lu } 2197e0e42142SYinghai Lu 2198e0e42142SYinghai Lu static int __cpuinitdata multi_checked; 2199e0e42142SYinghai Lu static int __cpuinitdata multi; 2200e0e42142SYinghai Lu 2201e0e42142SYinghai Lu static int __cpuinit set_multi(const struct dmi_system_id *d) 2202e0e42142SYinghai Lu { 2203e0e42142SYinghai Lu if (multi) 2204e0e42142SYinghai Lu return 0; 22056f0aced6SCyrill Gorcunov pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2206e0e42142SYinghai Lu multi = 1; 2207e0e42142SYinghai Lu return 0; 2208e0e42142SYinghai Lu } 2209e0e42142SYinghai Lu 2210e0e42142SYinghai Lu static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = { 2211e0e42142SYinghai Lu { 2212e0e42142SYinghai Lu .callback = set_multi, 2213e0e42142SYinghai Lu .ident = "IBM System Summit2", 2214e0e42142SYinghai Lu .matches = { 2215e0e42142SYinghai Lu DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2216e0e42142SYinghai Lu DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2217e0e42142SYinghai Lu }, 2218e0e42142SYinghai Lu }, 2219e0e42142SYinghai Lu {} 2220e0e42142SYinghai Lu }; 2221e0e42142SYinghai Lu 2222e0e42142SYinghai Lu static void __cpuinit dmi_check_multi(void) 2223e0e42142SYinghai Lu { 2224e0e42142SYinghai Lu if (multi_checked) 2225e0e42142SYinghai Lu return; 2226e0e42142SYinghai Lu 2227e0e42142SYinghai Lu dmi_check_system(multi_dmi_table); 2228e0e42142SYinghai Lu multi_checked = 1; 2229e0e42142SYinghai Lu } 2230f62bae50SIngo Molnar 2231f62bae50SIngo Molnar /* 2232e0e42142SYinghai Lu * apic_is_clustered_box() -- Check if we can expect good TSC 2233e0e42142SYinghai Lu * 2234e0e42142SYinghai Lu * Thus far, the major user of this is IBM's Summit2 series: 2235e0e42142SYinghai Lu * Clustered boxes may have unsynced TSC problems if they are 2236e0e42142SYinghai Lu * multi-chassis. 2237e0e42142SYinghai Lu * Use DMI to check them 2238f62bae50SIngo Molnar */ 2239e0e42142SYinghai Lu __cpuinit int apic_is_clustered_box(void) 2240e0e42142SYinghai Lu { 2241e0e42142SYinghai Lu dmi_check_multi(); 2242e0e42142SYinghai Lu if (multi) 2243e0e42142SYinghai Lu return 1; 2244e0e42142SYinghai Lu 2245e0e42142SYinghai Lu if (!is_vsmp_box()) 2246e0e42142SYinghai Lu return 0; 2247e0e42142SYinghai Lu 2248e0e42142SYinghai Lu /* 2249e0e42142SYinghai Lu * ScaleMP vSMPowered boxes have one cluster per board and TSCs are 2250e0e42142SYinghai Lu * not guaranteed to be synced between boards 2251e0e42142SYinghai Lu */ 2252e0e42142SYinghai Lu if (apic_cluster_num() > 1) 2253e0e42142SYinghai Lu return 1; 2254e0e42142SYinghai Lu 2255e0e42142SYinghai Lu return 0; 2256f62bae50SIngo Molnar } 2257f62bae50SIngo Molnar #endif 2258f62bae50SIngo Molnar 2259f62bae50SIngo Molnar /* 2260f62bae50SIngo Molnar * APIC command line parameters 2261f62bae50SIngo Molnar */ 2262f62bae50SIngo Molnar static int __init setup_disableapic(char *arg) 2263f62bae50SIngo Molnar { 2264f62bae50SIngo Molnar disable_apic = 1; 2265f62bae50SIngo Molnar setup_clear_cpu_cap(X86_FEATURE_APIC); 2266f62bae50SIngo Molnar return 0; 2267f62bae50SIngo Molnar } 2268f62bae50SIngo Molnar early_param("disableapic", setup_disableapic); 2269f62bae50SIngo Molnar 2270f62bae50SIngo Molnar /* same as disableapic, for compatibility */ 2271f62bae50SIngo Molnar static int __init setup_nolapic(char *arg) 2272f62bae50SIngo Molnar { 2273f62bae50SIngo Molnar return setup_disableapic(arg); 2274f62bae50SIngo Molnar } 2275f62bae50SIngo Molnar early_param("nolapic", setup_nolapic); 2276f62bae50SIngo Molnar 2277f62bae50SIngo Molnar static int __init parse_lapic_timer_c2_ok(char *arg) 2278f62bae50SIngo Molnar { 2279f62bae50SIngo Molnar local_apic_timer_c2_ok = 1; 2280f62bae50SIngo Molnar return 0; 2281f62bae50SIngo Molnar } 2282f62bae50SIngo Molnar early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2283f62bae50SIngo Molnar 2284f62bae50SIngo Molnar static int __init parse_disable_apic_timer(char *arg) 2285f62bae50SIngo Molnar { 2286f62bae50SIngo Molnar disable_apic_timer = 1; 2287f62bae50SIngo Molnar return 0; 2288f62bae50SIngo Molnar } 2289f62bae50SIngo Molnar early_param("noapictimer", parse_disable_apic_timer); 2290f62bae50SIngo Molnar 2291f62bae50SIngo Molnar static int __init parse_nolapic_timer(char *arg) 2292f62bae50SIngo Molnar { 2293f62bae50SIngo Molnar disable_apic_timer = 1; 2294f62bae50SIngo Molnar return 0; 2295f62bae50SIngo Molnar } 2296f62bae50SIngo Molnar early_param("nolapic_timer", parse_nolapic_timer); 2297f62bae50SIngo Molnar 2298f62bae50SIngo Molnar static int __init apic_set_verbosity(char *arg) 2299f62bae50SIngo Molnar { 2300f62bae50SIngo Molnar if (!arg) { 2301f62bae50SIngo Molnar #ifdef CONFIG_X86_64 2302f62bae50SIngo Molnar skip_ioapic_setup = 0; 2303f62bae50SIngo Molnar return 0; 2304f62bae50SIngo Molnar #endif 2305f62bae50SIngo Molnar return -EINVAL; 2306f62bae50SIngo Molnar } 2307f62bae50SIngo Molnar 2308f62bae50SIngo Molnar if (strcmp("debug", arg) == 0) 2309f62bae50SIngo Molnar apic_verbosity = APIC_DEBUG; 2310f62bae50SIngo Molnar else if (strcmp("verbose", arg) == 0) 2311f62bae50SIngo Molnar apic_verbosity = APIC_VERBOSE; 2312f62bae50SIngo Molnar else { 2313f62bae50SIngo Molnar pr_warning("APIC Verbosity level %s not recognised" 2314f62bae50SIngo Molnar " use apic=verbose or apic=debug\n", arg); 2315f62bae50SIngo Molnar return -EINVAL; 2316f62bae50SIngo Molnar } 2317f62bae50SIngo Molnar 2318f62bae50SIngo Molnar return 0; 2319f62bae50SIngo Molnar } 2320f62bae50SIngo Molnar early_param("apic", apic_set_verbosity); 2321f62bae50SIngo Molnar 2322f62bae50SIngo Molnar static int __init lapic_insert_resource(void) 2323f62bae50SIngo Molnar { 2324f62bae50SIngo Molnar if (!apic_phys) 2325f62bae50SIngo Molnar return -1; 2326f62bae50SIngo Molnar 2327f62bae50SIngo Molnar /* Put local APIC into the resource map. */ 2328f62bae50SIngo Molnar lapic_resource.start = apic_phys; 2329f62bae50SIngo Molnar lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2330f62bae50SIngo Molnar insert_resource(&iomem_resource, &lapic_resource); 2331f62bae50SIngo Molnar 2332f62bae50SIngo Molnar return 0; 2333f62bae50SIngo Molnar } 2334f62bae50SIngo Molnar 2335f62bae50SIngo Molnar /* 2336f62bae50SIngo Molnar * need call insert after e820_reserve_resources() 2337f62bae50SIngo Molnar * that is using request_resource 2338f62bae50SIngo Molnar */ 2339f62bae50SIngo Molnar late_initcall(lapic_insert_resource); 2340