1f62bae50SIngo Molnar /* 2f62bae50SIngo Molnar * Local APIC handling, local APIC timers 3f62bae50SIngo Molnar * 4f62bae50SIngo Molnar * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 5f62bae50SIngo Molnar * 6f62bae50SIngo Molnar * Fixes 7f62bae50SIngo Molnar * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8f62bae50SIngo Molnar * thanks to Eric Gilmore 9f62bae50SIngo Molnar * and Rolf G. Tews 10f62bae50SIngo Molnar * for testing these extensively. 11f62bae50SIngo Molnar * Maciej W. Rozycki : Various updates and fixes. 12f62bae50SIngo Molnar * Mikael Pettersson : Power Management for UP-APIC. 13f62bae50SIngo Molnar * Pavel Machek and 14f62bae50SIngo Molnar * Mikael Pettersson : PM converted to driver model. 15f62bae50SIngo Molnar */ 16f62bae50SIngo Molnar 17cdd6c482SIngo Molnar #include <linux/perf_event.h> 18f62bae50SIngo Molnar #include <linux/kernel_stat.h> 19f62bae50SIngo Molnar #include <linux/mc146818rtc.h> 20f62bae50SIngo Molnar #include <linux/acpi_pmtmr.h> 21f62bae50SIngo Molnar #include <linux/clockchips.h> 22f62bae50SIngo Molnar #include <linux/interrupt.h> 23f62bae50SIngo Molnar #include <linux/bootmem.h> 24f62bae50SIngo Molnar #include <linux/ftrace.h> 25f62bae50SIngo Molnar #include <linux/ioport.h> 26f62bae50SIngo Molnar #include <linux/module.h> 27f3c6ea1bSRafael J. Wysocki #include <linux/syscore_ops.h> 28f62bae50SIngo Molnar #include <linux/delay.h> 29f62bae50SIngo Molnar #include <linux/timex.h> 30334955efSRalf Baechle #include <linux/i8253.h> 31f62bae50SIngo Molnar #include <linux/dmar.h> 32f62bae50SIngo Molnar #include <linux/init.h> 33f62bae50SIngo Molnar #include <linux/cpu.h> 34f62bae50SIngo Molnar #include <linux/dmi.h> 35f62bae50SIngo Molnar #include <linux/smp.h> 36f62bae50SIngo Molnar #include <linux/mm.h> 37f62bae50SIngo Molnar 388a8f422dSSuresh Siddha #include <asm/irq_remapping.h> 39cdd6c482SIngo Molnar #include <asm/perf_event.h> 40736decacSThomas Gleixner #include <asm/x86_init.h> 41f62bae50SIngo Molnar #include <asm/pgalloc.h> 4260063497SArun Sharma #include <linux/atomic.h> 43f62bae50SIngo Molnar #include <asm/mpspec.h> 44f62bae50SIngo Molnar #include <asm/i8259.h> 45f62bae50SIngo Molnar #include <asm/proto.h> 46f62bae50SIngo Molnar #include <asm/apic.h> 477167d08eSHenrik Kretzschmar #include <asm/io_apic.h> 48f62bae50SIngo Molnar #include <asm/desc.h> 49f62bae50SIngo Molnar #include <asm/hpet.h> 50f62bae50SIngo Molnar #include <asm/idle.h> 51f62bae50SIngo Molnar #include <asm/mtrr.h> 5216f871bcSRalf Baechle #include <asm/time.h> 53f62bae50SIngo Molnar #include <asm/smp.h> 54638bee71SH. Peter Anvin #include <asm/mce.h> 558c3ba8d0SKerstin Jonsson #include <asm/tsc.h> 562904ed8dSSheng Yang #include <asm/hypervisor.h> 57f62bae50SIngo Molnar 58f62bae50SIngo Molnar unsigned int num_processors; 59f62bae50SIngo Molnar 60f62bae50SIngo Molnar unsigned disabled_cpus __cpuinitdata; 61f62bae50SIngo Molnar 62f62bae50SIngo Molnar /* Processor that is doing the boot up */ 63f62bae50SIngo Molnar unsigned int boot_cpu_physical_apicid = -1U; 64f62bae50SIngo Molnar 65f62bae50SIngo Molnar /* 66f62bae50SIngo Molnar * The highest APIC ID seen during enumeration. 67f62bae50SIngo Molnar */ 68f62bae50SIngo Molnar unsigned int max_physical_apicid; 69f62bae50SIngo Molnar 70f62bae50SIngo Molnar /* 71f62bae50SIngo Molnar * Bitmask of physically existing CPUs: 72f62bae50SIngo Molnar */ 73f62bae50SIngo Molnar physid_mask_t phys_cpu_present_map; 74f62bae50SIngo Molnar 75f62bae50SIngo Molnar /* 76f62bae50SIngo Molnar * Map cpu index to physical APIC ID 77f62bae50SIngo Molnar */ 780816b0f0SVlad Zolotarov DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); 790816b0f0SVlad Zolotarov DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); 80f62bae50SIngo Molnar EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 81f62bae50SIngo Molnar EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 82f62bae50SIngo Molnar 83f62bae50SIngo Molnar #ifdef CONFIG_X86_32 844c321ff8STejun Heo 854c321ff8STejun Heo /* 864c321ff8STejun Heo * On x86_32, the mapping between cpu and logical apicid may vary 874c321ff8STejun Heo * depending on apic in use. The following early percpu variable is 884c321ff8STejun Heo * used for the mapping. This is where the behaviors of x86_64 and 32 894c321ff8STejun Heo * actually diverge. Let's keep it ugly for now. 904c321ff8STejun Heo */ 910816b0f0SVlad Zolotarov DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); 924c321ff8STejun Heo 93f62bae50SIngo Molnar /* Local APIC was disabled by the BIOS and enabled by the kernel */ 94f62bae50SIngo Molnar static int enabled_via_apicbase; 95f62bae50SIngo Molnar 96c0eaa453SCyrill Gorcunov /* 97c0eaa453SCyrill Gorcunov * Handle interrupt mode configuration register (IMCR). 98c0eaa453SCyrill Gorcunov * This register controls whether the interrupt signals 99c0eaa453SCyrill Gorcunov * that reach the BSP come from the master PIC or from the 100c0eaa453SCyrill Gorcunov * local APIC. Before entering Symmetric I/O Mode, either 101c0eaa453SCyrill Gorcunov * the BIOS or the operating system must switch out of 102c0eaa453SCyrill Gorcunov * PIC Mode by changing the IMCR. 103c0eaa453SCyrill Gorcunov */ 1045cda395fSAlexander van Heukelum static inline void imcr_pic_to_apic(void) 105c0eaa453SCyrill Gorcunov { 106c0eaa453SCyrill Gorcunov /* select IMCR register */ 107c0eaa453SCyrill Gorcunov outb(0x70, 0x22); 108c0eaa453SCyrill Gorcunov /* NMI and 8259 INTR go through APIC */ 109c0eaa453SCyrill Gorcunov outb(0x01, 0x23); 110c0eaa453SCyrill Gorcunov } 111c0eaa453SCyrill Gorcunov 1125cda395fSAlexander van Heukelum static inline void imcr_apic_to_pic(void) 113c0eaa453SCyrill Gorcunov { 114c0eaa453SCyrill Gorcunov /* select IMCR register */ 115c0eaa453SCyrill Gorcunov outb(0x70, 0x22); 116c0eaa453SCyrill Gorcunov /* NMI and 8259 INTR go directly to BSP */ 117c0eaa453SCyrill Gorcunov outb(0x00, 0x23); 118c0eaa453SCyrill Gorcunov } 119f62bae50SIngo Molnar #endif 120f62bae50SIngo Molnar 121279f1461SSuresh Siddha /* 122279f1461SSuresh Siddha * Knob to control our willingness to enable the local APIC. 123279f1461SSuresh Siddha * 124279f1461SSuresh Siddha * +1=force-enable 125279f1461SSuresh Siddha */ 126279f1461SSuresh Siddha static int force_enable_local_apic __initdata; 127279f1461SSuresh Siddha /* 128279f1461SSuresh Siddha * APIC command line parameters 129279f1461SSuresh Siddha */ 130279f1461SSuresh Siddha static int __init parse_lapic(char *arg) 131279f1461SSuresh Siddha { 132279f1461SSuresh Siddha if (config_enabled(CONFIG_X86_32) && !arg) 133279f1461SSuresh Siddha force_enable_local_apic = 1; 134279f1461SSuresh Siddha else if (!strncmp(arg, "notscdeadline", 13)) 135279f1461SSuresh Siddha setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 136279f1461SSuresh Siddha return 0; 137279f1461SSuresh Siddha } 138279f1461SSuresh Siddha early_param("lapic", parse_lapic); 139279f1461SSuresh Siddha 140f62bae50SIngo Molnar #ifdef CONFIG_X86_64 141f62bae50SIngo Molnar static int apic_calibrate_pmtmr __initdata; 142f62bae50SIngo Molnar static __init int setup_apicpmtimer(char *s) 143f62bae50SIngo Molnar { 144f62bae50SIngo Molnar apic_calibrate_pmtmr = 1; 145f62bae50SIngo Molnar notsc_setup(NULL); 146f62bae50SIngo Molnar return 0; 147f62bae50SIngo Molnar } 148f62bae50SIngo Molnar __setup("apicpmtimer", setup_apicpmtimer); 149f62bae50SIngo Molnar #endif 150f62bae50SIngo Molnar 151fc1edaf9SSuresh Siddha int x2apic_mode; 152f62bae50SIngo Molnar #ifdef CONFIG_X86_X2APIC 153f62bae50SIngo Molnar /* x2apic enabled before OS handover */ 154fb209bd8SYinghai Lu int x2apic_preenabled; 155fb209bd8SYinghai Lu static int x2apic_disabled; 156a31bc327SYinghai Lu static int nox2apic; 157f62bae50SIngo Molnar static __init int setup_nox2apic(char *str) 158f62bae50SIngo Molnar { 15939d83a5dSSuresh Siddha if (x2apic_enabled()) { 160a31bc327SYinghai Lu int apicid = native_apic_msr_read(APIC_ID); 161a31bc327SYinghai Lu 162a31bc327SYinghai Lu if (apicid >= 255) { 163a31bc327SYinghai Lu pr_warning("Apicid: %08x, cannot enforce nox2apic\n", 164a31bc327SYinghai Lu apicid); 16539d83a5dSSuresh Siddha return 0; 16639d83a5dSSuresh Siddha } 16739d83a5dSSuresh Siddha 168a31bc327SYinghai Lu pr_warning("x2apic already enabled. will disable it\n"); 169a31bc327SYinghai Lu } else 170f62bae50SIngo Molnar setup_clear_cpu_cap(X86_FEATURE_X2APIC); 171a31bc327SYinghai Lu 172a31bc327SYinghai Lu nox2apic = 1; 173a31bc327SYinghai Lu 174f62bae50SIngo Molnar return 0; 175f62bae50SIngo Molnar } 176f62bae50SIngo Molnar early_param("nox2apic", setup_nox2apic); 177f62bae50SIngo Molnar #endif 178f62bae50SIngo Molnar 179f62bae50SIngo Molnar unsigned long mp_lapic_addr; 180f62bae50SIngo Molnar int disable_apic; 181f62bae50SIngo Molnar /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 18225874a29SHenrik Kretzschmar static int disable_apic_timer __initdata; 183f62bae50SIngo Molnar /* Local APIC timer works in C2 */ 184f62bae50SIngo Molnar int local_apic_timer_c2_ok; 185f62bae50SIngo Molnar EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 186f62bae50SIngo Molnar 187f62bae50SIngo Molnar int first_system_vector = 0xfe; 188f62bae50SIngo Molnar 189f62bae50SIngo Molnar /* 190f62bae50SIngo Molnar * Debug level, exported for io_apic.c 191f62bae50SIngo Molnar */ 192f62bae50SIngo Molnar unsigned int apic_verbosity; 193f62bae50SIngo Molnar 194f62bae50SIngo Molnar int pic_mode; 195f62bae50SIngo Molnar 196f62bae50SIngo Molnar /* Have we found an MP table */ 197f62bae50SIngo Molnar int smp_found_config; 198f62bae50SIngo Molnar 199f62bae50SIngo Molnar static struct resource lapic_resource = { 200f62bae50SIngo Molnar .name = "Local APIC", 201f62bae50SIngo Molnar .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 202f62bae50SIngo Molnar }; 203f62bae50SIngo Molnar 2041ade93efSJacob Pan unsigned int lapic_timer_frequency = 0; 205f62bae50SIngo Molnar 206f62bae50SIngo Molnar static void apic_pm_activate(void); 207f62bae50SIngo Molnar 208f62bae50SIngo Molnar static unsigned long apic_phys; 209f62bae50SIngo Molnar 210f62bae50SIngo Molnar /* 211f62bae50SIngo Molnar * Get the LAPIC version 212f62bae50SIngo Molnar */ 213f62bae50SIngo Molnar static inline int lapic_get_version(void) 214f62bae50SIngo Molnar { 215f62bae50SIngo Molnar return GET_APIC_VERSION(apic_read(APIC_LVR)); 216f62bae50SIngo Molnar } 217f62bae50SIngo Molnar 218f62bae50SIngo Molnar /* 219f62bae50SIngo Molnar * Check, if the APIC is integrated or a separate chip 220f62bae50SIngo Molnar */ 221f62bae50SIngo Molnar static inline int lapic_is_integrated(void) 222f62bae50SIngo Molnar { 223f62bae50SIngo Molnar #ifdef CONFIG_X86_64 224f62bae50SIngo Molnar return 1; 225f62bae50SIngo Molnar #else 226f62bae50SIngo Molnar return APIC_INTEGRATED(lapic_get_version()); 227f62bae50SIngo Molnar #endif 228f62bae50SIngo Molnar } 229f62bae50SIngo Molnar 230f62bae50SIngo Molnar /* 231f62bae50SIngo Molnar * Check, whether this is a modern or a first generation APIC 232f62bae50SIngo Molnar */ 233f62bae50SIngo Molnar static int modern_apic(void) 234f62bae50SIngo Molnar { 235f62bae50SIngo Molnar /* AMD systems use old APIC versions, so check the CPU */ 236f62bae50SIngo Molnar if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 237f62bae50SIngo Molnar boot_cpu_data.x86 >= 0xf) 238f62bae50SIngo Molnar return 1; 239f62bae50SIngo Molnar return lapic_get_version() >= 0x14; 240f62bae50SIngo Molnar } 241f62bae50SIngo Molnar 24208306ce6SCyrill Gorcunov /* 243a933c618SCyrill Gorcunov * right after this call apic become NOOP driven 244a933c618SCyrill Gorcunov * so apic->write/read doesn't do anything 24508306ce6SCyrill Gorcunov */ 24625874a29SHenrik Kretzschmar static void __init apic_disable(void) 24708306ce6SCyrill Gorcunov { 248f88f2b4fSCyrill Gorcunov pr_info("APIC: switched to apic NOOP\n"); 249a933c618SCyrill Gorcunov apic = &apic_noop; 25008306ce6SCyrill Gorcunov } 25108306ce6SCyrill Gorcunov 252f62bae50SIngo Molnar void native_apic_wait_icr_idle(void) 253f62bae50SIngo Molnar { 254f62bae50SIngo Molnar while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 255f62bae50SIngo Molnar cpu_relax(); 256f62bae50SIngo Molnar } 257f62bae50SIngo Molnar 258f62bae50SIngo Molnar u32 native_safe_apic_wait_icr_idle(void) 259f62bae50SIngo Molnar { 260f62bae50SIngo Molnar u32 send_status; 261f62bae50SIngo Molnar int timeout; 262f62bae50SIngo Molnar 263f62bae50SIngo Molnar timeout = 0; 264f62bae50SIngo Molnar do { 265f62bae50SIngo Molnar send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 266f62bae50SIngo Molnar if (!send_status) 267f62bae50SIngo Molnar break; 268b49d7d87SFernando Luis Vazquez Cao inc_irq_stat(icr_read_retry_count); 269f62bae50SIngo Molnar udelay(100); 270f62bae50SIngo Molnar } while (timeout++ < 1000); 271f62bae50SIngo Molnar 272f62bae50SIngo Molnar return send_status; 273f62bae50SIngo Molnar } 274f62bae50SIngo Molnar 275f62bae50SIngo Molnar void native_apic_icr_write(u32 low, u32 id) 276f62bae50SIngo Molnar { 277f62bae50SIngo Molnar apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 278f62bae50SIngo Molnar apic_write(APIC_ICR, low); 279f62bae50SIngo Molnar } 280f62bae50SIngo Molnar 281f62bae50SIngo Molnar u64 native_apic_icr_read(void) 282f62bae50SIngo Molnar { 283f62bae50SIngo Molnar u32 icr1, icr2; 284f62bae50SIngo Molnar 285f62bae50SIngo Molnar icr2 = apic_read(APIC_ICR2); 286f62bae50SIngo Molnar icr1 = apic_read(APIC_ICR); 287f62bae50SIngo Molnar 288f62bae50SIngo Molnar return icr1 | ((u64)icr2 << 32); 289f62bae50SIngo Molnar } 290f62bae50SIngo Molnar 291f62bae50SIngo Molnar #ifdef CONFIG_X86_32 292f62bae50SIngo Molnar /** 293f62bae50SIngo Molnar * get_physical_broadcast - Get number of physical broadcast IDs 294f62bae50SIngo Molnar */ 295f62bae50SIngo Molnar int get_physical_broadcast(void) 296f62bae50SIngo Molnar { 297f62bae50SIngo Molnar return modern_apic() ? 0xff : 0xf; 298f62bae50SIngo Molnar } 299f62bae50SIngo Molnar #endif 300f62bae50SIngo Molnar 301f62bae50SIngo Molnar /** 302f62bae50SIngo Molnar * lapic_get_maxlvt - get the maximum number of local vector table entries 303f62bae50SIngo Molnar */ 304f62bae50SIngo Molnar int lapic_get_maxlvt(void) 305f62bae50SIngo Molnar { 306f62bae50SIngo Molnar unsigned int v; 307f62bae50SIngo Molnar 308f62bae50SIngo Molnar v = apic_read(APIC_LVR); 309f62bae50SIngo Molnar /* 310f62bae50SIngo Molnar * - we always have APIC integrated on 64bit mode 311f62bae50SIngo Molnar * - 82489DXs do not report # of LVT entries 312f62bae50SIngo Molnar */ 313f62bae50SIngo Molnar return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; 314f62bae50SIngo Molnar } 315f62bae50SIngo Molnar 316f62bae50SIngo Molnar /* 317f62bae50SIngo Molnar * Local APIC timer 318f62bae50SIngo Molnar */ 319f62bae50SIngo Molnar 320f62bae50SIngo Molnar /* Clock divisor */ 321f62bae50SIngo Molnar #define APIC_DIVISOR 16 322279f1461SSuresh Siddha #define TSC_DIVISOR 32 323f62bae50SIngo Molnar 324f62bae50SIngo Molnar /* 325f62bae50SIngo Molnar * This function sets up the local APIC timer, with a timeout of 326f62bae50SIngo Molnar * 'clocks' APIC bus clock. During calibration we actually call 327f62bae50SIngo Molnar * this function twice on the boot CPU, once with a bogus timeout 328f62bae50SIngo Molnar * value, second time for real. The other (noncalibrating) CPUs 329f62bae50SIngo Molnar * call this function only once, with the real, calibrated value. 330f62bae50SIngo Molnar * 331f62bae50SIngo Molnar * We do reads before writes even if unnecessary, to get around the 332f62bae50SIngo Molnar * P5 APIC double write bug. 333f62bae50SIngo Molnar */ 334f62bae50SIngo Molnar static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 335f62bae50SIngo Molnar { 336f62bae50SIngo Molnar unsigned int lvtt_value, tmp_value; 337f62bae50SIngo Molnar 338f62bae50SIngo Molnar lvtt_value = LOCAL_TIMER_VECTOR; 339f62bae50SIngo Molnar if (!oneshot) 340f62bae50SIngo Molnar lvtt_value |= APIC_LVT_TIMER_PERIODIC; 341279f1461SSuresh Siddha else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 342279f1461SSuresh Siddha lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; 343279f1461SSuresh Siddha 344f62bae50SIngo Molnar if (!lapic_is_integrated()) 345f62bae50SIngo Molnar lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 346f62bae50SIngo Molnar 347f62bae50SIngo Molnar if (!irqen) 348f62bae50SIngo Molnar lvtt_value |= APIC_LVT_MASKED; 349f62bae50SIngo Molnar 350f62bae50SIngo Molnar apic_write(APIC_LVTT, lvtt_value); 351f62bae50SIngo Molnar 352279f1461SSuresh Siddha if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { 353279f1461SSuresh Siddha printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); 354279f1461SSuresh Siddha return; 355279f1461SSuresh Siddha } 356279f1461SSuresh Siddha 357f62bae50SIngo Molnar /* 358f62bae50SIngo Molnar * Divide PICLK by 16 359f62bae50SIngo Molnar */ 360f62bae50SIngo Molnar tmp_value = apic_read(APIC_TDCR); 361f62bae50SIngo Molnar apic_write(APIC_TDCR, 362f62bae50SIngo Molnar (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 363f62bae50SIngo Molnar APIC_TDR_DIV_16); 364f62bae50SIngo Molnar 365f62bae50SIngo Molnar if (!oneshot) 366f62bae50SIngo Molnar apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 367f62bae50SIngo Molnar } 368f62bae50SIngo Molnar 369f62bae50SIngo Molnar /* 370a68c439bSRobert Richter * Setup extended LVT, AMD specific 371f62bae50SIngo Molnar * 372a68c439bSRobert Richter * Software should use the LVT offsets the BIOS provides. The offsets 373a68c439bSRobert Richter * are determined by the subsystems using it like those for MCE 374a68c439bSRobert Richter * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 375a68c439bSRobert Richter * are supported. Beginning with family 10h at least 4 offsets are 376a68c439bSRobert Richter * available. 377f62bae50SIngo Molnar * 378a68c439bSRobert Richter * Since the offsets must be consistent for all cores, we keep track 379a68c439bSRobert Richter * of the LVT offsets in software and reserve the offset for the same 380a68c439bSRobert Richter * vector also to be used on other cores. An offset is freed by 381a68c439bSRobert Richter * setting the entry to APIC_EILVT_MASKED. 382a68c439bSRobert Richter * 383a68c439bSRobert Richter * If the BIOS is right, there should be no conflicts. Otherwise a 384a68c439bSRobert Richter * "[Firmware Bug]: ..." error message is generated. However, if 385a68c439bSRobert Richter * software does not properly determines the offsets, it is not 386a68c439bSRobert Richter * necessarily a BIOS bug. 387f62bae50SIngo Molnar */ 388f62bae50SIngo Molnar 389a68c439bSRobert Richter static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 390f62bae50SIngo Molnar 391a68c439bSRobert Richter static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 392a68c439bSRobert Richter { 393a68c439bSRobert Richter return (old & APIC_EILVT_MASKED) 394a68c439bSRobert Richter || (new == APIC_EILVT_MASKED) 395a68c439bSRobert Richter || ((new & ~APIC_EILVT_MASKED) == old); 396a68c439bSRobert Richter } 397a68c439bSRobert Richter 398a68c439bSRobert Richter static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 399a68c439bSRobert Richter { 4008abc3122SRobert Richter unsigned int rsvd, vector; 401a68c439bSRobert Richter 402a68c439bSRobert Richter if (offset >= APIC_EILVT_NR_MAX) 403a68c439bSRobert Richter return ~0; 404a68c439bSRobert Richter 4058abc3122SRobert Richter rsvd = atomic_read(&eilvt_offsets[offset]); 406a68c439bSRobert Richter do { 4078abc3122SRobert Richter vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ 4088abc3122SRobert Richter if (vector && !eilvt_entry_is_changeable(vector, new)) 409a68c439bSRobert Richter /* may not change if vectors are different */ 410a68c439bSRobert Richter return rsvd; 411a68c439bSRobert Richter rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 412a68c439bSRobert Richter } while (rsvd != new); 413a68c439bSRobert Richter 4148abc3122SRobert Richter rsvd &= ~APIC_EILVT_MASKED; 4158abc3122SRobert Richter if (rsvd && rsvd != vector) 4168abc3122SRobert Richter pr_info("LVT offset %d assigned for vector 0x%02x\n", 4178abc3122SRobert Richter offset, rsvd); 4188abc3122SRobert Richter 419a68c439bSRobert Richter return new; 420a68c439bSRobert Richter } 421a68c439bSRobert Richter 422a68c439bSRobert Richter /* 423a68c439bSRobert Richter * If mask=1, the LVT entry does not generate interrupts while mask=0 424cbf74ceaSRobert Richter * enables the vector. See also the BKDGs. Must be called with 425cbf74ceaSRobert Richter * preemption disabled. 426a68c439bSRobert Richter */ 427a68c439bSRobert Richter 42827afdf20SRobert Richter int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 429a68c439bSRobert Richter { 430a68c439bSRobert Richter unsigned long reg = APIC_EILVTn(offset); 431a68c439bSRobert Richter unsigned int new, old, reserved; 432a68c439bSRobert Richter 433a68c439bSRobert Richter new = (mask << 16) | (msg_type << 8) | vector; 434a68c439bSRobert Richter old = apic_read(reg); 435a68c439bSRobert Richter reserved = reserve_eilvt_offset(offset, new); 436a68c439bSRobert Richter 437a68c439bSRobert Richter if (reserved != new) { 438eb48c9cbSRobert Richter pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 439eb48c9cbSRobert Richter "vector 0x%x, but the register is already in use for " 440eb48c9cbSRobert Richter "vector 0x%x on another cpu\n", 441eb48c9cbSRobert Richter smp_processor_id(), reg, offset, new, reserved); 442a68c439bSRobert Richter return -EINVAL; 443a68c439bSRobert Richter } 444a68c439bSRobert Richter 445a68c439bSRobert Richter if (!eilvt_entry_is_changeable(old, new)) { 446eb48c9cbSRobert Richter pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 447eb48c9cbSRobert Richter "vector 0x%x, but the register is already in use for " 448eb48c9cbSRobert Richter "vector 0x%x on this cpu\n", 449eb48c9cbSRobert Richter smp_processor_id(), reg, offset, new, old); 450a68c439bSRobert Richter return -EBUSY; 451a68c439bSRobert Richter } 452a68c439bSRobert Richter 453a68c439bSRobert Richter apic_write(reg, new); 454a68c439bSRobert Richter 455a68c439bSRobert Richter return 0; 456f62bae50SIngo Molnar } 45727afdf20SRobert Richter EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 458f62bae50SIngo Molnar 459f62bae50SIngo Molnar /* 460f62bae50SIngo Molnar * Program the next event, relative to now 461f62bae50SIngo Molnar */ 462f62bae50SIngo Molnar static int lapic_next_event(unsigned long delta, 463f62bae50SIngo Molnar struct clock_event_device *evt) 464f62bae50SIngo Molnar { 465f62bae50SIngo Molnar apic_write(APIC_TMICT, delta); 466f62bae50SIngo Molnar return 0; 467f62bae50SIngo Molnar } 468f62bae50SIngo Molnar 469279f1461SSuresh Siddha static int lapic_next_deadline(unsigned long delta, 470279f1461SSuresh Siddha struct clock_event_device *evt) 471279f1461SSuresh Siddha { 472279f1461SSuresh Siddha u64 tsc; 473279f1461SSuresh Siddha 474279f1461SSuresh Siddha rdtscll(tsc); 475279f1461SSuresh Siddha wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); 476279f1461SSuresh Siddha return 0; 477279f1461SSuresh Siddha } 478279f1461SSuresh Siddha 479f62bae50SIngo Molnar /* 480f62bae50SIngo Molnar * Setup the lapic timer in periodic or oneshot mode 481f62bae50SIngo Molnar */ 482f62bae50SIngo Molnar static void lapic_timer_setup(enum clock_event_mode mode, 483f62bae50SIngo Molnar struct clock_event_device *evt) 484f62bae50SIngo Molnar { 485f62bae50SIngo Molnar unsigned long flags; 486f62bae50SIngo Molnar unsigned int v; 487f62bae50SIngo Molnar 488f62bae50SIngo Molnar /* Lapic used as dummy for broadcast ? */ 489f62bae50SIngo Molnar if (evt->features & CLOCK_EVT_FEAT_DUMMY) 490f62bae50SIngo Molnar return; 491f62bae50SIngo Molnar 492f62bae50SIngo Molnar local_irq_save(flags); 493f62bae50SIngo Molnar 494f62bae50SIngo Molnar switch (mode) { 495f62bae50SIngo Molnar case CLOCK_EVT_MODE_PERIODIC: 496f62bae50SIngo Molnar case CLOCK_EVT_MODE_ONESHOT: 4971ade93efSJacob Pan __setup_APIC_LVTT(lapic_timer_frequency, 498f62bae50SIngo Molnar mode != CLOCK_EVT_MODE_PERIODIC, 1); 499f62bae50SIngo Molnar break; 500f62bae50SIngo Molnar case CLOCK_EVT_MODE_UNUSED: 501f62bae50SIngo Molnar case CLOCK_EVT_MODE_SHUTDOWN: 502f62bae50SIngo Molnar v = apic_read(APIC_LVTT); 503f62bae50SIngo Molnar v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 504f62bae50SIngo Molnar apic_write(APIC_LVTT, v); 5056f9b4100SAndreas Herrmann apic_write(APIC_TMICT, 0); 506f62bae50SIngo Molnar break; 507f62bae50SIngo Molnar case CLOCK_EVT_MODE_RESUME: 508f62bae50SIngo Molnar /* Nothing to do here */ 509f62bae50SIngo Molnar break; 510f62bae50SIngo Molnar } 511f62bae50SIngo Molnar 512f62bae50SIngo Molnar local_irq_restore(flags); 513f62bae50SIngo Molnar } 514f62bae50SIngo Molnar 515f62bae50SIngo Molnar /* 516f62bae50SIngo Molnar * Local APIC timer broadcast function 517f62bae50SIngo Molnar */ 518f62bae50SIngo Molnar static void lapic_timer_broadcast(const struct cpumask *mask) 519f62bae50SIngo Molnar { 520f62bae50SIngo Molnar #ifdef CONFIG_SMP 521f62bae50SIngo Molnar apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 522f62bae50SIngo Molnar #endif 523f62bae50SIngo Molnar } 524f62bae50SIngo Molnar 52525874a29SHenrik Kretzschmar 52625874a29SHenrik Kretzschmar /* 52725874a29SHenrik Kretzschmar * The local apic timer can be used for any function which is CPU local. 52825874a29SHenrik Kretzschmar */ 52925874a29SHenrik Kretzschmar static struct clock_event_device lapic_clockevent = { 53025874a29SHenrik Kretzschmar .name = "lapic", 53125874a29SHenrik Kretzschmar .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT 53225874a29SHenrik Kretzschmar | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, 53325874a29SHenrik Kretzschmar .shift = 32, 53425874a29SHenrik Kretzschmar .set_mode = lapic_timer_setup, 53525874a29SHenrik Kretzschmar .set_next_event = lapic_next_event, 53625874a29SHenrik Kretzschmar .broadcast = lapic_timer_broadcast, 53725874a29SHenrik Kretzschmar .rating = 100, 53825874a29SHenrik Kretzschmar .irq = -1, 53925874a29SHenrik Kretzschmar }; 54025874a29SHenrik Kretzschmar static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 54125874a29SHenrik Kretzschmar 542f62bae50SIngo Molnar /* 543421f91d2SUwe Kleine-König * Setup the local APIC timer for this CPU. Copy the initialized values 544f62bae50SIngo Molnar * of the boot CPU and register the clock event in the framework. 545f62bae50SIngo Molnar */ 546f62bae50SIngo Molnar static void __cpuinit setup_APIC_timer(void) 547f62bae50SIngo Molnar { 548f62bae50SIngo Molnar struct clock_event_device *levt = &__get_cpu_var(lapic_events); 549f62bae50SIngo Molnar 550349c004eSChristoph Lameter if (this_cpu_has(X86_FEATURE_ARAT)) { 551db954b58SVenkatesh Pallipadi lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 552db954b58SVenkatesh Pallipadi /* Make LAPIC timer preferrable over percpu HPET */ 553db954b58SVenkatesh Pallipadi lapic_clockevent.rating = 150; 554db954b58SVenkatesh Pallipadi } 555db954b58SVenkatesh Pallipadi 556f62bae50SIngo Molnar memcpy(levt, &lapic_clockevent, sizeof(*levt)); 557f62bae50SIngo Molnar levt->cpumask = cpumask_of(smp_processor_id()); 558f62bae50SIngo Molnar 559279f1461SSuresh Siddha if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 560279f1461SSuresh Siddha levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | 561279f1461SSuresh Siddha CLOCK_EVT_FEAT_DUMMY); 562279f1461SSuresh Siddha levt->set_next_event = lapic_next_deadline; 563279f1461SSuresh Siddha clockevents_config_and_register(levt, 564279f1461SSuresh Siddha (tsc_khz / TSC_DIVISOR) * 1000, 565279f1461SSuresh Siddha 0xF, ~0UL); 566279f1461SSuresh Siddha } else 567f62bae50SIngo Molnar clockevents_register_device(levt); 568f62bae50SIngo Molnar } 569f62bae50SIngo Molnar 570f62bae50SIngo Molnar /* 571f62bae50SIngo Molnar * In this functions we calibrate APIC bus clocks to the external timer. 572f62bae50SIngo Molnar * 573f62bae50SIngo Molnar * We want to do the calibration only once since we want to have local timer 574f62bae50SIngo Molnar * irqs syncron. CPUs connected by the same APIC bus have the very same bus 575f62bae50SIngo Molnar * frequency. 576f62bae50SIngo Molnar * 577f62bae50SIngo Molnar * This was previously done by reading the PIT/HPET and waiting for a wrap 578f62bae50SIngo Molnar * around to find out, that a tick has elapsed. I have a box, where the PIT 579f62bae50SIngo Molnar * readout is broken, so it never gets out of the wait loop again. This was 580f62bae50SIngo Molnar * also reported by others. 581f62bae50SIngo Molnar * 582f62bae50SIngo Molnar * Monitoring the jiffies value is inaccurate and the clockevents 583f62bae50SIngo Molnar * infrastructure allows us to do a simple substitution of the interrupt 584f62bae50SIngo Molnar * handler. 585f62bae50SIngo Molnar * 586f62bae50SIngo Molnar * The calibration routine also uses the pm_timer when possible, as the PIT 587f62bae50SIngo Molnar * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 588f62bae50SIngo Molnar * back to normal later in the boot process). 589f62bae50SIngo Molnar */ 590f62bae50SIngo Molnar 591f62bae50SIngo Molnar #define LAPIC_CAL_LOOPS (HZ/10) 592f62bae50SIngo Molnar 593f62bae50SIngo Molnar static __initdata int lapic_cal_loops = -1; 594f62bae50SIngo Molnar static __initdata long lapic_cal_t1, lapic_cal_t2; 595f62bae50SIngo Molnar static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 596f62bae50SIngo Molnar static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 597f62bae50SIngo Molnar static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 598f62bae50SIngo Molnar 599f62bae50SIngo Molnar /* 600f62bae50SIngo Molnar * Temporary interrupt handler. 601f62bae50SIngo Molnar */ 602f62bae50SIngo Molnar static void __init lapic_cal_handler(struct clock_event_device *dev) 603f62bae50SIngo Molnar { 604f62bae50SIngo Molnar unsigned long long tsc = 0; 605f62bae50SIngo Molnar long tapic = apic_read(APIC_TMCCT); 606f62bae50SIngo Molnar unsigned long pm = acpi_pm_read_early(); 607f62bae50SIngo Molnar 608f62bae50SIngo Molnar if (cpu_has_tsc) 609f62bae50SIngo Molnar rdtscll(tsc); 610f62bae50SIngo Molnar 611f62bae50SIngo Molnar switch (lapic_cal_loops++) { 612f62bae50SIngo Molnar case 0: 613f62bae50SIngo Molnar lapic_cal_t1 = tapic; 614f62bae50SIngo Molnar lapic_cal_tsc1 = tsc; 615f62bae50SIngo Molnar lapic_cal_pm1 = pm; 616f62bae50SIngo Molnar lapic_cal_j1 = jiffies; 617f62bae50SIngo Molnar break; 618f62bae50SIngo Molnar 619f62bae50SIngo Molnar case LAPIC_CAL_LOOPS: 620f62bae50SIngo Molnar lapic_cal_t2 = tapic; 621f62bae50SIngo Molnar lapic_cal_tsc2 = tsc; 622f62bae50SIngo Molnar if (pm < lapic_cal_pm1) 623f62bae50SIngo Molnar pm += ACPI_PM_OVRRUN; 624f62bae50SIngo Molnar lapic_cal_pm2 = pm; 625f62bae50SIngo Molnar lapic_cal_j2 = jiffies; 626f62bae50SIngo Molnar break; 627f62bae50SIngo Molnar } 628f62bae50SIngo Molnar } 629f62bae50SIngo Molnar 630f62bae50SIngo Molnar static int __init 631f62bae50SIngo Molnar calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 632f62bae50SIngo Molnar { 633f62bae50SIngo Molnar const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 634f62bae50SIngo Molnar const long pm_thresh = pm_100ms / 100; 635f62bae50SIngo Molnar unsigned long mult; 636f62bae50SIngo Molnar u64 res; 637f62bae50SIngo Molnar 638f62bae50SIngo Molnar #ifndef CONFIG_X86_PM_TIMER 639f62bae50SIngo Molnar return -1; 640f62bae50SIngo Molnar #endif 641f62bae50SIngo Molnar 642f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 643f62bae50SIngo Molnar 644f62bae50SIngo Molnar /* Check, if the PM timer is available */ 645f62bae50SIngo Molnar if (!deltapm) 646f62bae50SIngo Molnar return -1; 647f62bae50SIngo Molnar 648f62bae50SIngo Molnar mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 649f62bae50SIngo Molnar 650f62bae50SIngo Molnar if (deltapm > (pm_100ms - pm_thresh) && 651f62bae50SIngo Molnar deltapm < (pm_100ms + pm_thresh)) { 652f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 653f62bae50SIngo Molnar return 0; 654f62bae50SIngo Molnar } 655f62bae50SIngo Molnar 656f62bae50SIngo Molnar res = (((u64)deltapm) * mult) >> 22; 657f62bae50SIngo Molnar do_div(res, 1000000); 658f62bae50SIngo Molnar pr_warning("APIC calibration not consistent " 659f62bae50SIngo Molnar "with PM-Timer: %ldms instead of 100ms\n",(long)res); 660f62bae50SIngo Molnar 661f62bae50SIngo Molnar /* Correct the lapic counter value */ 662f62bae50SIngo Molnar res = (((u64)(*delta)) * pm_100ms); 663f62bae50SIngo Molnar do_div(res, deltapm); 664f62bae50SIngo Molnar pr_info("APIC delta adjusted to PM-Timer: " 665f62bae50SIngo Molnar "%lu (%ld)\n", (unsigned long)res, *delta); 666f62bae50SIngo Molnar *delta = (long)res; 667f62bae50SIngo Molnar 668f62bae50SIngo Molnar /* Correct the tsc counter value */ 669f62bae50SIngo Molnar if (cpu_has_tsc) { 670f62bae50SIngo Molnar res = (((u64)(*deltatsc)) * pm_100ms); 671f62bae50SIngo Molnar do_div(res, deltapm); 672f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 673f62bae50SIngo Molnar "PM-Timer: %lu (%ld)\n", 674f62bae50SIngo Molnar (unsigned long)res, *deltatsc); 675f62bae50SIngo Molnar *deltatsc = (long)res; 676f62bae50SIngo Molnar } 677f62bae50SIngo Molnar 678f62bae50SIngo Molnar return 0; 679f62bae50SIngo Molnar } 680f62bae50SIngo Molnar 681f62bae50SIngo Molnar static int __init calibrate_APIC_clock(void) 682f62bae50SIngo Molnar { 683f62bae50SIngo Molnar struct clock_event_device *levt = &__get_cpu_var(lapic_events); 684f62bae50SIngo Molnar void (*real_handler)(struct clock_event_device *dev); 685f62bae50SIngo Molnar unsigned long deltaj; 686f62bae50SIngo Molnar long delta, deltatsc; 687f62bae50SIngo Molnar int pm_referenced = 0; 688f62bae50SIngo Molnar 6891ade93efSJacob Pan /** 6901ade93efSJacob Pan * check if lapic timer has already been calibrated by platform 6911ade93efSJacob Pan * specific routine, such as tsc calibration code. if so, we just fill 6921ade93efSJacob Pan * in the clockevent structure and return. 6931ade93efSJacob Pan */ 6941ade93efSJacob Pan 695279f1461SSuresh Siddha if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 696279f1461SSuresh Siddha return 0; 697279f1461SSuresh Siddha } else if (lapic_timer_frequency) { 6981ade93efSJacob Pan apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", 6991ade93efSJacob Pan lapic_timer_frequency); 7001ade93efSJacob Pan lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR, 7011ade93efSJacob Pan TICK_NSEC, lapic_clockevent.shift); 7021ade93efSJacob Pan lapic_clockevent.max_delta_ns = 7031ade93efSJacob Pan clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); 7041ade93efSJacob Pan lapic_clockevent.min_delta_ns = 7051ade93efSJacob Pan clockevent_delta2ns(0xF, &lapic_clockevent); 7061ade93efSJacob Pan lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 7071ade93efSJacob Pan return 0; 7081ade93efSJacob Pan } 7091ade93efSJacob Pan 710279f1461SSuresh Siddha apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 711279f1461SSuresh Siddha "calibrating APIC timer ...\n"); 712279f1461SSuresh Siddha 713f62bae50SIngo Molnar local_irq_disable(); 714f62bae50SIngo Molnar 715f62bae50SIngo Molnar /* Replace the global interrupt handler */ 716f62bae50SIngo Molnar real_handler = global_clock_event->event_handler; 717f62bae50SIngo Molnar global_clock_event->event_handler = lapic_cal_handler; 718f62bae50SIngo Molnar 719f62bae50SIngo Molnar /* 720f62bae50SIngo Molnar * Setup the APIC counter to maximum. There is no way the lapic 721f62bae50SIngo Molnar * can underflow in the 100ms detection time frame 722f62bae50SIngo Molnar */ 723f62bae50SIngo Molnar __setup_APIC_LVTT(0xffffffff, 0, 0); 724f62bae50SIngo Molnar 725f62bae50SIngo Molnar /* Let the interrupts run */ 726f62bae50SIngo Molnar local_irq_enable(); 727f62bae50SIngo Molnar 728f62bae50SIngo Molnar while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 729f62bae50SIngo Molnar cpu_relax(); 730f62bae50SIngo Molnar 731f62bae50SIngo Molnar local_irq_disable(); 732f62bae50SIngo Molnar 733f62bae50SIngo Molnar /* Restore the real event handler */ 734f62bae50SIngo Molnar global_clock_event->event_handler = real_handler; 735f62bae50SIngo Molnar 736f62bae50SIngo Molnar /* Build delta t1-t2 as apic timer counts down */ 737f62bae50SIngo Molnar delta = lapic_cal_t1 - lapic_cal_t2; 738f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 739f62bae50SIngo Molnar 740f62bae50SIngo Molnar deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 741f62bae50SIngo Molnar 742f62bae50SIngo Molnar /* we trust the PM based calibration if possible */ 743f62bae50SIngo Molnar pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 744f62bae50SIngo Molnar &delta, &deltatsc); 745f62bae50SIngo Molnar 746f62bae50SIngo Molnar /* Calculate the scaled math multiplication factor */ 747f62bae50SIngo Molnar lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 748f62bae50SIngo Molnar lapic_clockevent.shift); 749f62bae50SIngo Molnar lapic_clockevent.max_delta_ns = 7504aed89d6SPierre Tardy clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 751f62bae50SIngo Molnar lapic_clockevent.min_delta_ns = 752f62bae50SIngo Molnar clockevent_delta2ns(0xF, &lapic_clockevent); 753f62bae50SIngo Molnar 7541ade93efSJacob Pan lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 755f62bae50SIngo Molnar 756f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 757411462f6SThomas Gleixner apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 758f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 7591ade93efSJacob Pan lapic_timer_frequency); 760f62bae50SIngo Molnar 761f62bae50SIngo Molnar if (cpu_has_tsc) { 762f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 763f62bae50SIngo Molnar "%ld.%04ld MHz.\n", 764f62bae50SIngo Molnar (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 765f62bae50SIngo Molnar (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 766f62bae50SIngo Molnar } 767f62bae50SIngo Molnar 768f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 769f62bae50SIngo Molnar "%u.%04u MHz.\n", 7701ade93efSJacob Pan lapic_timer_frequency / (1000000 / HZ), 7711ade93efSJacob Pan lapic_timer_frequency % (1000000 / HZ)); 772f62bae50SIngo Molnar 773f62bae50SIngo Molnar /* 774f62bae50SIngo Molnar * Do a sanity check on the APIC calibration result 775f62bae50SIngo Molnar */ 7761ade93efSJacob Pan if (lapic_timer_frequency < (1000000 / HZ)) { 777f62bae50SIngo Molnar local_irq_enable(); 778f62bae50SIngo Molnar pr_warning("APIC frequency too slow, disabling apic timer\n"); 779f62bae50SIngo Molnar return -1; 780f62bae50SIngo Molnar } 781f62bae50SIngo Molnar 782f62bae50SIngo Molnar levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 783f62bae50SIngo Molnar 784f62bae50SIngo Molnar /* 785f62bae50SIngo Molnar * PM timer calibration failed or not turned on 786f62bae50SIngo Molnar * so lets try APIC timer based calibration 787f62bae50SIngo Molnar */ 788f62bae50SIngo Molnar if (!pm_referenced) { 789f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 790f62bae50SIngo Molnar 791f62bae50SIngo Molnar /* 792f62bae50SIngo Molnar * Setup the apic timer manually 793f62bae50SIngo Molnar */ 794f62bae50SIngo Molnar levt->event_handler = lapic_cal_handler; 795f62bae50SIngo Molnar lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); 796f62bae50SIngo Molnar lapic_cal_loops = -1; 797f62bae50SIngo Molnar 798f62bae50SIngo Molnar /* Let the interrupts run */ 799f62bae50SIngo Molnar local_irq_enable(); 800f62bae50SIngo Molnar 801f62bae50SIngo Molnar while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 802f62bae50SIngo Molnar cpu_relax(); 803f62bae50SIngo Molnar 804f62bae50SIngo Molnar /* Stop the lapic timer */ 805f62bae50SIngo Molnar lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); 806f62bae50SIngo Molnar 807f62bae50SIngo Molnar /* Jiffies delta */ 808f62bae50SIngo Molnar deltaj = lapic_cal_j2 - lapic_cal_j1; 809f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 810f62bae50SIngo Molnar 811f62bae50SIngo Molnar /* Check, if the jiffies result is consistent */ 812f62bae50SIngo Molnar if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 813f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 814f62bae50SIngo Molnar else 815f62bae50SIngo Molnar levt->features |= CLOCK_EVT_FEAT_DUMMY; 816f62bae50SIngo Molnar } else 817f62bae50SIngo Molnar local_irq_enable(); 818f62bae50SIngo Molnar 819f62bae50SIngo Molnar if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 820f62bae50SIngo Molnar pr_warning("APIC timer disabled due to verification failure\n"); 821f62bae50SIngo Molnar return -1; 822f62bae50SIngo Molnar } 823f62bae50SIngo Molnar 824f62bae50SIngo Molnar return 0; 825f62bae50SIngo Molnar } 826f62bae50SIngo Molnar 827f62bae50SIngo Molnar /* 828f62bae50SIngo Molnar * Setup the boot APIC 829f62bae50SIngo Molnar * 830f62bae50SIngo Molnar * Calibrate and verify the result. 831f62bae50SIngo Molnar */ 832f62bae50SIngo Molnar void __init setup_boot_APIC_clock(void) 833f62bae50SIngo Molnar { 834f62bae50SIngo Molnar /* 835f62bae50SIngo Molnar * The local apic timer can be disabled via the kernel 836f62bae50SIngo Molnar * commandline or from the CPU detection code. Register the lapic 837f62bae50SIngo Molnar * timer as a dummy clock event source on SMP systems, so the 838f62bae50SIngo Molnar * broadcast mechanism is used. On UP systems simply ignore it. 839f62bae50SIngo Molnar */ 840f62bae50SIngo Molnar if (disable_apic_timer) { 841f62bae50SIngo Molnar pr_info("Disabling APIC timer\n"); 842f62bae50SIngo Molnar /* No broadcast on UP ! */ 843f62bae50SIngo Molnar if (num_possible_cpus() > 1) { 844f62bae50SIngo Molnar lapic_clockevent.mult = 1; 845f62bae50SIngo Molnar setup_APIC_timer(); 846f62bae50SIngo Molnar } 847f62bae50SIngo Molnar return; 848f62bae50SIngo Molnar } 849f62bae50SIngo Molnar 850f62bae50SIngo Molnar if (calibrate_APIC_clock()) { 851f62bae50SIngo Molnar /* No broadcast on UP ! */ 852f62bae50SIngo Molnar if (num_possible_cpus() > 1) 853f62bae50SIngo Molnar setup_APIC_timer(); 854f62bae50SIngo Molnar return; 855f62bae50SIngo Molnar } 856f62bae50SIngo Molnar 857f62bae50SIngo Molnar /* 858f62bae50SIngo Molnar * If nmi_watchdog is set to IO_APIC, we need the 859f62bae50SIngo Molnar * PIT/HPET going. Otherwise register lapic as a dummy 860f62bae50SIngo Molnar * device. 861f62bae50SIngo Molnar */ 862f62bae50SIngo Molnar lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 863f62bae50SIngo Molnar 864f62bae50SIngo Molnar /* Setup the lapic or request the broadcast */ 865f62bae50SIngo Molnar setup_APIC_timer(); 866f62bae50SIngo Molnar } 867f62bae50SIngo Molnar 868f62bae50SIngo Molnar void __cpuinit setup_secondary_APIC_clock(void) 869f62bae50SIngo Molnar { 870f62bae50SIngo Molnar setup_APIC_timer(); 871f62bae50SIngo Molnar } 872f62bae50SIngo Molnar 873f62bae50SIngo Molnar /* 874f62bae50SIngo Molnar * The guts of the apic timer interrupt 875f62bae50SIngo Molnar */ 876f62bae50SIngo Molnar static void local_apic_timer_interrupt(void) 877f62bae50SIngo Molnar { 878f62bae50SIngo Molnar int cpu = smp_processor_id(); 879f62bae50SIngo Molnar struct clock_event_device *evt = &per_cpu(lapic_events, cpu); 880f62bae50SIngo Molnar 881f62bae50SIngo Molnar /* 882f62bae50SIngo Molnar * Normally we should not be here till LAPIC has been initialized but 883f62bae50SIngo Molnar * in some cases like kdump, its possible that there is a pending LAPIC 884f62bae50SIngo Molnar * timer interrupt from previous kernel's context and is delivered in 885f62bae50SIngo Molnar * new kernel the moment interrupts are enabled. 886f62bae50SIngo Molnar * 887f62bae50SIngo Molnar * Interrupts are enabled early and LAPIC is setup much later, hence 888f62bae50SIngo Molnar * its possible that when we get here evt->event_handler is NULL. 889f62bae50SIngo Molnar * Check for event_handler being NULL and discard the interrupt as 890f62bae50SIngo Molnar * spurious. 891f62bae50SIngo Molnar */ 892f62bae50SIngo Molnar if (!evt->event_handler) { 893f62bae50SIngo Molnar pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); 894f62bae50SIngo Molnar /* Switch it off */ 895f62bae50SIngo Molnar lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); 896f62bae50SIngo Molnar return; 897f62bae50SIngo Molnar } 898f62bae50SIngo Molnar 899f62bae50SIngo Molnar /* 900f62bae50SIngo Molnar * the NMI deadlock-detector uses this. 901f62bae50SIngo Molnar */ 902f62bae50SIngo Molnar inc_irq_stat(apic_timer_irqs); 903f62bae50SIngo Molnar 904f62bae50SIngo Molnar evt->event_handler(evt); 905f62bae50SIngo Molnar } 906f62bae50SIngo Molnar 907f62bae50SIngo Molnar /* 908f62bae50SIngo Molnar * Local APIC timer interrupt. This is the most natural way for doing 909f62bae50SIngo Molnar * local interrupts, but local timer interrupts can be emulated by 910f62bae50SIngo Molnar * broadcast interrupts too. [in case the hw doesn't support APIC timers] 911f62bae50SIngo Molnar * 912f62bae50SIngo Molnar * [ if a single-CPU system runs an SMP kernel then we call the local 913f62bae50SIngo Molnar * interrupt as well. Thus we cannot inline the local irq ... ] 914f62bae50SIngo Molnar */ 915f62bae50SIngo Molnar void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 916f62bae50SIngo Molnar { 917f62bae50SIngo Molnar struct pt_regs *old_regs = set_irq_regs(regs); 918f62bae50SIngo Molnar 919f62bae50SIngo Molnar /* 920f62bae50SIngo Molnar * NOTE! We'd better ACK the irq immediately, 921f62bae50SIngo Molnar * because timer handling can be slow. 922f62bae50SIngo Molnar */ 923f62bae50SIngo Molnar ack_APIC_irq(); 924f62bae50SIngo Molnar /* 925f62bae50SIngo Molnar * update_process_times() expects us to have done irq_enter(). 926f62bae50SIngo Molnar * Besides, if we don't timer interrupts ignore the global 927f62bae50SIngo Molnar * interrupt lock, which is the WrongThing (tm) to do. 928f62bae50SIngo Molnar */ 929f62bae50SIngo Molnar irq_enter(); 93098ad1cc1SFrederic Weisbecker exit_idle(); 931f62bae50SIngo Molnar local_apic_timer_interrupt(); 932f62bae50SIngo Molnar irq_exit(); 933f62bae50SIngo Molnar 934f62bae50SIngo Molnar set_irq_regs(old_regs); 935f62bae50SIngo Molnar } 936f62bae50SIngo Molnar 937f62bae50SIngo Molnar int setup_profiling_timer(unsigned int multiplier) 938f62bae50SIngo Molnar { 939f62bae50SIngo Molnar return -EINVAL; 940f62bae50SIngo Molnar } 941f62bae50SIngo Molnar 942f62bae50SIngo Molnar /* 943f62bae50SIngo Molnar * Local APIC start and shutdown 944f62bae50SIngo Molnar */ 945f62bae50SIngo Molnar 946f62bae50SIngo Molnar /** 947f62bae50SIngo Molnar * clear_local_APIC - shutdown the local APIC 948f62bae50SIngo Molnar * 949f62bae50SIngo Molnar * This is called, when a CPU is disabled and before rebooting, so the state of 950f62bae50SIngo Molnar * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 951f62bae50SIngo Molnar * leftovers during boot. 952f62bae50SIngo Molnar */ 953f62bae50SIngo Molnar void clear_local_APIC(void) 954f62bae50SIngo Molnar { 955f62bae50SIngo Molnar int maxlvt; 956f62bae50SIngo Molnar u32 v; 957f62bae50SIngo Molnar 958f62bae50SIngo Molnar /* APIC hasn't been mapped yet */ 959fc1edaf9SSuresh Siddha if (!x2apic_mode && !apic_phys) 960f62bae50SIngo Molnar return; 961f62bae50SIngo Molnar 962f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 963f62bae50SIngo Molnar /* 964f62bae50SIngo Molnar * Masking an LVT entry can trigger a local APIC error 965f62bae50SIngo Molnar * if the vector is zero. Mask LVTERR first to prevent this. 966f62bae50SIngo Molnar */ 967f62bae50SIngo Molnar if (maxlvt >= 3) { 968f62bae50SIngo Molnar v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 969f62bae50SIngo Molnar apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 970f62bae50SIngo Molnar } 971f62bae50SIngo Molnar /* 972f62bae50SIngo Molnar * Careful: we have to set masks only first to deassert 973f62bae50SIngo Molnar * any level-triggered sources. 974f62bae50SIngo Molnar */ 975f62bae50SIngo Molnar v = apic_read(APIC_LVTT); 976f62bae50SIngo Molnar apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 977f62bae50SIngo Molnar v = apic_read(APIC_LVT0); 978f62bae50SIngo Molnar apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 979f62bae50SIngo Molnar v = apic_read(APIC_LVT1); 980f62bae50SIngo Molnar apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 981f62bae50SIngo Molnar if (maxlvt >= 4) { 982f62bae50SIngo Molnar v = apic_read(APIC_LVTPC); 983f62bae50SIngo Molnar apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 984f62bae50SIngo Molnar } 985f62bae50SIngo Molnar 986f62bae50SIngo Molnar /* lets not touch this if we didn't frob it */ 9874efc0670SAndi Kleen #ifdef CONFIG_X86_THERMAL_VECTOR 988f62bae50SIngo Molnar if (maxlvt >= 5) { 989f62bae50SIngo Molnar v = apic_read(APIC_LVTTHMR); 990f62bae50SIngo Molnar apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 991f62bae50SIngo Molnar } 992f62bae50SIngo Molnar #endif 993638bee71SH. Peter Anvin #ifdef CONFIG_X86_MCE_INTEL 994638bee71SH. Peter Anvin if (maxlvt >= 6) { 995638bee71SH. Peter Anvin v = apic_read(APIC_LVTCMCI); 996638bee71SH. Peter Anvin if (!(v & APIC_LVT_MASKED)) 997638bee71SH. Peter Anvin apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 998638bee71SH. Peter Anvin } 999638bee71SH. Peter Anvin #endif 1000638bee71SH. Peter Anvin 1001f62bae50SIngo Molnar /* 1002f62bae50SIngo Molnar * Clean APIC state for other OSs: 1003f62bae50SIngo Molnar */ 1004f62bae50SIngo Molnar apic_write(APIC_LVTT, APIC_LVT_MASKED); 1005f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_LVT_MASKED); 1006f62bae50SIngo Molnar apic_write(APIC_LVT1, APIC_LVT_MASKED); 1007f62bae50SIngo Molnar if (maxlvt >= 3) 1008f62bae50SIngo Molnar apic_write(APIC_LVTERR, APIC_LVT_MASKED); 1009f62bae50SIngo Molnar if (maxlvt >= 4) 1010f62bae50SIngo Molnar apic_write(APIC_LVTPC, APIC_LVT_MASKED); 1011f62bae50SIngo Molnar 1012f62bae50SIngo Molnar /* Integrated APIC (!82489DX) ? */ 1013f62bae50SIngo Molnar if (lapic_is_integrated()) { 1014f62bae50SIngo Molnar if (maxlvt > 3) 1015f62bae50SIngo Molnar /* Clear ESR due to Pentium errata 3AP and 11AP */ 1016f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1017f62bae50SIngo Molnar apic_read(APIC_ESR); 1018f62bae50SIngo Molnar } 1019f62bae50SIngo Molnar } 1020f62bae50SIngo Molnar 1021f62bae50SIngo Molnar /** 1022f62bae50SIngo Molnar * disable_local_APIC - clear and disable the local APIC 1023f62bae50SIngo Molnar */ 1024f62bae50SIngo Molnar void disable_local_APIC(void) 1025f62bae50SIngo Molnar { 1026f62bae50SIngo Molnar unsigned int value; 1027f62bae50SIngo Molnar 1028f62bae50SIngo Molnar /* APIC hasn't been mapped yet */ 1029fd19dce7SYinghai Lu if (!x2apic_mode && !apic_phys) 1030f62bae50SIngo Molnar return; 1031f62bae50SIngo Molnar 1032f62bae50SIngo Molnar clear_local_APIC(); 1033f62bae50SIngo Molnar 1034f62bae50SIngo Molnar /* 1035f62bae50SIngo Molnar * Disable APIC (implies clearing of registers 1036f62bae50SIngo Molnar * for 82489DX!). 1037f62bae50SIngo Molnar */ 1038f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 1039f62bae50SIngo Molnar value &= ~APIC_SPIV_APIC_ENABLED; 1040f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 1041f62bae50SIngo Molnar 1042f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1043f62bae50SIngo Molnar /* 1044f62bae50SIngo Molnar * When LAPIC was disabled by the BIOS and enabled by the kernel, 1045f62bae50SIngo Molnar * restore the disabled state. 1046f62bae50SIngo Molnar */ 1047f62bae50SIngo Molnar if (enabled_via_apicbase) { 1048f62bae50SIngo Molnar unsigned int l, h; 1049f62bae50SIngo Molnar 1050f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, l, h); 1051f62bae50SIngo Molnar l &= ~MSR_IA32_APICBASE_ENABLE; 1052f62bae50SIngo Molnar wrmsr(MSR_IA32_APICBASE, l, h); 1053f62bae50SIngo Molnar } 1054f62bae50SIngo Molnar #endif 1055f62bae50SIngo Molnar } 1056f62bae50SIngo Molnar 1057f62bae50SIngo Molnar /* 1058f62bae50SIngo Molnar * If Linux enabled the LAPIC against the BIOS default disable it down before 1059f62bae50SIngo Molnar * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 1060f62bae50SIngo Molnar * not power-off. Additionally clear all LVT entries before disable_local_APIC 1061f62bae50SIngo Molnar * for the case where Linux didn't enable the LAPIC. 1062f62bae50SIngo Molnar */ 1063f62bae50SIngo Molnar void lapic_shutdown(void) 1064f62bae50SIngo Molnar { 1065f62bae50SIngo Molnar unsigned long flags; 1066f62bae50SIngo Molnar 10678312136fSCyrill Gorcunov if (!cpu_has_apic && !apic_from_smp_config()) 1068f62bae50SIngo Molnar return; 1069f62bae50SIngo Molnar 1070f62bae50SIngo Molnar local_irq_save(flags); 1071f62bae50SIngo Molnar 1072f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1073f62bae50SIngo Molnar if (!enabled_via_apicbase) 1074f62bae50SIngo Molnar clear_local_APIC(); 1075f62bae50SIngo Molnar else 1076f62bae50SIngo Molnar #endif 1077f62bae50SIngo Molnar disable_local_APIC(); 1078f62bae50SIngo Molnar 1079f62bae50SIngo Molnar 1080f62bae50SIngo Molnar local_irq_restore(flags); 1081f62bae50SIngo Molnar } 1082f62bae50SIngo Molnar 1083f62bae50SIngo Molnar /* 1084f62bae50SIngo Molnar * This is to verify that we're looking at a real local APIC. 1085f62bae50SIngo Molnar * Check these against your board if the CPUs aren't getting 1086f62bae50SIngo Molnar * started for no apparent reason. 1087f62bae50SIngo Molnar */ 1088f62bae50SIngo Molnar int __init verify_local_APIC(void) 1089f62bae50SIngo Molnar { 1090f62bae50SIngo Molnar unsigned int reg0, reg1; 1091f62bae50SIngo Molnar 1092f62bae50SIngo Molnar /* 1093f62bae50SIngo Molnar * The version register is read-only in a real APIC. 1094f62bae50SIngo Molnar */ 1095f62bae50SIngo Molnar reg0 = apic_read(APIC_LVR); 1096f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); 1097f62bae50SIngo Molnar apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); 1098f62bae50SIngo Molnar reg1 = apic_read(APIC_LVR); 1099f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); 1100f62bae50SIngo Molnar 1101f62bae50SIngo Molnar /* 1102f62bae50SIngo Molnar * The two version reads above should print the same 1103f62bae50SIngo Molnar * numbers. If the second one is different, then we 1104f62bae50SIngo Molnar * poke at a non-APIC. 1105f62bae50SIngo Molnar */ 1106f62bae50SIngo Molnar if (reg1 != reg0) 1107f62bae50SIngo Molnar return 0; 1108f62bae50SIngo Molnar 1109f62bae50SIngo Molnar /* 1110f62bae50SIngo Molnar * Check if the version looks reasonably. 1111f62bae50SIngo Molnar */ 1112f62bae50SIngo Molnar reg1 = GET_APIC_VERSION(reg0); 1113f62bae50SIngo Molnar if (reg1 == 0x00 || reg1 == 0xff) 1114f62bae50SIngo Molnar return 0; 1115f62bae50SIngo Molnar reg1 = lapic_get_maxlvt(); 1116f62bae50SIngo Molnar if (reg1 < 0x02 || reg1 == 0xff) 1117f62bae50SIngo Molnar return 0; 1118f62bae50SIngo Molnar 1119f62bae50SIngo Molnar /* 1120f62bae50SIngo Molnar * The ID register is read/write in a real APIC. 1121f62bae50SIngo Molnar */ 1122f62bae50SIngo Molnar reg0 = apic_read(APIC_ID); 1123f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); 1124f62bae50SIngo Molnar apic_write(APIC_ID, reg0 ^ apic->apic_id_mask); 1125f62bae50SIngo Molnar reg1 = apic_read(APIC_ID); 1126f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); 1127f62bae50SIngo Molnar apic_write(APIC_ID, reg0); 1128f62bae50SIngo Molnar if (reg1 != (reg0 ^ apic->apic_id_mask)) 1129f62bae50SIngo Molnar return 0; 1130f62bae50SIngo Molnar 1131f62bae50SIngo Molnar /* 1132f62bae50SIngo Molnar * The next two are just to see if we have sane values. 1133f62bae50SIngo Molnar * They're only really relevant if we're in Virtual Wire 1134f62bae50SIngo Molnar * compatibility mode, but most boxes are anymore. 1135f62bae50SIngo Molnar */ 1136f62bae50SIngo Molnar reg0 = apic_read(APIC_LVT0); 1137f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); 1138f62bae50SIngo Molnar reg1 = apic_read(APIC_LVT1); 1139f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); 1140f62bae50SIngo Molnar 1141f62bae50SIngo Molnar return 1; 1142f62bae50SIngo Molnar } 1143f62bae50SIngo Molnar 1144f62bae50SIngo Molnar /** 1145f62bae50SIngo Molnar * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1146f62bae50SIngo Molnar */ 1147f62bae50SIngo Molnar void __init sync_Arb_IDs(void) 1148f62bae50SIngo Molnar { 1149f62bae50SIngo Molnar /* 1150f62bae50SIngo Molnar * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1151f62bae50SIngo Molnar * needed on AMD. 1152f62bae50SIngo Molnar */ 1153f62bae50SIngo Molnar if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1154f62bae50SIngo Molnar return; 1155f62bae50SIngo Molnar 1156f62bae50SIngo Molnar /* 1157f62bae50SIngo Molnar * Wait for idle. 1158f62bae50SIngo Molnar */ 1159f62bae50SIngo Molnar apic_wait_icr_idle(); 1160f62bae50SIngo Molnar 1161f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1162f62bae50SIngo Molnar apic_write(APIC_ICR, APIC_DEST_ALLINC | 1163f62bae50SIngo Molnar APIC_INT_LEVELTRIG | APIC_DM_INIT); 1164f62bae50SIngo Molnar } 1165f62bae50SIngo Molnar 1166f62bae50SIngo Molnar /* 1167f62bae50SIngo Molnar * An initial setup of the virtual wire mode. 1168f62bae50SIngo Molnar */ 1169f62bae50SIngo Molnar void __init init_bsp_APIC(void) 1170f62bae50SIngo Molnar { 1171f62bae50SIngo Molnar unsigned int value; 1172f62bae50SIngo Molnar 1173f62bae50SIngo Molnar /* 1174f62bae50SIngo Molnar * Don't do the setup now if we have a SMP BIOS as the 1175f62bae50SIngo Molnar * through-I/O-APIC virtual wire mode might be active. 1176f62bae50SIngo Molnar */ 1177f62bae50SIngo Molnar if (smp_found_config || !cpu_has_apic) 1178f62bae50SIngo Molnar return; 1179f62bae50SIngo Molnar 1180f62bae50SIngo Molnar /* 1181f62bae50SIngo Molnar * Do not trust the local APIC being empty at bootup. 1182f62bae50SIngo Molnar */ 1183f62bae50SIngo Molnar clear_local_APIC(); 1184f62bae50SIngo Molnar 1185f62bae50SIngo Molnar /* 1186f62bae50SIngo Molnar * Enable APIC. 1187f62bae50SIngo Molnar */ 1188f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 1189f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 1190f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 1191f62bae50SIngo Molnar 1192f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1193f62bae50SIngo Molnar /* This bit is reserved on P4/Xeon and should be cleared */ 1194f62bae50SIngo Molnar if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1195f62bae50SIngo Molnar (boot_cpu_data.x86 == 15)) 1196f62bae50SIngo Molnar value &= ~APIC_SPIV_FOCUS_DISABLED; 1197f62bae50SIngo Molnar else 1198f62bae50SIngo Molnar #endif 1199f62bae50SIngo Molnar value |= APIC_SPIV_FOCUS_DISABLED; 1200f62bae50SIngo Molnar value |= SPURIOUS_APIC_VECTOR; 1201f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 1202f62bae50SIngo Molnar 1203f62bae50SIngo Molnar /* 1204f62bae50SIngo Molnar * Set up the virtual wire mode. 1205f62bae50SIngo Molnar */ 1206f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_DM_EXTINT); 1207f62bae50SIngo Molnar value = APIC_DM_NMI; 1208f62bae50SIngo Molnar if (!lapic_is_integrated()) /* 82489DX */ 1209f62bae50SIngo Molnar value |= APIC_LVT_LEVEL_TRIGGER; 1210f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 1211f62bae50SIngo Molnar } 1212f62bae50SIngo Molnar 1213f62bae50SIngo Molnar static void __cpuinit lapic_setup_esr(void) 1214f62bae50SIngo Molnar { 1215f62bae50SIngo Molnar unsigned int oldvalue, value, maxlvt; 1216f62bae50SIngo Molnar 1217f62bae50SIngo Molnar if (!lapic_is_integrated()) { 1218f62bae50SIngo Molnar pr_info("No ESR for 82489DX.\n"); 1219f62bae50SIngo Molnar return; 1220f62bae50SIngo Molnar } 1221f62bae50SIngo Molnar 1222f62bae50SIngo Molnar if (apic->disable_esr) { 1223f62bae50SIngo Molnar /* 1224f62bae50SIngo Molnar * Something untraceable is creating bad interrupts on 1225f62bae50SIngo Molnar * secondary quads ... for the moment, just leave the 1226f62bae50SIngo Molnar * ESR disabled - we can't do anything useful with the 1227f62bae50SIngo Molnar * errors anyway - mbligh 1228f62bae50SIngo Molnar */ 1229f62bae50SIngo Molnar pr_info("Leaving ESR disabled.\n"); 1230f62bae50SIngo Molnar return; 1231f62bae50SIngo Molnar } 1232f62bae50SIngo Molnar 1233f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 1234f62bae50SIngo Molnar if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1235f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1236f62bae50SIngo Molnar oldvalue = apic_read(APIC_ESR); 1237f62bae50SIngo Molnar 1238f62bae50SIngo Molnar /* enables sending errors */ 1239f62bae50SIngo Molnar value = ERROR_APIC_VECTOR; 1240f62bae50SIngo Molnar apic_write(APIC_LVTERR, value); 1241f62bae50SIngo Molnar 1242f62bae50SIngo Molnar /* 1243f62bae50SIngo Molnar * spec says clear errors after enabling vector. 1244f62bae50SIngo Molnar */ 1245f62bae50SIngo Molnar if (maxlvt > 3) 1246f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1247f62bae50SIngo Molnar value = apic_read(APIC_ESR); 1248f62bae50SIngo Molnar if (value != oldvalue) 1249f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "ESR value before enabling " 1250f62bae50SIngo Molnar "vector: 0x%08x after: 0x%08x\n", 1251f62bae50SIngo Molnar oldvalue, value); 1252f62bae50SIngo Molnar } 1253f62bae50SIngo Molnar 1254f62bae50SIngo Molnar /** 1255f62bae50SIngo Molnar * setup_local_APIC - setup the local APIC 12560aa002feSTejun Heo * 12570aa002feSTejun Heo * Used to setup local APIC while initializing BSP or bringin up APs. 12580aa002feSTejun Heo * Always called with preemption disabled. 1259f62bae50SIngo Molnar */ 1260f62bae50SIngo Molnar void __cpuinit setup_local_APIC(void) 1261f62bae50SIngo Molnar { 12620aa002feSTejun Heo int cpu = smp_processor_id(); 12638c3ba8d0SKerstin Jonsson unsigned int value, queued; 12648c3ba8d0SKerstin Jonsson int i, j, acked = 0; 12658c3ba8d0SKerstin Jonsson unsigned long long tsc = 0, ntsc; 12668c3ba8d0SKerstin Jonsson long long max_loops = cpu_khz; 12678c3ba8d0SKerstin Jonsson 12688c3ba8d0SKerstin Jonsson if (cpu_has_tsc) 12698c3ba8d0SKerstin Jonsson rdtscll(tsc); 1270f62bae50SIngo Molnar 1271f62bae50SIngo Molnar if (disable_apic) { 12727167d08eSHenrik Kretzschmar disable_ioapic_support(); 1273f62bae50SIngo Molnar return; 1274f62bae50SIngo Molnar } 1275f62bae50SIngo Molnar 1276f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1277f62bae50SIngo Molnar /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1278f62bae50SIngo Molnar if (lapic_is_integrated() && apic->disable_esr) { 1279f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1280f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1281f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1282f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1283f62bae50SIngo Molnar } 1284f62bae50SIngo Molnar #endif 1285cdd6c482SIngo Molnar perf_events_lapic_init(); 1286f62bae50SIngo Molnar 1287f62bae50SIngo Molnar /* 1288f62bae50SIngo Molnar * Double-check whether this APIC is really registered. 1289f62bae50SIngo Molnar * This is meaningless in clustered apic mode, so we skip it. 1290f62bae50SIngo Molnar */ 1291c2777f98SDaniel Walker BUG_ON(!apic->apic_id_registered()); 1292f62bae50SIngo Molnar 1293f62bae50SIngo Molnar /* 1294f62bae50SIngo Molnar * Intel recommends to set DFR, LDR and TPR before enabling 1295f62bae50SIngo Molnar * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1296f62bae50SIngo Molnar * document number 292116). So here it goes... 1297f62bae50SIngo Molnar */ 1298f62bae50SIngo Molnar apic->init_apic_ldr(); 1299f62bae50SIngo Molnar 13006f802c4bSTejun Heo #ifdef CONFIG_X86_32 13016f802c4bSTejun Heo /* 1302acb8bc09STejun Heo * APIC LDR is initialized. If logical_apicid mapping was 1303acb8bc09STejun Heo * initialized during get_smp_config(), make sure it matches the 1304acb8bc09STejun Heo * actual value. 13056f802c4bSTejun Heo */ 1306acb8bc09STejun Heo i = early_per_cpu(x86_cpu_to_logical_apicid, cpu); 1307acb8bc09STejun Heo WARN_ON(i != BAD_APICID && i != logical_smp_processor_id()); 1308acb8bc09STejun Heo /* always use the value from LDR */ 13096f802c4bSTejun Heo early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 13106f802c4bSTejun Heo logical_smp_processor_id(); 1311c4b90c11STejun Heo 1312c4b90c11STejun Heo /* 1313c4b90c11STejun Heo * Some NUMA implementations (NUMAQ) don't initialize apicid to 1314c4b90c11STejun Heo * node mapping during NUMA init. Now that logical apicid is 1315c4b90c11STejun Heo * guaranteed to be known, give it another chance. This is already 1316c4b90c11STejun Heo * a bit too late - percpu allocation has already happened without 1317c4b90c11STejun Heo * proper NUMA affinity. 1318c4b90c11STejun Heo */ 131984914ed0STejun Heo if (apic->x86_32_numa_cpu_node) 1320c4b90c11STejun Heo set_apicid_to_node(early_per_cpu(x86_cpu_to_apicid, cpu), 1321c4b90c11STejun Heo apic->x86_32_numa_cpu_node(cpu)); 13226f802c4bSTejun Heo #endif 13236f802c4bSTejun Heo 1324f62bae50SIngo Molnar /* 1325f62bae50SIngo Molnar * Set Task Priority to 'accept all'. We never change this 1326f62bae50SIngo Molnar * later on. 1327f62bae50SIngo Molnar */ 1328f62bae50SIngo Molnar value = apic_read(APIC_TASKPRI); 1329f62bae50SIngo Molnar value &= ~APIC_TPRI_MASK; 1330f62bae50SIngo Molnar apic_write(APIC_TASKPRI, value); 1331f62bae50SIngo Molnar 1332f62bae50SIngo Molnar /* 1333f62bae50SIngo Molnar * After a crash, we no longer service the interrupts and a pending 1334f62bae50SIngo Molnar * interrupt from previous kernel might still have ISR bit set. 1335f62bae50SIngo Molnar * 1336f62bae50SIngo Molnar * Most probably by now CPU has serviced that pending interrupt and 1337f62bae50SIngo Molnar * it might not have done the ack_APIC_irq() because it thought, 1338f62bae50SIngo Molnar * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1339f62bae50SIngo Molnar * does not clear the ISR bit and cpu thinks it has already serivced 1340f62bae50SIngo Molnar * the interrupt. Hence a vector might get locked. It was noticed 1341f62bae50SIngo Molnar * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1342f62bae50SIngo Molnar */ 13438c3ba8d0SKerstin Jonsson do { 13448c3ba8d0SKerstin Jonsson queued = 0; 13458c3ba8d0SKerstin Jonsson for (i = APIC_ISR_NR - 1; i >= 0; i--) 13468c3ba8d0SKerstin Jonsson queued |= apic_read(APIC_IRR + i*0x10); 13478c3ba8d0SKerstin Jonsson 1348f62bae50SIngo Molnar for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1349f62bae50SIngo Molnar value = apic_read(APIC_ISR + i*0x10); 1350f62bae50SIngo Molnar for (j = 31; j >= 0; j--) { 13518c3ba8d0SKerstin Jonsson if (value & (1<<j)) { 1352f62bae50SIngo Molnar ack_APIC_irq(); 13538c3ba8d0SKerstin Jonsson acked++; 1354f62bae50SIngo Molnar } 1355f62bae50SIngo Molnar } 13568c3ba8d0SKerstin Jonsson } 13578c3ba8d0SKerstin Jonsson if (acked > 256) { 13588c3ba8d0SKerstin Jonsson printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", 13598c3ba8d0SKerstin Jonsson acked); 13608c3ba8d0SKerstin Jonsson break; 13618c3ba8d0SKerstin Jonsson } 136242fa4250SShai Fultheim if (queued) { 13638c3ba8d0SKerstin Jonsson if (cpu_has_tsc) { 13648c3ba8d0SKerstin Jonsson rdtscll(ntsc); 13658c3ba8d0SKerstin Jonsson max_loops = (cpu_khz << 10) - (ntsc - tsc); 13668c3ba8d0SKerstin Jonsson } else 13678c3ba8d0SKerstin Jonsson max_loops--; 136842fa4250SShai Fultheim } 13698c3ba8d0SKerstin Jonsson } while (queued && max_loops > 0); 13708c3ba8d0SKerstin Jonsson WARN_ON(max_loops <= 0); 1371f62bae50SIngo Molnar 1372f62bae50SIngo Molnar /* 1373f62bae50SIngo Molnar * Now that we are all set up, enable the APIC 1374f62bae50SIngo Molnar */ 1375f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 1376f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 1377f62bae50SIngo Molnar /* 1378f62bae50SIngo Molnar * Enable APIC 1379f62bae50SIngo Molnar */ 1380f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 1381f62bae50SIngo Molnar 1382f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1383f62bae50SIngo Molnar /* 1384f62bae50SIngo Molnar * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1385f62bae50SIngo Molnar * certain networking cards. If high frequency interrupts are 1386f62bae50SIngo Molnar * happening on a particular IOAPIC pin, plus the IOAPIC routing 1387f62bae50SIngo Molnar * entry is masked/unmasked at a high rate as well then sooner or 1388f62bae50SIngo Molnar * later IOAPIC line gets 'stuck', no more interrupts are received 1389f62bae50SIngo Molnar * from the device. If focus CPU is disabled then the hang goes 1390f62bae50SIngo Molnar * away, oh well :-( 1391f62bae50SIngo Molnar * 1392f62bae50SIngo Molnar * [ This bug can be reproduced easily with a level-triggered 1393f62bae50SIngo Molnar * PCI Ne2000 networking cards and PII/PIII processors, dual 1394f62bae50SIngo Molnar * BX chipset. ] 1395f62bae50SIngo Molnar */ 1396f62bae50SIngo Molnar /* 1397f62bae50SIngo Molnar * Actually disabling the focus CPU check just makes the hang less 1398f62bae50SIngo Molnar * frequent as it makes the interrupt distributon model be more 1399f62bae50SIngo Molnar * like LRU than MRU (the short-term load is more even across CPUs). 1400f62bae50SIngo Molnar * See also the comment in end_level_ioapic_irq(). --macro 1401f62bae50SIngo Molnar */ 1402f62bae50SIngo Molnar 1403f62bae50SIngo Molnar /* 1404f62bae50SIngo Molnar * - enable focus processor (bit==0) 1405f62bae50SIngo Molnar * - 64bit mode always use processor focus 1406f62bae50SIngo Molnar * so no need to set it 1407f62bae50SIngo Molnar */ 1408f62bae50SIngo Molnar value &= ~APIC_SPIV_FOCUS_DISABLED; 1409f62bae50SIngo Molnar #endif 1410f62bae50SIngo Molnar 1411f62bae50SIngo Molnar /* 1412f62bae50SIngo Molnar * Set spurious IRQ vector 1413f62bae50SIngo Molnar */ 1414f62bae50SIngo Molnar value |= SPURIOUS_APIC_VECTOR; 1415f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 1416f62bae50SIngo Molnar 1417f62bae50SIngo Molnar /* 1418f62bae50SIngo Molnar * Set up LVT0, LVT1: 1419f62bae50SIngo Molnar * 1420f62bae50SIngo Molnar * set up through-local-APIC on the BP's LINT0. This is not 1421f62bae50SIngo Molnar * strictly necessary in pure symmetric-IO mode, but sometimes 1422f62bae50SIngo Molnar * we delegate interrupts to the 8259A. 1423f62bae50SIngo Molnar */ 1424f62bae50SIngo Molnar /* 1425f62bae50SIngo Molnar * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1426f62bae50SIngo Molnar */ 1427f62bae50SIngo Molnar value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 14280aa002feSTejun Heo if (!cpu && (pic_mode || !value)) { 1429f62bae50SIngo Molnar value = APIC_DM_EXTINT; 14300aa002feSTejun Heo apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1431f62bae50SIngo Molnar } else { 1432f62bae50SIngo Molnar value = APIC_DM_EXTINT | APIC_LVT_MASKED; 14330aa002feSTejun Heo apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1434f62bae50SIngo Molnar } 1435f62bae50SIngo Molnar apic_write(APIC_LVT0, value); 1436f62bae50SIngo Molnar 1437f62bae50SIngo Molnar /* 1438f62bae50SIngo Molnar * only the BP should see the LINT1 NMI signal, obviously. 1439f62bae50SIngo Molnar */ 14400aa002feSTejun Heo if (!cpu) 1441f62bae50SIngo Molnar value = APIC_DM_NMI; 1442f62bae50SIngo Molnar else 1443f62bae50SIngo Molnar value = APIC_DM_NMI | APIC_LVT_MASKED; 1444f62bae50SIngo Molnar if (!lapic_is_integrated()) /* 82489DX */ 1445f62bae50SIngo Molnar value |= APIC_LVT_LEVEL_TRIGGER; 1446f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 1447f62bae50SIngo Molnar 1448638bee71SH. Peter Anvin #ifdef CONFIG_X86_MCE_INTEL 1449638bee71SH. Peter Anvin /* Recheck CMCI information after local APIC is up on CPU #0 */ 14500aa002feSTejun Heo if (!cpu) 1451638bee71SH. Peter Anvin cmci_recheck(); 1452638bee71SH. Peter Anvin #endif 1453f62bae50SIngo Molnar } 1454f62bae50SIngo Molnar 1455f62bae50SIngo Molnar void __cpuinit end_local_APIC_setup(void) 1456f62bae50SIngo Molnar { 1457f62bae50SIngo Molnar lapic_setup_esr(); 1458f62bae50SIngo Molnar 1459f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1460f62bae50SIngo Molnar { 1461f62bae50SIngo Molnar unsigned int value; 1462f62bae50SIngo Molnar /* Disable the local apic timer */ 1463f62bae50SIngo Molnar value = apic_read(APIC_LVTT); 1464f62bae50SIngo Molnar value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1465f62bae50SIngo Molnar apic_write(APIC_LVTT, value); 1466f62bae50SIngo Molnar } 1467f62bae50SIngo Molnar #endif 1468f62bae50SIngo Molnar 1469f62bae50SIngo Molnar apic_pm_activate(); 14702fb270f3SJan Beulich } 14712fb270f3SJan Beulich 14722fb270f3SJan Beulich void __init bsp_end_local_APIC_setup(void) 14732fb270f3SJan Beulich { 14742fb270f3SJan Beulich end_local_APIC_setup(); 14757f7fbf45SKenji Kaneshige 14767f7fbf45SKenji Kaneshige /* 14777f7fbf45SKenji Kaneshige * Now that local APIC setup is completed for BP, configure the fault 14787f7fbf45SKenji Kaneshige * handling for interrupt remapping. 14797f7fbf45SKenji Kaneshige */ 148095a02e97SSuresh Siddha if (irq_remapping_enabled) 148195a02e97SSuresh Siddha irq_remap_enable_fault_handling(); 14827f7fbf45SKenji Kaneshige 1483f62bae50SIngo Molnar } 1484f62bae50SIngo Molnar 1485f62bae50SIngo Molnar #ifdef CONFIG_X86_X2APIC 1486fb209bd8SYinghai Lu /* 1487fb209bd8SYinghai Lu * Need to disable xapic and x2apic at the same time and then enable xapic mode 1488fb209bd8SYinghai Lu */ 1489fb209bd8SYinghai Lu static inline void __disable_x2apic(u64 msr) 1490fb209bd8SYinghai Lu { 1491fb209bd8SYinghai Lu wrmsrl(MSR_IA32_APICBASE, 1492fb209bd8SYinghai Lu msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); 1493fb209bd8SYinghai Lu wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); 1494fb209bd8SYinghai Lu } 1495fb209bd8SYinghai Lu 1496a31bc327SYinghai Lu static __init void disable_x2apic(void) 1497fb209bd8SYinghai Lu { 1498fb209bd8SYinghai Lu u64 msr; 1499fb209bd8SYinghai Lu 1500fb209bd8SYinghai Lu if (!cpu_has_x2apic) 1501fb209bd8SYinghai Lu return; 1502fb209bd8SYinghai Lu 1503fb209bd8SYinghai Lu rdmsrl(MSR_IA32_APICBASE, msr); 1504fb209bd8SYinghai Lu if (msr & X2APIC_ENABLE) { 1505fb209bd8SYinghai Lu u32 x2apic_id = read_apic_id(); 1506fb209bd8SYinghai Lu 1507fb209bd8SYinghai Lu if (x2apic_id >= 255) 1508fb209bd8SYinghai Lu panic("Cannot disable x2apic, id: %08x\n", x2apic_id); 1509fb209bd8SYinghai Lu 1510fb209bd8SYinghai Lu pr_info("Disabling x2apic\n"); 1511fb209bd8SYinghai Lu __disable_x2apic(msr); 1512fb209bd8SYinghai Lu 1513a31bc327SYinghai Lu if (nox2apic) { 1514a31bc327SYinghai Lu clear_cpu_cap(&cpu_data(0), X86_FEATURE_X2APIC); 1515a31bc327SYinghai Lu setup_clear_cpu_cap(X86_FEATURE_X2APIC); 1516a31bc327SYinghai Lu } 1517a31bc327SYinghai Lu 1518fb209bd8SYinghai Lu x2apic_disabled = 1; 1519fb209bd8SYinghai Lu x2apic_mode = 0; 1520fb209bd8SYinghai Lu 1521fb209bd8SYinghai Lu register_lapic_address(mp_lapic_addr); 1522fb209bd8SYinghai Lu } 1523fb209bd8SYinghai Lu } 1524fb209bd8SYinghai Lu 1525f62bae50SIngo Molnar void check_x2apic(void) 1526f62bae50SIngo Molnar { 1527ef1f87aaSSuresh Siddha if (x2apic_enabled()) { 1528f62bae50SIngo Molnar pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); 1529fc1edaf9SSuresh Siddha x2apic_preenabled = x2apic_mode = 1; 1530f62bae50SIngo Molnar } 1531f62bae50SIngo Molnar } 1532f62bae50SIngo Molnar 1533f62bae50SIngo Molnar void enable_x2apic(void) 1534f62bae50SIngo Molnar { 1535fb209bd8SYinghai Lu u64 msr; 1536fb209bd8SYinghai Lu 1537fb209bd8SYinghai Lu rdmsrl(MSR_IA32_APICBASE, msr); 1538fb209bd8SYinghai Lu if (x2apic_disabled) { 1539fb209bd8SYinghai Lu __disable_x2apic(msr); 1540fb209bd8SYinghai Lu return; 1541fb209bd8SYinghai Lu } 1542f62bae50SIngo Molnar 1543fc1edaf9SSuresh Siddha if (!x2apic_mode) 1544f62bae50SIngo Molnar return; 1545f62bae50SIngo Molnar 1546f62bae50SIngo Molnar if (!(msr & X2APIC_ENABLE)) { 1547450b1e8dSMike Travis printk_once(KERN_INFO "Enabling x2apic\n"); 1548fb209bd8SYinghai Lu wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); 1549f62bae50SIngo Molnar } 1550f62bae50SIngo Molnar } 155193758238SWeidong Han #endif /* CONFIG_X86_X2APIC */ 1552f62bae50SIngo Molnar 1553ce69a784SGleb Natapov int __init enable_IR(void) 1554f62bae50SIngo Molnar { 1555d3f13810SSuresh Siddha #ifdef CONFIG_IRQ_REMAP 155695a02e97SSuresh Siddha if (!irq_remapping_supported()) { 155793758238SWeidong Han pr_debug("intr-remapping not supported\n"); 155841750d31SSuresh Siddha return -1; 155993758238SWeidong Han } 156093758238SWeidong Han 156193758238SWeidong Han if (!x2apic_preenabled && skip_ioapic_setup) { 156293758238SWeidong Han pr_info("Skipped enabling intr-remap because of skipping " 156393758238SWeidong Han "io-apic setup\n"); 156441750d31SSuresh Siddha return -1; 1565f62bae50SIngo Molnar } 1566f62bae50SIngo Molnar 156795a02e97SSuresh Siddha return irq_remapping_enable(); 1568ce69a784SGleb Natapov #endif 156941750d31SSuresh Siddha return -1; 1570ce69a784SGleb Natapov } 1571ce69a784SGleb Natapov 1572ce69a784SGleb Natapov void __init enable_IR_x2apic(void) 1573ce69a784SGleb Natapov { 1574ce69a784SGleb Natapov unsigned long flags; 1575ce69a784SGleb Natapov int ret, x2apic_enabled = 0; 1576736baef4SJoerg Roedel int hardware_init_ret; 1577b7f42ab2SYinghai Lu 1578736baef4SJoerg Roedel /* Make sure irq_remap_ops are initialized */ 157995a02e97SSuresh Siddha setup_irq_remapping_ops(); 1580736baef4SJoerg Roedel 158195a02e97SSuresh Siddha hardware_init_ret = irq_remapping_prepare(); 1582736baef4SJoerg Roedel if (hardware_init_ret && !x2apic_supported()) 1583e670761fSYinghai Lu return; 1584ce69a784SGleb Natapov 158531dce14aSSuresh Siddha ret = save_ioapic_entries(); 1586f62bae50SIngo Molnar if (ret) { 1587f62bae50SIngo Molnar pr_info("Saving IO-APIC state failed: %d\n", ret); 1588fb209bd8SYinghai Lu return; 1589f62bae50SIngo Molnar } 1590f62bae50SIngo Molnar 159105c3dc2cSSuresh Siddha local_irq_save(flags); 1592b81bb373SJacob Pan legacy_pic->mask_all(); 159331dce14aSSuresh Siddha mask_ioapic_entries(); 159405c3dc2cSSuresh Siddha 1595a31bc327SYinghai Lu if (x2apic_preenabled && nox2apic) 1596a31bc327SYinghai Lu disable_x2apic(); 1597a31bc327SYinghai Lu 1598736baef4SJoerg Roedel if (hardware_init_ret) 159941750d31SSuresh Siddha ret = -1; 1600b7f42ab2SYinghai Lu else 1601ce69a784SGleb Natapov ret = enable_IR(); 1602b7f42ab2SYinghai Lu 1603fb209bd8SYinghai Lu if (!x2apic_supported()) 1604a31bc327SYinghai Lu goto skip_x2apic; 1605fb209bd8SYinghai Lu 160641750d31SSuresh Siddha if (ret < 0) { 1607ce69a784SGleb Natapov /* IR is required if there is APIC ID > 255 even when running 1608ce69a784SGleb Natapov * under KVM 1609ce69a784SGleb Natapov */ 16102904ed8dSSheng Yang if (max_physical_apicid > 255 || 1611fb209bd8SYinghai Lu !hypervisor_x2apic_available()) { 1612fb209bd8SYinghai Lu if (x2apic_preenabled) 1613fb209bd8SYinghai Lu disable_x2apic(); 1614a31bc327SYinghai Lu goto skip_x2apic; 1615fb209bd8SYinghai Lu } 1616ce69a784SGleb Natapov /* 1617ce69a784SGleb Natapov * without IR all CPUs can be addressed by IOAPIC/MSI 1618ce69a784SGleb Natapov * only in physical mode 1619ce69a784SGleb Natapov */ 1620ce69a784SGleb Natapov x2apic_force_phys(); 1621ce69a784SGleb Natapov } 1622f62bae50SIngo Molnar 1623fb209bd8SYinghai Lu if (ret == IRQ_REMAP_XAPIC_MODE) { 1624fb209bd8SYinghai Lu pr_info("x2apic not enabled, IRQ remapping is in xapic mode\n"); 1625a31bc327SYinghai Lu goto skip_x2apic; 1626fb209bd8SYinghai Lu } 162741750d31SSuresh Siddha 1628ce69a784SGleb Natapov x2apic_enabled = 1; 162993758238SWeidong Han 1630fc1edaf9SSuresh Siddha if (x2apic_supported() && !x2apic_mode) { 1631fc1edaf9SSuresh Siddha x2apic_mode = 1; 1632f62bae50SIngo Molnar enable_x2apic(); 163393758238SWeidong Han pr_info("Enabled x2apic\n"); 1634f62bae50SIngo Molnar } 1635f62bae50SIngo Molnar 1636a31bc327SYinghai Lu skip_x2apic: 163741750d31SSuresh Siddha if (ret < 0) /* IR enabling failed */ 163831dce14aSSuresh Siddha restore_ioapic_entries(); 1639b81bb373SJacob Pan legacy_pic->restore_mask(); 1640f62bae50SIngo Molnar local_irq_restore(flags); 1641f62bae50SIngo Molnar } 164293758238SWeidong Han 1643f62bae50SIngo Molnar #ifdef CONFIG_X86_64 1644f62bae50SIngo Molnar /* 1645f62bae50SIngo Molnar * Detect and enable local APICs on non-SMP boards. 1646f62bae50SIngo Molnar * Original code written by Keir Fraser. 1647f62bae50SIngo Molnar * On AMD64 we trust the BIOS - if it says no APIC it is likely 1648f62bae50SIngo Molnar * not correctly set up (usually the APIC timer won't work etc.) 1649f62bae50SIngo Molnar */ 1650f62bae50SIngo Molnar static int __init detect_init_APIC(void) 1651f62bae50SIngo Molnar { 1652f62bae50SIngo Molnar if (!cpu_has_apic) { 1653f62bae50SIngo Molnar pr_info("No local APIC present\n"); 1654f62bae50SIngo Molnar return -1; 1655f62bae50SIngo Molnar } 1656f62bae50SIngo Molnar 1657f62bae50SIngo Molnar mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1658f62bae50SIngo Molnar return 0; 1659f62bae50SIngo Molnar } 1660f62bae50SIngo Molnar #else 16615a7ae78fSThomas Gleixner 166225874a29SHenrik Kretzschmar static int __init apic_verify(void) 16635a7ae78fSThomas Gleixner { 16645a7ae78fSThomas Gleixner u32 features, h, l; 16655a7ae78fSThomas Gleixner 16665a7ae78fSThomas Gleixner /* 16675a7ae78fSThomas Gleixner * The APIC feature bit should now be enabled 16685a7ae78fSThomas Gleixner * in `cpuid' 16695a7ae78fSThomas Gleixner */ 16705a7ae78fSThomas Gleixner features = cpuid_edx(1); 16715a7ae78fSThomas Gleixner if (!(features & (1 << X86_FEATURE_APIC))) { 16725a7ae78fSThomas Gleixner pr_warning("Could not enable APIC!\n"); 16735a7ae78fSThomas Gleixner return -1; 16745a7ae78fSThomas Gleixner } 16755a7ae78fSThomas Gleixner set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 16765a7ae78fSThomas Gleixner mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 16775a7ae78fSThomas Gleixner 16785a7ae78fSThomas Gleixner /* The BIOS may have set up the APIC at some other address */ 1679cbf2829bSBryan O'Donoghue if (boot_cpu_data.x86 >= 6) { 16805a7ae78fSThomas Gleixner rdmsr(MSR_IA32_APICBASE, l, h); 16815a7ae78fSThomas Gleixner if (l & MSR_IA32_APICBASE_ENABLE) 16825a7ae78fSThomas Gleixner mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1683cbf2829bSBryan O'Donoghue } 16845a7ae78fSThomas Gleixner 16855a7ae78fSThomas Gleixner pr_info("Found and enabled local APIC!\n"); 16865a7ae78fSThomas Gleixner return 0; 16875a7ae78fSThomas Gleixner } 16885a7ae78fSThomas Gleixner 168925874a29SHenrik Kretzschmar int __init apic_force_enable(unsigned long addr) 16905a7ae78fSThomas Gleixner { 16915a7ae78fSThomas Gleixner u32 h, l; 16925a7ae78fSThomas Gleixner 16935a7ae78fSThomas Gleixner if (disable_apic) 16945a7ae78fSThomas Gleixner return -1; 16955a7ae78fSThomas Gleixner 16965a7ae78fSThomas Gleixner /* 16975a7ae78fSThomas Gleixner * Some BIOSes disable the local APIC in the APIC_BASE 16985a7ae78fSThomas Gleixner * MSR. This can only be done in software for Intel P6 or later 16995a7ae78fSThomas Gleixner * and AMD K7 (Model > 1) or later. 17005a7ae78fSThomas Gleixner */ 1701cbf2829bSBryan O'Donoghue if (boot_cpu_data.x86 >= 6) { 17025a7ae78fSThomas Gleixner rdmsr(MSR_IA32_APICBASE, l, h); 17035a7ae78fSThomas Gleixner if (!(l & MSR_IA32_APICBASE_ENABLE)) { 17045a7ae78fSThomas Gleixner pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 17055a7ae78fSThomas Gleixner l &= ~MSR_IA32_APICBASE_BASE; 1706a906fdaaSThomas Gleixner l |= MSR_IA32_APICBASE_ENABLE | addr; 17075a7ae78fSThomas Gleixner wrmsr(MSR_IA32_APICBASE, l, h); 17085a7ae78fSThomas Gleixner enabled_via_apicbase = 1; 17095a7ae78fSThomas Gleixner } 1710cbf2829bSBryan O'Donoghue } 17115a7ae78fSThomas Gleixner return apic_verify(); 17125a7ae78fSThomas Gleixner } 17135a7ae78fSThomas Gleixner 1714f62bae50SIngo Molnar /* 1715f62bae50SIngo Molnar * Detect and initialize APIC 1716f62bae50SIngo Molnar */ 1717f62bae50SIngo Molnar static int __init detect_init_APIC(void) 1718f62bae50SIngo Molnar { 1719f62bae50SIngo Molnar /* Disabled by kernel option? */ 1720f62bae50SIngo Molnar if (disable_apic) 1721f62bae50SIngo Molnar return -1; 1722f62bae50SIngo Molnar 1723f62bae50SIngo Molnar switch (boot_cpu_data.x86_vendor) { 1724f62bae50SIngo Molnar case X86_VENDOR_AMD: 1725f62bae50SIngo Molnar if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1726f62bae50SIngo Molnar (boot_cpu_data.x86 >= 15)) 1727f62bae50SIngo Molnar break; 1728f62bae50SIngo Molnar goto no_apic; 1729f62bae50SIngo Molnar case X86_VENDOR_INTEL: 1730f62bae50SIngo Molnar if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1731f62bae50SIngo Molnar (boot_cpu_data.x86 == 5 && cpu_has_apic)) 1732f62bae50SIngo Molnar break; 1733f62bae50SIngo Molnar goto no_apic; 1734f62bae50SIngo Molnar default: 1735f62bae50SIngo Molnar goto no_apic; 1736f62bae50SIngo Molnar } 1737f62bae50SIngo Molnar 1738f62bae50SIngo Molnar if (!cpu_has_apic) { 1739f62bae50SIngo Molnar /* 1740f62bae50SIngo Molnar * Over-ride BIOS and try to enable the local APIC only if 1741f62bae50SIngo Molnar * "lapic" specified. 1742f62bae50SIngo Molnar */ 1743f62bae50SIngo Molnar if (!force_enable_local_apic) { 1744f62bae50SIngo Molnar pr_info("Local APIC disabled by BIOS -- " 1745f62bae50SIngo Molnar "you can enable it with \"lapic\"\n"); 1746f62bae50SIngo Molnar return -1; 1747f62bae50SIngo Molnar } 1748a906fdaaSThomas Gleixner if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) 17495a7ae78fSThomas Gleixner return -1; 17505a7ae78fSThomas Gleixner } else { 17515a7ae78fSThomas Gleixner if (apic_verify()) 1752f62bae50SIngo Molnar return -1; 1753f62bae50SIngo Molnar } 1754f62bae50SIngo Molnar 1755f62bae50SIngo Molnar apic_pm_activate(); 1756f62bae50SIngo Molnar 1757f62bae50SIngo Molnar return 0; 1758f62bae50SIngo Molnar 1759f62bae50SIngo Molnar no_apic: 1760f62bae50SIngo Molnar pr_info("No local APIC present or hardware disabled\n"); 1761f62bae50SIngo Molnar return -1; 1762f62bae50SIngo Molnar } 1763f62bae50SIngo Molnar #endif 1764f62bae50SIngo Molnar 1765f62bae50SIngo Molnar /** 1766f62bae50SIngo Molnar * init_apic_mappings - initialize APIC mappings 1767f62bae50SIngo Molnar */ 1768f62bae50SIngo Molnar void __init init_apic_mappings(void) 1769f62bae50SIngo Molnar { 17704401da61SYinghai Lu unsigned int new_apicid; 17714401da61SYinghai Lu 1772fc1edaf9SSuresh Siddha if (x2apic_mode) { 1773f62bae50SIngo Molnar boot_cpu_physical_apicid = read_apic_id(); 1774f62bae50SIngo Molnar return; 1775f62bae50SIngo Molnar } 1776f62bae50SIngo Molnar 17774797f6b0SYinghai Lu /* If no local APIC can be found return early */ 1778f62bae50SIngo Molnar if (!smp_found_config && detect_init_APIC()) { 17794797f6b0SYinghai Lu /* lets NOP'ify apic operations */ 17804797f6b0SYinghai Lu pr_info("APIC: disable apic facility\n"); 17814797f6b0SYinghai Lu apic_disable(); 17824797f6b0SYinghai Lu } else { 1783f62bae50SIngo Molnar apic_phys = mp_lapic_addr; 1784f62bae50SIngo Molnar 17854401da61SYinghai Lu /* 17864401da61SYinghai Lu * acpi lapic path already maps that address in 17874401da61SYinghai Lu * acpi_register_lapic_address() 17884401da61SYinghai Lu */ 17895989cd6aSEric W. Biederman if (!acpi_lapic && !smp_found_config) 1790326a2e6bSYinghai Lu register_lapic_address(apic_phys); 1791cec6be6dSCyrill Gorcunov } 1792f62bae50SIngo Molnar 1793f62bae50SIngo Molnar /* 1794f62bae50SIngo Molnar * Fetch the APIC ID of the BSP in case we have a 1795f62bae50SIngo Molnar * default configuration (or the MP table is broken). 1796f62bae50SIngo Molnar */ 17974401da61SYinghai Lu new_apicid = read_apic_id(); 17984401da61SYinghai Lu if (boot_cpu_physical_apicid != new_apicid) { 17994401da61SYinghai Lu boot_cpu_physical_apicid = new_apicid; 1800103428e5SCyrill Gorcunov /* 1801103428e5SCyrill Gorcunov * yeah -- we lie about apic_version 1802103428e5SCyrill Gorcunov * in case if apic was disabled via boot option 1803103428e5SCyrill Gorcunov * but it's not a problem for SMP compiled kernel 1804103428e5SCyrill Gorcunov * since smp_sanity_check is prepared for such a case 1805103428e5SCyrill Gorcunov * and disable smp mode 1806103428e5SCyrill Gorcunov */ 18074401da61SYinghai Lu apic_version[new_apicid] = 18084401da61SYinghai Lu GET_APIC_VERSION(apic_read(APIC_LVR)); 180908306ce6SCyrill Gorcunov } 1810f62bae50SIngo Molnar } 1811f62bae50SIngo Molnar 1812c0104d38SYinghai Lu void __init register_lapic_address(unsigned long address) 1813c0104d38SYinghai Lu { 1814c0104d38SYinghai Lu mp_lapic_addr = address; 1815c0104d38SYinghai Lu 18160450193bSYinghai Lu if (!x2apic_mode) { 1817c0104d38SYinghai Lu set_fixmap_nocache(FIX_APIC_BASE, address); 1818f1157141SYinghai Lu apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 1819f1157141SYinghai Lu APIC_BASE, mp_lapic_addr); 18200450193bSYinghai Lu } 1821c0104d38SYinghai Lu if (boot_cpu_physical_apicid == -1U) { 1822c0104d38SYinghai Lu boot_cpu_physical_apicid = read_apic_id(); 1823c0104d38SYinghai Lu apic_version[boot_cpu_physical_apicid] = 1824c0104d38SYinghai Lu GET_APIC_VERSION(apic_read(APIC_LVR)); 1825c0104d38SYinghai Lu } 1826c0104d38SYinghai Lu } 1827c0104d38SYinghai Lu 1828f62bae50SIngo Molnar /* 1829f62bae50SIngo Molnar * This initializes the IO-APIC and APIC hardware if this is 1830f62bae50SIngo Molnar * a UP kernel. 1831f62bae50SIngo Molnar */ 183256d91f13SYinghai Lu int apic_version[MAX_LOCAL_APIC]; 1833f62bae50SIngo Molnar 1834f62bae50SIngo Molnar int __init APIC_init_uniprocessor(void) 1835f62bae50SIngo Molnar { 1836f62bae50SIngo Molnar if (disable_apic) { 1837f62bae50SIngo Molnar pr_info("Apic disabled\n"); 1838f62bae50SIngo Molnar return -1; 1839f62bae50SIngo Molnar } 1840f62bae50SIngo Molnar #ifdef CONFIG_X86_64 1841f62bae50SIngo Molnar if (!cpu_has_apic) { 1842f62bae50SIngo Molnar disable_apic = 1; 1843f62bae50SIngo Molnar pr_info("Apic disabled by BIOS\n"); 1844f62bae50SIngo Molnar return -1; 1845f62bae50SIngo Molnar } 1846f62bae50SIngo Molnar #else 1847f62bae50SIngo Molnar if (!smp_found_config && !cpu_has_apic) 1848f62bae50SIngo Molnar return -1; 1849f62bae50SIngo Molnar 1850f62bae50SIngo Molnar /* 1851f62bae50SIngo Molnar * Complain if the BIOS pretends there is one. 1852f62bae50SIngo Molnar */ 1853f62bae50SIngo Molnar if (!cpu_has_apic && 1854f62bae50SIngo Molnar APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 1855f62bae50SIngo Molnar pr_err("BIOS bug, local APIC 0x%x not detected!...\n", 1856f62bae50SIngo Molnar boot_cpu_physical_apicid); 1857f62bae50SIngo Molnar return -1; 1858f62bae50SIngo Molnar } 1859f62bae50SIngo Molnar #endif 1860f62bae50SIngo Molnar 1861f62bae50SIngo Molnar default_setup_apic_routing(); 1862f62bae50SIngo Molnar 1863f62bae50SIngo Molnar verify_local_APIC(); 1864f62bae50SIngo Molnar connect_bsp_APIC(); 1865f62bae50SIngo Molnar 1866f62bae50SIngo Molnar #ifdef CONFIG_X86_64 1867f62bae50SIngo Molnar apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); 1868f62bae50SIngo Molnar #else 1869f62bae50SIngo Molnar /* 1870f62bae50SIngo Molnar * Hack: In case of kdump, after a crash, kernel might be booting 1871f62bae50SIngo Molnar * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 1872f62bae50SIngo Molnar * might be zero if read from MP tables. Get it from LAPIC. 1873f62bae50SIngo Molnar */ 1874f62bae50SIngo Molnar # ifdef CONFIG_CRASH_DUMP 1875f62bae50SIngo Molnar boot_cpu_physical_apicid = read_apic_id(); 1876f62bae50SIngo Molnar # endif 1877f62bae50SIngo Molnar #endif 1878f62bae50SIngo Molnar physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1879f62bae50SIngo Molnar setup_local_APIC(); 1880f62bae50SIngo Molnar 1881f62bae50SIngo Molnar #ifdef CONFIG_X86_IO_APIC 1882f62bae50SIngo Molnar /* 1883f62bae50SIngo Molnar * Now enable IO-APICs, actually call clear_IO_APIC 1884f62bae50SIngo Molnar * We need clear_IO_APIC before enabling error vector 1885f62bae50SIngo Molnar */ 1886f62bae50SIngo Molnar if (!skip_ioapic_setup && nr_ioapics) 1887f62bae50SIngo Molnar enable_IO_APIC(); 1888f62bae50SIngo Molnar #endif 1889f62bae50SIngo Molnar 18902fb270f3SJan Beulich bsp_end_local_APIC_setup(); 1891f62bae50SIngo Molnar 1892f62bae50SIngo Molnar #ifdef CONFIG_X86_IO_APIC 1893f62bae50SIngo Molnar if (smp_found_config && !skip_ioapic_setup && nr_ioapics) 1894f62bae50SIngo Molnar setup_IO_APIC(); 1895f62bae50SIngo Molnar else { 1896f62bae50SIngo Molnar nr_ioapics = 0; 1897f62bae50SIngo Molnar } 1898f62bae50SIngo Molnar #endif 1899f62bae50SIngo Molnar 1900736decacSThomas Gleixner x86_init.timers.setup_percpu_clockev(); 1901f62bae50SIngo Molnar return 0; 1902f62bae50SIngo Molnar } 1903f62bae50SIngo Molnar 1904f62bae50SIngo Molnar /* 1905f62bae50SIngo Molnar * Local APIC interrupts 1906f62bae50SIngo Molnar */ 1907f62bae50SIngo Molnar 1908f62bae50SIngo Molnar /* 1909f62bae50SIngo Molnar * This interrupt should _never_ happen with our APIC/SMP architecture 1910f62bae50SIngo Molnar */ 1911f62bae50SIngo Molnar void smp_spurious_interrupt(struct pt_regs *regs) 1912f62bae50SIngo Molnar { 1913f62bae50SIngo Molnar u32 v; 1914f62bae50SIngo Molnar 1915f62bae50SIngo Molnar irq_enter(); 191698ad1cc1SFrederic Weisbecker exit_idle(); 1917f62bae50SIngo Molnar /* 1918f62bae50SIngo Molnar * Check if this really is a spurious interrupt and ACK it 1919f62bae50SIngo Molnar * if it is a vectored one. Just in case... 1920f62bae50SIngo Molnar * Spurious interrupts should not be ACKed. 1921f62bae50SIngo Molnar */ 1922f62bae50SIngo Molnar v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); 1923f62bae50SIngo Molnar if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) 1924f62bae50SIngo Molnar ack_APIC_irq(); 1925f62bae50SIngo Molnar 1926f62bae50SIngo Molnar inc_irq_stat(irq_spurious_count); 1927f62bae50SIngo Molnar 1928f62bae50SIngo Molnar /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 1929f62bae50SIngo Molnar pr_info("spurious APIC interrupt on CPU#%d, " 1930f62bae50SIngo Molnar "should never happen.\n", smp_processor_id()); 1931f62bae50SIngo Molnar irq_exit(); 1932f62bae50SIngo Molnar } 1933f62bae50SIngo Molnar 1934f62bae50SIngo Molnar /* 1935f62bae50SIngo Molnar * This interrupt should never happen with our APIC/SMP architecture 1936f62bae50SIngo Molnar */ 1937f62bae50SIngo Molnar void smp_error_interrupt(struct pt_regs *regs) 1938f62bae50SIngo Molnar { 19392b398bd9SYouquan Song u32 v0, v1; 19402b398bd9SYouquan Song u32 i = 0; 19412b398bd9SYouquan Song static const char * const error_interrupt_reason[] = { 19422b398bd9SYouquan Song "Send CS error", /* APIC Error Bit 0 */ 19432b398bd9SYouquan Song "Receive CS error", /* APIC Error Bit 1 */ 19442b398bd9SYouquan Song "Send accept error", /* APIC Error Bit 2 */ 19452b398bd9SYouquan Song "Receive accept error", /* APIC Error Bit 3 */ 19462b398bd9SYouquan Song "Redirectable IPI", /* APIC Error Bit 4 */ 19472b398bd9SYouquan Song "Send illegal vector", /* APIC Error Bit 5 */ 19482b398bd9SYouquan Song "Received illegal vector", /* APIC Error Bit 6 */ 19492b398bd9SYouquan Song "Illegal register address", /* APIC Error Bit 7 */ 19502b398bd9SYouquan Song }; 1951f62bae50SIngo Molnar 1952f62bae50SIngo Molnar irq_enter(); 195398ad1cc1SFrederic Weisbecker exit_idle(); 1954f62bae50SIngo Molnar /* First tickle the hardware, only then report what went on. -- REW */ 19552b398bd9SYouquan Song v0 = apic_read(APIC_ESR); 1956f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1957f62bae50SIngo Molnar v1 = apic_read(APIC_ESR); 1958f62bae50SIngo Molnar ack_APIC_irq(); 1959f62bae50SIngo Molnar atomic_inc(&irq_err_count); 1960f62bae50SIngo Molnar 19612b398bd9SYouquan Song apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x(%02x)", 19622b398bd9SYouquan Song smp_processor_id(), v0 , v1); 19632b398bd9SYouquan Song 19642b398bd9SYouquan Song v1 = v1 & 0xff; 19652b398bd9SYouquan Song while (v1) { 19662b398bd9SYouquan Song if (v1 & 0x1) 19672b398bd9SYouquan Song apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); 19682b398bd9SYouquan Song i++; 19692b398bd9SYouquan Song v1 >>= 1; 19704b8073e4SPeter Senna Tschudin } 19712b398bd9SYouquan Song 19722b398bd9SYouquan Song apic_printk(APIC_DEBUG, KERN_CONT "\n"); 19732b398bd9SYouquan Song 1974f62bae50SIngo Molnar irq_exit(); 1975f62bae50SIngo Molnar } 1976f62bae50SIngo Molnar 1977f62bae50SIngo Molnar /** 1978f62bae50SIngo Molnar * connect_bsp_APIC - attach the APIC to the interrupt system 1979f62bae50SIngo Molnar */ 1980f62bae50SIngo Molnar void __init connect_bsp_APIC(void) 1981f62bae50SIngo Molnar { 1982f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1983f62bae50SIngo Molnar if (pic_mode) { 1984f62bae50SIngo Molnar /* 1985f62bae50SIngo Molnar * Do not trust the local APIC being empty at bootup. 1986f62bae50SIngo Molnar */ 1987f62bae50SIngo Molnar clear_local_APIC(); 1988f62bae50SIngo Molnar /* 1989f62bae50SIngo Molnar * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 1990f62bae50SIngo Molnar * local APIC to INT and NMI lines. 1991f62bae50SIngo Molnar */ 1992f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "leaving PIC mode, " 1993f62bae50SIngo Molnar "enabling APIC mode.\n"); 1994c0eaa453SCyrill Gorcunov imcr_pic_to_apic(); 1995f62bae50SIngo Molnar } 1996f62bae50SIngo Molnar #endif 1997f62bae50SIngo Molnar if (apic->enable_apic_mode) 1998f62bae50SIngo Molnar apic->enable_apic_mode(); 1999f62bae50SIngo Molnar } 2000f62bae50SIngo Molnar 2001f62bae50SIngo Molnar /** 2002f62bae50SIngo Molnar * disconnect_bsp_APIC - detach the APIC from the interrupt system 2003f62bae50SIngo Molnar * @virt_wire_setup: indicates, whether virtual wire mode is selected 2004f62bae50SIngo Molnar * 2005f62bae50SIngo Molnar * Virtual wire mode is necessary to deliver legacy interrupts even when the 2006f62bae50SIngo Molnar * APIC is disabled. 2007f62bae50SIngo Molnar */ 2008f62bae50SIngo Molnar void disconnect_bsp_APIC(int virt_wire_setup) 2009f62bae50SIngo Molnar { 2010f62bae50SIngo Molnar unsigned int value; 2011f62bae50SIngo Molnar 2012f62bae50SIngo Molnar #ifdef CONFIG_X86_32 2013f62bae50SIngo Molnar if (pic_mode) { 2014f62bae50SIngo Molnar /* 2015f62bae50SIngo Molnar * Put the board back into PIC mode (has an effect only on 2016f62bae50SIngo Molnar * certain older boards). Note that APIC interrupts, including 2017f62bae50SIngo Molnar * IPIs, won't work beyond this point! The only exception are 2018f62bae50SIngo Molnar * INIT IPIs. 2019f62bae50SIngo Molnar */ 2020f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "disabling APIC mode, " 2021f62bae50SIngo Molnar "entering PIC mode.\n"); 2022c0eaa453SCyrill Gorcunov imcr_apic_to_pic(); 2023f62bae50SIngo Molnar return; 2024f62bae50SIngo Molnar } 2025f62bae50SIngo Molnar #endif 2026f62bae50SIngo Molnar 2027f62bae50SIngo Molnar /* Go back to Virtual Wire compatibility mode */ 2028f62bae50SIngo Molnar 2029f62bae50SIngo Molnar /* For the spurious interrupt use vector F, and enable it */ 2030f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 2031f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 2032f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 2033f62bae50SIngo Molnar value |= 0xf; 2034f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 2035f62bae50SIngo Molnar 2036f62bae50SIngo Molnar if (!virt_wire_setup) { 2037f62bae50SIngo Molnar /* 2038f62bae50SIngo Molnar * For LVT0 make it edge triggered, active high, 2039f62bae50SIngo Molnar * external and enabled 2040f62bae50SIngo Molnar */ 2041f62bae50SIngo Molnar value = apic_read(APIC_LVT0); 2042f62bae50SIngo Molnar value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2043f62bae50SIngo Molnar APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2044f62bae50SIngo Molnar APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2045f62bae50SIngo Molnar value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2046f62bae50SIngo Molnar value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 2047f62bae50SIngo Molnar apic_write(APIC_LVT0, value); 2048f62bae50SIngo Molnar } else { 2049f62bae50SIngo Molnar /* Disable LVT0 */ 2050f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_LVT_MASKED); 2051f62bae50SIngo Molnar } 2052f62bae50SIngo Molnar 2053f62bae50SIngo Molnar /* 2054f62bae50SIngo Molnar * For LVT1 make it edge triggered, active high, 2055f62bae50SIngo Molnar * nmi and enabled 2056f62bae50SIngo Molnar */ 2057f62bae50SIngo Molnar value = apic_read(APIC_LVT1); 2058f62bae50SIngo Molnar value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2059f62bae50SIngo Molnar APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2060f62bae50SIngo Molnar APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2061f62bae50SIngo Molnar value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2062f62bae50SIngo Molnar value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 2063f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 2064f62bae50SIngo Molnar } 2065f62bae50SIngo Molnar 2066f62bae50SIngo Molnar void __cpuinit generic_processor_info(int apicid, int version) 2067f62bae50SIngo Molnar { 206814cb6dcfSVivek Goyal int cpu, max = nr_cpu_ids; 206914cb6dcfSVivek Goyal bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, 207014cb6dcfSVivek Goyal phys_cpu_present_map); 207114cb6dcfSVivek Goyal 207214cb6dcfSVivek Goyal /* 207314cb6dcfSVivek Goyal * If boot cpu has not been detected yet, then only allow upto 207414cb6dcfSVivek Goyal * nr_cpu_ids - 1 processors and keep one slot free for boot cpu 207514cb6dcfSVivek Goyal */ 207614cb6dcfSVivek Goyal if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && 207714cb6dcfSVivek Goyal apicid != boot_cpu_physical_apicid) { 207814cb6dcfSVivek Goyal int thiscpu = max + disabled_cpus - 1; 207914cb6dcfSVivek Goyal 208014cb6dcfSVivek Goyal pr_warning( 208114cb6dcfSVivek Goyal "ACPI: NR_CPUS/possible_cpus limit of %i almost" 208214cb6dcfSVivek Goyal " reached. Keeping one slot for boot cpu." 208314cb6dcfSVivek Goyal " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 208414cb6dcfSVivek Goyal 208514cb6dcfSVivek Goyal disabled_cpus++; 208614cb6dcfSVivek Goyal return; 208714cb6dcfSVivek Goyal } 2088f62bae50SIngo Molnar 2089f62bae50SIngo Molnar if (num_processors >= nr_cpu_ids) { 2090f62bae50SIngo Molnar int thiscpu = max + disabled_cpus; 2091f62bae50SIngo Molnar 2092f62bae50SIngo Molnar pr_warning( 2093f62bae50SIngo Molnar "ACPI: NR_CPUS/possible_cpus limit of %i reached." 2094f62bae50SIngo Molnar " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2095f62bae50SIngo Molnar 2096f62bae50SIngo Molnar disabled_cpus++; 2097f62bae50SIngo Molnar return; 2098f62bae50SIngo Molnar } 2099f62bae50SIngo Molnar 2100f62bae50SIngo Molnar num_processors++; 2101f62bae50SIngo Molnar if (apicid == boot_cpu_physical_apicid) { 2102f62bae50SIngo Molnar /* 2103f62bae50SIngo Molnar * x86_bios_cpu_apicid is required to have processors listed 2104f62bae50SIngo Molnar * in same order as logical cpu numbers. Hence the first 2105f62bae50SIngo Molnar * entry is BSP, and so on. 2106e5fea868SYinghai Lu * boot_cpu_init() already hold bit 0 in cpu_present_mask 2107e5fea868SYinghai Lu * for BSP. 2108f62bae50SIngo Molnar */ 2109f62bae50SIngo Molnar cpu = 0; 2110e5fea868SYinghai Lu } else 2111e5fea868SYinghai Lu cpu = cpumask_next_zero(-1, cpu_present_mask); 2112e5fea868SYinghai Lu 2113e5fea868SYinghai Lu /* 2114e5fea868SYinghai Lu * Validate version 2115e5fea868SYinghai Lu */ 2116e5fea868SYinghai Lu if (version == 0x0) { 2117e5fea868SYinghai Lu pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", 2118e5fea868SYinghai Lu cpu, apicid); 2119e5fea868SYinghai Lu version = 0x10; 2120f62bae50SIngo Molnar } 2121e5fea868SYinghai Lu apic_version[apicid] = version; 2122e5fea868SYinghai Lu 2123e5fea868SYinghai Lu if (version != apic_version[boot_cpu_physical_apicid]) { 2124e5fea868SYinghai Lu pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", 2125e5fea868SYinghai Lu apic_version[boot_cpu_physical_apicid], cpu, version); 2126e5fea868SYinghai Lu } 2127e5fea868SYinghai Lu 2128e5fea868SYinghai Lu physid_set(apicid, phys_cpu_present_map); 2129f62bae50SIngo Molnar if (apicid > max_physical_apicid) 2130f62bae50SIngo Molnar max_physical_apicid = apicid; 2131f62bae50SIngo Molnar 2132f62bae50SIngo Molnar #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 2133f62bae50SIngo Molnar early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 2134f62bae50SIngo Molnar early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 2135f62bae50SIngo Molnar #endif 2136acb8bc09STejun Heo #ifdef CONFIG_X86_32 2137acb8bc09STejun Heo early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 2138acb8bc09STejun Heo apic->x86_32_early_logical_apicid(cpu); 2139acb8bc09STejun Heo #endif 2140f62bae50SIngo Molnar set_cpu_possible(cpu, true); 2141f62bae50SIngo Molnar set_cpu_present(cpu, true); 2142f62bae50SIngo Molnar } 2143f62bae50SIngo Molnar 2144f62bae50SIngo Molnar int hard_smp_processor_id(void) 2145f62bae50SIngo Molnar { 2146f62bae50SIngo Molnar return read_apic_id(); 2147f62bae50SIngo Molnar } 2148f62bae50SIngo Molnar 2149f62bae50SIngo Molnar void default_init_apic_ldr(void) 2150f62bae50SIngo Molnar { 2151f62bae50SIngo Molnar unsigned long val; 2152f62bae50SIngo Molnar 2153f62bae50SIngo Molnar apic_write(APIC_DFR, APIC_DFR_VALUE); 2154f62bae50SIngo Molnar val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; 2155f62bae50SIngo Molnar val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); 2156f62bae50SIngo Molnar apic_write(APIC_LDR, val); 2157f62bae50SIngo Molnar } 2158f62bae50SIngo Molnar 2159ff164324SAlexander Gordeev int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 2160ff164324SAlexander Gordeev const struct cpumask *andmask, 2161ff164324SAlexander Gordeev unsigned int *apicid) 21626398268dSAlexander Gordeev { 2163ea3807eaSAlexander Gordeev unsigned int cpu; 21646398268dSAlexander Gordeev 21656398268dSAlexander Gordeev for_each_cpu_and(cpu, cpumask, andmask) { 21666398268dSAlexander Gordeev if (cpumask_test_cpu(cpu, cpu_online_mask)) 21676398268dSAlexander Gordeev break; 21686398268dSAlexander Gordeev } 2169ff164324SAlexander Gordeev 2170ea3807eaSAlexander Gordeev if (likely(cpu < nr_cpu_ids)) { 2171a5a39156SAlexander Gordeev *apicid = per_cpu(x86_cpu_to_apicid, cpu); 2172a5a39156SAlexander Gordeev return 0; 2173a5a39156SAlexander Gordeev } 2174ea3807eaSAlexander Gordeev 2175ea3807eaSAlexander Gordeev return -EINVAL; 21766398268dSAlexander Gordeev } 21776398268dSAlexander Gordeev 2178f62bae50SIngo Molnar /* 21791551df64SMichael S. Tsirkin * Override the generic EOI implementation with an optimized version. 21801551df64SMichael S. Tsirkin * Only called during early boot when only one CPU is active and with 21811551df64SMichael S. Tsirkin * interrupts disabled, so we know this does not race with actual APIC driver 21821551df64SMichael S. Tsirkin * use. 21831551df64SMichael S. Tsirkin */ 21841551df64SMichael S. Tsirkin void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) 21851551df64SMichael S. Tsirkin { 21861551df64SMichael S. Tsirkin struct apic **drv; 21871551df64SMichael S. Tsirkin 21881551df64SMichael S. Tsirkin for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { 21891551df64SMichael S. Tsirkin /* Should happen once for each apic */ 21901551df64SMichael S. Tsirkin WARN_ON((*drv)->eoi_write == eoi_write); 21911551df64SMichael S. Tsirkin (*drv)->eoi_write = eoi_write; 21921551df64SMichael S. Tsirkin } 21931551df64SMichael S. Tsirkin } 21941551df64SMichael S. Tsirkin 21951551df64SMichael S. Tsirkin /* 2196f62bae50SIngo Molnar * Power management 2197f62bae50SIngo Molnar */ 2198f62bae50SIngo Molnar #ifdef CONFIG_PM 2199f62bae50SIngo Molnar 2200f62bae50SIngo Molnar static struct { 2201f62bae50SIngo Molnar /* 2202f62bae50SIngo Molnar * 'active' is true if the local APIC was enabled by us and 2203f62bae50SIngo Molnar * not the BIOS; this signifies that we are also responsible 2204f62bae50SIngo Molnar * for disabling it before entering apm/acpi suspend 2205f62bae50SIngo Molnar */ 2206f62bae50SIngo Molnar int active; 2207f62bae50SIngo Molnar /* r/w apic fields */ 2208f62bae50SIngo Molnar unsigned int apic_id; 2209f62bae50SIngo Molnar unsigned int apic_taskpri; 2210f62bae50SIngo Molnar unsigned int apic_ldr; 2211f62bae50SIngo Molnar unsigned int apic_dfr; 2212f62bae50SIngo Molnar unsigned int apic_spiv; 2213f62bae50SIngo Molnar unsigned int apic_lvtt; 2214f62bae50SIngo Molnar unsigned int apic_lvtpc; 2215f62bae50SIngo Molnar unsigned int apic_lvt0; 2216f62bae50SIngo Molnar unsigned int apic_lvt1; 2217f62bae50SIngo Molnar unsigned int apic_lvterr; 2218f62bae50SIngo Molnar unsigned int apic_tmict; 2219f62bae50SIngo Molnar unsigned int apic_tdcr; 2220f62bae50SIngo Molnar unsigned int apic_thmr; 2221f62bae50SIngo Molnar } apic_pm_state; 2222f62bae50SIngo Molnar 2223f3c6ea1bSRafael J. Wysocki static int lapic_suspend(void) 2224f62bae50SIngo Molnar { 2225f62bae50SIngo Molnar unsigned long flags; 2226f62bae50SIngo Molnar int maxlvt; 2227f62bae50SIngo Molnar 2228f62bae50SIngo Molnar if (!apic_pm_state.active) 2229f62bae50SIngo Molnar return 0; 2230f62bae50SIngo Molnar 2231f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 2232f62bae50SIngo Molnar 2233f62bae50SIngo Molnar apic_pm_state.apic_id = apic_read(APIC_ID); 2234f62bae50SIngo Molnar apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2235f62bae50SIngo Molnar apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2236f62bae50SIngo Molnar apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2237f62bae50SIngo Molnar apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2238f62bae50SIngo Molnar apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2239f62bae50SIngo Molnar if (maxlvt >= 4) 2240f62bae50SIngo Molnar apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2241f62bae50SIngo Molnar apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2242f62bae50SIngo Molnar apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2243f62bae50SIngo Molnar apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2244f62bae50SIngo Molnar apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2245f62bae50SIngo Molnar apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 22464efc0670SAndi Kleen #ifdef CONFIG_X86_THERMAL_VECTOR 2247f62bae50SIngo Molnar if (maxlvt >= 5) 2248f62bae50SIngo Molnar apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2249f62bae50SIngo Molnar #endif 2250f62bae50SIngo Molnar 2251f62bae50SIngo Molnar local_irq_save(flags); 2252f62bae50SIngo Molnar disable_local_APIC(); 2253fc1edaf9SSuresh Siddha 225495a02e97SSuresh Siddha if (irq_remapping_enabled) 225595a02e97SSuresh Siddha irq_remapping_disable(); 2256fc1edaf9SSuresh Siddha 2257f62bae50SIngo Molnar local_irq_restore(flags); 2258f62bae50SIngo Molnar return 0; 2259f62bae50SIngo Molnar } 2260f62bae50SIngo Molnar 2261f3c6ea1bSRafael J. Wysocki static void lapic_resume(void) 2262f62bae50SIngo Molnar { 2263f62bae50SIngo Molnar unsigned int l, h; 2264f62bae50SIngo Molnar unsigned long flags; 226531dce14aSSuresh Siddha int maxlvt; 2266b24696bcSFenghua Yu 2267f62bae50SIngo Molnar if (!apic_pm_state.active) 2268f3c6ea1bSRafael J. Wysocki return; 2269f62bae50SIngo Molnar 2270b24696bcSFenghua Yu local_irq_save(flags); 227195a02e97SSuresh Siddha if (irq_remapping_enabled) { 227231dce14aSSuresh Siddha /* 227331dce14aSSuresh Siddha * IO-APIC and PIC have their own resume routines. 227431dce14aSSuresh Siddha * We just mask them here to make sure the interrupt 227531dce14aSSuresh Siddha * subsystem is completely quiet while we enable x2apic 227631dce14aSSuresh Siddha * and interrupt-remapping. 227731dce14aSSuresh Siddha */ 227831dce14aSSuresh Siddha mask_ioapic_entries(); 2279b81bb373SJacob Pan legacy_pic->mask_all(); 2280b24696bcSFenghua Yu } 2281f62bae50SIngo Molnar 2282fc1edaf9SSuresh Siddha if (x2apic_mode) 2283f62bae50SIngo Molnar enable_x2apic(); 2284cf6567feSSuresh Siddha else { 2285f62bae50SIngo Molnar /* 2286f62bae50SIngo Molnar * Make sure the APICBASE points to the right address 2287f62bae50SIngo Molnar * 2288f62bae50SIngo Molnar * FIXME! This will be wrong if we ever support suspend on 2289f62bae50SIngo Molnar * SMP! We'll need to do this as part of the CPU restore! 2290f62bae50SIngo Molnar */ 2291cbf2829bSBryan O'Donoghue if (boot_cpu_data.x86 >= 6) { 2292f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, l, h); 2293f62bae50SIngo Molnar l &= ~MSR_IA32_APICBASE_BASE; 2294f62bae50SIngo Molnar l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2295f62bae50SIngo Molnar wrmsr(MSR_IA32_APICBASE, l, h); 2296f62bae50SIngo Molnar } 2297cbf2829bSBryan O'Donoghue } 2298f62bae50SIngo Molnar 2299b24696bcSFenghua Yu maxlvt = lapic_get_maxlvt(); 2300f62bae50SIngo Molnar apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2301f62bae50SIngo Molnar apic_write(APIC_ID, apic_pm_state.apic_id); 2302f62bae50SIngo Molnar apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2303f62bae50SIngo Molnar apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2304f62bae50SIngo Molnar apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2305f62bae50SIngo Molnar apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2306f62bae50SIngo Molnar apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2307f62bae50SIngo Molnar apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2308f62bae50SIngo Molnar #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) 2309f62bae50SIngo Molnar if (maxlvt >= 5) 2310f62bae50SIngo Molnar apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2311f62bae50SIngo Molnar #endif 2312f62bae50SIngo Molnar if (maxlvt >= 4) 2313f62bae50SIngo Molnar apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2314f62bae50SIngo Molnar apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2315f62bae50SIngo Molnar apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2316f62bae50SIngo Molnar apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2317f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 2318f62bae50SIngo Molnar apic_read(APIC_ESR); 2319f62bae50SIngo Molnar apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2320f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 2321f62bae50SIngo Molnar apic_read(APIC_ESR); 2322f62bae50SIngo Molnar 232395a02e97SSuresh Siddha if (irq_remapping_enabled) 232495a02e97SSuresh Siddha irq_remapping_reenable(x2apic_mode); 232531dce14aSSuresh Siddha 2326f62bae50SIngo Molnar local_irq_restore(flags); 2327f62bae50SIngo Molnar } 2328f62bae50SIngo Molnar 2329f62bae50SIngo Molnar /* 2330f62bae50SIngo Molnar * This device has no shutdown method - fully functioning local APICs 2331f62bae50SIngo Molnar * are needed on every CPU up until machine_halt/restart/poweroff. 2332f62bae50SIngo Molnar */ 2333f62bae50SIngo Molnar 2334f3c6ea1bSRafael J. Wysocki static struct syscore_ops lapic_syscore_ops = { 2335f62bae50SIngo Molnar .resume = lapic_resume, 2336f62bae50SIngo Molnar .suspend = lapic_suspend, 2337f62bae50SIngo Molnar }; 2338f62bae50SIngo Molnar 2339f62bae50SIngo Molnar static void __cpuinit apic_pm_activate(void) 2340f62bae50SIngo Molnar { 2341f62bae50SIngo Molnar apic_pm_state.active = 1; 2342f62bae50SIngo Molnar } 2343f62bae50SIngo Molnar 2344f62bae50SIngo Molnar static int __init init_lapic_sysfs(void) 2345f62bae50SIngo Molnar { 2346f62bae50SIngo Molnar /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2347f3c6ea1bSRafael J. Wysocki if (cpu_has_apic) 2348f3c6ea1bSRafael J. Wysocki register_syscore_ops(&lapic_syscore_ops); 2349f62bae50SIngo Molnar 2350f3c6ea1bSRafael J. Wysocki return 0; 2351f62bae50SIngo Molnar } 2352b24696bcSFenghua Yu 2353b24696bcSFenghua Yu /* local apic needs to resume before other devices access its registers. */ 2354b24696bcSFenghua Yu core_initcall(init_lapic_sysfs); 2355f62bae50SIngo Molnar 2356f62bae50SIngo Molnar #else /* CONFIG_PM */ 2357f62bae50SIngo Molnar 2358f62bae50SIngo Molnar static void apic_pm_activate(void) { } 2359f62bae50SIngo Molnar 2360f62bae50SIngo Molnar #endif /* CONFIG_PM */ 2361f62bae50SIngo Molnar 2362f62bae50SIngo Molnar #ifdef CONFIG_X86_64 2363e0e42142SYinghai Lu 2364e0e42142SYinghai Lu static int __cpuinit apic_cluster_num(void) 2365f62bae50SIngo Molnar { 2366f62bae50SIngo Molnar int i, clusters, zeros; 2367f62bae50SIngo Molnar unsigned id; 2368f62bae50SIngo Molnar u16 *bios_cpu_apicid; 2369f62bae50SIngo Molnar DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); 2370f62bae50SIngo Molnar 2371f62bae50SIngo Molnar bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); 2372f62bae50SIngo Molnar bitmap_zero(clustermap, NUM_APIC_CLUSTERS); 2373f62bae50SIngo Molnar 2374f62bae50SIngo Molnar for (i = 0; i < nr_cpu_ids; i++) { 2375f62bae50SIngo Molnar /* are we being called early in kernel startup? */ 2376f62bae50SIngo Molnar if (bios_cpu_apicid) { 2377f62bae50SIngo Molnar id = bios_cpu_apicid[i]; 2378f62bae50SIngo Molnar } else if (i < nr_cpu_ids) { 2379f62bae50SIngo Molnar if (cpu_present(i)) 2380f62bae50SIngo Molnar id = per_cpu(x86_bios_cpu_apicid, i); 2381f62bae50SIngo Molnar else 2382f62bae50SIngo Molnar continue; 2383f62bae50SIngo Molnar } else 2384f62bae50SIngo Molnar break; 2385f62bae50SIngo Molnar 2386f62bae50SIngo Molnar if (id != BAD_APICID) 2387f62bae50SIngo Molnar __set_bit(APIC_CLUSTERID(id), clustermap); 2388f62bae50SIngo Molnar } 2389f62bae50SIngo Molnar 2390f62bae50SIngo Molnar /* Problem: Partially populated chassis may not have CPUs in some of 2391f62bae50SIngo Molnar * the APIC clusters they have been allocated. Only present CPUs have 2392f62bae50SIngo Molnar * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. 2393f62bae50SIngo Molnar * Since clusters are allocated sequentially, count zeros only if 2394f62bae50SIngo Molnar * they are bounded by ones. 2395f62bae50SIngo Molnar */ 2396f62bae50SIngo Molnar clusters = 0; 2397f62bae50SIngo Molnar zeros = 0; 2398f62bae50SIngo Molnar for (i = 0; i < NUM_APIC_CLUSTERS; i++) { 2399f62bae50SIngo Molnar if (test_bit(i, clustermap)) { 2400f62bae50SIngo Molnar clusters += 1 + zeros; 2401f62bae50SIngo Molnar zeros = 0; 2402f62bae50SIngo Molnar } else 2403f62bae50SIngo Molnar ++zeros; 2404f62bae50SIngo Molnar } 2405f62bae50SIngo Molnar 2406e0e42142SYinghai Lu return clusters; 2407e0e42142SYinghai Lu } 2408e0e42142SYinghai Lu 2409e0e42142SYinghai Lu static int __cpuinitdata multi_checked; 2410e0e42142SYinghai Lu static int __cpuinitdata multi; 2411e0e42142SYinghai Lu 2412e0e42142SYinghai Lu static int __cpuinit set_multi(const struct dmi_system_id *d) 2413e0e42142SYinghai Lu { 2414e0e42142SYinghai Lu if (multi) 2415e0e42142SYinghai Lu return 0; 24166f0aced6SCyrill Gorcunov pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2417e0e42142SYinghai Lu multi = 1; 2418e0e42142SYinghai Lu return 0; 2419e0e42142SYinghai Lu } 2420e0e42142SYinghai Lu 2421e0e42142SYinghai Lu static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = { 2422e0e42142SYinghai Lu { 2423e0e42142SYinghai Lu .callback = set_multi, 2424e0e42142SYinghai Lu .ident = "IBM System Summit2", 2425e0e42142SYinghai Lu .matches = { 2426e0e42142SYinghai Lu DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2427e0e42142SYinghai Lu DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2428e0e42142SYinghai Lu }, 2429e0e42142SYinghai Lu }, 2430e0e42142SYinghai Lu {} 2431e0e42142SYinghai Lu }; 2432e0e42142SYinghai Lu 2433e0e42142SYinghai Lu static void __cpuinit dmi_check_multi(void) 2434e0e42142SYinghai Lu { 2435e0e42142SYinghai Lu if (multi_checked) 2436e0e42142SYinghai Lu return; 2437e0e42142SYinghai Lu 2438e0e42142SYinghai Lu dmi_check_system(multi_dmi_table); 2439e0e42142SYinghai Lu multi_checked = 1; 2440e0e42142SYinghai Lu } 2441f62bae50SIngo Molnar 2442f62bae50SIngo Molnar /* 2443e0e42142SYinghai Lu * apic_is_clustered_box() -- Check if we can expect good TSC 2444e0e42142SYinghai Lu * 2445e0e42142SYinghai Lu * Thus far, the major user of this is IBM's Summit2 series: 2446e0e42142SYinghai Lu * Clustered boxes may have unsynced TSC problems if they are 2447e0e42142SYinghai Lu * multi-chassis. 2448e0e42142SYinghai Lu * Use DMI to check them 2449f62bae50SIngo Molnar */ 2450e0e42142SYinghai Lu __cpuinit int apic_is_clustered_box(void) 2451e0e42142SYinghai Lu { 2452e0e42142SYinghai Lu dmi_check_multi(); 2453e0e42142SYinghai Lu if (multi) 2454e0e42142SYinghai Lu return 1; 2455e0e42142SYinghai Lu 2456e0e42142SYinghai Lu if (!is_vsmp_box()) 2457e0e42142SYinghai Lu return 0; 2458e0e42142SYinghai Lu 2459e0e42142SYinghai Lu /* 2460e0e42142SYinghai Lu * ScaleMP vSMPowered boxes have one cluster per board and TSCs are 2461e0e42142SYinghai Lu * not guaranteed to be synced between boards 2462e0e42142SYinghai Lu */ 2463e0e42142SYinghai Lu if (apic_cluster_num() > 1) 2464e0e42142SYinghai Lu return 1; 2465e0e42142SYinghai Lu 2466e0e42142SYinghai Lu return 0; 2467f62bae50SIngo Molnar } 2468f62bae50SIngo Molnar #endif 2469f62bae50SIngo Molnar 2470f62bae50SIngo Molnar /* 2471f62bae50SIngo Molnar * APIC command line parameters 2472f62bae50SIngo Molnar */ 2473f62bae50SIngo Molnar static int __init setup_disableapic(char *arg) 2474f62bae50SIngo Molnar { 2475f62bae50SIngo Molnar disable_apic = 1; 2476f62bae50SIngo Molnar setup_clear_cpu_cap(X86_FEATURE_APIC); 2477f62bae50SIngo Molnar return 0; 2478f62bae50SIngo Molnar } 2479f62bae50SIngo Molnar early_param("disableapic", setup_disableapic); 2480f62bae50SIngo Molnar 2481f62bae50SIngo Molnar /* same as disableapic, for compatibility */ 2482f62bae50SIngo Molnar static int __init setup_nolapic(char *arg) 2483f62bae50SIngo Molnar { 2484f62bae50SIngo Molnar return setup_disableapic(arg); 2485f62bae50SIngo Molnar } 2486f62bae50SIngo Molnar early_param("nolapic", setup_nolapic); 2487f62bae50SIngo Molnar 2488f62bae50SIngo Molnar static int __init parse_lapic_timer_c2_ok(char *arg) 2489f62bae50SIngo Molnar { 2490f62bae50SIngo Molnar local_apic_timer_c2_ok = 1; 2491f62bae50SIngo Molnar return 0; 2492f62bae50SIngo Molnar } 2493f62bae50SIngo Molnar early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2494f62bae50SIngo Molnar 2495f62bae50SIngo Molnar static int __init parse_disable_apic_timer(char *arg) 2496f62bae50SIngo Molnar { 2497f62bae50SIngo Molnar disable_apic_timer = 1; 2498f62bae50SIngo Molnar return 0; 2499f62bae50SIngo Molnar } 2500f62bae50SIngo Molnar early_param("noapictimer", parse_disable_apic_timer); 2501f62bae50SIngo Molnar 2502f62bae50SIngo Molnar static int __init parse_nolapic_timer(char *arg) 2503f62bae50SIngo Molnar { 2504f62bae50SIngo Molnar disable_apic_timer = 1; 2505f62bae50SIngo Molnar return 0; 2506f62bae50SIngo Molnar } 2507f62bae50SIngo Molnar early_param("nolapic_timer", parse_nolapic_timer); 2508f62bae50SIngo Molnar 2509f62bae50SIngo Molnar static int __init apic_set_verbosity(char *arg) 2510f62bae50SIngo Molnar { 2511f62bae50SIngo Molnar if (!arg) { 2512f62bae50SIngo Molnar #ifdef CONFIG_X86_64 2513f62bae50SIngo Molnar skip_ioapic_setup = 0; 2514f62bae50SIngo Molnar return 0; 2515f62bae50SIngo Molnar #endif 2516f62bae50SIngo Molnar return -EINVAL; 2517f62bae50SIngo Molnar } 2518f62bae50SIngo Molnar 2519f62bae50SIngo Molnar if (strcmp("debug", arg) == 0) 2520f62bae50SIngo Molnar apic_verbosity = APIC_DEBUG; 2521f62bae50SIngo Molnar else if (strcmp("verbose", arg) == 0) 2522f62bae50SIngo Molnar apic_verbosity = APIC_VERBOSE; 2523f62bae50SIngo Molnar else { 2524f62bae50SIngo Molnar pr_warning("APIC Verbosity level %s not recognised" 2525f62bae50SIngo Molnar " use apic=verbose or apic=debug\n", arg); 2526f62bae50SIngo Molnar return -EINVAL; 2527f62bae50SIngo Molnar } 2528f62bae50SIngo Molnar 2529f62bae50SIngo Molnar return 0; 2530f62bae50SIngo Molnar } 2531f62bae50SIngo Molnar early_param("apic", apic_set_verbosity); 2532f62bae50SIngo Molnar 2533f62bae50SIngo Molnar static int __init lapic_insert_resource(void) 2534f62bae50SIngo Molnar { 2535f62bae50SIngo Molnar if (!apic_phys) 2536f62bae50SIngo Molnar return -1; 2537f62bae50SIngo Molnar 2538f62bae50SIngo Molnar /* Put local APIC into the resource map. */ 2539f62bae50SIngo Molnar lapic_resource.start = apic_phys; 2540f62bae50SIngo Molnar lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2541f62bae50SIngo Molnar insert_resource(&iomem_resource, &lapic_resource); 2542f62bae50SIngo Molnar 2543f62bae50SIngo Molnar return 0; 2544f62bae50SIngo Molnar } 2545f62bae50SIngo Molnar 2546f62bae50SIngo Molnar /* 2547f62bae50SIngo Molnar * need call insert after e820_reserve_resources() 2548f62bae50SIngo Molnar * that is using request_resource 2549f62bae50SIngo Molnar */ 2550f62bae50SIngo Molnar late_initcall(lapic_insert_resource); 2551