1f62bae50SIngo Molnar /* 2f62bae50SIngo Molnar * Local APIC handling, local APIC timers 3f62bae50SIngo Molnar * 4f62bae50SIngo Molnar * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 5f62bae50SIngo Molnar * 6f62bae50SIngo Molnar * Fixes 7f62bae50SIngo Molnar * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8f62bae50SIngo Molnar * thanks to Eric Gilmore 9f62bae50SIngo Molnar * and Rolf G. Tews 10f62bae50SIngo Molnar * for testing these extensively. 11f62bae50SIngo Molnar * Maciej W. Rozycki : Various updates and fixes. 12f62bae50SIngo Molnar * Mikael Pettersson : Power Management for UP-APIC. 13f62bae50SIngo Molnar * Pavel Machek and 14f62bae50SIngo Molnar * Mikael Pettersson : PM converted to driver model. 15f62bae50SIngo Molnar */ 16f62bae50SIngo Molnar 17cdd6c482SIngo Molnar #include <linux/perf_event.h> 18f62bae50SIngo Molnar #include <linux/kernel_stat.h> 19f62bae50SIngo Molnar #include <linux/mc146818rtc.h> 20f62bae50SIngo Molnar #include <linux/acpi_pmtmr.h> 21f62bae50SIngo Molnar #include <linux/clockchips.h> 22f62bae50SIngo Molnar #include <linux/interrupt.h> 23f62bae50SIngo Molnar #include <linux/bootmem.h> 24f62bae50SIngo Molnar #include <linux/ftrace.h> 25f62bae50SIngo Molnar #include <linux/ioport.h> 26f62bae50SIngo Molnar #include <linux/module.h> 27f3c6ea1bSRafael J. Wysocki #include <linux/syscore_ops.h> 28f62bae50SIngo Molnar #include <linux/delay.h> 29f62bae50SIngo Molnar #include <linux/timex.h> 30f62bae50SIngo Molnar #include <linux/dmar.h> 31f62bae50SIngo Molnar #include <linux/init.h> 32f62bae50SIngo Molnar #include <linux/cpu.h> 33f62bae50SIngo Molnar #include <linux/dmi.h> 34f62bae50SIngo Molnar #include <linux/smp.h> 35f62bae50SIngo Molnar #include <linux/mm.h> 36f62bae50SIngo Molnar 37cdd6c482SIngo Molnar #include <asm/perf_event.h> 38736decacSThomas Gleixner #include <asm/x86_init.h> 39f62bae50SIngo Molnar #include <asm/pgalloc.h> 40f62bae50SIngo Molnar #include <asm/atomic.h> 41f62bae50SIngo Molnar #include <asm/mpspec.h> 42f62bae50SIngo Molnar #include <asm/i8253.h> 43f62bae50SIngo Molnar #include <asm/i8259.h> 44f62bae50SIngo Molnar #include <asm/proto.h> 45f62bae50SIngo Molnar #include <asm/apic.h> 467167d08eSHenrik Kretzschmar #include <asm/io_apic.h> 47f62bae50SIngo Molnar #include <asm/desc.h> 48f62bae50SIngo Molnar #include <asm/hpet.h> 49f62bae50SIngo Molnar #include <asm/idle.h> 50f62bae50SIngo Molnar #include <asm/mtrr.h> 51f62bae50SIngo Molnar #include <asm/smp.h> 52638bee71SH. Peter Anvin #include <asm/mce.h> 538c3ba8d0SKerstin Jonsson #include <asm/tsc.h> 542904ed8dSSheng Yang #include <asm/hypervisor.h> 55f62bae50SIngo Molnar 56f62bae50SIngo Molnar unsigned int num_processors; 57f62bae50SIngo Molnar 58f62bae50SIngo Molnar unsigned disabled_cpus __cpuinitdata; 59f62bae50SIngo Molnar 60f62bae50SIngo Molnar /* Processor that is doing the boot up */ 61f62bae50SIngo Molnar unsigned int boot_cpu_physical_apicid = -1U; 62f62bae50SIngo Molnar 63f62bae50SIngo Molnar /* 64f62bae50SIngo Molnar * The highest APIC ID seen during enumeration. 65f62bae50SIngo Molnar */ 66f62bae50SIngo Molnar unsigned int max_physical_apicid; 67f62bae50SIngo Molnar 68f62bae50SIngo Molnar /* 69f62bae50SIngo Molnar * Bitmask of physically existing CPUs: 70f62bae50SIngo Molnar */ 71f62bae50SIngo Molnar physid_mask_t phys_cpu_present_map; 72f62bae50SIngo Molnar 73f62bae50SIngo Molnar /* 74f62bae50SIngo Molnar * Map cpu index to physical APIC ID 75f62bae50SIngo Molnar */ 76f62bae50SIngo Molnar DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID); 77f62bae50SIngo Molnar DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID); 78f62bae50SIngo Molnar EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 79f62bae50SIngo Molnar EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 80f62bae50SIngo Molnar 81f62bae50SIngo Molnar #ifdef CONFIG_X86_32 824c321ff8STejun Heo 834c321ff8STejun Heo /* 844c321ff8STejun Heo * On x86_32, the mapping between cpu and logical apicid may vary 854c321ff8STejun Heo * depending on apic in use. The following early percpu variable is 864c321ff8STejun Heo * used for the mapping. This is where the behaviors of x86_64 and 32 874c321ff8STejun Heo * actually diverge. Let's keep it ugly for now. 884c321ff8STejun Heo */ 894c321ff8STejun Heo DEFINE_EARLY_PER_CPU(int, x86_cpu_to_logical_apicid, BAD_APICID); 904c321ff8STejun Heo 91f62bae50SIngo Molnar /* 92f62bae50SIngo Molnar * Knob to control our willingness to enable the local APIC. 93f62bae50SIngo Molnar * 94f62bae50SIngo Molnar * +1=force-enable 95f62bae50SIngo Molnar */ 9625874a29SHenrik Kretzschmar static int force_enable_local_apic __initdata; 97f62bae50SIngo Molnar /* 98f62bae50SIngo Molnar * APIC command line parameters 99f62bae50SIngo Molnar */ 100f62bae50SIngo Molnar static int __init parse_lapic(char *arg) 101f62bae50SIngo Molnar { 102f62bae50SIngo Molnar force_enable_local_apic = 1; 103f62bae50SIngo Molnar return 0; 104f62bae50SIngo Molnar } 105f62bae50SIngo Molnar early_param("lapic", parse_lapic); 106f62bae50SIngo Molnar /* Local APIC was disabled by the BIOS and enabled by the kernel */ 107f62bae50SIngo Molnar static int enabled_via_apicbase; 108f62bae50SIngo Molnar 109c0eaa453SCyrill Gorcunov /* 110c0eaa453SCyrill Gorcunov * Handle interrupt mode configuration register (IMCR). 111c0eaa453SCyrill Gorcunov * This register controls whether the interrupt signals 112c0eaa453SCyrill Gorcunov * that reach the BSP come from the master PIC or from the 113c0eaa453SCyrill Gorcunov * local APIC. Before entering Symmetric I/O Mode, either 114c0eaa453SCyrill Gorcunov * the BIOS or the operating system must switch out of 115c0eaa453SCyrill Gorcunov * PIC Mode by changing the IMCR. 116c0eaa453SCyrill Gorcunov */ 1175cda395fSAlexander van Heukelum static inline void imcr_pic_to_apic(void) 118c0eaa453SCyrill Gorcunov { 119c0eaa453SCyrill Gorcunov /* select IMCR register */ 120c0eaa453SCyrill Gorcunov outb(0x70, 0x22); 121c0eaa453SCyrill Gorcunov /* NMI and 8259 INTR go through APIC */ 122c0eaa453SCyrill Gorcunov outb(0x01, 0x23); 123c0eaa453SCyrill Gorcunov } 124c0eaa453SCyrill Gorcunov 1255cda395fSAlexander van Heukelum static inline void imcr_apic_to_pic(void) 126c0eaa453SCyrill Gorcunov { 127c0eaa453SCyrill Gorcunov /* select IMCR register */ 128c0eaa453SCyrill Gorcunov outb(0x70, 0x22); 129c0eaa453SCyrill Gorcunov /* NMI and 8259 INTR go directly to BSP */ 130c0eaa453SCyrill Gorcunov outb(0x00, 0x23); 131c0eaa453SCyrill Gorcunov } 132f62bae50SIngo Molnar #endif 133f62bae50SIngo Molnar 134f62bae50SIngo Molnar #ifdef CONFIG_X86_64 135f62bae50SIngo Molnar static int apic_calibrate_pmtmr __initdata; 136f62bae50SIngo Molnar static __init int setup_apicpmtimer(char *s) 137f62bae50SIngo Molnar { 138f62bae50SIngo Molnar apic_calibrate_pmtmr = 1; 139f62bae50SIngo Molnar notsc_setup(NULL); 140f62bae50SIngo Molnar return 0; 141f62bae50SIngo Molnar } 142f62bae50SIngo Molnar __setup("apicpmtimer", setup_apicpmtimer); 143f62bae50SIngo Molnar #endif 144f62bae50SIngo Molnar 145fc1edaf9SSuresh Siddha int x2apic_mode; 146f62bae50SIngo Molnar #ifdef CONFIG_X86_X2APIC 147f62bae50SIngo Molnar /* x2apic enabled before OS handover */ 148f62bae50SIngo Molnar static int x2apic_preenabled; 149f62bae50SIngo Molnar static __init int setup_nox2apic(char *str) 150f62bae50SIngo Molnar { 15139d83a5dSSuresh Siddha if (x2apic_enabled()) { 15239d83a5dSSuresh Siddha pr_warning("Bios already enabled x2apic, " 15339d83a5dSSuresh Siddha "can't enforce nox2apic"); 15439d83a5dSSuresh Siddha return 0; 15539d83a5dSSuresh Siddha } 15639d83a5dSSuresh Siddha 157f62bae50SIngo Molnar setup_clear_cpu_cap(X86_FEATURE_X2APIC); 158f62bae50SIngo Molnar return 0; 159f62bae50SIngo Molnar } 160f62bae50SIngo Molnar early_param("nox2apic", setup_nox2apic); 161f62bae50SIngo Molnar #endif 162f62bae50SIngo Molnar 163f62bae50SIngo Molnar unsigned long mp_lapic_addr; 164f62bae50SIngo Molnar int disable_apic; 165f62bae50SIngo Molnar /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 16625874a29SHenrik Kretzschmar static int disable_apic_timer __initdata; 167f62bae50SIngo Molnar /* Local APIC timer works in C2 */ 168f62bae50SIngo Molnar int local_apic_timer_c2_ok; 169f62bae50SIngo Molnar EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 170f62bae50SIngo Molnar 171f62bae50SIngo Molnar int first_system_vector = 0xfe; 172f62bae50SIngo Molnar 173f62bae50SIngo Molnar /* 174f62bae50SIngo Molnar * Debug level, exported for io_apic.c 175f62bae50SIngo Molnar */ 176f62bae50SIngo Molnar unsigned int apic_verbosity; 177f62bae50SIngo Molnar 178f62bae50SIngo Molnar int pic_mode; 179f62bae50SIngo Molnar 180f62bae50SIngo Molnar /* Have we found an MP table */ 181f62bae50SIngo Molnar int smp_found_config; 182f62bae50SIngo Molnar 183f62bae50SIngo Molnar static struct resource lapic_resource = { 184f62bae50SIngo Molnar .name = "Local APIC", 185f62bae50SIngo Molnar .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 186f62bae50SIngo Molnar }; 187f62bae50SIngo Molnar 188f62bae50SIngo Molnar static unsigned int calibration_result; 189f62bae50SIngo Molnar 190f62bae50SIngo Molnar static void apic_pm_activate(void); 191f62bae50SIngo Molnar 192f62bae50SIngo Molnar static unsigned long apic_phys; 193f62bae50SIngo Molnar 194f62bae50SIngo Molnar /* 195f62bae50SIngo Molnar * Get the LAPIC version 196f62bae50SIngo Molnar */ 197f62bae50SIngo Molnar static inline int lapic_get_version(void) 198f62bae50SIngo Molnar { 199f62bae50SIngo Molnar return GET_APIC_VERSION(apic_read(APIC_LVR)); 200f62bae50SIngo Molnar } 201f62bae50SIngo Molnar 202f62bae50SIngo Molnar /* 203f62bae50SIngo Molnar * Check, if the APIC is integrated or a separate chip 204f62bae50SIngo Molnar */ 205f62bae50SIngo Molnar static inline int lapic_is_integrated(void) 206f62bae50SIngo Molnar { 207f62bae50SIngo Molnar #ifdef CONFIG_X86_64 208f62bae50SIngo Molnar return 1; 209f62bae50SIngo Molnar #else 210f62bae50SIngo Molnar return APIC_INTEGRATED(lapic_get_version()); 211f62bae50SIngo Molnar #endif 212f62bae50SIngo Molnar } 213f62bae50SIngo Molnar 214f62bae50SIngo Molnar /* 215f62bae50SIngo Molnar * Check, whether this is a modern or a first generation APIC 216f62bae50SIngo Molnar */ 217f62bae50SIngo Molnar static int modern_apic(void) 218f62bae50SIngo Molnar { 219f62bae50SIngo Molnar /* AMD systems use old APIC versions, so check the CPU */ 220f62bae50SIngo Molnar if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 221f62bae50SIngo Molnar boot_cpu_data.x86 >= 0xf) 222f62bae50SIngo Molnar return 1; 223f62bae50SIngo Molnar return lapic_get_version() >= 0x14; 224f62bae50SIngo Molnar } 225f62bae50SIngo Molnar 22608306ce6SCyrill Gorcunov /* 227a933c618SCyrill Gorcunov * right after this call apic become NOOP driven 228a933c618SCyrill Gorcunov * so apic->write/read doesn't do anything 22908306ce6SCyrill Gorcunov */ 23025874a29SHenrik Kretzschmar static void __init apic_disable(void) 23108306ce6SCyrill Gorcunov { 232f88f2b4fSCyrill Gorcunov pr_info("APIC: switched to apic NOOP\n"); 233a933c618SCyrill Gorcunov apic = &apic_noop; 23408306ce6SCyrill Gorcunov } 23508306ce6SCyrill Gorcunov 236f62bae50SIngo Molnar void native_apic_wait_icr_idle(void) 237f62bae50SIngo Molnar { 238f62bae50SIngo Molnar while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 239f62bae50SIngo Molnar cpu_relax(); 240f62bae50SIngo Molnar } 241f62bae50SIngo Molnar 242f62bae50SIngo Molnar u32 native_safe_apic_wait_icr_idle(void) 243f62bae50SIngo Molnar { 244f62bae50SIngo Molnar u32 send_status; 245f62bae50SIngo Molnar int timeout; 246f62bae50SIngo Molnar 247f62bae50SIngo Molnar timeout = 0; 248f62bae50SIngo Molnar do { 249f62bae50SIngo Molnar send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 250f62bae50SIngo Molnar if (!send_status) 251f62bae50SIngo Molnar break; 252f62bae50SIngo Molnar udelay(100); 253f62bae50SIngo Molnar } while (timeout++ < 1000); 254f62bae50SIngo Molnar 255f62bae50SIngo Molnar return send_status; 256f62bae50SIngo Molnar } 257f62bae50SIngo Molnar 258f62bae50SIngo Molnar void native_apic_icr_write(u32 low, u32 id) 259f62bae50SIngo Molnar { 260f62bae50SIngo Molnar apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 261f62bae50SIngo Molnar apic_write(APIC_ICR, low); 262f62bae50SIngo Molnar } 263f62bae50SIngo Molnar 264f62bae50SIngo Molnar u64 native_apic_icr_read(void) 265f62bae50SIngo Molnar { 266f62bae50SIngo Molnar u32 icr1, icr2; 267f62bae50SIngo Molnar 268f62bae50SIngo Molnar icr2 = apic_read(APIC_ICR2); 269f62bae50SIngo Molnar icr1 = apic_read(APIC_ICR); 270f62bae50SIngo Molnar 271f62bae50SIngo Molnar return icr1 | ((u64)icr2 << 32); 272f62bae50SIngo Molnar } 273f62bae50SIngo Molnar 274f62bae50SIngo Molnar #ifdef CONFIG_X86_32 275f62bae50SIngo Molnar /** 276f62bae50SIngo Molnar * get_physical_broadcast - Get number of physical broadcast IDs 277f62bae50SIngo Molnar */ 278f62bae50SIngo Molnar int get_physical_broadcast(void) 279f62bae50SIngo Molnar { 280f62bae50SIngo Molnar return modern_apic() ? 0xff : 0xf; 281f62bae50SIngo Molnar } 282f62bae50SIngo Molnar #endif 283f62bae50SIngo Molnar 284f62bae50SIngo Molnar /** 285f62bae50SIngo Molnar * lapic_get_maxlvt - get the maximum number of local vector table entries 286f62bae50SIngo Molnar */ 287f62bae50SIngo Molnar int lapic_get_maxlvt(void) 288f62bae50SIngo Molnar { 289f62bae50SIngo Molnar unsigned int v; 290f62bae50SIngo Molnar 291f62bae50SIngo Molnar v = apic_read(APIC_LVR); 292f62bae50SIngo Molnar /* 293f62bae50SIngo Molnar * - we always have APIC integrated on 64bit mode 294f62bae50SIngo Molnar * - 82489DXs do not report # of LVT entries 295f62bae50SIngo Molnar */ 296f62bae50SIngo Molnar return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; 297f62bae50SIngo Molnar } 298f62bae50SIngo Molnar 299f62bae50SIngo Molnar /* 300f62bae50SIngo Molnar * Local APIC timer 301f62bae50SIngo Molnar */ 302f62bae50SIngo Molnar 303f62bae50SIngo Molnar /* Clock divisor */ 304f62bae50SIngo Molnar #define APIC_DIVISOR 16 305f62bae50SIngo Molnar 306f62bae50SIngo Molnar /* 307f62bae50SIngo Molnar * This function sets up the local APIC timer, with a timeout of 308f62bae50SIngo Molnar * 'clocks' APIC bus clock. During calibration we actually call 309f62bae50SIngo Molnar * this function twice on the boot CPU, once with a bogus timeout 310f62bae50SIngo Molnar * value, second time for real. The other (noncalibrating) CPUs 311f62bae50SIngo Molnar * call this function only once, with the real, calibrated value. 312f62bae50SIngo Molnar * 313f62bae50SIngo Molnar * We do reads before writes even if unnecessary, to get around the 314f62bae50SIngo Molnar * P5 APIC double write bug. 315f62bae50SIngo Molnar */ 316f62bae50SIngo Molnar static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 317f62bae50SIngo Molnar { 318f62bae50SIngo Molnar unsigned int lvtt_value, tmp_value; 319f62bae50SIngo Molnar 320f62bae50SIngo Molnar lvtt_value = LOCAL_TIMER_VECTOR; 321f62bae50SIngo Molnar if (!oneshot) 322f62bae50SIngo Molnar lvtt_value |= APIC_LVT_TIMER_PERIODIC; 323f62bae50SIngo Molnar if (!lapic_is_integrated()) 324f62bae50SIngo Molnar lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 325f62bae50SIngo Molnar 326f62bae50SIngo Molnar if (!irqen) 327f62bae50SIngo Molnar lvtt_value |= APIC_LVT_MASKED; 328f62bae50SIngo Molnar 329f62bae50SIngo Molnar apic_write(APIC_LVTT, lvtt_value); 330f62bae50SIngo Molnar 331f62bae50SIngo Molnar /* 332f62bae50SIngo Molnar * Divide PICLK by 16 333f62bae50SIngo Molnar */ 334f62bae50SIngo Molnar tmp_value = apic_read(APIC_TDCR); 335f62bae50SIngo Molnar apic_write(APIC_TDCR, 336f62bae50SIngo Molnar (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 337f62bae50SIngo Molnar APIC_TDR_DIV_16); 338f62bae50SIngo Molnar 339f62bae50SIngo Molnar if (!oneshot) 340f62bae50SIngo Molnar apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 341f62bae50SIngo Molnar } 342f62bae50SIngo Molnar 343f62bae50SIngo Molnar /* 344a68c439bSRobert Richter * Setup extended LVT, AMD specific 345f62bae50SIngo Molnar * 346a68c439bSRobert Richter * Software should use the LVT offsets the BIOS provides. The offsets 347a68c439bSRobert Richter * are determined by the subsystems using it like those for MCE 348a68c439bSRobert Richter * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 349a68c439bSRobert Richter * are supported. Beginning with family 10h at least 4 offsets are 350a68c439bSRobert Richter * available. 351f62bae50SIngo Molnar * 352a68c439bSRobert Richter * Since the offsets must be consistent for all cores, we keep track 353a68c439bSRobert Richter * of the LVT offsets in software and reserve the offset for the same 354a68c439bSRobert Richter * vector also to be used on other cores. An offset is freed by 355a68c439bSRobert Richter * setting the entry to APIC_EILVT_MASKED. 356a68c439bSRobert Richter * 357a68c439bSRobert Richter * If the BIOS is right, there should be no conflicts. Otherwise a 358a68c439bSRobert Richter * "[Firmware Bug]: ..." error message is generated. However, if 359a68c439bSRobert Richter * software does not properly determines the offsets, it is not 360a68c439bSRobert Richter * necessarily a BIOS bug. 361f62bae50SIngo Molnar */ 362f62bae50SIngo Molnar 363a68c439bSRobert Richter static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 364f62bae50SIngo Molnar 365a68c439bSRobert Richter static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 366a68c439bSRobert Richter { 367a68c439bSRobert Richter return (old & APIC_EILVT_MASKED) 368a68c439bSRobert Richter || (new == APIC_EILVT_MASKED) 369a68c439bSRobert Richter || ((new & ~APIC_EILVT_MASKED) == old); 370a68c439bSRobert Richter } 371a68c439bSRobert Richter 372a68c439bSRobert Richter static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 373a68c439bSRobert Richter { 374a68c439bSRobert Richter unsigned int rsvd; /* 0: uninitialized */ 375a68c439bSRobert Richter 376a68c439bSRobert Richter if (offset >= APIC_EILVT_NR_MAX) 377a68c439bSRobert Richter return ~0; 378a68c439bSRobert Richter 379a68c439bSRobert Richter rsvd = atomic_read(&eilvt_offsets[offset]) & ~APIC_EILVT_MASKED; 380a68c439bSRobert Richter do { 381a68c439bSRobert Richter if (rsvd && 382a68c439bSRobert Richter !eilvt_entry_is_changeable(rsvd, new)) 383a68c439bSRobert Richter /* may not change if vectors are different */ 384a68c439bSRobert Richter return rsvd; 385a68c439bSRobert Richter rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 386a68c439bSRobert Richter } while (rsvd != new); 387a68c439bSRobert Richter 388a68c439bSRobert Richter return new; 389a68c439bSRobert Richter } 390a68c439bSRobert Richter 391a68c439bSRobert Richter /* 392a68c439bSRobert Richter * If mask=1, the LVT entry does not generate interrupts while mask=0 393cbf74ceaSRobert Richter * enables the vector. See also the BKDGs. Must be called with 394cbf74ceaSRobert Richter * preemption disabled. 395a68c439bSRobert Richter */ 396a68c439bSRobert Richter 39727afdf20SRobert Richter int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 398a68c439bSRobert Richter { 399a68c439bSRobert Richter unsigned long reg = APIC_EILVTn(offset); 400a68c439bSRobert Richter unsigned int new, old, reserved; 401a68c439bSRobert Richter 402a68c439bSRobert Richter new = (mask << 16) | (msg_type << 8) | vector; 403a68c439bSRobert Richter old = apic_read(reg); 404a68c439bSRobert Richter reserved = reserve_eilvt_offset(offset, new); 405a68c439bSRobert Richter 406a68c439bSRobert Richter if (reserved != new) { 407eb48c9cbSRobert Richter pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 408eb48c9cbSRobert Richter "vector 0x%x, but the register is already in use for " 409eb48c9cbSRobert Richter "vector 0x%x on another cpu\n", 410eb48c9cbSRobert Richter smp_processor_id(), reg, offset, new, reserved); 411a68c439bSRobert Richter return -EINVAL; 412a68c439bSRobert Richter } 413a68c439bSRobert Richter 414a68c439bSRobert Richter if (!eilvt_entry_is_changeable(old, new)) { 415eb48c9cbSRobert Richter pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 416eb48c9cbSRobert Richter "vector 0x%x, but the register is already in use for " 417eb48c9cbSRobert Richter "vector 0x%x on this cpu\n", 418eb48c9cbSRobert Richter smp_processor_id(), reg, offset, new, old); 419a68c439bSRobert Richter return -EBUSY; 420a68c439bSRobert Richter } 421a68c439bSRobert Richter 422a68c439bSRobert Richter apic_write(reg, new); 423a68c439bSRobert Richter 424a68c439bSRobert Richter return 0; 425f62bae50SIngo Molnar } 42627afdf20SRobert Richter EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 427f62bae50SIngo Molnar 428f62bae50SIngo Molnar /* 429f62bae50SIngo Molnar * Program the next event, relative to now 430f62bae50SIngo Molnar */ 431f62bae50SIngo Molnar static int lapic_next_event(unsigned long delta, 432f62bae50SIngo Molnar struct clock_event_device *evt) 433f62bae50SIngo Molnar { 434f62bae50SIngo Molnar apic_write(APIC_TMICT, delta); 435f62bae50SIngo Molnar return 0; 436f62bae50SIngo Molnar } 437f62bae50SIngo Molnar 438f62bae50SIngo Molnar /* 439f62bae50SIngo Molnar * Setup the lapic timer in periodic or oneshot mode 440f62bae50SIngo Molnar */ 441f62bae50SIngo Molnar static void lapic_timer_setup(enum clock_event_mode mode, 442f62bae50SIngo Molnar struct clock_event_device *evt) 443f62bae50SIngo Molnar { 444f62bae50SIngo Molnar unsigned long flags; 445f62bae50SIngo Molnar unsigned int v; 446f62bae50SIngo Molnar 447f62bae50SIngo Molnar /* Lapic used as dummy for broadcast ? */ 448f62bae50SIngo Molnar if (evt->features & CLOCK_EVT_FEAT_DUMMY) 449f62bae50SIngo Molnar return; 450f62bae50SIngo Molnar 451f62bae50SIngo Molnar local_irq_save(flags); 452f62bae50SIngo Molnar 453f62bae50SIngo Molnar switch (mode) { 454f62bae50SIngo Molnar case CLOCK_EVT_MODE_PERIODIC: 455f62bae50SIngo Molnar case CLOCK_EVT_MODE_ONESHOT: 456f62bae50SIngo Molnar __setup_APIC_LVTT(calibration_result, 457f62bae50SIngo Molnar mode != CLOCK_EVT_MODE_PERIODIC, 1); 458f62bae50SIngo Molnar break; 459f62bae50SIngo Molnar case CLOCK_EVT_MODE_UNUSED: 460f62bae50SIngo Molnar case CLOCK_EVT_MODE_SHUTDOWN: 461f62bae50SIngo Molnar v = apic_read(APIC_LVTT); 462f62bae50SIngo Molnar v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 463f62bae50SIngo Molnar apic_write(APIC_LVTT, v); 4646f9b4100SAndreas Herrmann apic_write(APIC_TMICT, 0); 465f62bae50SIngo Molnar break; 466f62bae50SIngo Molnar case CLOCK_EVT_MODE_RESUME: 467f62bae50SIngo Molnar /* Nothing to do here */ 468f62bae50SIngo Molnar break; 469f62bae50SIngo Molnar } 470f62bae50SIngo Molnar 471f62bae50SIngo Molnar local_irq_restore(flags); 472f62bae50SIngo Molnar } 473f62bae50SIngo Molnar 474f62bae50SIngo Molnar /* 475f62bae50SIngo Molnar * Local APIC timer broadcast function 476f62bae50SIngo Molnar */ 477f62bae50SIngo Molnar static void lapic_timer_broadcast(const struct cpumask *mask) 478f62bae50SIngo Molnar { 479f62bae50SIngo Molnar #ifdef CONFIG_SMP 480f62bae50SIngo Molnar apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 481f62bae50SIngo Molnar #endif 482f62bae50SIngo Molnar } 483f62bae50SIngo Molnar 48425874a29SHenrik Kretzschmar 48525874a29SHenrik Kretzschmar /* 48625874a29SHenrik Kretzschmar * The local apic timer can be used for any function which is CPU local. 48725874a29SHenrik Kretzschmar */ 48825874a29SHenrik Kretzschmar static struct clock_event_device lapic_clockevent = { 48925874a29SHenrik Kretzschmar .name = "lapic", 49025874a29SHenrik Kretzschmar .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT 49125874a29SHenrik Kretzschmar | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, 49225874a29SHenrik Kretzschmar .shift = 32, 49325874a29SHenrik Kretzschmar .set_mode = lapic_timer_setup, 49425874a29SHenrik Kretzschmar .set_next_event = lapic_next_event, 49525874a29SHenrik Kretzschmar .broadcast = lapic_timer_broadcast, 49625874a29SHenrik Kretzschmar .rating = 100, 49725874a29SHenrik Kretzschmar .irq = -1, 49825874a29SHenrik Kretzschmar }; 49925874a29SHenrik Kretzschmar static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 50025874a29SHenrik Kretzschmar 501f62bae50SIngo Molnar /* 502421f91d2SUwe Kleine-König * Setup the local APIC timer for this CPU. Copy the initialized values 503f62bae50SIngo Molnar * of the boot CPU and register the clock event in the framework. 504f62bae50SIngo Molnar */ 505f62bae50SIngo Molnar static void __cpuinit setup_APIC_timer(void) 506f62bae50SIngo Molnar { 507f62bae50SIngo Molnar struct clock_event_device *levt = &__get_cpu_var(lapic_events); 508f62bae50SIngo Molnar 509349c004eSChristoph Lameter if (this_cpu_has(X86_FEATURE_ARAT)) { 510db954b58SVenkatesh Pallipadi lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 511db954b58SVenkatesh Pallipadi /* Make LAPIC timer preferrable over percpu HPET */ 512db954b58SVenkatesh Pallipadi lapic_clockevent.rating = 150; 513db954b58SVenkatesh Pallipadi } 514db954b58SVenkatesh Pallipadi 515f62bae50SIngo Molnar memcpy(levt, &lapic_clockevent, sizeof(*levt)); 516f62bae50SIngo Molnar levt->cpumask = cpumask_of(smp_processor_id()); 517f62bae50SIngo Molnar 518f62bae50SIngo Molnar clockevents_register_device(levt); 519f62bae50SIngo Molnar } 520f62bae50SIngo Molnar 521f62bae50SIngo Molnar /* 522f62bae50SIngo Molnar * In this functions we calibrate APIC bus clocks to the external timer. 523f62bae50SIngo Molnar * 524f62bae50SIngo Molnar * We want to do the calibration only once since we want to have local timer 525f62bae50SIngo Molnar * irqs syncron. CPUs connected by the same APIC bus have the very same bus 526f62bae50SIngo Molnar * frequency. 527f62bae50SIngo Molnar * 528f62bae50SIngo Molnar * This was previously done by reading the PIT/HPET and waiting for a wrap 529f62bae50SIngo Molnar * around to find out, that a tick has elapsed. I have a box, where the PIT 530f62bae50SIngo Molnar * readout is broken, so it never gets out of the wait loop again. This was 531f62bae50SIngo Molnar * also reported by others. 532f62bae50SIngo Molnar * 533f62bae50SIngo Molnar * Monitoring the jiffies value is inaccurate and the clockevents 534f62bae50SIngo Molnar * infrastructure allows us to do a simple substitution of the interrupt 535f62bae50SIngo Molnar * handler. 536f62bae50SIngo Molnar * 537f62bae50SIngo Molnar * The calibration routine also uses the pm_timer when possible, as the PIT 538f62bae50SIngo Molnar * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 539f62bae50SIngo Molnar * back to normal later in the boot process). 540f62bae50SIngo Molnar */ 541f62bae50SIngo Molnar 542f62bae50SIngo Molnar #define LAPIC_CAL_LOOPS (HZ/10) 543f62bae50SIngo Molnar 544f62bae50SIngo Molnar static __initdata int lapic_cal_loops = -1; 545f62bae50SIngo Molnar static __initdata long lapic_cal_t1, lapic_cal_t2; 546f62bae50SIngo Molnar static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 547f62bae50SIngo Molnar static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 548f62bae50SIngo Molnar static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 549f62bae50SIngo Molnar 550f62bae50SIngo Molnar /* 551f62bae50SIngo Molnar * Temporary interrupt handler. 552f62bae50SIngo Molnar */ 553f62bae50SIngo Molnar static void __init lapic_cal_handler(struct clock_event_device *dev) 554f62bae50SIngo Molnar { 555f62bae50SIngo Molnar unsigned long long tsc = 0; 556f62bae50SIngo Molnar long tapic = apic_read(APIC_TMCCT); 557f62bae50SIngo Molnar unsigned long pm = acpi_pm_read_early(); 558f62bae50SIngo Molnar 559f62bae50SIngo Molnar if (cpu_has_tsc) 560f62bae50SIngo Molnar rdtscll(tsc); 561f62bae50SIngo Molnar 562f62bae50SIngo Molnar switch (lapic_cal_loops++) { 563f62bae50SIngo Molnar case 0: 564f62bae50SIngo Molnar lapic_cal_t1 = tapic; 565f62bae50SIngo Molnar lapic_cal_tsc1 = tsc; 566f62bae50SIngo Molnar lapic_cal_pm1 = pm; 567f62bae50SIngo Molnar lapic_cal_j1 = jiffies; 568f62bae50SIngo Molnar break; 569f62bae50SIngo Molnar 570f62bae50SIngo Molnar case LAPIC_CAL_LOOPS: 571f62bae50SIngo Molnar lapic_cal_t2 = tapic; 572f62bae50SIngo Molnar lapic_cal_tsc2 = tsc; 573f62bae50SIngo Molnar if (pm < lapic_cal_pm1) 574f62bae50SIngo Molnar pm += ACPI_PM_OVRRUN; 575f62bae50SIngo Molnar lapic_cal_pm2 = pm; 576f62bae50SIngo Molnar lapic_cal_j2 = jiffies; 577f62bae50SIngo Molnar break; 578f62bae50SIngo Molnar } 579f62bae50SIngo Molnar } 580f62bae50SIngo Molnar 581f62bae50SIngo Molnar static int __init 582f62bae50SIngo Molnar calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 583f62bae50SIngo Molnar { 584f62bae50SIngo Molnar const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 585f62bae50SIngo Molnar const long pm_thresh = pm_100ms / 100; 586f62bae50SIngo Molnar unsigned long mult; 587f62bae50SIngo Molnar u64 res; 588f62bae50SIngo Molnar 589f62bae50SIngo Molnar #ifndef CONFIG_X86_PM_TIMER 590f62bae50SIngo Molnar return -1; 591f62bae50SIngo Molnar #endif 592f62bae50SIngo Molnar 593f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 594f62bae50SIngo Molnar 595f62bae50SIngo Molnar /* Check, if the PM timer is available */ 596f62bae50SIngo Molnar if (!deltapm) 597f62bae50SIngo Molnar return -1; 598f62bae50SIngo Molnar 599f62bae50SIngo Molnar mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 600f62bae50SIngo Molnar 601f62bae50SIngo Molnar if (deltapm > (pm_100ms - pm_thresh) && 602f62bae50SIngo Molnar deltapm < (pm_100ms + pm_thresh)) { 603f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 604f62bae50SIngo Molnar return 0; 605f62bae50SIngo Molnar } 606f62bae50SIngo Molnar 607f62bae50SIngo Molnar res = (((u64)deltapm) * mult) >> 22; 608f62bae50SIngo Molnar do_div(res, 1000000); 609f62bae50SIngo Molnar pr_warning("APIC calibration not consistent " 610f62bae50SIngo Molnar "with PM-Timer: %ldms instead of 100ms\n",(long)res); 611f62bae50SIngo Molnar 612f62bae50SIngo Molnar /* Correct the lapic counter value */ 613f62bae50SIngo Molnar res = (((u64)(*delta)) * pm_100ms); 614f62bae50SIngo Molnar do_div(res, deltapm); 615f62bae50SIngo Molnar pr_info("APIC delta adjusted to PM-Timer: " 616f62bae50SIngo Molnar "%lu (%ld)\n", (unsigned long)res, *delta); 617f62bae50SIngo Molnar *delta = (long)res; 618f62bae50SIngo Molnar 619f62bae50SIngo Molnar /* Correct the tsc counter value */ 620f62bae50SIngo Molnar if (cpu_has_tsc) { 621f62bae50SIngo Molnar res = (((u64)(*deltatsc)) * pm_100ms); 622f62bae50SIngo Molnar do_div(res, deltapm); 623f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 624f62bae50SIngo Molnar "PM-Timer: %lu (%ld)\n", 625f62bae50SIngo Molnar (unsigned long)res, *deltatsc); 626f62bae50SIngo Molnar *deltatsc = (long)res; 627f62bae50SIngo Molnar } 628f62bae50SIngo Molnar 629f62bae50SIngo Molnar return 0; 630f62bae50SIngo Molnar } 631f62bae50SIngo Molnar 632f62bae50SIngo Molnar static int __init calibrate_APIC_clock(void) 633f62bae50SIngo Molnar { 634f62bae50SIngo Molnar struct clock_event_device *levt = &__get_cpu_var(lapic_events); 635f62bae50SIngo Molnar void (*real_handler)(struct clock_event_device *dev); 636f62bae50SIngo Molnar unsigned long deltaj; 637f62bae50SIngo Molnar long delta, deltatsc; 638f62bae50SIngo Molnar int pm_referenced = 0; 639f62bae50SIngo Molnar 640f62bae50SIngo Molnar local_irq_disable(); 641f62bae50SIngo Molnar 642f62bae50SIngo Molnar /* Replace the global interrupt handler */ 643f62bae50SIngo Molnar real_handler = global_clock_event->event_handler; 644f62bae50SIngo Molnar global_clock_event->event_handler = lapic_cal_handler; 645f62bae50SIngo Molnar 646f62bae50SIngo Molnar /* 647f62bae50SIngo Molnar * Setup the APIC counter to maximum. There is no way the lapic 648f62bae50SIngo Molnar * can underflow in the 100ms detection time frame 649f62bae50SIngo Molnar */ 650f62bae50SIngo Molnar __setup_APIC_LVTT(0xffffffff, 0, 0); 651f62bae50SIngo Molnar 652f62bae50SIngo Molnar /* Let the interrupts run */ 653f62bae50SIngo Molnar local_irq_enable(); 654f62bae50SIngo Molnar 655f62bae50SIngo Molnar while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 656f62bae50SIngo Molnar cpu_relax(); 657f62bae50SIngo Molnar 658f62bae50SIngo Molnar local_irq_disable(); 659f62bae50SIngo Molnar 660f62bae50SIngo Molnar /* Restore the real event handler */ 661f62bae50SIngo Molnar global_clock_event->event_handler = real_handler; 662f62bae50SIngo Molnar 663f62bae50SIngo Molnar /* Build delta t1-t2 as apic timer counts down */ 664f62bae50SIngo Molnar delta = lapic_cal_t1 - lapic_cal_t2; 665f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 666f62bae50SIngo Molnar 667f62bae50SIngo Molnar deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 668f62bae50SIngo Molnar 669f62bae50SIngo Molnar /* we trust the PM based calibration if possible */ 670f62bae50SIngo Molnar pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 671f62bae50SIngo Molnar &delta, &deltatsc); 672f62bae50SIngo Molnar 673f62bae50SIngo Molnar /* Calculate the scaled math multiplication factor */ 674f62bae50SIngo Molnar lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 675f62bae50SIngo Molnar lapic_clockevent.shift); 676f62bae50SIngo Molnar lapic_clockevent.max_delta_ns = 6774aed89d6SPierre Tardy clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 678f62bae50SIngo Molnar lapic_clockevent.min_delta_ns = 679f62bae50SIngo Molnar clockevent_delta2ns(0xF, &lapic_clockevent); 680f62bae50SIngo Molnar 681f62bae50SIngo Molnar calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 682f62bae50SIngo Molnar 683f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 684411462f6SThomas Gleixner apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 685f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 686f62bae50SIngo Molnar calibration_result); 687f62bae50SIngo Molnar 688f62bae50SIngo Molnar if (cpu_has_tsc) { 689f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 690f62bae50SIngo Molnar "%ld.%04ld MHz.\n", 691f62bae50SIngo Molnar (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 692f62bae50SIngo Molnar (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 693f62bae50SIngo Molnar } 694f62bae50SIngo Molnar 695f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 696f62bae50SIngo Molnar "%u.%04u MHz.\n", 697f62bae50SIngo Molnar calibration_result / (1000000 / HZ), 698f62bae50SIngo Molnar calibration_result % (1000000 / HZ)); 699f62bae50SIngo Molnar 700f62bae50SIngo Molnar /* 701f62bae50SIngo Molnar * Do a sanity check on the APIC calibration result 702f62bae50SIngo Molnar */ 703f62bae50SIngo Molnar if (calibration_result < (1000000 / HZ)) { 704f62bae50SIngo Molnar local_irq_enable(); 705f62bae50SIngo Molnar pr_warning("APIC frequency too slow, disabling apic timer\n"); 706f62bae50SIngo Molnar return -1; 707f62bae50SIngo Molnar } 708f62bae50SIngo Molnar 709f62bae50SIngo Molnar levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 710f62bae50SIngo Molnar 711f62bae50SIngo Molnar /* 712f62bae50SIngo Molnar * PM timer calibration failed or not turned on 713f62bae50SIngo Molnar * so lets try APIC timer based calibration 714f62bae50SIngo Molnar */ 715f62bae50SIngo Molnar if (!pm_referenced) { 716f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 717f62bae50SIngo Molnar 718f62bae50SIngo Molnar /* 719f62bae50SIngo Molnar * Setup the apic timer manually 720f62bae50SIngo Molnar */ 721f62bae50SIngo Molnar levt->event_handler = lapic_cal_handler; 722f62bae50SIngo Molnar lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); 723f62bae50SIngo Molnar lapic_cal_loops = -1; 724f62bae50SIngo Molnar 725f62bae50SIngo Molnar /* Let the interrupts run */ 726f62bae50SIngo Molnar local_irq_enable(); 727f62bae50SIngo Molnar 728f62bae50SIngo Molnar while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 729f62bae50SIngo Molnar cpu_relax(); 730f62bae50SIngo Molnar 731f62bae50SIngo Molnar /* Stop the lapic timer */ 732f62bae50SIngo Molnar lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); 733f62bae50SIngo Molnar 734f62bae50SIngo Molnar /* Jiffies delta */ 735f62bae50SIngo Molnar deltaj = lapic_cal_j2 - lapic_cal_j1; 736f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 737f62bae50SIngo Molnar 738f62bae50SIngo Molnar /* Check, if the jiffies result is consistent */ 739f62bae50SIngo Molnar if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 740f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 741f62bae50SIngo Molnar else 742f62bae50SIngo Molnar levt->features |= CLOCK_EVT_FEAT_DUMMY; 743f62bae50SIngo Molnar } else 744f62bae50SIngo Molnar local_irq_enable(); 745f62bae50SIngo Molnar 746f62bae50SIngo Molnar if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 747f62bae50SIngo Molnar pr_warning("APIC timer disabled due to verification failure\n"); 748f62bae50SIngo Molnar return -1; 749f62bae50SIngo Molnar } 750f62bae50SIngo Molnar 751f62bae50SIngo Molnar return 0; 752f62bae50SIngo Molnar } 753f62bae50SIngo Molnar 754f62bae50SIngo Molnar /* 755f62bae50SIngo Molnar * Setup the boot APIC 756f62bae50SIngo Molnar * 757f62bae50SIngo Molnar * Calibrate and verify the result. 758f62bae50SIngo Molnar */ 759f62bae50SIngo Molnar void __init setup_boot_APIC_clock(void) 760f62bae50SIngo Molnar { 761f62bae50SIngo Molnar /* 762f62bae50SIngo Molnar * The local apic timer can be disabled via the kernel 763f62bae50SIngo Molnar * commandline or from the CPU detection code. Register the lapic 764f62bae50SIngo Molnar * timer as a dummy clock event source on SMP systems, so the 765f62bae50SIngo Molnar * broadcast mechanism is used. On UP systems simply ignore it. 766f62bae50SIngo Molnar */ 767f62bae50SIngo Molnar if (disable_apic_timer) { 768f62bae50SIngo Molnar pr_info("Disabling APIC timer\n"); 769f62bae50SIngo Molnar /* No broadcast on UP ! */ 770f62bae50SIngo Molnar if (num_possible_cpus() > 1) { 771f62bae50SIngo Molnar lapic_clockevent.mult = 1; 772f62bae50SIngo Molnar setup_APIC_timer(); 773f62bae50SIngo Molnar } 774f62bae50SIngo Molnar return; 775f62bae50SIngo Molnar } 776f62bae50SIngo Molnar 777f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 778f62bae50SIngo Molnar "calibrating APIC timer ...\n"); 779f62bae50SIngo Molnar 780f62bae50SIngo Molnar if (calibrate_APIC_clock()) { 781f62bae50SIngo Molnar /* No broadcast on UP ! */ 782f62bae50SIngo Molnar if (num_possible_cpus() > 1) 783f62bae50SIngo Molnar setup_APIC_timer(); 784f62bae50SIngo Molnar return; 785f62bae50SIngo Molnar } 786f62bae50SIngo Molnar 787f62bae50SIngo Molnar /* 788f62bae50SIngo Molnar * If nmi_watchdog is set to IO_APIC, we need the 789f62bae50SIngo Molnar * PIT/HPET going. Otherwise register lapic as a dummy 790f62bae50SIngo Molnar * device. 791f62bae50SIngo Molnar */ 792f62bae50SIngo Molnar lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 793f62bae50SIngo Molnar 794f62bae50SIngo Molnar /* Setup the lapic or request the broadcast */ 795f62bae50SIngo Molnar setup_APIC_timer(); 796f62bae50SIngo Molnar } 797f62bae50SIngo Molnar 798f62bae50SIngo Molnar void __cpuinit setup_secondary_APIC_clock(void) 799f62bae50SIngo Molnar { 800f62bae50SIngo Molnar setup_APIC_timer(); 801f62bae50SIngo Molnar } 802f62bae50SIngo Molnar 803f62bae50SIngo Molnar /* 804f62bae50SIngo Molnar * The guts of the apic timer interrupt 805f62bae50SIngo Molnar */ 806f62bae50SIngo Molnar static void local_apic_timer_interrupt(void) 807f62bae50SIngo Molnar { 808f62bae50SIngo Molnar int cpu = smp_processor_id(); 809f62bae50SIngo Molnar struct clock_event_device *evt = &per_cpu(lapic_events, cpu); 810f62bae50SIngo Molnar 811f62bae50SIngo Molnar /* 812f62bae50SIngo Molnar * Normally we should not be here till LAPIC has been initialized but 813f62bae50SIngo Molnar * in some cases like kdump, its possible that there is a pending LAPIC 814f62bae50SIngo Molnar * timer interrupt from previous kernel's context and is delivered in 815f62bae50SIngo Molnar * new kernel the moment interrupts are enabled. 816f62bae50SIngo Molnar * 817f62bae50SIngo Molnar * Interrupts are enabled early and LAPIC is setup much later, hence 818f62bae50SIngo Molnar * its possible that when we get here evt->event_handler is NULL. 819f62bae50SIngo Molnar * Check for event_handler being NULL and discard the interrupt as 820f62bae50SIngo Molnar * spurious. 821f62bae50SIngo Molnar */ 822f62bae50SIngo Molnar if (!evt->event_handler) { 823f62bae50SIngo Molnar pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); 824f62bae50SIngo Molnar /* Switch it off */ 825f62bae50SIngo Molnar lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); 826f62bae50SIngo Molnar return; 827f62bae50SIngo Molnar } 828f62bae50SIngo Molnar 829f62bae50SIngo Molnar /* 830f62bae50SIngo Molnar * the NMI deadlock-detector uses this. 831f62bae50SIngo Molnar */ 832f62bae50SIngo Molnar inc_irq_stat(apic_timer_irqs); 833f62bae50SIngo Molnar 834f62bae50SIngo Molnar evt->event_handler(evt); 835f62bae50SIngo Molnar } 836f62bae50SIngo Molnar 837f62bae50SIngo Molnar /* 838f62bae50SIngo Molnar * Local APIC timer interrupt. This is the most natural way for doing 839f62bae50SIngo Molnar * local interrupts, but local timer interrupts can be emulated by 840f62bae50SIngo Molnar * broadcast interrupts too. [in case the hw doesn't support APIC timers] 841f62bae50SIngo Molnar * 842f62bae50SIngo Molnar * [ if a single-CPU system runs an SMP kernel then we call the local 843f62bae50SIngo Molnar * interrupt as well. Thus we cannot inline the local irq ... ] 844f62bae50SIngo Molnar */ 845f62bae50SIngo Molnar void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 846f62bae50SIngo Molnar { 847f62bae50SIngo Molnar struct pt_regs *old_regs = set_irq_regs(regs); 848f62bae50SIngo Molnar 849f62bae50SIngo Molnar /* 850f62bae50SIngo Molnar * NOTE! We'd better ACK the irq immediately, 851f62bae50SIngo Molnar * because timer handling can be slow. 852f62bae50SIngo Molnar */ 853f62bae50SIngo Molnar ack_APIC_irq(); 854f62bae50SIngo Molnar /* 855f62bae50SIngo Molnar * update_process_times() expects us to have done irq_enter(). 856f62bae50SIngo Molnar * Besides, if we don't timer interrupts ignore the global 857f62bae50SIngo Molnar * interrupt lock, which is the WrongThing (tm) to do. 858f62bae50SIngo Molnar */ 859f62bae50SIngo Molnar exit_idle(); 860f62bae50SIngo Molnar irq_enter(); 861f62bae50SIngo Molnar local_apic_timer_interrupt(); 862f62bae50SIngo Molnar irq_exit(); 863f62bae50SIngo Molnar 864f62bae50SIngo Molnar set_irq_regs(old_regs); 865f62bae50SIngo Molnar } 866f62bae50SIngo Molnar 867f62bae50SIngo Molnar int setup_profiling_timer(unsigned int multiplier) 868f62bae50SIngo Molnar { 869f62bae50SIngo Molnar return -EINVAL; 870f62bae50SIngo Molnar } 871f62bae50SIngo Molnar 872f62bae50SIngo Molnar /* 873f62bae50SIngo Molnar * Local APIC start and shutdown 874f62bae50SIngo Molnar */ 875f62bae50SIngo Molnar 876f62bae50SIngo Molnar /** 877f62bae50SIngo Molnar * clear_local_APIC - shutdown the local APIC 878f62bae50SIngo Molnar * 879f62bae50SIngo Molnar * This is called, when a CPU is disabled and before rebooting, so the state of 880f62bae50SIngo Molnar * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 881f62bae50SIngo Molnar * leftovers during boot. 882f62bae50SIngo Molnar */ 883f62bae50SIngo Molnar void clear_local_APIC(void) 884f62bae50SIngo Molnar { 885f62bae50SIngo Molnar int maxlvt; 886f62bae50SIngo Molnar u32 v; 887f62bae50SIngo Molnar 888f62bae50SIngo Molnar /* APIC hasn't been mapped yet */ 889fc1edaf9SSuresh Siddha if (!x2apic_mode && !apic_phys) 890f62bae50SIngo Molnar return; 891f62bae50SIngo Molnar 892f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 893f62bae50SIngo Molnar /* 894f62bae50SIngo Molnar * Masking an LVT entry can trigger a local APIC error 895f62bae50SIngo Molnar * if the vector is zero. Mask LVTERR first to prevent this. 896f62bae50SIngo Molnar */ 897f62bae50SIngo Molnar if (maxlvt >= 3) { 898f62bae50SIngo Molnar v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 899f62bae50SIngo Molnar apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 900f62bae50SIngo Molnar } 901f62bae50SIngo Molnar /* 902f62bae50SIngo Molnar * Careful: we have to set masks only first to deassert 903f62bae50SIngo Molnar * any level-triggered sources. 904f62bae50SIngo Molnar */ 905f62bae50SIngo Molnar v = apic_read(APIC_LVTT); 906f62bae50SIngo Molnar apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 907f62bae50SIngo Molnar v = apic_read(APIC_LVT0); 908f62bae50SIngo Molnar apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 909f62bae50SIngo Molnar v = apic_read(APIC_LVT1); 910f62bae50SIngo Molnar apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 911f62bae50SIngo Molnar if (maxlvt >= 4) { 912f62bae50SIngo Molnar v = apic_read(APIC_LVTPC); 913f62bae50SIngo Molnar apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 914f62bae50SIngo Molnar } 915f62bae50SIngo Molnar 916f62bae50SIngo Molnar /* lets not touch this if we didn't frob it */ 9174efc0670SAndi Kleen #ifdef CONFIG_X86_THERMAL_VECTOR 918f62bae50SIngo Molnar if (maxlvt >= 5) { 919f62bae50SIngo Molnar v = apic_read(APIC_LVTTHMR); 920f62bae50SIngo Molnar apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 921f62bae50SIngo Molnar } 922f62bae50SIngo Molnar #endif 923638bee71SH. Peter Anvin #ifdef CONFIG_X86_MCE_INTEL 924638bee71SH. Peter Anvin if (maxlvt >= 6) { 925638bee71SH. Peter Anvin v = apic_read(APIC_LVTCMCI); 926638bee71SH. Peter Anvin if (!(v & APIC_LVT_MASKED)) 927638bee71SH. Peter Anvin apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 928638bee71SH. Peter Anvin } 929638bee71SH. Peter Anvin #endif 930638bee71SH. Peter Anvin 931f62bae50SIngo Molnar /* 932f62bae50SIngo Molnar * Clean APIC state for other OSs: 933f62bae50SIngo Molnar */ 934f62bae50SIngo Molnar apic_write(APIC_LVTT, APIC_LVT_MASKED); 935f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_LVT_MASKED); 936f62bae50SIngo Molnar apic_write(APIC_LVT1, APIC_LVT_MASKED); 937f62bae50SIngo Molnar if (maxlvt >= 3) 938f62bae50SIngo Molnar apic_write(APIC_LVTERR, APIC_LVT_MASKED); 939f62bae50SIngo Molnar if (maxlvt >= 4) 940f62bae50SIngo Molnar apic_write(APIC_LVTPC, APIC_LVT_MASKED); 941f62bae50SIngo Molnar 942f62bae50SIngo Molnar /* Integrated APIC (!82489DX) ? */ 943f62bae50SIngo Molnar if (lapic_is_integrated()) { 944f62bae50SIngo Molnar if (maxlvt > 3) 945f62bae50SIngo Molnar /* Clear ESR due to Pentium errata 3AP and 11AP */ 946f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 947f62bae50SIngo Molnar apic_read(APIC_ESR); 948f62bae50SIngo Molnar } 949f62bae50SIngo Molnar } 950f62bae50SIngo Molnar 951f62bae50SIngo Molnar /** 952f62bae50SIngo Molnar * disable_local_APIC - clear and disable the local APIC 953f62bae50SIngo Molnar */ 954f62bae50SIngo Molnar void disable_local_APIC(void) 955f62bae50SIngo Molnar { 956f62bae50SIngo Molnar unsigned int value; 957f62bae50SIngo Molnar 958f62bae50SIngo Molnar /* APIC hasn't been mapped yet */ 959fd19dce7SYinghai Lu if (!x2apic_mode && !apic_phys) 960f62bae50SIngo Molnar return; 961f62bae50SIngo Molnar 962f62bae50SIngo Molnar clear_local_APIC(); 963f62bae50SIngo Molnar 964f62bae50SIngo Molnar /* 965f62bae50SIngo Molnar * Disable APIC (implies clearing of registers 966f62bae50SIngo Molnar * for 82489DX!). 967f62bae50SIngo Molnar */ 968f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 969f62bae50SIngo Molnar value &= ~APIC_SPIV_APIC_ENABLED; 970f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 971f62bae50SIngo Molnar 972f62bae50SIngo Molnar #ifdef CONFIG_X86_32 973f62bae50SIngo Molnar /* 974f62bae50SIngo Molnar * When LAPIC was disabled by the BIOS and enabled by the kernel, 975f62bae50SIngo Molnar * restore the disabled state. 976f62bae50SIngo Molnar */ 977f62bae50SIngo Molnar if (enabled_via_apicbase) { 978f62bae50SIngo Molnar unsigned int l, h; 979f62bae50SIngo Molnar 980f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, l, h); 981f62bae50SIngo Molnar l &= ~MSR_IA32_APICBASE_ENABLE; 982f62bae50SIngo Molnar wrmsr(MSR_IA32_APICBASE, l, h); 983f62bae50SIngo Molnar } 984f62bae50SIngo Molnar #endif 985f62bae50SIngo Molnar } 986f62bae50SIngo Molnar 987f62bae50SIngo Molnar /* 988f62bae50SIngo Molnar * If Linux enabled the LAPIC against the BIOS default disable it down before 989f62bae50SIngo Molnar * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 990f62bae50SIngo Molnar * not power-off. Additionally clear all LVT entries before disable_local_APIC 991f62bae50SIngo Molnar * for the case where Linux didn't enable the LAPIC. 992f62bae50SIngo Molnar */ 993f62bae50SIngo Molnar void lapic_shutdown(void) 994f62bae50SIngo Molnar { 995f62bae50SIngo Molnar unsigned long flags; 996f62bae50SIngo Molnar 9978312136fSCyrill Gorcunov if (!cpu_has_apic && !apic_from_smp_config()) 998f62bae50SIngo Molnar return; 999f62bae50SIngo Molnar 1000f62bae50SIngo Molnar local_irq_save(flags); 1001f62bae50SIngo Molnar 1002f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1003f62bae50SIngo Molnar if (!enabled_via_apicbase) 1004f62bae50SIngo Molnar clear_local_APIC(); 1005f62bae50SIngo Molnar else 1006f62bae50SIngo Molnar #endif 1007f62bae50SIngo Molnar disable_local_APIC(); 1008f62bae50SIngo Molnar 1009f62bae50SIngo Molnar 1010f62bae50SIngo Molnar local_irq_restore(flags); 1011f62bae50SIngo Molnar } 1012f62bae50SIngo Molnar 1013f62bae50SIngo Molnar /* 1014f62bae50SIngo Molnar * This is to verify that we're looking at a real local APIC. 1015f62bae50SIngo Molnar * Check these against your board if the CPUs aren't getting 1016f62bae50SIngo Molnar * started for no apparent reason. 1017f62bae50SIngo Molnar */ 1018f62bae50SIngo Molnar int __init verify_local_APIC(void) 1019f62bae50SIngo Molnar { 1020f62bae50SIngo Molnar unsigned int reg0, reg1; 1021f62bae50SIngo Molnar 1022f62bae50SIngo Molnar /* 1023f62bae50SIngo Molnar * The version register is read-only in a real APIC. 1024f62bae50SIngo Molnar */ 1025f62bae50SIngo Molnar reg0 = apic_read(APIC_LVR); 1026f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); 1027f62bae50SIngo Molnar apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); 1028f62bae50SIngo Molnar reg1 = apic_read(APIC_LVR); 1029f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); 1030f62bae50SIngo Molnar 1031f62bae50SIngo Molnar /* 1032f62bae50SIngo Molnar * The two version reads above should print the same 1033f62bae50SIngo Molnar * numbers. If the second one is different, then we 1034f62bae50SIngo Molnar * poke at a non-APIC. 1035f62bae50SIngo Molnar */ 1036f62bae50SIngo Molnar if (reg1 != reg0) 1037f62bae50SIngo Molnar return 0; 1038f62bae50SIngo Molnar 1039f62bae50SIngo Molnar /* 1040f62bae50SIngo Molnar * Check if the version looks reasonably. 1041f62bae50SIngo Molnar */ 1042f62bae50SIngo Molnar reg1 = GET_APIC_VERSION(reg0); 1043f62bae50SIngo Molnar if (reg1 == 0x00 || reg1 == 0xff) 1044f62bae50SIngo Molnar return 0; 1045f62bae50SIngo Molnar reg1 = lapic_get_maxlvt(); 1046f62bae50SIngo Molnar if (reg1 < 0x02 || reg1 == 0xff) 1047f62bae50SIngo Molnar return 0; 1048f62bae50SIngo Molnar 1049f62bae50SIngo Molnar /* 1050f62bae50SIngo Molnar * The ID register is read/write in a real APIC. 1051f62bae50SIngo Molnar */ 1052f62bae50SIngo Molnar reg0 = apic_read(APIC_ID); 1053f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); 1054f62bae50SIngo Molnar apic_write(APIC_ID, reg0 ^ apic->apic_id_mask); 1055f62bae50SIngo Molnar reg1 = apic_read(APIC_ID); 1056f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); 1057f62bae50SIngo Molnar apic_write(APIC_ID, reg0); 1058f62bae50SIngo Molnar if (reg1 != (reg0 ^ apic->apic_id_mask)) 1059f62bae50SIngo Molnar return 0; 1060f62bae50SIngo Molnar 1061f62bae50SIngo Molnar /* 1062f62bae50SIngo Molnar * The next two are just to see if we have sane values. 1063f62bae50SIngo Molnar * They're only really relevant if we're in Virtual Wire 1064f62bae50SIngo Molnar * compatibility mode, but most boxes are anymore. 1065f62bae50SIngo Molnar */ 1066f62bae50SIngo Molnar reg0 = apic_read(APIC_LVT0); 1067f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); 1068f62bae50SIngo Molnar reg1 = apic_read(APIC_LVT1); 1069f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); 1070f62bae50SIngo Molnar 1071f62bae50SIngo Molnar return 1; 1072f62bae50SIngo Molnar } 1073f62bae50SIngo Molnar 1074f62bae50SIngo Molnar /** 1075f62bae50SIngo Molnar * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1076f62bae50SIngo Molnar */ 1077f62bae50SIngo Molnar void __init sync_Arb_IDs(void) 1078f62bae50SIngo Molnar { 1079f62bae50SIngo Molnar /* 1080f62bae50SIngo Molnar * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1081f62bae50SIngo Molnar * needed on AMD. 1082f62bae50SIngo Molnar */ 1083f62bae50SIngo Molnar if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1084f62bae50SIngo Molnar return; 1085f62bae50SIngo Molnar 1086f62bae50SIngo Molnar /* 1087f62bae50SIngo Molnar * Wait for idle. 1088f62bae50SIngo Molnar */ 1089f62bae50SIngo Molnar apic_wait_icr_idle(); 1090f62bae50SIngo Molnar 1091f62bae50SIngo Molnar apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1092f62bae50SIngo Molnar apic_write(APIC_ICR, APIC_DEST_ALLINC | 1093f62bae50SIngo Molnar APIC_INT_LEVELTRIG | APIC_DM_INIT); 1094f62bae50SIngo Molnar } 1095f62bae50SIngo Molnar 1096f62bae50SIngo Molnar /* 1097f62bae50SIngo Molnar * An initial setup of the virtual wire mode. 1098f62bae50SIngo Molnar */ 1099f62bae50SIngo Molnar void __init init_bsp_APIC(void) 1100f62bae50SIngo Molnar { 1101f62bae50SIngo Molnar unsigned int value; 1102f62bae50SIngo Molnar 1103f62bae50SIngo Molnar /* 1104f62bae50SIngo Molnar * Don't do the setup now if we have a SMP BIOS as the 1105f62bae50SIngo Molnar * through-I/O-APIC virtual wire mode might be active. 1106f62bae50SIngo Molnar */ 1107f62bae50SIngo Molnar if (smp_found_config || !cpu_has_apic) 1108f62bae50SIngo Molnar return; 1109f62bae50SIngo Molnar 1110f62bae50SIngo Molnar /* 1111f62bae50SIngo Molnar * Do not trust the local APIC being empty at bootup. 1112f62bae50SIngo Molnar */ 1113f62bae50SIngo Molnar clear_local_APIC(); 1114f62bae50SIngo Molnar 1115f62bae50SIngo Molnar /* 1116f62bae50SIngo Molnar * Enable APIC. 1117f62bae50SIngo Molnar */ 1118f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 1119f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 1120f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 1121f62bae50SIngo Molnar 1122f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1123f62bae50SIngo Molnar /* This bit is reserved on P4/Xeon and should be cleared */ 1124f62bae50SIngo Molnar if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1125f62bae50SIngo Molnar (boot_cpu_data.x86 == 15)) 1126f62bae50SIngo Molnar value &= ~APIC_SPIV_FOCUS_DISABLED; 1127f62bae50SIngo Molnar else 1128f62bae50SIngo Molnar #endif 1129f62bae50SIngo Molnar value |= APIC_SPIV_FOCUS_DISABLED; 1130f62bae50SIngo Molnar value |= SPURIOUS_APIC_VECTOR; 1131f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 1132f62bae50SIngo Molnar 1133f62bae50SIngo Molnar /* 1134f62bae50SIngo Molnar * Set up the virtual wire mode. 1135f62bae50SIngo Molnar */ 1136f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_DM_EXTINT); 1137f62bae50SIngo Molnar value = APIC_DM_NMI; 1138f62bae50SIngo Molnar if (!lapic_is_integrated()) /* 82489DX */ 1139f62bae50SIngo Molnar value |= APIC_LVT_LEVEL_TRIGGER; 1140f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 1141f62bae50SIngo Molnar } 1142f62bae50SIngo Molnar 1143f62bae50SIngo Molnar static void __cpuinit lapic_setup_esr(void) 1144f62bae50SIngo Molnar { 1145f62bae50SIngo Molnar unsigned int oldvalue, value, maxlvt; 1146f62bae50SIngo Molnar 1147f62bae50SIngo Molnar if (!lapic_is_integrated()) { 1148f62bae50SIngo Molnar pr_info("No ESR for 82489DX.\n"); 1149f62bae50SIngo Molnar return; 1150f62bae50SIngo Molnar } 1151f62bae50SIngo Molnar 1152f62bae50SIngo Molnar if (apic->disable_esr) { 1153f62bae50SIngo Molnar /* 1154f62bae50SIngo Molnar * Something untraceable is creating bad interrupts on 1155f62bae50SIngo Molnar * secondary quads ... for the moment, just leave the 1156f62bae50SIngo Molnar * ESR disabled - we can't do anything useful with the 1157f62bae50SIngo Molnar * errors anyway - mbligh 1158f62bae50SIngo Molnar */ 1159f62bae50SIngo Molnar pr_info("Leaving ESR disabled.\n"); 1160f62bae50SIngo Molnar return; 1161f62bae50SIngo Molnar } 1162f62bae50SIngo Molnar 1163f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 1164f62bae50SIngo Molnar if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1165f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1166f62bae50SIngo Molnar oldvalue = apic_read(APIC_ESR); 1167f62bae50SIngo Molnar 1168f62bae50SIngo Molnar /* enables sending errors */ 1169f62bae50SIngo Molnar value = ERROR_APIC_VECTOR; 1170f62bae50SIngo Molnar apic_write(APIC_LVTERR, value); 1171f62bae50SIngo Molnar 1172f62bae50SIngo Molnar /* 1173f62bae50SIngo Molnar * spec says clear errors after enabling vector. 1174f62bae50SIngo Molnar */ 1175f62bae50SIngo Molnar if (maxlvt > 3) 1176f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1177f62bae50SIngo Molnar value = apic_read(APIC_ESR); 1178f62bae50SIngo Molnar if (value != oldvalue) 1179f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "ESR value before enabling " 1180f62bae50SIngo Molnar "vector: 0x%08x after: 0x%08x\n", 1181f62bae50SIngo Molnar oldvalue, value); 1182f62bae50SIngo Molnar } 1183f62bae50SIngo Molnar 1184f62bae50SIngo Molnar /** 1185f62bae50SIngo Molnar * setup_local_APIC - setup the local APIC 11860aa002feSTejun Heo * 11870aa002feSTejun Heo * Used to setup local APIC while initializing BSP or bringin up APs. 11880aa002feSTejun Heo * Always called with preemption disabled. 1189f62bae50SIngo Molnar */ 1190f62bae50SIngo Molnar void __cpuinit setup_local_APIC(void) 1191f62bae50SIngo Molnar { 11920aa002feSTejun Heo int cpu = smp_processor_id(); 11938c3ba8d0SKerstin Jonsson unsigned int value, queued; 11948c3ba8d0SKerstin Jonsson int i, j, acked = 0; 11958c3ba8d0SKerstin Jonsson unsigned long long tsc = 0, ntsc; 11968c3ba8d0SKerstin Jonsson long long max_loops = cpu_khz; 11978c3ba8d0SKerstin Jonsson 11988c3ba8d0SKerstin Jonsson if (cpu_has_tsc) 11998c3ba8d0SKerstin Jonsson rdtscll(tsc); 1200f62bae50SIngo Molnar 1201f62bae50SIngo Molnar if (disable_apic) { 12027167d08eSHenrik Kretzschmar disable_ioapic_support(); 1203f62bae50SIngo Molnar return; 1204f62bae50SIngo Molnar } 1205f62bae50SIngo Molnar 1206f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1207f62bae50SIngo Molnar /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1208f62bae50SIngo Molnar if (lapic_is_integrated() && apic->disable_esr) { 1209f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1210f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1211f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1212f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1213f62bae50SIngo Molnar } 1214f62bae50SIngo Molnar #endif 1215cdd6c482SIngo Molnar perf_events_lapic_init(); 1216f62bae50SIngo Molnar 1217f62bae50SIngo Molnar /* 1218f62bae50SIngo Molnar * Double-check whether this APIC is really registered. 1219f62bae50SIngo Molnar * This is meaningless in clustered apic mode, so we skip it. 1220f62bae50SIngo Molnar */ 1221c2777f98SDaniel Walker BUG_ON(!apic->apic_id_registered()); 1222f62bae50SIngo Molnar 1223f62bae50SIngo Molnar /* 1224f62bae50SIngo Molnar * Intel recommends to set DFR, LDR and TPR before enabling 1225f62bae50SIngo Molnar * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1226f62bae50SIngo Molnar * document number 292116). So here it goes... 1227f62bae50SIngo Molnar */ 1228f62bae50SIngo Molnar apic->init_apic_ldr(); 1229f62bae50SIngo Molnar 12306f802c4bSTejun Heo #ifdef CONFIG_X86_32 12316f802c4bSTejun Heo /* 1232acb8bc09STejun Heo * APIC LDR is initialized. If logical_apicid mapping was 1233acb8bc09STejun Heo * initialized during get_smp_config(), make sure it matches the 1234acb8bc09STejun Heo * actual value. 12356f802c4bSTejun Heo */ 1236acb8bc09STejun Heo i = early_per_cpu(x86_cpu_to_logical_apicid, cpu); 1237acb8bc09STejun Heo WARN_ON(i != BAD_APICID && i != logical_smp_processor_id()); 1238acb8bc09STejun Heo /* always use the value from LDR */ 12396f802c4bSTejun Heo early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 12406f802c4bSTejun Heo logical_smp_processor_id(); 1241c4b90c11STejun Heo 1242c4b90c11STejun Heo /* 1243c4b90c11STejun Heo * Some NUMA implementations (NUMAQ) don't initialize apicid to 1244c4b90c11STejun Heo * node mapping during NUMA init. Now that logical apicid is 1245c4b90c11STejun Heo * guaranteed to be known, give it another chance. This is already 1246c4b90c11STejun Heo * a bit too late - percpu allocation has already happened without 1247c4b90c11STejun Heo * proper NUMA affinity. 1248c4b90c11STejun Heo */ 124984914ed0STejun Heo if (apic->x86_32_numa_cpu_node) 1250c4b90c11STejun Heo set_apicid_to_node(early_per_cpu(x86_cpu_to_apicid, cpu), 1251c4b90c11STejun Heo apic->x86_32_numa_cpu_node(cpu)); 12526f802c4bSTejun Heo #endif 12536f802c4bSTejun Heo 1254f62bae50SIngo Molnar /* 1255f62bae50SIngo Molnar * Set Task Priority to 'accept all'. We never change this 1256f62bae50SIngo Molnar * later on. 1257f62bae50SIngo Molnar */ 1258f62bae50SIngo Molnar value = apic_read(APIC_TASKPRI); 1259f62bae50SIngo Molnar value &= ~APIC_TPRI_MASK; 1260f62bae50SIngo Molnar apic_write(APIC_TASKPRI, value); 1261f62bae50SIngo Molnar 1262f62bae50SIngo Molnar /* 1263f62bae50SIngo Molnar * After a crash, we no longer service the interrupts and a pending 1264f62bae50SIngo Molnar * interrupt from previous kernel might still have ISR bit set. 1265f62bae50SIngo Molnar * 1266f62bae50SIngo Molnar * Most probably by now CPU has serviced that pending interrupt and 1267f62bae50SIngo Molnar * it might not have done the ack_APIC_irq() because it thought, 1268f62bae50SIngo Molnar * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1269f62bae50SIngo Molnar * does not clear the ISR bit and cpu thinks it has already serivced 1270f62bae50SIngo Molnar * the interrupt. Hence a vector might get locked. It was noticed 1271f62bae50SIngo Molnar * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1272f62bae50SIngo Molnar */ 12738c3ba8d0SKerstin Jonsson do { 12748c3ba8d0SKerstin Jonsson queued = 0; 12758c3ba8d0SKerstin Jonsson for (i = APIC_ISR_NR - 1; i >= 0; i--) 12768c3ba8d0SKerstin Jonsson queued |= apic_read(APIC_IRR + i*0x10); 12778c3ba8d0SKerstin Jonsson 1278f62bae50SIngo Molnar for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1279f62bae50SIngo Molnar value = apic_read(APIC_ISR + i*0x10); 1280f62bae50SIngo Molnar for (j = 31; j >= 0; j--) { 12818c3ba8d0SKerstin Jonsson if (value & (1<<j)) { 1282f62bae50SIngo Molnar ack_APIC_irq(); 12838c3ba8d0SKerstin Jonsson acked++; 1284f62bae50SIngo Molnar } 1285f62bae50SIngo Molnar } 12868c3ba8d0SKerstin Jonsson } 12878c3ba8d0SKerstin Jonsson if (acked > 256) { 12888c3ba8d0SKerstin Jonsson printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", 12898c3ba8d0SKerstin Jonsson acked); 12908c3ba8d0SKerstin Jonsson break; 12918c3ba8d0SKerstin Jonsson } 12928c3ba8d0SKerstin Jonsson if (cpu_has_tsc) { 12938c3ba8d0SKerstin Jonsson rdtscll(ntsc); 12948c3ba8d0SKerstin Jonsson max_loops = (cpu_khz << 10) - (ntsc - tsc); 12958c3ba8d0SKerstin Jonsson } else 12968c3ba8d0SKerstin Jonsson max_loops--; 12978c3ba8d0SKerstin Jonsson } while (queued && max_loops > 0); 12988c3ba8d0SKerstin Jonsson WARN_ON(max_loops <= 0); 1299f62bae50SIngo Molnar 1300f62bae50SIngo Molnar /* 1301f62bae50SIngo Molnar * Now that we are all set up, enable the APIC 1302f62bae50SIngo Molnar */ 1303f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 1304f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 1305f62bae50SIngo Molnar /* 1306f62bae50SIngo Molnar * Enable APIC 1307f62bae50SIngo Molnar */ 1308f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 1309f62bae50SIngo Molnar 1310f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1311f62bae50SIngo Molnar /* 1312f62bae50SIngo Molnar * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1313f62bae50SIngo Molnar * certain networking cards. If high frequency interrupts are 1314f62bae50SIngo Molnar * happening on a particular IOAPIC pin, plus the IOAPIC routing 1315f62bae50SIngo Molnar * entry is masked/unmasked at a high rate as well then sooner or 1316f62bae50SIngo Molnar * later IOAPIC line gets 'stuck', no more interrupts are received 1317f62bae50SIngo Molnar * from the device. If focus CPU is disabled then the hang goes 1318f62bae50SIngo Molnar * away, oh well :-( 1319f62bae50SIngo Molnar * 1320f62bae50SIngo Molnar * [ This bug can be reproduced easily with a level-triggered 1321f62bae50SIngo Molnar * PCI Ne2000 networking cards and PII/PIII processors, dual 1322f62bae50SIngo Molnar * BX chipset. ] 1323f62bae50SIngo Molnar */ 1324f62bae50SIngo Molnar /* 1325f62bae50SIngo Molnar * Actually disabling the focus CPU check just makes the hang less 1326f62bae50SIngo Molnar * frequent as it makes the interrupt distributon model be more 1327f62bae50SIngo Molnar * like LRU than MRU (the short-term load is more even across CPUs). 1328f62bae50SIngo Molnar * See also the comment in end_level_ioapic_irq(). --macro 1329f62bae50SIngo Molnar */ 1330f62bae50SIngo Molnar 1331f62bae50SIngo Molnar /* 1332f62bae50SIngo Molnar * - enable focus processor (bit==0) 1333f62bae50SIngo Molnar * - 64bit mode always use processor focus 1334f62bae50SIngo Molnar * so no need to set it 1335f62bae50SIngo Molnar */ 1336f62bae50SIngo Molnar value &= ~APIC_SPIV_FOCUS_DISABLED; 1337f62bae50SIngo Molnar #endif 1338f62bae50SIngo Molnar 1339f62bae50SIngo Molnar /* 1340f62bae50SIngo Molnar * Set spurious IRQ vector 1341f62bae50SIngo Molnar */ 1342f62bae50SIngo Molnar value |= SPURIOUS_APIC_VECTOR; 1343f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 1344f62bae50SIngo Molnar 1345f62bae50SIngo Molnar /* 1346f62bae50SIngo Molnar * Set up LVT0, LVT1: 1347f62bae50SIngo Molnar * 1348f62bae50SIngo Molnar * set up through-local-APIC on the BP's LINT0. This is not 1349f62bae50SIngo Molnar * strictly necessary in pure symmetric-IO mode, but sometimes 1350f62bae50SIngo Molnar * we delegate interrupts to the 8259A. 1351f62bae50SIngo Molnar */ 1352f62bae50SIngo Molnar /* 1353f62bae50SIngo Molnar * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1354f62bae50SIngo Molnar */ 1355f62bae50SIngo Molnar value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 13560aa002feSTejun Heo if (!cpu && (pic_mode || !value)) { 1357f62bae50SIngo Molnar value = APIC_DM_EXTINT; 13580aa002feSTejun Heo apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1359f62bae50SIngo Molnar } else { 1360f62bae50SIngo Molnar value = APIC_DM_EXTINT | APIC_LVT_MASKED; 13610aa002feSTejun Heo apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1362f62bae50SIngo Molnar } 1363f62bae50SIngo Molnar apic_write(APIC_LVT0, value); 1364f62bae50SIngo Molnar 1365f62bae50SIngo Molnar /* 1366f62bae50SIngo Molnar * only the BP should see the LINT1 NMI signal, obviously. 1367f62bae50SIngo Molnar */ 13680aa002feSTejun Heo if (!cpu) 1369f62bae50SIngo Molnar value = APIC_DM_NMI; 1370f62bae50SIngo Molnar else 1371f62bae50SIngo Molnar value = APIC_DM_NMI | APIC_LVT_MASKED; 1372f62bae50SIngo Molnar if (!lapic_is_integrated()) /* 82489DX */ 1373f62bae50SIngo Molnar value |= APIC_LVT_LEVEL_TRIGGER; 1374f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 1375f62bae50SIngo Molnar 1376638bee71SH. Peter Anvin #ifdef CONFIG_X86_MCE_INTEL 1377638bee71SH. Peter Anvin /* Recheck CMCI information after local APIC is up on CPU #0 */ 13780aa002feSTejun Heo if (!cpu) 1379638bee71SH. Peter Anvin cmci_recheck(); 1380638bee71SH. Peter Anvin #endif 1381f62bae50SIngo Molnar } 1382f62bae50SIngo Molnar 1383f62bae50SIngo Molnar void __cpuinit end_local_APIC_setup(void) 1384f62bae50SIngo Molnar { 1385f62bae50SIngo Molnar lapic_setup_esr(); 1386f62bae50SIngo Molnar 1387f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1388f62bae50SIngo Molnar { 1389f62bae50SIngo Molnar unsigned int value; 1390f62bae50SIngo Molnar /* Disable the local apic timer */ 1391f62bae50SIngo Molnar value = apic_read(APIC_LVTT); 1392f62bae50SIngo Molnar value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1393f62bae50SIngo Molnar apic_write(APIC_LVTT, value); 1394f62bae50SIngo Molnar } 1395f62bae50SIngo Molnar #endif 1396f62bae50SIngo Molnar 1397f62bae50SIngo Molnar apic_pm_activate(); 13982fb270f3SJan Beulich } 13992fb270f3SJan Beulich 14002fb270f3SJan Beulich void __init bsp_end_local_APIC_setup(void) 14012fb270f3SJan Beulich { 14022fb270f3SJan Beulich end_local_APIC_setup(); 14037f7fbf45SKenji Kaneshige 14047f7fbf45SKenji Kaneshige /* 14057f7fbf45SKenji Kaneshige * Now that local APIC setup is completed for BP, configure the fault 14067f7fbf45SKenji Kaneshige * handling for interrupt remapping. 14077f7fbf45SKenji Kaneshige */ 14082fb270f3SJan Beulich if (intr_remapping_enabled) 14097f7fbf45SKenji Kaneshige enable_drhd_fault_handling(); 14107f7fbf45SKenji Kaneshige 1411f62bae50SIngo Molnar } 1412f62bae50SIngo Molnar 1413f62bae50SIngo Molnar #ifdef CONFIG_X86_X2APIC 1414f62bae50SIngo Molnar void check_x2apic(void) 1415f62bae50SIngo Molnar { 1416ef1f87aaSSuresh Siddha if (x2apic_enabled()) { 1417f62bae50SIngo Molnar pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); 1418fc1edaf9SSuresh Siddha x2apic_preenabled = x2apic_mode = 1; 1419f62bae50SIngo Molnar } 1420f62bae50SIngo Molnar } 1421f62bae50SIngo Molnar 1422f62bae50SIngo Molnar void enable_x2apic(void) 1423f62bae50SIngo Molnar { 1424f62bae50SIngo Molnar int msr, msr2; 1425f62bae50SIngo Molnar 1426fc1edaf9SSuresh Siddha if (!x2apic_mode) 1427f62bae50SIngo Molnar return; 1428f62bae50SIngo Molnar 1429f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, msr, msr2); 1430f62bae50SIngo Molnar if (!(msr & X2APIC_ENABLE)) { 1431450b1e8dSMike Travis printk_once(KERN_INFO "Enabling x2apic\n"); 143225970852SNaga Chumbalkar wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, msr2); 1433f62bae50SIngo Molnar } 1434f62bae50SIngo Molnar } 143593758238SWeidong Han #endif /* CONFIG_X86_X2APIC */ 1436f62bae50SIngo Molnar 1437ce69a784SGleb Natapov int __init enable_IR(void) 1438f62bae50SIngo Molnar { 1439f62bae50SIngo Molnar #ifdef CONFIG_INTR_REMAP 144093758238SWeidong Han if (!intr_remapping_supported()) { 144193758238SWeidong Han pr_debug("intr-remapping not supported\n"); 1442ce69a784SGleb Natapov return 0; 144393758238SWeidong Han } 144493758238SWeidong Han 144593758238SWeidong Han if (!x2apic_preenabled && skip_ioapic_setup) { 144693758238SWeidong Han pr_info("Skipped enabling intr-remap because of skipping " 144793758238SWeidong Han "io-apic setup\n"); 1448ce69a784SGleb Natapov return 0; 1449f62bae50SIngo Molnar } 1450f62bae50SIngo Molnar 1451ce69a784SGleb Natapov if (enable_intr_remapping(x2apic_supported())) 1452ce69a784SGleb Natapov return 0; 1453ce69a784SGleb Natapov 1454ce69a784SGleb Natapov pr_info("Enabled Interrupt-remapping\n"); 1455ce69a784SGleb Natapov 1456ce69a784SGleb Natapov return 1; 1457ce69a784SGleb Natapov 1458ce69a784SGleb Natapov #endif 1459ce69a784SGleb Natapov return 0; 1460ce69a784SGleb Natapov } 1461ce69a784SGleb Natapov 1462ce69a784SGleb Natapov void __init enable_IR_x2apic(void) 1463ce69a784SGleb Natapov { 1464ce69a784SGleb Natapov unsigned long flags; 1465ce69a784SGleb Natapov int ret, x2apic_enabled = 0; 1466e670761fSYinghai Lu int dmar_table_init_ret; 1467b7f42ab2SYinghai Lu 1468b7f42ab2SYinghai Lu dmar_table_init_ret = dmar_table_init(); 1469e670761fSYinghai Lu if (dmar_table_init_ret && !x2apic_supported()) 1470e670761fSYinghai Lu return; 1471ce69a784SGleb Natapov 147231dce14aSSuresh Siddha ret = save_ioapic_entries(); 1473f62bae50SIngo Molnar if (ret) { 1474f62bae50SIngo Molnar pr_info("Saving IO-APIC state failed: %d\n", ret); 1475ce69a784SGleb Natapov goto out; 1476f62bae50SIngo Molnar } 1477f62bae50SIngo Molnar 147805c3dc2cSSuresh Siddha local_irq_save(flags); 1479b81bb373SJacob Pan legacy_pic->mask_all(); 148031dce14aSSuresh Siddha mask_ioapic_entries(); 148105c3dc2cSSuresh Siddha 1482b7f42ab2SYinghai Lu if (dmar_table_init_ret) 1483b7f42ab2SYinghai Lu ret = 0; 1484b7f42ab2SYinghai Lu else 1485ce69a784SGleb Natapov ret = enable_IR(); 1486b7f42ab2SYinghai Lu 1487ce69a784SGleb Natapov if (!ret) { 1488ce69a784SGleb Natapov /* IR is required if there is APIC ID > 255 even when running 1489ce69a784SGleb Natapov * under KVM 1490ce69a784SGleb Natapov */ 14912904ed8dSSheng Yang if (max_physical_apicid > 255 || 14922904ed8dSSheng Yang !hypervisor_x2apic_available()) 1493ce69a784SGleb Natapov goto nox2apic; 1494ce69a784SGleb Natapov /* 1495ce69a784SGleb Natapov * without IR all CPUs can be addressed by IOAPIC/MSI 1496ce69a784SGleb Natapov * only in physical mode 1497ce69a784SGleb Natapov */ 1498ce69a784SGleb Natapov x2apic_force_phys(); 1499ce69a784SGleb Natapov } 1500f62bae50SIngo Molnar 1501ce69a784SGleb Natapov x2apic_enabled = 1; 150293758238SWeidong Han 1503fc1edaf9SSuresh Siddha if (x2apic_supported() && !x2apic_mode) { 1504fc1edaf9SSuresh Siddha x2apic_mode = 1; 1505f62bae50SIngo Molnar enable_x2apic(); 150693758238SWeidong Han pr_info("Enabled x2apic\n"); 1507f62bae50SIngo Molnar } 1508f62bae50SIngo Molnar 1509ce69a784SGleb Natapov nox2apic: 1510ce69a784SGleb Natapov if (!ret) /* IR enabling failed */ 151131dce14aSSuresh Siddha restore_ioapic_entries(); 1512b81bb373SJacob Pan legacy_pic->restore_mask(); 1513f62bae50SIngo Molnar local_irq_restore(flags); 1514f62bae50SIngo Molnar 1515ce69a784SGleb Natapov out: 1516ce69a784SGleb Natapov if (x2apic_enabled) 151793758238SWeidong Han return; 151893758238SWeidong Han 151993758238SWeidong Han if (x2apic_preenabled) 1520ce69a784SGleb Natapov panic("x2apic: enabled by BIOS but kernel init failed."); 152193758238SWeidong Han else if (cpu_has_x2apic) 1522ce69a784SGleb Natapov pr_info("Not enabling x2apic, Intr-remapping init failed.\n"); 1523f62bae50SIngo Molnar } 152493758238SWeidong Han 1525f62bae50SIngo Molnar #ifdef CONFIG_X86_64 1526f62bae50SIngo Molnar /* 1527f62bae50SIngo Molnar * Detect and enable local APICs on non-SMP boards. 1528f62bae50SIngo Molnar * Original code written by Keir Fraser. 1529f62bae50SIngo Molnar * On AMD64 we trust the BIOS - if it says no APIC it is likely 1530f62bae50SIngo Molnar * not correctly set up (usually the APIC timer won't work etc.) 1531f62bae50SIngo Molnar */ 1532f62bae50SIngo Molnar static int __init detect_init_APIC(void) 1533f62bae50SIngo Molnar { 1534f62bae50SIngo Molnar if (!cpu_has_apic) { 1535f62bae50SIngo Molnar pr_info("No local APIC present\n"); 1536f62bae50SIngo Molnar return -1; 1537f62bae50SIngo Molnar } 1538f62bae50SIngo Molnar 1539f62bae50SIngo Molnar mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1540f62bae50SIngo Molnar return 0; 1541f62bae50SIngo Molnar } 1542f62bae50SIngo Molnar #else 15435a7ae78fSThomas Gleixner 154425874a29SHenrik Kretzschmar static int __init apic_verify(void) 15455a7ae78fSThomas Gleixner { 15465a7ae78fSThomas Gleixner u32 features, h, l; 15475a7ae78fSThomas Gleixner 15485a7ae78fSThomas Gleixner /* 15495a7ae78fSThomas Gleixner * The APIC feature bit should now be enabled 15505a7ae78fSThomas Gleixner * in `cpuid' 15515a7ae78fSThomas Gleixner */ 15525a7ae78fSThomas Gleixner features = cpuid_edx(1); 15535a7ae78fSThomas Gleixner if (!(features & (1 << X86_FEATURE_APIC))) { 15545a7ae78fSThomas Gleixner pr_warning("Could not enable APIC!\n"); 15555a7ae78fSThomas Gleixner return -1; 15565a7ae78fSThomas Gleixner } 15575a7ae78fSThomas Gleixner set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 15585a7ae78fSThomas Gleixner mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 15595a7ae78fSThomas Gleixner 15605a7ae78fSThomas Gleixner /* The BIOS may have set up the APIC at some other address */ 15615a7ae78fSThomas Gleixner rdmsr(MSR_IA32_APICBASE, l, h); 15625a7ae78fSThomas Gleixner if (l & MSR_IA32_APICBASE_ENABLE) 15635a7ae78fSThomas Gleixner mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 15645a7ae78fSThomas Gleixner 15655a7ae78fSThomas Gleixner pr_info("Found and enabled local APIC!\n"); 15665a7ae78fSThomas Gleixner return 0; 15675a7ae78fSThomas Gleixner } 15685a7ae78fSThomas Gleixner 156925874a29SHenrik Kretzschmar int __init apic_force_enable(unsigned long addr) 15705a7ae78fSThomas Gleixner { 15715a7ae78fSThomas Gleixner u32 h, l; 15725a7ae78fSThomas Gleixner 15735a7ae78fSThomas Gleixner if (disable_apic) 15745a7ae78fSThomas Gleixner return -1; 15755a7ae78fSThomas Gleixner 15765a7ae78fSThomas Gleixner /* 15775a7ae78fSThomas Gleixner * Some BIOSes disable the local APIC in the APIC_BASE 15785a7ae78fSThomas Gleixner * MSR. This can only be done in software for Intel P6 or later 15795a7ae78fSThomas Gleixner * and AMD K7 (Model > 1) or later. 15805a7ae78fSThomas Gleixner */ 15815a7ae78fSThomas Gleixner rdmsr(MSR_IA32_APICBASE, l, h); 15825a7ae78fSThomas Gleixner if (!(l & MSR_IA32_APICBASE_ENABLE)) { 15835a7ae78fSThomas Gleixner pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 15845a7ae78fSThomas Gleixner l &= ~MSR_IA32_APICBASE_BASE; 1585a906fdaaSThomas Gleixner l |= MSR_IA32_APICBASE_ENABLE | addr; 15865a7ae78fSThomas Gleixner wrmsr(MSR_IA32_APICBASE, l, h); 15875a7ae78fSThomas Gleixner enabled_via_apicbase = 1; 15885a7ae78fSThomas Gleixner } 15895a7ae78fSThomas Gleixner return apic_verify(); 15905a7ae78fSThomas Gleixner } 15915a7ae78fSThomas Gleixner 1592f62bae50SIngo Molnar /* 1593f62bae50SIngo Molnar * Detect and initialize APIC 1594f62bae50SIngo Molnar */ 1595f62bae50SIngo Molnar static int __init detect_init_APIC(void) 1596f62bae50SIngo Molnar { 1597f62bae50SIngo Molnar /* Disabled by kernel option? */ 1598f62bae50SIngo Molnar if (disable_apic) 1599f62bae50SIngo Molnar return -1; 1600f62bae50SIngo Molnar 1601f62bae50SIngo Molnar switch (boot_cpu_data.x86_vendor) { 1602f62bae50SIngo Molnar case X86_VENDOR_AMD: 1603f62bae50SIngo Molnar if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1604f62bae50SIngo Molnar (boot_cpu_data.x86 >= 15)) 1605f62bae50SIngo Molnar break; 1606f62bae50SIngo Molnar goto no_apic; 1607f62bae50SIngo Molnar case X86_VENDOR_INTEL: 1608f62bae50SIngo Molnar if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1609f62bae50SIngo Molnar (boot_cpu_data.x86 == 5 && cpu_has_apic)) 1610f62bae50SIngo Molnar break; 1611f62bae50SIngo Molnar goto no_apic; 1612f62bae50SIngo Molnar default: 1613f62bae50SIngo Molnar goto no_apic; 1614f62bae50SIngo Molnar } 1615f62bae50SIngo Molnar 1616f62bae50SIngo Molnar if (!cpu_has_apic) { 1617f62bae50SIngo Molnar /* 1618f62bae50SIngo Molnar * Over-ride BIOS and try to enable the local APIC only if 1619f62bae50SIngo Molnar * "lapic" specified. 1620f62bae50SIngo Molnar */ 1621f62bae50SIngo Molnar if (!force_enable_local_apic) { 1622f62bae50SIngo Molnar pr_info("Local APIC disabled by BIOS -- " 1623f62bae50SIngo Molnar "you can enable it with \"lapic\"\n"); 1624f62bae50SIngo Molnar return -1; 1625f62bae50SIngo Molnar } 1626a906fdaaSThomas Gleixner if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) 16275a7ae78fSThomas Gleixner return -1; 16285a7ae78fSThomas Gleixner } else { 16295a7ae78fSThomas Gleixner if (apic_verify()) 1630f62bae50SIngo Molnar return -1; 1631f62bae50SIngo Molnar } 1632f62bae50SIngo Molnar 1633f62bae50SIngo Molnar apic_pm_activate(); 1634f62bae50SIngo Molnar 1635f62bae50SIngo Molnar return 0; 1636f62bae50SIngo Molnar 1637f62bae50SIngo Molnar no_apic: 1638f62bae50SIngo Molnar pr_info("No local APIC present or hardware disabled\n"); 1639f62bae50SIngo Molnar return -1; 1640f62bae50SIngo Molnar } 1641f62bae50SIngo Molnar #endif 1642f62bae50SIngo Molnar 1643f62bae50SIngo Molnar /** 1644f62bae50SIngo Molnar * init_apic_mappings - initialize APIC mappings 1645f62bae50SIngo Molnar */ 1646f62bae50SIngo Molnar void __init init_apic_mappings(void) 1647f62bae50SIngo Molnar { 16484401da61SYinghai Lu unsigned int new_apicid; 16494401da61SYinghai Lu 1650fc1edaf9SSuresh Siddha if (x2apic_mode) { 1651f62bae50SIngo Molnar boot_cpu_physical_apicid = read_apic_id(); 1652f62bae50SIngo Molnar return; 1653f62bae50SIngo Molnar } 1654f62bae50SIngo Molnar 16554797f6b0SYinghai Lu /* If no local APIC can be found return early */ 1656f62bae50SIngo Molnar if (!smp_found_config && detect_init_APIC()) { 16574797f6b0SYinghai Lu /* lets NOP'ify apic operations */ 16584797f6b0SYinghai Lu pr_info("APIC: disable apic facility\n"); 16594797f6b0SYinghai Lu apic_disable(); 16604797f6b0SYinghai Lu } else { 1661f62bae50SIngo Molnar apic_phys = mp_lapic_addr; 1662f62bae50SIngo Molnar 16634401da61SYinghai Lu /* 16644401da61SYinghai Lu * acpi lapic path already maps that address in 16654401da61SYinghai Lu * acpi_register_lapic_address() 16664401da61SYinghai Lu */ 16675989cd6aSEric W. Biederman if (!acpi_lapic && !smp_found_config) 1668326a2e6bSYinghai Lu register_lapic_address(apic_phys); 1669cec6be6dSCyrill Gorcunov } 1670f62bae50SIngo Molnar 1671f62bae50SIngo Molnar /* 1672f62bae50SIngo Molnar * Fetch the APIC ID of the BSP in case we have a 1673f62bae50SIngo Molnar * default configuration (or the MP table is broken). 1674f62bae50SIngo Molnar */ 16754401da61SYinghai Lu new_apicid = read_apic_id(); 16764401da61SYinghai Lu if (boot_cpu_physical_apicid != new_apicid) { 16774401da61SYinghai Lu boot_cpu_physical_apicid = new_apicid; 1678103428e5SCyrill Gorcunov /* 1679103428e5SCyrill Gorcunov * yeah -- we lie about apic_version 1680103428e5SCyrill Gorcunov * in case if apic was disabled via boot option 1681103428e5SCyrill Gorcunov * but it's not a problem for SMP compiled kernel 1682103428e5SCyrill Gorcunov * since smp_sanity_check is prepared for such a case 1683103428e5SCyrill Gorcunov * and disable smp mode 1684103428e5SCyrill Gorcunov */ 16854401da61SYinghai Lu apic_version[new_apicid] = 16864401da61SYinghai Lu GET_APIC_VERSION(apic_read(APIC_LVR)); 168708306ce6SCyrill Gorcunov } 1688f62bae50SIngo Molnar } 1689f62bae50SIngo Molnar 1690c0104d38SYinghai Lu void __init register_lapic_address(unsigned long address) 1691c0104d38SYinghai Lu { 1692c0104d38SYinghai Lu mp_lapic_addr = address; 1693c0104d38SYinghai Lu 16940450193bSYinghai Lu if (!x2apic_mode) { 1695c0104d38SYinghai Lu set_fixmap_nocache(FIX_APIC_BASE, address); 1696f1157141SYinghai Lu apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 1697f1157141SYinghai Lu APIC_BASE, mp_lapic_addr); 16980450193bSYinghai Lu } 1699c0104d38SYinghai Lu if (boot_cpu_physical_apicid == -1U) { 1700c0104d38SYinghai Lu boot_cpu_physical_apicid = read_apic_id(); 1701c0104d38SYinghai Lu apic_version[boot_cpu_physical_apicid] = 1702c0104d38SYinghai Lu GET_APIC_VERSION(apic_read(APIC_LVR)); 1703c0104d38SYinghai Lu } 1704c0104d38SYinghai Lu } 1705c0104d38SYinghai Lu 1706f62bae50SIngo Molnar /* 1707f62bae50SIngo Molnar * This initializes the IO-APIC and APIC hardware if this is 1708f62bae50SIngo Molnar * a UP kernel. 1709f62bae50SIngo Molnar */ 171056d91f13SYinghai Lu int apic_version[MAX_LOCAL_APIC]; 1711f62bae50SIngo Molnar 1712f62bae50SIngo Molnar int __init APIC_init_uniprocessor(void) 1713f62bae50SIngo Molnar { 1714f62bae50SIngo Molnar if (disable_apic) { 1715f62bae50SIngo Molnar pr_info("Apic disabled\n"); 1716f62bae50SIngo Molnar return -1; 1717f62bae50SIngo Molnar } 1718f62bae50SIngo Molnar #ifdef CONFIG_X86_64 1719f62bae50SIngo Molnar if (!cpu_has_apic) { 1720f62bae50SIngo Molnar disable_apic = 1; 1721f62bae50SIngo Molnar pr_info("Apic disabled by BIOS\n"); 1722f62bae50SIngo Molnar return -1; 1723f62bae50SIngo Molnar } 1724f62bae50SIngo Molnar #else 1725f62bae50SIngo Molnar if (!smp_found_config && !cpu_has_apic) 1726f62bae50SIngo Molnar return -1; 1727f62bae50SIngo Molnar 1728f62bae50SIngo Molnar /* 1729f62bae50SIngo Molnar * Complain if the BIOS pretends there is one. 1730f62bae50SIngo Molnar */ 1731f62bae50SIngo Molnar if (!cpu_has_apic && 1732f62bae50SIngo Molnar APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 1733f62bae50SIngo Molnar pr_err("BIOS bug, local APIC 0x%x not detected!...\n", 1734f62bae50SIngo Molnar boot_cpu_physical_apicid); 1735f62bae50SIngo Molnar return -1; 1736f62bae50SIngo Molnar } 1737f62bae50SIngo Molnar #endif 1738f62bae50SIngo Molnar 1739f62bae50SIngo Molnar default_setup_apic_routing(); 1740f62bae50SIngo Molnar 1741f62bae50SIngo Molnar verify_local_APIC(); 1742f62bae50SIngo Molnar connect_bsp_APIC(); 1743f62bae50SIngo Molnar 1744f62bae50SIngo Molnar #ifdef CONFIG_X86_64 1745f62bae50SIngo Molnar apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); 1746f62bae50SIngo Molnar #else 1747f62bae50SIngo Molnar /* 1748f62bae50SIngo Molnar * Hack: In case of kdump, after a crash, kernel might be booting 1749f62bae50SIngo Molnar * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 1750f62bae50SIngo Molnar * might be zero if read from MP tables. Get it from LAPIC. 1751f62bae50SIngo Molnar */ 1752f62bae50SIngo Molnar # ifdef CONFIG_CRASH_DUMP 1753f62bae50SIngo Molnar boot_cpu_physical_apicid = read_apic_id(); 1754f62bae50SIngo Molnar # endif 1755f62bae50SIngo Molnar #endif 1756f62bae50SIngo Molnar physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1757f62bae50SIngo Molnar setup_local_APIC(); 1758f62bae50SIngo Molnar 1759f62bae50SIngo Molnar #ifdef CONFIG_X86_IO_APIC 1760f62bae50SIngo Molnar /* 1761f62bae50SIngo Molnar * Now enable IO-APICs, actually call clear_IO_APIC 1762f62bae50SIngo Molnar * We need clear_IO_APIC before enabling error vector 1763f62bae50SIngo Molnar */ 1764f62bae50SIngo Molnar if (!skip_ioapic_setup && nr_ioapics) 1765f62bae50SIngo Molnar enable_IO_APIC(); 1766f62bae50SIngo Molnar #endif 1767f62bae50SIngo Molnar 17682fb270f3SJan Beulich bsp_end_local_APIC_setup(); 1769f62bae50SIngo Molnar 1770f62bae50SIngo Molnar #ifdef CONFIG_X86_IO_APIC 1771f62bae50SIngo Molnar if (smp_found_config && !skip_ioapic_setup && nr_ioapics) 1772f62bae50SIngo Molnar setup_IO_APIC(); 1773f62bae50SIngo Molnar else { 1774f62bae50SIngo Molnar nr_ioapics = 0; 1775f62bae50SIngo Molnar } 1776f62bae50SIngo Molnar #endif 1777f62bae50SIngo Molnar 1778736decacSThomas Gleixner x86_init.timers.setup_percpu_clockev(); 1779f62bae50SIngo Molnar return 0; 1780f62bae50SIngo Molnar } 1781f62bae50SIngo Molnar 1782f62bae50SIngo Molnar /* 1783f62bae50SIngo Molnar * Local APIC interrupts 1784f62bae50SIngo Molnar */ 1785f62bae50SIngo Molnar 1786f62bae50SIngo Molnar /* 1787f62bae50SIngo Molnar * This interrupt should _never_ happen with our APIC/SMP architecture 1788f62bae50SIngo Molnar */ 1789f62bae50SIngo Molnar void smp_spurious_interrupt(struct pt_regs *regs) 1790f62bae50SIngo Molnar { 1791f62bae50SIngo Molnar u32 v; 1792f62bae50SIngo Molnar 1793f62bae50SIngo Molnar exit_idle(); 1794f62bae50SIngo Molnar irq_enter(); 1795f62bae50SIngo Molnar /* 1796f62bae50SIngo Molnar * Check if this really is a spurious interrupt and ACK it 1797f62bae50SIngo Molnar * if it is a vectored one. Just in case... 1798f62bae50SIngo Molnar * Spurious interrupts should not be ACKed. 1799f62bae50SIngo Molnar */ 1800f62bae50SIngo Molnar v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); 1801f62bae50SIngo Molnar if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) 1802f62bae50SIngo Molnar ack_APIC_irq(); 1803f62bae50SIngo Molnar 1804f62bae50SIngo Molnar inc_irq_stat(irq_spurious_count); 1805f62bae50SIngo Molnar 1806f62bae50SIngo Molnar /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 1807f62bae50SIngo Molnar pr_info("spurious APIC interrupt on CPU#%d, " 1808f62bae50SIngo Molnar "should never happen.\n", smp_processor_id()); 1809f62bae50SIngo Molnar irq_exit(); 1810f62bae50SIngo Molnar } 1811f62bae50SIngo Molnar 1812f62bae50SIngo Molnar /* 1813f62bae50SIngo Molnar * This interrupt should never happen with our APIC/SMP architecture 1814f62bae50SIngo Molnar */ 1815f62bae50SIngo Molnar void smp_error_interrupt(struct pt_regs *regs) 1816f62bae50SIngo Molnar { 18172b398bd9SYouquan Song u32 v0, v1; 18182b398bd9SYouquan Song u32 i = 0; 18192b398bd9SYouquan Song static const char * const error_interrupt_reason[] = { 18202b398bd9SYouquan Song "Send CS error", /* APIC Error Bit 0 */ 18212b398bd9SYouquan Song "Receive CS error", /* APIC Error Bit 1 */ 18222b398bd9SYouquan Song "Send accept error", /* APIC Error Bit 2 */ 18232b398bd9SYouquan Song "Receive accept error", /* APIC Error Bit 3 */ 18242b398bd9SYouquan Song "Redirectable IPI", /* APIC Error Bit 4 */ 18252b398bd9SYouquan Song "Send illegal vector", /* APIC Error Bit 5 */ 18262b398bd9SYouquan Song "Received illegal vector", /* APIC Error Bit 6 */ 18272b398bd9SYouquan Song "Illegal register address", /* APIC Error Bit 7 */ 18282b398bd9SYouquan Song }; 1829f62bae50SIngo Molnar 1830f62bae50SIngo Molnar exit_idle(); 1831f62bae50SIngo Molnar irq_enter(); 1832f62bae50SIngo Molnar /* First tickle the hardware, only then report what went on. -- REW */ 18332b398bd9SYouquan Song v0 = apic_read(APIC_ESR); 1834f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 1835f62bae50SIngo Molnar v1 = apic_read(APIC_ESR); 1836f62bae50SIngo Molnar ack_APIC_irq(); 1837f62bae50SIngo Molnar atomic_inc(&irq_err_count); 1838f62bae50SIngo Molnar 18392b398bd9SYouquan Song apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x(%02x)", 18402b398bd9SYouquan Song smp_processor_id(), v0 , v1); 18412b398bd9SYouquan Song 18422b398bd9SYouquan Song v1 = v1 & 0xff; 18432b398bd9SYouquan Song while (v1) { 18442b398bd9SYouquan Song if (v1 & 0x1) 18452b398bd9SYouquan Song apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); 18462b398bd9SYouquan Song i++; 18472b398bd9SYouquan Song v1 >>= 1; 18482b398bd9SYouquan Song }; 18492b398bd9SYouquan Song 18502b398bd9SYouquan Song apic_printk(APIC_DEBUG, KERN_CONT "\n"); 18512b398bd9SYouquan Song 1852f62bae50SIngo Molnar irq_exit(); 1853f62bae50SIngo Molnar } 1854f62bae50SIngo Molnar 1855f62bae50SIngo Molnar /** 1856f62bae50SIngo Molnar * connect_bsp_APIC - attach the APIC to the interrupt system 1857f62bae50SIngo Molnar */ 1858f62bae50SIngo Molnar void __init connect_bsp_APIC(void) 1859f62bae50SIngo Molnar { 1860f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1861f62bae50SIngo Molnar if (pic_mode) { 1862f62bae50SIngo Molnar /* 1863f62bae50SIngo Molnar * Do not trust the local APIC being empty at bootup. 1864f62bae50SIngo Molnar */ 1865f62bae50SIngo Molnar clear_local_APIC(); 1866f62bae50SIngo Molnar /* 1867f62bae50SIngo Molnar * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 1868f62bae50SIngo Molnar * local APIC to INT and NMI lines. 1869f62bae50SIngo Molnar */ 1870f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "leaving PIC mode, " 1871f62bae50SIngo Molnar "enabling APIC mode.\n"); 1872c0eaa453SCyrill Gorcunov imcr_pic_to_apic(); 1873f62bae50SIngo Molnar } 1874f62bae50SIngo Molnar #endif 1875f62bae50SIngo Molnar if (apic->enable_apic_mode) 1876f62bae50SIngo Molnar apic->enable_apic_mode(); 1877f62bae50SIngo Molnar } 1878f62bae50SIngo Molnar 1879f62bae50SIngo Molnar /** 1880f62bae50SIngo Molnar * disconnect_bsp_APIC - detach the APIC from the interrupt system 1881f62bae50SIngo Molnar * @virt_wire_setup: indicates, whether virtual wire mode is selected 1882f62bae50SIngo Molnar * 1883f62bae50SIngo Molnar * Virtual wire mode is necessary to deliver legacy interrupts even when the 1884f62bae50SIngo Molnar * APIC is disabled. 1885f62bae50SIngo Molnar */ 1886f62bae50SIngo Molnar void disconnect_bsp_APIC(int virt_wire_setup) 1887f62bae50SIngo Molnar { 1888f62bae50SIngo Molnar unsigned int value; 1889f62bae50SIngo Molnar 1890f62bae50SIngo Molnar #ifdef CONFIG_X86_32 1891f62bae50SIngo Molnar if (pic_mode) { 1892f62bae50SIngo Molnar /* 1893f62bae50SIngo Molnar * Put the board back into PIC mode (has an effect only on 1894f62bae50SIngo Molnar * certain older boards). Note that APIC interrupts, including 1895f62bae50SIngo Molnar * IPIs, won't work beyond this point! The only exception are 1896f62bae50SIngo Molnar * INIT IPIs. 1897f62bae50SIngo Molnar */ 1898f62bae50SIngo Molnar apic_printk(APIC_VERBOSE, "disabling APIC mode, " 1899f62bae50SIngo Molnar "entering PIC mode.\n"); 1900c0eaa453SCyrill Gorcunov imcr_apic_to_pic(); 1901f62bae50SIngo Molnar return; 1902f62bae50SIngo Molnar } 1903f62bae50SIngo Molnar #endif 1904f62bae50SIngo Molnar 1905f62bae50SIngo Molnar /* Go back to Virtual Wire compatibility mode */ 1906f62bae50SIngo Molnar 1907f62bae50SIngo Molnar /* For the spurious interrupt use vector F, and enable it */ 1908f62bae50SIngo Molnar value = apic_read(APIC_SPIV); 1909f62bae50SIngo Molnar value &= ~APIC_VECTOR_MASK; 1910f62bae50SIngo Molnar value |= APIC_SPIV_APIC_ENABLED; 1911f62bae50SIngo Molnar value |= 0xf; 1912f62bae50SIngo Molnar apic_write(APIC_SPIV, value); 1913f62bae50SIngo Molnar 1914f62bae50SIngo Molnar if (!virt_wire_setup) { 1915f62bae50SIngo Molnar /* 1916f62bae50SIngo Molnar * For LVT0 make it edge triggered, active high, 1917f62bae50SIngo Molnar * external and enabled 1918f62bae50SIngo Molnar */ 1919f62bae50SIngo Molnar value = apic_read(APIC_LVT0); 1920f62bae50SIngo Molnar value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1921f62bae50SIngo Molnar APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1922f62bae50SIngo Molnar APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1923f62bae50SIngo Molnar value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1924f62bae50SIngo Molnar value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 1925f62bae50SIngo Molnar apic_write(APIC_LVT0, value); 1926f62bae50SIngo Molnar } else { 1927f62bae50SIngo Molnar /* Disable LVT0 */ 1928f62bae50SIngo Molnar apic_write(APIC_LVT0, APIC_LVT_MASKED); 1929f62bae50SIngo Molnar } 1930f62bae50SIngo Molnar 1931f62bae50SIngo Molnar /* 1932f62bae50SIngo Molnar * For LVT1 make it edge triggered, active high, 1933f62bae50SIngo Molnar * nmi and enabled 1934f62bae50SIngo Molnar */ 1935f62bae50SIngo Molnar value = apic_read(APIC_LVT1); 1936f62bae50SIngo Molnar value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1937f62bae50SIngo Molnar APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1938f62bae50SIngo Molnar APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1939f62bae50SIngo Molnar value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1940f62bae50SIngo Molnar value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 1941f62bae50SIngo Molnar apic_write(APIC_LVT1, value); 1942f62bae50SIngo Molnar } 1943f62bae50SIngo Molnar 1944f62bae50SIngo Molnar void __cpuinit generic_processor_info(int apicid, int version) 1945f62bae50SIngo Molnar { 1946f62bae50SIngo Molnar int cpu; 1947f62bae50SIngo Molnar 1948f62bae50SIngo Molnar if (num_processors >= nr_cpu_ids) { 1949f62bae50SIngo Molnar int max = nr_cpu_ids; 1950f62bae50SIngo Molnar int thiscpu = max + disabled_cpus; 1951f62bae50SIngo Molnar 1952f62bae50SIngo Molnar pr_warning( 1953f62bae50SIngo Molnar "ACPI: NR_CPUS/possible_cpus limit of %i reached." 1954f62bae50SIngo Molnar " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 1955f62bae50SIngo Molnar 1956f62bae50SIngo Molnar disabled_cpus++; 1957f62bae50SIngo Molnar return; 1958f62bae50SIngo Molnar } 1959f62bae50SIngo Molnar 1960f62bae50SIngo Molnar num_processors++; 1961f62bae50SIngo Molnar if (apicid == boot_cpu_physical_apicid) { 1962f62bae50SIngo Molnar /* 1963f62bae50SIngo Molnar * x86_bios_cpu_apicid is required to have processors listed 1964f62bae50SIngo Molnar * in same order as logical cpu numbers. Hence the first 1965f62bae50SIngo Molnar * entry is BSP, and so on. 1966e5fea868SYinghai Lu * boot_cpu_init() already hold bit 0 in cpu_present_mask 1967e5fea868SYinghai Lu * for BSP. 1968f62bae50SIngo Molnar */ 1969f62bae50SIngo Molnar cpu = 0; 1970e5fea868SYinghai Lu } else 1971e5fea868SYinghai Lu cpu = cpumask_next_zero(-1, cpu_present_mask); 1972e5fea868SYinghai Lu 1973e5fea868SYinghai Lu /* 1974e5fea868SYinghai Lu * Validate version 1975e5fea868SYinghai Lu */ 1976e5fea868SYinghai Lu if (version == 0x0) { 1977e5fea868SYinghai Lu pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", 1978e5fea868SYinghai Lu cpu, apicid); 1979e5fea868SYinghai Lu version = 0x10; 1980f62bae50SIngo Molnar } 1981e5fea868SYinghai Lu apic_version[apicid] = version; 1982e5fea868SYinghai Lu 1983e5fea868SYinghai Lu if (version != apic_version[boot_cpu_physical_apicid]) { 1984e5fea868SYinghai Lu pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", 1985e5fea868SYinghai Lu apic_version[boot_cpu_physical_apicid], cpu, version); 1986e5fea868SYinghai Lu } 1987e5fea868SYinghai Lu 1988e5fea868SYinghai Lu physid_set(apicid, phys_cpu_present_map); 1989f62bae50SIngo Molnar if (apicid > max_physical_apicid) 1990f62bae50SIngo Molnar max_physical_apicid = apicid; 1991f62bae50SIngo Molnar 1992f62bae50SIngo Molnar #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 1993f62bae50SIngo Molnar early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 1994f62bae50SIngo Molnar early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 1995f62bae50SIngo Molnar #endif 1996acb8bc09STejun Heo #ifdef CONFIG_X86_32 1997acb8bc09STejun Heo early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 1998acb8bc09STejun Heo apic->x86_32_early_logical_apicid(cpu); 1999acb8bc09STejun Heo #endif 2000f62bae50SIngo Molnar set_cpu_possible(cpu, true); 2001f62bae50SIngo Molnar set_cpu_present(cpu, true); 2002f62bae50SIngo Molnar } 2003f62bae50SIngo Molnar 2004f62bae50SIngo Molnar int hard_smp_processor_id(void) 2005f62bae50SIngo Molnar { 2006f62bae50SIngo Molnar return read_apic_id(); 2007f62bae50SIngo Molnar } 2008f62bae50SIngo Molnar 2009f62bae50SIngo Molnar void default_init_apic_ldr(void) 2010f62bae50SIngo Molnar { 2011f62bae50SIngo Molnar unsigned long val; 2012f62bae50SIngo Molnar 2013f62bae50SIngo Molnar apic_write(APIC_DFR, APIC_DFR_VALUE); 2014f62bae50SIngo Molnar val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; 2015f62bae50SIngo Molnar val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); 2016f62bae50SIngo Molnar apic_write(APIC_LDR, val); 2017f62bae50SIngo Molnar } 2018f62bae50SIngo Molnar 2019f62bae50SIngo Molnar /* 2020f62bae50SIngo Molnar * Power management 2021f62bae50SIngo Molnar */ 2022f62bae50SIngo Molnar #ifdef CONFIG_PM 2023f62bae50SIngo Molnar 2024f62bae50SIngo Molnar static struct { 2025f62bae50SIngo Molnar /* 2026f62bae50SIngo Molnar * 'active' is true if the local APIC was enabled by us and 2027f62bae50SIngo Molnar * not the BIOS; this signifies that we are also responsible 2028f62bae50SIngo Molnar * for disabling it before entering apm/acpi suspend 2029f62bae50SIngo Molnar */ 2030f62bae50SIngo Molnar int active; 2031f62bae50SIngo Molnar /* r/w apic fields */ 2032f62bae50SIngo Molnar unsigned int apic_id; 2033f62bae50SIngo Molnar unsigned int apic_taskpri; 2034f62bae50SIngo Molnar unsigned int apic_ldr; 2035f62bae50SIngo Molnar unsigned int apic_dfr; 2036f62bae50SIngo Molnar unsigned int apic_spiv; 2037f62bae50SIngo Molnar unsigned int apic_lvtt; 2038f62bae50SIngo Molnar unsigned int apic_lvtpc; 2039f62bae50SIngo Molnar unsigned int apic_lvt0; 2040f62bae50SIngo Molnar unsigned int apic_lvt1; 2041f62bae50SIngo Molnar unsigned int apic_lvterr; 2042f62bae50SIngo Molnar unsigned int apic_tmict; 2043f62bae50SIngo Molnar unsigned int apic_tdcr; 2044f62bae50SIngo Molnar unsigned int apic_thmr; 2045f62bae50SIngo Molnar } apic_pm_state; 2046f62bae50SIngo Molnar 2047f3c6ea1bSRafael J. Wysocki static int lapic_suspend(void) 2048f62bae50SIngo Molnar { 2049f62bae50SIngo Molnar unsigned long flags; 2050f62bae50SIngo Molnar int maxlvt; 2051f62bae50SIngo Molnar 2052f62bae50SIngo Molnar if (!apic_pm_state.active) 2053f62bae50SIngo Molnar return 0; 2054f62bae50SIngo Molnar 2055f62bae50SIngo Molnar maxlvt = lapic_get_maxlvt(); 2056f62bae50SIngo Molnar 2057f62bae50SIngo Molnar apic_pm_state.apic_id = apic_read(APIC_ID); 2058f62bae50SIngo Molnar apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2059f62bae50SIngo Molnar apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2060f62bae50SIngo Molnar apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2061f62bae50SIngo Molnar apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2062f62bae50SIngo Molnar apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2063f62bae50SIngo Molnar if (maxlvt >= 4) 2064f62bae50SIngo Molnar apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2065f62bae50SIngo Molnar apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2066f62bae50SIngo Molnar apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2067f62bae50SIngo Molnar apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2068f62bae50SIngo Molnar apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2069f62bae50SIngo Molnar apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 20704efc0670SAndi Kleen #ifdef CONFIG_X86_THERMAL_VECTOR 2071f62bae50SIngo Molnar if (maxlvt >= 5) 2072f62bae50SIngo Molnar apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2073f62bae50SIngo Molnar #endif 2074f62bae50SIngo Molnar 2075f62bae50SIngo Molnar local_irq_save(flags); 2076f62bae50SIngo Molnar disable_local_APIC(); 2077fc1edaf9SSuresh Siddha 2078b24696bcSFenghua Yu if (intr_remapping_enabled) 2079b24696bcSFenghua Yu disable_intr_remapping(); 2080fc1edaf9SSuresh Siddha 2081f62bae50SIngo Molnar local_irq_restore(flags); 2082f62bae50SIngo Molnar return 0; 2083f62bae50SIngo Molnar } 2084f62bae50SIngo Molnar 2085f3c6ea1bSRafael J. Wysocki static void lapic_resume(void) 2086f62bae50SIngo Molnar { 2087f62bae50SIngo Molnar unsigned int l, h; 2088f62bae50SIngo Molnar unsigned long flags; 208931dce14aSSuresh Siddha int maxlvt; 2090b24696bcSFenghua Yu 2091f62bae50SIngo Molnar if (!apic_pm_state.active) 2092f3c6ea1bSRafael J. Wysocki return; 2093f62bae50SIngo Molnar 2094b24696bcSFenghua Yu local_irq_save(flags); 20959a2755c3SWeidong Han if (intr_remapping_enabled) { 209631dce14aSSuresh Siddha /* 209731dce14aSSuresh Siddha * IO-APIC and PIC have their own resume routines. 209831dce14aSSuresh Siddha * We just mask them here to make sure the interrupt 209931dce14aSSuresh Siddha * subsystem is completely quiet while we enable x2apic 210031dce14aSSuresh Siddha * and interrupt-remapping. 210131dce14aSSuresh Siddha */ 210231dce14aSSuresh Siddha mask_ioapic_entries(); 2103b81bb373SJacob Pan legacy_pic->mask_all(); 2104b24696bcSFenghua Yu } 2105f62bae50SIngo Molnar 2106fc1edaf9SSuresh Siddha if (x2apic_mode) 2107f62bae50SIngo Molnar enable_x2apic(); 2108cf6567feSSuresh Siddha else { 2109f62bae50SIngo Molnar /* 2110f62bae50SIngo Molnar * Make sure the APICBASE points to the right address 2111f62bae50SIngo Molnar * 2112f62bae50SIngo Molnar * FIXME! This will be wrong if we ever support suspend on 2113f62bae50SIngo Molnar * SMP! We'll need to do this as part of the CPU restore! 2114f62bae50SIngo Molnar */ 2115f62bae50SIngo Molnar rdmsr(MSR_IA32_APICBASE, l, h); 2116f62bae50SIngo Molnar l &= ~MSR_IA32_APICBASE_BASE; 2117f62bae50SIngo Molnar l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2118f62bae50SIngo Molnar wrmsr(MSR_IA32_APICBASE, l, h); 2119f62bae50SIngo Molnar } 2120f62bae50SIngo Molnar 2121b24696bcSFenghua Yu maxlvt = lapic_get_maxlvt(); 2122f62bae50SIngo Molnar apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2123f62bae50SIngo Molnar apic_write(APIC_ID, apic_pm_state.apic_id); 2124f62bae50SIngo Molnar apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2125f62bae50SIngo Molnar apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2126f62bae50SIngo Molnar apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2127f62bae50SIngo Molnar apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2128f62bae50SIngo Molnar apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2129f62bae50SIngo Molnar apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2130f62bae50SIngo Molnar #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) 2131f62bae50SIngo Molnar if (maxlvt >= 5) 2132f62bae50SIngo Molnar apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2133f62bae50SIngo Molnar #endif 2134f62bae50SIngo Molnar if (maxlvt >= 4) 2135f62bae50SIngo Molnar apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2136f62bae50SIngo Molnar apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2137f62bae50SIngo Molnar apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2138f62bae50SIngo Molnar apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2139f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 2140f62bae50SIngo Molnar apic_read(APIC_ESR); 2141f62bae50SIngo Molnar apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2142f62bae50SIngo Molnar apic_write(APIC_ESR, 0); 2143f62bae50SIngo Molnar apic_read(APIC_ESR); 2144f62bae50SIngo Molnar 214531dce14aSSuresh Siddha if (intr_remapping_enabled) 2146fc1edaf9SSuresh Siddha reenable_intr_remapping(x2apic_mode); 214731dce14aSSuresh Siddha 2148f62bae50SIngo Molnar local_irq_restore(flags); 2149f62bae50SIngo Molnar } 2150f62bae50SIngo Molnar 2151f62bae50SIngo Molnar /* 2152f62bae50SIngo Molnar * This device has no shutdown method - fully functioning local APICs 2153f62bae50SIngo Molnar * are needed on every CPU up until machine_halt/restart/poweroff. 2154f62bae50SIngo Molnar */ 2155f62bae50SIngo Molnar 2156f3c6ea1bSRafael J. Wysocki static struct syscore_ops lapic_syscore_ops = { 2157f62bae50SIngo Molnar .resume = lapic_resume, 2158f62bae50SIngo Molnar .suspend = lapic_suspend, 2159f62bae50SIngo Molnar }; 2160f62bae50SIngo Molnar 2161f62bae50SIngo Molnar static void __cpuinit apic_pm_activate(void) 2162f62bae50SIngo Molnar { 2163f62bae50SIngo Molnar apic_pm_state.active = 1; 2164f62bae50SIngo Molnar } 2165f62bae50SIngo Molnar 2166f62bae50SIngo Molnar static int __init init_lapic_sysfs(void) 2167f62bae50SIngo Molnar { 2168f62bae50SIngo Molnar /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2169f3c6ea1bSRafael J. Wysocki if (cpu_has_apic) 2170f3c6ea1bSRafael J. Wysocki register_syscore_ops(&lapic_syscore_ops); 2171f62bae50SIngo Molnar 2172f3c6ea1bSRafael J. Wysocki return 0; 2173f62bae50SIngo Molnar } 2174b24696bcSFenghua Yu 2175b24696bcSFenghua Yu /* local apic needs to resume before other devices access its registers. */ 2176b24696bcSFenghua Yu core_initcall(init_lapic_sysfs); 2177f62bae50SIngo Molnar 2178f62bae50SIngo Molnar #else /* CONFIG_PM */ 2179f62bae50SIngo Molnar 2180f62bae50SIngo Molnar static void apic_pm_activate(void) { } 2181f62bae50SIngo Molnar 2182f62bae50SIngo Molnar #endif /* CONFIG_PM */ 2183f62bae50SIngo Molnar 2184f62bae50SIngo Molnar #ifdef CONFIG_X86_64 2185e0e42142SYinghai Lu 2186e0e42142SYinghai Lu static int __cpuinit apic_cluster_num(void) 2187f62bae50SIngo Molnar { 2188f62bae50SIngo Molnar int i, clusters, zeros; 2189f62bae50SIngo Molnar unsigned id; 2190f62bae50SIngo Molnar u16 *bios_cpu_apicid; 2191f62bae50SIngo Molnar DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); 2192f62bae50SIngo Molnar 2193f62bae50SIngo Molnar bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); 2194f62bae50SIngo Molnar bitmap_zero(clustermap, NUM_APIC_CLUSTERS); 2195f62bae50SIngo Molnar 2196f62bae50SIngo Molnar for (i = 0; i < nr_cpu_ids; i++) { 2197f62bae50SIngo Molnar /* are we being called early in kernel startup? */ 2198f62bae50SIngo Molnar if (bios_cpu_apicid) { 2199f62bae50SIngo Molnar id = bios_cpu_apicid[i]; 2200f62bae50SIngo Molnar } else if (i < nr_cpu_ids) { 2201f62bae50SIngo Molnar if (cpu_present(i)) 2202f62bae50SIngo Molnar id = per_cpu(x86_bios_cpu_apicid, i); 2203f62bae50SIngo Molnar else 2204f62bae50SIngo Molnar continue; 2205f62bae50SIngo Molnar } else 2206f62bae50SIngo Molnar break; 2207f62bae50SIngo Molnar 2208f62bae50SIngo Molnar if (id != BAD_APICID) 2209f62bae50SIngo Molnar __set_bit(APIC_CLUSTERID(id), clustermap); 2210f62bae50SIngo Molnar } 2211f62bae50SIngo Molnar 2212f62bae50SIngo Molnar /* Problem: Partially populated chassis may not have CPUs in some of 2213f62bae50SIngo Molnar * the APIC clusters they have been allocated. Only present CPUs have 2214f62bae50SIngo Molnar * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. 2215f62bae50SIngo Molnar * Since clusters are allocated sequentially, count zeros only if 2216f62bae50SIngo Molnar * they are bounded by ones. 2217f62bae50SIngo Molnar */ 2218f62bae50SIngo Molnar clusters = 0; 2219f62bae50SIngo Molnar zeros = 0; 2220f62bae50SIngo Molnar for (i = 0; i < NUM_APIC_CLUSTERS; i++) { 2221f62bae50SIngo Molnar if (test_bit(i, clustermap)) { 2222f62bae50SIngo Molnar clusters += 1 + zeros; 2223f62bae50SIngo Molnar zeros = 0; 2224f62bae50SIngo Molnar } else 2225f62bae50SIngo Molnar ++zeros; 2226f62bae50SIngo Molnar } 2227f62bae50SIngo Molnar 2228e0e42142SYinghai Lu return clusters; 2229e0e42142SYinghai Lu } 2230e0e42142SYinghai Lu 2231e0e42142SYinghai Lu static int __cpuinitdata multi_checked; 2232e0e42142SYinghai Lu static int __cpuinitdata multi; 2233e0e42142SYinghai Lu 2234e0e42142SYinghai Lu static int __cpuinit set_multi(const struct dmi_system_id *d) 2235e0e42142SYinghai Lu { 2236e0e42142SYinghai Lu if (multi) 2237e0e42142SYinghai Lu return 0; 22386f0aced6SCyrill Gorcunov pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2239e0e42142SYinghai Lu multi = 1; 2240e0e42142SYinghai Lu return 0; 2241e0e42142SYinghai Lu } 2242e0e42142SYinghai Lu 2243e0e42142SYinghai Lu static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = { 2244e0e42142SYinghai Lu { 2245e0e42142SYinghai Lu .callback = set_multi, 2246e0e42142SYinghai Lu .ident = "IBM System Summit2", 2247e0e42142SYinghai Lu .matches = { 2248e0e42142SYinghai Lu DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2249e0e42142SYinghai Lu DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2250e0e42142SYinghai Lu }, 2251e0e42142SYinghai Lu }, 2252e0e42142SYinghai Lu {} 2253e0e42142SYinghai Lu }; 2254e0e42142SYinghai Lu 2255e0e42142SYinghai Lu static void __cpuinit dmi_check_multi(void) 2256e0e42142SYinghai Lu { 2257e0e42142SYinghai Lu if (multi_checked) 2258e0e42142SYinghai Lu return; 2259e0e42142SYinghai Lu 2260e0e42142SYinghai Lu dmi_check_system(multi_dmi_table); 2261e0e42142SYinghai Lu multi_checked = 1; 2262e0e42142SYinghai Lu } 2263f62bae50SIngo Molnar 2264f62bae50SIngo Molnar /* 2265e0e42142SYinghai Lu * apic_is_clustered_box() -- Check if we can expect good TSC 2266e0e42142SYinghai Lu * 2267e0e42142SYinghai Lu * Thus far, the major user of this is IBM's Summit2 series: 2268e0e42142SYinghai Lu * Clustered boxes may have unsynced TSC problems if they are 2269e0e42142SYinghai Lu * multi-chassis. 2270e0e42142SYinghai Lu * Use DMI to check them 2271f62bae50SIngo Molnar */ 2272e0e42142SYinghai Lu __cpuinit int apic_is_clustered_box(void) 2273e0e42142SYinghai Lu { 2274e0e42142SYinghai Lu dmi_check_multi(); 2275e0e42142SYinghai Lu if (multi) 2276e0e42142SYinghai Lu return 1; 2277e0e42142SYinghai Lu 2278e0e42142SYinghai Lu if (!is_vsmp_box()) 2279e0e42142SYinghai Lu return 0; 2280e0e42142SYinghai Lu 2281e0e42142SYinghai Lu /* 2282e0e42142SYinghai Lu * ScaleMP vSMPowered boxes have one cluster per board and TSCs are 2283e0e42142SYinghai Lu * not guaranteed to be synced between boards 2284e0e42142SYinghai Lu */ 2285e0e42142SYinghai Lu if (apic_cluster_num() > 1) 2286e0e42142SYinghai Lu return 1; 2287e0e42142SYinghai Lu 2288e0e42142SYinghai Lu return 0; 2289f62bae50SIngo Molnar } 2290f62bae50SIngo Molnar #endif 2291f62bae50SIngo Molnar 2292f62bae50SIngo Molnar /* 2293f62bae50SIngo Molnar * APIC command line parameters 2294f62bae50SIngo Molnar */ 2295f62bae50SIngo Molnar static int __init setup_disableapic(char *arg) 2296f62bae50SIngo Molnar { 2297f62bae50SIngo Molnar disable_apic = 1; 2298f62bae50SIngo Molnar setup_clear_cpu_cap(X86_FEATURE_APIC); 2299f62bae50SIngo Molnar return 0; 2300f62bae50SIngo Molnar } 2301f62bae50SIngo Molnar early_param("disableapic", setup_disableapic); 2302f62bae50SIngo Molnar 2303f62bae50SIngo Molnar /* same as disableapic, for compatibility */ 2304f62bae50SIngo Molnar static int __init setup_nolapic(char *arg) 2305f62bae50SIngo Molnar { 2306f62bae50SIngo Molnar return setup_disableapic(arg); 2307f62bae50SIngo Molnar } 2308f62bae50SIngo Molnar early_param("nolapic", setup_nolapic); 2309f62bae50SIngo Molnar 2310f62bae50SIngo Molnar static int __init parse_lapic_timer_c2_ok(char *arg) 2311f62bae50SIngo Molnar { 2312f62bae50SIngo Molnar local_apic_timer_c2_ok = 1; 2313f62bae50SIngo Molnar return 0; 2314f62bae50SIngo Molnar } 2315f62bae50SIngo Molnar early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2316f62bae50SIngo Molnar 2317f62bae50SIngo Molnar static int __init parse_disable_apic_timer(char *arg) 2318f62bae50SIngo Molnar { 2319f62bae50SIngo Molnar disable_apic_timer = 1; 2320f62bae50SIngo Molnar return 0; 2321f62bae50SIngo Molnar } 2322f62bae50SIngo Molnar early_param("noapictimer", parse_disable_apic_timer); 2323f62bae50SIngo Molnar 2324f62bae50SIngo Molnar static int __init parse_nolapic_timer(char *arg) 2325f62bae50SIngo Molnar { 2326f62bae50SIngo Molnar disable_apic_timer = 1; 2327f62bae50SIngo Molnar return 0; 2328f62bae50SIngo Molnar } 2329f62bae50SIngo Molnar early_param("nolapic_timer", parse_nolapic_timer); 2330f62bae50SIngo Molnar 2331f62bae50SIngo Molnar static int __init apic_set_verbosity(char *arg) 2332f62bae50SIngo Molnar { 2333f62bae50SIngo Molnar if (!arg) { 2334f62bae50SIngo Molnar #ifdef CONFIG_X86_64 2335f62bae50SIngo Molnar skip_ioapic_setup = 0; 2336f62bae50SIngo Molnar return 0; 2337f62bae50SIngo Molnar #endif 2338f62bae50SIngo Molnar return -EINVAL; 2339f62bae50SIngo Molnar } 2340f62bae50SIngo Molnar 2341f62bae50SIngo Molnar if (strcmp("debug", arg) == 0) 2342f62bae50SIngo Molnar apic_verbosity = APIC_DEBUG; 2343f62bae50SIngo Molnar else if (strcmp("verbose", arg) == 0) 2344f62bae50SIngo Molnar apic_verbosity = APIC_VERBOSE; 2345f62bae50SIngo Molnar else { 2346f62bae50SIngo Molnar pr_warning("APIC Verbosity level %s not recognised" 2347f62bae50SIngo Molnar " use apic=verbose or apic=debug\n", arg); 2348f62bae50SIngo Molnar return -EINVAL; 2349f62bae50SIngo Molnar } 2350f62bae50SIngo Molnar 2351f62bae50SIngo Molnar return 0; 2352f62bae50SIngo Molnar } 2353f62bae50SIngo Molnar early_param("apic", apic_set_verbosity); 2354f62bae50SIngo Molnar 2355f62bae50SIngo Molnar static int __init lapic_insert_resource(void) 2356f62bae50SIngo Molnar { 2357f62bae50SIngo Molnar if (!apic_phys) 2358f62bae50SIngo Molnar return -1; 2359f62bae50SIngo Molnar 2360f62bae50SIngo Molnar /* Put local APIC into the resource map. */ 2361f62bae50SIngo Molnar lapic_resource.start = apic_phys; 2362f62bae50SIngo Molnar lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2363f62bae50SIngo Molnar insert_resource(&iomem_resource, &lapic_resource); 2364f62bae50SIngo Molnar 2365f62bae50SIngo Molnar return 0; 2366f62bae50SIngo Molnar } 2367f62bae50SIngo Molnar 2368f62bae50SIngo Molnar /* 2369f62bae50SIngo Molnar * need call insert after e820_reserve_resources() 2370f62bae50SIngo Molnar * that is using request_resource 2371f62bae50SIngo Molnar */ 2372f62bae50SIngo Molnar late_initcall(lapic_insert_resource); 2373