1 /* 2 * Firmware replacement code. 3 * 4 * Work around broken BIOSes that don't set an aperture or only set the 5 * aperture in the AGP bridge. 6 * If all fails map the aperture over some low memory. This is cheaper than 7 * doing bounce buffering. The memory is lost. This is done at early boot 8 * because only the bootmem allocator can allocate 32+MB. 9 * 10 * Copyright 2002 Andi Kleen, SuSE Labs. 11 */ 12 #include <linux/kernel.h> 13 #include <linux/types.h> 14 #include <linux/init.h> 15 #include <linux/bootmem.h> 16 #include <linux/mmzone.h> 17 #include <linux/pci_ids.h> 18 #include <linux/pci.h> 19 #include <linux/bitops.h> 20 #include <linux/ioport.h> 21 #include <linux/suspend.h> 22 #include <asm/e820.h> 23 #include <asm/io.h> 24 #include <asm/gart.h> 25 #include <asm/pci-direct.h> 26 #include <asm/dma.h> 27 #include <asm/k8.h> 28 29 int gart_iommu_aperture; 30 int gart_iommu_aperture_disabled __initdata = 0; 31 int gart_iommu_aperture_allowed __initdata = 0; 32 33 int fallback_aper_order __initdata = 1; /* 64MB */ 34 int fallback_aper_force __initdata = 0; 35 36 int fix_aperture __initdata = 1; 37 38 static struct resource gart_resource = { 39 .name = "GART", 40 .flags = IORESOURCE_MEM, 41 }; 42 43 static void __init insert_aperture_resource(u32 aper_base, u32 aper_size) 44 { 45 gart_resource.start = aper_base; 46 gart_resource.end = aper_base + aper_size - 1; 47 insert_resource(&iomem_resource, &gart_resource); 48 } 49 50 /* This code runs before the PCI subsystem is initialized, so just 51 access the northbridge directly. */ 52 53 static u32 __init allocate_aperture(void) 54 { 55 u32 aper_size; 56 void *p; 57 58 if (fallback_aper_order > 7) 59 fallback_aper_order = 7; 60 aper_size = (32 * 1024 * 1024) << fallback_aper_order; 61 62 /* 63 * Aperture has to be naturally aligned. This means a 2GB aperture 64 * won't have much chance of finding a place in the lower 4GB of 65 * memory. Unfortunately we cannot move it up because that would 66 * make the IOMMU useless. 67 */ 68 p = __alloc_bootmem_nopanic(aper_size, aper_size, 0); 69 if (!p || __pa(p)+aper_size > 0xffffffff) { 70 printk(KERN_ERR 71 "Cannot allocate aperture memory hole (%p,%uK)\n", 72 p, aper_size>>10); 73 if (p) 74 free_bootmem(__pa(p), aper_size); 75 return 0; 76 } 77 printk(KERN_INFO "Mapping aperture over %d KB of RAM @ %lx\n", 78 aper_size >> 10, __pa(p)); 79 insert_aperture_resource((u32)__pa(p), aper_size); 80 register_nosave_region((u32)__pa(p) >> PAGE_SHIFT, 81 (u32)__pa(p+aper_size) >> PAGE_SHIFT); 82 83 return (u32)__pa(p); 84 } 85 86 static int __init aperture_valid(u64 aper_base, u32 aper_size) 87 { 88 if (!aper_base) 89 return 0; 90 91 if (aper_base + aper_size > 0x100000000UL) { 92 printk(KERN_ERR "Aperture beyond 4GB. Ignoring.\n"); 93 return 0; 94 } 95 if (e820_any_mapped(aper_base, aper_base + aper_size, E820_RAM)) { 96 printk(KERN_ERR "Aperture pointing to e820 RAM. Ignoring.\n"); 97 return 0; 98 } 99 if (aper_size < 64*1024*1024) { 100 printk(KERN_ERR "Aperture too small (%d MB)\n", aper_size>>20); 101 return 0; 102 } 103 104 return 1; 105 } 106 107 /* Find a PCI capability */ 108 static __u32 __init find_cap(int num, int slot, int func, int cap) 109 { 110 int bytes; 111 u8 pos; 112 113 if (!(read_pci_config_16(num, slot, func, PCI_STATUS) & 114 PCI_STATUS_CAP_LIST)) 115 return 0; 116 117 pos = read_pci_config_byte(num, slot, func, PCI_CAPABILITY_LIST); 118 for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) { 119 u8 id; 120 121 pos &= ~3; 122 id = read_pci_config_byte(num, slot, func, pos+PCI_CAP_LIST_ID); 123 if (id == 0xff) 124 break; 125 if (id == cap) 126 return pos; 127 pos = read_pci_config_byte(num, slot, func, 128 pos+PCI_CAP_LIST_NEXT); 129 } 130 return 0; 131 } 132 133 /* Read a standard AGPv3 bridge header */ 134 static __u32 __init read_agp(int num, int slot, int func, int cap, u32 *order) 135 { 136 u32 apsize; 137 u32 apsizereg; 138 int nbits; 139 u32 aper_low, aper_hi; 140 u64 aper; 141 142 printk(KERN_INFO "AGP bridge at %02x:%02x:%02x\n", num, slot, func); 143 apsizereg = read_pci_config_16(num, slot, func, cap + 0x14); 144 if (apsizereg == 0xffffffff) { 145 printk(KERN_ERR "APSIZE in AGP bridge unreadable\n"); 146 return 0; 147 } 148 149 apsize = apsizereg & 0xfff; 150 /* Some BIOS use weird encodings not in the AGPv3 table. */ 151 if (apsize & 0xff) 152 apsize |= 0xf00; 153 nbits = hweight16(apsize); 154 *order = 7 - nbits; 155 if ((int)*order < 0) /* < 32MB */ 156 *order = 0; 157 158 aper_low = read_pci_config(num, slot, func, 0x10); 159 aper_hi = read_pci_config(num, slot, func, 0x14); 160 aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32); 161 162 printk(KERN_INFO "Aperture from AGP @ %Lx size %u MB (APSIZE %x)\n", 163 aper, 32 << *order, apsizereg); 164 165 if (!aperture_valid(aper, (32*1024*1024) << *order)) 166 return 0; 167 return (u32)aper; 168 } 169 170 /* 171 * Look for an AGP bridge. Windows only expects the aperture in the 172 * AGP bridge and some BIOS forget to initialize the Northbridge too. 173 * Work around this here. 174 * 175 * Do an PCI bus scan by hand because we're running before the PCI 176 * subsystem. 177 * 178 * All K8 AGP bridges are AGPv3 compliant, so we can do this scan 179 * generically. It's probably overkill to always scan all slots because 180 * the AGP bridges should be always an own bus on the HT hierarchy, 181 * but do it here for future safety. 182 */ 183 static __u32 __init search_agp_bridge(u32 *order, int *valid_agp) 184 { 185 int num, slot, func; 186 187 /* Poor man's PCI discovery */ 188 for (num = 0; num < 256; num++) { 189 for (slot = 0; slot < 32; slot++) { 190 for (func = 0; func < 8; func++) { 191 u32 class, cap; 192 u8 type; 193 class = read_pci_config(num, slot, func, 194 PCI_CLASS_REVISION); 195 if (class == 0xffffffff) 196 break; 197 198 switch (class >> 16) { 199 case PCI_CLASS_BRIDGE_HOST: 200 case PCI_CLASS_BRIDGE_OTHER: /* needed? */ 201 /* AGP bridge? */ 202 cap = find_cap(num, slot, func, 203 PCI_CAP_ID_AGP); 204 if (!cap) 205 break; 206 *valid_agp = 1; 207 return read_agp(num, slot, func, cap, 208 order); 209 } 210 211 /* No multi-function device? */ 212 type = read_pci_config_byte(num, slot, func, 213 PCI_HEADER_TYPE); 214 if (!(type & 0x80)) 215 break; 216 } 217 } 218 } 219 printk(KERN_INFO "No AGP bridge found\n"); 220 221 return 0; 222 } 223 224 static int gart_fix_e820 __initdata = 1; 225 226 static int __init parse_gart_mem(char *p) 227 { 228 if (!p) 229 return -EINVAL; 230 231 if (!strncmp(p, "off", 3)) 232 gart_fix_e820 = 0; 233 else if (!strncmp(p, "on", 2)) 234 gart_fix_e820 = 1; 235 236 return 0; 237 } 238 early_param("gart_fix_e820", parse_gart_mem); 239 240 void __init early_gart_iommu_check(void) 241 { 242 /* 243 * in case it is enabled before, esp for kexec/kdump, 244 * previous kernel already enable that. memset called 245 * by allocate_aperture/__alloc_bootmem_nopanic cause restart. 246 * or second kernel have different position for GART hole. and new 247 * kernel could use hole as RAM that is still used by GART set by 248 * first kernel 249 * or BIOS forget to put that in reserved. 250 * try to update e820 to make that region as reserved. 251 */ 252 int fix, num; 253 u32 ctl; 254 u32 aper_size = 0, aper_order = 0, last_aper_order = 0; 255 u64 aper_base = 0, last_aper_base = 0; 256 int aper_enabled = 0, last_aper_enabled = 0; 257 258 if (!early_pci_allowed()) 259 return; 260 261 fix = 0; 262 for (num = 24; num < 32; num++) { 263 if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00))) 264 continue; 265 266 ctl = read_pci_config(0, num, 3, 0x90); 267 aper_enabled = ctl & 1; 268 aper_order = (ctl >> 1) & 7; 269 aper_size = (32 * 1024 * 1024) << aper_order; 270 aper_base = read_pci_config(0, num, 3, 0x94) & 0x7fff; 271 aper_base <<= 25; 272 273 if ((last_aper_order && aper_order != last_aper_order) || 274 (last_aper_base && aper_base != last_aper_base) || 275 (last_aper_enabled && aper_enabled != last_aper_enabled)) { 276 fix = 1; 277 break; 278 } 279 last_aper_order = aper_order; 280 last_aper_base = aper_base; 281 last_aper_enabled = aper_enabled; 282 } 283 284 if (!fix && !aper_enabled) 285 return; 286 287 if (!aper_base || !aper_size || aper_base + aper_size > 0x100000000UL) 288 fix = 1; 289 290 if (gart_fix_e820 && !fix && aper_enabled) { 291 if (e820_any_mapped(aper_base, aper_base + aper_size, 292 E820_RAM)) { 293 /* reserved it, so we can resuse it in second kernel */ 294 printk(KERN_INFO "update e820 for GART\n"); 295 add_memory_region(aper_base, aper_size, E820_RESERVED); 296 update_e820(); 297 } 298 return; 299 } 300 301 /* different nodes have different setting, disable them all at first*/ 302 for (num = 24; num < 32; num++) { 303 if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00))) 304 continue; 305 306 ctl = read_pci_config(0, num, 3, 0x90); 307 ctl &= ~1; 308 write_pci_config(0, num, 3, 0x90, ctl); 309 } 310 311 } 312 313 void __init gart_iommu_hole_init(void) 314 { 315 u32 aper_size, aper_alloc = 0, aper_order = 0, last_aper_order = 0; 316 u64 aper_base, last_aper_base = 0; 317 int fix, num, valid_agp = 0; 318 int node; 319 320 if (gart_iommu_aperture_disabled || !fix_aperture || 321 !early_pci_allowed()) 322 return; 323 324 printk(KERN_INFO "Checking aperture...\n"); 325 326 fix = 0; 327 node = 0; 328 for (num = 24; num < 32; num++) { 329 if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00))) 330 continue; 331 332 iommu_detected = 1; 333 gart_iommu_aperture = 1; 334 335 aper_order = (read_pci_config(0, num, 3, 0x90) >> 1) & 7; 336 aper_size = (32 * 1024 * 1024) << aper_order; 337 aper_base = read_pci_config(0, num, 3, 0x94) & 0x7fff; 338 aper_base <<= 25; 339 340 printk(KERN_INFO "Node %d: aperture @ %Lx size %u MB\n", 341 node, aper_base, aper_size >> 20); 342 node++; 343 344 if (!aperture_valid(aper_base, aper_size)) { 345 fix = 1; 346 break; 347 } 348 349 if ((last_aper_order && aper_order != last_aper_order) || 350 (last_aper_base && aper_base != last_aper_base)) { 351 fix = 1; 352 break; 353 } 354 last_aper_order = aper_order; 355 last_aper_base = aper_base; 356 } 357 358 if (!fix && !fallback_aper_force) { 359 if (last_aper_base) { 360 unsigned long n = (32 * 1024 * 1024) << last_aper_order; 361 362 insert_aperture_resource((u32)last_aper_base, n); 363 } 364 return; 365 } 366 367 if (!fallback_aper_force) 368 aper_alloc = search_agp_bridge(&aper_order, &valid_agp); 369 370 if (aper_alloc) { 371 /* Got the aperture from the AGP bridge */ 372 } else if (swiotlb && !valid_agp) { 373 /* Do nothing */ 374 } else if ((!no_iommu && end_pfn > MAX_DMA32_PFN) || 375 force_iommu || 376 valid_agp || 377 fallback_aper_force) { 378 printk(KERN_ERR 379 "Your BIOS doesn't leave a aperture memory hole\n"); 380 printk(KERN_ERR 381 "Please enable the IOMMU option in the BIOS setup\n"); 382 printk(KERN_ERR 383 "This costs you %d MB of RAM\n", 384 32 << fallback_aper_order); 385 386 aper_order = fallback_aper_order; 387 aper_alloc = allocate_aperture(); 388 if (!aper_alloc) { 389 /* 390 * Could disable AGP and IOMMU here, but it's 391 * probably not worth it. But the later users 392 * cannot deal with bad apertures and turning 393 * on the aperture over memory causes very 394 * strange problems, so it's better to panic 395 * early. 396 */ 397 panic("Not enough memory for aperture"); 398 } 399 } else { 400 return; 401 } 402 403 /* Fix up the north bridges */ 404 for (num = 24; num < 32; num++) { 405 if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00))) 406 continue; 407 408 /* 409 * Don't enable translation yet. That is done later. 410 * Assume this BIOS didn't initialise the GART so 411 * just overwrite all previous bits 412 */ 413 write_pci_config(0, num, 3, 0x90, aper_order<<1); 414 write_pci_config(0, num, 3, 0x94, aper_alloc>>25); 415 } 416 } 417