1 // SPDX-License-Identifier: GPL-2.0-only 2 #define pr_fmt(fmt) "SMP alternatives: " fmt 3 4 #include <linux/module.h> 5 #include <linux/sched.h> 6 #include <linux/perf_event.h> 7 #include <linux/mutex.h> 8 #include <linux/list.h> 9 #include <linux/stringify.h> 10 #include <linux/highmem.h> 11 #include <linux/mm.h> 12 #include <linux/vmalloc.h> 13 #include <linux/memory.h> 14 #include <linux/stop_machine.h> 15 #include <linux/slab.h> 16 #include <linux/kdebug.h> 17 #include <linux/kprobes.h> 18 #include <linux/mmu_context.h> 19 #include <linux/bsearch.h> 20 #include <linux/sync_core.h> 21 #include <asm/text-patching.h> 22 #include <asm/alternative.h> 23 #include <asm/sections.h> 24 #include <asm/mce.h> 25 #include <asm/nmi.h> 26 #include <asm/cacheflush.h> 27 #include <asm/tlbflush.h> 28 #include <asm/insn.h> 29 #include <asm/io.h> 30 #include <asm/fixmap.h> 31 #include <asm/paravirt.h> 32 #include <asm/asm-prototypes.h> 33 34 int __read_mostly alternatives_patched; 35 36 EXPORT_SYMBOL_GPL(alternatives_patched); 37 38 #define MAX_PATCH_LEN (255-1) 39 40 #define DA_ALL (~0) 41 #define DA_ALT 0x01 42 #define DA_RET 0x02 43 #define DA_RETPOLINE 0x04 44 #define DA_ENDBR 0x08 45 #define DA_SMP 0x10 46 47 static unsigned int __initdata_or_module debug_alternative; 48 49 static int __init debug_alt(char *str) 50 { 51 if (str && *str == '=') 52 str++; 53 54 if (!str || kstrtouint(str, 0, &debug_alternative)) 55 debug_alternative = DA_ALL; 56 57 return 1; 58 } 59 __setup("debug-alternative", debug_alt); 60 61 static int noreplace_smp; 62 63 static int __init setup_noreplace_smp(char *str) 64 { 65 noreplace_smp = 1; 66 return 1; 67 } 68 __setup("noreplace-smp", setup_noreplace_smp); 69 70 #define DPRINTK(type, fmt, args...) \ 71 do { \ 72 if (debug_alternative & DA_##type) \ 73 printk(KERN_DEBUG pr_fmt(fmt) "\n", ##args); \ 74 } while (0) 75 76 #define DUMP_BYTES(type, buf, len, fmt, args...) \ 77 do { \ 78 if (unlikely(debug_alternative & DA_##type)) { \ 79 int j; \ 80 \ 81 if (!(len)) \ 82 break; \ 83 \ 84 printk(KERN_DEBUG pr_fmt(fmt), ##args); \ 85 for (j = 0; j < (len) - 1; j++) \ 86 printk(KERN_CONT "%02hhx ", buf[j]); \ 87 printk(KERN_CONT "%02hhx\n", buf[j]); \ 88 } \ 89 } while (0) 90 91 static const unsigned char x86nops[] = 92 { 93 BYTES_NOP1, 94 BYTES_NOP2, 95 BYTES_NOP3, 96 BYTES_NOP4, 97 BYTES_NOP5, 98 BYTES_NOP6, 99 BYTES_NOP7, 100 BYTES_NOP8, 101 #ifdef CONFIG_64BIT 102 BYTES_NOP9, 103 BYTES_NOP10, 104 BYTES_NOP11, 105 #endif 106 }; 107 108 const unsigned char * const x86_nops[ASM_NOP_MAX+1] = 109 { 110 NULL, 111 x86nops, 112 x86nops + 1, 113 x86nops + 1 + 2, 114 x86nops + 1 + 2 + 3, 115 x86nops + 1 + 2 + 3 + 4, 116 x86nops + 1 + 2 + 3 + 4 + 5, 117 x86nops + 1 + 2 + 3 + 4 + 5 + 6, 118 x86nops + 1 + 2 + 3 + 4 + 5 + 6 + 7, 119 #ifdef CONFIG_64BIT 120 x86nops + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8, 121 x86nops + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9, 122 x86nops + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10, 123 #endif 124 }; 125 126 /* 127 * Fill the buffer with a single effective instruction of size @len. 128 * 129 * In order not to issue an ORC stack depth tracking CFI entry (Call Frame Info) 130 * for every single-byte NOP, try to generate the maximally available NOP of 131 * size <= ASM_NOP_MAX such that only a single CFI entry is generated (vs one for 132 * each single-byte NOPs). If @len to fill out is > ASM_NOP_MAX, pad with INT3 and 133 * *jump* over instead of executing long and daft NOPs. 134 */ 135 static void __init_or_module add_nop(u8 *instr, unsigned int len) 136 { 137 u8 *target = instr + len; 138 139 if (!len) 140 return; 141 142 if (len <= ASM_NOP_MAX) { 143 memcpy(instr, x86_nops[len], len); 144 return; 145 } 146 147 if (len < 128) { 148 __text_gen_insn(instr, JMP8_INSN_OPCODE, instr, target, JMP8_INSN_SIZE); 149 instr += JMP8_INSN_SIZE; 150 } else { 151 __text_gen_insn(instr, JMP32_INSN_OPCODE, instr, target, JMP32_INSN_SIZE); 152 instr += JMP32_INSN_SIZE; 153 } 154 155 for (;instr < target; instr++) 156 *instr = INT3_INSN_OPCODE; 157 } 158 159 extern s32 __retpoline_sites[], __retpoline_sites_end[]; 160 extern s32 __return_sites[], __return_sites_end[]; 161 extern s32 __cfi_sites[], __cfi_sites_end[]; 162 extern s32 __ibt_endbr_seal[], __ibt_endbr_seal_end[]; 163 extern struct alt_instr __alt_instructions[], __alt_instructions_end[]; 164 extern s32 __smp_locks[], __smp_locks_end[]; 165 void text_poke_early(void *addr, const void *opcode, size_t len); 166 167 /* 168 * Matches NOP and NOPL, not any of the other possible NOPs. 169 */ 170 static bool insn_is_nop(struct insn *insn) 171 { 172 /* Anything NOP, but no REP NOP */ 173 if (insn->opcode.bytes[0] == 0x90 && 174 (!insn->prefixes.nbytes || insn->prefixes.bytes[0] != 0xF3)) 175 return true; 176 177 /* NOPL */ 178 if (insn->opcode.bytes[0] == 0x0F && insn->opcode.bytes[1] == 0x1F) 179 return true; 180 181 /* TODO: more nops */ 182 183 return false; 184 } 185 186 /* 187 * Find the offset of the first non-NOP instruction starting at @offset 188 * but no further than @len. 189 */ 190 static int skip_nops(u8 *instr, int offset, int len) 191 { 192 struct insn insn; 193 194 for (; offset < len; offset += insn.length) { 195 if (insn_decode_kernel(&insn, &instr[offset])) 196 break; 197 198 if (!insn_is_nop(&insn)) 199 break; 200 } 201 202 return offset; 203 } 204 205 /* 206 * Optimize a sequence of NOPs, possibly preceded by an unconditional jump 207 * to the end of the NOP sequence into a single NOP. 208 */ 209 static bool __init_or_module 210 __optimize_nops(u8 *instr, size_t len, struct insn *insn, int *next, int *prev, int *target) 211 { 212 int i = *next - insn->length; 213 214 switch (insn->opcode.bytes[0]) { 215 case JMP8_INSN_OPCODE: 216 case JMP32_INSN_OPCODE: 217 *prev = i; 218 *target = *next + insn->immediate.value; 219 return false; 220 } 221 222 if (insn_is_nop(insn)) { 223 int nop = i; 224 225 *next = skip_nops(instr, *next, len); 226 if (*target && *next == *target) 227 nop = *prev; 228 229 add_nop(instr + nop, *next - nop); 230 DUMP_BYTES(ALT, instr, len, "%px: [%d:%d) optimized NOPs: ", instr, nop, *next); 231 return true; 232 } 233 234 *target = 0; 235 return false; 236 } 237 238 /* 239 * "noinline" to cause control flow change and thus invalidate I$ and 240 * cause refetch after modification. 241 */ 242 static void __init_or_module noinline optimize_nops(u8 *instr, size_t len) 243 { 244 int prev, target = 0; 245 246 for (int next, i = 0; i < len; i = next) { 247 struct insn insn; 248 249 if (insn_decode_kernel(&insn, &instr[i])) 250 return; 251 252 next = i + insn.length; 253 254 __optimize_nops(instr, len, &insn, &next, &prev, &target); 255 } 256 } 257 258 /* 259 * In this context, "source" is where the instructions are placed in the 260 * section .altinstr_replacement, for example during kernel build by the 261 * toolchain. 262 * "Destination" is where the instructions are being patched in by this 263 * machinery. 264 * 265 * The source offset is: 266 * 267 * src_imm = target - src_next_ip (1) 268 * 269 * and the target offset is: 270 * 271 * dst_imm = target - dst_next_ip (2) 272 * 273 * so rework (1) as an expression for target like: 274 * 275 * target = src_imm + src_next_ip (1a) 276 * 277 * and substitute in (2) to get: 278 * 279 * dst_imm = (src_imm + src_next_ip) - dst_next_ip (3) 280 * 281 * Now, since the instruction stream is 'identical' at src and dst (it 282 * is being copied after all) it can be stated that: 283 * 284 * src_next_ip = src + ip_offset 285 * dst_next_ip = dst + ip_offset (4) 286 * 287 * Substitute (4) in (3) and observe ip_offset being cancelled out to 288 * obtain: 289 * 290 * dst_imm = src_imm + (src + ip_offset) - (dst + ip_offset) 291 * = src_imm + src - dst + ip_offset - ip_offset 292 * = src_imm + src - dst (5) 293 * 294 * IOW, only the relative displacement of the code block matters. 295 */ 296 297 #define apply_reloc_n(n_, p_, d_) \ 298 do { \ 299 s32 v = *(s##n_ *)(p_); \ 300 v += (d_); \ 301 BUG_ON((v >> 31) != (v >> (n_-1))); \ 302 *(s##n_ *)(p_) = (s##n_)v; \ 303 } while (0) 304 305 306 static __always_inline 307 void apply_reloc(int n, void *ptr, uintptr_t diff) 308 { 309 switch (n) { 310 case 1: apply_reloc_n(8, ptr, diff); break; 311 case 2: apply_reloc_n(16, ptr, diff); break; 312 case 4: apply_reloc_n(32, ptr, diff); break; 313 default: BUG(); 314 } 315 } 316 317 static __always_inline 318 bool need_reloc(unsigned long offset, u8 *src, size_t src_len) 319 { 320 u8 *target = src + offset; 321 /* 322 * If the target is inside the patched block, it's relative to the 323 * block itself and does not need relocation. 324 */ 325 return (target < src || target > src + src_len); 326 } 327 328 static void __init_or_module noinline 329 apply_relocation(u8 *buf, size_t len, u8 *dest, u8 *src, size_t src_len) 330 { 331 int prev, target = 0; 332 333 for (int next, i = 0; i < len; i = next) { 334 struct insn insn; 335 336 if (WARN_ON_ONCE(insn_decode_kernel(&insn, &buf[i]))) 337 return; 338 339 next = i + insn.length; 340 341 if (__optimize_nops(buf, len, &insn, &next, &prev, &target)) 342 continue; 343 344 switch (insn.opcode.bytes[0]) { 345 case 0x0f: 346 if (insn.opcode.bytes[1] < 0x80 || 347 insn.opcode.bytes[1] > 0x8f) 348 break; 349 350 fallthrough; /* Jcc.d32 */ 351 case 0x70 ... 0x7f: /* Jcc.d8 */ 352 case JMP8_INSN_OPCODE: 353 case JMP32_INSN_OPCODE: 354 case CALL_INSN_OPCODE: 355 if (need_reloc(next + insn.immediate.value, src, src_len)) { 356 apply_reloc(insn.immediate.nbytes, 357 buf + i + insn_offset_immediate(&insn), 358 src - dest); 359 } 360 361 /* 362 * Where possible, convert JMP.d32 into JMP.d8. 363 */ 364 if (insn.opcode.bytes[0] == JMP32_INSN_OPCODE) { 365 s32 imm = insn.immediate.value; 366 imm += src - dest; 367 imm += JMP32_INSN_SIZE - JMP8_INSN_SIZE; 368 if ((imm >> 31) == (imm >> 7)) { 369 buf[i+0] = JMP8_INSN_OPCODE; 370 buf[i+1] = (s8)imm; 371 372 memset(&buf[i+2], INT3_INSN_OPCODE, insn.length - 2); 373 } 374 } 375 break; 376 } 377 378 if (insn_rip_relative(&insn)) { 379 if (need_reloc(next + insn.displacement.value, src, src_len)) { 380 apply_reloc(insn.displacement.nbytes, 381 buf + i + insn_offset_displacement(&insn), 382 src - dest); 383 } 384 } 385 } 386 } 387 388 /* 389 * Replace instructions with better alternatives for this CPU type. This runs 390 * before SMP is initialized to avoid SMP problems with self modifying code. 391 * This implies that asymmetric systems where APs have less capabilities than 392 * the boot processor are not handled. Tough. Make sure you disable such 393 * features by hand. 394 * 395 * Marked "noinline" to cause control flow change and thus insn cache 396 * to refetch changed I$ lines. 397 */ 398 void __init_or_module noinline apply_alternatives(struct alt_instr *start, 399 struct alt_instr *end) 400 { 401 struct alt_instr *a; 402 u8 *instr, *replacement; 403 u8 insn_buff[MAX_PATCH_LEN]; 404 405 DPRINTK(ALT, "alt table %px, -> %px", start, end); 406 /* 407 * The scan order should be from start to end. A later scanned 408 * alternative code can overwrite previously scanned alternative code. 409 * Some kernel functions (e.g. memcpy, memset, etc) use this order to 410 * patch code. 411 * 412 * So be careful if you want to change the scan order to any other 413 * order. 414 */ 415 for (a = start; a < end; a++) { 416 int insn_buff_sz = 0; 417 418 instr = (u8 *)&a->instr_offset + a->instr_offset; 419 replacement = (u8 *)&a->repl_offset + a->repl_offset; 420 BUG_ON(a->instrlen > sizeof(insn_buff)); 421 BUG_ON(a->cpuid >= (NCAPINTS + NBUGINTS) * 32); 422 423 /* 424 * Patch if either: 425 * - feature is present 426 * - feature not present but ALT_FLAG_NOT is set to mean, 427 * patch if feature is *NOT* present. 428 */ 429 if (!boot_cpu_has(a->cpuid) == !(a->flags & ALT_FLAG_NOT)) { 430 optimize_nops(instr, a->instrlen); 431 continue; 432 } 433 434 DPRINTK(ALT, "feat: %s%d*32+%d, old: (%pS (%px) len: %d), repl: (%px, len: %d)", 435 (a->flags & ALT_FLAG_NOT) ? "!" : "", 436 a->cpuid >> 5, 437 a->cpuid & 0x1f, 438 instr, instr, a->instrlen, 439 replacement, a->replacementlen); 440 441 memcpy(insn_buff, replacement, a->replacementlen); 442 insn_buff_sz = a->replacementlen; 443 444 for (; insn_buff_sz < a->instrlen; insn_buff_sz++) 445 insn_buff[insn_buff_sz] = 0x90; 446 447 apply_relocation(insn_buff, a->instrlen, instr, replacement, a->replacementlen); 448 449 DUMP_BYTES(ALT, instr, a->instrlen, "%px: old_insn: ", instr); 450 DUMP_BYTES(ALT, replacement, a->replacementlen, "%px: rpl_insn: ", replacement); 451 DUMP_BYTES(ALT, insn_buff, insn_buff_sz, "%px: final_insn: ", instr); 452 453 text_poke_early(instr, insn_buff, insn_buff_sz); 454 } 455 } 456 457 static inline bool is_jcc32(struct insn *insn) 458 { 459 /* Jcc.d32 second opcode byte is in the range: 0x80-0x8f */ 460 return insn->opcode.bytes[0] == 0x0f && (insn->opcode.bytes[1] & 0xf0) == 0x80; 461 } 462 463 #if defined(CONFIG_RETPOLINE) && defined(CONFIG_OBJTOOL) 464 465 /* 466 * CALL/JMP *%\reg 467 */ 468 static int emit_indirect(int op, int reg, u8 *bytes) 469 { 470 int i = 0; 471 u8 modrm; 472 473 switch (op) { 474 case CALL_INSN_OPCODE: 475 modrm = 0x10; /* Reg = 2; CALL r/m */ 476 break; 477 478 case JMP32_INSN_OPCODE: 479 modrm = 0x20; /* Reg = 4; JMP r/m */ 480 break; 481 482 default: 483 WARN_ON_ONCE(1); 484 return -1; 485 } 486 487 if (reg >= 8) { 488 bytes[i++] = 0x41; /* REX.B prefix */ 489 reg -= 8; 490 } 491 492 modrm |= 0xc0; /* Mod = 3 */ 493 modrm += reg; 494 495 bytes[i++] = 0xff; /* opcode */ 496 bytes[i++] = modrm; 497 498 return i; 499 } 500 501 static int emit_call_track_retpoline(void *addr, struct insn *insn, int reg, u8 *bytes) 502 { 503 u8 op = insn->opcode.bytes[0]; 504 int i = 0; 505 506 /* 507 * Clang does 'weird' Jcc __x86_indirect_thunk_r11 conditional 508 * tail-calls. Deal with them. 509 */ 510 if (is_jcc32(insn)) { 511 bytes[i++] = op; 512 op = insn->opcode.bytes[1]; 513 goto clang_jcc; 514 } 515 516 if (insn->length == 6) 517 bytes[i++] = 0x2e; /* CS-prefix */ 518 519 switch (op) { 520 case CALL_INSN_OPCODE: 521 __text_gen_insn(bytes+i, op, addr+i, 522 __x86_indirect_call_thunk_array[reg], 523 CALL_INSN_SIZE); 524 i += CALL_INSN_SIZE; 525 break; 526 527 case JMP32_INSN_OPCODE: 528 clang_jcc: 529 __text_gen_insn(bytes+i, op, addr+i, 530 __x86_indirect_jump_thunk_array[reg], 531 JMP32_INSN_SIZE); 532 i += JMP32_INSN_SIZE; 533 break; 534 535 default: 536 WARN(1, "%pS %px %*ph\n", addr, addr, 6, addr); 537 return -1; 538 } 539 540 WARN_ON_ONCE(i != insn->length); 541 542 return i; 543 } 544 545 /* 546 * Rewrite the compiler generated retpoline thunk calls. 547 * 548 * For spectre_v2=off (!X86_FEATURE_RETPOLINE), rewrite them into immediate 549 * indirect instructions, avoiding the extra indirection. 550 * 551 * For example, convert: 552 * 553 * CALL __x86_indirect_thunk_\reg 554 * 555 * into: 556 * 557 * CALL *%\reg 558 * 559 * It also tries to inline spectre_v2=retpoline,lfence when size permits. 560 */ 561 static int patch_retpoline(void *addr, struct insn *insn, u8 *bytes) 562 { 563 retpoline_thunk_t *target; 564 int reg, ret, i = 0; 565 u8 op, cc; 566 567 target = addr + insn->length + insn->immediate.value; 568 reg = target - __x86_indirect_thunk_array; 569 570 if (WARN_ON_ONCE(reg & ~0xf)) 571 return -1; 572 573 /* If anyone ever does: CALL/JMP *%rsp, we're in deep trouble. */ 574 BUG_ON(reg == 4); 575 576 if (cpu_feature_enabled(X86_FEATURE_RETPOLINE) && 577 !cpu_feature_enabled(X86_FEATURE_RETPOLINE_LFENCE)) { 578 if (cpu_feature_enabled(X86_FEATURE_CALL_DEPTH)) 579 return emit_call_track_retpoline(addr, insn, reg, bytes); 580 581 return -1; 582 } 583 584 op = insn->opcode.bytes[0]; 585 586 /* 587 * Convert: 588 * 589 * Jcc.d32 __x86_indirect_thunk_\reg 590 * 591 * into: 592 * 593 * Jncc.d8 1f 594 * [ LFENCE ] 595 * JMP *%\reg 596 * [ NOP ] 597 * 1: 598 */ 599 if (is_jcc32(insn)) { 600 cc = insn->opcode.bytes[1] & 0xf; 601 cc ^= 1; /* invert condition */ 602 603 bytes[i++] = 0x70 + cc; /* Jcc.d8 */ 604 bytes[i++] = insn->length - 2; /* sizeof(Jcc.d8) == 2 */ 605 606 /* Continue as if: JMP.d32 __x86_indirect_thunk_\reg */ 607 op = JMP32_INSN_OPCODE; 608 } 609 610 /* 611 * For RETPOLINE_LFENCE: prepend the indirect CALL/JMP with an LFENCE. 612 */ 613 if (cpu_feature_enabled(X86_FEATURE_RETPOLINE_LFENCE)) { 614 bytes[i++] = 0x0f; 615 bytes[i++] = 0xae; 616 bytes[i++] = 0xe8; /* LFENCE */ 617 } 618 619 ret = emit_indirect(op, reg, bytes + i); 620 if (ret < 0) 621 return ret; 622 i += ret; 623 624 /* 625 * The compiler is supposed to EMIT an INT3 after every unconditional 626 * JMP instruction due to AMD BTC. However, if the compiler is too old 627 * or SLS isn't enabled, we still need an INT3 after indirect JMPs 628 * even on Intel. 629 */ 630 if (op == JMP32_INSN_OPCODE && i < insn->length) 631 bytes[i++] = INT3_INSN_OPCODE; 632 633 for (; i < insn->length;) 634 bytes[i++] = BYTES_NOP1; 635 636 return i; 637 } 638 639 /* 640 * Generated by 'objtool --retpoline'. 641 */ 642 void __init_or_module noinline apply_retpolines(s32 *start, s32 *end) 643 { 644 s32 *s; 645 646 for (s = start; s < end; s++) { 647 void *addr = (void *)s + *s; 648 struct insn insn; 649 int len, ret; 650 u8 bytes[16]; 651 u8 op1, op2; 652 653 ret = insn_decode_kernel(&insn, addr); 654 if (WARN_ON_ONCE(ret < 0)) 655 continue; 656 657 op1 = insn.opcode.bytes[0]; 658 op2 = insn.opcode.bytes[1]; 659 660 switch (op1) { 661 case CALL_INSN_OPCODE: 662 case JMP32_INSN_OPCODE: 663 break; 664 665 case 0x0f: /* escape */ 666 if (op2 >= 0x80 && op2 <= 0x8f) 667 break; 668 fallthrough; 669 default: 670 WARN_ON_ONCE(1); 671 continue; 672 } 673 674 DPRINTK(RETPOLINE, "retpoline at: %pS (%px) len: %d to: %pS", 675 addr, addr, insn.length, 676 addr + insn.length + insn.immediate.value); 677 678 len = patch_retpoline(addr, &insn, bytes); 679 if (len == insn.length) { 680 optimize_nops(bytes, len); 681 DUMP_BYTES(RETPOLINE, ((u8*)addr), len, "%px: orig: ", addr); 682 DUMP_BYTES(RETPOLINE, ((u8*)bytes), len, "%px: repl: ", addr); 683 text_poke_early(addr, bytes, len); 684 } 685 } 686 } 687 688 #ifdef CONFIG_RETHUNK 689 690 #ifdef CONFIG_CALL_THUNKS 691 void (*x86_return_thunk)(void) __ro_after_init = &__x86_return_thunk; 692 #endif 693 694 /* 695 * Rewrite the compiler generated return thunk tail-calls. 696 * 697 * For example, convert: 698 * 699 * JMP __x86_return_thunk 700 * 701 * into: 702 * 703 * RET 704 */ 705 static int patch_return(void *addr, struct insn *insn, u8 *bytes) 706 { 707 int i = 0; 708 709 /* Patch the custom return thunks... */ 710 if (cpu_feature_enabled(X86_FEATURE_RETHUNK)) { 711 i = JMP32_INSN_SIZE; 712 __text_gen_insn(bytes, JMP32_INSN_OPCODE, addr, x86_return_thunk, i); 713 } else { 714 /* ... or patch them out if not needed. */ 715 bytes[i++] = RET_INSN_OPCODE; 716 } 717 718 for (; i < insn->length;) 719 bytes[i++] = INT3_INSN_OPCODE; 720 return i; 721 } 722 723 void __init_or_module noinline apply_returns(s32 *start, s32 *end) 724 { 725 s32 *s; 726 727 /* 728 * Do not patch out the default return thunks if those needed are the 729 * ones generated by the compiler. 730 */ 731 if (cpu_feature_enabled(X86_FEATURE_RETHUNK) && 732 (x86_return_thunk == __x86_return_thunk)) 733 return; 734 735 for (s = start; s < end; s++) { 736 void *dest = NULL, *addr = (void *)s + *s; 737 struct insn insn; 738 int len, ret; 739 u8 bytes[16]; 740 u8 op; 741 742 ret = insn_decode_kernel(&insn, addr); 743 if (WARN_ON_ONCE(ret < 0)) 744 continue; 745 746 op = insn.opcode.bytes[0]; 747 if (op == JMP32_INSN_OPCODE) 748 dest = addr + insn.length + insn.immediate.value; 749 750 if (__static_call_fixup(addr, op, dest) || 751 WARN_ONCE(dest != &__x86_return_thunk, 752 "missing return thunk: %pS-%pS: %*ph", 753 addr, dest, 5, addr)) 754 continue; 755 756 DPRINTK(RET, "return thunk at: %pS (%px) len: %d to: %pS", 757 addr, addr, insn.length, 758 addr + insn.length + insn.immediate.value); 759 760 len = patch_return(addr, &insn, bytes); 761 if (len == insn.length) { 762 DUMP_BYTES(RET, ((u8*)addr), len, "%px: orig: ", addr); 763 DUMP_BYTES(RET, ((u8*)bytes), len, "%px: repl: ", addr); 764 text_poke_early(addr, bytes, len); 765 } 766 } 767 } 768 #else 769 void __init_or_module noinline apply_returns(s32 *start, s32 *end) { } 770 #endif /* CONFIG_RETHUNK */ 771 772 #else /* !CONFIG_RETPOLINE || !CONFIG_OBJTOOL */ 773 774 void __init_or_module noinline apply_retpolines(s32 *start, s32 *end) { } 775 void __init_or_module noinline apply_returns(s32 *start, s32 *end) { } 776 777 #endif /* CONFIG_RETPOLINE && CONFIG_OBJTOOL */ 778 779 #ifdef CONFIG_X86_KERNEL_IBT 780 781 static void __init_or_module poison_endbr(void *addr, bool warn) 782 { 783 u32 endbr, poison = gen_endbr_poison(); 784 785 if (WARN_ON_ONCE(get_kernel_nofault(endbr, addr))) 786 return; 787 788 if (!is_endbr(endbr)) { 789 WARN_ON_ONCE(warn); 790 return; 791 } 792 793 DPRINTK(ENDBR, "ENDBR at: %pS (%px)", addr, addr); 794 795 /* 796 * When we have IBT, the lack of ENDBR will trigger #CP 797 */ 798 DUMP_BYTES(ENDBR, ((u8*)addr), 4, "%px: orig: ", addr); 799 DUMP_BYTES(ENDBR, ((u8*)&poison), 4, "%px: repl: ", addr); 800 text_poke_early(addr, &poison, 4); 801 } 802 803 /* 804 * Generated by: objtool --ibt 805 */ 806 void __init_or_module noinline apply_ibt_endbr(s32 *start, s32 *end) 807 { 808 s32 *s; 809 810 for (s = start; s < end; s++) { 811 void *addr = (void *)s + *s; 812 813 poison_endbr(addr, true); 814 if (IS_ENABLED(CONFIG_FINEIBT)) 815 poison_endbr(addr - 16, false); 816 } 817 } 818 819 #else 820 821 void __init_or_module apply_ibt_endbr(s32 *start, s32 *end) { } 822 823 #endif /* CONFIG_X86_KERNEL_IBT */ 824 825 #ifdef CONFIG_FINEIBT 826 827 enum cfi_mode { 828 CFI_DEFAULT, 829 CFI_OFF, 830 CFI_KCFI, 831 CFI_FINEIBT, 832 }; 833 834 static enum cfi_mode cfi_mode __ro_after_init = CFI_DEFAULT; 835 static bool cfi_rand __ro_after_init = true; 836 static u32 cfi_seed __ro_after_init; 837 838 /* 839 * Re-hash the CFI hash with a boot-time seed while making sure the result is 840 * not a valid ENDBR instruction. 841 */ 842 static u32 cfi_rehash(u32 hash) 843 { 844 hash ^= cfi_seed; 845 while (unlikely(is_endbr(hash) || is_endbr(-hash))) { 846 bool lsb = hash & 1; 847 hash >>= 1; 848 if (lsb) 849 hash ^= 0x80200003; 850 } 851 return hash; 852 } 853 854 static __init int cfi_parse_cmdline(char *str) 855 { 856 if (!str) 857 return -EINVAL; 858 859 while (str) { 860 char *next = strchr(str, ','); 861 if (next) { 862 *next = 0; 863 next++; 864 } 865 866 if (!strcmp(str, "auto")) { 867 cfi_mode = CFI_DEFAULT; 868 } else if (!strcmp(str, "off")) { 869 cfi_mode = CFI_OFF; 870 cfi_rand = false; 871 } else if (!strcmp(str, "kcfi")) { 872 cfi_mode = CFI_KCFI; 873 } else if (!strcmp(str, "fineibt")) { 874 cfi_mode = CFI_FINEIBT; 875 } else if (!strcmp(str, "norand")) { 876 cfi_rand = false; 877 } else { 878 pr_err("Ignoring unknown cfi option (%s).", str); 879 } 880 881 str = next; 882 } 883 884 return 0; 885 } 886 early_param("cfi", cfi_parse_cmdline); 887 888 /* 889 * kCFI FineIBT 890 * 891 * __cfi_\func: __cfi_\func: 892 * movl $0x12345678,%eax // 5 endbr64 // 4 893 * nop subl $0x12345678,%r10d // 7 894 * nop jz 1f // 2 895 * nop ud2 // 2 896 * nop 1: nop // 1 897 * nop 898 * nop 899 * nop 900 * nop 901 * nop 902 * nop 903 * nop 904 * 905 * 906 * caller: caller: 907 * movl $(-0x12345678),%r10d // 6 movl $0x12345678,%r10d // 6 908 * addl $-15(%r11),%r10d // 4 sub $16,%r11 // 4 909 * je 1f // 2 nop4 // 4 910 * ud2 // 2 911 * 1: call __x86_indirect_thunk_r11 // 5 call *%r11; nop2; // 5 912 * 913 */ 914 915 asm( ".pushsection .rodata \n" 916 "fineibt_preamble_start: \n" 917 " endbr64 \n" 918 " subl $0x12345678, %r10d \n" 919 " je fineibt_preamble_end \n" 920 " ud2 \n" 921 " nop \n" 922 "fineibt_preamble_end: \n" 923 ".popsection\n" 924 ); 925 926 extern u8 fineibt_preamble_start[]; 927 extern u8 fineibt_preamble_end[]; 928 929 #define fineibt_preamble_size (fineibt_preamble_end - fineibt_preamble_start) 930 #define fineibt_preamble_hash 7 931 932 asm( ".pushsection .rodata \n" 933 "fineibt_caller_start: \n" 934 " movl $0x12345678, %r10d \n" 935 " sub $16, %r11 \n" 936 ASM_NOP4 937 "fineibt_caller_end: \n" 938 ".popsection \n" 939 ); 940 941 extern u8 fineibt_caller_start[]; 942 extern u8 fineibt_caller_end[]; 943 944 #define fineibt_caller_size (fineibt_caller_end - fineibt_caller_start) 945 #define fineibt_caller_hash 2 946 947 #define fineibt_caller_jmp (fineibt_caller_size - 2) 948 949 static u32 decode_preamble_hash(void *addr) 950 { 951 u8 *p = addr; 952 953 /* b8 78 56 34 12 mov $0x12345678,%eax */ 954 if (p[0] == 0xb8) 955 return *(u32 *)(addr + 1); 956 957 return 0; /* invalid hash value */ 958 } 959 960 static u32 decode_caller_hash(void *addr) 961 { 962 u8 *p = addr; 963 964 /* 41 ba 78 56 34 12 mov $0x12345678,%r10d */ 965 if (p[0] == 0x41 && p[1] == 0xba) 966 return -*(u32 *)(addr + 2); 967 968 /* e8 0c 78 56 34 12 jmp.d8 +12 */ 969 if (p[0] == JMP8_INSN_OPCODE && p[1] == fineibt_caller_jmp) 970 return -*(u32 *)(addr + 2); 971 972 return 0; /* invalid hash value */ 973 } 974 975 /* .retpoline_sites */ 976 static int cfi_disable_callers(s32 *start, s32 *end) 977 { 978 /* 979 * Disable kCFI by patching in a JMP.d8, this leaves the hash immediate 980 * in tact for later usage. Also see decode_caller_hash() and 981 * cfi_rewrite_callers(). 982 */ 983 const u8 jmp[] = { JMP8_INSN_OPCODE, fineibt_caller_jmp }; 984 s32 *s; 985 986 for (s = start; s < end; s++) { 987 void *addr = (void *)s + *s; 988 u32 hash; 989 990 addr -= fineibt_caller_size; 991 hash = decode_caller_hash(addr); 992 if (!hash) /* nocfi callers */ 993 continue; 994 995 text_poke_early(addr, jmp, 2); 996 } 997 998 return 0; 999 } 1000 1001 static int cfi_enable_callers(s32 *start, s32 *end) 1002 { 1003 /* 1004 * Re-enable kCFI, undo what cfi_disable_callers() did. 1005 */ 1006 const u8 mov[] = { 0x41, 0xba }; 1007 s32 *s; 1008 1009 for (s = start; s < end; s++) { 1010 void *addr = (void *)s + *s; 1011 u32 hash; 1012 1013 addr -= fineibt_caller_size; 1014 hash = decode_caller_hash(addr); 1015 if (!hash) /* nocfi callers */ 1016 continue; 1017 1018 text_poke_early(addr, mov, 2); 1019 } 1020 1021 return 0; 1022 } 1023 1024 /* .cfi_sites */ 1025 static int cfi_rand_preamble(s32 *start, s32 *end) 1026 { 1027 s32 *s; 1028 1029 for (s = start; s < end; s++) { 1030 void *addr = (void *)s + *s; 1031 u32 hash; 1032 1033 hash = decode_preamble_hash(addr); 1034 if (WARN(!hash, "no CFI hash found at: %pS %px %*ph\n", 1035 addr, addr, 5, addr)) 1036 return -EINVAL; 1037 1038 hash = cfi_rehash(hash); 1039 text_poke_early(addr + 1, &hash, 4); 1040 } 1041 1042 return 0; 1043 } 1044 1045 static int cfi_rewrite_preamble(s32 *start, s32 *end) 1046 { 1047 s32 *s; 1048 1049 for (s = start; s < end; s++) { 1050 void *addr = (void *)s + *s; 1051 u32 hash; 1052 1053 hash = decode_preamble_hash(addr); 1054 if (WARN(!hash, "no CFI hash found at: %pS %px %*ph\n", 1055 addr, addr, 5, addr)) 1056 return -EINVAL; 1057 1058 text_poke_early(addr, fineibt_preamble_start, fineibt_preamble_size); 1059 WARN_ON(*(u32 *)(addr + fineibt_preamble_hash) != 0x12345678); 1060 text_poke_early(addr + fineibt_preamble_hash, &hash, 4); 1061 } 1062 1063 return 0; 1064 } 1065 1066 /* .retpoline_sites */ 1067 static int cfi_rand_callers(s32 *start, s32 *end) 1068 { 1069 s32 *s; 1070 1071 for (s = start; s < end; s++) { 1072 void *addr = (void *)s + *s; 1073 u32 hash; 1074 1075 addr -= fineibt_caller_size; 1076 hash = decode_caller_hash(addr); 1077 if (hash) { 1078 hash = -cfi_rehash(hash); 1079 text_poke_early(addr + 2, &hash, 4); 1080 } 1081 } 1082 1083 return 0; 1084 } 1085 1086 static int cfi_rewrite_callers(s32 *start, s32 *end) 1087 { 1088 s32 *s; 1089 1090 for (s = start; s < end; s++) { 1091 void *addr = (void *)s + *s; 1092 u32 hash; 1093 1094 addr -= fineibt_caller_size; 1095 hash = decode_caller_hash(addr); 1096 if (hash) { 1097 text_poke_early(addr, fineibt_caller_start, fineibt_caller_size); 1098 WARN_ON(*(u32 *)(addr + fineibt_caller_hash) != 0x12345678); 1099 text_poke_early(addr + fineibt_caller_hash, &hash, 4); 1100 } 1101 /* rely on apply_retpolines() */ 1102 } 1103 1104 return 0; 1105 } 1106 1107 static void __apply_fineibt(s32 *start_retpoline, s32 *end_retpoline, 1108 s32 *start_cfi, s32 *end_cfi, bool builtin) 1109 { 1110 int ret; 1111 1112 if (WARN_ONCE(fineibt_preamble_size != 16, 1113 "FineIBT preamble wrong size: %ld", fineibt_preamble_size)) 1114 return; 1115 1116 if (cfi_mode == CFI_DEFAULT) { 1117 cfi_mode = CFI_KCFI; 1118 if (HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT)) 1119 cfi_mode = CFI_FINEIBT; 1120 } 1121 1122 /* 1123 * Rewrite the callers to not use the __cfi_ stubs, such that we might 1124 * rewrite them. This disables all CFI. If this succeeds but any of the 1125 * later stages fails, we're without CFI. 1126 */ 1127 ret = cfi_disable_callers(start_retpoline, end_retpoline); 1128 if (ret) 1129 goto err; 1130 1131 if (cfi_rand) { 1132 if (builtin) 1133 cfi_seed = get_random_u32(); 1134 1135 ret = cfi_rand_preamble(start_cfi, end_cfi); 1136 if (ret) 1137 goto err; 1138 1139 ret = cfi_rand_callers(start_retpoline, end_retpoline); 1140 if (ret) 1141 goto err; 1142 } 1143 1144 switch (cfi_mode) { 1145 case CFI_OFF: 1146 if (builtin) 1147 pr_info("Disabling CFI\n"); 1148 return; 1149 1150 case CFI_KCFI: 1151 ret = cfi_enable_callers(start_retpoline, end_retpoline); 1152 if (ret) 1153 goto err; 1154 1155 if (builtin) 1156 pr_info("Using kCFI\n"); 1157 return; 1158 1159 case CFI_FINEIBT: 1160 ret = cfi_rewrite_preamble(start_cfi, end_cfi); 1161 if (ret) 1162 goto err; 1163 1164 ret = cfi_rewrite_callers(start_retpoline, end_retpoline); 1165 if (ret) 1166 goto err; 1167 1168 if (builtin) 1169 pr_info("Using FineIBT CFI\n"); 1170 return; 1171 1172 default: 1173 break; 1174 } 1175 1176 err: 1177 pr_err("Something went horribly wrong trying to rewrite the CFI implementation.\n"); 1178 } 1179 1180 #else 1181 1182 static void __apply_fineibt(s32 *start_retpoline, s32 *end_retpoline, 1183 s32 *start_cfi, s32 *end_cfi, bool builtin) 1184 { 1185 } 1186 1187 #endif 1188 1189 void apply_fineibt(s32 *start_retpoline, s32 *end_retpoline, 1190 s32 *start_cfi, s32 *end_cfi) 1191 { 1192 return __apply_fineibt(start_retpoline, end_retpoline, 1193 start_cfi, end_cfi, 1194 /* .builtin = */ false); 1195 } 1196 1197 #ifdef CONFIG_SMP 1198 static void alternatives_smp_lock(const s32 *start, const s32 *end, 1199 u8 *text, u8 *text_end) 1200 { 1201 const s32 *poff; 1202 1203 for (poff = start; poff < end; poff++) { 1204 u8 *ptr = (u8 *)poff + *poff; 1205 1206 if (!*poff || ptr < text || ptr >= text_end) 1207 continue; 1208 /* turn DS segment override prefix into lock prefix */ 1209 if (*ptr == 0x3e) 1210 text_poke(ptr, ((unsigned char []){0xf0}), 1); 1211 } 1212 } 1213 1214 static void alternatives_smp_unlock(const s32 *start, const s32 *end, 1215 u8 *text, u8 *text_end) 1216 { 1217 const s32 *poff; 1218 1219 for (poff = start; poff < end; poff++) { 1220 u8 *ptr = (u8 *)poff + *poff; 1221 1222 if (!*poff || ptr < text || ptr >= text_end) 1223 continue; 1224 /* turn lock prefix into DS segment override prefix */ 1225 if (*ptr == 0xf0) 1226 text_poke(ptr, ((unsigned char []){0x3E}), 1); 1227 } 1228 } 1229 1230 struct smp_alt_module { 1231 /* what is this ??? */ 1232 struct module *mod; 1233 char *name; 1234 1235 /* ptrs to lock prefixes */ 1236 const s32 *locks; 1237 const s32 *locks_end; 1238 1239 /* .text segment, needed to avoid patching init code ;) */ 1240 u8 *text; 1241 u8 *text_end; 1242 1243 struct list_head next; 1244 }; 1245 static LIST_HEAD(smp_alt_modules); 1246 static bool uniproc_patched = false; /* protected by text_mutex */ 1247 1248 void __init_or_module alternatives_smp_module_add(struct module *mod, 1249 char *name, 1250 void *locks, void *locks_end, 1251 void *text, void *text_end) 1252 { 1253 struct smp_alt_module *smp; 1254 1255 mutex_lock(&text_mutex); 1256 if (!uniproc_patched) 1257 goto unlock; 1258 1259 if (num_possible_cpus() == 1) 1260 /* Don't bother remembering, we'll never have to undo it. */ 1261 goto smp_unlock; 1262 1263 smp = kzalloc(sizeof(*smp), GFP_KERNEL); 1264 if (NULL == smp) 1265 /* we'll run the (safe but slow) SMP code then ... */ 1266 goto unlock; 1267 1268 smp->mod = mod; 1269 smp->name = name; 1270 smp->locks = locks; 1271 smp->locks_end = locks_end; 1272 smp->text = text; 1273 smp->text_end = text_end; 1274 DPRINTK(SMP, "locks %p -> %p, text %p -> %p, name %s\n", 1275 smp->locks, smp->locks_end, 1276 smp->text, smp->text_end, smp->name); 1277 1278 list_add_tail(&smp->next, &smp_alt_modules); 1279 smp_unlock: 1280 alternatives_smp_unlock(locks, locks_end, text, text_end); 1281 unlock: 1282 mutex_unlock(&text_mutex); 1283 } 1284 1285 void __init_or_module alternatives_smp_module_del(struct module *mod) 1286 { 1287 struct smp_alt_module *item; 1288 1289 mutex_lock(&text_mutex); 1290 list_for_each_entry(item, &smp_alt_modules, next) { 1291 if (mod != item->mod) 1292 continue; 1293 list_del(&item->next); 1294 kfree(item); 1295 break; 1296 } 1297 mutex_unlock(&text_mutex); 1298 } 1299 1300 void alternatives_enable_smp(void) 1301 { 1302 struct smp_alt_module *mod; 1303 1304 /* Why bother if there are no other CPUs? */ 1305 BUG_ON(num_possible_cpus() == 1); 1306 1307 mutex_lock(&text_mutex); 1308 1309 if (uniproc_patched) { 1310 pr_info("switching to SMP code\n"); 1311 BUG_ON(num_online_cpus() != 1); 1312 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_UP); 1313 clear_cpu_cap(&cpu_data(0), X86_FEATURE_UP); 1314 list_for_each_entry(mod, &smp_alt_modules, next) 1315 alternatives_smp_lock(mod->locks, mod->locks_end, 1316 mod->text, mod->text_end); 1317 uniproc_patched = false; 1318 } 1319 mutex_unlock(&text_mutex); 1320 } 1321 1322 /* 1323 * Return 1 if the address range is reserved for SMP-alternatives. 1324 * Must hold text_mutex. 1325 */ 1326 int alternatives_text_reserved(void *start, void *end) 1327 { 1328 struct smp_alt_module *mod; 1329 const s32 *poff; 1330 u8 *text_start = start; 1331 u8 *text_end = end; 1332 1333 lockdep_assert_held(&text_mutex); 1334 1335 list_for_each_entry(mod, &smp_alt_modules, next) { 1336 if (mod->text > text_end || mod->text_end < text_start) 1337 continue; 1338 for (poff = mod->locks; poff < mod->locks_end; poff++) { 1339 const u8 *ptr = (const u8 *)poff + *poff; 1340 1341 if (text_start <= ptr && text_end > ptr) 1342 return 1; 1343 } 1344 } 1345 1346 return 0; 1347 } 1348 #endif /* CONFIG_SMP */ 1349 1350 #ifdef CONFIG_PARAVIRT 1351 1352 /* Use this to add nops to a buffer, then text_poke the whole buffer. */ 1353 static void __init_or_module add_nops(void *insns, unsigned int len) 1354 { 1355 while (len > 0) { 1356 unsigned int noplen = len; 1357 if (noplen > ASM_NOP_MAX) 1358 noplen = ASM_NOP_MAX; 1359 memcpy(insns, x86_nops[noplen], noplen); 1360 insns += noplen; 1361 len -= noplen; 1362 } 1363 } 1364 1365 void __init_or_module apply_paravirt(struct paravirt_patch_site *start, 1366 struct paravirt_patch_site *end) 1367 { 1368 struct paravirt_patch_site *p; 1369 char insn_buff[MAX_PATCH_LEN]; 1370 1371 for (p = start; p < end; p++) { 1372 unsigned int used; 1373 1374 BUG_ON(p->len > MAX_PATCH_LEN); 1375 /* prep the buffer with the original instructions */ 1376 memcpy(insn_buff, p->instr, p->len); 1377 used = paravirt_patch(p->type, insn_buff, (unsigned long)p->instr, p->len); 1378 1379 BUG_ON(used > p->len); 1380 1381 /* Pad the rest with nops */ 1382 add_nops(insn_buff + used, p->len - used); 1383 text_poke_early(p->instr, insn_buff, p->len); 1384 } 1385 } 1386 extern struct paravirt_patch_site __start_parainstructions[], 1387 __stop_parainstructions[]; 1388 #endif /* CONFIG_PARAVIRT */ 1389 1390 /* 1391 * Self-test for the INT3 based CALL emulation code. 1392 * 1393 * This exercises int3_emulate_call() to make sure INT3 pt_regs are set up 1394 * properly and that there is a stack gap between the INT3 frame and the 1395 * previous context. Without this gap doing a virtual PUSH on the interrupted 1396 * stack would corrupt the INT3 IRET frame. 1397 * 1398 * See entry_{32,64}.S for more details. 1399 */ 1400 1401 /* 1402 * We define the int3_magic() function in assembly to control the calling 1403 * convention such that we can 'call' it from assembly. 1404 */ 1405 1406 extern void int3_magic(unsigned int *ptr); /* defined in asm */ 1407 1408 asm ( 1409 " .pushsection .init.text, \"ax\", @progbits\n" 1410 " .type int3_magic, @function\n" 1411 "int3_magic:\n" 1412 ANNOTATE_NOENDBR 1413 " movl $1, (%" _ASM_ARG1 ")\n" 1414 ASM_RET 1415 " .size int3_magic, .-int3_magic\n" 1416 " .popsection\n" 1417 ); 1418 1419 extern void int3_selftest_ip(void); /* defined in asm below */ 1420 1421 static int __init 1422 int3_exception_notify(struct notifier_block *self, unsigned long val, void *data) 1423 { 1424 unsigned long selftest = (unsigned long)&int3_selftest_ip; 1425 struct die_args *args = data; 1426 struct pt_regs *regs = args->regs; 1427 1428 OPTIMIZER_HIDE_VAR(selftest); 1429 1430 if (!regs || user_mode(regs)) 1431 return NOTIFY_DONE; 1432 1433 if (val != DIE_INT3) 1434 return NOTIFY_DONE; 1435 1436 if (regs->ip - INT3_INSN_SIZE != selftest) 1437 return NOTIFY_DONE; 1438 1439 int3_emulate_call(regs, (unsigned long)&int3_magic); 1440 return NOTIFY_STOP; 1441 } 1442 1443 /* Must be noinline to ensure uniqueness of int3_selftest_ip. */ 1444 static noinline void __init int3_selftest(void) 1445 { 1446 static __initdata struct notifier_block int3_exception_nb = { 1447 .notifier_call = int3_exception_notify, 1448 .priority = INT_MAX-1, /* last */ 1449 }; 1450 unsigned int val = 0; 1451 1452 BUG_ON(register_die_notifier(&int3_exception_nb)); 1453 1454 /* 1455 * Basically: int3_magic(&val); but really complicated :-) 1456 * 1457 * INT3 padded with NOP to CALL_INSN_SIZE. The int3_exception_nb 1458 * notifier above will emulate CALL for us. 1459 */ 1460 asm volatile ("int3_selftest_ip:\n\t" 1461 ANNOTATE_NOENDBR 1462 " int3; nop; nop; nop; nop\n\t" 1463 : ASM_CALL_CONSTRAINT 1464 : __ASM_SEL_RAW(a, D) (&val) 1465 : "memory"); 1466 1467 BUG_ON(val != 1); 1468 1469 unregister_die_notifier(&int3_exception_nb); 1470 } 1471 1472 static __initdata int __alt_reloc_selftest_addr; 1473 1474 __visible noinline void __init __alt_reloc_selftest(void *arg) 1475 { 1476 WARN_ON(arg != &__alt_reloc_selftest_addr); 1477 } 1478 1479 static noinline void __init alt_reloc_selftest(void) 1480 { 1481 /* 1482 * Tests apply_relocation(). 1483 * 1484 * This has a relative immediate (CALL) in a place other than the first 1485 * instruction and additionally on x86_64 we get a RIP-relative LEA: 1486 * 1487 * lea 0x0(%rip),%rdi # 5d0: R_X86_64_PC32 .init.data+0x5566c 1488 * call +0 # 5d5: R_X86_64_PLT32 __alt_reloc_selftest-0x4 1489 * 1490 * Getting this wrong will either crash and burn or tickle the WARN 1491 * above. 1492 */ 1493 asm_inline volatile ( 1494 ALTERNATIVE("", "lea %[mem], %%" _ASM_ARG1 "; call __alt_reloc_selftest;", X86_FEATURE_ALWAYS) 1495 : /* output */ 1496 : [mem] "m" (__alt_reloc_selftest_addr) 1497 : _ASM_ARG1 1498 ); 1499 } 1500 1501 void __init alternative_instructions(void) 1502 { 1503 int3_selftest(); 1504 1505 /* 1506 * The patching is not fully atomic, so try to avoid local 1507 * interruptions that might execute the to be patched code. 1508 * Other CPUs are not running. 1509 */ 1510 stop_nmi(); 1511 1512 /* 1513 * Don't stop machine check exceptions while patching. 1514 * MCEs only happen when something got corrupted and in this 1515 * case we must do something about the corruption. 1516 * Ignoring it is worse than an unlikely patching race. 1517 * Also machine checks tend to be broadcast and if one CPU 1518 * goes into machine check the others follow quickly, so we don't 1519 * expect a machine check to cause undue problems during to code 1520 * patching. 1521 */ 1522 1523 /* 1524 * Paravirt patching and alternative patching can be combined to 1525 * replace a function call with a short direct code sequence (e.g. 1526 * by setting a constant return value instead of doing that in an 1527 * external function). 1528 * In order to make this work the following sequence is required: 1529 * 1. set (artificial) features depending on used paravirt 1530 * functions which can later influence alternative patching 1531 * 2. apply paravirt patching (generally replacing an indirect 1532 * function call with a direct one) 1533 * 3. apply alternative patching (e.g. replacing a direct function 1534 * call with a custom code sequence) 1535 * Doing paravirt patching after alternative patching would clobber 1536 * the optimization of the custom code with a function call again. 1537 */ 1538 paravirt_set_cap(); 1539 1540 /* 1541 * First patch paravirt functions, such that we overwrite the indirect 1542 * call with the direct call. 1543 */ 1544 apply_paravirt(__parainstructions, __parainstructions_end); 1545 1546 __apply_fineibt(__retpoline_sites, __retpoline_sites_end, 1547 __cfi_sites, __cfi_sites_end, true); 1548 1549 /* 1550 * Rewrite the retpolines, must be done before alternatives since 1551 * those can rewrite the retpoline thunks. 1552 */ 1553 apply_retpolines(__retpoline_sites, __retpoline_sites_end); 1554 apply_returns(__return_sites, __return_sites_end); 1555 1556 /* 1557 * Then patch alternatives, such that those paravirt calls that are in 1558 * alternatives can be overwritten by their immediate fragments. 1559 */ 1560 apply_alternatives(__alt_instructions, __alt_instructions_end); 1561 1562 /* 1563 * Now all calls are established. Apply the call thunks if 1564 * required. 1565 */ 1566 callthunks_patch_builtin_calls(); 1567 1568 apply_ibt_endbr(__ibt_endbr_seal, __ibt_endbr_seal_end); 1569 1570 #ifdef CONFIG_SMP 1571 /* Patch to UP if other cpus not imminent. */ 1572 if (!noreplace_smp && (num_present_cpus() == 1 || setup_max_cpus <= 1)) { 1573 uniproc_patched = true; 1574 alternatives_smp_module_add(NULL, "core kernel", 1575 __smp_locks, __smp_locks_end, 1576 _text, _etext); 1577 } 1578 1579 if (!uniproc_patched || num_possible_cpus() == 1) { 1580 free_init_pages("SMP alternatives", 1581 (unsigned long)__smp_locks, 1582 (unsigned long)__smp_locks_end); 1583 } 1584 #endif 1585 1586 restart_nmi(); 1587 alternatives_patched = 1; 1588 1589 alt_reloc_selftest(); 1590 } 1591 1592 /** 1593 * text_poke_early - Update instructions on a live kernel at boot time 1594 * @addr: address to modify 1595 * @opcode: source of the copy 1596 * @len: length to copy 1597 * 1598 * When you use this code to patch more than one byte of an instruction 1599 * you need to make sure that other CPUs cannot execute this code in parallel. 1600 * Also no thread must be currently preempted in the middle of these 1601 * instructions. And on the local CPU you need to be protected against NMI or 1602 * MCE handlers seeing an inconsistent instruction while you patch. 1603 */ 1604 void __init_or_module text_poke_early(void *addr, const void *opcode, 1605 size_t len) 1606 { 1607 unsigned long flags; 1608 1609 if (boot_cpu_has(X86_FEATURE_NX) && 1610 is_module_text_address((unsigned long)addr)) { 1611 /* 1612 * Modules text is marked initially as non-executable, so the 1613 * code cannot be running and speculative code-fetches are 1614 * prevented. Just change the code. 1615 */ 1616 memcpy(addr, opcode, len); 1617 } else { 1618 local_irq_save(flags); 1619 memcpy(addr, opcode, len); 1620 local_irq_restore(flags); 1621 sync_core(); 1622 1623 /* 1624 * Could also do a CLFLUSH here to speed up CPU recovery; but 1625 * that causes hangs on some VIA CPUs. 1626 */ 1627 } 1628 } 1629 1630 typedef struct { 1631 struct mm_struct *mm; 1632 } temp_mm_state_t; 1633 1634 /* 1635 * Using a temporary mm allows to set temporary mappings that are not accessible 1636 * by other CPUs. Such mappings are needed to perform sensitive memory writes 1637 * that override the kernel memory protections (e.g., W^X), without exposing the 1638 * temporary page-table mappings that are required for these write operations to 1639 * other CPUs. Using a temporary mm also allows to avoid TLB shootdowns when the 1640 * mapping is torn down. 1641 * 1642 * Context: The temporary mm needs to be used exclusively by a single core. To 1643 * harden security IRQs must be disabled while the temporary mm is 1644 * loaded, thereby preventing interrupt handler bugs from overriding 1645 * the kernel memory protection. 1646 */ 1647 static inline temp_mm_state_t use_temporary_mm(struct mm_struct *mm) 1648 { 1649 temp_mm_state_t temp_state; 1650 1651 lockdep_assert_irqs_disabled(); 1652 1653 /* 1654 * Make sure not to be in TLB lazy mode, as otherwise we'll end up 1655 * with a stale address space WITHOUT being in lazy mode after 1656 * restoring the previous mm. 1657 */ 1658 if (this_cpu_read(cpu_tlbstate_shared.is_lazy)) 1659 leave_mm(smp_processor_id()); 1660 1661 temp_state.mm = this_cpu_read(cpu_tlbstate.loaded_mm); 1662 switch_mm_irqs_off(NULL, mm, current); 1663 1664 /* 1665 * If breakpoints are enabled, disable them while the temporary mm is 1666 * used. Userspace might set up watchpoints on addresses that are used 1667 * in the temporary mm, which would lead to wrong signals being sent or 1668 * crashes. 1669 * 1670 * Note that breakpoints are not disabled selectively, which also causes 1671 * kernel breakpoints (e.g., perf's) to be disabled. This might be 1672 * undesirable, but still seems reasonable as the code that runs in the 1673 * temporary mm should be short. 1674 */ 1675 if (hw_breakpoint_active()) 1676 hw_breakpoint_disable(); 1677 1678 return temp_state; 1679 } 1680 1681 static inline void unuse_temporary_mm(temp_mm_state_t prev_state) 1682 { 1683 lockdep_assert_irqs_disabled(); 1684 switch_mm_irqs_off(NULL, prev_state.mm, current); 1685 1686 /* 1687 * Restore the breakpoints if they were disabled before the temporary mm 1688 * was loaded. 1689 */ 1690 if (hw_breakpoint_active()) 1691 hw_breakpoint_restore(); 1692 } 1693 1694 __ro_after_init struct mm_struct *poking_mm; 1695 __ro_after_init unsigned long poking_addr; 1696 1697 static void text_poke_memcpy(void *dst, const void *src, size_t len) 1698 { 1699 memcpy(dst, src, len); 1700 } 1701 1702 static void text_poke_memset(void *dst, const void *src, size_t len) 1703 { 1704 int c = *(const int *)src; 1705 1706 memset(dst, c, len); 1707 } 1708 1709 typedef void text_poke_f(void *dst, const void *src, size_t len); 1710 1711 static void *__text_poke(text_poke_f func, void *addr, const void *src, size_t len) 1712 { 1713 bool cross_page_boundary = offset_in_page(addr) + len > PAGE_SIZE; 1714 struct page *pages[2] = {NULL}; 1715 temp_mm_state_t prev; 1716 unsigned long flags; 1717 pte_t pte, *ptep; 1718 spinlock_t *ptl; 1719 pgprot_t pgprot; 1720 1721 /* 1722 * While boot memory allocator is running we cannot use struct pages as 1723 * they are not yet initialized. There is no way to recover. 1724 */ 1725 BUG_ON(!after_bootmem); 1726 1727 if (!core_kernel_text((unsigned long)addr)) { 1728 pages[0] = vmalloc_to_page(addr); 1729 if (cross_page_boundary) 1730 pages[1] = vmalloc_to_page(addr + PAGE_SIZE); 1731 } else { 1732 pages[0] = virt_to_page(addr); 1733 WARN_ON(!PageReserved(pages[0])); 1734 if (cross_page_boundary) 1735 pages[1] = virt_to_page(addr + PAGE_SIZE); 1736 } 1737 /* 1738 * If something went wrong, crash and burn since recovery paths are not 1739 * implemented. 1740 */ 1741 BUG_ON(!pages[0] || (cross_page_boundary && !pages[1])); 1742 1743 /* 1744 * Map the page without the global bit, as TLB flushing is done with 1745 * flush_tlb_mm_range(), which is intended for non-global PTEs. 1746 */ 1747 pgprot = __pgprot(pgprot_val(PAGE_KERNEL) & ~_PAGE_GLOBAL); 1748 1749 /* 1750 * The lock is not really needed, but this allows to avoid open-coding. 1751 */ 1752 ptep = get_locked_pte(poking_mm, poking_addr, &ptl); 1753 1754 /* 1755 * This must not fail; preallocated in poking_init(). 1756 */ 1757 VM_BUG_ON(!ptep); 1758 1759 local_irq_save(flags); 1760 1761 pte = mk_pte(pages[0], pgprot); 1762 set_pte_at(poking_mm, poking_addr, ptep, pte); 1763 1764 if (cross_page_boundary) { 1765 pte = mk_pte(pages[1], pgprot); 1766 set_pte_at(poking_mm, poking_addr + PAGE_SIZE, ptep + 1, pte); 1767 } 1768 1769 /* 1770 * Loading the temporary mm behaves as a compiler barrier, which 1771 * guarantees that the PTE will be set at the time memcpy() is done. 1772 */ 1773 prev = use_temporary_mm(poking_mm); 1774 1775 kasan_disable_current(); 1776 func((u8 *)poking_addr + offset_in_page(addr), src, len); 1777 kasan_enable_current(); 1778 1779 /* 1780 * Ensure that the PTE is only cleared after the instructions of memcpy 1781 * were issued by using a compiler barrier. 1782 */ 1783 barrier(); 1784 1785 pte_clear(poking_mm, poking_addr, ptep); 1786 if (cross_page_boundary) 1787 pte_clear(poking_mm, poking_addr + PAGE_SIZE, ptep + 1); 1788 1789 /* 1790 * Loading the previous page-table hierarchy requires a serializing 1791 * instruction that already allows the core to see the updated version. 1792 * Xen-PV is assumed to serialize execution in a similar manner. 1793 */ 1794 unuse_temporary_mm(prev); 1795 1796 /* 1797 * Flushing the TLB might involve IPIs, which would require enabled 1798 * IRQs, but not if the mm is not used, as it is in this point. 1799 */ 1800 flush_tlb_mm_range(poking_mm, poking_addr, poking_addr + 1801 (cross_page_boundary ? 2 : 1) * PAGE_SIZE, 1802 PAGE_SHIFT, false); 1803 1804 if (func == text_poke_memcpy) { 1805 /* 1806 * If the text does not match what we just wrote then something is 1807 * fundamentally screwy; there's nothing we can really do about that. 1808 */ 1809 BUG_ON(memcmp(addr, src, len)); 1810 } 1811 1812 local_irq_restore(flags); 1813 pte_unmap_unlock(ptep, ptl); 1814 return addr; 1815 } 1816 1817 /** 1818 * text_poke - Update instructions on a live kernel 1819 * @addr: address to modify 1820 * @opcode: source of the copy 1821 * @len: length to copy 1822 * 1823 * Only atomic text poke/set should be allowed when not doing early patching. 1824 * It means the size must be writable atomically and the address must be aligned 1825 * in a way that permits an atomic write. It also makes sure we fit on a single 1826 * page. 1827 * 1828 * Note that the caller must ensure that if the modified code is part of a 1829 * module, the module would not be removed during poking. This can be achieved 1830 * by registering a module notifier, and ordering module removal and patching 1831 * trough a mutex. 1832 */ 1833 void *text_poke(void *addr, const void *opcode, size_t len) 1834 { 1835 lockdep_assert_held(&text_mutex); 1836 1837 return __text_poke(text_poke_memcpy, addr, opcode, len); 1838 } 1839 1840 /** 1841 * text_poke_kgdb - Update instructions on a live kernel by kgdb 1842 * @addr: address to modify 1843 * @opcode: source of the copy 1844 * @len: length to copy 1845 * 1846 * Only atomic text poke/set should be allowed when not doing early patching. 1847 * It means the size must be writable atomically and the address must be aligned 1848 * in a way that permits an atomic write. It also makes sure we fit on a single 1849 * page. 1850 * 1851 * Context: should only be used by kgdb, which ensures no other core is running, 1852 * despite the fact it does not hold the text_mutex. 1853 */ 1854 void *text_poke_kgdb(void *addr, const void *opcode, size_t len) 1855 { 1856 return __text_poke(text_poke_memcpy, addr, opcode, len); 1857 } 1858 1859 void *text_poke_copy_locked(void *addr, const void *opcode, size_t len, 1860 bool core_ok) 1861 { 1862 unsigned long start = (unsigned long)addr; 1863 size_t patched = 0; 1864 1865 if (WARN_ON_ONCE(!core_ok && core_kernel_text(start))) 1866 return NULL; 1867 1868 while (patched < len) { 1869 unsigned long ptr = start + patched; 1870 size_t s; 1871 1872 s = min_t(size_t, PAGE_SIZE * 2 - offset_in_page(ptr), len - patched); 1873 1874 __text_poke(text_poke_memcpy, (void *)ptr, opcode + patched, s); 1875 patched += s; 1876 } 1877 return addr; 1878 } 1879 1880 /** 1881 * text_poke_copy - Copy instructions into (an unused part of) RX memory 1882 * @addr: address to modify 1883 * @opcode: source of the copy 1884 * @len: length to copy, could be more than 2x PAGE_SIZE 1885 * 1886 * Not safe against concurrent execution; useful for JITs to dump 1887 * new code blocks into unused regions of RX memory. Can be used in 1888 * conjunction with synchronize_rcu_tasks() to wait for existing 1889 * execution to quiesce after having made sure no existing functions 1890 * pointers are live. 1891 */ 1892 void *text_poke_copy(void *addr, const void *opcode, size_t len) 1893 { 1894 mutex_lock(&text_mutex); 1895 addr = text_poke_copy_locked(addr, opcode, len, false); 1896 mutex_unlock(&text_mutex); 1897 return addr; 1898 } 1899 1900 /** 1901 * text_poke_set - memset into (an unused part of) RX memory 1902 * @addr: address to modify 1903 * @c: the byte to fill the area with 1904 * @len: length to copy, could be more than 2x PAGE_SIZE 1905 * 1906 * This is useful to overwrite unused regions of RX memory with illegal 1907 * instructions. 1908 */ 1909 void *text_poke_set(void *addr, int c, size_t len) 1910 { 1911 unsigned long start = (unsigned long)addr; 1912 size_t patched = 0; 1913 1914 if (WARN_ON_ONCE(core_kernel_text(start))) 1915 return NULL; 1916 1917 mutex_lock(&text_mutex); 1918 while (patched < len) { 1919 unsigned long ptr = start + patched; 1920 size_t s; 1921 1922 s = min_t(size_t, PAGE_SIZE * 2 - offset_in_page(ptr), len - patched); 1923 1924 __text_poke(text_poke_memset, (void *)ptr, (void *)&c, s); 1925 patched += s; 1926 } 1927 mutex_unlock(&text_mutex); 1928 return addr; 1929 } 1930 1931 static void do_sync_core(void *info) 1932 { 1933 sync_core(); 1934 } 1935 1936 void text_poke_sync(void) 1937 { 1938 on_each_cpu(do_sync_core, NULL, 1); 1939 } 1940 1941 /* 1942 * NOTE: crazy scheme to allow patching Jcc.d32 but not increase the size of 1943 * this thing. When len == 6 everything is prefixed with 0x0f and we map 1944 * opcode to Jcc.d8, using len to distinguish. 1945 */ 1946 struct text_poke_loc { 1947 /* addr := _stext + rel_addr */ 1948 s32 rel_addr; 1949 s32 disp; 1950 u8 len; 1951 u8 opcode; 1952 const u8 text[POKE_MAX_OPCODE_SIZE]; 1953 /* see text_poke_bp_batch() */ 1954 u8 old; 1955 }; 1956 1957 struct bp_patching_desc { 1958 struct text_poke_loc *vec; 1959 int nr_entries; 1960 atomic_t refs; 1961 }; 1962 1963 static struct bp_patching_desc bp_desc; 1964 1965 static __always_inline 1966 struct bp_patching_desc *try_get_desc(void) 1967 { 1968 struct bp_patching_desc *desc = &bp_desc; 1969 1970 if (!raw_atomic_inc_not_zero(&desc->refs)) 1971 return NULL; 1972 1973 return desc; 1974 } 1975 1976 static __always_inline void put_desc(void) 1977 { 1978 struct bp_patching_desc *desc = &bp_desc; 1979 1980 smp_mb__before_atomic(); 1981 raw_atomic_dec(&desc->refs); 1982 } 1983 1984 static __always_inline void *text_poke_addr(struct text_poke_loc *tp) 1985 { 1986 return _stext + tp->rel_addr; 1987 } 1988 1989 static __always_inline int patch_cmp(const void *key, const void *elt) 1990 { 1991 struct text_poke_loc *tp = (struct text_poke_loc *) elt; 1992 1993 if (key < text_poke_addr(tp)) 1994 return -1; 1995 if (key > text_poke_addr(tp)) 1996 return 1; 1997 return 0; 1998 } 1999 2000 noinstr int poke_int3_handler(struct pt_regs *regs) 2001 { 2002 struct bp_patching_desc *desc; 2003 struct text_poke_loc *tp; 2004 int ret = 0; 2005 void *ip; 2006 2007 if (user_mode(regs)) 2008 return 0; 2009 2010 /* 2011 * Having observed our INT3 instruction, we now must observe 2012 * bp_desc with non-zero refcount: 2013 * 2014 * bp_desc.refs = 1 INT3 2015 * WMB RMB 2016 * write INT3 if (bp_desc.refs != 0) 2017 */ 2018 smp_rmb(); 2019 2020 desc = try_get_desc(); 2021 if (!desc) 2022 return 0; 2023 2024 /* 2025 * Discount the INT3. See text_poke_bp_batch(). 2026 */ 2027 ip = (void *) regs->ip - INT3_INSN_SIZE; 2028 2029 /* 2030 * Skip the binary search if there is a single member in the vector. 2031 */ 2032 if (unlikely(desc->nr_entries > 1)) { 2033 tp = __inline_bsearch(ip, desc->vec, desc->nr_entries, 2034 sizeof(struct text_poke_loc), 2035 patch_cmp); 2036 if (!tp) 2037 goto out_put; 2038 } else { 2039 tp = desc->vec; 2040 if (text_poke_addr(tp) != ip) 2041 goto out_put; 2042 } 2043 2044 ip += tp->len; 2045 2046 switch (tp->opcode) { 2047 case INT3_INSN_OPCODE: 2048 /* 2049 * Someone poked an explicit INT3, they'll want to handle it, 2050 * do not consume. 2051 */ 2052 goto out_put; 2053 2054 case RET_INSN_OPCODE: 2055 int3_emulate_ret(regs); 2056 break; 2057 2058 case CALL_INSN_OPCODE: 2059 int3_emulate_call(regs, (long)ip + tp->disp); 2060 break; 2061 2062 case JMP32_INSN_OPCODE: 2063 case JMP8_INSN_OPCODE: 2064 int3_emulate_jmp(regs, (long)ip + tp->disp); 2065 break; 2066 2067 case 0x70 ... 0x7f: /* Jcc */ 2068 int3_emulate_jcc(regs, tp->opcode & 0xf, (long)ip, tp->disp); 2069 break; 2070 2071 default: 2072 BUG(); 2073 } 2074 2075 ret = 1; 2076 2077 out_put: 2078 put_desc(); 2079 return ret; 2080 } 2081 2082 #define TP_VEC_MAX (PAGE_SIZE / sizeof(struct text_poke_loc)) 2083 static struct text_poke_loc tp_vec[TP_VEC_MAX]; 2084 static int tp_vec_nr; 2085 2086 /** 2087 * text_poke_bp_batch() -- update instructions on live kernel on SMP 2088 * @tp: vector of instructions to patch 2089 * @nr_entries: number of entries in the vector 2090 * 2091 * Modify multi-byte instruction by using int3 breakpoint on SMP. 2092 * We completely avoid stop_machine() here, and achieve the 2093 * synchronization using int3 breakpoint. 2094 * 2095 * The way it is done: 2096 * - For each entry in the vector: 2097 * - add a int3 trap to the address that will be patched 2098 * - sync cores 2099 * - For each entry in the vector: 2100 * - update all but the first byte of the patched range 2101 * - sync cores 2102 * - For each entry in the vector: 2103 * - replace the first byte (int3) by the first byte of 2104 * replacing opcode 2105 * - sync cores 2106 */ 2107 static void text_poke_bp_batch(struct text_poke_loc *tp, unsigned int nr_entries) 2108 { 2109 unsigned char int3 = INT3_INSN_OPCODE; 2110 unsigned int i; 2111 int do_sync; 2112 2113 lockdep_assert_held(&text_mutex); 2114 2115 bp_desc.vec = tp; 2116 bp_desc.nr_entries = nr_entries; 2117 2118 /* 2119 * Corresponds to the implicit memory barrier in try_get_desc() to 2120 * ensure reading a non-zero refcount provides up to date bp_desc data. 2121 */ 2122 atomic_set_release(&bp_desc.refs, 1); 2123 2124 /* 2125 * Function tracing can enable thousands of places that need to be 2126 * updated. This can take quite some time, and with full kernel debugging 2127 * enabled, this could cause the softlockup watchdog to trigger. 2128 * This function gets called every 256 entries added to be patched. 2129 * Call cond_resched() here to make sure that other tasks can get scheduled 2130 * while processing all the functions being patched. 2131 */ 2132 cond_resched(); 2133 2134 /* 2135 * Corresponding read barrier in int3 notifier for making sure the 2136 * nr_entries and handler are correctly ordered wrt. patching. 2137 */ 2138 smp_wmb(); 2139 2140 /* 2141 * First step: add a int3 trap to the address that will be patched. 2142 */ 2143 for (i = 0; i < nr_entries; i++) { 2144 tp[i].old = *(u8 *)text_poke_addr(&tp[i]); 2145 text_poke(text_poke_addr(&tp[i]), &int3, INT3_INSN_SIZE); 2146 } 2147 2148 text_poke_sync(); 2149 2150 /* 2151 * Second step: update all but the first byte of the patched range. 2152 */ 2153 for (do_sync = 0, i = 0; i < nr_entries; i++) { 2154 u8 old[POKE_MAX_OPCODE_SIZE+1] = { tp[i].old, }; 2155 u8 _new[POKE_MAX_OPCODE_SIZE+1]; 2156 const u8 *new = tp[i].text; 2157 int len = tp[i].len; 2158 2159 if (len - INT3_INSN_SIZE > 0) { 2160 memcpy(old + INT3_INSN_SIZE, 2161 text_poke_addr(&tp[i]) + INT3_INSN_SIZE, 2162 len - INT3_INSN_SIZE); 2163 2164 if (len == 6) { 2165 _new[0] = 0x0f; 2166 memcpy(_new + 1, new, 5); 2167 new = _new; 2168 } 2169 2170 text_poke(text_poke_addr(&tp[i]) + INT3_INSN_SIZE, 2171 new + INT3_INSN_SIZE, 2172 len - INT3_INSN_SIZE); 2173 2174 do_sync++; 2175 } 2176 2177 /* 2178 * Emit a perf event to record the text poke, primarily to 2179 * support Intel PT decoding which must walk the executable code 2180 * to reconstruct the trace. The flow up to here is: 2181 * - write INT3 byte 2182 * - IPI-SYNC 2183 * - write instruction tail 2184 * At this point the actual control flow will be through the 2185 * INT3 and handler and not hit the old or new instruction. 2186 * Intel PT outputs FUP/TIP packets for the INT3, so the flow 2187 * can still be decoded. Subsequently: 2188 * - emit RECORD_TEXT_POKE with the new instruction 2189 * - IPI-SYNC 2190 * - write first byte 2191 * - IPI-SYNC 2192 * So before the text poke event timestamp, the decoder will see 2193 * either the old instruction flow or FUP/TIP of INT3. After the 2194 * text poke event timestamp, the decoder will see either the 2195 * new instruction flow or FUP/TIP of INT3. Thus decoders can 2196 * use the timestamp as the point at which to modify the 2197 * executable code. 2198 * The old instruction is recorded so that the event can be 2199 * processed forwards or backwards. 2200 */ 2201 perf_event_text_poke(text_poke_addr(&tp[i]), old, len, new, len); 2202 } 2203 2204 if (do_sync) { 2205 /* 2206 * According to Intel, this core syncing is very likely 2207 * not necessary and we'd be safe even without it. But 2208 * better safe than sorry (plus there's not only Intel). 2209 */ 2210 text_poke_sync(); 2211 } 2212 2213 /* 2214 * Third step: replace the first byte (int3) by the first byte of 2215 * replacing opcode. 2216 */ 2217 for (do_sync = 0, i = 0; i < nr_entries; i++) { 2218 u8 byte = tp[i].text[0]; 2219 2220 if (tp[i].len == 6) 2221 byte = 0x0f; 2222 2223 if (byte == INT3_INSN_OPCODE) 2224 continue; 2225 2226 text_poke(text_poke_addr(&tp[i]), &byte, INT3_INSN_SIZE); 2227 do_sync++; 2228 } 2229 2230 if (do_sync) 2231 text_poke_sync(); 2232 2233 /* 2234 * Remove and wait for refs to be zero. 2235 */ 2236 if (!atomic_dec_and_test(&bp_desc.refs)) 2237 atomic_cond_read_acquire(&bp_desc.refs, !VAL); 2238 } 2239 2240 static void text_poke_loc_init(struct text_poke_loc *tp, void *addr, 2241 const void *opcode, size_t len, const void *emulate) 2242 { 2243 struct insn insn; 2244 int ret, i = 0; 2245 2246 if (len == 6) 2247 i = 1; 2248 memcpy((void *)tp->text, opcode+i, len-i); 2249 if (!emulate) 2250 emulate = opcode; 2251 2252 ret = insn_decode_kernel(&insn, emulate); 2253 BUG_ON(ret < 0); 2254 2255 tp->rel_addr = addr - (void *)_stext; 2256 tp->len = len; 2257 tp->opcode = insn.opcode.bytes[0]; 2258 2259 if (is_jcc32(&insn)) { 2260 /* 2261 * Map Jcc.d32 onto Jcc.d8 and use len to distinguish. 2262 */ 2263 tp->opcode = insn.opcode.bytes[1] - 0x10; 2264 } 2265 2266 switch (tp->opcode) { 2267 case RET_INSN_OPCODE: 2268 case JMP32_INSN_OPCODE: 2269 case JMP8_INSN_OPCODE: 2270 /* 2271 * Control flow instructions without implied execution of the 2272 * next instruction can be padded with INT3. 2273 */ 2274 for (i = insn.length; i < len; i++) 2275 BUG_ON(tp->text[i] != INT3_INSN_OPCODE); 2276 break; 2277 2278 default: 2279 BUG_ON(len != insn.length); 2280 } 2281 2282 switch (tp->opcode) { 2283 case INT3_INSN_OPCODE: 2284 case RET_INSN_OPCODE: 2285 break; 2286 2287 case CALL_INSN_OPCODE: 2288 case JMP32_INSN_OPCODE: 2289 case JMP8_INSN_OPCODE: 2290 case 0x70 ... 0x7f: /* Jcc */ 2291 tp->disp = insn.immediate.value; 2292 break; 2293 2294 default: /* assume NOP */ 2295 switch (len) { 2296 case 2: /* NOP2 -- emulate as JMP8+0 */ 2297 BUG_ON(memcmp(emulate, x86_nops[len], len)); 2298 tp->opcode = JMP8_INSN_OPCODE; 2299 tp->disp = 0; 2300 break; 2301 2302 case 5: /* NOP5 -- emulate as JMP32+0 */ 2303 BUG_ON(memcmp(emulate, x86_nops[len], len)); 2304 tp->opcode = JMP32_INSN_OPCODE; 2305 tp->disp = 0; 2306 break; 2307 2308 default: /* unknown instruction */ 2309 BUG(); 2310 } 2311 break; 2312 } 2313 } 2314 2315 /* 2316 * We hard rely on the tp_vec being ordered; ensure this is so by flushing 2317 * early if needed. 2318 */ 2319 static bool tp_order_fail(void *addr) 2320 { 2321 struct text_poke_loc *tp; 2322 2323 if (!tp_vec_nr) 2324 return false; 2325 2326 if (!addr) /* force */ 2327 return true; 2328 2329 tp = &tp_vec[tp_vec_nr - 1]; 2330 if ((unsigned long)text_poke_addr(tp) > (unsigned long)addr) 2331 return true; 2332 2333 return false; 2334 } 2335 2336 static void text_poke_flush(void *addr) 2337 { 2338 if (tp_vec_nr == TP_VEC_MAX || tp_order_fail(addr)) { 2339 text_poke_bp_batch(tp_vec, tp_vec_nr); 2340 tp_vec_nr = 0; 2341 } 2342 } 2343 2344 void text_poke_finish(void) 2345 { 2346 text_poke_flush(NULL); 2347 } 2348 2349 void __ref text_poke_queue(void *addr, const void *opcode, size_t len, const void *emulate) 2350 { 2351 struct text_poke_loc *tp; 2352 2353 text_poke_flush(addr); 2354 2355 tp = &tp_vec[tp_vec_nr++]; 2356 text_poke_loc_init(tp, addr, opcode, len, emulate); 2357 } 2358 2359 /** 2360 * text_poke_bp() -- update instructions on live kernel on SMP 2361 * @addr: address to patch 2362 * @opcode: opcode of new instruction 2363 * @len: length to copy 2364 * @emulate: instruction to be emulated 2365 * 2366 * Update a single instruction with the vector in the stack, avoiding 2367 * dynamically allocated memory. This function should be used when it is 2368 * not possible to allocate memory. 2369 */ 2370 void __ref text_poke_bp(void *addr, const void *opcode, size_t len, const void *emulate) 2371 { 2372 struct text_poke_loc tp; 2373 2374 text_poke_loc_init(&tp, addr, opcode, len, emulate); 2375 text_poke_bp_batch(&tp, 1); 2376 } 2377