1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2005 Intel Corporation 4 * Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> 5 * - Added _PDC for SMP C-states on Intel CPUs 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/export.h> 10 #include <linux/init.h> 11 #include <linux/acpi.h> 12 #include <linux/cpu.h> 13 #include <linux/sched.h> 14 15 #include <acpi/processor.h> 16 #include <asm/mwait.h> 17 #include <asm/special_insns.h> 18 19 /* 20 * Initialize bm_flags based on the CPU cache properties 21 * On SMP it depends on cache configuration 22 * - When cache is not shared among all CPUs, we flush cache 23 * before entering C3. 24 * - When cache is shared among all CPUs, we use bm_check 25 * mechanism as in UP case 26 * 27 * This routine is called only after all the CPUs are online 28 */ 29 void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags, 30 unsigned int cpu) 31 { 32 struct cpuinfo_x86 *c = &cpu_data(cpu); 33 34 flags->bm_check = 0; 35 if (num_online_cpus() == 1) 36 flags->bm_check = 1; 37 else if (c->x86_vendor == X86_VENDOR_INTEL) { 38 /* 39 * Today all MP CPUs that support C3 share cache. 40 * And caches should not be flushed by software while 41 * entering C3 type state. 42 */ 43 flags->bm_check = 1; 44 } 45 46 /* 47 * On all recent Intel platforms, ARB_DISABLE is a nop. 48 * So, set bm_control to zero to indicate that ARB_DISABLE 49 * is not required while entering C3 type state on 50 * P4, Core and beyond CPUs 51 */ 52 if (c->x86_vendor == X86_VENDOR_INTEL && 53 (c->x86 > 0xf || (c->x86 == 6 && c->x86_model >= 0x0f))) 54 flags->bm_control = 0; 55 /* 56 * For all recent Centaur CPUs, the ucode will make sure that each 57 * core can keep cache coherence with each other while entering C3 58 * type state. So, set bm_check to 1 to indicate that the kernel 59 * doesn't need to execute a cache flush operation (WBINVD) when 60 * entering C3 type state. 61 */ 62 if (c->x86_vendor == X86_VENDOR_CENTAUR) { 63 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model == 0x0f && 64 c->x86_stepping >= 0x0e)) 65 flags->bm_check = 1; 66 } 67 } 68 EXPORT_SYMBOL(acpi_processor_power_init_bm_check); 69 70 /* The code below handles cstate entry with monitor-mwait pair on Intel*/ 71 72 struct cstate_entry { 73 struct { 74 unsigned int eax; 75 unsigned int ecx; 76 } states[ACPI_PROCESSOR_MAX_POWER]; 77 }; 78 static struct cstate_entry __percpu *cpu_cstate_entry; /* per CPU ptr */ 79 80 static short mwait_supported[ACPI_PROCESSOR_MAX_POWER]; 81 82 #define NATIVE_CSTATE_BEYOND_HALT (2) 83 84 static long acpi_processor_ffh_cstate_probe_cpu(void *_cx) 85 { 86 struct acpi_processor_cx *cx = _cx; 87 long retval; 88 unsigned int eax, ebx, ecx, edx; 89 unsigned int edx_part; 90 unsigned int cstate_type; /* C-state type and not ACPI C-state type */ 91 unsigned int num_cstate_subtype; 92 93 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx); 94 95 /* Check whether this particular cx_type (in CST) is supported or not */ 96 cstate_type = ((cx->address >> MWAIT_SUBSTATE_SIZE) & 97 MWAIT_CSTATE_MASK) + 1; 98 edx_part = edx >> (cstate_type * MWAIT_SUBSTATE_SIZE); 99 num_cstate_subtype = edx_part & MWAIT_SUBSTATE_MASK; 100 101 retval = 0; 102 /* If the HW does not support any sub-states in this C-state */ 103 if (num_cstate_subtype == 0) { 104 pr_warn(FW_BUG "ACPI MWAIT C-state 0x%x not supported by HW (0x%x)\n", 105 cx->address, edx_part); 106 retval = -1; 107 goto out; 108 } 109 110 /* mwait ecx extensions INTERRUPT_BREAK should be supported for C2/C3 */ 111 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) || 112 !(ecx & CPUID5_ECX_INTERRUPT_BREAK)) { 113 retval = -1; 114 goto out; 115 } 116 117 if (!mwait_supported[cstate_type]) { 118 mwait_supported[cstate_type] = 1; 119 printk(KERN_DEBUG 120 "Monitor-Mwait will be used to enter C-%d state\n", 121 cx->type); 122 } 123 snprintf(cx->desc, 124 ACPI_CX_DESC_LEN, "ACPI FFH MWAIT 0x%x", 125 cx->address); 126 out: 127 return retval; 128 } 129 130 int acpi_processor_ffh_cstate_probe(unsigned int cpu, 131 struct acpi_processor_cx *cx, struct acpi_power_register *reg) 132 { 133 struct cstate_entry *percpu_entry; 134 struct cpuinfo_x86 *c = &cpu_data(cpu); 135 long retval; 136 137 if (!cpu_cstate_entry || c->cpuid_level < CPUID_MWAIT_LEAF) 138 return -1; 139 140 if (reg->bit_offset != NATIVE_CSTATE_BEYOND_HALT) 141 return -1; 142 143 percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu); 144 percpu_entry->states[cx->index].eax = 0; 145 percpu_entry->states[cx->index].ecx = 0; 146 147 /* Make sure we are running on right CPU */ 148 149 retval = work_on_cpu(cpu, acpi_processor_ffh_cstate_probe_cpu, cx); 150 if (retval == 0) { 151 /* Use the hint in CST */ 152 percpu_entry->states[cx->index].eax = cx->address; 153 percpu_entry->states[cx->index].ecx = MWAIT_ECX_INTERRUPT_BREAK; 154 } 155 156 /* 157 * For _CST FFH on Intel, if GAS.access_size bit 1 is cleared, 158 * then we should skip checking BM_STS for this C-state. 159 * ref: "Intel Processor Vendor-Specific ACPI Interface Specification" 160 */ 161 if ((c->x86_vendor == X86_VENDOR_INTEL) && !(reg->access_size & 0x2)) 162 cx->bm_sts_skip = 1; 163 164 return retval; 165 } 166 EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_probe); 167 168 void __cpuidle acpi_processor_ffh_cstate_enter(struct acpi_processor_cx *cx) 169 { 170 unsigned int cpu = smp_processor_id(); 171 struct cstate_entry *percpu_entry; 172 173 percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu); 174 mwait_idle_with_hints(percpu_entry->states[cx->index].eax, 175 percpu_entry->states[cx->index].ecx); 176 } 177 EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_enter); 178 179 static int __init ffh_cstate_init(void) 180 { 181 struct cpuinfo_x86 *c = &boot_cpu_data; 182 183 if (c->x86_vendor != X86_VENDOR_INTEL && 184 c->x86_vendor != X86_VENDOR_AMD) 185 return -1; 186 187 cpu_cstate_entry = alloc_percpu(struct cstate_entry); 188 return 0; 189 } 190 191 static void __exit ffh_cstate_exit(void) 192 { 193 free_percpu(cpu_cstate_entry); 194 cpu_cstate_entry = NULL; 195 } 196 197 arch_initcall(ffh_cstate_init); 198 __exitcall(ffh_cstate_exit); 199