1 #ifndef _ASM_X86_KVM_H 2 #define _ASM_X86_KVM_H 3 4 /* 5 * KVM x86 specific structures and definitions 6 * 7 */ 8 9 #include <linux/types.h> 10 #include <linux/ioctl.h> 11 12 #define DE_VECTOR 0 13 #define DB_VECTOR 1 14 #define BP_VECTOR 3 15 #define OF_VECTOR 4 16 #define BR_VECTOR 5 17 #define UD_VECTOR 6 18 #define NM_VECTOR 7 19 #define DF_VECTOR 8 20 #define TS_VECTOR 10 21 #define NP_VECTOR 11 22 #define SS_VECTOR 12 23 #define GP_VECTOR 13 24 #define PF_VECTOR 14 25 #define MF_VECTOR 16 26 #define AC_VECTOR 17 27 #define MC_VECTOR 18 28 #define XM_VECTOR 19 29 #define VE_VECTOR 20 30 31 /* Select x86 specific features in <linux/kvm.h> */ 32 #define __KVM_HAVE_PIT 33 #define __KVM_HAVE_IOAPIC 34 #define __KVM_HAVE_IRQ_LINE 35 #define __KVM_HAVE_MSI 36 #define __KVM_HAVE_USER_NMI 37 #define __KVM_HAVE_GUEST_DEBUG 38 #define __KVM_HAVE_MSIX 39 #define __KVM_HAVE_MCE 40 #define __KVM_HAVE_PIT_STATE2 41 #define __KVM_HAVE_XEN_HVM 42 #define __KVM_HAVE_VCPU_EVENTS 43 #define __KVM_HAVE_DEBUGREGS 44 #define __KVM_HAVE_XSAVE 45 #define __KVM_HAVE_XCRS 46 #define __KVM_HAVE_READONLY_MEM 47 48 /* Architectural interrupt line count. */ 49 #define KVM_NR_INTERRUPTS 256 50 51 struct kvm_memory_alias { 52 __u32 slot; /* this has a different namespace than memory slots */ 53 __u32 flags; 54 __u64 guest_phys_addr; 55 __u64 memory_size; 56 __u64 target_phys_addr; 57 }; 58 59 /* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */ 60 struct kvm_pic_state { 61 __u8 last_irr; /* edge detection */ 62 __u8 irr; /* interrupt request register */ 63 __u8 imr; /* interrupt mask register */ 64 __u8 isr; /* interrupt service register */ 65 __u8 priority_add; /* highest irq priority */ 66 __u8 irq_base; 67 __u8 read_reg_select; 68 __u8 poll; 69 __u8 special_mask; 70 __u8 init_state; 71 __u8 auto_eoi; 72 __u8 rotate_on_auto_eoi; 73 __u8 special_fully_nested_mode; 74 __u8 init4; /* true if 4 byte init */ 75 __u8 elcr; /* PIIX edge/trigger selection */ 76 __u8 elcr_mask; 77 }; 78 79 #define KVM_IOAPIC_NUM_PINS 24 80 struct kvm_ioapic_state { 81 __u64 base_address; 82 __u32 ioregsel; 83 __u32 id; 84 __u32 irr; 85 __u32 pad; 86 union { 87 __u64 bits; 88 struct { 89 __u8 vector; 90 __u8 delivery_mode:3; 91 __u8 dest_mode:1; 92 __u8 delivery_status:1; 93 __u8 polarity:1; 94 __u8 remote_irr:1; 95 __u8 trig_mode:1; 96 __u8 mask:1; 97 __u8 reserve:7; 98 __u8 reserved[4]; 99 __u8 dest_id; 100 } fields; 101 } redirtbl[KVM_IOAPIC_NUM_PINS]; 102 }; 103 104 #define KVM_IRQCHIP_PIC_MASTER 0 105 #define KVM_IRQCHIP_PIC_SLAVE 1 106 #define KVM_IRQCHIP_IOAPIC 2 107 #define KVM_NR_IRQCHIPS 3 108 109 /* for KVM_GET_REGS and KVM_SET_REGS */ 110 struct kvm_regs { 111 /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */ 112 __u64 rax, rbx, rcx, rdx; 113 __u64 rsi, rdi, rsp, rbp; 114 __u64 r8, r9, r10, r11; 115 __u64 r12, r13, r14, r15; 116 __u64 rip, rflags; 117 }; 118 119 /* for KVM_GET_LAPIC and KVM_SET_LAPIC */ 120 #define KVM_APIC_REG_SIZE 0x400 121 struct kvm_lapic_state { 122 char regs[KVM_APIC_REG_SIZE]; 123 }; 124 125 struct kvm_segment { 126 __u64 base; 127 __u32 limit; 128 __u16 selector; 129 __u8 type; 130 __u8 present, dpl, db, s, l, g, avl; 131 __u8 unusable; 132 __u8 padding; 133 }; 134 135 struct kvm_dtable { 136 __u64 base; 137 __u16 limit; 138 __u16 padding[3]; 139 }; 140 141 142 /* for KVM_GET_SREGS and KVM_SET_SREGS */ 143 struct kvm_sregs { 144 /* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */ 145 struct kvm_segment cs, ds, es, fs, gs, ss; 146 struct kvm_segment tr, ldt; 147 struct kvm_dtable gdt, idt; 148 __u64 cr0, cr2, cr3, cr4, cr8; 149 __u64 efer; 150 __u64 apic_base; 151 __u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64]; 152 }; 153 154 /* for KVM_GET_FPU and KVM_SET_FPU */ 155 struct kvm_fpu { 156 __u8 fpr[8][16]; 157 __u16 fcw; 158 __u16 fsw; 159 __u8 ftwx; /* in fxsave format */ 160 __u8 pad1; 161 __u16 last_opcode; 162 __u64 last_ip; 163 __u64 last_dp; 164 __u8 xmm[16][16]; 165 __u32 mxcsr; 166 __u32 pad2; 167 }; 168 169 struct kvm_msr_entry { 170 __u32 index; 171 __u32 reserved; 172 __u64 data; 173 }; 174 175 /* for KVM_GET_MSRS and KVM_SET_MSRS */ 176 struct kvm_msrs { 177 __u32 nmsrs; /* number of msrs in entries */ 178 __u32 pad; 179 180 struct kvm_msr_entry entries[0]; 181 }; 182 183 /* for KVM_GET_MSR_INDEX_LIST */ 184 struct kvm_msr_list { 185 __u32 nmsrs; /* number of msrs in entries */ 186 __u32 indices[0]; 187 }; 188 189 190 struct kvm_cpuid_entry { 191 __u32 function; 192 __u32 eax; 193 __u32 ebx; 194 __u32 ecx; 195 __u32 edx; 196 __u32 padding; 197 }; 198 199 /* for KVM_SET_CPUID */ 200 struct kvm_cpuid { 201 __u32 nent; 202 __u32 padding; 203 struct kvm_cpuid_entry entries[0]; 204 }; 205 206 struct kvm_cpuid_entry2 { 207 __u32 function; 208 __u32 index; 209 __u32 flags; 210 __u32 eax; 211 __u32 ebx; 212 __u32 ecx; 213 __u32 edx; 214 __u32 padding[3]; 215 }; 216 217 #define KVM_CPUID_FLAG_SIGNIFCANT_INDEX BIT(0) 218 #define KVM_CPUID_FLAG_STATEFUL_FUNC BIT(1) 219 #define KVM_CPUID_FLAG_STATE_READ_NEXT BIT(2) 220 221 /* for KVM_SET_CPUID2 */ 222 struct kvm_cpuid2 { 223 __u32 nent; 224 __u32 padding; 225 struct kvm_cpuid_entry2 entries[0]; 226 }; 227 228 /* for KVM_GET_PIT and KVM_SET_PIT */ 229 struct kvm_pit_channel_state { 230 __u32 count; /* can be 65536 */ 231 __u16 latched_count; 232 __u8 count_latched; 233 __u8 status_latched; 234 __u8 status; 235 __u8 read_state; 236 __u8 write_state; 237 __u8 write_latch; 238 __u8 rw_mode; 239 __u8 mode; 240 __u8 bcd; 241 __u8 gate; 242 __s64 count_load_time; 243 }; 244 245 struct kvm_debug_exit_arch { 246 __u32 exception; 247 __u32 pad; 248 __u64 pc; 249 __u64 dr6; 250 __u64 dr7; 251 }; 252 253 #define KVM_GUESTDBG_USE_SW_BP 0x00010000 254 #define KVM_GUESTDBG_USE_HW_BP 0x00020000 255 #define KVM_GUESTDBG_INJECT_DB 0x00040000 256 #define KVM_GUESTDBG_INJECT_BP 0x00080000 257 258 /* for KVM_SET_GUEST_DEBUG */ 259 struct kvm_guest_debug_arch { 260 __u64 debugreg[8]; 261 }; 262 263 struct kvm_pit_state { 264 struct kvm_pit_channel_state channels[3]; 265 }; 266 267 #define KVM_PIT_FLAGS_HPET_LEGACY 0x00000001 268 269 struct kvm_pit_state2 { 270 struct kvm_pit_channel_state channels[3]; 271 __u32 flags; 272 __u32 reserved[9]; 273 }; 274 275 struct kvm_reinject_control { 276 __u8 pit_reinject; 277 __u8 reserved[31]; 278 }; 279 280 /* When set in flags, include corresponding fields on KVM_SET_VCPU_EVENTS */ 281 #define KVM_VCPUEVENT_VALID_NMI_PENDING 0x00000001 282 #define KVM_VCPUEVENT_VALID_SIPI_VECTOR 0x00000002 283 #define KVM_VCPUEVENT_VALID_SHADOW 0x00000004 284 285 /* Interrupt shadow states */ 286 #define KVM_X86_SHADOW_INT_MOV_SS 0x01 287 #define KVM_X86_SHADOW_INT_STI 0x02 288 289 /* for KVM_GET/SET_VCPU_EVENTS */ 290 struct kvm_vcpu_events { 291 struct { 292 __u8 injected; 293 __u8 nr; 294 __u8 has_error_code; 295 __u8 pad; 296 __u32 error_code; 297 } exception; 298 struct { 299 __u8 injected; 300 __u8 nr; 301 __u8 soft; 302 __u8 shadow; 303 } interrupt; 304 struct { 305 __u8 injected; 306 __u8 pending; 307 __u8 masked; 308 __u8 pad; 309 } nmi; 310 __u32 sipi_vector; 311 __u32 flags; 312 __u32 reserved[10]; 313 }; 314 315 /* for KVM_GET/SET_DEBUGREGS */ 316 struct kvm_debugregs { 317 __u64 db[4]; 318 __u64 dr6; 319 __u64 dr7; 320 __u64 flags; 321 __u64 reserved[9]; 322 }; 323 324 /* for KVM_CAP_XSAVE */ 325 struct kvm_xsave { 326 __u32 region[1024]; 327 }; 328 329 #define KVM_MAX_XCRS 16 330 331 struct kvm_xcr { 332 __u32 xcr; 333 __u32 reserved; 334 __u64 value; 335 }; 336 337 struct kvm_xcrs { 338 __u32 nr_xcrs; 339 __u32 flags; 340 struct kvm_xcr xcrs[KVM_MAX_XCRS]; 341 __u64 padding[16]; 342 }; 343 344 /* definition of registers in kvm_run */ 345 struct kvm_sync_regs { 346 }; 347 348 #endif /* _ASM_X86_KVM_H */ 349