105e4d316SH. Peter Anvin #ifndef _ASM_X86_XEN_EVENTS_H 205e4d316SH. Peter Anvin #define _ASM_X86_XEN_EVENTS_H 3bb898558SAl Viro 4bb898558SAl Viro enum ipi_vector { 5bb898558SAl Viro XEN_RESCHEDULE_VECTOR, 6bb898558SAl Viro XEN_CALL_FUNCTION_VECTOR, 7bb898558SAl Viro XEN_CALL_FUNCTION_SINGLE_VECTOR, 8bb898558SAl Viro XEN_SPIN_UNLOCK_VECTOR, 91ff2b0c3SLin Ming XEN_IRQ_WORK_VECTOR, 10bb898558SAl Viro 11bb898558SAl Viro XEN_NR_IPIS, 12bb898558SAl Viro }; 13bb898558SAl Viro 14bb898558SAl Viro static inline int xen_irqs_disabled(struct pt_regs *regs) 15bb898558SAl Viro { 16bb898558SAl Viro return raw_irqs_disabled_flags(regs->flags); 17bb898558SAl Viro } 18bb898558SAl Viro 19c81611c4SIan Campbell /* No need for a barrier -- XCHG is a barrier on x86. */ 20c81611c4SIan Campbell #define xchg_xen_ulong(ptr, val) xchg((ptr), (val)) 21c81611c4SIan Campbell 2205e4d316SH. Peter Anvin #endif /* _ASM_X86_XEN_EVENTS_H */ 23