1 /* 2 * vmx.h: VMX Architecture related definitions 3 * Copyright (c) 2004, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple 16 * Place - Suite 330, Boston, MA 02111-1307 USA. 17 * 18 * A few random additions are: 19 * Copyright (C) 2006 Qumranet 20 * Avi Kivity <avi@qumranet.com> 21 * Yaniv Kamay <yaniv@qumranet.com> 22 * 23 */ 24 #ifndef VMX_H 25 #define VMX_H 26 27 28 #include <linux/types.h> 29 #include <uapi/asm/vmx.h> 30 31 /* 32 * Definitions of Primary Processor-Based VM-Execution Controls. 33 */ 34 #define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004 35 #define CPU_BASED_USE_TSC_OFFSETING 0x00000008 36 #define CPU_BASED_HLT_EXITING 0x00000080 37 #define CPU_BASED_INVLPG_EXITING 0x00000200 38 #define CPU_BASED_MWAIT_EXITING 0x00000400 39 #define CPU_BASED_RDPMC_EXITING 0x00000800 40 #define CPU_BASED_RDTSC_EXITING 0x00001000 41 #define CPU_BASED_CR3_LOAD_EXITING 0x00008000 42 #define CPU_BASED_CR3_STORE_EXITING 0x00010000 43 #define CPU_BASED_CR8_LOAD_EXITING 0x00080000 44 #define CPU_BASED_CR8_STORE_EXITING 0x00100000 45 #define CPU_BASED_TPR_SHADOW 0x00200000 46 #define CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000 47 #define CPU_BASED_MOV_DR_EXITING 0x00800000 48 #define CPU_BASED_UNCOND_IO_EXITING 0x01000000 49 #define CPU_BASED_USE_IO_BITMAPS 0x02000000 50 #define CPU_BASED_USE_MSR_BITMAPS 0x10000000 51 #define CPU_BASED_MONITOR_EXITING 0x20000000 52 #define CPU_BASED_PAUSE_EXITING 0x40000000 53 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000 54 /* 55 * Definitions of Secondary Processor-Based VM-Execution Controls. 56 */ 57 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001 58 #define SECONDARY_EXEC_ENABLE_EPT 0x00000002 59 #define SECONDARY_EXEC_RDTSCP 0x00000008 60 #define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010 61 #define SECONDARY_EXEC_ENABLE_VPID 0x00000020 62 #define SECONDARY_EXEC_WBINVD_EXITING 0x00000040 63 #define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080 64 #define SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100 65 #define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200 66 #define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400 67 #define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000 68 #define SECONDARY_EXEC_SHADOW_VMCS 0x00004000 69 70 71 #define PIN_BASED_EXT_INTR_MASK 0x00000001 72 #define PIN_BASED_NMI_EXITING 0x00000008 73 #define PIN_BASED_VIRTUAL_NMIS 0x00000020 74 #define PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040 75 #define PIN_BASED_POSTED_INTR 0x00000080 76 77 #define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x00000016 78 79 #define VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000002 80 #define VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200 81 #define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000 82 #define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000 83 #define VM_EXIT_SAVE_IA32_PAT 0x00040000 84 #define VM_EXIT_LOAD_IA32_PAT 0x00080000 85 #define VM_EXIT_SAVE_IA32_EFER 0x00100000 86 #define VM_EXIT_LOAD_IA32_EFER 0x00200000 87 #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000 88 #define VM_EXIT_CLEAR_BNDCFGS 0x00800000 89 90 #define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR 0x00036dff 91 92 #define VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000002 93 #define VM_ENTRY_IA32E_MODE 0x00000200 94 #define VM_ENTRY_SMM 0x00000400 95 #define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800 96 #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000 97 #define VM_ENTRY_LOAD_IA32_PAT 0x00004000 98 #define VM_ENTRY_LOAD_IA32_EFER 0x00008000 99 #define VM_ENTRY_LOAD_BNDCFGS 0x00010000 100 101 #define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR 0x000011ff 102 103 #define VMX_MISC_PREEMPTION_TIMER_RATE_MASK 0x0000001f 104 #define VMX_MISC_SAVE_EFER_LMA 0x00000020 105 #define VMX_MISC_ACTIVITY_HLT 0x00000040 106 107 /* VMCS Encodings */ 108 enum vmcs_field { 109 VIRTUAL_PROCESSOR_ID = 0x00000000, 110 POSTED_INTR_NV = 0x00000002, 111 GUEST_ES_SELECTOR = 0x00000800, 112 GUEST_CS_SELECTOR = 0x00000802, 113 GUEST_SS_SELECTOR = 0x00000804, 114 GUEST_DS_SELECTOR = 0x00000806, 115 GUEST_FS_SELECTOR = 0x00000808, 116 GUEST_GS_SELECTOR = 0x0000080a, 117 GUEST_LDTR_SELECTOR = 0x0000080c, 118 GUEST_TR_SELECTOR = 0x0000080e, 119 GUEST_INTR_STATUS = 0x00000810, 120 HOST_ES_SELECTOR = 0x00000c00, 121 HOST_CS_SELECTOR = 0x00000c02, 122 HOST_SS_SELECTOR = 0x00000c04, 123 HOST_DS_SELECTOR = 0x00000c06, 124 HOST_FS_SELECTOR = 0x00000c08, 125 HOST_GS_SELECTOR = 0x00000c0a, 126 HOST_TR_SELECTOR = 0x00000c0c, 127 IO_BITMAP_A = 0x00002000, 128 IO_BITMAP_A_HIGH = 0x00002001, 129 IO_BITMAP_B = 0x00002002, 130 IO_BITMAP_B_HIGH = 0x00002003, 131 MSR_BITMAP = 0x00002004, 132 MSR_BITMAP_HIGH = 0x00002005, 133 VM_EXIT_MSR_STORE_ADDR = 0x00002006, 134 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007, 135 VM_EXIT_MSR_LOAD_ADDR = 0x00002008, 136 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009, 137 VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a, 138 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b, 139 TSC_OFFSET = 0x00002010, 140 TSC_OFFSET_HIGH = 0x00002011, 141 VIRTUAL_APIC_PAGE_ADDR = 0x00002012, 142 VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013, 143 APIC_ACCESS_ADDR = 0x00002014, 144 APIC_ACCESS_ADDR_HIGH = 0x00002015, 145 POSTED_INTR_DESC_ADDR = 0x00002016, 146 POSTED_INTR_DESC_ADDR_HIGH = 0x00002017, 147 EPT_POINTER = 0x0000201a, 148 EPT_POINTER_HIGH = 0x0000201b, 149 EOI_EXIT_BITMAP0 = 0x0000201c, 150 EOI_EXIT_BITMAP0_HIGH = 0x0000201d, 151 EOI_EXIT_BITMAP1 = 0x0000201e, 152 EOI_EXIT_BITMAP1_HIGH = 0x0000201f, 153 EOI_EXIT_BITMAP2 = 0x00002020, 154 EOI_EXIT_BITMAP2_HIGH = 0x00002021, 155 EOI_EXIT_BITMAP3 = 0x00002022, 156 EOI_EXIT_BITMAP3_HIGH = 0x00002023, 157 VMREAD_BITMAP = 0x00002026, 158 VMWRITE_BITMAP = 0x00002028, 159 GUEST_PHYSICAL_ADDRESS = 0x00002400, 160 GUEST_PHYSICAL_ADDRESS_HIGH = 0x00002401, 161 VMCS_LINK_POINTER = 0x00002800, 162 VMCS_LINK_POINTER_HIGH = 0x00002801, 163 GUEST_IA32_DEBUGCTL = 0x00002802, 164 GUEST_IA32_DEBUGCTL_HIGH = 0x00002803, 165 GUEST_IA32_PAT = 0x00002804, 166 GUEST_IA32_PAT_HIGH = 0x00002805, 167 GUEST_IA32_EFER = 0x00002806, 168 GUEST_IA32_EFER_HIGH = 0x00002807, 169 GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808, 170 GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809, 171 GUEST_PDPTR0 = 0x0000280a, 172 GUEST_PDPTR0_HIGH = 0x0000280b, 173 GUEST_PDPTR1 = 0x0000280c, 174 GUEST_PDPTR1_HIGH = 0x0000280d, 175 GUEST_PDPTR2 = 0x0000280e, 176 GUEST_PDPTR2_HIGH = 0x0000280f, 177 GUEST_PDPTR3 = 0x00002810, 178 GUEST_PDPTR3_HIGH = 0x00002811, 179 GUEST_BNDCFGS = 0x00002812, 180 GUEST_BNDCFGS_HIGH = 0x00002813, 181 HOST_IA32_PAT = 0x00002c00, 182 HOST_IA32_PAT_HIGH = 0x00002c01, 183 HOST_IA32_EFER = 0x00002c02, 184 HOST_IA32_EFER_HIGH = 0x00002c03, 185 HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04, 186 HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05, 187 PIN_BASED_VM_EXEC_CONTROL = 0x00004000, 188 CPU_BASED_VM_EXEC_CONTROL = 0x00004002, 189 EXCEPTION_BITMAP = 0x00004004, 190 PAGE_FAULT_ERROR_CODE_MASK = 0x00004006, 191 PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008, 192 CR3_TARGET_COUNT = 0x0000400a, 193 VM_EXIT_CONTROLS = 0x0000400c, 194 VM_EXIT_MSR_STORE_COUNT = 0x0000400e, 195 VM_EXIT_MSR_LOAD_COUNT = 0x00004010, 196 VM_ENTRY_CONTROLS = 0x00004012, 197 VM_ENTRY_MSR_LOAD_COUNT = 0x00004014, 198 VM_ENTRY_INTR_INFO_FIELD = 0x00004016, 199 VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018, 200 VM_ENTRY_INSTRUCTION_LEN = 0x0000401a, 201 TPR_THRESHOLD = 0x0000401c, 202 SECONDARY_VM_EXEC_CONTROL = 0x0000401e, 203 PLE_GAP = 0x00004020, 204 PLE_WINDOW = 0x00004022, 205 VM_INSTRUCTION_ERROR = 0x00004400, 206 VM_EXIT_REASON = 0x00004402, 207 VM_EXIT_INTR_INFO = 0x00004404, 208 VM_EXIT_INTR_ERROR_CODE = 0x00004406, 209 IDT_VECTORING_INFO_FIELD = 0x00004408, 210 IDT_VECTORING_ERROR_CODE = 0x0000440a, 211 VM_EXIT_INSTRUCTION_LEN = 0x0000440c, 212 VMX_INSTRUCTION_INFO = 0x0000440e, 213 GUEST_ES_LIMIT = 0x00004800, 214 GUEST_CS_LIMIT = 0x00004802, 215 GUEST_SS_LIMIT = 0x00004804, 216 GUEST_DS_LIMIT = 0x00004806, 217 GUEST_FS_LIMIT = 0x00004808, 218 GUEST_GS_LIMIT = 0x0000480a, 219 GUEST_LDTR_LIMIT = 0x0000480c, 220 GUEST_TR_LIMIT = 0x0000480e, 221 GUEST_GDTR_LIMIT = 0x00004810, 222 GUEST_IDTR_LIMIT = 0x00004812, 223 GUEST_ES_AR_BYTES = 0x00004814, 224 GUEST_CS_AR_BYTES = 0x00004816, 225 GUEST_SS_AR_BYTES = 0x00004818, 226 GUEST_DS_AR_BYTES = 0x0000481a, 227 GUEST_FS_AR_BYTES = 0x0000481c, 228 GUEST_GS_AR_BYTES = 0x0000481e, 229 GUEST_LDTR_AR_BYTES = 0x00004820, 230 GUEST_TR_AR_BYTES = 0x00004822, 231 GUEST_INTERRUPTIBILITY_INFO = 0x00004824, 232 GUEST_ACTIVITY_STATE = 0X00004826, 233 GUEST_SYSENTER_CS = 0x0000482A, 234 VMX_PREEMPTION_TIMER_VALUE = 0x0000482E, 235 HOST_IA32_SYSENTER_CS = 0x00004c00, 236 CR0_GUEST_HOST_MASK = 0x00006000, 237 CR4_GUEST_HOST_MASK = 0x00006002, 238 CR0_READ_SHADOW = 0x00006004, 239 CR4_READ_SHADOW = 0x00006006, 240 CR3_TARGET_VALUE0 = 0x00006008, 241 CR3_TARGET_VALUE1 = 0x0000600a, 242 CR3_TARGET_VALUE2 = 0x0000600c, 243 CR3_TARGET_VALUE3 = 0x0000600e, 244 EXIT_QUALIFICATION = 0x00006400, 245 GUEST_LINEAR_ADDRESS = 0x0000640a, 246 GUEST_CR0 = 0x00006800, 247 GUEST_CR3 = 0x00006802, 248 GUEST_CR4 = 0x00006804, 249 GUEST_ES_BASE = 0x00006806, 250 GUEST_CS_BASE = 0x00006808, 251 GUEST_SS_BASE = 0x0000680a, 252 GUEST_DS_BASE = 0x0000680c, 253 GUEST_FS_BASE = 0x0000680e, 254 GUEST_GS_BASE = 0x00006810, 255 GUEST_LDTR_BASE = 0x00006812, 256 GUEST_TR_BASE = 0x00006814, 257 GUEST_GDTR_BASE = 0x00006816, 258 GUEST_IDTR_BASE = 0x00006818, 259 GUEST_DR7 = 0x0000681a, 260 GUEST_RSP = 0x0000681c, 261 GUEST_RIP = 0x0000681e, 262 GUEST_RFLAGS = 0x00006820, 263 GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822, 264 GUEST_SYSENTER_ESP = 0x00006824, 265 GUEST_SYSENTER_EIP = 0x00006826, 266 HOST_CR0 = 0x00006c00, 267 HOST_CR3 = 0x00006c02, 268 HOST_CR4 = 0x00006c04, 269 HOST_FS_BASE = 0x00006c06, 270 HOST_GS_BASE = 0x00006c08, 271 HOST_TR_BASE = 0x00006c0a, 272 HOST_GDTR_BASE = 0x00006c0c, 273 HOST_IDTR_BASE = 0x00006c0e, 274 HOST_IA32_SYSENTER_ESP = 0x00006c10, 275 HOST_IA32_SYSENTER_EIP = 0x00006c12, 276 HOST_RSP = 0x00006c14, 277 HOST_RIP = 0x00006c16, 278 }; 279 280 /* 281 * Interruption-information format 282 */ 283 #define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */ 284 #define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */ 285 #define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */ 286 #define INTR_INFO_UNBLOCK_NMI 0x1000 /* 12 */ 287 #define INTR_INFO_VALID_MASK 0x80000000 /* 31 */ 288 #define INTR_INFO_RESVD_BITS_MASK 0x7ffff000 289 290 #define VECTORING_INFO_VECTOR_MASK INTR_INFO_VECTOR_MASK 291 #define VECTORING_INFO_TYPE_MASK INTR_INFO_INTR_TYPE_MASK 292 #define VECTORING_INFO_DELIVER_CODE_MASK INTR_INFO_DELIVER_CODE_MASK 293 #define VECTORING_INFO_VALID_MASK INTR_INFO_VALID_MASK 294 295 #define INTR_TYPE_EXT_INTR (0 << 8) /* external interrupt */ 296 #define INTR_TYPE_NMI_INTR (2 << 8) /* NMI */ 297 #define INTR_TYPE_HARD_EXCEPTION (3 << 8) /* processor exception */ 298 #define INTR_TYPE_SOFT_INTR (4 << 8) /* software interrupt */ 299 #define INTR_TYPE_SOFT_EXCEPTION (6 << 8) /* software exception */ 300 301 /* GUEST_INTERRUPTIBILITY_INFO flags. */ 302 #define GUEST_INTR_STATE_STI 0x00000001 303 #define GUEST_INTR_STATE_MOV_SS 0x00000002 304 #define GUEST_INTR_STATE_SMI 0x00000004 305 #define GUEST_INTR_STATE_NMI 0x00000008 306 307 /* GUEST_ACTIVITY_STATE flags */ 308 #define GUEST_ACTIVITY_ACTIVE 0 309 #define GUEST_ACTIVITY_HLT 1 310 #define GUEST_ACTIVITY_SHUTDOWN 2 311 #define GUEST_ACTIVITY_WAIT_SIPI 3 312 313 /* 314 * Exit Qualifications for MOV for Control Register Access 315 */ 316 #define CONTROL_REG_ACCESS_NUM 0x7 /* 2:0, number of control reg.*/ 317 #define CONTROL_REG_ACCESS_TYPE 0x30 /* 5:4, access type */ 318 #define CONTROL_REG_ACCESS_REG 0xf00 /* 10:8, general purpose reg. */ 319 #define LMSW_SOURCE_DATA_SHIFT 16 320 #define LMSW_SOURCE_DATA (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */ 321 #define REG_EAX (0 << 8) 322 #define REG_ECX (1 << 8) 323 #define REG_EDX (2 << 8) 324 #define REG_EBX (3 << 8) 325 #define REG_ESP (4 << 8) 326 #define REG_EBP (5 << 8) 327 #define REG_ESI (6 << 8) 328 #define REG_EDI (7 << 8) 329 #define REG_R8 (8 << 8) 330 #define REG_R9 (9 << 8) 331 #define REG_R10 (10 << 8) 332 #define REG_R11 (11 << 8) 333 #define REG_R12 (12 << 8) 334 #define REG_R13 (13 << 8) 335 #define REG_R14 (14 << 8) 336 #define REG_R15 (15 << 8) 337 338 /* 339 * Exit Qualifications for MOV for Debug Register Access 340 */ 341 #define DEBUG_REG_ACCESS_NUM 0x7 /* 2:0, number of debug reg. */ 342 #define DEBUG_REG_ACCESS_TYPE 0x10 /* 4, direction of access */ 343 #define TYPE_MOV_TO_DR (0 << 4) 344 #define TYPE_MOV_FROM_DR (1 << 4) 345 #define DEBUG_REG_ACCESS_REG(eq) (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */ 346 347 348 /* 349 * Exit Qualifications for APIC-Access 350 */ 351 #define APIC_ACCESS_OFFSET 0xfff /* 11:0, offset within the APIC page */ 352 #define APIC_ACCESS_TYPE 0xf000 /* 15:12, access type */ 353 #define TYPE_LINEAR_APIC_INST_READ (0 << 12) 354 #define TYPE_LINEAR_APIC_INST_WRITE (1 << 12) 355 #define TYPE_LINEAR_APIC_INST_FETCH (2 << 12) 356 #define TYPE_LINEAR_APIC_EVENT (3 << 12) 357 #define TYPE_PHYSICAL_APIC_EVENT (10 << 12) 358 #define TYPE_PHYSICAL_APIC_INST (15 << 12) 359 360 /* segment AR */ 361 #define SEGMENT_AR_L_MASK (1 << 13) 362 363 #define AR_TYPE_ACCESSES_MASK 1 364 #define AR_TYPE_READABLE_MASK (1 << 1) 365 #define AR_TYPE_WRITEABLE_MASK (1 << 2) 366 #define AR_TYPE_CODE_MASK (1 << 3) 367 #define AR_TYPE_MASK 0x0f 368 #define AR_TYPE_BUSY_64_TSS 11 369 #define AR_TYPE_BUSY_32_TSS 11 370 #define AR_TYPE_BUSY_16_TSS 3 371 #define AR_TYPE_LDT 2 372 373 #define AR_UNUSABLE_MASK (1 << 16) 374 #define AR_S_MASK (1 << 4) 375 #define AR_P_MASK (1 << 7) 376 #define AR_L_MASK (1 << 13) 377 #define AR_DB_MASK (1 << 14) 378 #define AR_G_MASK (1 << 15) 379 #define AR_DPL_SHIFT 5 380 #define AR_DPL(ar) (((ar) >> AR_DPL_SHIFT) & 3) 381 382 #define AR_RESERVD_MASK 0xfffe0f00 383 384 #define TSS_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 0) 385 #define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 1) 386 #define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 2) 387 388 #define VMX_NR_VPIDS (1 << 16) 389 #define VMX_VPID_EXTENT_SINGLE_CONTEXT 1 390 #define VMX_VPID_EXTENT_ALL_CONTEXT 2 391 392 #define VMX_EPT_EXTENT_INDIVIDUAL_ADDR 0 393 #define VMX_EPT_EXTENT_CONTEXT 1 394 #define VMX_EPT_EXTENT_GLOBAL 2 395 #define VMX_EPT_EXTENT_SHIFT 24 396 397 #define VMX_EPT_EXECUTE_ONLY_BIT (1ull) 398 #define VMX_EPT_PAGE_WALK_4_BIT (1ull << 6) 399 #define VMX_EPTP_UC_BIT (1ull << 8) 400 #define VMX_EPTP_WB_BIT (1ull << 14) 401 #define VMX_EPT_2MB_PAGE_BIT (1ull << 16) 402 #define VMX_EPT_1GB_PAGE_BIT (1ull << 17) 403 #define VMX_EPT_INVEPT_BIT (1ull << 20) 404 #define VMX_EPT_AD_BIT (1ull << 21) 405 #define VMX_EPT_EXTENT_CONTEXT_BIT (1ull << 25) 406 #define VMX_EPT_EXTENT_GLOBAL_BIT (1ull << 26) 407 408 #define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT (1ull << 9) /* (41 - 32) */ 409 #define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT (1ull << 10) /* (42 - 32) */ 410 411 #define VMX_EPT_DEFAULT_GAW 3 412 #define VMX_EPT_MAX_GAW 0x4 413 #define VMX_EPT_MT_EPTE_SHIFT 3 414 #define VMX_EPT_GAW_EPTP_SHIFT 3 415 #define VMX_EPT_AD_ENABLE_BIT (1ull << 6) 416 #define VMX_EPT_DEFAULT_MT 0x6ull 417 #define VMX_EPT_READABLE_MASK 0x1ull 418 #define VMX_EPT_WRITABLE_MASK 0x2ull 419 #define VMX_EPT_EXECUTABLE_MASK 0x4ull 420 #define VMX_EPT_IPAT_BIT (1ull << 6) 421 #define VMX_EPT_ACCESS_BIT (1ull << 8) 422 #define VMX_EPT_DIRTY_BIT (1ull << 9) 423 424 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul 425 426 427 #define ASM_VMX_VMCLEAR_RAX ".byte 0x66, 0x0f, 0xc7, 0x30" 428 #define ASM_VMX_VMLAUNCH ".byte 0x0f, 0x01, 0xc2" 429 #define ASM_VMX_VMRESUME ".byte 0x0f, 0x01, 0xc3" 430 #define ASM_VMX_VMPTRLD_RAX ".byte 0x0f, 0xc7, 0x30" 431 #define ASM_VMX_VMREAD_RDX_RAX ".byte 0x0f, 0x78, 0xd0" 432 #define ASM_VMX_VMWRITE_RAX_RDX ".byte 0x0f, 0x79, 0xd0" 433 #define ASM_VMX_VMWRITE_RSP_RDX ".byte 0x0f, 0x79, 0xd4" 434 #define ASM_VMX_VMXOFF ".byte 0x0f, 0x01, 0xc4" 435 #define ASM_VMX_VMXON_RAX ".byte 0xf3, 0x0f, 0xc7, 0x30" 436 #define ASM_VMX_INVEPT ".byte 0x66, 0x0f, 0x38, 0x80, 0x08" 437 #define ASM_VMX_INVVPID ".byte 0x66, 0x0f, 0x38, 0x81, 0x08" 438 439 struct vmx_msr_entry { 440 u32 index; 441 u32 reserved; 442 u64 value; 443 } __aligned(16); 444 445 /* 446 * Exit Qualifications for entry failure during or after loading guest state 447 */ 448 #define ENTRY_FAIL_DEFAULT 0 449 #define ENTRY_FAIL_PDPTE 2 450 #define ENTRY_FAIL_NMI 3 451 #define ENTRY_FAIL_VMCS_LINK_PTR 4 452 453 /* 454 * VM-instruction error numbers 455 */ 456 enum vm_instruction_error_number { 457 VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1, 458 VMXERR_VMCLEAR_INVALID_ADDRESS = 2, 459 VMXERR_VMCLEAR_VMXON_POINTER = 3, 460 VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4, 461 VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5, 462 VMXERR_VMRESUME_AFTER_VMXOFF = 6, 463 VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7, 464 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8, 465 VMXERR_VMPTRLD_INVALID_ADDRESS = 9, 466 VMXERR_VMPTRLD_VMXON_POINTER = 10, 467 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11, 468 VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12, 469 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13, 470 VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15, 471 VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16, 472 VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17, 473 VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18, 474 VMXERR_VMCALL_NONCLEAR_VMCS = 19, 475 VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20, 476 VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22, 477 VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23, 478 VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24, 479 VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25, 480 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26, 481 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28, 482 }; 483 484 #endif 485