1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * vmx.h: VMX Architecture related definitions 4 * Copyright (c) 2004, Intel Corporation. 5 * 6 * A few random additions are: 7 * Copyright (C) 2006 Qumranet 8 * Avi Kivity <avi@qumranet.com> 9 * Yaniv Kamay <yaniv@qumranet.com> 10 */ 11 #ifndef VMX_H 12 #define VMX_H 13 14 15 #include <linux/bitops.h> 16 #include <linux/types.h> 17 #include <uapi/asm/vmx.h> 18 19 /* 20 * Definitions of Primary Processor-Based VM-Execution Controls. 21 */ 22 #define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004 23 #define CPU_BASED_USE_TSC_OFFSETING 0x00000008 24 #define CPU_BASED_HLT_EXITING 0x00000080 25 #define CPU_BASED_INVLPG_EXITING 0x00000200 26 #define CPU_BASED_MWAIT_EXITING 0x00000400 27 #define CPU_BASED_RDPMC_EXITING 0x00000800 28 #define CPU_BASED_RDTSC_EXITING 0x00001000 29 #define CPU_BASED_CR3_LOAD_EXITING 0x00008000 30 #define CPU_BASED_CR3_STORE_EXITING 0x00010000 31 #define CPU_BASED_CR8_LOAD_EXITING 0x00080000 32 #define CPU_BASED_CR8_STORE_EXITING 0x00100000 33 #define CPU_BASED_TPR_SHADOW 0x00200000 34 #define CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000 35 #define CPU_BASED_MOV_DR_EXITING 0x00800000 36 #define CPU_BASED_UNCOND_IO_EXITING 0x01000000 37 #define CPU_BASED_USE_IO_BITMAPS 0x02000000 38 #define CPU_BASED_MONITOR_TRAP_FLAG 0x08000000 39 #define CPU_BASED_USE_MSR_BITMAPS 0x10000000 40 #define CPU_BASED_MONITOR_EXITING 0x20000000 41 #define CPU_BASED_PAUSE_EXITING 0x40000000 42 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000 43 44 #define CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x0401e172 45 46 /* 47 * Definitions of Secondary Processor-Based VM-Execution Controls. 48 */ 49 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001 50 #define SECONDARY_EXEC_ENABLE_EPT 0x00000002 51 #define SECONDARY_EXEC_DESC 0x00000004 52 #define SECONDARY_EXEC_RDTSCP 0x00000008 53 #define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010 54 #define SECONDARY_EXEC_ENABLE_VPID 0x00000020 55 #define SECONDARY_EXEC_WBINVD_EXITING 0x00000040 56 #define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080 57 #define SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100 58 #define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200 59 #define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400 60 #define SECONDARY_EXEC_RDRAND_EXITING 0x00000800 61 #define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000 62 #define SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000 63 #define SECONDARY_EXEC_SHADOW_VMCS 0x00004000 64 #define SECONDARY_EXEC_ENCLS_EXITING 0x00008000 65 #define SECONDARY_EXEC_RDSEED_EXITING 0x00010000 66 #define SECONDARY_EXEC_ENABLE_PML 0x00020000 67 #define SECONDARY_EXEC_PT_CONCEAL_VMX 0x00080000 68 #define SECONDARY_EXEC_XSAVES 0x00100000 69 #define SECONDARY_EXEC_PT_USE_GPA 0x01000000 70 #define SECONDARY_EXEC_MODE_BASED_EPT_EXEC 0x00400000 71 #define SECONDARY_EXEC_TSC_SCALING 0x02000000 72 73 #define PIN_BASED_EXT_INTR_MASK 0x00000001 74 #define PIN_BASED_NMI_EXITING 0x00000008 75 #define PIN_BASED_VIRTUAL_NMIS 0x00000020 76 #define PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040 77 #define PIN_BASED_POSTED_INTR 0x00000080 78 79 #define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x00000016 80 81 #define VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004 82 #define VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200 83 #define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000 84 #define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000 85 #define VM_EXIT_SAVE_IA32_PAT 0x00040000 86 #define VM_EXIT_LOAD_IA32_PAT 0x00080000 87 #define VM_EXIT_SAVE_IA32_EFER 0x00100000 88 #define VM_EXIT_LOAD_IA32_EFER 0x00200000 89 #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000 90 #define VM_EXIT_CLEAR_BNDCFGS 0x00800000 91 #define VM_EXIT_PT_CONCEAL_PIP 0x01000000 92 #define VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000 93 94 #define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR 0x00036dff 95 96 #define VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004 97 #define VM_ENTRY_IA32E_MODE 0x00000200 98 #define VM_ENTRY_SMM 0x00000400 99 #define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800 100 #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000 101 #define VM_ENTRY_LOAD_IA32_PAT 0x00004000 102 #define VM_ENTRY_LOAD_IA32_EFER 0x00008000 103 #define VM_ENTRY_LOAD_BNDCFGS 0x00010000 104 #define VM_ENTRY_PT_CONCEAL_PIP 0x00020000 105 #define VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000 106 107 #define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR 0x000011ff 108 109 #define VMX_MISC_PREEMPTION_TIMER_RATE_MASK 0x0000001f 110 #define VMX_MISC_SAVE_EFER_LMA 0x00000020 111 #define VMX_MISC_ACTIVITY_HLT 0x00000040 112 #define VMX_MISC_ZERO_LEN_INS 0x40000000 113 114 /* VMFUNC functions */ 115 #define VMX_VMFUNC_EPTP_SWITCHING 0x00000001 116 #define VMFUNC_EPTP_ENTRIES 512 117 118 static inline u32 vmx_basic_vmcs_revision_id(u64 vmx_basic) 119 { 120 return vmx_basic & GENMASK_ULL(30, 0); 121 } 122 123 static inline u32 vmx_basic_vmcs_size(u64 vmx_basic) 124 { 125 return (vmx_basic & GENMASK_ULL(44, 32)) >> 32; 126 } 127 128 static inline int vmx_misc_preemption_timer_rate(u64 vmx_misc) 129 { 130 return vmx_misc & VMX_MISC_PREEMPTION_TIMER_RATE_MASK; 131 } 132 133 static inline int vmx_misc_cr3_count(u64 vmx_misc) 134 { 135 return (vmx_misc & GENMASK_ULL(24, 16)) >> 16; 136 } 137 138 static inline int vmx_misc_max_msr(u64 vmx_misc) 139 { 140 return (vmx_misc & GENMASK_ULL(27, 25)) >> 25; 141 } 142 143 static inline int vmx_misc_mseg_revid(u64 vmx_misc) 144 { 145 return (vmx_misc & GENMASK_ULL(63, 32)) >> 32; 146 } 147 148 /* VMCS Encodings */ 149 enum vmcs_field { 150 VIRTUAL_PROCESSOR_ID = 0x00000000, 151 POSTED_INTR_NV = 0x00000002, 152 GUEST_ES_SELECTOR = 0x00000800, 153 GUEST_CS_SELECTOR = 0x00000802, 154 GUEST_SS_SELECTOR = 0x00000804, 155 GUEST_DS_SELECTOR = 0x00000806, 156 GUEST_FS_SELECTOR = 0x00000808, 157 GUEST_GS_SELECTOR = 0x0000080a, 158 GUEST_LDTR_SELECTOR = 0x0000080c, 159 GUEST_TR_SELECTOR = 0x0000080e, 160 GUEST_INTR_STATUS = 0x00000810, 161 GUEST_PML_INDEX = 0x00000812, 162 HOST_ES_SELECTOR = 0x00000c00, 163 HOST_CS_SELECTOR = 0x00000c02, 164 HOST_SS_SELECTOR = 0x00000c04, 165 HOST_DS_SELECTOR = 0x00000c06, 166 HOST_FS_SELECTOR = 0x00000c08, 167 HOST_GS_SELECTOR = 0x00000c0a, 168 HOST_TR_SELECTOR = 0x00000c0c, 169 IO_BITMAP_A = 0x00002000, 170 IO_BITMAP_A_HIGH = 0x00002001, 171 IO_BITMAP_B = 0x00002002, 172 IO_BITMAP_B_HIGH = 0x00002003, 173 MSR_BITMAP = 0x00002004, 174 MSR_BITMAP_HIGH = 0x00002005, 175 VM_EXIT_MSR_STORE_ADDR = 0x00002006, 176 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007, 177 VM_EXIT_MSR_LOAD_ADDR = 0x00002008, 178 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009, 179 VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a, 180 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b, 181 PML_ADDRESS = 0x0000200e, 182 PML_ADDRESS_HIGH = 0x0000200f, 183 TSC_OFFSET = 0x00002010, 184 TSC_OFFSET_HIGH = 0x00002011, 185 VIRTUAL_APIC_PAGE_ADDR = 0x00002012, 186 VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013, 187 APIC_ACCESS_ADDR = 0x00002014, 188 APIC_ACCESS_ADDR_HIGH = 0x00002015, 189 POSTED_INTR_DESC_ADDR = 0x00002016, 190 POSTED_INTR_DESC_ADDR_HIGH = 0x00002017, 191 VM_FUNCTION_CONTROL = 0x00002018, 192 VM_FUNCTION_CONTROL_HIGH = 0x00002019, 193 EPT_POINTER = 0x0000201a, 194 EPT_POINTER_HIGH = 0x0000201b, 195 EOI_EXIT_BITMAP0 = 0x0000201c, 196 EOI_EXIT_BITMAP0_HIGH = 0x0000201d, 197 EOI_EXIT_BITMAP1 = 0x0000201e, 198 EOI_EXIT_BITMAP1_HIGH = 0x0000201f, 199 EOI_EXIT_BITMAP2 = 0x00002020, 200 EOI_EXIT_BITMAP2_HIGH = 0x00002021, 201 EOI_EXIT_BITMAP3 = 0x00002022, 202 EOI_EXIT_BITMAP3_HIGH = 0x00002023, 203 EPTP_LIST_ADDRESS = 0x00002024, 204 EPTP_LIST_ADDRESS_HIGH = 0x00002025, 205 VMREAD_BITMAP = 0x00002026, 206 VMREAD_BITMAP_HIGH = 0x00002027, 207 VMWRITE_BITMAP = 0x00002028, 208 VMWRITE_BITMAP_HIGH = 0x00002029, 209 XSS_EXIT_BITMAP = 0x0000202C, 210 XSS_EXIT_BITMAP_HIGH = 0x0000202D, 211 ENCLS_EXITING_BITMAP = 0x0000202E, 212 ENCLS_EXITING_BITMAP_HIGH = 0x0000202F, 213 TSC_MULTIPLIER = 0x00002032, 214 TSC_MULTIPLIER_HIGH = 0x00002033, 215 GUEST_PHYSICAL_ADDRESS = 0x00002400, 216 GUEST_PHYSICAL_ADDRESS_HIGH = 0x00002401, 217 VMCS_LINK_POINTER = 0x00002800, 218 VMCS_LINK_POINTER_HIGH = 0x00002801, 219 GUEST_IA32_DEBUGCTL = 0x00002802, 220 GUEST_IA32_DEBUGCTL_HIGH = 0x00002803, 221 GUEST_IA32_PAT = 0x00002804, 222 GUEST_IA32_PAT_HIGH = 0x00002805, 223 GUEST_IA32_EFER = 0x00002806, 224 GUEST_IA32_EFER_HIGH = 0x00002807, 225 GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808, 226 GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809, 227 GUEST_PDPTR0 = 0x0000280a, 228 GUEST_PDPTR0_HIGH = 0x0000280b, 229 GUEST_PDPTR1 = 0x0000280c, 230 GUEST_PDPTR1_HIGH = 0x0000280d, 231 GUEST_PDPTR2 = 0x0000280e, 232 GUEST_PDPTR2_HIGH = 0x0000280f, 233 GUEST_PDPTR3 = 0x00002810, 234 GUEST_PDPTR3_HIGH = 0x00002811, 235 GUEST_BNDCFGS = 0x00002812, 236 GUEST_BNDCFGS_HIGH = 0x00002813, 237 GUEST_IA32_RTIT_CTL = 0x00002814, 238 GUEST_IA32_RTIT_CTL_HIGH = 0x00002815, 239 HOST_IA32_PAT = 0x00002c00, 240 HOST_IA32_PAT_HIGH = 0x00002c01, 241 HOST_IA32_EFER = 0x00002c02, 242 HOST_IA32_EFER_HIGH = 0x00002c03, 243 HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04, 244 HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05, 245 PIN_BASED_VM_EXEC_CONTROL = 0x00004000, 246 CPU_BASED_VM_EXEC_CONTROL = 0x00004002, 247 EXCEPTION_BITMAP = 0x00004004, 248 PAGE_FAULT_ERROR_CODE_MASK = 0x00004006, 249 PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008, 250 CR3_TARGET_COUNT = 0x0000400a, 251 VM_EXIT_CONTROLS = 0x0000400c, 252 VM_EXIT_MSR_STORE_COUNT = 0x0000400e, 253 VM_EXIT_MSR_LOAD_COUNT = 0x00004010, 254 VM_ENTRY_CONTROLS = 0x00004012, 255 VM_ENTRY_MSR_LOAD_COUNT = 0x00004014, 256 VM_ENTRY_INTR_INFO_FIELD = 0x00004016, 257 VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018, 258 VM_ENTRY_INSTRUCTION_LEN = 0x0000401a, 259 TPR_THRESHOLD = 0x0000401c, 260 SECONDARY_VM_EXEC_CONTROL = 0x0000401e, 261 PLE_GAP = 0x00004020, 262 PLE_WINDOW = 0x00004022, 263 VM_INSTRUCTION_ERROR = 0x00004400, 264 VM_EXIT_REASON = 0x00004402, 265 VM_EXIT_INTR_INFO = 0x00004404, 266 VM_EXIT_INTR_ERROR_CODE = 0x00004406, 267 IDT_VECTORING_INFO_FIELD = 0x00004408, 268 IDT_VECTORING_ERROR_CODE = 0x0000440a, 269 VM_EXIT_INSTRUCTION_LEN = 0x0000440c, 270 VMX_INSTRUCTION_INFO = 0x0000440e, 271 GUEST_ES_LIMIT = 0x00004800, 272 GUEST_CS_LIMIT = 0x00004802, 273 GUEST_SS_LIMIT = 0x00004804, 274 GUEST_DS_LIMIT = 0x00004806, 275 GUEST_FS_LIMIT = 0x00004808, 276 GUEST_GS_LIMIT = 0x0000480a, 277 GUEST_LDTR_LIMIT = 0x0000480c, 278 GUEST_TR_LIMIT = 0x0000480e, 279 GUEST_GDTR_LIMIT = 0x00004810, 280 GUEST_IDTR_LIMIT = 0x00004812, 281 GUEST_ES_AR_BYTES = 0x00004814, 282 GUEST_CS_AR_BYTES = 0x00004816, 283 GUEST_SS_AR_BYTES = 0x00004818, 284 GUEST_DS_AR_BYTES = 0x0000481a, 285 GUEST_FS_AR_BYTES = 0x0000481c, 286 GUEST_GS_AR_BYTES = 0x0000481e, 287 GUEST_LDTR_AR_BYTES = 0x00004820, 288 GUEST_TR_AR_BYTES = 0x00004822, 289 GUEST_INTERRUPTIBILITY_INFO = 0x00004824, 290 GUEST_ACTIVITY_STATE = 0X00004826, 291 GUEST_SYSENTER_CS = 0x0000482A, 292 VMX_PREEMPTION_TIMER_VALUE = 0x0000482E, 293 HOST_IA32_SYSENTER_CS = 0x00004c00, 294 CR0_GUEST_HOST_MASK = 0x00006000, 295 CR4_GUEST_HOST_MASK = 0x00006002, 296 CR0_READ_SHADOW = 0x00006004, 297 CR4_READ_SHADOW = 0x00006006, 298 CR3_TARGET_VALUE0 = 0x00006008, 299 CR3_TARGET_VALUE1 = 0x0000600a, 300 CR3_TARGET_VALUE2 = 0x0000600c, 301 CR3_TARGET_VALUE3 = 0x0000600e, 302 EXIT_QUALIFICATION = 0x00006400, 303 GUEST_LINEAR_ADDRESS = 0x0000640a, 304 GUEST_CR0 = 0x00006800, 305 GUEST_CR3 = 0x00006802, 306 GUEST_CR4 = 0x00006804, 307 GUEST_ES_BASE = 0x00006806, 308 GUEST_CS_BASE = 0x00006808, 309 GUEST_SS_BASE = 0x0000680a, 310 GUEST_DS_BASE = 0x0000680c, 311 GUEST_FS_BASE = 0x0000680e, 312 GUEST_GS_BASE = 0x00006810, 313 GUEST_LDTR_BASE = 0x00006812, 314 GUEST_TR_BASE = 0x00006814, 315 GUEST_GDTR_BASE = 0x00006816, 316 GUEST_IDTR_BASE = 0x00006818, 317 GUEST_DR7 = 0x0000681a, 318 GUEST_RSP = 0x0000681c, 319 GUEST_RIP = 0x0000681e, 320 GUEST_RFLAGS = 0x00006820, 321 GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822, 322 GUEST_SYSENTER_ESP = 0x00006824, 323 GUEST_SYSENTER_EIP = 0x00006826, 324 HOST_CR0 = 0x00006c00, 325 HOST_CR3 = 0x00006c02, 326 HOST_CR4 = 0x00006c04, 327 HOST_FS_BASE = 0x00006c06, 328 HOST_GS_BASE = 0x00006c08, 329 HOST_TR_BASE = 0x00006c0a, 330 HOST_GDTR_BASE = 0x00006c0c, 331 HOST_IDTR_BASE = 0x00006c0e, 332 HOST_IA32_SYSENTER_ESP = 0x00006c10, 333 HOST_IA32_SYSENTER_EIP = 0x00006c12, 334 HOST_RSP = 0x00006c14, 335 HOST_RIP = 0x00006c16, 336 }; 337 338 /* 339 * Interruption-information format 340 */ 341 #define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */ 342 #define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */ 343 #define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */ 344 #define INTR_INFO_UNBLOCK_NMI 0x1000 /* 12 */ 345 #define INTR_INFO_VALID_MASK 0x80000000 /* 31 */ 346 #define INTR_INFO_RESVD_BITS_MASK 0x7ffff000 347 348 #define VECTORING_INFO_VECTOR_MASK INTR_INFO_VECTOR_MASK 349 #define VECTORING_INFO_TYPE_MASK INTR_INFO_INTR_TYPE_MASK 350 #define VECTORING_INFO_DELIVER_CODE_MASK INTR_INFO_DELIVER_CODE_MASK 351 #define VECTORING_INFO_VALID_MASK INTR_INFO_VALID_MASK 352 353 #define INTR_TYPE_EXT_INTR (0 << 8) /* external interrupt */ 354 #define INTR_TYPE_RESERVED (1 << 8) /* reserved */ 355 #define INTR_TYPE_NMI_INTR (2 << 8) /* NMI */ 356 #define INTR_TYPE_HARD_EXCEPTION (3 << 8) /* processor exception */ 357 #define INTR_TYPE_SOFT_INTR (4 << 8) /* software interrupt */ 358 #define INTR_TYPE_PRIV_SW_EXCEPTION (5 << 8) /* ICE breakpoint - undocumented */ 359 #define INTR_TYPE_SOFT_EXCEPTION (6 << 8) /* software exception */ 360 #define INTR_TYPE_OTHER_EVENT (7 << 8) /* other event */ 361 362 /* GUEST_INTERRUPTIBILITY_INFO flags. */ 363 #define GUEST_INTR_STATE_STI 0x00000001 364 #define GUEST_INTR_STATE_MOV_SS 0x00000002 365 #define GUEST_INTR_STATE_SMI 0x00000004 366 #define GUEST_INTR_STATE_NMI 0x00000008 367 368 /* GUEST_ACTIVITY_STATE flags */ 369 #define GUEST_ACTIVITY_ACTIVE 0 370 #define GUEST_ACTIVITY_HLT 1 371 #define GUEST_ACTIVITY_SHUTDOWN 2 372 #define GUEST_ACTIVITY_WAIT_SIPI 3 373 374 /* 375 * Exit Qualifications for MOV for Control Register Access 376 */ 377 #define CONTROL_REG_ACCESS_NUM 0x7 /* 2:0, number of control reg.*/ 378 #define CONTROL_REG_ACCESS_TYPE 0x30 /* 5:4, access type */ 379 #define CONTROL_REG_ACCESS_REG 0xf00 /* 10:8, general purpose reg. */ 380 #define LMSW_SOURCE_DATA_SHIFT 16 381 #define LMSW_SOURCE_DATA (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */ 382 #define REG_EAX (0 << 8) 383 #define REG_ECX (1 << 8) 384 #define REG_EDX (2 << 8) 385 #define REG_EBX (3 << 8) 386 #define REG_ESP (4 << 8) 387 #define REG_EBP (5 << 8) 388 #define REG_ESI (6 << 8) 389 #define REG_EDI (7 << 8) 390 #define REG_R8 (8 << 8) 391 #define REG_R9 (9 << 8) 392 #define REG_R10 (10 << 8) 393 #define REG_R11 (11 << 8) 394 #define REG_R12 (12 << 8) 395 #define REG_R13 (13 << 8) 396 #define REG_R14 (14 << 8) 397 #define REG_R15 (15 << 8) 398 399 /* 400 * Exit Qualifications for MOV for Debug Register Access 401 */ 402 #define DEBUG_REG_ACCESS_NUM 0x7 /* 2:0, number of debug reg. */ 403 #define DEBUG_REG_ACCESS_TYPE 0x10 /* 4, direction of access */ 404 #define TYPE_MOV_TO_DR (0 << 4) 405 #define TYPE_MOV_FROM_DR (1 << 4) 406 #define DEBUG_REG_ACCESS_REG(eq) (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */ 407 408 409 /* 410 * Exit Qualifications for APIC-Access 411 */ 412 #define APIC_ACCESS_OFFSET 0xfff /* 11:0, offset within the APIC page */ 413 #define APIC_ACCESS_TYPE 0xf000 /* 15:12, access type */ 414 #define TYPE_LINEAR_APIC_INST_READ (0 << 12) 415 #define TYPE_LINEAR_APIC_INST_WRITE (1 << 12) 416 #define TYPE_LINEAR_APIC_INST_FETCH (2 << 12) 417 #define TYPE_LINEAR_APIC_EVENT (3 << 12) 418 #define TYPE_PHYSICAL_APIC_EVENT (10 << 12) 419 #define TYPE_PHYSICAL_APIC_INST (15 << 12) 420 421 /* segment AR in VMCS -- these are different from what LAR reports */ 422 #define VMX_SEGMENT_AR_L_MASK (1 << 13) 423 424 #define VMX_AR_TYPE_ACCESSES_MASK 1 425 #define VMX_AR_TYPE_READABLE_MASK (1 << 1) 426 #define VMX_AR_TYPE_WRITEABLE_MASK (1 << 2) 427 #define VMX_AR_TYPE_CODE_MASK (1 << 3) 428 #define VMX_AR_TYPE_MASK 0x0f 429 #define VMX_AR_TYPE_BUSY_64_TSS 11 430 #define VMX_AR_TYPE_BUSY_32_TSS 11 431 #define VMX_AR_TYPE_BUSY_16_TSS 3 432 #define VMX_AR_TYPE_LDT 2 433 434 #define VMX_AR_UNUSABLE_MASK (1 << 16) 435 #define VMX_AR_S_MASK (1 << 4) 436 #define VMX_AR_P_MASK (1 << 7) 437 #define VMX_AR_L_MASK (1 << 13) 438 #define VMX_AR_DB_MASK (1 << 14) 439 #define VMX_AR_G_MASK (1 << 15) 440 #define VMX_AR_DPL_SHIFT 5 441 #define VMX_AR_DPL(ar) (((ar) >> VMX_AR_DPL_SHIFT) & 3) 442 443 #define VMX_AR_RESERVD_MASK 0xfffe0f00 444 445 #define TSS_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 0) 446 #define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 1) 447 #define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 2) 448 449 #define VMX_NR_VPIDS (1 << 16) 450 #define VMX_VPID_EXTENT_INDIVIDUAL_ADDR 0 451 #define VMX_VPID_EXTENT_SINGLE_CONTEXT 1 452 #define VMX_VPID_EXTENT_ALL_CONTEXT 2 453 #define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL 3 454 455 #define VMX_EPT_EXTENT_CONTEXT 1 456 #define VMX_EPT_EXTENT_GLOBAL 2 457 #define VMX_EPT_EXTENT_SHIFT 24 458 459 #define VMX_EPT_EXECUTE_ONLY_BIT (1ull) 460 #define VMX_EPT_PAGE_WALK_4_BIT (1ull << 6) 461 #define VMX_EPT_PAGE_WALK_5_BIT (1ull << 7) 462 #define VMX_EPTP_UC_BIT (1ull << 8) 463 #define VMX_EPTP_WB_BIT (1ull << 14) 464 #define VMX_EPT_2MB_PAGE_BIT (1ull << 16) 465 #define VMX_EPT_1GB_PAGE_BIT (1ull << 17) 466 #define VMX_EPT_INVEPT_BIT (1ull << 20) 467 #define VMX_EPT_AD_BIT (1ull << 21) 468 #define VMX_EPT_EXTENT_CONTEXT_BIT (1ull << 25) 469 #define VMX_EPT_EXTENT_GLOBAL_BIT (1ull << 26) 470 471 #define VMX_VPID_INVVPID_BIT (1ull << 0) /* (32 - 32) */ 472 #define VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT (1ull << 8) /* (40 - 32) */ 473 #define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT (1ull << 9) /* (41 - 32) */ 474 #define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT (1ull << 10) /* (42 - 32) */ 475 #define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT (1ull << 11) /* (43 - 32) */ 476 477 #define VMX_EPT_MT_EPTE_SHIFT 3 478 #define VMX_EPTP_PWL_MASK 0x38ull 479 #define VMX_EPTP_PWL_4 0x18ull 480 #define VMX_EPTP_PWL_5 0x20ull 481 #define VMX_EPTP_AD_ENABLE_BIT (1ull << 6) 482 #define VMX_EPTP_MT_MASK 0x7ull 483 #define VMX_EPTP_MT_WB 0x6ull 484 #define VMX_EPTP_MT_UC 0x0ull 485 #define VMX_EPT_READABLE_MASK 0x1ull 486 #define VMX_EPT_WRITABLE_MASK 0x2ull 487 #define VMX_EPT_EXECUTABLE_MASK 0x4ull 488 #define VMX_EPT_IPAT_BIT (1ull << 6) 489 #define VMX_EPT_ACCESS_BIT (1ull << 8) 490 #define VMX_EPT_DIRTY_BIT (1ull << 9) 491 #define VMX_EPT_RWX_MASK (VMX_EPT_READABLE_MASK | \ 492 VMX_EPT_WRITABLE_MASK | \ 493 VMX_EPT_EXECUTABLE_MASK) 494 #define VMX_EPT_MT_MASK (7ull << VMX_EPT_MT_EPTE_SHIFT) 495 496 /* The mask to use to trigger an EPT Misconfiguration in order to track MMIO */ 497 #define VMX_EPT_MISCONFIG_WX_VALUE (VMX_EPT_WRITABLE_MASK | \ 498 VMX_EPT_EXECUTABLE_MASK) 499 500 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul 501 502 struct vmx_msr_entry { 503 u32 index; 504 u32 reserved; 505 u64 value; 506 } __aligned(16); 507 508 /* 509 * Exit Qualifications for entry failure during or after loading guest state 510 */ 511 #define ENTRY_FAIL_DEFAULT 0 512 #define ENTRY_FAIL_PDPTE 2 513 #define ENTRY_FAIL_NMI 3 514 #define ENTRY_FAIL_VMCS_LINK_PTR 4 515 516 /* 517 * Exit Qualifications for EPT Violations 518 */ 519 #define EPT_VIOLATION_ACC_READ_BIT 0 520 #define EPT_VIOLATION_ACC_WRITE_BIT 1 521 #define EPT_VIOLATION_ACC_INSTR_BIT 2 522 #define EPT_VIOLATION_READABLE_BIT 3 523 #define EPT_VIOLATION_WRITABLE_BIT 4 524 #define EPT_VIOLATION_EXECUTABLE_BIT 5 525 #define EPT_VIOLATION_GVA_TRANSLATED_BIT 8 526 #define EPT_VIOLATION_ACC_READ (1 << EPT_VIOLATION_ACC_READ_BIT) 527 #define EPT_VIOLATION_ACC_WRITE (1 << EPT_VIOLATION_ACC_WRITE_BIT) 528 #define EPT_VIOLATION_ACC_INSTR (1 << EPT_VIOLATION_ACC_INSTR_BIT) 529 #define EPT_VIOLATION_READABLE (1 << EPT_VIOLATION_READABLE_BIT) 530 #define EPT_VIOLATION_WRITABLE (1 << EPT_VIOLATION_WRITABLE_BIT) 531 #define EPT_VIOLATION_EXECUTABLE (1 << EPT_VIOLATION_EXECUTABLE_BIT) 532 #define EPT_VIOLATION_GVA_TRANSLATED (1 << EPT_VIOLATION_GVA_TRANSLATED_BIT) 533 534 /* 535 * VM-instruction error numbers 536 */ 537 enum vm_instruction_error_number { 538 VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1, 539 VMXERR_VMCLEAR_INVALID_ADDRESS = 2, 540 VMXERR_VMCLEAR_VMXON_POINTER = 3, 541 VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4, 542 VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5, 543 VMXERR_VMRESUME_AFTER_VMXOFF = 6, 544 VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7, 545 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8, 546 VMXERR_VMPTRLD_INVALID_ADDRESS = 9, 547 VMXERR_VMPTRLD_VMXON_POINTER = 10, 548 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11, 549 VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12, 550 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13, 551 VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15, 552 VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16, 553 VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17, 554 VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18, 555 VMXERR_VMCALL_NONCLEAR_VMCS = 19, 556 VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20, 557 VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22, 558 VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23, 559 VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24, 560 VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25, 561 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26, 562 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28, 563 }; 564 565 enum vmx_l1d_flush_state { 566 VMENTER_L1D_FLUSH_AUTO, 567 VMENTER_L1D_FLUSH_NEVER, 568 VMENTER_L1D_FLUSH_COND, 569 VMENTER_L1D_FLUSH_ALWAYS, 570 VMENTER_L1D_FLUSH_EPT_DISABLED, 571 VMENTER_L1D_FLUSH_NOT_REQUIRED, 572 }; 573 574 extern enum vmx_l1d_flush_state l1tf_vmx_mitigation; 575 576 #endif 577