xref: /openbmc/linux/arch/x86/include/asm/uv/uv_mmrs.h (revision 8365a898)
1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * SGI UV MMR definitions
7  *
8  * Copyright (C) 2007-2016 Silicon Graphics, Inc. All rights reserved.
9  */
10 
11 #ifndef _ASM_X86_UV_UV_MMRS_H
12 #define _ASM_X86_UV_UV_MMRS_H
13 
14 /*
15  * This file contains MMR definitions for all UV hubs types.
16  *
17  * To minimize coding differences between hub types, the symbols are
18  * grouped by architecture types.
19  *
20  * UVH  - definitions common to all UV hub types.
21  * UVXH - definitions common to all UV eXtended hub types (currently 2, 3, 4).
22  * UV1H - definitions specific to UV type 1 hub.
23  * UV2H - definitions specific to UV type 2 hub.
24  * UV3H - definitions specific to UV type 3 hub.
25  * UV4H - definitions specific to UV type 4 hub.
26  *
27  * So in general, MMR addresses and structures are identical on all hubs types.
28  * These MMRs are identified as:
29  *	#define UVH_xxx		<address>
30  *	union uvh_xxx {
31  *		unsigned long       v;
32  *		struct uvh_int_cmpd_s {
33  *		} s;
34  *	};
35  *
36  * If the MMR exists on all hub types but have different addresses,
37  * use a conditional operator to define the value at runtime.
38  *	#define UV1Hxxx	a
39  *	#define UV2Hxxx	b
40  *	#define UV3Hxxx	c
41  *	#define UV4Hxxx	d
42  *	#define UV4AHxxx e
43  *	#define UVHxxx	(is_uv1_hub() ? UV1Hxxx :
44  *			(is_uv2_hub() ? UV2Hxxx :
45  *			(is_uv3_hub() ? UV3Hxxx :
46  *			(is_uv4a_hub() ? UV4AHxxx :
47  *					UV4Hxxx))
48  *
49  * If the MMR exists on all hub types > 1 but have different addresses, the
50  * variation using "UVX" as the prefix exists.
51  *	#define UV2Hxxx	b
52  *	#define UV3Hxxx	c
53  *	#define UV4Hxxx	d
54  *	#define UV4AHxxx e
55  *	#define UVHxxx	(is_uv2_hub() ? UV2Hxxx :
56  *			(is_uv3_hub() ? UV3Hxxx :
57  *			(is_uv4a_hub() ? UV4AHxxx :
58  *					UV4Hxxx))
59  *
60  *	union uvh_xxx {
61  *		unsigned long       v;
62  *		struct uvh_xxx_s {	 # Common fields only
63  *		} s;
64  *		struct uv1h_xxx_s {	 # Full UV1 definition (*)
65  *		} s1;
66  *		struct uv2h_xxx_s {	 # Full UV2 definition (*)
67  *		} s2;
68  *		struct uv3h_xxx_s {	 # Full UV3 definition (*)
69  *		} s3;
70  *		(NOTE: No struct uv4ah_xxx_s members exist)
71  *		struct uv4h_xxx_s {	 # Full UV4 definition (*)
72  *		} s4;
73  *	};
74  *		(* - if present and different than the common struct)
75  *
76  * Only essential differences are enumerated. For example, if the address is
77  * the same for all UV's, only a single #define is generated. Likewise,
78  * if the contents is the same for all hubs, only the "s" structure is
79  * generated.
80  *
81  * If the MMR exists on ONLY 1 type of hub, no generic definition is
82  * generated:
83  *	#define UVnH_xxx	<uvn address>
84  *	union uvnh_xxx {
85  *		unsigned long       v;
86  *		struct uvh_int_cmpd_s {
87  *		} sn;
88  *	};
89  *
90  * (GEN Flags: mflags_opt= undefs=function UV234=UVXH)
91  */
92 
93 #define UV_MMR_ENABLE		(1UL << 63)
94 
95 #define UV1_HUB_PART_NUMBER	0x88a5
96 #define UV2_HUB_PART_NUMBER	0x8eb8
97 #define UV2_HUB_PART_NUMBER_X	0x1111
98 #define UV3_HUB_PART_NUMBER	0x9578
99 #define UV3_HUB_PART_NUMBER_X	0x4321
100 #define UV4_HUB_PART_NUMBER	0x99a1
101 
102 /* Error function to catch undefined references */
103 extern unsigned long uv_undefined(char *str);
104 
105 /* ========================================================================= */
106 /*                          UVH_BAU_DATA_BROADCAST                           */
107 /* ========================================================================= */
108 #define UVH_BAU_DATA_BROADCAST 0x61688UL
109 
110 #define UV1H_BAU_DATA_BROADCAST_32 0x440
111 #define UV2H_BAU_DATA_BROADCAST_32 0x440
112 #define UV3H_BAU_DATA_BROADCAST_32 0x440
113 #define UV4H_BAU_DATA_BROADCAST_32 0x360
114 #define UVH_BAU_DATA_BROADCAST_32 (					\
115 	is_uv1_hub() ? UV1H_BAU_DATA_BROADCAST_32 :			\
116 	is_uv2_hub() ? UV2H_BAU_DATA_BROADCAST_32 :			\
117 	is_uv3_hub() ? UV3H_BAU_DATA_BROADCAST_32 :			\
118 	/*is_uv4_hub*/ UV4H_BAU_DATA_BROADCAST_32)
119 
120 #define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT		0
121 #define UVH_BAU_DATA_BROADCAST_ENABLE_MASK		0x0000000000000001UL
122 
123 
124 union uvh_bau_data_broadcast_u {
125 	unsigned long	v;
126 	struct uvh_bau_data_broadcast_s {
127 		unsigned long	enable:1;			/* RW */
128 		unsigned long	rsvd_1_63:63;
129 	} s;
130 };
131 
132 /* ========================================================================= */
133 /*                           UVH_BAU_DATA_CONFIG                             */
134 /* ========================================================================= */
135 #define UVH_BAU_DATA_CONFIG 0x61680UL
136 
137 #define UV1H_BAU_DATA_CONFIG_32 0x438
138 #define UV2H_BAU_DATA_CONFIG_32 0x438
139 #define UV3H_BAU_DATA_CONFIG_32 0x438
140 #define UV4H_BAU_DATA_CONFIG_32 0x358
141 #define UVH_BAU_DATA_CONFIG_32 (					\
142 	is_uv1_hub() ? UV1H_BAU_DATA_CONFIG_32 :			\
143 	is_uv2_hub() ? UV2H_BAU_DATA_CONFIG_32 :			\
144 	is_uv3_hub() ? UV3H_BAU_DATA_CONFIG_32 :			\
145 	/*is_uv4_hub*/ UV4H_BAU_DATA_CONFIG_32)
146 
147 #define UVH_BAU_DATA_CONFIG_VECTOR_SHFT			0
148 #define UVH_BAU_DATA_CONFIG_DM_SHFT			8
149 #define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT		11
150 #define UVH_BAU_DATA_CONFIG_STATUS_SHFT			12
151 #define UVH_BAU_DATA_CONFIG_P_SHFT			13
152 #define UVH_BAU_DATA_CONFIG_T_SHFT			15
153 #define UVH_BAU_DATA_CONFIG_M_SHFT			16
154 #define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT		32
155 #define UVH_BAU_DATA_CONFIG_VECTOR_MASK			0x00000000000000ffUL
156 #define UVH_BAU_DATA_CONFIG_DM_MASK			0x0000000000000700UL
157 #define UVH_BAU_DATA_CONFIG_DESTMODE_MASK		0x0000000000000800UL
158 #define UVH_BAU_DATA_CONFIG_STATUS_MASK			0x0000000000001000UL
159 #define UVH_BAU_DATA_CONFIG_P_MASK			0x0000000000002000UL
160 #define UVH_BAU_DATA_CONFIG_T_MASK			0x0000000000008000UL
161 #define UVH_BAU_DATA_CONFIG_M_MASK			0x0000000000010000UL
162 #define UVH_BAU_DATA_CONFIG_APIC_ID_MASK		0xffffffff00000000UL
163 
164 
165 union uvh_bau_data_config_u {
166 	unsigned long	v;
167 	struct uvh_bau_data_config_s {
168 		unsigned long	vector_:8;			/* RW */
169 		unsigned long	dm:3;				/* RW */
170 		unsigned long	destmode:1;			/* RW */
171 		unsigned long	status:1;			/* RO */
172 		unsigned long	p:1;				/* RO */
173 		unsigned long	rsvd_14:1;
174 		unsigned long	t:1;				/* RO */
175 		unsigned long	m:1;				/* RW */
176 		unsigned long	rsvd_17_31:15;
177 		unsigned long	apic_id:32;			/* RW */
178 	} s;
179 };
180 
181 /* ========================================================================= */
182 /*                           UVH_EVENT_OCCURRED0                             */
183 /* ========================================================================= */
184 #define UVH_EVENT_OCCURRED0 0x70000UL
185 #define UVH_EVENT_OCCURRED0_32 0x5e8
186 
187 #define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT		0
188 #define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT		11
189 #define UVH_EVENT_OCCURRED0_LB_HCERR_MASK		0x0000000000000001UL
190 #define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK		0x0000000000000800UL
191 
192 #define UV1H_EVENT_OCCURRED0_GR0_HCERR_SHFT		1
193 #define UV1H_EVENT_OCCURRED0_GR1_HCERR_SHFT		2
194 #define UV1H_EVENT_OCCURRED0_LH_HCERR_SHFT		3
195 #define UV1H_EVENT_OCCURRED0_RH_HCERR_SHFT		4
196 #define UV1H_EVENT_OCCURRED0_XN_HCERR_SHFT		5
197 #define UV1H_EVENT_OCCURRED0_SI_HCERR_SHFT		6
198 #define UV1H_EVENT_OCCURRED0_LB_AOERR0_SHFT		7
199 #define UV1H_EVENT_OCCURRED0_GR0_AOERR0_SHFT		8
200 #define UV1H_EVENT_OCCURRED0_GR1_AOERR0_SHFT		9
201 #define UV1H_EVENT_OCCURRED0_LH_AOERR0_SHFT		10
202 #define UV1H_EVENT_OCCURRED0_XN_AOERR0_SHFT		12
203 #define UV1H_EVENT_OCCURRED0_SI_AOERR0_SHFT		13
204 #define UV1H_EVENT_OCCURRED0_LB_AOERR1_SHFT		14
205 #define UV1H_EVENT_OCCURRED0_GR0_AOERR1_SHFT		15
206 #define UV1H_EVENT_OCCURRED0_GR1_AOERR1_SHFT		16
207 #define UV1H_EVENT_OCCURRED0_LH_AOERR1_SHFT		17
208 #define UV1H_EVENT_OCCURRED0_RH_AOERR1_SHFT		18
209 #define UV1H_EVENT_OCCURRED0_XN_AOERR1_SHFT		19
210 #define UV1H_EVENT_OCCURRED0_SI_AOERR1_SHFT		20
211 #define UV1H_EVENT_OCCURRED0_RH_VPI_INT_SHFT		21
212 #define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT	22
213 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT		23
214 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT		24
215 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT		25
216 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT		26
217 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT		27
218 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT		28
219 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT		29
220 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT		30
221 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT		31
222 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT		32
223 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT		33
224 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT		34
225 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT		35
226 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT		36
227 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT		37
228 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT		38
229 #define UV1H_EVENT_OCCURRED0_L1_NMI_INT_SHFT		39
230 #define UV1H_EVENT_OCCURRED0_STOP_CLOCK_SHFT		40
231 #define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT		41
232 #define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT		42
233 #define UV1H_EVENT_OCCURRED0_LTC_INT_SHFT		43
234 #define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT	44
235 #define UV1H_EVENT_OCCURRED0_IPI_INT_SHFT		45
236 #define UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT		46
237 #define UV1H_EVENT_OCCURRED0_EXTIO_INT1_SHFT		47
238 #define UV1H_EVENT_OCCURRED0_EXTIO_INT2_SHFT		48
239 #define UV1H_EVENT_OCCURRED0_EXTIO_INT3_SHFT		49
240 #define UV1H_EVENT_OCCURRED0_PROFILE_INT_SHFT		50
241 #define UV1H_EVENT_OCCURRED0_RTC0_SHFT			51
242 #define UV1H_EVENT_OCCURRED0_RTC1_SHFT			52
243 #define UV1H_EVENT_OCCURRED0_RTC2_SHFT			53
244 #define UV1H_EVENT_OCCURRED0_RTC3_SHFT			54
245 #define UV1H_EVENT_OCCURRED0_BAU_DATA_SHFT		55
246 #define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT	56
247 #define UV1H_EVENT_OCCURRED0_GR0_HCERR_MASK		0x0000000000000002UL
248 #define UV1H_EVENT_OCCURRED0_GR1_HCERR_MASK		0x0000000000000004UL
249 #define UV1H_EVENT_OCCURRED0_LH_HCERR_MASK		0x0000000000000008UL
250 #define UV1H_EVENT_OCCURRED0_RH_HCERR_MASK		0x0000000000000010UL
251 #define UV1H_EVENT_OCCURRED0_XN_HCERR_MASK		0x0000000000000020UL
252 #define UV1H_EVENT_OCCURRED0_SI_HCERR_MASK		0x0000000000000040UL
253 #define UV1H_EVENT_OCCURRED0_LB_AOERR0_MASK		0x0000000000000080UL
254 #define UV1H_EVENT_OCCURRED0_GR0_AOERR0_MASK		0x0000000000000100UL
255 #define UV1H_EVENT_OCCURRED0_GR1_AOERR0_MASK		0x0000000000000200UL
256 #define UV1H_EVENT_OCCURRED0_LH_AOERR0_MASK		0x0000000000000400UL
257 #define UV1H_EVENT_OCCURRED0_XN_AOERR0_MASK		0x0000000000001000UL
258 #define UV1H_EVENT_OCCURRED0_SI_AOERR0_MASK		0x0000000000002000UL
259 #define UV1H_EVENT_OCCURRED0_LB_AOERR1_MASK		0x0000000000004000UL
260 #define UV1H_EVENT_OCCURRED0_GR0_AOERR1_MASK		0x0000000000008000UL
261 #define UV1H_EVENT_OCCURRED0_GR1_AOERR1_MASK		0x0000000000010000UL
262 #define UV1H_EVENT_OCCURRED0_LH_AOERR1_MASK		0x0000000000020000UL
263 #define UV1H_EVENT_OCCURRED0_RH_AOERR1_MASK		0x0000000000040000UL
264 #define UV1H_EVENT_OCCURRED0_XN_AOERR1_MASK		0x0000000000080000UL
265 #define UV1H_EVENT_OCCURRED0_SI_AOERR1_MASK		0x0000000000100000UL
266 #define UV1H_EVENT_OCCURRED0_RH_VPI_INT_MASK		0x0000000000200000UL
267 #define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK	0x0000000000400000UL
268 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK		0x0000000000800000UL
269 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK		0x0000000001000000UL
270 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK		0x0000000002000000UL
271 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK		0x0000000004000000UL
272 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK		0x0000000008000000UL
273 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK		0x0000000010000000UL
274 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK		0x0000000020000000UL
275 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK		0x0000000040000000UL
276 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK		0x0000000080000000UL
277 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK		0x0000000100000000UL
278 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK		0x0000000200000000UL
279 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK		0x0000000400000000UL
280 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK		0x0000000800000000UL
281 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK		0x0000001000000000UL
282 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK		0x0000002000000000UL
283 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK		0x0000004000000000UL
284 #define UV1H_EVENT_OCCURRED0_L1_NMI_INT_MASK		0x0000008000000000UL
285 #define UV1H_EVENT_OCCURRED0_STOP_CLOCK_MASK		0x0000010000000000UL
286 #define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_MASK		0x0000020000000000UL
287 #define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_MASK		0x0000040000000000UL
288 #define UV1H_EVENT_OCCURRED0_LTC_INT_MASK		0x0000080000000000UL
289 #define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK	0x0000100000000000UL
290 #define UV1H_EVENT_OCCURRED0_IPI_INT_MASK		0x0000200000000000UL
291 #define UV1H_EVENT_OCCURRED0_EXTIO_INT0_MASK		0x0000400000000000UL
292 #define UV1H_EVENT_OCCURRED0_EXTIO_INT1_MASK		0x0000800000000000UL
293 #define UV1H_EVENT_OCCURRED0_EXTIO_INT2_MASK		0x0001000000000000UL
294 #define UV1H_EVENT_OCCURRED0_EXTIO_INT3_MASK		0x0002000000000000UL
295 #define UV1H_EVENT_OCCURRED0_PROFILE_INT_MASK		0x0004000000000000UL
296 #define UV1H_EVENT_OCCURRED0_RTC0_MASK			0x0008000000000000UL
297 #define UV1H_EVENT_OCCURRED0_RTC1_MASK			0x0010000000000000UL
298 #define UV1H_EVENT_OCCURRED0_RTC2_MASK			0x0020000000000000UL
299 #define UV1H_EVENT_OCCURRED0_RTC3_MASK			0x0040000000000000UL
300 #define UV1H_EVENT_OCCURRED0_BAU_DATA_MASK		0x0080000000000000UL
301 #define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK	0x0100000000000000UL
302 
303 #define UVXH_EVENT_OCCURRED0_RH_HCERR_SHFT		2
304 #define UVXH_EVENT_OCCURRED0_LH0_HCERR_SHFT		3
305 #define UVXH_EVENT_OCCURRED0_LH1_HCERR_SHFT		4
306 #define UVXH_EVENT_OCCURRED0_GR0_HCERR_SHFT		5
307 #define UVXH_EVENT_OCCURRED0_GR1_HCERR_SHFT		6
308 #define UVXH_EVENT_OCCURRED0_NI0_HCERR_SHFT		7
309 #define UVXH_EVENT_OCCURRED0_NI1_HCERR_SHFT		8
310 #define UVXH_EVENT_OCCURRED0_LB_AOERR0_SHFT		9
311 #define UVXH_EVENT_OCCURRED0_LH0_AOERR0_SHFT		12
312 #define UVXH_EVENT_OCCURRED0_LH1_AOERR0_SHFT		13
313 #define UVXH_EVENT_OCCURRED0_GR0_AOERR0_SHFT		14
314 #define UVXH_EVENT_OCCURRED0_GR1_AOERR0_SHFT		15
315 #define UVXH_EVENT_OCCURRED0_XB_AOERR0_SHFT		16
316 #define UVXH_EVENT_OCCURRED0_RH_HCERR_MASK		0x0000000000000004UL
317 #define UVXH_EVENT_OCCURRED0_LH0_HCERR_MASK		0x0000000000000008UL
318 #define UVXH_EVENT_OCCURRED0_LH1_HCERR_MASK		0x0000000000000010UL
319 #define UVXH_EVENT_OCCURRED0_GR0_HCERR_MASK		0x0000000000000020UL
320 #define UVXH_EVENT_OCCURRED0_GR1_HCERR_MASK		0x0000000000000040UL
321 #define UVXH_EVENT_OCCURRED0_NI0_HCERR_MASK		0x0000000000000080UL
322 #define UVXH_EVENT_OCCURRED0_NI1_HCERR_MASK		0x0000000000000100UL
323 #define UVXH_EVENT_OCCURRED0_LB_AOERR0_MASK		0x0000000000000200UL
324 #define UVXH_EVENT_OCCURRED0_LH0_AOERR0_MASK		0x0000000000001000UL
325 #define UVXH_EVENT_OCCURRED0_LH1_AOERR0_MASK		0x0000000000002000UL
326 #define UVXH_EVENT_OCCURRED0_GR0_AOERR0_MASK		0x0000000000004000UL
327 #define UVXH_EVENT_OCCURRED0_GR1_AOERR0_MASK		0x0000000000008000UL
328 #define UVXH_EVENT_OCCURRED0_XB_AOERR0_MASK		0x0000000000010000UL
329 
330 #define UV2H_EVENT_OCCURRED0_QP_HCERR_SHFT		1
331 #define UV2H_EVENT_OCCURRED0_QP_AOERR0_SHFT		10
332 #define UV2H_EVENT_OCCURRED0_RT_AOERR0_SHFT		17
333 #define UV2H_EVENT_OCCURRED0_NI0_AOERR0_SHFT		18
334 #define UV2H_EVENT_OCCURRED0_NI1_AOERR0_SHFT		19
335 #define UV2H_EVENT_OCCURRED0_LB_AOERR1_SHFT		20
336 #define UV2H_EVENT_OCCURRED0_QP_AOERR1_SHFT		21
337 #define UV2H_EVENT_OCCURRED0_RH_AOERR1_SHFT		22
338 #define UV2H_EVENT_OCCURRED0_LH0_AOERR1_SHFT		23
339 #define UV2H_EVENT_OCCURRED0_LH1_AOERR1_SHFT		24
340 #define UV2H_EVENT_OCCURRED0_GR0_AOERR1_SHFT		25
341 #define UV2H_EVENT_OCCURRED0_GR1_AOERR1_SHFT		26
342 #define UV2H_EVENT_OCCURRED0_XB_AOERR1_SHFT		27
343 #define UV2H_EVENT_OCCURRED0_RT_AOERR1_SHFT		28
344 #define UV2H_EVENT_OCCURRED0_NI0_AOERR1_SHFT		29
345 #define UV2H_EVENT_OCCURRED0_NI1_AOERR1_SHFT		30
346 #define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT	31
347 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT		32
348 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT		33
349 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT		34
350 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT		35
351 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT		36
352 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT		37
353 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT		38
354 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT		39
355 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT		40
356 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT		41
357 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT		42
358 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT		43
359 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT		44
360 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT		45
361 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT		46
362 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT		47
363 #define UV2H_EVENT_OCCURRED0_L1_NMI_INT_SHFT		48
364 #define UV2H_EVENT_OCCURRED0_STOP_CLOCK_SHFT		49
365 #define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT		50
366 #define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT		51
367 #define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT	52
368 #define UV2H_EVENT_OCCURRED0_IPI_INT_SHFT		53
369 #define UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT		54
370 #define UV2H_EVENT_OCCURRED0_EXTIO_INT1_SHFT		55
371 #define UV2H_EVENT_OCCURRED0_EXTIO_INT2_SHFT		56
372 #define UV2H_EVENT_OCCURRED0_EXTIO_INT3_SHFT		57
373 #define UV2H_EVENT_OCCURRED0_PROFILE_INT_SHFT		58
374 #define UV2H_EVENT_OCCURRED0_QP_HCERR_MASK		0x0000000000000002UL
375 #define UV2H_EVENT_OCCURRED0_QP_AOERR0_MASK		0x0000000000000400UL
376 #define UV2H_EVENT_OCCURRED0_RT_AOERR0_MASK		0x0000000000020000UL
377 #define UV2H_EVENT_OCCURRED0_NI0_AOERR0_MASK		0x0000000000040000UL
378 #define UV2H_EVENT_OCCURRED0_NI1_AOERR0_MASK		0x0000000000080000UL
379 #define UV2H_EVENT_OCCURRED0_LB_AOERR1_MASK		0x0000000000100000UL
380 #define UV2H_EVENT_OCCURRED0_QP_AOERR1_MASK		0x0000000000200000UL
381 #define UV2H_EVENT_OCCURRED0_RH_AOERR1_MASK		0x0000000000400000UL
382 #define UV2H_EVENT_OCCURRED0_LH0_AOERR1_MASK		0x0000000000800000UL
383 #define UV2H_EVENT_OCCURRED0_LH1_AOERR1_MASK		0x0000000001000000UL
384 #define UV2H_EVENT_OCCURRED0_GR0_AOERR1_MASK		0x0000000002000000UL
385 #define UV2H_EVENT_OCCURRED0_GR1_AOERR1_MASK		0x0000000004000000UL
386 #define UV2H_EVENT_OCCURRED0_XB_AOERR1_MASK		0x0000000008000000UL
387 #define UV2H_EVENT_OCCURRED0_RT_AOERR1_MASK		0x0000000010000000UL
388 #define UV2H_EVENT_OCCURRED0_NI0_AOERR1_MASK		0x0000000020000000UL
389 #define UV2H_EVENT_OCCURRED0_NI1_AOERR1_MASK		0x0000000040000000UL
390 #define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK	0x0000000080000000UL
391 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK		0x0000000100000000UL
392 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK		0x0000000200000000UL
393 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK		0x0000000400000000UL
394 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK		0x0000000800000000UL
395 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK		0x0000001000000000UL
396 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK		0x0000002000000000UL
397 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK		0x0000004000000000UL
398 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK		0x0000008000000000UL
399 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK		0x0000010000000000UL
400 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK		0x0000020000000000UL
401 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK		0x0000040000000000UL
402 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK		0x0000080000000000UL
403 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK		0x0000100000000000UL
404 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK		0x0000200000000000UL
405 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK		0x0000400000000000UL
406 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK		0x0000800000000000UL
407 #define UV2H_EVENT_OCCURRED0_L1_NMI_INT_MASK		0x0001000000000000UL
408 #define UV2H_EVENT_OCCURRED0_STOP_CLOCK_MASK		0x0002000000000000UL
409 #define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_MASK		0x0004000000000000UL
410 #define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_MASK		0x0008000000000000UL
411 #define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK	0x0010000000000000UL
412 #define UV2H_EVENT_OCCURRED0_IPI_INT_MASK		0x0020000000000000UL
413 #define UV2H_EVENT_OCCURRED0_EXTIO_INT0_MASK		0x0040000000000000UL
414 #define UV2H_EVENT_OCCURRED0_EXTIO_INT1_MASK		0x0080000000000000UL
415 #define UV2H_EVENT_OCCURRED0_EXTIO_INT2_MASK		0x0100000000000000UL
416 #define UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK		0x0200000000000000UL
417 #define UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK		0x0400000000000000UL
418 
419 #define UV3H_EVENT_OCCURRED0_QP_HCERR_SHFT		1
420 #define UV3H_EVENT_OCCURRED0_QP_AOERR0_SHFT		10
421 #define UV3H_EVENT_OCCURRED0_RT_AOERR0_SHFT		17
422 #define UV3H_EVENT_OCCURRED0_NI0_AOERR0_SHFT		18
423 #define UV3H_EVENT_OCCURRED0_NI1_AOERR0_SHFT		19
424 #define UV3H_EVENT_OCCURRED0_LB_AOERR1_SHFT		20
425 #define UV3H_EVENT_OCCURRED0_QP_AOERR1_SHFT		21
426 #define UV3H_EVENT_OCCURRED0_RH_AOERR1_SHFT		22
427 #define UV3H_EVENT_OCCURRED0_LH0_AOERR1_SHFT		23
428 #define UV3H_EVENT_OCCURRED0_LH1_AOERR1_SHFT		24
429 #define UV3H_EVENT_OCCURRED0_GR0_AOERR1_SHFT		25
430 #define UV3H_EVENT_OCCURRED0_GR1_AOERR1_SHFT		26
431 #define UV3H_EVENT_OCCURRED0_XB_AOERR1_SHFT		27
432 #define UV3H_EVENT_OCCURRED0_RT_AOERR1_SHFT		28
433 #define UV3H_EVENT_OCCURRED0_NI0_AOERR1_SHFT		29
434 #define UV3H_EVENT_OCCURRED0_NI1_AOERR1_SHFT		30
435 #define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT	31
436 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT		32
437 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT		33
438 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT		34
439 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT		35
440 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT		36
441 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT		37
442 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT		38
443 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT		39
444 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT		40
445 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT		41
446 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT		42
447 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT		43
448 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT		44
449 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT		45
450 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT		46
451 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT		47
452 #define UV3H_EVENT_OCCURRED0_L1_NMI_INT_SHFT		48
453 #define UV3H_EVENT_OCCURRED0_STOP_CLOCK_SHFT		49
454 #define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT		50
455 #define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT		51
456 #define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT	52
457 #define UV3H_EVENT_OCCURRED0_IPI_INT_SHFT		53
458 #define UV3H_EVENT_OCCURRED0_EXTIO_INT0_SHFT		54
459 #define UV3H_EVENT_OCCURRED0_EXTIO_INT1_SHFT		55
460 #define UV3H_EVENT_OCCURRED0_EXTIO_INT2_SHFT		56
461 #define UV3H_EVENT_OCCURRED0_EXTIO_INT3_SHFT		57
462 #define UV3H_EVENT_OCCURRED0_PROFILE_INT_SHFT		58
463 #define UV3H_EVENT_OCCURRED0_QP_HCERR_MASK		0x0000000000000002UL
464 #define UV3H_EVENT_OCCURRED0_QP_AOERR0_MASK		0x0000000000000400UL
465 #define UV3H_EVENT_OCCURRED0_RT_AOERR0_MASK		0x0000000000020000UL
466 #define UV3H_EVENT_OCCURRED0_NI0_AOERR0_MASK		0x0000000000040000UL
467 #define UV3H_EVENT_OCCURRED0_NI1_AOERR0_MASK		0x0000000000080000UL
468 #define UV3H_EVENT_OCCURRED0_LB_AOERR1_MASK		0x0000000000100000UL
469 #define UV3H_EVENT_OCCURRED0_QP_AOERR1_MASK		0x0000000000200000UL
470 #define UV3H_EVENT_OCCURRED0_RH_AOERR1_MASK		0x0000000000400000UL
471 #define UV3H_EVENT_OCCURRED0_LH0_AOERR1_MASK		0x0000000000800000UL
472 #define UV3H_EVENT_OCCURRED0_LH1_AOERR1_MASK		0x0000000001000000UL
473 #define UV3H_EVENT_OCCURRED0_GR0_AOERR1_MASK		0x0000000002000000UL
474 #define UV3H_EVENT_OCCURRED0_GR1_AOERR1_MASK		0x0000000004000000UL
475 #define UV3H_EVENT_OCCURRED0_XB_AOERR1_MASK		0x0000000008000000UL
476 #define UV3H_EVENT_OCCURRED0_RT_AOERR1_MASK		0x0000000010000000UL
477 #define UV3H_EVENT_OCCURRED0_NI0_AOERR1_MASK		0x0000000020000000UL
478 #define UV3H_EVENT_OCCURRED0_NI1_AOERR1_MASK		0x0000000040000000UL
479 #define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK	0x0000000080000000UL
480 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK		0x0000000100000000UL
481 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK		0x0000000200000000UL
482 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK		0x0000000400000000UL
483 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK		0x0000000800000000UL
484 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK		0x0000001000000000UL
485 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK		0x0000002000000000UL
486 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK		0x0000004000000000UL
487 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK		0x0000008000000000UL
488 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK		0x0000010000000000UL
489 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK		0x0000020000000000UL
490 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK		0x0000040000000000UL
491 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK		0x0000080000000000UL
492 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK		0x0000100000000000UL
493 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK		0x0000200000000000UL
494 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK		0x0000400000000000UL
495 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK		0x0000800000000000UL
496 #define UV3H_EVENT_OCCURRED0_L1_NMI_INT_MASK		0x0001000000000000UL
497 #define UV3H_EVENT_OCCURRED0_STOP_CLOCK_MASK		0x0002000000000000UL
498 #define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_MASK		0x0004000000000000UL
499 #define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_MASK		0x0008000000000000UL
500 #define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK	0x0010000000000000UL
501 #define UV3H_EVENT_OCCURRED0_IPI_INT_MASK		0x0020000000000000UL
502 #define UV3H_EVENT_OCCURRED0_EXTIO_INT0_MASK		0x0040000000000000UL
503 #define UV3H_EVENT_OCCURRED0_EXTIO_INT1_MASK		0x0080000000000000UL
504 #define UV3H_EVENT_OCCURRED0_EXTIO_INT2_MASK		0x0100000000000000UL
505 #define UV3H_EVENT_OCCURRED0_EXTIO_INT3_MASK		0x0200000000000000UL
506 #define UV3H_EVENT_OCCURRED0_PROFILE_INT_MASK		0x0400000000000000UL
507 
508 #define UV4H_EVENT_OCCURRED0_KT_HCERR_SHFT		1
509 #define UV4H_EVENT_OCCURRED0_KT_AOERR0_SHFT		10
510 #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR0_SHFT		17
511 #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR0_SHFT		18
512 #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR0_SHFT		19
513 #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR0_SHFT		20
514 #define UV4H_EVENT_OCCURRED0_NI0_AOERR0_SHFT		21
515 #define UV4H_EVENT_OCCURRED0_NI1_AOERR0_SHFT		22
516 #define UV4H_EVENT_OCCURRED0_LB_AOERR1_SHFT		23
517 #define UV4H_EVENT_OCCURRED0_KT_AOERR1_SHFT		24
518 #define UV4H_EVENT_OCCURRED0_RH_AOERR1_SHFT		25
519 #define UV4H_EVENT_OCCURRED0_LH0_AOERR1_SHFT		26
520 #define UV4H_EVENT_OCCURRED0_LH1_AOERR1_SHFT		27
521 #define UV4H_EVENT_OCCURRED0_GR0_AOERR1_SHFT		28
522 #define UV4H_EVENT_OCCURRED0_GR1_AOERR1_SHFT		29
523 #define UV4H_EVENT_OCCURRED0_XB_AOERR1_SHFT		30
524 #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR1_SHFT		31
525 #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR1_SHFT		32
526 #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR1_SHFT		33
527 #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR1_SHFT		34
528 #define UV4H_EVENT_OCCURRED0_NI0_AOERR1_SHFT		35
529 #define UV4H_EVENT_OCCURRED0_NI1_AOERR1_SHFT		36
530 #define UV4H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT	37
531 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT		38
532 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT		39
533 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT		40
534 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT		41
535 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT		42
536 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT		43
537 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT		44
538 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT		45
539 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT		46
540 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT		47
541 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT		48
542 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT		49
543 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT		50
544 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT		51
545 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT		52
546 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT		53
547 #define UV4H_EVENT_OCCURRED0_L1_NMI_INT_SHFT		54
548 #define UV4H_EVENT_OCCURRED0_STOP_CLOCK_SHFT		55
549 #define UV4H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT		56
550 #define UV4H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT		57
551 #define UV4H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT	58
552 #define UV4H_EVENT_OCCURRED0_IPI_INT_SHFT		59
553 #define UV4H_EVENT_OCCURRED0_EXTIO_INT0_SHFT		60
554 #define UV4H_EVENT_OCCURRED0_EXTIO_INT1_SHFT		61
555 #define UV4H_EVENT_OCCURRED0_EXTIO_INT2_SHFT		62
556 #define UV4H_EVENT_OCCURRED0_EXTIO_INT3_SHFT		63
557 #define UV4H_EVENT_OCCURRED0_KT_HCERR_MASK		0x0000000000000002UL
558 #define UV4H_EVENT_OCCURRED0_KT_AOERR0_MASK		0x0000000000000400UL
559 #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR0_MASK		0x0000000000020000UL
560 #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR0_MASK		0x0000000000040000UL
561 #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR0_MASK		0x0000000000080000UL
562 #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR0_MASK		0x0000000000100000UL
563 #define UV4H_EVENT_OCCURRED0_NI0_AOERR0_MASK		0x0000000000200000UL
564 #define UV4H_EVENT_OCCURRED0_NI1_AOERR0_MASK		0x0000000000400000UL
565 #define UV4H_EVENT_OCCURRED0_LB_AOERR1_MASK		0x0000000000800000UL
566 #define UV4H_EVENT_OCCURRED0_KT_AOERR1_MASK		0x0000000001000000UL
567 #define UV4H_EVENT_OCCURRED0_RH_AOERR1_MASK		0x0000000002000000UL
568 #define UV4H_EVENT_OCCURRED0_LH0_AOERR1_MASK		0x0000000004000000UL
569 #define UV4H_EVENT_OCCURRED0_LH1_AOERR1_MASK		0x0000000008000000UL
570 #define UV4H_EVENT_OCCURRED0_GR0_AOERR1_MASK		0x0000000010000000UL
571 #define UV4H_EVENT_OCCURRED0_GR1_AOERR1_MASK		0x0000000020000000UL
572 #define UV4H_EVENT_OCCURRED0_XB_AOERR1_MASK		0x0000000040000000UL
573 #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR1_MASK		0x0000000080000000UL
574 #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR1_MASK		0x0000000100000000UL
575 #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR1_MASK		0x0000000200000000UL
576 #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR1_MASK		0x0000000400000000UL
577 #define UV4H_EVENT_OCCURRED0_NI0_AOERR1_MASK		0x0000000800000000UL
578 #define UV4H_EVENT_OCCURRED0_NI1_AOERR1_MASK		0x0000001000000000UL
579 #define UV4H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK	0x0000002000000000UL
580 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK		0x0000004000000000UL
581 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK		0x0000008000000000UL
582 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK		0x0000010000000000UL
583 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK		0x0000020000000000UL
584 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK		0x0000040000000000UL
585 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK		0x0000080000000000UL
586 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK		0x0000100000000000UL
587 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK		0x0000200000000000UL
588 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK		0x0000400000000000UL
589 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK		0x0000800000000000UL
590 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK		0x0001000000000000UL
591 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK		0x0002000000000000UL
592 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK		0x0004000000000000UL
593 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK		0x0008000000000000UL
594 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK		0x0010000000000000UL
595 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK		0x0020000000000000UL
596 #define UV4H_EVENT_OCCURRED0_L1_NMI_INT_MASK		0x0040000000000000UL
597 #define UV4H_EVENT_OCCURRED0_STOP_CLOCK_MASK		0x0080000000000000UL
598 #define UV4H_EVENT_OCCURRED0_ASIC_TO_L1_MASK		0x0100000000000000UL
599 #define UV4H_EVENT_OCCURRED0_L1_TO_ASIC_MASK		0x0200000000000000UL
600 #define UV4H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK	0x0400000000000000UL
601 #define UV4H_EVENT_OCCURRED0_IPI_INT_MASK		0x0800000000000000UL
602 #define UV4H_EVENT_OCCURRED0_EXTIO_INT0_MASK		0x1000000000000000UL
603 #define UV4H_EVENT_OCCURRED0_EXTIO_INT1_MASK		0x2000000000000000UL
604 #define UV4H_EVENT_OCCURRED0_EXTIO_INT2_MASK		0x4000000000000000UL
605 #define UV4H_EVENT_OCCURRED0_EXTIO_INT3_MASK		0x8000000000000000UL
606 
607 #define UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT (				\
608 	is_uv1_hub() ? UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT :		\
609 	is_uv2_hub() ? UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT :		\
610 	is_uv3_hub() ? UV3H_EVENT_OCCURRED0_EXTIO_INT0_SHFT :		\
611 	/*is_uv4_hub*/ UV4H_EVENT_OCCURRED0_EXTIO_INT0_SHFT)
612 
613 union uvh_event_occurred0_u {
614 	unsigned long	v;
615 	struct uvh_event_occurred0_s {
616 		unsigned long	lb_hcerr:1;			/* RW, W1C */
617 		unsigned long	rsvd_1_10:10;
618 		unsigned long	rh_aoerr0:1;			/* RW, W1C */
619 		unsigned long	rsvd_12_63:52;
620 	} s;
621 	struct uvxh_event_occurred0_s {
622 		unsigned long	lb_hcerr:1;			/* RW */
623 		unsigned long	rsvd_1:1;
624 		unsigned long	rh_hcerr:1;			/* RW */
625 		unsigned long	lh0_hcerr:1;			/* RW */
626 		unsigned long	lh1_hcerr:1;			/* RW */
627 		unsigned long	gr0_hcerr:1;			/* RW */
628 		unsigned long	gr1_hcerr:1;			/* RW */
629 		unsigned long	ni0_hcerr:1;			/* RW */
630 		unsigned long	ni1_hcerr:1;			/* RW */
631 		unsigned long	lb_aoerr0:1;			/* RW */
632 		unsigned long	rsvd_10:1;
633 		unsigned long	rh_aoerr0:1;			/* RW */
634 		unsigned long	lh0_aoerr0:1;			/* RW */
635 		unsigned long	lh1_aoerr0:1;			/* RW */
636 		unsigned long	gr0_aoerr0:1;			/* RW */
637 		unsigned long	gr1_aoerr0:1;			/* RW */
638 		unsigned long	xb_aoerr0:1;			/* RW */
639 		unsigned long	rsvd_17_63:47;
640 	} sx;
641 	struct uv4h_event_occurred0_s {
642 		unsigned long	lb_hcerr:1;			/* RW */
643 		unsigned long	kt_hcerr:1;			/* RW */
644 		unsigned long	rh_hcerr:1;			/* RW */
645 		unsigned long	lh0_hcerr:1;			/* RW */
646 		unsigned long	lh1_hcerr:1;			/* RW */
647 		unsigned long	gr0_hcerr:1;			/* RW */
648 		unsigned long	gr1_hcerr:1;			/* RW */
649 		unsigned long	ni0_hcerr:1;			/* RW */
650 		unsigned long	ni1_hcerr:1;			/* RW */
651 		unsigned long	lb_aoerr0:1;			/* RW */
652 		unsigned long	kt_aoerr0:1;			/* RW */
653 		unsigned long	rh_aoerr0:1;			/* RW */
654 		unsigned long	lh0_aoerr0:1;			/* RW */
655 		unsigned long	lh1_aoerr0:1;			/* RW */
656 		unsigned long	gr0_aoerr0:1;			/* RW */
657 		unsigned long	gr1_aoerr0:1;			/* RW */
658 		unsigned long	xb_aoerr0:1;			/* RW */
659 		unsigned long	rtq0_aoerr0:1;			/* RW */
660 		unsigned long	rtq1_aoerr0:1;			/* RW */
661 		unsigned long	rtq2_aoerr0:1;			/* RW */
662 		unsigned long	rtq3_aoerr0:1;			/* RW */
663 		unsigned long	ni0_aoerr0:1;			/* RW */
664 		unsigned long	ni1_aoerr0:1;			/* RW */
665 		unsigned long	lb_aoerr1:1;			/* RW */
666 		unsigned long	kt_aoerr1:1;			/* RW */
667 		unsigned long	rh_aoerr1:1;			/* RW */
668 		unsigned long	lh0_aoerr1:1;			/* RW */
669 		unsigned long	lh1_aoerr1:1;			/* RW */
670 		unsigned long	gr0_aoerr1:1;			/* RW */
671 		unsigned long	gr1_aoerr1:1;			/* RW */
672 		unsigned long	xb_aoerr1:1;			/* RW */
673 		unsigned long	rtq0_aoerr1:1;			/* RW */
674 		unsigned long	rtq1_aoerr1:1;			/* RW */
675 		unsigned long	rtq2_aoerr1:1;			/* RW */
676 		unsigned long	rtq3_aoerr1:1;			/* RW */
677 		unsigned long	ni0_aoerr1:1;			/* RW */
678 		unsigned long	ni1_aoerr1:1;			/* RW */
679 		unsigned long	system_shutdown_int:1;		/* RW */
680 		unsigned long	lb_irq_int_0:1;			/* RW */
681 		unsigned long	lb_irq_int_1:1;			/* RW */
682 		unsigned long	lb_irq_int_2:1;			/* RW */
683 		unsigned long	lb_irq_int_3:1;			/* RW */
684 		unsigned long	lb_irq_int_4:1;			/* RW */
685 		unsigned long	lb_irq_int_5:1;			/* RW */
686 		unsigned long	lb_irq_int_6:1;			/* RW */
687 		unsigned long	lb_irq_int_7:1;			/* RW */
688 		unsigned long	lb_irq_int_8:1;			/* RW */
689 		unsigned long	lb_irq_int_9:1;			/* RW */
690 		unsigned long	lb_irq_int_10:1;		/* RW */
691 		unsigned long	lb_irq_int_11:1;		/* RW */
692 		unsigned long	lb_irq_int_12:1;		/* RW */
693 		unsigned long	lb_irq_int_13:1;		/* RW */
694 		unsigned long	lb_irq_int_14:1;		/* RW */
695 		unsigned long	lb_irq_int_15:1;		/* RW */
696 		unsigned long	l1_nmi_int:1;			/* RW */
697 		unsigned long	stop_clock:1;			/* RW */
698 		unsigned long	asic_to_l1:1;			/* RW */
699 		unsigned long	l1_to_asic:1;			/* RW */
700 		unsigned long	la_seq_trigger:1;		/* RW */
701 		unsigned long	ipi_int:1;			/* RW */
702 		unsigned long	extio_int0:1;			/* RW */
703 		unsigned long	extio_int1:1;			/* RW */
704 		unsigned long	extio_int2:1;			/* RW */
705 		unsigned long	extio_int3:1;			/* RW */
706 	} s4;
707 };
708 
709 /* ========================================================================= */
710 /*                        UVH_EVENT_OCCURRED0_ALIAS                          */
711 /* ========================================================================= */
712 #define UVH_EVENT_OCCURRED0_ALIAS 0x70008UL
713 #define UVH_EVENT_OCCURRED0_ALIAS_32 0x5f0
714 
715 
716 /* ========================================================================= */
717 /*                         UVH_EXTIO_INT0_BROADCAST                          */
718 /* ========================================================================= */
719 #define UVH_EXTIO_INT0_BROADCAST 0x61448UL
720 
721 #define UV1H_EXTIO_INT0_BROADCAST_32 0x3f0
722 #define UV2H_EXTIO_INT0_BROADCAST_32 0x3f0
723 #define UV3H_EXTIO_INT0_BROADCAST_32 0x3f0
724 #define UV4H_EXTIO_INT0_BROADCAST_32 0x310
725 #define UVH_EXTIO_INT0_BROADCAST_32 (					\
726 	is_uv1_hub() ? UV1H_EXTIO_INT0_BROADCAST_32 :			\
727 	is_uv2_hub() ? UV2H_EXTIO_INT0_BROADCAST_32 :			\
728 	is_uv3_hub() ? UV3H_EXTIO_INT0_BROADCAST_32 :			\
729 	/*is_uv4_hub*/ UV4H_EXTIO_INT0_BROADCAST_32)
730 
731 #define UVH_EXTIO_INT0_BROADCAST_ENABLE_SHFT		0
732 #define UVH_EXTIO_INT0_BROADCAST_ENABLE_MASK		0x0000000000000001UL
733 
734 
735 union uvh_extio_int0_broadcast_u {
736 	unsigned long	v;
737 	struct uvh_extio_int0_broadcast_s {
738 		unsigned long	enable:1;			/* RW */
739 		unsigned long	rsvd_1_63:63;
740 	} s;
741 };
742 
743 /* ========================================================================= */
744 /*                         UVH_GR0_TLB_INT0_CONFIG                           */
745 /* ========================================================================= */
746 #define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL
747 
748 #define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT		0
749 #define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT			8
750 #define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT		11
751 #define UVH_GR0_TLB_INT0_CONFIG_STATUS_SHFT		12
752 #define UVH_GR0_TLB_INT0_CONFIG_P_SHFT			13
753 #define UVH_GR0_TLB_INT0_CONFIG_T_SHFT			15
754 #define UVH_GR0_TLB_INT0_CONFIG_M_SHFT			16
755 #define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT		32
756 #define UVH_GR0_TLB_INT0_CONFIG_VECTOR_MASK		0x00000000000000ffUL
757 #define UVH_GR0_TLB_INT0_CONFIG_DM_MASK			0x0000000000000700UL
758 #define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK		0x0000000000000800UL
759 #define UVH_GR0_TLB_INT0_CONFIG_STATUS_MASK		0x0000000000001000UL
760 #define UVH_GR0_TLB_INT0_CONFIG_P_MASK			0x0000000000002000UL
761 #define UVH_GR0_TLB_INT0_CONFIG_T_MASK			0x0000000000008000UL
762 #define UVH_GR0_TLB_INT0_CONFIG_M_MASK			0x0000000000010000UL
763 #define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK		0xffffffff00000000UL
764 
765 
766 union uvh_gr0_tlb_int0_config_u {
767 	unsigned long	v;
768 	struct uvh_gr0_tlb_int0_config_s {
769 		unsigned long	vector_:8;			/* RW */
770 		unsigned long	dm:3;				/* RW */
771 		unsigned long	destmode:1;			/* RW */
772 		unsigned long	status:1;			/* RO */
773 		unsigned long	p:1;				/* RO */
774 		unsigned long	rsvd_14:1;
775 		unsigned long	t:1;				/* RO */
776 		unsigned long	m:1;				/* RW */
777 		unsigned long	rsvd_17_31:15;
778 		unsigned long	apic_id:32;			/* RW */
779 	} s;
780 };
781 
782 /* ========================================================================= */
783 /*                         UVH_GR0_TLB_INT1_CONFIG                           */
784 /* ========================================================================= */
785 #define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL
786 
787 #define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT		0
788 #define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT			8
789 #define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT		11
790 #define UVH_GR0_TLB_INT1_CONFIG_STATUS_SHFT		12
791 #define UVH_GR0_TLB_INT1_CONFIG_P_SHFT			13
792 #define UVH_GR0_TLB_INT1_CONFIG_T_SHFT			15
793 #define UVH_GR0_TLB_INT1_CONFIG_M_SHFT			16
794 #define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT		32
795 #define UVH_GR0_TLB_INT1_CONFIG_VECTOR_MASK		0x00000000000000ffUL
796 #define UVH_GR0_TLB_INT1_CONFIG_DM_MASK			0x0000000000000700UL
797 #define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK		0x0000000000000800UL
798 #define UVH_GR0_TLB_INT1_CONFIG_STATUS_MASK		0x0000000000001000UL
799 #define UVH_GR0_TLB_INT1_CONFIG_P_MASK			0x0000000000002000UL
800 #define UVH_GR0_TLB_INT1_CONFIG_T_MASK			0x0000000000008000UL
801 #define UVH_GR0_TLB_INT1_CONFIG_M_MASK			0x0000000000010000UL
802 #define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK		0xffffffff00000000UL
803 
804 
805 union uvh_gr0_tlb_int1_config_u {
806 	unsigned long	v;
807 	struct uvh_gr0_tlb_int1_config_s {
808 		unsigned long	vector_:8;			/* RW */
809 		unsigned long	dm:3;				/* RW */
810 		unsigned long	destmode:1;			/* RW */
811 		unsigned long	status:1;			/* RO */
812 		unsigned long	p:1;				/* RO */
813 		unsigned long	rsvd_14:1;
814 		unsigned long	t:1;				/* RO */
815 		unsigned long	m:1;				/* RW */
816 		unsigned long	rsvd_17_31:15;
817 		unsigned long	apic_id:32;			/* RW */
818 	} s;
819 };
820 
821 /* ========================================================================= */
822 /*                         UVH_GR0_TLB_MMR_CONTROL                           */
823 /* ========================================================================= */
824 #define UV1H_GR0_TLB_MMR_CONTROL 0x401080UL
825 #define UV2H_GR0_TLB_MMR_CONTROL 0xc01080UL
826 #define UV3H_GR0_TLB_MMR_CONTROL 0xc01080UL
827 #define UV4H_GR0_TLB_MMR_CONTROL 0x601080UL
828 #define UVH_GR0_TLB_MMR_CONTROL (					\
829 	is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL :			\
830 	is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL :			\
831 	is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL :			\
832 	/*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL)
833 
834 #define UVH_GR0_TLB_MMR_CONTROL_INDEX_SHFT		0
835 #define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
836 #define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
837 #define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
838 #define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT		31
839 #define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
840 #define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
841 #define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
842 #define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL
843 
844 #define UV1H_GR0_TLB_MMR_CONTROL_INDEX_SHFT		0
845 #define UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT		12
846 #define UV1H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
847 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
848 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
849 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT		31
850 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT	48
851 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT	52
852 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_SHFT	54
853 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_SHFT	56
854 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_SHFT	60
855 #define UV1H_GR0_TLB_MMR_CONTROL_INDEX_MASK		0x0000000000000fffUL
856 #define UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK		0x0000000000003000UL
857 #define UV1H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
858 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
859 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
860 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL
861 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK	0x0001000000000000UL
862 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK	0x0010000000000000UL
863 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_MASK	0x0040000000000000UL
864 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK	0x0100000000000000UL
865 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK	0x1000000000000000UL
866 
867 #define UVXH_GR0_TLB_MMR_CONTROL_INDEX_SHFT		0
868 #define UVXH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
869 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
870 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
871 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT		31
872 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT	32
873 #define UVXH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
874 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
875 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
876 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL
877 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK	0x0000000100000000UL
878 
879 #define UV2H_GR0_TLB_MMR_CONTROL_INDEX_SHFT		0
880 #define UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT		12
881 #define UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
882 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
883 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
884 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT		31
885 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT	32
886 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT	48
887 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT	52
888 #define UV2H_GR0_TLB_MMR_CONTROL_INDEX_MASK		0x0000000000000fffUL
889 #define UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK		0x0000000000003000UL
890 #define UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
891 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
892 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
893 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL
894 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK	0x0000000100000000UL
895 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK	0x0001000000000000UL
896 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK	0x0010000000000000UL
897 
898 #define UV3H_GR0_TLB_MMR_CONTROL_INDEX_SHFT		0
899 #define UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT		12
900 #define UV3H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
901 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
902 #define UV3H_GR0_TLB_MMR_CONTROL_ECC_SEL_SHFT		21
903 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
904 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT		31
905 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT	32
906 #define UV3H_GR0_TLB_MMR_CONTROL_INDEX_MASK		0x0000000000000fffUL
907 #define UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK		0x0000000000003000UL
908 #define UV3H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
909 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
910 #define UV3H_GR0_TLB_MMR_CONTROL_ECC_SEL_MASK		0x0000000000200000UL
911 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
912 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL
913 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK	0x0000000100000000UL
914 
915 #define UV4H_GR0_TLB_MMR_CONTROL_INDEX_SHFT		0
916 #define UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT		13
917 #define UV4H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
918 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
919 #define UV4H_GR0_TLB_MMR_CONTROL_ECC_SEL_SHFT		21
920 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
921 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT		31
922 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT	32
923 #define UV4H_GR0_TLB_MMR_CONTROL_PAGE_SIZE_SHFT		59
924 #define UV4H_GR0_TLB_MMR_CONTROL_INDEX_MASK		0x0000000000001fffUL
925 #define UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK		0x0000000000006000UL
926 #define UV4H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
927 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
928 #define UV4H_GR0_TLB_MMR_CONTROL_ECC_SEL_MASK		0x0000000000200000UL
929 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
930 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL
931 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK	0x0000000100000000UL
932 #define UV4H_GR0_TLB_MMR_CONTROL_PAGE_SIZE_MASK		0xf800000000000000UL
933 
934 #define UVH_GR0_TLB_MMR_CONTROL_INDEX_MASK (				\
935 	is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL_INDEX_MASK :		\
936 	is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL_INDEX_MASK :		\
937 	is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL_INDEX_MASK :		\
938 	/*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL_INDEX_MASK)
939 #define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK (				\
940 	is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK :		\
941 	is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK :		\
942 	is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK :		\
943 	/*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK)
944 #define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT (				\
945 	is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT :		\
946 	is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT :		\
947 	is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT :		\
948 	/*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT)
949 
950 union uvh_gr0_tlb_mmr_control_u {
951 	unsigned long	v;
952 	struct uvh_gr0_tlb_mmr_control_s {
953 		unsigned long	rsvd_0_15:16;
954 		unsigned long	auto_valid_en:1;		/* RW */
955 		unsigned long	rsvd_17_19:3;
956 		unsigned long	mmr_hash_index_en:1;		/* RW */
957 		unsigned long	rsvd_21_29:9;
958 		unsigned long	mmr_write:1;			/* WP */
959 		unsigned long	mmr_read:1;			/* WP */
960 		unsigned long	rsvd_32_48:17;
961 		unsigned long	rsvd_49_51:3;
962 		unsigned long	rsvd_52_63:12;
963 	} s;
964 	struct uv1h_gr0_tlb_mmr_control_s {
965 		unsigned long	index:12;			/* RW */
966 		unsigned long	mem_sel:2;			/* RW */
967 		unsigned long	rsvd_14_15:2;
968 		unsigned long	auto_valid_en:1;		/* RW */
969 		unsigned long	rsvd_17_19:3;
970 		unsigned long	mmr_hash_index_en:1;		/* RW */
971 		unsigned long	rsvd_21_29:9;
972 		unsigned long	mmr_write:1;			/* WP */
973 		unsigned long	mmr_read:1;			/* WP */
974 		unsigned long	rsvd_32_47:16;
975 		unsigned long	mmr_inj_con:1;			/* RW */
976 		unsigned long	rsvd_49_51:3;
977 		unsigned long	mmr_inj_tlbram:1;		/* RW */
978 		unsigned long	rsvd_53:1;
979 		unsigned long	mmr_inj_tlbpgsize:1;		/* RW */
980 		unsigned long	rsvd_55:1;
981 		unsigned long	mmr_inj_tlbrreg:1;		/* RW */
982 		unsigned long	rsvd_57_59:3;
983 		unsigned long	mmr_inj_tlblruv:1;		/* RW */
984 		unsigned long	rsvd_61_63:3;
985 	} s1;
986 	struct uvxh_gr0_tlb_mmr_control_s {
987 		unsigned long	rsvd_0_15:16;
988 		unsigned long	auto_valid_en:1;		/* RW */
989 		unsigned long	rsvd_17_19:3;
990 		unsigned long	mmr_hash_index_en:1;		/* RW */
991 		unsigned long	rsvd_21_29:9;
992 		unsigned long	mmr_write:1;			/* WP */
993 		unsigned long	mmr_read:1;			/* WP */
994 		unsigned long	mmr_op_done:1;			/* RW */
995 		unsigned long	rsvd_33_47:15;
996 		unsigned long	rsvd_48:1;
997 		unsigned long	rsvd_49_51:3;
998 		unsigned long	rsvd_52_63:12;
999 	} sx;
1000 	struct uv2h_gr0_tlb_mmr_control_s {
1001 		unsigned long	index:12;			/* RW */
1002 		unsigned long	mem_sel:2;			/* RW */
1003 		unsigned long	rsvd_14_15:2;
1004 		unsigned long	auto_valid_en:1;		/* RW */
1005 		unsigned long	rsvd_17_19:3;
1006 		unsigned long	mmr_hash_index_en:1;		/* RW */
1007 		unsigned long	rsvd_21_29:9;
1008 		unsigned long	mmr_write:1;			/* WP */
1009 		unsigned long	mmr_read:1;			/* WP */
1010 		unsigned long	mmr_op_done:1;			/* RW */
1011 		unsigned long	rsvd_33_47:15;
1012 		unsigned long	mmr_inj_con:1;			/* RW */
1013 		unsigned long	rsvd_49_51:3;
1014 		unsigned long	mmr_inj_tlbram:1;		/* RW */
1015 		unsigned long	rsvd_53_63:11;
1016 	} s2;
1017 	struct uv3h_gr0_tlb_mmr_control_s {
1018 		unsigned long	index:12;			/* RW */
1019 		unsigned long	mem_sel:2;			/* RW */
1020 		unsigned long	rsvd_14_15:2;
1021 		unsigned long	auto_valid_en:1;		/* RW */
1022 		unsigned long	rsvd_17_19:3;
1023 		unsigned long	mmr_hash_index_en:1;		/* RW */
1024 		unsigned long	ecc_sel:1;			/* RW */
1025 		unsigned long	rsvd_22_29:8;
1026 		unsigned long	mmr_write:1;			/* WP */
1027 		unsigned long	mmr_read:1;			/* WP */
1028 		unsigned long	mmr_op_done:1;			/* RW */
1029 		unsigned long	rsvd_33_47:15;
1030 		unsigned long	undef_48:1;			/* Undefined */
1031 		unsigned long	rsvd_49_51:3;
1032 		unsigned long	undef_52:1;			/* Undefined */
1033 		unsigned long	rsvd_53_63:11;
1034 	} s3;
1035 	struct uv4h_gr0_tlb_mmr_control_s {
1036 		unsigned long	index:13;			/* RW */
1037 		unsigned long	mem_sel:2;			/* RW */
1038 		unsigned long	rsvd_15:1;
1039 		unsigned long	auto_valid_en:1;		/* RW */
1040 		unsigned long	rsvd_17_19:3;
1041 		unsigned long	mmr_hash_index_en:1;		/* RW */
1042 		unsigned long	ecc_sel:1;			/* RW */
1043 		unsigned long	rsvd_22_29:8;
1044 		unsigned long	mmr_write:1;			/* WP */
1045 		unsigned long	mmr_read:1;			/* WP */
1046 		unsigned long	mmr_op_done:1;			/* RW */
1047 		unsigned long	rsvd_33_47:15;
1048 		unsigned long	undef_48:1;			/* Undefined */
1049 		unsigned long	rsvd_49_51:3;
1050 		unsigned long	rsvd_52_58:7;
1051 		unsigned long	page_size:5;			/* RW */
1052 	} s4;
1053 };
1054 
1055 /* ========================================================================= */
1056 /*                       UVH_GR0_TLB_MMR_READ_DATA_HI                        */
1057 /* ========================================================================= */
1058 #define UV1H_GR0_TLB_MMR_READ_DATA_HI 0x4010a0UL
1059 #define UV2H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL
1060 #define UV3H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL
1061 #define UV4H_GR0_TLB_MMR_READ_DATA_HI 0x6010a0UL
1062 #define UVH_GR0_TLB_MMR_READ_DATA_HI (					\
1063 	is_uv1_hub() ? UV1H_GR0_TLB_MMR_READ_DATA_HI :			\
1064 	is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_HI :			\
1065 	is_uv3_hub() ? UV3H_GR0_TLB_MMR_READ_DATA_HI :			\
1066 	/*is_uv4_hub*/ UV4H_GR0_TLB_MMR_READ_DATA_HI)
1067 
1068 #define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
1069 
1070 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
1071 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT		41
1072 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT	43
1073 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT	44
1074 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK		0x000001ffffffffffUL
1075 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK		0x0000060000000000UL
1076 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK	0x0000080000000000UL
1077 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK	0x0000100000000000UL
1078 
1079 #define UVXH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
1080 
1081 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
1082 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT		41
1083 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT	43
1084 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT	44
1085 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK		0x000001ffffffffffUL
1086 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK		0x0000060000000000UL
1087 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK	0x0000080000000000UL
1088 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK	0x0000100000000000UL
1089 
1090 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
1091 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT		41
1092 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT	43
1093 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT	44
1094 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT	45
1095 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT	55
1096 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK		0x000001ffffffffffUL
1097 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK		0x0000060000000000UL
1098 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK	0x0000080000000000UL
1099 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK	0x0000100000000000UL
1100 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_MASK	0x0000200000000000UL
1101 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK	0xff80000000000000UL
1102 
1103 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
1104 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_PNID_SHFT		34
1105 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT		49
1106 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT	51
1107 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT	52
1108 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT	53
1109 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT	55
1110 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK		0x00000003ffffffffUL
1111 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_PNID_MASK		0x0001fffc00000000UL
1112 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK		0x0006000000000000UL
1113 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK	0x0008000000000000UL
1114 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK	0x0010000000000000UL
1115 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_MASK	0x0020000000000000UL
1116 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK	0xff80000000000000UL
1117 
1118 
1119 union uvh_gr0_tlb_mmr_read_data_hi_u {
1120 	unsigned long	v;
1121 	struct uv1h_gr0_tlb_mmr_read_data_hi_s {
1122 		unsigned long	pfn:41;				/* RO */
1123 		unsigned long	gaa:2;				/* RO */
1124 		unsigned long	dirty:1;			/* RO */
1125 		unsigned long	larger:1;			/* RO */
1126 		unsigned long	rsvd_45_63:19;
1127 	} s1;
1128 	struct uv2h_gr0_tlb_mmr_read_data_hi_s {
1129 		unsigned long	pfn:41;				/* RO */
1130 		unsigned long	gaa:2;				/* RO */
1131 		unsigned long	dirty:1;			/* RO */
1132 		unsigned long	larger:1;			/* RO */
1133 		unsigned long	rsvd_45_63:19;
1134 	} s2;
1135 	struct uv3h_gr0_tlb_mmr_read_data_hi_s {
1136 		unsigned long	pfn:41;				/* RO */
1137 		unsigned long	gaa:2;				/* RO */
1138 		unsigned long	dirty:1;			/* RO */
1139 		unsigned long	larger:1;			/* RO */
1140 		unsigned long	aa_ext:1;			/* RO */
1141 		unsigned long	undef_46_54:9;			/* Undefined */
1142 		unsigned long	way_ecc:9;			/* RO */
1143 	} s3;
1144 	struct uv4h_gr0_tlb_mmr_read_data_hi_s {
1145 		unsigned long	pfn:34;				/* RO */
1146 		unsigned long	pnid:15;			/* RO */
1147 		unsigned long	gaa:2;				/* RO */
1148 		unsigned long	dirty:1;			/* RO */
1149 		unsigned long	larger:1;			/* RO */
1150 		unsigned long	aa_ext:1;			/* RO */
1151 		unsigned long	undef_54:1;			/* Undefined */
1152 		unsigned long	way_ecc:9;			/* RO */
1153 	} s4;
1154 };
1155 
1156 /* ========================================================================= */
1157 /*                       UVH_GR0_TLB_MMR_READ_DATA_LO                        */
1158 /* ========================================================================= */
1159 #define UV1H_GR0_TLB_MMR_READ_DATA_LO 0x4010a8UL
1160 #define UV2H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL
1161 #define UV3H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL
1162 #define UV4H_GR0_TLB_MMR_READ_DATA_LO 0x6010a8UL
1163 #define UVH_GR0_TLB_MMR_READ_DATA_LO (					\
1164 	is_uv1_hub() ? UV1H_GR0_TLB_MMR_READ_DATA_LO :			\
1165 	is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_LO :			\
1166 	is_uv3_hub() ? UV3H_GR0_TLB_MMR_READ_DATA_LO :			\
1167 	/*is_uv4_hub*/ UV4H_GR0_TLB_MMR_READ_DATA_LO)
1168 
1169 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
1170 #define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
1171 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT		63
1172 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
1173 #define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
1174 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK		0x8000000000000000UL
1175 
1176 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
1177 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
1178 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT	63
1179 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
1180 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
1181 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK	0x8000000000000000UL
1182 
1183 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
1184 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
1185 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT	63
1186 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
1187 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
1188 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK	0x8000000000000000UL
1189 
1190 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
1191 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
1192 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT	63
1193 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
1194 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
1195 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK	0x8000000000000000UL
1196 
1197 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
1198 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
1199 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT	63
1200 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
1201 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
1202 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK	0x8000000000000000UL
1203 
1204 #define UV4H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
1205 #define UV4H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
1206 #define UV4H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT	63
1207 #define UV4H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
1208 #define UV4H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
1209 #define UV4H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK	0x8000000000000000UL
1210 
1211 
1212 union uvh_gr0_tlb_mmr_read_data_lo_u {
1213 	unsigned long	v;
1214 	struct uvh_gr0_tlb_mmr_read_data_lo_s {
1215 		unsigned long	vpn:39;				/* RO */
1216 		unsigned long	asid:24;			/* RO */
1217 		unsigned long	valid:1;			/* RO */
1218 	} s;
1219 	struct uv1h_gr0_tlb_mmr_read_data_lo_s {
1220 		unsigned long	vpn:39;				/* RO */
1221 		unsigned long	asid:24;			/* RO */
1222 		unsigned long	valid:1;			/* RO */
1223 	} s1;
1224 	struct uvxh_gr0_tlb_mmr_read_data_lo_s {
1225 		unsigned long	vpn:39;				/* RO */
1226 		unsigned long	asid:24;			/* RO */
1227 		unsigned long	valid:1;			/* RO */
1228 	} sx;
1229 	struct uv2h_gr0_tlb_mmr_read_data_lo_s {
1230 		unsigned long	vpn:39;				/* RO */
1231 		unsigned long	asid:24;			/* RO */
1232 		unsigned long	valid:1;			/* RO */
1233 	} s2;
1234 	struct uv3h_gr0_tlb_mmr_read_data_lo_s {
1235 		unsigned long	vpn:39;				/* RO */
1236 		unsigned long	asid:24;			/* RO */
1237 		unsigned long	valid:1;			/* RO */
1238 	} s3;
1239 	struct uv4h_gr0_tlb_mmr_read_data_lo_s {
1240 		unsigned long	vpn:39;				/* RO */
1241 		unsigned long	asid:24;			/* RO */
1242 		unsigned long	valid:1;			/* RO */
1243 	} s4;
1244 };
1245 
1246 /* ========================================================================= */
1247 /*                         UVH_GR1_TLB_INT0_CONFIG                           */
1248 /* ========================================================================= */
1249 #define UV1H_GR1_TLB_INT0_CONFIG 0x61f00UL
1250 #define UV2H_GR1_TLB_INT0_CONFIG 0x61f00UL
1251 #define UV3H_GR1_TLB_INT0_CONFIG 0x61f00UL
1252 #define UV4H_GR1_TLB_INT0_CONFIG 0x62100UL
1253 #define UVH_GR1_TLB_INT0_CONFIG (					\
1254 	is_uv1_hub() ? UV1H_GR1_TLB_INT0_CONFIG :			\
1255 	is_uv2_hub() ? UV2H_GR1_TLB_INT0_CONFIG :			\
1256 	is_uv3_hub() ? UV3H_GR1_TLB_INT0_CONFIG :			\
1257 	/*is_uv4_hub*/ UV4H_GR1_TLB_INT0_CONFIG)
1258 
1259 #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT		0
1260 #define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT			8
1261 #define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT		11
1262 #define UVH_GR1_TLB_INT0_CONFIG_STATUS_SHFT		12
1263 #define UVH_GR1_TLB_INT0_CONFIG_P_SHFT			13
1264 #define UVH_GR1_TLB_INT0_CONFIG_T_SHFT			15
1265 #define UVH_GR1_TLB_INT0_CONFIG_M_SHFT			16
1266 #define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT		32
1267 #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK		0x00000000000000ffUL
1268 #define UVH_GR1_TLB_INT0_CONFIG_DM_MASK			0x0000000000000700UL
1269 #define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK		0x0000000000000800UL
1270 #define UVH_GR1_TLB_INT0_CONFIG_STATUS_MASK		0x0000000000001000UL
1271 #define UVH_GR1_TLB_INT0_CONFIG_P_MASK			0x0000000000002000UL
1272 #define UVH_GR1_TLB_INT0_CONFIG_T_MASK			0x0000000000008000UL
1273 #define UVH_GR1_TLB_INT0_CONFIG_M_MASK			0x0000000000010000UL
1274 #define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK		0xffffffff00000000UL
1275 
1276 
1277 union uvh_gr1_tlb_int0_config_u {
1278 	unsigned long	v;
1279 	struct uvh_gr1_tlb_int0_config_s {
1280 		unsigned long	vector_:8;			/* RW */
1281 		unsigned long	dm:3;				/* RW */
1282 		unsigned long	destmode:1;			/* RW */
1283 		unsigned long	status:1;			/* RO */
1284 		unsigned long	p:1;				/* RO */
1285 		unsigned long	rsvd_14:1;
1286 		unsigned long	t:1;				/* RO */
1287 		unsigned long	m:1;				/* RW */
1288 		unsigned long	rsvd_17_31:15;
1289 		unsigned long	apic_id:32;			/* RW */
1290 	} s;
1291 };
1292 
1293 /* ========================================================================= */
1294 /*                         UVH_GR1_TLB_INT1_CONFIG                           */
1295 /* ========================================================================= */
1296 #define UV1H_GR1_TLB_INT1_CONFIG 0x61f40UL
1297 #define UV2H_GR1_TLB_INT1_CONFIG 0x61f40UL
1298 #define UV3H_GR1_TLB_INT1_CONFIG 0x61f40UL
1299 #define UV4H_GR1_TLB_INT1_CONFIG 0x62140UL
1300 #define UVH_GR1_TLB_INT1_CONFIG (					\
1301 	is_uv1_hub() ? UV1H_GR1_TLB_INT1_CONFIG :			\
1302 	is_uv2_hub() ? UV2H_GR1_TLB_INT1_CONFIG :			\
1303 	is_uv3_hub() ? UV3H_GR1_TLB_INT1_CONFIG :			\
1304 	/*is_uv4_hub*/ UV4H_GR1_TLB_INT1_CONFIG)
1305 
1306 #define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT		0
1307 #define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT			8
1308 #define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT		11
1309 #define UVH_GR1_TLB_INT1_CONFIG_STATUS_SHFT		12
1310 #define UVH_GR1_TLB_INT1_CONFIG_P_SHFT			13
1311 #define UVH_GR1_TLB_INT1_CONFIG_T_SHFT			15
1312 #define UVH_GR1_TLB_INT1_CONFIG_M_SHFT			16
1313 #define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT		32
1314 #define UVH_GR1_TLB_INT1_CONFIG_VECTOR_MASK		0x00000000000000ffUL
1315 #define UVH_GR1_TLB_INT1_CONFIG_DM_MASK			0x0000000000000700UL
1316 #define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK		0x0000000000000800UL
1317 #define UVH_GR1_TLB_INT1_CONFIG_STATUS_MASK		0x0000000000001000UL
1318 #define UVH_GR1_TLB_INT1_CONFIG_P_MASK			0x0000000000002000UL
1319 #define UVH_GR1_TLB_INT1_CONFIG_T_MASK			0x0000000000008000UL
1320 #define UVH_GR1_TLB_INT1_CONFIG_M_MASK			0x0000000000010000UL
1321 #define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK		0xffffffff00000000UL
1322 
1323 
1324 union uvh_gr1_tlb_int1_config_u {
1325 	unsigned long	v;
1326 	struct uvh_gr1_tlb_int1_config_s {
1327 		unsigned long	vector_:8;			/* RW */
1328 		unsigned long	dm:3;				/* RW */
1329 		unsigned long	destmode:1;			/* RW */
1330 		unsigned long	status:1;			/* RO */
1331 		unsigned long	p:1;				/* RO */
1332 		unsigned long	rsvd_14:1;
1333 		unsigned long	t:1;				/* RO */
1334 		unsigned long	m:1;				/* RW */
1335 		unsigned long	rsvd_17_31:15;
1336 		unsigned long	apic_id:32;			/* RW */
1337 	} s;
1338 };
1339 
1340 /* ========================================================================= */
1341 /*                         UVH_GR1_TLB_MMR_CONTROL                           */
1342 /* ========================================================================= */
1343 #define UV1H_GR1_TLB_MMR_CONTROL 0x801080UL
1344 #define UV2H_GR1_TLB_MMR_CONTROL 0x1001080UL
1345 #define UV3H_GR1_TLB_MMR_CONTROL 0x1001080UL
1346 #define UV4H_GR1_TLB_MMR_CONTROL 0x701080UL
1347 #define UVH_GR1_TLB_MMR_CONTROL (					\
1348 	is_uv1_hub() ? UV1H_GR1_TLB_MMR_CONTROL :			\
1349 	is_uv2_hub() ? UV2H_GR1_TLB_MMR_CONTROL :			\
1350 	is_uv3_hub() ? UV3H_GR1_TLB_MMR_CONTROL :			\
1351 	/*is_uv4_hub*/ UV4H_GR1_TLB_MMR_CONTROL)
1352 
1353 #define UVH_GR1_TLB_MMR_CONTROL_INDEX_SHFT		0
1354 #define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
1355 #define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
1356 #define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
1357 #define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT		31
1358 #define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
1359 #define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
1360 #define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
1361 #define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL
1362 
1363 #define UV1H_GR1_TLB_MMR_CONTROL_INDEX_SHFT		0
1364 #define UV1H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT		12
1365 #define UV1H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
1366 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
1367 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
1368 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT		31
1369 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT	48
1370 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT	52
1371 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_SHFT	54
1372 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_SHFT	56
1373 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_SHFT	60
1374 #define UV1H_GR1_TLB_MMR_CONTROL_INDEX_MASK		0x0000000000000fffUL
1375 #define UV1H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK		0x0000000000003000UL
1376 #define UV1H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
1377 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
1378 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
1379 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL
1380 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK	0x0001000000000000UL
1381 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK	0x0010000000000000UL
1382 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_MASK	0x0040000000000000UL
1383 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK	0x0100000000000000UL
1384 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK	0x1000000000000000UL
1385 
1386 #define UVXH_GR1_TLB_MMR_CONTROL_INDEX_SHFT		0
1387 #define UVXH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
1388 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
1389 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
1390 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT		31
1391 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT	32
1392 #define UVXH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
1393 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
1394 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
1395 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL
1396 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK	0x0000000100000000UL
1397 
1398 #define UV2H_GR1_TLB_MMR_CONTROL_INDEX_SHFT		0
1399 #define UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT		12
1400 #define UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
1401 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
1402 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
1403 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT		31
1404 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT	32
1405 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT	48
1406 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT	52
1407 #define UV2H_GR1_TLB_MMR_CONTROL_INDEX_MASK		0x0000000000000fffUL
1408 #define UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK		0x0000000000003000UL
1409 #define UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
1410 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
1411 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
1412 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL
1413 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK	0x0000000100000000UL
1414 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK	0x0001000000000000UL
1415 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK	0x0010000000000000UL
1416 
1417 #define UV3H_GR1_TLB_MMR_CONTROL_INDEX_SHFT		0
1418 #define UV3H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT		12
1419 #define UV3H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
1420 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
1421 #define UV3H_GR1_TLB_MMR_CONTROL_ECC_SEL_SHFT		21
1422 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
1423 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT		31
1424 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT	32
1425 #define UV3H_GR1_TLB_MMR_CONTROL_INDEX_MASK		0x0000000000000fffUL
1426 #define UV3H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK		0x0000000000003000UL
1427 #define UV3H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
1428 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
1429 #define UV3H_GR1_TLB_MMR_CONTROL_ECC_SEL_MASK		0x0000000000200000UL
1430 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
1431 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL
1432 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK	0x0000000100000000UL
1433 
1434 #define UV4H_GR1_TLB_MMR_CONTROL_INDEX_SHFT		0
1435 #define UV4H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT		13
1436 #define UV4H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT	16
1437 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT	20
1438 #define UV4H_GR1_TLB_MMR_CONTROL_ECC_SEL_SHFT		21
1439 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT		30
1440 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT		31
1441 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT	32
1442 #define UV4H_GR1_TLB_MMR_CONTROL_PAGE_SIZE_SHFT		59
1443 #define UV4H_GR1_TLB_MMR_CONTROL_INDEX_MASK		0x0000000000001fffUL
1444 #define UV4H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK		0x0000000000006000UL
1445 #define UV4H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK	0x0000000000010000UL
1446 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK	0x0000000000100000UL
1447 #define UV4H_GR1_TLB_MMR_CONTROL_ECC_SEL_MASK		0x0000000000200000UL
1448 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK		0x0000000040000000UL
1449 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK		0x0000000080000000UL
1450 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK	0x0000000100000000UL
1451 #define UV4H_GR1_TLB_MMR_CONTROL_PAGE_SIZE_MASK		0xf800000000000000UL
1452 
1453 
1454 union uvh_gr1_tlb_mmr_control_u {
1455 	unsigned long	v;
1456 	struct uvh_gr1_tlb_mmr_control_s {
1457 		unsigned long	rsvd_0_15:16;
1458 		unsigned long	auto_valid_en:1;		/* RW */
1459 		unsigned long	rsvd_17_19:3;
1460 		unsigned long	mmr_hash_index_en:1;		/* RW */
1461 		unsigned long	rsvd_21_29:9;
1462 		unsigned long	mmr_write:1;			/* WP */
1463 		unsigned long	mmr_read:1;			/* WP */
1464 		unsigned long	rsvd_32_48:17;
1465 		unsigned long	rsvd_49_51:3;
1466 		unsigned long	rsvd_52_63:12;
1467 	} s;
1468 	struct uv1h_gr1_tlb_mmr_control_s {
1469 		unsigned long	index:12;			/* RW */
1470 		unsigned long	mem_sel:2;			/* RW */
1471 		unsigned long	rsvd_14_15:2;
1472 		unsigned long	auto_valid_en:1;		/* RW */
1473 		unsigned long	rsvd_17_19:3;
1474 		unsigned long	mmr_hash_index_en:1;		/* RW */
1475 		unsigned long	rsvd_21_29:9;
1476 		unsigned long	mmr_write:1;			/* WP */
1477 		unsigned long	mmr_read:1;			/* WP */
1478 		unsigned long	rsvd_32_47:16;
1479 		unsigned long	mmr_inj_con:1;			/* RW */
1480 		unsigned long	rsvd_49_51:3;
1481 		unsigned long	mmr_inj_tlbram:1;		/* RW */
1482 		unsigned long	rsvd_53:1;
1483 		unsigned long	mmr_inj_tlbpgsize:1;		/* RW */
1484 		unsigned long	rsvd_55:1;
1485 		unsigned long	mmr_inj_tlbrreg:1;		/* RW */
1486 		unsigned long	rsvd_57_59:3;
1487 		unsigned long	mmr_inj_tlblruv:1;		/* RW */
1488 		unsigned long	rsvd_61_63:3;
1489 	} s1;
1490 	struct uvxh_gr1_tlb_mmr_control_s {
1491 		unsigned long	rsvd_0_15:16;
1492 		unsigned long	auto_valid_en:1;		/* RW */
1493 		unsigned long	rsvd_17_19:3;
1494 		unsigned long	mmr_hash_index_en:1;		/* RW */
1495 		unsigned long	rsvd_21_29:9;
1496 		unsigned long	mmr_write:1;			/* WP */
1497 		unsigned long	mmr_read:1;			/* WP */
1498 		unsigned long	mmr_op_done:1;			/* RW */
1499 		unsigned long	rsvd_33_47:15;
1500 		unsigned long	rsvd_48:1;
1501 		unsigned long	rsvd_49_51:3;
1502 		unsigned long	rsvd_52_63:12;
1503 	} sx;
1504 	struct uv2h_gr1_tlb_mmr_control_s {
1505 		unsigned long	index:12;			/* RW */
1506 		unsigned long	mem_sel:2;			/* RW */
1507 		unsigned long	rsvd_14_15:2;
1508 		unsigned long	auto_valid_en:1;		/* RW */
1509 		unsigned long	rsvd_17_19:3;
1510 		unsigned long	mmr_hash_index_en:1;		/* RW */
1511 		unsigned long	rsvd_21_29:9;
1512 		unsigned long	mmr_write:1;			/* WP */
1513 		unsigned long	mmr_read:1;			/* WP */
1514 		unsigned long	mmr_op_done:1;			/* RW */
1515 		unsigned long	rsvd_33_47:15;
1516 		unsigned long	mmr_inj_con:1;			/* RW */
1517 		unsigned long	rsvd_49_51:3;
1518 		unsigned long	mmr_inj_tlbram:1;		/* RW */
1519 		unsigned long	rsvd_53_63:11;
1520 	} s2;
1521 	struct uv3h_gr1_tlb_mmr_control_s {
1522 		unsigned long	index:12;			/* RW */
1523 		unsigned long	mem_sel:2;			/* RW */
1524 		unsigned long	rsvd_14_15:2;
1525 		unsigned long	auto_valid_en:1;		/* RW */
1526 		unsigned long	rsvd_17_19:3;
1527 		unsigned long	mmr_hash_index_en:1;		/* RW */
1528 		unsigned long	ecc_sel:1;			/* RW */
1529 		unsigned long	rsvd_22_29:8;
1530 		unsigned long	mmr_write:1;			/* WP */
1531 		unsigned long	mmr_read:1;			/* WP */
1532 		unsigned long	mmr_op_done:1;			/* RW */
1533 		unsigned long	rsvd_33_47:15;
1534 		unsigned long	undef_48:1;			/* Undefined */
1535 		unsigned long	rsvd_49_51:3;
1536 		unsigned long	undef_52:1;			/* Undefined */
1537 		unsigned long	rsvd_53_63:11;
1538 	} s3;
1539 	struct uv4h_gr1_tlb_mmr_control_s {
1540 		unsigned long	index:13;			/* RW */
1541 		unsigned long	mem_sel:2;			/* RW */
1542 		unsigned long	rsvd_15:1;
1543 		unsigned long	auto_valid_en:1;		/* RW */
1544 		unsigned long	rsvd_17_19:3;
1545 		unsigned long	mmr_hash_index_en:1;		/* RW */
1546 		unsigned long	ecc_sel:1;			/* RW */
1547 		unsigned long	rsvd_22_29:8;
1548 		unsigned long	mmr_write:1;			/* WP */
1549 		unsigned long	mmr_read:1;			/* WP */
1550 		unsigned long	mmr_op_done:1;			/* RW */
1551 		unsigned long	rsvd_33_47:15;
1552 		unsigned long	undef_48:1;			/* Undefined */
1553 		unsigned long	rsvd_49_51:3;
1554 		unsigned long	rsvd_52_58:7;
1555 		unsigned long	page_size:5;			/* RW */
1556 	} s4;
1557 };
1558 
1559 /* ========================================================================= */
1560 /*                       UVH_GR1_TLB_MMR_READ_DATA_HI                        */
1561 /* ========================================================================= */
1562 #define UV1H_GR1_TLB_MMR_READ_DATA_HI 0x8010a0UL
1563 #define UV2H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL
1564 #define UV3H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL
1565 #define UV4H_GR1_TLB_MMR_READ_DATA_HI 0x7010a0UL
1566 #define UVH_GR1_TLB_MMR_READ_DATA_HI (					\
1567 	is_uv1_hub() ? UV1H_GR1_TLB_MMR_READ_DATA_HI :			\
1568 	is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_HI :			\
1569 	is_uv3_hub() ? UV3H_GR1_TLB_MMR_READ_DATA_HI :			\
1570 	/*is_uv4_hub*/ UV4H_GR1_TLB_MMR_READ_DATA_HI)
1571 
1572 #define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
1573 
1574 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
1575 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT		41
1576 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT	43
1577 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT	44
1578 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK		0x000001ffffffffffUL
1579 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK		0x0000060000000000UL
1580 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK	0x0000080000000000UL
1581 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK	0x0000100000000000UL
1582 
1583 #define UVXH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
1584 
1585 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
1586 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT		41
1587 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT	43
1588 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT	44
1589 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK		0x000001ffffffffffUL
1590 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK		0x0000060000000000UL
1591 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK	0x0000080000000000UL
1592 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK	0x0000100000000000UL
1593 
1594 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
1595 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT		41
1596 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT	43
1597 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT	44
1598 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT	45
1599 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT	55
1600 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK		0x000001ffffffffffUL
1601 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK		0x0000060000000000UL
1602 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK	0x0000080000000000UL
1603 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK	0x0000100000000000UL
1604 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_MASK	0x0000200000000000UL
1605 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK	0xff80000000000000UL
1606 
1607 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT		0
1608 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_PNID_SHFT		34
1609 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT		49
1610 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT	51
1611 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT	52
1612 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT	53
1613 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT	55
1614 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK		0x00000003ffffffffUL
1615 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_PNID_MASK		0x0001fffc00000000UL
1616 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK		0x0006000000000000UL
1617 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK	0x0008000000000000UL
1618 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK	0x0010000000000000UL
1619 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_MASK	0x0020000000000000UL
1620 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK	0xff80000000000000UL
1621 
1622 
1623 union uvh_gr1_tlb_mmr_read_data_hi_u {
1624 	unsigned long	v;
1625 	struct uv1h_gr1_tlb_mmr_read_data_hi_s {
1626 		unsigned long	pfn:41;				/* RO */
1627 		unsigned long	gaa:2;				/* RO */
1628 		unsigned long	dirty:1;			/* RO */
1629 		unsigned long	larger:1;			/* RO */
1630 		unsigned long	rsvd_45_63:19;
1631 	} s1;
1632 	struct uv2h_gr1_tlb_mmr_read_data_hi_s {
1633 		unsigned long	pfn:41;				/* RO */
1634 		unsigned long	gaa:2;				/* RO */
1635 		unsigned long	dirty:1;			/* RO */
1636 		unsigned long	larger:1;			/* RO */
1637 		unsigned long	rsvd_45_63:19;
1638 	} s2;
1639 	struct uv3h_gr1_tlb_mmr_read_data_hi_s {
1640 		unsigned long	pfn:41;				/* RO */
1641 		unsigned long	gaa:2;				/* RO */
1642 		unsigned long	dirty:1;			/* RO */
1643 		unsigned long	larger:1;			/* RO */
1644 		unsigned long	aa_ext:1;			/* RO */
1645 		unsigned long	undef_46_54:9;			/* Undefined */
1646 		unsigned long	way_ecc:9;			/* RO */
1647 	} s3;
1648 	struct uv4h_gr1_tlb_mmr_read_data_hi_s {
1649 		unsigned long	pfn:34;				/* RO */
1650 		unsigned long	pnid:15;			/* RO */
1651 		unsigned long	gaa:2;				/* RO */
1652 		unsigned long	dirty:1;			/* RO */
1653 		unsigned long	larger:1;			/* RO */
1654 		unsigned long	aa_ext:1;			/* RO */
1655 		unsigned long	undef_54:1;			/* Undefined */
1656 		unsigned long	way_ecc:9;			/* RO */
1657 	} s4;
1658 };
1659 
1660 /* ========================================================================= */
1661 /*                       UVH_GR1_TLB_MMR_READ_DATA_LO                        */
1662 /* ========================================================================= */
1663 #define UV1H_GR1_TLB_MMR_READ_DATA_LO 0x8010a8UL
1664 #define UV2H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL
1665 #define UV3H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL
1666 #define UV4H_GR1_TLB_MMR_READ_DATA_LO 0x7010a8UL
1667 #define UVH_GR1_TLB_MMR_READ_DATA_LO (					\
1668 	is_uv1_hub() ? UV1H_GR1_TLB_MMR_READ_DATA_LO :			\
1669 	is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_LO :			\
1670 	is_uv3_hub() ? UV3H_GR1_TLB_MMR_READ_DATA_LO :			\
1671 	/*is_uv4_hub*/ UV4H_GR1_TLB_MMR_READ_DATA_LO)
1672 
1673 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
1674 #define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
1675 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT		63
1676 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
1677 #define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
1678 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK		0x8000000000000000UL
1679 
1680 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
1681 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
1682 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT	63
1683 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
1684 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
1685 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK	0x8000000000000000UL
1686 
1687 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
1688 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
1689 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT	63
1690 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
1691 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
1692 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK	0x8000000000000000UL
1693 
1694 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
1695 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
1696 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT	63
1697 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
1698 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
1699 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK	0x8000000000000000UL
1700 
1701 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
1702 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
1703 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT	63
1704 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
1705 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
1706 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK	0x8000000000000000UL
1707 
1708 #define UV4H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT		0
1709 #define UV4H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT		39
1710 #define UV4H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT	63
1711 #define UV4H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK		0x0000007fffffffffUL
1712 #define UV4H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK		0x7fffff8000000000UL
1713 #define UV4H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK	0x8000000000000000UL
1714 
1715 
1716 union uvh_gr1_tlb_mmr_read_data_lo_u {
1717 	unsigned long	v;
1718 	struct uvh_gr1_tlb_mmr_read_data_lo_s {
1719 		unsigned long	vpn:39;				/* RO */
1720 		unsigned long	asid:24;			/* RO */
1721 		unsigned long	valid:1;			/* RO */
1722 	} s;
1723 	struct uv1h_gr1_tlb_mmr_read_data_lo_s {
1724 		unsigned long	vpn:39;				/* RO */
1725 		unsigned long	asid:24;			/* RO */
1726 		unsigned long	valid:1;			/* RO */
1727 	} s1;
1728 	struct uvxh_gr1_tlb_mmr_read_data_lo_s {
1729 		unsigned long	vpn:39;				/* RO */
1730 		unsigned long	asid:24;			/* RO */
1731 		unsigned long	valid:1;			/* RO */
1732 	} sx;
1733 	struct uv2h_gr1_tlb_mmr_read_data_lo_s {
1734 		unsigned long	vpn:39;				/* RO */
1735 		unsigned long	asid:24;			/* RO */
1736 		unsigned long	valid:1;			/* RO */
1737 	} s2;
1738 	struct uv3h_gr1_tlb_mmr_read_data_lo_s {
1739 		unsigned long	vpn:39;				/* RO */
1740 		unsigned long	asid:24;			/* RO */
1741 		unsigned long	valid:1;			/* RO */
1742 	} s3;
1743 	struct uv4h_gr1_tlb_mmr_read_data_lo_s {
1744 		unsigned long	vpn:39;				/* RO */
1745 		unsigned long	asid:24;			/* RO */
1746 		unsigned long	valid:1;			/* RO */
1747 	} s4;
1748 };
1749 
1750 /* ========================================================================= */
1751 /*                               UVH_INT_CMPB                                */
1752 /* ========================================================================= */
1753 #define UVH_INT_CMPB 0x22080UL
1754 
1755 #define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT		0
1756 #define UVH_INT_CMPB_REAL_TIME_CMPB_MASK		0x00ffffffffffffffUL
1757 
1758 
1759 union uvh_int_cmpb_u {
1760 	unsigned long	v;
1761 	struct uvh_int_cmpb_s {
1762 		unsigned long	real_time_cmpb:56;		/* RW */
1763 		unsigned long	rsvd_56_63:8;
1764 	} s;
1765 };
1766 
1767 /* ========================================================================= */
1768 /*                               UVH_INT_CMPC                                */
1769 /* ========================================================================= */
1770 #define UVH_INT_CMPC 0x22100UL
1771 
1772 
1773 #define UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT		0
1774 #define UV1H_INT_CMPC_REAL_TIME_CMPC_MASK		0x00ffffffffffffffUL
1775 
1776 #define UVXH_INT_CMPC_REAL_TIME_CMP_2_SHFT		0
1777 #define UVXH_INT_CMPC_REAL_TIME_CMP_2_MASK		0x00ffffffffffffffUL
1778 
1779 
1780 union uvh_int_cmpc_u {
1781 	unsigned long	v;
1782 	struct uvh_int_cmpc_s {
1783 		unsigned long	real_time_cmpc:56;		/* RW */
1784 		unsigned long	rsvd_56_63:8;
1785 	} s;
1786 };
1787 
1788 /* ========================================================================= */
1789 /*                               UVH_INT_CMPD                                */
1790 /* ========================================================================= */
1791 #define UVH_INT_CMPD 0x22180UL
1792 
1793 
1794 #define UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT		0
1795 #define UV1H_INT_CMPD_REAL_TIME_CMPD_MASK		0x00ffffffffffffffUL
1796 
1797 #define UVXH_INT_CMPD_REAL_TIME_CMP_3_SHFT		0
1798 #define UVXH_INT_CMPD_REAL_TIME_CMP_3_MASK		0x00ffffffffffffffUL
1799 
1800 
1801 union uvh_int_cmpd_u {
1802 	unsigned long	v;
1803 	struct uvh_int_cmpd_s {
1804 		unsigned long	real_time_cmpd:56;		/* RW */
1805 		unsigned long	rsvd_56_63:8;
1806 	} s;
1807 };
1808 
1809 /* ========================================================================= */
1810 /*                               UVH_IPI_INT                                 */
1811 /* ========================================================================= */
1812 #define UVH_IPI_INT 0x60500UL
1813 
1814 #define UV1H_IPI_INT_32 0x348
1815 #define UV2H_IPI_INT_32 0x348
1816 #define UV3H_IPI_INT_32 0x348
1817 #define UV4H_IPI_INT_32 0x268
1818 #define UVH_IPI_INT_32 (						\
1819 	is_uv1_hub() ? UV1H_IPI_INT_32 :				\
1820 	is_uv2_hub() ? UV2H_IPI_INT_32 :				\
1821 	is_uv3_hub() ? UV3H_IPI_INT_32 :				\
1822 	/*is_uv4_hub*/ UV4H_IPI_INT_32)
1823 
1824 #define UVH_IPI_INT_VECTOR_SHFT				0
1825 #define UVH_IPI_INT_DELIVERY_MODE_SHFT			8
1826 #define UVH_IPI_INT_DESTMODE_SHFT			11
1827 #define UVH_IPI_INT_APIC_ID_SHFT			16
1828 #define UVH_IPI_INT_SEND_SHFT				63
1829 #define UVH_IPI_INT_VECTOR_MASK				0x00000000000000ffUL
1830 #define UVH_IPI_INT_DELIVERY_MODE_MASK			0x0000000000000700UL
1831 #define UVH_IPI_INT_DESTMODE_MASK			0x0000000000000800UL
1832 #define UVH_IPI_INT_APIC_ID_MASK			0x0000ffffffff0000UL
1833 #define UVH_IPI_INT_SEND_MASK				0x8000000000000000UL
1834 
1835 
1836 union uvh_ipi_int_u {
1837 	unsigned long	v;
1838 	struct uvh_ipi_int_s {
1839 		unsigned long	vector_:8;			/* RW */
1840 		unsigned long	delivery_mode:3;		/* RW */
1841 		unsigned long	destmode:1;			/* RW */
1842 		unsigned long	rsvd_12_15:4;
1843 		unsigned long	apic_id:32;			/* RW */
1844 		unsigned long	rsvd_48_62:15;
1845 		unsigned long	send:1;				/* WP */
1846 	} s;
1847 };
1848 
1849 /* ========================================================================= */
1850 /*                   UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST                     */
1851 /* ========================================================================= */
1852 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
1853 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
1854 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
1855 #define UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST uv_undefined("UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST")
1856 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST (				\
1857 	is_uv1_hub() ? UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST :		\
1858 	is_uv2_hub() ? UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST :		\
1859 	is_uv3_hub() ? UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST :		\
1860 	/*is_uv4_hub*/ UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST)
1861 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x9c0
1862 
1863 
1864 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
1865 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
1866 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
1867 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
1868 
1869 
1870 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
1871 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
1872 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
1873 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
1874 
1875 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
1876 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
1877 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
1878 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
1879 
1880 
1881 union uvh_lb_bau_intd_payload_queue_first_u {
1882 	unsigned long	v;
1883 	struct uv1h_lb_bau_intd_payload_queue_first_s {
1884 		unsigned long	rsvd_0_3:4;
1885 		unsigned long	address:39;			/* RW */
1886 		unsigned long	rsvd_43_48:6;
1887 		unsigned long	node_id:14;			/* RW */
1888 		unsigned long	rsvd_63:1;
1889 	} s1;
1890 	struct uv2h_lb_bau_intd_payload_queue_first_s {
1891 		unsigned long	rsvd_0_3:4;
1892 		unsigned long	address:39;			/* RW */
1893 		unsigned long	rsvd_43_48:6;
1894 		unsigned long	node_id:14;			/* RW */
1895 		unsigned long	rsvd_63:1;
1896 	} s2;
1897 	struct uv3h_lb_bau_intd_payload_queue_first_s {
1898 		unsigned long	rsvd_0_3:4;
1899 		unsigned long	address:39;			/* RW */
1900 		unsigned long	rsvd_43_48:6;
1901 		unsigned long	node_id:14;			/* RW */
1902 		unsigned long	rsvd_63:1;
1903 	} s3;
1904 };
1905 
1906 /* ========================================================================= */
1907 /*                    UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST                     */
1908 /* ========================================================================= */
1909 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
1910 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
1911 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
1912 #define UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST uv_undefined("UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST")
1913 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST (				\
1914 	is_uv1_hub() ? UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST :		\
1915 	is_uv2_hub() ? UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST :		\
1916 	is_uv3_hub() ? UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST :		\
1917 	/*is_uv4_hub*/ UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST)
1918 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x9c8
1919 
1920 
1921 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
1922 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
1923 
1924 
1925 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
1926 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
1927 
1928 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
1929 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
1930 
1931 
1932 union uvh_lb_bau_intd_payload_queue_last_u {
1933 	unsigned long	v;
1934 	struct uv1h_lb_bau_intd_payload_queue_last_s {
1935 		unsigned long	rsvd_0_3:4;
1936 		unsigned long	address:39;			/* RW */
1937 		unsigned long	rsvd_43_63:21;
1938 	} s1;
1939 	struct uv2h_lb_bau_intd_payload_queue_last_s {
1940 		unsigned long	rsvd_0_3:4;
1941 		unsigned long	address:39;			/* RW */
1942 		unsigned long	rsvd_43_63:21;
1943 	} s2;
1944 	struct uv3h_lb_bau_intd_payload_queue_last_s {
1945 		unsigned long	rsvd_0_3:4;
1946 		unsigned long	address:39;			/* RW */
1947 		unsigned long	rsvd_43_63:21;
1948 	} s3;
1949 };
1950 
1951 /* ========================================================================= */
1952 /*                    UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL                     */
1953 /* ========================================================================= */
1954 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
1955 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
1956 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
1957 #define UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL uv_undefined("UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL")
1958 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL (				\
1959 	is_uv1_hub() ? UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL :		\
1960 	is_uv2_hub() ? UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL :		\
1961 	is_uv3_hub() ? UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL :		\
1962 	/*is_uv4_hub*/ UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL)
1963 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x9d0
1964 
1965 
1966 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
1967 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
1968 
1969 
1970 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
1971 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
1972 
1973 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
1974 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
1975 
1976 
1977 union uvh_lb_bau_intd_payload_queue_tail_u {
1978 	unsigned long	v;
1979 	struct uv1h_lb_bau_intd_payload_queue_tail_s {
1980 		unsigned long	rsvd_0_3:4;
1981 		unsigned long	address:39;			/* RW */
1982 		unsigned long	rsvd_43_63:21;
1983 	} s1;
1984 	struct uv2h_lb_bau_intd_payload_queue_tail_s {
1985 		unsigned long	rsvd_0_3:4;
1986 		unsigned long	address:39;			/* RW */
1987 		unsigned long	rsvd_43_63:21;
1988 	} s2;
1989 	struct uv3h_lb_bau_intd_payload_queue_tail_s {
1990 		unsigned long	rsvd_0_3:4;
1991 		unsigned long	address:39;			/* RW */
1992 		unsigned long	rsvd_43_63:21;
1993 	} s3;
1994 };
1995 
1996 /* ========================================================================= */
1997 /*                   UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE                    */
1998 /* ========================================================================= */
1999 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
2000 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
2001 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
2002 #define UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE uv_undefined("UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE")
2003 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE (				\
2004 	is_uv1_hub() ? UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE :		\
2005 	is_uv2_hub() ? UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE :		\
2006 	is_uv3_hub() ? UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE :		\
2007 	/*is_uv4_hub*/ UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE)
2008 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0xa68
2009 
2010 
2011 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
2012 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
2013 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
2014 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
2015 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
2016 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
2017 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
2018 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
2019 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
2020 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
2021 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
2022 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
2023 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
2024 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
2025 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
2026 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
2027 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
2028 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
2029 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
2030 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
2031 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
2032 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
2033 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
2034 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
2035 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
2036 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
2037 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
2038 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
2039 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
2040 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
2041 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
2042 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
2043 
2044 
2045 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
2046 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
2047 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
2048 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
2049 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
2050 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
2051 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
2052 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
2053 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
2054 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
2055 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
2056 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
2057 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
2058 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
2059 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
2060 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
2061 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
2062 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
2063 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
2064 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
2065 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
2066 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
2067 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
2068 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
2069 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
2070 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
2071 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
2072 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
2073 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
2074 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
2075 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
2076 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
2077 
2078 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
2079 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
2080 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
2081 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
2082 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
2083 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
2084 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
2085 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
2086 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
2087 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
2088 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
2089 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
2090 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
2091 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
2092 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
2093 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
2094 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
2095 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
2096 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
2097 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
2098 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
2099 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
2100 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
2101 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
2102 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
2103 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
2104 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
2105 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
2106 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
2107 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
2108 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
2109 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
2110 
2111 
2112 union uvh_lb_bau_intd_software_acknowledge_u {
2113 	unsigned long	v;
2114 	struct uv1h_lb_bau_intd_software_acknowledge_s {
2115 		unsigned long	pending_0:1;			/* RW, W1C */
2116 		unsigned long	pending_1:1;			/* RW, W1C */
2117 		unsigned long	pending_2:1;			/* RW, W1C */
2118 		unsigned long	pending_3:1;			/* RW, W1C */
2119 		unsigned long	pending_4:1;			/* RW, W1C */
2120 		unsigned long	pending_5:1;			/* RW, W1C */
2121 		unsigned long	pending_6:1;			/* RW, W1C */
2122 		unsigned long	pending_7:1;			/* RW, W1C */
2123 		unsigned long	timeout_0:1;			/* RW, W1C */
2124 		unsigned long	timeout_1:1;			/* RW, W1C */
2125 		unsigned long	timeout_2:1;			/* RW, W1C */
2126 		unsigned long	timeout_3:1;			/* RW, W1C */
2127 		unsigned long	timeout_4:1;			/* RW, W1C */
2128 		unsigned long	timeout_5:1;			/* RW, W1C */
2129 		unsigned long	timeout_6:1;			/* RW, W1C */
2130 		unsigned long	timeout_7:1;			/* RW, W1C */
2131 		unsigned long	rsvd_16_63:48;
2132 	} s1;
2133 	struct uv2h_lb_bau_intd_software_acknowledge_s {
2134 		unsigned long	pending_0:1;			/* RW */
2135 		unsigned long	pending_1:1;			/* RW */
2136 		unsigned long	pending_2:1;			/* RW */
2137 		unsigned long	pending_3:1;			/* RW */
2138 		unsigned long	pending_4:1;			/* RW */
2139 		unsigned long	pending_5:1;			/* RW */
2140 		unsigned long	pending_6:1;			/* RW */
2141 		unsigned long	pending_7:1;			/* RW */
2142 		unsigned long	timeout_0:1;			/* RW */
2143 		unsigned long	timeout_1:1;			/* RW */
2144 		unsigned long	timeout_2:1;			/* RW */
2145 		unsigned long	timeout_3:1;			/* RW */
2146 		unsigned long	timeout_4:1;			/* RW */
2147 		unsigned long	timeout_5:1;			/* RW */
2148 		unsigned long	timeout_6:1;			/* RW */
2149 		unsigned long	timeout_7:1;			/* RW */
2150 		unsigned long	rsvd_16_63:48;
2151 	} s2;
2152 	struct uv3h_lb_bau_intd_software_acknowledge_s {
2153 		unsigned long	pending_0:1;			/* RW */
2154 		unsigned long	pending_1:1;			/* RW */
2155 		unsigned long	pending_2:1;			/* RW */
2156 		unsigned long	pending_3:1;			/* RW */
2157 		unsigned long	pending_4:1;			/* RW */
2158 		unsigned long	pending_5:1;			/* RW */
2159 		unsigned long	pending_6:1;			/* RW */
2160 		unsigned long	pending_7:1;			/* RW */
2161 		unsigned long	timeout_0:1;			/* RW */
2162 		unsigned long	timeout_1:1;			/* RW */
2163 		unsigned long	timeout_2:1;			/* RW */
2164 		unsigned long	timeout_3:1;			/* RW */
2165 		unsigned long	timeout_4:1;			/* RW */
2166 		unsigned long	timeout_5:1;			/* RW */
2167 		unsigned long	timeout_6:1;			/* RW */
2168 		unsigned long	timeout_7:1;			/* RW */
2169 		unsigned long	rsvd_16_63:48;
2170 	} s3;
2171 };
2172 
2173 /* ========================================================================= */
2174 /*                UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS                 */
2175 /* ========================================================================= */
2176 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL
2177 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL
2178 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL
2179 #define UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS uv_undefined("UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS")
2180 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS (			\
2181 	is_uv1_hub() ? UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS :	\
2182 	is_uv2_hub() ? UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS :	\
2183 	is_uv3_hub() ? UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS :	\
2184 	/*is_uv4_hub*/ UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS)
2185 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0xa70
2186 
2187 
2188 /* ========================================================================= */
2189 /*                         UVH_LB_BAU_MISC_CONTROL                           */
2190 /* ========================================================================= */
2191 #define UV1H_LB_BAU_MISC_CONTROL 0x320170UL
2192 #define UV2H_LB_BAU_MISC_CONTROL 0x320170UL
2193 #define UV3H_LB_BAU_MISC_CONTROL 0x320170UL
2194 #define UV4H_LB_BAU_MISC_CONTROL 0xc8170UL
2195 #define UVH_LB_BAU_MISC_CONTROL (					\
2196 	is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL :			\
2197 	is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL :			\
2198 	is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL :			\
2199 	/*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL)
2200 
2201 #define UV1H_LB_BAU_MISC_CONTROL_32 0xa10
2202 #define UV2H_LB_BAU_MISC_CONTROL_32 0xa10
2203 #define UV3H_LB_BAU_MISC_CONTROL_32 0xa10
2204 #define UV4H_LB_BAU_MISC_CONTROL_32 0xa18
2205 #define UVH_LB_BAU_MISC_CONTROL_32 (					\
2206 	is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_32 :			\
2207 	is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_32 :			\
2208 	is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_32 :			\
2209 	/*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_32)
2210 
2211 #define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT	0
2212 #define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT		8
2213 #define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT	9
2214 #define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT	10
2215 #define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
2216 #define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
2217 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
2218 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
2219 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
2220 #define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
2221 #define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
2222 #define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
2223 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
2224 #define UVH_LB_BAU_MISC_CONTROL_FUN_SHFT		48
2225 #define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK	0x00000000000000ffUL
2226 #define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK		0x0000000000000100UL
2227 #define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK	0x0000000000000200UL
2228 #define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK	0x0000000000000400UL
2229 #define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
2230 #define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
2231 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
2232 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
2233 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
2234 #define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
2235 #define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
2236 #define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
2237 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
2238 #define UVH_LB_BAU_MISC_CONTROL_FUN_MASK		0xffff000000000000UL
2239 
2240 #define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT	0
2241 #define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT		8
2242 #define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT	9
2243 #define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT	10
2244 #define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
2245 #define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
2246 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
2247 #define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
2248 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
2249 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
2250 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
2251 #define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
2252 #define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
2253 #define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
2254 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
2255 #define UV1H_LB_BAU_MISC_CONTROL_FUN_SHFT		48
2256 #define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK	0x00000000000000ffUL
2257 #define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK		0x0000000000000100UL
2258 #define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK	0x0000000000000200UL
2259 #define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK	0x0000000000000400UL
2260 #define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
2261 #define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
2262 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
2263 #define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
2264 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
2265 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
2266 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
2267 #define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
2268 #define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
2269 #define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
2270 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
2271 #define UV1H_LB_BAU_MISC_CONTROL_FUN_MASK		0xffff000000000000UL
2272 
2273 #define UVXH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT	0
2274 #define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT		8
2275 #define UVXH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT	9
2276 #define UVXH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT	10
2277 #define UVXH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
2278 #define UVXH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
2279 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
2280 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
2281 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
2282 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
2283 #define UVXH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
2284 #define UVXH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
2285 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
2286 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29
2287 #define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT	30
2288 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31
2289 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32
2290 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33
2291 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34
2292 #define UVXH_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35
2293 #define UVXH_LB_BAU_MISC_CONTROL_FUN_SHFT		48
2294 #define UVXH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK	0x00000000000000ffUL
2295 #define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK		0x0000000000000100UL
2296 #define UVXH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK	0x0000000000000200UL
2297 #define UVXH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK	0x0000000000000400UL
2298 #define UVXH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
2299 #define UVXH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
2300 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
2301 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
2302 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
2303 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
2304 #define UVXH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
2305 #define UVXH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
2306 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
2307 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL
2308 #define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK	0x0000000040000000UL
2309 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL
2310 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL
2311 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL
2312 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL
2313 #define UVXH_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL
2314 #define UVXH_LB_BAU_MISC_CONTROL_FUN_MASK		0xffff000000000000UL
2315 
2316 #define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT	0
2317 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT		8
2318 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT	9
2319 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT	10
2320 #define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
2321 #define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
2322 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
2323 #define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
2324 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
2325 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
2326 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
2327 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
2328 #define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
2329 #define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
2330 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
2331 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29
2332 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT	30
2333 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31
2334 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32
2335 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33
2336 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34
2337 #define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35
2338 #define UV2H_LB_BAU_MISC_CONTROL_FUN_SHFT		48
2339 #define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK	0x00000000000000ffUL
2340 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK		0x0000000000000100UL
2341 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK	0x0000000000000200UL
2342 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK	0x0000000000000400UL
2343 #define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
2344 #define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
2345 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
2346 #define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
2347 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
2348 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
2349 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
2350 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
2351 #define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
2352 #define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
2353 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
2354 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL
2355 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK	0x0000000040000000UL
2356 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL
2357 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL
2358 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL
2359 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL
2360 #define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL
2361 #define UV2H_LB_BAU_MISC_CONTROL_FUN_MASK		0xffff000000000000UL
2362 
2363 #define UV3H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT	0
2364 #define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT		8
2365 #define UV3H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT	9
2366 #define UV3H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT	10
2367 #define UV3H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
2368 #define UV3H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
2369 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
2370 #define UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
2371 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
2372 #define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
2373 #define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
2374 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
2375 #define UV3H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
2376 #define UV3H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
2377 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
2378 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29
2379 #define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT	30
2380 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31
2381 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32
2382 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33
2383 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34
2384 #define UV3H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35
2385 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_SHFT 36
2386 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_PREFETCH_HINT_SHFT 37
2387 #define UV3H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_SHFT 38
2388 #define UV3H_LB_BAU_MISC_CONTROL_FUN_SHFT		48
2389 #define UV3H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK	0x00000000000000ffUL
2390 #define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK		0x0000000000000100UL
2391 #define UV3H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK	0x0000000000000200UL
2392 #define UV3H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK	0x0000000000000400UL
2393 #define UV3H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
2394 #define UV3H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
2395 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
2396 #define UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
2397 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
2398 #define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
2399 #define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
2400 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
2401 #define UV3H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
2402 #define UV3H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
2403 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
2404 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL
2405 #define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK	0x0000000040000000UL
2406 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL
2407 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL
2408 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL
2409 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL
2410 #define UV3H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL
2411 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_MASK 0x0000001000000000UL
2412 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_PREFETCH_HINT_MASK 0x0000002000000000UL
2413 #define UV3H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_MASK 0x00003fc000000000UL
2414 #define UV3H_LB_BAU_MISC_CONTROL_FUN_MASK		0xffff000000000000UL
2415 
2416 #define UV4H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT	0
2417 #define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT		8
2418 #define UV4H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT	9
2419 #define UV4H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT	10
2420 #define UV4H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
2421 #define UV4H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
2422 #define UV4H_LB_BAU_MISC_CONTROL_RESERVED_15_19_SHFT	15
2423 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
2424 #define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
2425 #define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
2426 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
2427 #define UV4H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
2428 #define UV4H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
2429 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
2430 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29
2431 #define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT	30
2432 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31
2433 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32
2434 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33
2435 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34
2436 #define UV4H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35
2437 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_SHFT 36
2438 #define UV4H_LB_BAU_MISC_CONTROL_RESERVED_37_SHFT	37
2439 #define UV4H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_SHFT 38
2440 #define UV4H_LB_BAU_MISC_CONTROL_ADDRESS_INTERLEAVE_SELECT_SHFT 46
2441 #define UV4H_LB_BAU_MISC_CONTROL_FUN_SHFT		48
2442 #define UV4H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK	0x00000000000000ffUL
2443 #define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK		0x0000000000000100UL
2444 #define UV4H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK	0x0000000000000200UL
2445 #define UV4H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK	0x0000000000000400UL
2446 #define UV4H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
2447 #define UV4H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
2448 #define UV4H_LB_BAU_MISC_CONTROL_RESERVED_15_19_MASK	0x00000000000f8000UL
2449 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
2450 #define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
2451 #define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
2452 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
2453 #define UV4H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
2454 #define UV4H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
2455 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
2456 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL
2457 #define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK	0x0000000040000000UL
2458 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL
2459 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL
2460 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL
2461 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL
2462 #define UV4H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL
2463 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_MASK 0x0000001000000000UL
2464 #define UV4H_LB_BAU_MISC_CONTROL_RESERVED_37_MASK	0x0000002000000000UL
2465 #define UV4H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_MASK 0x00003fc000000000UL
2466 #define UV4H_LB_BAU_MISC_CONTROL_ADDRESS_INTERLEAVE_SELECT_MASK 0x0000400000000000UL
2467 #define UV4H_LB_BAU_MISC_CONTROL_FUN_MASK		0xffff000000000000UL
2468 
2469 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK	\
2470 	uv_undefined("UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK")
2471 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK (	\
2472 	is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK : \
2473 	is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK : \
2474 	is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK : \
2475 	/*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK)
2476 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT	\
2477 	uv_undefined("UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT")
2478 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT (	\
2479 	is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT : \
2480 	is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT : \
2481 	is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT : \
2482 	/*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT)
2483 #define UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK	\
2484 	uv_undefined("UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK")
2485 #define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK (	\
2486 	is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK : \
2487 	is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK : \
2488 	is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK : \
2489 	/*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK)
2490 #define UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT	\
2491 	uv_undefined("UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT")
2492 #define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT (	\
2493 	is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT : \
2494 	is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT : \
2495 	is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT : \
2496 	/*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT)
2497 
2498 union uvh_lb_bau_misc_control_u {
2499 	unsigned long	v;
2500 	struct uvh_lb_bau_misc_control_s {
2501 		unsigned long	rejection_delay:8;		/* RW */
2502 		unsigned long	apic_mode:1;			/* RW */
2503 		unsigned long	force_broadcast:1;		/* RW */
2504 		unsigned long	force_lock_nop:1;		/* RW */
2505 		unsigned long	qpi_agent_presence_vector:3;	/* RW */
2506 		unsigned long	descriptor_fetch_mode:1;	/* RW */
2507 		unsigned long	rsvd_15_19:5;
2508 		unsigned long	enable_dual_mapping_mode:1;	/* RW */
2509 		unsigned long	vga_io_port_decode_enable:1;	/* RW */
2510 		unsigned long	vga_io_port_16_bit_decode:1;	/* RW */
2511 		unsigned long	suppress_dest_registration:1;	/* RW */
2512 		unsigned long	programmed_initial_priority:3;	/* RW */
2513 		unsigned long	use_incoming_priority:1;	/* RW */
2514 		unsigned long	enable_programmed_initial_priority:1;/* RW */
2515 		unsigned long	rsvd_29_47:19;
2516 		unsigned long	fun:16;				/* RW */
2517 	} s;
2518 	struct uv1h_lb_bau_misc_control_s {
2519 		unsigned long	rejection_delay:8;		/* RW */
2520 		unsigned long	apic_mode:1;			/* RW */
2521 		unsigned long	force_broadcast:1;		/* RW */
2522 		unsigned long	force_lock_nop:1;		/* RW */
2523 		unsigned long	qpi_agent_presence_vector:3;	/* RW */
2524 		unsigned long	descriptor_fetch_mode:1;	/* RW */
2525 		unsigned long	enable_intd_soft_ack_mode:1;	/* RW */
2526 		unsigned long	intd_soft_ack_timeout_period:4;	/* RW */
2527 		unsigned long	enable_dual_mapping_mode:1;	/* RW */
2528 		unsigned long	vga_io_port_decode_enable:1;	/* RW */
2529 		unsigned long	vga_io_port_16_bit_decode:1;	/* RW */
2530 		unsigned long	suppress_dest_registration:1;	/* RW */
2531 		unsigned long	programmed_initial_priority:3;	/* RW */
2532 		unsigned long	use_incoming_priority:1;	/* RW */
2533 		unsigned long	enable_programmed_initial_priority:1;/* RW */
2534 		unsigned long	rsvd_29_47:19;
2535 		unsigned long	fun:16;				/* RW */
2536 	} s1;
2537 	struct uvxh_lb_bau_misc_control_s {
2538 		unsigned long	rejection_delay:8;		/* RW */
2539 		unsigned long	apic_mode:1;			/* RW */
2540 		unsigned long	force_broadcast:1;		/* RW */
2541 		unsigned long	force_lock_nop:1;		/* RW */
2542 		unsigned long	qpi_agent_presence_vector:3;	/* RW */
2543 		unsigned long	descriptor_fetch_mode:1;	/* RW */
2544 		unsigned long	rsvd_15_19:5;
2545 		unsigned long	enable_dual_mapping_mode:1;	/* RW */
2546 		unsigned long	vga_io_port_decode_enable:1;	/* RW */
2547 		unsigned long	vga_io_port_16_bit_decode:1;	/* RW */
2548 		unsigned long	suppress_dest_registration:1;	/* RW */
2549 		unsigned long	programmed_initial_priority:3;	/* RW */
2550 		unsigned long	use_incoming_priority:1;	/* RW */
2551 		unsigned long	enable_programmed_initial_priority:1;/* RW */
2552 		unsigned long	enable_automatic_apic_mode_selection:1;/* RW */
2553 		unsigned long	apic_mode_status:1;		/* RO */
2554 		unsigned long	suppress_interrupts_to_self:1;	/* RW */
2555 		unsigned long	enable_lock_based_system_flush:1;/* RW */
2556 		unsigned long	enable_extended_sb_status:1;	/* RW */
2557 		unsigned long	suppress_int_prio_udt_to_self:1;/* RW */
2558 		unsigned long	use_legacy_descriptor_formats:1;/* RW */
2559 		unsigned long	rsvd_36_47:12;
2560 		unsigned long	fun:16;				/* RW */
2561 	} sx;
2562 	struct uv2h_lb_bau_misc_control_s {
2563 		unsigned long	rejection_delay:8;		/* RW */
2564 		unsigned long	apic_mode:1;			/* RW */
2565 		unsigned long	force_broadcast:1;		/* RW */
2566 		unsigned long	force_lock_nop:1;		/* RW */
2567 		unsigned long	qpi_agent_presence_vector:3;	/* RW */
2568 		unsigned long	descriptor_fetch_mode:1;	/* RW */
2569 		unsigned long	enable_intd_soft_ack_mode:1;	/* RW */
2570 		unsigned long	intd_soft_ack_timeout_period:4;	/* RW */
2571 		unsigned long	enable_dual_mapping_mode:1;	/* RW */
2572 		unsigned long	vga_io_port_decode_enable:1;	/* RW */
2573 		unsigned long	vga_io_port_16_bit_decode:1;	/* RW */
2574 		unsigned long	suppress_dest_registration:1;	/* RW */
2575 		unsigned long	programmed_initial_priority:3;	/* RW */
2576 		unsigned long	use_incoming_priority:1;	/* RW */
2577 		unsigned long	enable_programmed_initial_priority:1;/* RW */
2578 		unsigned long	enable_automatic_apic_mode_selection:1;/* RW */
2579 		unsigned long	apic_mode_status:1;		/* RO */
2580 		unsigned long	suppress_interrupts_to_self:1;	/* RW */
2581 		unsigned long	enable_lock_based_system_flush:1;/* RW */
2582 		unsigned long	enable_extended_sb_status:1;	/* RW */
2583 		unsigned long	suppress_int_prio_udt_to_self:1;/* RW */
2584 		unsigned long	use_legacy_descriptor_formats:1;/* RW */
2585 		unsigned long	rsvd_36_47:12;
2586 		unsigned long	fun:16;				/* RW */
2587 	} s2;
2588 	struct uv3h_lb_bau_misc_control_s {
2589 		unsigned long	rejection_delay:8;		/* RW */
2590 		unsigned long	apic_mode:1;			/* RW */
2591 		unsigned long	force_broadcast:1;		/* RW */
2592 		unsigned long	force_lock_nop:1;		/* RW */
2593 		unsigned long	qpi_agent_presence_vector:3;	/* RW */
2594 		unsigned long	descriptor_fetch_mode:1;	/* RW */
2595 		unsigned long	enable_intd_soft_ack_mode:1;	/* RW */
2596 		unsigned long	intd_soft_ack_timeout_period:4;	/* RW */
2597 		unsigned long	enable_dual_mapping_mode:1;	/* RW */
2598 		unsigned long	vga_io_port_decode_enable:1;	/* RW */
2599 		unsigned long	vga_io_port_16_bit_decode:1;	/* RW */
2600 		unsigned long	suppress_dest_registration:1;	/* RW */
2601 		unsigned long	programmed_initial_priority:3;	/* RW */
2602 		unsigned long	use_incoming_priority:1;	/* RW */
2603 		unsigned long	enable_programmed_initial_priority:1;/* RW */
2604 		unsigned long	enable_automatic_apic_mode_selection:1;/* RW */
2605 		unsigned long	apic_mode_status:1;		/* RO */
2606 		unsigned long	suppress_interrupts_to_self:1;	/* RW */
2607 		unsigned long	enable_lock_based_system_flush:1;/* RW */
2608 		unsigned long	enable_extended_sb_status:1;	/* RW */
2609 		unsigned long	suppress_int_prio_udt_to_self:1;/* RW */
2610 		unsigned long	use_legacy_descriptor_formats:1;/* RW */
2611 		unsigned long	suppress_quiesce_msgs_to_qpi:1;	/* RW */
2612 		unsigned long	enable_intd_prefetch_hint:1;	/* RW */
2613 		unsigned long	thread_kill_timebase:8;		/* RW */
2614 		unsigned long	rsvd_46_47:2;
2615 		unsigned long	fun:16;				/* RW */
2616 	} s3;
2617 	struct uv4h_lb_bau_misc_control_s {
2618 		unsigned long	rejection_delay:8;		/* RW */
2619 		unsigned long	apic_mode:1;			/* RW */
2620 		unsigned long	force_broadcast:1;		/* RW */
2621 		unsigned long	force_lock_nop:1;		/* RW */
2622 		unsigned long	qpi_agent_presence_vector:3;	/* RW */
2623 		unsigned long	descriptor_fetch_mode:1;	/* RW */
2624 		unsigned long	rsvd_15_19:5;
2625 		unsigned long	enable_dual_mapping_mode:1;	/* RW */
2626 		unsigned long	vga_io_port_decode_enable:1;	/* RW */
2627 		unsigned long	vga_io_port_16_bit_decode:1;	/* RW */
2628 		unsigned long	suppress_dest_registration:1;	/* RW */
2629 		unsigned long	programmed_initial_priority:3;	/* RW */
2630 		unsigned long	use_incoming_priority:1;	/* RW */
2631 		unsigned long	enable_programmed_initial_priority:1;/* RW */
2632 		unsigned long	enable_automatic_apic_mode_selection:1;/* RW */
2633 		unsigned long	apic_mode_status:1;		/* RO */
2634 		unsigned long	suppress_interrupts_to_self:1;	/* RW */
2635 		unsigned long	enable_lock_based_system_flush:1;/* RW */
2636 		unsigned long	enable_extended_sb_status:1;	/* RW */
2637 		unsigned long	suppress_int_prio_udt_to_self:1;/* RW */
2638 		unsigned long	use_legacy_descriptor_formats:1;/* RW */
2639 		unsigned long	suppress_quiesce_msgs_to_qpi:1;	/* RW */
2640 		unsigned long	rsvd_37:1;
2641 		unsigned long	thread_kill_timebase:8;		/* RW */
2642 		unsigned long	address_interleave_select:1;	/* RW */
2643 		unsigned long	rsvd_47:1;
2644 		unsigned long	fun:16;				/* RW */
2645 	} s4;
2646 };
2647 
2648 /* ========================================================================= */
2649 /*                     UVH_LB_BAU_SB_ACTIVATION_CONTROL                      */
2650 /* ========================================================================= */
2651 #define UV1H_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
2652 #define UV2H_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
2653 #define UV3H_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
2654 #define UV4H_LB_BAU_SB_ACTIVATION_CONTROL 0xc8020UL
2655 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL (				\
2656 	is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_CONTROL :		\
2657 	is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_CONTROL :		\
2658 	is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_CONTROL :		\
2659 	/*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_CONTROL)
2660 
2661 #define UV1H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8
2662 #define UV2H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8
2663 #define UV3H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8
2664 #define UV4H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9c8
2665 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 (				\
2666 	is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_CONTROL_32 :		\
2667 	is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_CONTROL_32 :		\
2668 	is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_CONTROL_32 :		\
2669 	/*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_CONTROL_32)
2670 
2671 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT	0
2672 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT	62
2673 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT	63
2674 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK	0x000000000000003fUL
2675 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK	0x4000000000000000UL
2676 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK	0x8000000000000000UL
2677 
2678 
2679 union uvh_lb_bau_sb_activation_control_u {
2680 	unsigned long	v;
2681 	struct uvh_lb_bau_sb_activation_control_s {
2682 		unsigned long	index:6;			/* RW */
2683 		unsigned long	rsvd_6_61:56;
2684 		unsigned long	push:1;				/* WP */
2685 		unsigned long	init:1;				/* WP */
2686 	} s;
2687 };
2688 
2689 /* ========================================================================= */
2690 /*                    UVH_LB_BAU_SB_ACTIVATION_STATUS_0                      */
2691 /* ========================================================================= */
2692 #define UV1H_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
2693 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
2694 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
2695 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_0 0xc8030UL
2696 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 (				\
2697 	is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_STATUS_0 :		\
2698 	is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_0 :		\
2699 	is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_0 :		\
2700 	/*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_0)
2701 
2702 #define UV1H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0
2703 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0
2704 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0
2705 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9d0
2706 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 (				\
2707 	is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_STATUS_0_32 :		\
2708 	is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_0_32 :		\
2709 	is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_0_32 :		\
2710 	/*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_0_32)
2711 
2712 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT	0
2713 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK	0xffffffffffffffffUL
2714 
2715 
2716 union uvh_lb_bau_sb_activation_status_0_u {
2717 	unsigned long	v;
2718 	struct uvh_lb_bau_sb_activation_status_0_s {
2719 		unsigned long	status:64;			/* RW */
2720 	} s;
2721 };
2722 
2723 /* ========================================================================= */
2724 /*                    UVH_LB_BAU_SB_ACTIVATION_STATUS_1                      */
2725 /* ========================================================================= */
2726 #define UV1H_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
2727 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
2728 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
2729 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_1 0xc8040UL
2730 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 (				\
2731 	is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_STATUS_1 :		\
2732 	is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_1 :		\
2733 	is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_1 :		\
2734 	/*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_1)
2735 
2736 #define UV1H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8
2737 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8
2738 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8
2739 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9d8
2740 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 (				\
2741 	is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_STATUS_1_32 :		\
2742 	is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_1_32 :		\
2743 	is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_1_32 :		\
2744 	/*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_1_32)
2745 
2746 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT	0
2747 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK	0xffffffffffffffffUL
2748 
2749 
2750 union uvh_lb_bau_sb_activation_status_1_u {
2751 	unsigned long	v;
2752 	struct uvh_lb_bau_sb_activation_status_1_s {
2753 		unsigned long	status:64;			/* RW */
2754 	} s;
2755 };
2756 
2757 /* ========================================================================= */
2758 /*                      UVH_LB_BAU_SB_DESCRIPTOR_BASE                        */
2759 /* ========================================================================= */
2760 #define UV1H_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
2761 #define UV2H_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
2762 #define UV3H_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
2763 #define UV4H_LB_BAU_SB_DESCRIPTOR_BASE 0xc8010UL
2764 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE (					\
2765 	is_uv1_hub() ? UV1H_LB_BAU_SB_DESCRIPTOR_BASE :			\
2766 	is_uv2_hub() ? UV2H_LB_BAU_SB_DESCRIPTOR_BASE :			\
2767 	is_uv3_hub() ? UV3H_LB_BAU_SB_DESCRIPTOR_BASE :			\
2768 	/*is_uv4_hub*/ UV4H_LB_BAU_SB_DESCRIPTOR_BASE)
2769 
2770 #define UV1H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0
2771 #define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0
2772 #define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0
2773 #define UV4H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9c0
2774 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 (				\
2775 	is_uv1_hub() ? UV1H_LB_BAU_SB_DESCRIPTOR_BASE_32 :		\
2776 	is_uv2_hub() ? UV2H_LB_BAU_SB_DESCRIPTOR_BASE_32 :		\
2777 	is_uv3_hub() ? UV3H_LB_BAU_SB_DESCRIPTOR_BASE_32 :		\
2778 	/*is_uv4_hub*/ UV4H_LB_BAU_SB_DESCRIPTOR_BASE_32)
2779 
2780 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT	12
2781 
2782 #define UV1H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT	49
2783 #define UV1H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
2784 #define UV1H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK	0x7ffe000000000000UL
2785 
2786 #define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT	49
2787 #define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
2788 #define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK	0x7ffe000000000000UL
2789 
2790 #define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT	49
2791 #define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
2792 #define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK	0x7ffe000000000000UL
2793 
2794 #define UV4H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT	49
2795 #define UV4H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x00003ffffffff000UL
2796 #define UV4H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK	0x7ffe000000000000UL
2797 
2798 #define UV4AH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT	53
2799 #define UV4AH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000ffffffffff000UL
2800 #define UV4AH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK	0xffe0000000000000UL
2801 
2802 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT (			\
2803 	is_uv1_hub() ? UV1H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT :	\
2804 	is_uv2_hub() ? UV2H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT :	\
2805 	is_uv3_hub() ? UV3H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT :	\
2806 	is_uv4a_hub() ? UV4AH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT :	\
2807 	/*is_uv4_hub*/ UV4H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT)
2808 
2809 #define UVH_LB_BAU_SB_DESCRIPTOR_PAGE_ADDRESS_MASK (			\
2810 	is_uv1_hub() ? UV1H_LB_BAU_SB_DESCRIPTOR_PAGE_ADDRESS_MASK :	\
2811 	is_uv2_hub() ? UV2H_LB_BAU_SB_DESCRIPTOR_PAGE_ADDRESS_MASK :	\
2812 	is_uv3_hub() ? UV3H_LB_BAU_SB_DESCRIPTOR_PAGE_ADDRESS_MASK :	\
2813 	is_uv4a_hub() ? UV4AH_LB_BAU_SB_DESCRIPTOR_PAGE_ADDRESS_MASK :	\
2814 	/*is_uv4_hub*/ UV4H_LB_BAU_SB_DESCRIPTOR_PAGE_ADDRESS_MASK)
2815 
2816 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK (			\
2817 	is_uv1_hub() ? UV1H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK :	\
2818 	is_uv2_hub() ? UV2H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK :	\
2819 	is_uv3_hub() ? UV3H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK :	\
2820 	is_uv4a_hub() ? UV4AH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK :	\
2821 	/*is_uv4_hub*/ UV4H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK)
2822 
2823 /* ========================================================================= */
2824 /*                               UVH_NODE_ID                                 */
2825 /* ========================================================================= */
2826 #define UVH_NODE_ID 0x0UL
2827 #define UV1H_NODE_ID 0x0UL
2828 #define UV2H_NODE_ID 0x0UL
2829 #define UV3H_NODE_ID 0x0UL
2830 #define UV4H_NODE_ID 0x0UL
2831 
2832 #define UVH_NODE_ID_FORCE1_SHFT				0
2833 #define UVH_NODE_ID_MANUFACTURER_SHFT			1
2834 #define UVH_NODE_ID_PART_NUMBER_SHFT			12
2835 #define UVH_NODE_ID_REVISION_SHFT			28
2836 #define UVH_NODE_ID_NODE_ID_SHFT			32
2837 #define UVH_NODE_ID_FORCE1_MASK				0x0000000000000001UL
2838 #define UVH_NODE_ID_MANUFACTURER_MASK			0x0000000000000ffeUL
2839 #define UVH_NODE_ID_PART_NUMBER_MASK			0x000000000ffff000UL
2840 #define UVH_NODE_ID_REVISION_MASK			0x00000000f0000000UL
2841 #define UVH_NODE_ID_NODE_ID_MASK			0x00007fff00000000UL
2842 
2843 #define UV1H_NODE_ID_FORCE1_SHFT			0
2844 #define UV1H_NODE_ID_MANUFACTURER_SHFT			1
2845 #define UV1H_NODE_ID_PART_NUMBER_SHFT			12
2846 #define UV1H_NODE_ID_REVISION_SHFT			28
2847 #define UV1H_NODE_ID_NODE_ID_SHFT			32
2848 #define UV1H_NODE_ID_NODES_PER_BIT_SHFT			48
2849 #define UV1H_NODE_ID_NI_PORT_SHFT			56
2850 #define UV1H_NODE_ID_FORCE1_MASK			0x0000000000000001UL
2851 #define UV1H_NODE_ID_MANUFACTURER_MASK			0x0000000000000ffeUL
2852 #define UV1H_NODE_ID_PART_NUMBER_MASK			0x000000000ffff000UL
2853 #define UV1H_NODE_ID_REVISION_MASK			0x00000000f0000000UL
2854 #define UV1H_NODE_ID_NODE_ID_MASK			0x00007fff00000000UL
2855 #define UV1H_NODE_ID_NODES_PER_BIT_MASK			0x007f000000000000UL
2856 #define UV1H_NODE_ID_NI_PORT_MASK			0x0f00000000000000UL
2857 
2858 #define UVXH_NODE_ID_FORCE1_SHFT			0
2859 #define UVXH_NODE_ID_MANUFACTURER_SHFT			1
2860 #define UVXH_NODE_ID_PART_NUMBER_SHFT			12
2861 #define UVXH_NODE_ID_REVISION_SHFT			28
2862 #define UVXH_NODE_ID_NODE_ID_SHFT			32
2863 #define UVXH_NODE_ID_NODES_PER_BIT_SHFT			50
2864 #define UVXH_NODE_ID_NI_PORT_SHFT			57
2865 #define UVXH_NODE_ID_FORCE1_MASK			0x0000000000000001UL
2866 #define UVXH_NODE_ID_MANUFACTURER_MASK			0x0000000000000ffeUL
2867 #define UVXH_NODE_ID_PART_NUMBER_MASK			0x000000000ffff000UL
2868 #define UVXH_NODE_ID_REVISION_MASK			0x00000000f0000000UL
2869 #define UVXH_NODE_ID_NODE_ID_MASK			0x00007fff00000000UL
2870 #define UVXH_NODE_ID_NODES_PER_BIT_MASK			0x01fc000000000000UL
2871 #define UVXH_NODE_ID_NI_PORT_MASK			0x3e00000000000000UL
2872 
2873 #define UV2H_NODE_ID_FORCE1_SHFT			0
2874 #define UV2H_NODE_ID_MANUFACTURER_SHFT			1
2875 #define UV2H_NODE_ID_PART_NUMBER_SHFT			12
2876 #define UV2H_NODE_ID_REVISION_SHFT			28
2877 #define UV2H_NODE_ID_NODE_ID_SHFT			32
2878 #define UV2H_NODE_ID_NODES_PER_BIT_SHFT			50
2879 #define UV2H_NODE_ID_NI_PORT_SHFT			57
2880 #define UV2H_NODE_ID_FORCE1_MASK			0x0000000000000001UL
2881 #define UV2H_NODE_ID_MANUFACTURER_MASK			0x0000000000000ffeUL
2882 #define UV2H_NODE_ID_PART_NUMBER_MASK			0x000000000ffff000UL
2883 #define UV2H_NODE_ID_REVISION_MASK			0x00000000f0000000UL
2884 #define UV2H_NODE_ID_NODE_ID_MASK			0x00007fff00000000UL
2885 #define UV2H_NODE_ID_NODES_PER_BIT_MASK			0x01fc000000000000UL
2886 #define UV2H_NODE_ID_NI_PORT_MASK			0x3e00000000000000UL
2887 
2888 #define UV3H_NODE_ID_FORCE1_SHFT			0
2889 #define UV3H_NODE_ID_MANUFACTURER_SHFT			1
2890 #define UV3H_NODE_ID_PART_NUMBER_SHFT			12
2891 #define UV3H_NODE_ID_REVISION_SHFT			28
2892 #define UV3H_NODE_ID_NODE_ID_SHFT			32
2893 #define UV3H_NODE_ID_ROUTER_SELECT_SHFT			48
2894 #define UV3H_NODE_ID_RESERVED_2_SHFT			49
2895 #define UV3H_NODE_ID_NODES_PER_BIT_SHFT			50
2896 #define UV3H_NODE_ID_NI_PORT_SHFT			57
2897 #define UV3H_NODE_ID_FORCE1_MASK			0x0000000000000001UL
2898 #define UV3H_NODE_ID_MANUFACTURER_MASK			0x0000000000000ffeUL
2899 #define UV3H_NODE_ID_PART_NUMBER_MASK			0x000000000ffff000UL
2900 #define UV3H_NODE_ID_REVISION_MASK			0x00000000f0000000UL
2901 #define UV3H_NODE_ID_NODE_ID_MASK			0x00007fff00000000UL
2902 #define UV3H_NODE_ID_ROUTER_SELECT_MASK			0x0001000000000000UL
2903 #define UV3H_NODE_ID_RESERVED_2_MASK			0x0002000000000000UL
2904 #define UV3H_NODE_ID_NODES_PER_BIT_MASK			0x01fc000000000000UL
2905 #define UV3H_NODE_ID_NI_PORT_MASK			0x3e00000000000000UL
2906 
2907 #define UV4H_NODE_ID_FORCE1_SHFT			0
2908 #define UV4H_NODE_ID_MANUFACTURER_SHFT			1
2909 #define UV4H_NODE_ID_PART_NUMBER_SHFT			12
2910 #define UV4H_NODE_ID_REVISION_SHFT			28
2911 #define UV4H_NODE_ID_NODE_ID_SHFT			32
2912 #define UV4H_NODE_ID_ROUTER_SELECT_SHFT			48
2913 #define UV4H_NODE_ID_RESERVED_2_SHFT			49
2914 #define UV4H_NODE_ID_NODES_PER_BIT_SHFT			50
2915 #define UV4H_NODE_ID_NI_PORT_SHFT			57
2916 #define UV4H_NODE_ID_FORCE1_MASK			0x0000000000000001UL
2917 #define UV4H_NODE_ID_MANUFACTURER_MASK			0x0000000000000ffeUL
2918 #define UV4H_NODE_ID_PART_NUMBER_MASK			0x000000000ffff000UL
2919 #define UV4H_NODE_ID_REVISION_MASK			0x00000000f0000000UL
2920 #define UV4H_NODE_ID_NODE_ID_MASK			0x00007fff00000000UL
2921 #define UV4H_NODE_ID_ROUTER_SELECT_MASK			0x0001000000000000UL
2922 #define UV4H_NODE_ID_RESERVED_2_MASK			0x0002000000000000UL
2923 #define UV4H_NODE_ID_NODES_PER_BIT_MASK			0x01fc000000000000UL
2924 #define UV4H_NODE_ID_NI_PORT_MASK			0x3e00000000000000UL
2925 
2926 
2927 union uvh_node_id_u {
2928 	unsigned long	v;
2929 	struct uvh_node_id_s {
2930 		unsigned long	force1:1;			/* RO */
2931 		unsigned long	manufacturer:11;		/* RO */
2932 		unsigned long	part_number:16;			/* RO */
2933 		unsigned long	revision:4;			/* RO */
2934 		unsigned long	node_id:15;			/* RW */
2935 		unsigned long	rsvd_47_63:17;
2936 	} s;
2937 	struct uv1h_node_id_s {
2938 		unsigned long	force1:1;			/* RO */
2939 		unsigned long	manufacturer:11;		/* RO */
2940 		unsigned long	part_number:16;			/* RO */
2941 		unsigned long	revision:4;			/* RO */
2942 		unsigned long	node_id:15;			/* RW */
2943 		unsigned long	rsvd_47:1;
2944 		unsigned long	nodes_per_bit:7;		/* RW */
2945 		unsigned long	rsvd_55:1;
2946 		unsigned long	ni_port:4;			/* RO */
2947 		unsigned long	rsvd_60_63:4;
2948 	} s1;
2949 	struct uvxh_node_id_s {
2950 		unsigned long	force1:1;			/* RO */
2951 		unsigned long	manufacturer:11;		/* RO */
2952 		unsigned long	part_number:16;			/* RO */
2953 		unsigned long	revision:4;			/* RO */
2954 		unsigned long	node_id:15;			/* RW */
2955 		unsigned long	rsvd_47_49:3;
2956 		unsigned long	nodes_per_bit:7;		/* RO */
2957 		unsigned long	ni_port:5;			/* RO */
2958 		unsigned long	rsvd_62_63:2;
2959 	} sx;
2960 	struct uv2h_node_id_s {
2961 		unsigned long	force1:1;			/* RO */
2962 		unsigned long	manufacturer:11;		/* RO */
2963 		unsigned long	part_number:16;			/* RO */
2964 		unsigned long	revision:4;			/* RO */
2965 		unsigned long	node_id:15;			/* RW */
2966 		unsigned long	rsvd_47_49:3;
2967 		unsigned long	nodes_per_bit:7;		/* RO */
2968 		unsigned long	ni_port:5;			/* RO */
2969 		unsigned long	rsvd_62_63:2;
2970 	} s2;
2971 	struct uv3h_node_id_s {
2972 		unsigned long	force1:1;			/* RO */
2973 		unsigned long	manufacturer:11;		/* RO */
2974 		unsigned long	part_number:16;			/* RO */
2975 		unsigned long	revision:4;			/* RO */
2976 		unsigned long	node_id:15;			/* RW */
2977 		unsigned long	rsvd_47:1;
2978 		unsigned long	router_select:1;		/* RO */
2979 		unsigned long	rsvd_49:1;
2980 		unsigned long	nodes_per_bit:7;		/* RO */
2981 		unsigned long	ni_port:5;			/* RO */
2982 		unsigned long	rsvd_62_63:2;
2983 	} s3;
2984 	struct uv4h_node_id_s {
2985 		unsigned long	force1:1;			/* RO */
2986 		unsigned long	manufacturer:11;		/* RO */
2987 		unsigned long	part_number:16;			/* RO */
2988 		unsigned long	revision:4;			/* RO */
2989 		unsigned long	node_id:15;			/* RW */
2990 		unsigned long	rsvd_47:1;
2991 		unsigned long	router_select:1;		/* RO */
2992 		unsigned long	rsvd_49:1;
2993 		unsigned long	nodes_per_bit:7;		/* RO */
2994 		unsigned long	ni_port:5;			/* RO */
2995 		unsigned long	rsvd_62_63:2;
2996 	} s4;
2997 };
2998 
2999 /* ========================================================================= */
3000 /*                          UVH_NODE_PRESENT_TABLE                           */
3001 /* ========================================================================= */
3002 #define UVH_NODE_PRESENT_TABLE 0x1400UL
3003 
3004 #define UV1H_NODE_PRESENT_TABLE_DEPTH 16
3005 #define UV2H_NODE_PRESENT_TABLE_DEPTH 16
3006 #define UV3H_NODE_PRESENT_TABLE_DEPTH 16
3007 #define UV4H_NODE_PRESENT_TABLE_DEPTH 4
3008 #define UVH_NODE_PRESENT_TABLE_DEPTH (					\
3009 	is_uv1_hub() ? UV1H_NODE_PRESENT_TABLE_DEPTH :			\
3010 	is_uv2_hub() ? UV2H_NODE_PRESENT_TABLE_DEPTH :			\
3011 	is_uv3_hub() ? UV3H_NODE_PRESENT_TABLE_DEPTH :			\
3012 	/*is_uv4_hub*/ UV4H_NODE_PRESENT_TABLE_DEPTH)
3013 
3014 #define UVH_NODE_PRESENT_TABLE_NODES_SHFT		0
3015 #define UVH_NODE_PRESENT_TABLE_NODES_MASK		0xffffffffffffffffUL
3016 
3017 
3018 union uvh_node_present_table_u {
3019 	unsigned long	v;
3020 	struct uvh_node_present_table_s {
3021 		unsigned long	nodes:64;			/* RW */
3022 	} s;
3023 };
3024 
3025 /* ========================================================================= */
3026 /*                 UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR                  */
3027 /* ========================================================================= */
3028 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL
3029 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL
3030 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL
3031 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x4800c8UL
3032 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR (			\
3033 	is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR :	\
3034 	is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR :	\
3035 	is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR :	\
3036 	/*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR)
3037 
3038 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
3039 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
3040 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
3041 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
3042 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
3043 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
3044 
3045 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
3046 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
3047 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
3048 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
3049 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
3050 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
3051 
3052 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
3053 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
3054 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
3055 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
3056 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
3057 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
3058 
3059 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
3060 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
3061 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
3062 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
3063 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
3064 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
3065 
3066 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
3067 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
3068 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
3069 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
3070 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
3071 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
3072 
3073 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
3074 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
3075 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
3076 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
3077 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
3078 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
3079 
3080 
3081 union uvh_rh_gam_alias210_overlay_config_0_mmr_u {
3082 	unsigned long	v;
3083 	struct uvh_rh_gam_alias210_overlay_config_0_mmr_s {
3084 		unsigned long	rsvd_0_23:24;
3085 		unsigned long	base:8;				/* RW */
3086 		unsigned long	rsvd_32_47:16;
3087 		unsigned long	m_alias:5;			/* RW */
3088 		unsigned long	rsvd_53_62:10;
3089 		unsigned long	enable:1;			/* RW */
3090 	} s;
3091 	struct uv1h_rh_gam_alias210_overlay_config_0_mmr_s {
3092 		unsigned long	rsvd_0_23:24;
3093 		unsigned long	base:8;				/* RW */
3094 		unsigned long	rsvd_32_47:16;
3095 		unsigned long	m_alias:5;			/* RW */
3096 		unsigned long	rsvd_53_62:10;
3097 		unsigned long	enable:1;			/* RW */
3098 	} s1;
3099 	struct uvxh_rh_gam_alias210_overlay_config_0_mmr_s {
3100 		unsigned long	rsvd_0_23:24;
3101 		unsigned long	base:8;				/* RW */
3102 		unsigned long	rsvd_32_47:16;
3103 		unsigned long	m_alias:5;			/* RW */
3104 		unsigned long	rsvd_53_62:10;
3105 		unsigned long	enable:1;			/* RW */
3106 	} sx;
3107 	struct uv2h_rh_gam_alias210_overlay_config_0_mmr_s {
3108 		unsigned long	rsvd_0_23:24;
3109 		unsigned long	base:8;				/* RW */
3110 		unsigned long	rsvd_32_47:16;
3111 		unsigned long	m_alias:5;			/* RW */
3112 		unsigned long	rsvd_53_62:10;
3113 		unsigned long	enable:1;			/* RW */
3114 	} s2;
3115 	struct uv3h_rh_gam_alias210_overlay_config_0_mmr_s {
3116 		unsigned long	rsvd_0_23:24;
3117 		unsigned long	base:8;				/* RW */
3118 		unsigned long	rsvd_32_47:16;
3119 		unsigned long	m_alias:5;			/* RW */
3120 		unsigned long	rsvd_53_62:10;
3121 		unsigned long	enable:1;			/* RW */
3122 	} s3;
3123 	struct uv4h_rh_gam_alias210_overlay_config_0_mmr_s {
3124 		unsigned long	rsvd_0_23:24;
3125 		unsigned long	base:8;				/* RW */
3126 		unsigned long	rsvd_32_47:16;
3127 		unsigned long	m_alias:5;			/* RW */
3128 		unsigned long	rsvd_53_62:10;
3129 		unsigned long	enable:1;			/* RW */
3130 	} s4;
3131 };
3132 
3133 /* ========================================================================= */
3134 /*                 UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR                  */
3135 /* ========================================================================= */
3136 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL
3137 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL
3138 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL
3139 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x4800d8UL
3140 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR (			\
3141 	is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR :	\
3142 	is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR :	\
3143 	is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR :	\
3144 	/*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR)
3145 
3146 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
3147 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
3148 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
3149 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
3150 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
3151 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
3152 
3153 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
3154 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
3155 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
3156 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
3157 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
3158 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
3159 
3160 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
3161 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
3162 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
3163 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
3164 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
3165 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
3166 
3167 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
3168 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
3169 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
3170 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
3171 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
3172 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
3173 
3174 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
3175 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
3176 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
3177 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
3178 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
3179 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
3180 
3181 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
3182 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
3183 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
3184 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
3185 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
3186 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
3187 
3188 
3189 union uvh_rh_gam_alias210_overlay_config_1_mmr_u {
3190 	unsigned long	v;
3191 	struct uvh_rh_gam_alias210_overlay_config_1_mmr_s {
3192 		unsigned long	rsvd_0_23:24;
3193 		unsigned long	base:8;				/* RW */
3194 		unsigned long	rsvd_32_47:16;
3195 		unsigned long	m_alias:5;			/* RW */
3196 		unsigned long	rsvd_53_62:10;
3197 		unsigned long	enable:1;			/* RW */
3198 	} s;
3199 	struct uv1h_rh_gam_alias210_overlay_config_1_mmr_s {
3200 		unsigned long	rsvd_0_23:24;
3201 		unsigned long	base:8;				/* RW */
3202 		unsigned long	rsvd_32_47:16;
3203 		unsigned long	m_alias:5;			/* RW */
3204 		unsigned long	rsvd_53_62:10;
3205 		unsigned long	enable:1;			/* RW */
3206 	} s1;
3207 	struct uvxh_rh_gam_alias210_overlay_config_1_mmr_s {
3208 		unsigned long	rsvd_0_23:24;
3209 		unsigned long	base:8;				/* RW */
3210 		unsigned long	rsvd_32_47:16;
3211 		unsigned long	m_alias:5;			/* RW */
3212 		unsigned long	rsvd_53_62:10;
3213 		unsigned long	enable:1;			/* RW */
3214 	} sx;
3215 	struct uv2h_rh_gam_alias210_overlay_config_1_mmr_s {
3216 		unsigned long	rsvd_0_23:24;
3217 		unsigned long	base:8;				/* RW */
3218 		unsigned long	rsvd_32_47:16;
3219 		unsigned long	m_alias:5;			/* RW */
3220 		unsigned long	rsvd_53_62:10;
3221 		unsigned long	enable:1;			/* RW */
3222 	} s2;
3223 	struct uv3h_rh_gam_alias210_overlay_config_1_mmr_s {
3224 		unsigned long	rsvd_0_23:24;
3225 		unsigned long	base:8;				/* RW */
3226 		unsigned long	rsvd_32_47:16;
3227 		unsigned long	m_alias:5;			/* RW */
3228 		unsigned long	rsvd_53_62:10;
3229 		unsigned long	enable:1;			/* RW */
3230 	} s3;
3231 	struct uv4h_rh_gam_alias210_overlay_config_1_mmr_s {
3232 		unsigned long	rsvd_0_23:24;
3233 		unsigned long	base:8;				/* RW */
3234 		unsigned long	rsvd_32_47:16;
3235 		unsigned long	m_alias:5;			/* RW */
3236 		unsigned long	rsvd_53_62:10;
3237 		unsigned long	enable:1;			/* RW */
3238 	} s4;
3239 };
3240 
3241 /* ========================================================================= */
3242 /*                 UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR                  */
3243 /* ========================================================================= */
3244 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL
3245 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL
3246 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL
3247 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x4800e8UL
3248 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR (			\
3249 	is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR :	\
3250 	is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR :	\
3251 	is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR :	\
3252 	/*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR)
3253 
3254 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
3255 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
3256 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
3257 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
3258 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
3259 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
3260 
3261 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
3262 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
3263 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
3264 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
3265 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
3266 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
3267 
3268 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
3269 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
3270 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
3271 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
3272 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
3273 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
3274 
3275 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
3276 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
3277 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
3278 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
3279 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
3280 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
3281 
3282 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
3283 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
3284 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
3285 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
3286 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
3287 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
3288 
3289 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
3290 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
3291 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
3292 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
3293 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
3294 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
3295 
3296 
3297 union uvh_rh_gam_alias210_overlay_config_2_mmr_u {
3298 	unsigned long	v;
3299 	struct uvh_rh_gam_alias210_overlay_config_2_mmr_s {
3300 		unsigned long	rsvd_0_23:24;
3301 		unsigned long	base:8;				/* RW */
3302 		unsigned long	rsvd_32_47:16;
3303 		unsigned long	m_alias:5;			/* RW */
3304 		unsigned long	rsvd_53_62:10;
3305 		unsigned long	enable:1;			/* RW */
3306 	} s;
3307 	struct uv1h_rh_gam_alias210_overlay_config_2_mmr_s {
3308 		unsigned long	rsvd_0_23:24;
3309 		unsigned long	base:8;				/* RW */
3310 		unsigned long	rsvd_32_47:16;
3311 		unsigned long	m_alias:5;			/* RW */
3312 		unsigned long	rsvd_53_62:10;
3313 		unsigned long	enable:1;			/* RW */
3314 	} s1;
3315 	struct uvxh_rh_gam_alias210_overlay_config_2_mmr_s {
3316 		unsigned long	rsvd_0_23:24;
3317 		unsigned long	base:8;				/* RW */
3318 		unsigned long	rsvd_32_47:16;
3319 		unsigned long	m_alias:5;			/* RW */
3320 		unsigned long	rsvd_53_62:10;
3321 		unsigned long	enable:1;			/* RW */
3322 	} sx;
3323 	struct uv2h_rh_gam_alias210_overlay_config_2_mmr_s {
3324 		unsigned long	rsvd_0_23:24;
3325 		unsigned long	base:8;				/* RW */
3326 		unsigned long	rsvd_32_47:16;
3327 		unsigned long	m_alias:5;			/* RW */
3328 		unsigned long	rsvd_53_62:10;
3329 		unsigned long	enable:1;			/* RW */
3330 	} s2;
3331 	struct uv3h_rh_gam_alias210_overlay_config_2_mmr_s {
3332 		unsigned long	rsvd_0_23:24;
3333 		unsigned long	base:8;				/* RW */
3334 		unsigned long	rsvd_32_47:16;
3335 		unsigned long	m_alias:5;			/* RW */
3336 		unsigned long	rsvd_53_62:10;
3337 		unsigned long	enable:1;			/* RW */
3338 	} s3;
3339 	struct uv4h_rh_gam_alias210_overlay_config_2_mmr_s {
3340 		unsigned long	rsvd_0_23:24;
3341 		unsigned long	base:8;				/* RW */
3342 		unsigned long	rsvd_32_47:16;
3343 		unsigned long	m_alias:5;			/* RW */
3344 		unsigned long	rsvd_53_62:10;
3345 		unsigned long	enable:1;			/* RW */
3346 	} s4;
3347 };
3348 
3349 /* ========================================================================= */
3350 /*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR                  */
3351 /* ========================================================================= */
3352 #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
3353 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
3354 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
3355 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x4800d0UL
3356 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR (			\
3357 	is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR :	\
3358 	is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR :	\
3359 	is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR :	\
3360 	/*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR)
3361 
3362 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
3363 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3364 
3365 #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
3366 #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3367 
3368 #define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
3369 #define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3370 
3371 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
3372 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3373 
3374 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
3375 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3376 
3377 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
3378 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3379 
3380 
3381 union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
3382 	unsigned long	v;
3383 	struct uvh_rh_gam_alias210_redirect_config_0_mmr_s {
3384 		unsigned long	rsvd_0_23:24;
3385 		unsigned long	dest_base:22;			/* RW */
3386 		unsigned long	rsvd_46_63:18;
3387 	} s;
3388 	struct uv1h_rh_gam_alias210_redirect_config_0_mmr_s {
3389 		unsigned long	rsvd_0_23:24;
3390 		unsigned long	dest_base:22;			/* RW */
3391 		unsigned long	rsvd_46_63:18;
3392 	} s1;
3393 	struct uvxh_rh_gam_alias210_redirect_config_0_mmr_s {
3394 		unsigned long	rsvd_0_23:24;
3395 		unsigned long	dest_base:22;			/* RW */
3396 		unsigned long	rsvd_46_63:18;
3397 	} sx;
3398 	struct uv2h_rh_gam_alias210_redirect_config_0_mmr_s {
3399 		unsigned long	rsvd_0_23:24;
3400 		unsigned long	dest_base:22;			/* RW */
3401 		unsigned long	rsvd_46_63:18;
3402 	} s2;
3403 	struct uv3h_rh_gam_alias210_redirect_config_0_mmr_s {
3404 		unsigned long	rsvd_0_23:24;
3405 		unsigned long	dest_base:22;			/* RW */
3406 		unsigned long	rsvd_46_63:18;
3407 	} s3;
3408 	struct uv4h_rh_gam_alias210_redirect_config_0_mmr_s {
3409 		unsigned long	rsvd_0_23:24;
3410 		unsigned long	dest_base:22;			/* RW */
3411 		unsigned long	rsvd_46_63:18;
3412 	} s4;
3413 };
3414 
3415 /* ========================================================================= */
3416 /*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR                  */
3417 /* ========================================================================= */
3418 #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
3419 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
3420 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
3421 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x4800e0UL
3422 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR (			\
3423 	is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR :	\
3424 	is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR :	\
3425 	is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR :	\
3426 	/*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR)
3427 
3428 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
3429 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3430 
3431 #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
3432 #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3433 
3434 #define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
3435 #define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3436 
3437 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
3438 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3439 
3440 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
3441 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3442 
3443 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
3444 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3445 
3446 
3447 union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
3448 	unsigned long	v;
3449 	struct uvh_rh_gam_alias210_redirect_config_1_mmr_s {
3450 		unsigned long	rsvd_0_23:24;
3451 		unsigned long	dest_base:22;			/* RW */
3452 		unsigned long	rsvd_46_63:18;
3453 	} s;
3454 	struct uv1h_rh_gam_alias210_redirect_config_1_mmr_s {
3455 		unsigned long	rsvd_0_23:24;
3456 		unsigned long	dest_base:22;			/* RW */
3457 		unsigned long	rsvd_46_63:18;
3458 	} s1;
3459 	struct uvxh_rh_gam_alias210_redirect_config_1_mmr_s {
3460 		unsigned long	rsvd_0_23:24;
3461 		unsigned long	dest_base:22;			/* RW */
3462 		unsigned long	rsvd_46_63:18;
3463 	} sx;
3464 	struct uv2h_rh_gam_alias210_redirect_config_1_mmr_s {
3465 		unsigned long	rsvd_0_23:24;
3466 		unsigned long	dest_base:22;			/* RW */
3467 		unsigned long	rsvd_46_63:18;
3468 	} s2;
3469 	struct uv3h_rh_gam_alias210_redirect_config_1_mmr_s {
3470 		unsigned long	rsvd_0_23:24;
3471 		unsigned long	dest_base:22;			/* RW */
3472 		unsigned long	rsvd_46_63:18;
3473 	} s3;
3474 	struct uv4h_rh_gam_alias210_redirect_config_1_mmr_s {
3475 		unsigned long	rsvd_0_23:24;
3476 		unsigned long	dest_base:22;			/* RW */
3477 		unsigned long	rsvd_46_63:18;
3478 	} s4;
3479 };
3480 
3481 /* ========================================================================= */
3482 /*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR                  */
3483 /* ========================================================================= */
3484 #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
3485 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
3486 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
3487 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x4800f0UL
3488 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR (			\
3489 	is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR :	\
3490 	is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR :	\
3491 	is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR :	\
3492 	/*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR)
3493 
3494 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
3495 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3496 
3497 #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
3498 #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3499 
3500 #define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
3501 #define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3502 
3503 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
3504 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3505 
3506 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
3507 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3508 
3509 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
3510 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
3511 
3512 
3513 union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
3514 	unsigned long	v;
3515 	struct uvh_rh_gam_alias210_redirect_config_2_mmr_s {
3516 		unsigned long	rsvd_0_23:24;
3517 		unsigned long	dest_base:22;			/* RW */
3518 		unsigned long	rsvd_46_63:18;
3519 	} s;
3520 	struct uv1h_rh_gam_alias210_redirect_config_2_mmr_s {
3521 		unsigned long	rsvd_0_23:24;
3522 		unsigned long	dest_base:22;			/* RW */
3523 		unsigned long	rsvd_46_63:18;
3524 	} s1;
3525 	struct uvxh_rh_gam_alias210_redirect_config_2_mmr_s {
3526 		unsigned long	rsvd_0_23:24;
3527 		unsigned long	dest_base:22;			/* RW */
3528 		unsigned long	rsvd_46_63:18;
3529 	} sx;
3530 	struct uv2h_rh_gam_alias210_redirect_config_2_mmr_s {
3531 		unsigned long	rsvd_0_23:24;
3532 		unsigned long	dest_base:22;			/* RW */
3533 		unsigned long	rsvd_46_63:18;
3534 	} s2;
3535 	struct uv3h_rh_gam_alias210_redirect_config_2_mmr_s {
3536 		unsigned long	rsvd_0_23:24;
3537 		unsigned long	dest_base:22;			/* RW */
3538 		unsigned long	rsvd_46_63:18;
3539 	} s3;
3540 	struct uv4h_rh_gam_alias210_redirect_config_2_mmr_s {
3541 		unsigned long	rsvd_0_23:24;
3542 		unsigned long	dest_base:22;			/* RW */
3543 		unsigned long	rsvd_46_63:18;
3544 	} s4;
3545 };
3546 
3547 /* ========================================================================= */
3548 /*                          UVH_RH_GAM_CONFIG_MMR                            */
3549 /* ========================================================================= */
3550 #define UV1H_RH_GAM_CONFIG_MMR 0x1600000UL
3551 #define UV2H_RH_GAM_CONFIG_MMR 0x1600000UL
3552 #define UV3H_RH_GAM_CONFIG_MMR 0x1600000UL
3553 #define UV4H_RH_GAM_CONFIG_MMR 0x480000UL
3554 #define UVH_RH_GAM_CONFIG_MMR (						\
3555 	is_uv1_hub() ? UV1H_RH_GAM_CONFIG_MMR :				\
3556 	is_uv2_hub() ? UV2H_RH_GAM_CONFIG_MMR :				\
3557 	is_uv3_hub() ? UV3H_RH_GAM_CONFIG_MMR :				\
3558 	/*is_uv4_hub*/ UV4H_RH_GAM_CONFIG_MMR)
3559 
3560 #define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT		6
3561 #define UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK		0x00000000000003c0UL
3562 
3563 #define UV1H_RH_GAM_CONFIG_MMR_M_SKT_SHFT		0
3564 #define UV1H_RH_GAM_CONFIG_MMR_N_SKT_SHFT		6
3565 #define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_SHFT		12
3566 #define UV1H_RH_GAM_CONFIG_MMR_M_SKT_MASK		0x000000000000003fUL
3567 #define UV1H_RH_GAM_CONFIG_MMR_N_SKT_MASK		0x00000000000003c0UL
3568 #define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK		0x0000000000001000UL
3569 
3570 #define UVXH_RH_GAM_CONFIG_MMR_N_SKT_SHFT		6
3571 #define UVXH_RH_GAM_CONFIG_MMR_N_SKT_MASK		0x00000000000003c0UL
3572 
3573 #define UV2H_RH_GAM_CONFIG_MMR_M_SKT_SHFT		0
3574 #define UV2H_RH_GAM_CONFIG_MMR_N_SKT_SHFT		6
3575 #define UV2H_RH_GAM_CONFIG_MMR_M_SKT_MASK		0x000000000000003fUL
3576 #define UV2H_RH_GAM_CONFIG_MMR_N_SKT_MASK		0x00000000000003c0UL
3577 
3578 #define UV3H_RH_GAM_CONFIG_MMR_M_SKT_SHFT		0
3579 #define UV3H_RH_GAM_CONFIG_MMR_N_SKT_SHFT		6
3580 #define UV3H_RH_GAM_CONFIG_MMR_M_SKT_MASK		0x000000000000003fUL
3581 #define UV3H_RH_GAM_CONFIG_MMR_N_SKT_MASK		0x00000000000003c0UL
3582 
3583 #define UV4H_RH_GAM_CONFIG_MMR_N_SKT_SHFT		6
3584 #define UV4H_RH_GAM_CONFIG_MMR_N_SKT_MASK		0x00000000000003c0UL
3585 
3586 
3587 union uvh_rh_gam_config_mmr_u {
3588 	unsigned long	v;
3589 	struct uvh_rh_gam_config_mmr_s {
3590 		unsigned long	rsvd_0_5:6;
3591 		unsigned long	n_skt:4;			/* RW */
3592 		unsigned long	rsvd_10_63:54;
3593 	} s;
3594 	struct uv1h_rh_gam_config_mmr_s {
3595 		unsigned long	m_skt:6;			/* RW */
3596 		unsigned long	n_skt:4;			/* RW */
3597 		unsigned long	rsvd_10_11:2;
3598 		unsigned long	mmiol_cfg:1;			/* RW */
3599 		unsigned long	rsvd_13_63:51;
3600 	} s1;
3601 	struct uvxh_rh_gam_config_mmr_s {
3602 		unsigned long	rsvd_0_5:6;
3603 		unsigned long	n_skt:4;			/* RW */
3604 		unsigned long	rsvd_10_63:54;
3605 	} sx;
3606 	struct uv2h_rh_gam_config_mmr_s {
3607 		unsigned long	m_skt:6;			/* RW */
3608 		unsigned long	n_skt:4;			/* RW */
3609 		unsigned long	rsvd_10_63:54;
3610 	} s2;
3611 	struct uv3h_rh_gam_config_mmr_s {
3612 		unsigned long	m_skt:6;			/* RW */
3613 		unsigned long	n_skt:4;			/* RW */
3614 		unsigned long	rsvd_10_63:54;
3615 	} s3;
3616 	struct uv4h_rh_gam_config_mmr_s {
3617 		unsigned long	rsvd_0_5:6;
3618 		unsigned long	n_skt:4;			/* RW */
3619 		unsigned long	rsvd_10_63:54;
3620 	} s4;
3621 };
3622 
3623 /* ========================================================================= */
3624 /*                    UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR                      */
3625 /* ========================================================================= */
3626 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
3627 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
3628 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
3629 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x480010UL
3630 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR (				\
3631 	is_uv1_hub() ? UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR :		\
3632 	is_uv2_hub() ? UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR :		\
3633 	is_uv3_hub() ? UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR :		\
3634 	/*is_uv4_hub*/ UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR)
3635 
3636 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT	52
3637 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
3638 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK	0x00f0000000000000UL
3639 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL
3640 
3641 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT	28
3642 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT	48
3643 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT	52
3644 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
3645 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffff0000000UL
3646 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK	0x0001000000000000UL
3647 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK	0x00f0000000000000UL
3648 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL
3649 
3650 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT	52
3651 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
3652 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK	0x00f0000000000000UL
3653 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL
3654 
3655 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT	28
3656 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT	52
3657 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
3658 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffff0000000UL
3659 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK	0x00f0000000000000UL
3660 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL
3661 
3662 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT	28
3663 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT	52
3664 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_MODE_SHFT	62
3665 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
3666 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffff0000000UL
3667 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK	0x00f0000000000000UL
3668 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_MODE_MASK	0x4000000000000000UL
3669 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL
3670 
3671 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT	26
3672 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT	52
3673 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
3674 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffffc000000UL
3675 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK	0x00f0000000000000UL
3676 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL
3677 
3678 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK (			\
3679 	is_uv1_hub() ? UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK :	\
3680 	is_uv2_hub() ? UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK :	\
3681 	is_uv3_hub() ? UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK :	\
3682 	/*is_uv4_hub*/ UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK)
3683 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT (			\
3684 	is_uv1_hub() ? UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT :	\
3685 	is_uv2_hub() ? UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT :	\
3686 	is_uv3_hub() ? UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT :	\
3687 	/*is_uv4_hub*/ UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT)
3688 
3689 union uvh_rh_gam_gru_overlay_config_mmr_u {
3690 	unsigned long	v;
3691 	struct uvh_rh_gam_gru_overlay_config_mmr_s {
3692 		unsigned long	rsvd_0_51:52;
3693 		unsigned long	n_gru:4;			/* RW */
3694 		unsigned long	rsvd_56_62:7;
3695 		unsigned long	enable:1;			/* RW */
3696 	} s;
3697 	struct uv1h_rh_gam_gru_overlay_config_mmr_s {
3698 		unsigned long	rsvd_0_27:28;
3699 		unsigned long	base:18;			/* RW */
3700 		unsigned long	rsvd_46_47:2;
3701 		unsigned long	gr4:1;				/* RW */
3702 		unsigned long	rsvd_49_51:3;
3703 		unsigned long	n_gru:4;			/* RW */
3704 		unsigned long	rsvd_56_62:7;
3705 		unsigned long	enable:1;			/* RW */
3706 	} s1;
3707 	struct uvxh_rh_gam_gru_overlay_config_mmr_s {
3708 		unsigned long	rsvd_0_45:46;
3709 		unsigned long	rsvd_46_51:6;
3710 		unsigned long	n_gru:4;			/* RW */
3711 		unsigned long	rsvd_56_62:7;
3712 		unsigned long	enable:1;			/* RW */
3713 	} sx;
3714 	struct uv2h_rh_gam_gru_overlay_config_mmr_s {
3715 		unsigned long	rsvd_0_27:28;
3716 		unsigned long	base:18;			/* RW */
3717 		unsigned long	rsvd_46_51:6;
3718 		unsigned long	n_gru:4;			/* RW */
3719 		unsigned long	rsvd_56_62:7;
3720 		unsigned long	enable:1;			/* RW */
3721 	} s2;
3722 	struct uv3h_rh_gam_gru_overlay_config_mmr_s {
3723 		unsigned long	rsvd_0_27:28;
3724 		unsigned long	base:18;			/* RW */
3725 		unsigned long	rsvd_46_51:6;
3726 		unsigned long	n_gru:4;			/* RW */
3727 		unsigned long	rsvd_56_61:6;
3728 		unsigned long	mode:1;				/* RW */
3729 		unsigned long	enable:1;			/* RW */
3730 	} s3;
3731 	struct uv4h_rh_gam_gru_overlay_config_mmr_s {
3732 		unsigned long	rsvd_0_24:25;
3733 		unsigned long	undef_25:1;			/* Undefined */
3734 		unsigned long	base:20;			/* RW */
3735 		unsigned long	rsvd_46_51:6;
3736 		unsigned long	n_gru:4;			/* RW */
3737 		unsigned long	rsvd_56_62:7;
3738 		unsigned long	enable:1;			/* RW */
3739 	} s4;
3740 };
3741 
3742 /* ========================================================================= */
3743 /*                   UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR                    */
3744 /* ========================================================================= */
3745 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR uv_undefined("UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR")
3746 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR uv_undefined("UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR")
3747 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR 0x1603000UL
3748 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR 0x483000UL
3749 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR (				\
3750 	is_uv1_hub() ? UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR :		\
3751 	is_uv2_hub() ? UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR :		\
3752 	is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR :		\
3753 	/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR)
3754 
3755 
3756 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT	26
3757 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT	46
3758 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_SHFT 63
3759 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK	0x00003ffffc000000UL
3760 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK	0x000fc00000000000UL
3761 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK 0x8000000000000000UL
3762 
3763 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT	26
3764 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT	46
3765 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_SHFT 63
3766 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK	0x00003ffffc000000UL
3767 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK	0x000fc00000000000UL
3768 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK 0x8000000000000000UL
3769 
3770 #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT 52
3771 #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK 0x000ffffffc000000UL
3772 #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK 0x03f0000000000000UL
3773 #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK 0x8000000000000000UL
3774 
3775 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT (		\
3776 	is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT : \
3777 	is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT : \
3778 	/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT)
3779 
3780 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK (		\
3781 	is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK : \
3782 	is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK : \
3783 	/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK)
3784 
3785 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK (		\
3786 	is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK : \
3787 	is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK : \
3788 	/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK)
3789 
3790 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK (		\
3791 	is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK : \
3792 	is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK : \
3793 	/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK)
3794 
3795 union uvh_rh_gam_mmioh_overlay_config0_mmr_u {
3796 	unsigned long	v;
3797 	struct uv3h_rh_gam_mmioh_overlay_config0_mmr_s {
3798 		unsigned long	rsvd_0_25:26;
3799 		unsigned long	base:20;			/* RW */
3800 		unsigned long	m_io:6;				/* RW */
3801 		unsigned long	n_io:4;
3802 		unsigned long	rsvd_56_62:7;
3803 		unsigned long	enable:1;			/* RW */
3804 	} s3;
3805 	struct uv4h_rh_gam_mmioh_overlay_config0_mmr_s {
3806 		unsigned long	rsvd_0_25:26;
3807 		unsigned long	base:20;			/* RW */
3808 		unsigned long	m_io:6;				/* RW */
3809 		unsigned long	n_io:4;
3810 		unsigned long	rsvd_56_62:7;
3811 		unsigned long	enable:1;			/* RW */
3812 	} s4;
3813 	struct uv4ah_rh_gam_mmioh_overlay_config0_mmr_s {
3814 		unsigned long	rsvd_0_25:26;
3815 		unsigned long	base:26;			/* RW */
3816 		unsigned long	m_io:6;				/* RW */
3817 		unsigned long	n_io:4;
3818 		unsigned long	undef_62:1;			/* Undefined */
3819 		unsigned long	enable:1;			/* RW */
3820 	} s4a;
3821 };
3822 
3823 /* ========================================================================= */
3824 /*                   UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR                    */
3825 /* ========================================================================= */
3826 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR uv_undefined("UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR")
3827 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR uv_undefined("UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR")
3828 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR 0x1603000UL
3829 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR 0x484000UL
3830 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR (				\
3831 	is_uv1_hub() ? UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR :		\
3832 	is_uv2_hub() ? UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR :		\
3833 	is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR :		\
3834 	/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR)
3835 
3836 
3837 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_SHFT	26
3838 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT	46
3839 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_SHFT 63
3840 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK	0x00003ffffc000000UL
3841 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK	0x000fc00000000000UL
3842 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_MASK 0x8000000000000000UL
3843 
3844 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_SHFT	26
3845 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT	46
3846 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_SHFT 63
3847 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK	0x00003ffffc000000UL
3848 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK	0x000fc00000000000UL
3849 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_MASK 0x8000000000000000UL
3850 
3851 #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT 52
3852 #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK 0x000ffffffc000000UL
3853 #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK 0x03f0000000000000UL
3854 
3855 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT (		\
3856 	is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT : \
3857 	is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT : \
3858 	/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT)
3859 
3860 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK (		\
3861 	is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK : \
3862 	is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK : \
3863 	/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK)
3864 
3865 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK (		\
3866 	is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK : \
3867 	is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK : \
3868 	/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK)
3869 
3870 union uvh_rh_gam_mmioh_overlay_config1_mmr_u {
3871 	unsigned long	v;
3872 	struct uv3h_rh_gam_mmioh_overlay_config1_mmr_s {
3873 		unsigned long	rsvd_0_25:26;
3874 		unsigned long	base:20;			/* RW */
3875 		unsigned long	m_io:6;				/* RW */
3876 		unsigned long	n_io:4;
3877 		unsigned long	rsvd_56_62:7;
3878 		unsigned long	enable:1;			/* RW */
3879 	} s3;
3880 	struct uv4h_rh_gam_mmioh_overlay_config1_mmr_s {
3881 		unsigned long	rsvd_0_25:26;
3882 		unsigned long	base:20;			/* RW */
3883 		unsigned long	m_io:6;				/* RW */
3884 		unsigned long	n_io:4;
3885 		unsigned long	rsvd_56_62:7;
3886 		unsigned long	enable:1;			/* RW */
3887 	} s4;
3888 	struct uv4ah_rh_gam_mmioh_overlay_config1_mmr_s {
3889 		unsigned long	rsvd_0_25:26;
3890 		unsigned long	base:26;			/* RW */
3891 		unsigned long	m_io:6;				/* RW */
3892 		unsigned long	n_io:4;
3893 		unsigned long	undef_62:1;			/* Undefined */
3894 		unsigned long	enable:1;			/* RW */
3895 	} s4a;
3896 };
3897 
3898 /* ========================================================================= */
3899 /*                   UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR                     */
3900 /* ========================================================================= */
3901 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL
3902 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL
3903 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR uv_undefined("UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR")
3904 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR uv_undefined("UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR")
3905 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR (				\
3906 	is_uv1_hub() ? UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR :		\
3907 	is_uv2_hub() ? UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR :		\
3908 	is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR :		\
3909 	/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR)
3910 
3911 
3912 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT	30
3913 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT	46
3914 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT	52
3915 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
3916 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003fffc0000000UL
3917 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK	0x000fc00000000000UL
3918 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK	0x00f0000000000000UL
3919 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
3920 
3921 
3922 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT	27
3923 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT	46
3924 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT	52
3925 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
3926 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffff8000000UL
3927 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK	0x000fc00000000000UL
3928 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK	0x00f0000000000000UL
3929 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
3930 
3931 
3932 union uvh_rh_gam_mmioh_overlay_config_mmr_u {
3933 	unsigned long	v;
3934 	struct uv1h_rh_gam_mmioh_overlay_config_mmr_s {
3935 		unsigned long	rsvd_0_29:30;
3936 		unsigned long	base:16;			/* RW */
3937 		unsigned long	m_io:6;				/* RW */
3938 		unsigned long	n_io:4;				/* RW */
3939 		unsigned long	rsvd_56_62:7;
3940 		unsigned long	enable:1;			/* RW */
3941 	} s1;
3942 	struct uv2h_rh_gam_mmioh_overlay_config_mmr_s {
3943 		unsigned long	rsvd_0_26:27;
3944 		unsigned long	base:19;			/* RW */
3945 		unsigned long	m_io:6;				/* RW */
3946 		unsigned long	n_io:4;				/* RW */
3947 		unsigned long	rsvd_56_62:7;
3948 		unsigned long	enable:1;			/* RW */
3949 	} s2;
3950 };
3951 
3952 /* ========================================================================= */
3953 /*                  UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR                    */
3954 /* ========================================================================= */
3955 #define UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR uv_undefined("UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR")
3956 #define UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR uv_undefined("UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR")
3957 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR 0x1603800UL
3958 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR 0x483800UL
3959 #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR (				\
3960 	is_uv1_hub() ? UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR :		\
3961 	is_uv2_hub() ? UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR :		\
3962 	is_uv3_hub() ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR :		\
3963 	/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR)
3964 
3965 #define UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH uv_undefined("UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH")
3966 #define UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH uv_undefined("UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH")
3967 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH 128
3968 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH 128
3969 #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH (			\
3970 	is_uv1_hub() ? UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH :	\
3971 	is_uv2_hub() ? UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH :	\
3972 	is_uv3_hub() ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH :	\
3973 	/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH)
3974 
3975 
3976 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_SHFT 0
3977 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK 0x0000000000007fffUL
3978 
3979 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_SHFT 0
3980 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK 0x0000000000007fffUL
3981 
3982 #define UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK 0x0000000000000fffUL
3983 
3984 #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK (		\
3985 	is_uv3_hub() ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK : \
3986 	is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK : \
3987 	/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK)
3988 
3989 union uvh_rh_gam_mmioh_redirect_config0_mmr_u {
3990 	unsigned long	v;
3991 	struct uv3h_rh_gam_mmioh_redirect_config0_mmr_s {
3992 		unsigned long	nasid:15;			/* RW */
3993 		unsigned long	rsvd_15_63:49;
3994 	} s3;
3995 	struct uv4h_rh_gam_mmioh_redirect_config0_mmr_s {
3996 		unsigned long	nasid:15;			/* RW */
3997 		unsigned long	rsvd_15_63:49;
3998 	} s4;
3999 	struct uv4ah_rh_gam_mmioh_redirect_config0_mmr_s {
4000 		unsigned long	nasid:12;			/* RW */
4001 		unsigned long	rsvd_12_63:52;
4002 	} s4a;
4003 };
4004 
4005 /* ========================================================================= */
4006 /*                  UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR                    */
4007 /* ========================================================================= */
4008 #define UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR uv_undefined("UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR")
4009 #define UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR uv_undefined("UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR")
4010 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR 0x1604800UL
4011 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR 0x484800UL
4012 #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR (				\
4013 	is_uv1_hub() ? UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR :		\
4014 	is_uv2_hub() ? UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR :		\
4015 	is_uv3_hub() ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR :		\
4016 	/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR)
4017 
4018 #define UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH uv_undefined("UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH")
4019 #define UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH uv_undefined("UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH")
4020 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH 128
4021 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH 128
4022 #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH (			\
4023 	is_uv1_hub() ? UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH :	\
4024 	is_uv2_hub() ? UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH :	\
4025 	is_uv3_hub() ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH :	\
4026 	/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH)
4027 
4028 
4029 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_SHFT 0
4030 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK 0x0000000000007fffUL
4031 
4032 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_SHFT 0
4033 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK 0x0000000000007fffUL
4034 
4035 #define UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK 0x0000000000000fffUL
4036 
4037 #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK (		\
4038 	is_uv3_hub() ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK : \
4039 	is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK : \
4040 	/*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK)
4041 
4042 union uvh_rh_gam_mmioh_redirect_config1_mmr_u {
4043 	unsigned long	v;
4044 	struct uv3h_rh_gam_mmioh_redirect_config1_mmr_s {
4045 		unsigned long	nasid:15;			/* RW */
4046 		unsigned long	rsvd_15_63:49;
4047 	} s3;
4048 	struct uv4h_rh_gam_mmioh_redirect_config1_mmr_s {
4049 		unsigned long	nasid:15;			/* RW */
4050 		unsigned long	rsvd_15_63:49;
4051 	} s4;
4052 	struct uv4ah_rh_gam_mmioh_redirect_config1_mmr_s {
4053 		unsigned long	nasid:12;			/* RW */
4054 		unsigned long	rsvd_12_63:52;
4055 	} s4a;
4056 };
4057 
4058 /* ========================================================================= */
4059 /*                    UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR                      */
4060 /* ========================================================================= */
4061 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
4062 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
4063 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
4064 #define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x480028UL
4065 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR (				\
4066 	is_uv1_hub() ? UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR :		\
4067 	is_uv2_hub() ? UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR :		\
4068 	is_uv3_hub() ? UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR :		\
4069 	/*is_uv4_hub*/ UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR)
4070 
4071 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT	26
4072 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
4073 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffffc000000UL
4074 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL
4075 
4076 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT	26
4077 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46
4078 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
4079 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffffc000000UL
4080 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL
4081 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL
4082 
4083 #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT	26
4084 #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
4085 #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffffc000000UL
4086 #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL
4087 
4088 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT	26
4089 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
4090 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffffc000000UL
4091 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL
4092 
4093 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT	26
4094 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
4095 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffffc000000UL
4096 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL
4097 
4098 #define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT	26
4099 #define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT	63
4100 #define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK	0x00003ffffc000000UL
4101 #define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK	0x8000000000000000UL
4102 
4103 
4104 union uvh_rh_gam_mmr_overlay_config_mmr_u {
4105 	unsigned long	v;
4106 	struct uvh_rh_gam_mmr_overlay_config_mmr_s {
4107 		unsigned long	rsvd_0_25:26;
4108 		unsigned long	base:20;			/* RW */
4109 		unsigned long	rsvd_46_62:17;
4110 		unsigned long	enable:1;			/* RW */
4111 	} s;
4112 	struct uv1h_rh_gam_mmr_overlay_config_mmr_s {
4113 		unsigned long	rsvd_0_25:26;
4114 		unsigned long	base:20;			/* RW */
4115 		unsigned long	dual_hub:1;			/* RW */
4116 		unsigned long	rsvd_47_62:16;
4117 		unsigned long	enable:1;			/* RW */
4118 	} s1;
4119 	struct uvxh_rh_gam_mmr_overlay_config_mmr_s {
4120 		unsigned long	rsvd_0_25:26;
4121 		unsigned long	base:20;			/* RW */
4122 		unsigned long	rsvd_46_62:17;
4123 		unsigned long	enable:1;			/* RW */
4124 	} sx;
4125 	struct uv2h_rh_gam_mmr_overlay_config_mmr_s {
4126 		unsigned long	rsvd_0_25:26;
4127 		unsigned long	base:20;			/* RW */
4128 		unsigned long	rsvd_46_62:17;
4129 		unsigned long	enable:1;			/* RW */
4130 	} s2;
4131 	struct uv3h_rh_gam_mmr_overlay_config_mmr_s {
4132 		unsigned long	rsvd_0_25:26;
4133 		unsigned long	base:20;			/* RW */
4134 		unsigned long	rsvd_46_62:17;
4135 		unsigned long	enable:1;			/* RW */
4136 	} s3;
4137 	struct uv4h_rh_gam_mmr_overlay_config_mmr_s {
4138 		unsigned long	rsvd_0_25:26;
4139 		unsigned long	base:20;			/* RW */
4140 		unsigned long	rsvd_46_62:17;
4141 		unsigned long	enable:1;			/* RW */
4142 	} s4;
4143 };
4144 
4145 /* ========================================================================= */
4146 /*                                 UVH_RTC                                   */
4147 /* ========================================================================= */
4148 #define UV1H_RTC 0x340000UL
4149 #define UV2H_RTC 0x340000UL
4150 #define UV3H_RTC 0x340000UL
4151 #define UV4H_RTC 0xe0000UL
4152 #define UVH_RTC (							\
4153 	is_uv1_hub() ? UV1H_RTC :					\
4154 	is_uv2_hub() ? UV2H_RTC :					\
4155 	is_uv3_hub() ? UV3H_RTC :					\
4156 	/*is_uv4_hub*/ UV4H_RTC)
4157 
4158 #define UVH_RTC_REAL_TIME_CLOCK_SHFT			0
4159 #define UVH_RTC_REAL_TIME_CLOCK_MASK			0x00ffffffffffffffUL
4160 
4161 
4162 union uvh_rtc_u {
4163 	unsigned long	v;
4164 	struct uvh_rtc_s {
4165 		unsigned long	real_time_clock:56;		/* RW */
4166 		unsigned long	rsvd_56_63:8;
4167 	} s;
4168 };
4169 
4170 /* ========================================================================= */
4171 /*                           UVH_RTC1_INT_CONFIG                             */
4172 /* ========================================================================= */
4173 #define UVH_RTC1_INT_CONFIG 0x615c0UL
4174 
4175 #define UVH_RTC1_INT_CONFIG_VECTOR_SHFT			0
4176 #define UVH_RTC1_INT_CONFIG_DM_SHFT			8
4177 #define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT		11
4178 #define UVH_RTC1_INT_CONFIG_STATUS_SHFT			12
4179 #define UVH_RTC1_INT_CONFIG_P_SHFT			13
4180 #define UVH_RTC1_INT_CONFIG_T_SHFT			15
4181 #define UVH_RTC1_INT_CONFIG_M_SHFT			16
4182 #define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT		32
4183 #define UVH_RTC1_INT_CONFIG_VECTOR_MASK			0x00000000000000ffUL
4184 #define UVH_RTC1_INT_CONFIG_DM_MASK			0x0000000000000700UL
4185 #define UVH_RTC1_INT_CONFIG_DESTMODE_MASK		0x0000000000000800UL
4186 #define UVH_RTC1_INT_CONFIG_STATUS_MASK			0x0000000000001000UL
4187 #define UVH_RTC1_INT_CONFIG_P_MASK			0x0000000000002000UL
4188 #define UVH_RTC1_INT_CONFIG_T_MASK			0x0000000000008000UL
4189 #define UVH_RTC1_INT_CONFIG_M_MASK			0x0000000000010000UL
4190 #define UVH_RTC1_INT_CONFIG_APIC_ID_MASK		0xffffffff00000000UL
4191 
4192 
4193 union uvh_rtc1_int_config_u {
4194 	unsigned long	v;
4195 	struct uvh_rtc1_int_config_s {
4196 		unsigned long	vector_:8;			/* RW */
4197 		unsigned long	dm:3;				/* RW */
4198 		unsigned long	destmode:1;			/* RW */
4199 		unsigned long	status:1;			/* RO */
4200 		unsigned long	p:1;				/* RO */
4201 		unsigned long	rsvd_14:1;
4202 		unsigned long	t:1;				/* RO */
4203 		unsigned long	m:1;				/* RW */
4204 		unsigned long	rsvd_17_31:15;
4205 		unsigned long	apic_id:32;			/* RW */
4206 	} s;
4207 };
4208 
4209 /* ========================================================================= */
4210 /*                               UVH_SCRATCH5                                */
4211 /* ========================================================================= */
4212 #define UV1H_SCRATCH5 0x2d0200UL
4213 #define UV2H_SCRATCH5 0x2d0200UL
4214 #define UV3H_SCRATCH5 0x2d0200UL
4215 #define UV4H_SCRATCH5 0xb0200UL
4216 #define UVH_SCRATCH5 (							\
4217 	is_uv1_hub() ? UV1H_SCRATCH5 :					\
4218 	is_uv2_hub() ? UV2H_SCRATCH5 :					\
4219 	is_uv3_hub() ? UV3H_SCRATCH5 :					\
4220 	/*is_uv4_hub*/ UV4H_SCRATCH5)
4221 
4222 #define UV1H_SCRATCH5_32 0x778
4223 #define UV2H_SCRATCH5_32 0x778
4224 #define UV3H_SCRATCH5_32 0x778
4225 #define UV4H_SCRATCH5_32 0x798
4226 #define UVH_SCRATCH5_32 (						\
4227 	is_uv1_hub() ? UV1H_SCRATCH5_32 :				\
4228 	is_uv2_hub() ? UV2H_SCRATCH5_32 :				\
4229 	is_uv3_hub() ? UV3H_SCRATCH5_32 :				\
4230 	/*is_uv4_hub*/ UV4H_SCRATCH5_32)
4231 
4232 #define UVH_SCRATCH5_SCRATCH5_SHFT			0
4233 #define UVH_SCRATCH5_SCRATCH5_MASK			0xffffffffffffffffUL
4234 
4235 
4236 union uvh_scratch5_u {
4237 	unsigned long	v;
4238 	struct uvh_scratch5_s {
4239 		unsigned long	scratch5:64;			/* RW, W1CS */
4240 	} s;
4241 };
4242 
4243 /* ========================================================================= */
4244 /*                            UVH_SCRATCH5_ALIAS                             */
4245 /* ========================================================================= */
4246 #define UV1H_SCRATCH5_ALIAS 0x2d0208UL
4247 #define UV2H_SCRATCH5_ALIAS 0x2d0208UL
4248 #define UV3H_SCRATCH5_ALIAS 0x2d0208UL
4249 #define UV4H_SCRATCH5_ALIAS 0xb0208UL
4250 #define UVH_SCRATCH5_ALIAS (						\
4251 	is_uv1_hub() ? UV1H_SCRATCH5_ALIAS :				\
4252 	is_uv2_hub() ? UV2H_SCRATCH5_ALIAS :				\
4253 	is_uv3_hub() ? UV3H_SCRATCH5_ALIAS :				\
4254 	/*is_uv4_hub*/ UV4H_SCRATCH5_ALIAS)
4255 
4256 #define UV1H_SCRATCH5_ALIAS_32 0x780
4257 #define UV2H_SCRATCH5_ALIAS_32 0x780
4258 #define UV3H_SCRATCH5_ALIAS_32 0x780
4259 #define UV4H_SCRATCH5_ALIAS_32 0x7a0
4260 #define UVH_SCRATCH5_ALIAS_32 (						\
4261 	is_uv1_hub() ? UV1H_SCRATCH5_ALIAS_32 :				\
4262 	is_uv2_hub() ? UV2H_SCRATCH5_ALIAS_32 :				\
4263 	is_uv3_hub() ? UV3H_SCRATCH5_ALIAS_32 :				\
4264 	/*is_uv4_hub*/ UV4H_SCRATCH5_ALIAS_32)
4265 
4266 
4267 /* ========================================================================= */
4268 /*                           UVH_SCRATCH5_ALIAS_2                            */
4269 /* ========================================================================= */
4270 #define UV1H_SCRATCH5_ALIAS_2 0x2d0210UL
4271 #define UV2H_SCRATCH5_ALIAS_2 0x2d0210UL
4272 #define UV3H_SCRATCH5_ALIAS_2 0x2d0210UL
4273 #define UV4H_SCRATCH5_ALIAS_2 0xb0210UL
4274 #define UVH_SCRATCH5_ALIAS_2 (						\
4275 	is_uv1_hub() ? UV1H_SCRATCH5_ALIAS_2 :				\
4276 	is_uv2_hub() ? UV2H_SCRATCH5_ALIAS_2 :				\
4277 	is_uv3_hub() ? UV3H_SCRATCH5_ALIAS_2 :				\
4278 	/*is_uv4_hub*/ UV4H_SCRATCH5_ALIAS_2)
4279 #define UVH_SCRATCH5_ALIAS_2_32 0x788
4280 
4281 
4282 /* ========================================================================= */
4283 /*                          UVXH_EVENT_OCCURRED2                             */
4284 /* ========================================================================= */
4285 #define UVXH_EVENT_OCCURRED2 0x70100UL
4286 
4287 #define UV2H_EVENT_OCCURRED2_32 0xb68
4288 #define UV3H_EVENT_OCCURRED2_32 0xb68
4289 #define UV4H_EVENT_OCCURRED2_32 0x608
4290 #define UVH_EVENT_OCCURRED2_32 (					\
4291 	is_uv2_hub() ? UV2H_EVENT_OCCURRED2_32 :			\
4292 	is_uv3_hub() ? UV3H_EVENT_OCCURRED2_32 :			\
4293 	/*is_uv4_hub*/ UV4H_EVENT_OCCURRED2_32)
4294 
4295 
4296 #define UV2H_EVENT_OCCURRED2_RTC_0_SHFT			0
4297 #define UV2H_EVENT_OCCURRED2_RTC_1_SHFT			1
4298 #define UV2H_EVENT_OCCURRED2_RTC_2_SHFT			2
4299 #define UV2H_EVENT_OCCURRED2_RTC_3_SHFT			3
4300 #define UV2H_EVENT_OCCURRED2_RTC_4_SHFT			4
4301 #define UV2H_EVENT_OCCURRED2_RTC_5_SHFT			5
4302 #define UV2H_EVENT_OCCURRED2_RTC_6_SHFT			6
4303 #define UV2H_EVENT_OCCURRED2_RTC_7_SHFT			7
4304 #define UV2H_EVENT_OCCURRED2_RTC_8_SHFT			8
4305 #define UV2H_EVENT_OCCURRED2_RTC_9_SHFT			9
4306 #define UV2H_EVENT_OCCURRED2_RTC_10_SHFT		10
4307 #define UV2H_EVENT_OCCURRED2_RTC_11_SHFT		11
4308 #define UV2H_EVENT_OCCURRED2_RTC_12_SHFT		12
4309 #define UV2H_EVENT_OCCURRED2_RTC_13_SHFT		13
4310 #define UV2H_EVENT_OCCURRED2_RTC_14_SHFT		14
4311 #define UV2H_EVENT_OCCURRED2_RTC_15_SHFT		15
4312 #define UV2H_EVENT_OCCURRED2_RTC_16_SHFT		16
4313 #define UV2H_EVENT_OCCURRED2_RTC_17_SHFT		17
4314 #define UV2H_EVENT_OCCURRED2_RTC_18_SHFT		18
4315 #define UV2H_EVENT_OCCURRED2_RTC_19_SHFT		19
4316 #define UV2H_EVENT_OCCURRED2_RTC_20_SHFT		20
4317 #define UV2H_EVENT_OCCURRED2_RTC_21_SHFT		21
4318 #define UV2H_EVENT_OCCURRED2_RTC_22_SHFT		22
4319 #define UV2H_EVENT_OCCURRED2_RTC_23_SHFT		23
4320 #define UV2H_EVENT_OCCURRED2_RTC_24_SHFT		24
4321 #define UV2H_EVENT_OCCURRED2_RTC_25_SHFT		25
4322 #define UV2H_EVENT_OCCURRED2_RTC_26_SHFT		26
4323 #define UV2H_EVENT_OCCURRED2_RTC_27_SHFT		27
4324 #define UV2H_EVENT_OCCURRED2_RTC_28_SHFT		28
4325 #define UV2H_EVENT_OCCURRED2_RTC_29_SHFT		29
4326 #define UV2H_EVENT_OCCURRED2_RTC_30_SHFT		30
4327 #define UV2H_EVENT_OCCURRED2_RTC_31_SHFT		31
4328 #define UV2H_EVENT_OCCURRED2_RTC_0_MASK			0x0000000000000001UL
4329 #define UV2H_EVENT_OCCURRED2_RTC_1_MASK			0x0000000000000002UL
4330 #define UV2H_EVENT_OCCURRED2_RTC_2_MASK			0x0000000000000004UL
4331 #define UV2H_EVENT_OCCURRED2_RTC_3_MASK			0x0000000000000008UL
4332 #define UV2H_EVENT_OCCURRED2_RTC_4_MASK			0x0000000000000010UL
4333 #define UV2H_EVENT_OCCURRED2_RTC_5_MASK			0x0000000000000020UL
4334 #define UV2H_EVENT_OCCURRED2_RTC_6_MASK			0x0000000000000040UL
4335 #define UV2H_EVENT_OCCURRED2_RTC_7_MASK			0x0000000000000080UL
4336 #define UV2H_EVENT_OCCURRED2_RTC_8_MASK			0x0000000000000100UL
4337 #define UV2H_EVENT_OCCURRED2_RTC_9_MASK			0x0000000000000200UL
4338 #define UV2H_EVENT_OCCURRED2_RTC_10_MASK		0x0000000000000400UL
4339 #define UV2H_EVENT_OCCURRED2_RTC_11_MASK		0x0000000000000800UL
4340 #define UV2H_EVENT_OCCURRED2_RTC_12_MASK		0x0000000000001000UL
4341 #define UV2H_EVENT_OCCURRED2_RTC_13_MASK		0x0000000000002000UL
4342 #define UV2H_EVENT_OCCURRED2_RTC_14_MASK		0x0000000000004000UL
4343 #define UV2H_EVENT_OCCURRED2_RTC_15_MASK		0x0000000000008000UL
4344 #define UV2H_EVENT_OCCURRED2_RTC_16_MASK		0x0000000000010000UL
4345 #define UV2H_EVENT_OCCURRED2_RTC_17_MASK		0x0000000000020000UL
4346 #define UV2H_EVENT_OCCURRED2_RTC_18_MASK		0x0000000000040000UL
4347 #define UV2H_EVENT_OCCURRED2_RTC_19_MASK		0x0000000000080000UL
4348 #define UV2H_EVENT_OCCURRED2_RTC_20_MASK		0x0000000000100000UL
4349 #define UV2H_EVENT_OCCURRED2_RTC_21_MASK		0x0000000000200000UL
4350 #define UV2H_EVENT_OCCURRED2_RTC_22_MASK		0x0000000000400000UL
4351 #define UV2H_EVENT_OCCURRED2_RTC_23_MASK		0x0000000000800000UL
4352 #define UV2H_EVENT_OCCURRED2_RTC_24_MASK		0x0000000001000000UL
4353 #define UV2H_EVENT_OCCURRED2_RTC_25_MASK		0x0000000002000000UL
4354 #define UV2H_EVENT_OCCURRED2_RTC_26_MASK		0x0000000004000000UL
4355 #define UV2H_EVENT_OCCURRED2_RTC_27_MASK		0x0000000008000000UL
4356 #define UV2H_EVENT_OCCURRED2_RTC_28_MASK		0x0000000010000000UL
4357 #define UV2H_EVENT_OCCURRED2_RTC_29_MASK		0x0000000020000000UL
4358 #define UV2H_EVENT_OCCURRED2_RTC_30_MASK		0x0000000040000000UL
4359 #define UV2H_EVENT_OCCURRED2_RTC_31_MASK		0x0000000080000000UL
4360 
4361 #define UV3H_EVENT_OCCURRED2_RTC_0_SHFT			0
4362 #define UV3H_EVENT_OCCURRED2_RTC_1_SHFT			1
4363 #define UV3H_EVENT_OCCURRED2_RTC_2_SHFT			2
4364 #define UV3H_EVENT_OCCURRED2_RTC_3_SHFT			3
4365 #define UV3H_EVENT_OCCURRED2_RTC_4_SHFT			4
4366 #define UV3H_EVENT_OCCURRED2_RTC_5_SHFT			5
4367 #define UV3H_EVENT_OCCURRED2_RTC_6_SHFT			6
4368 #define UV3H_EVENT_OCCURRED2_RTC_7_SHFT			7
4369 #define UV3H_EVENT_OCCURRED2_RTC_8_SHFT			8
4370 #define UV3H_EVENT_OCCURRED2_RTC_9_SHFT			9
4371 #define UV3H_EVENT_OCCURRED2_RTC_10_SHFT		10
4372 #define UV3H_EVENT_OCCURRED2_RTC_11_SHFT		11
4373 #define UV3H_EVENT_OCCURRED2_RTC_12_SHFT		12
4374 #define UV3H_EVENT_OCCURRED2_RTC_13_SHFT		13
4375 #define UV3H_EVENT_OCCURRED2_RTC_14_SHFT		14
4376 #define UV3H_EVENT_OCCURRED2_RTC_15_SHFT		15
4377 #define UV3H_EVENT_OCCURRED2_RTC_16_SHFT		16
4378 #define UV3H_EVENT_OCCURRED2_RTC_17_SHFT		17
4379 #define UV3H_EVENT_OCCURRED2_RTC_18_SHFT		18
4380 #define UV3H_EVENT_OCCURRED2_RTC_19_SHFT		19
4381 #define UV3H_EVENT_OCCURRED2_RTC_20_SHFT		20
4382 #define UV3H_EVENT_OCCURRED2_RTC_21_SHFT		21
4383 #define UV3H_EVENT_OCCURRED2_RTC_22_SHFT		22
4384 #define UV3H_EVENT_OCCURRED2_RTC_23_SHFT		23
4385 #define UV3H_EVENT_OCCURRED2_RTC_24_SHFT		24
4386 #define UV3H_EVENT_OCCURRED2_RTC_25_SHFT		25
4387 #define UV3H_EVENT_OCCURRED2_RTC_26_SHFT		26
4388 #define UV3H_EVENT_OCCURRED2_RTC_27_SHFT		27
4389 #define UV3H_EVENT_OCCURRED2_RTC_28_SHFT		28
4390 #define UV3H_EVENT_OCCURRED2_RTC_29_SHFT		29
4391 #define UV3H_EVENT_OCCURRED2_RTC_30_SHFT		30
4392 #define UV3H_EVENT_OCCURRED2_RTC_31_SHFT		31
4393 #define UV3H_EVENT_OCCURRED2_RTC_0_MASK			0x0000000000000001UL
4394 #define UV3H_EVENT_OCCURRED2_RTC_1_MASK			0x0000000000000002UL
4395 #define UV3H_EVENT_OCCURRED2_RTC_2_MASK			0x0000000000000004UL
4396 #define UV3H_EVENT_OCCURRED2_RTC_3_MASK			0x0000000000000008UL
4397 #define UV3H_EVENT_OCCURRED2_RTC_4_MASK			0x0000000000000010UL
4398 #define UV3H_EVENT_OCCURRED2_RTC_5_MASK			0x0000000000000020UL
4399 #define UV3H_EVENT_OCCURRED2_RTC_6_MASK			0x0000000000000040UL
4400 #define UV3H_EVENT_OCCURRED2_RTC_7_MASK			0x0000000000000080UL
4401 #define UV3H_EVENT_OCCURRED2_RTC_8_MASK			0x0000000000000100UL
4402 #define UV3H_EVENT_OCCURRED2_RTC_9_MASK			0x0000000000000200UL
4403 #define UV3H_EVENT_OCCURRED2_RTC_10_MASK		0x0000000000000400UL
4404 #define UV3H_EVENT_OCCURRED2_RTC_11_MASK		0x0000000000000800UL
4405 #define UV3H_EVENT_OCCURRED2_RTC_12_MASK		0x0000000000001000UL
4406 #define UV3H_EVENT_OCCURRED2_RTC_13_MASK		0x0000000000002000UL
4407 #define UV3H_EVENT_OCCURRED2_RTC_14_MASK		0x0000000000004000UL
4408 #define UV3H_EVENT_OCCURRED2_RTC_15_MASK		0x0000000000008000UL
4409 #define UV3H_EVENT_OCCURRED2_RTC_16_MASK		0x0000000000010000UL
4410 #define UV3H_EVENT_OCCURRED2_RTC_17_MASK		0x0000000000020000UL
4411 #define UV3H_EVENT_OCCURRED2_RTC_18_MASK		0x0000000000040000UL
4412 #define UV3H_EVENT_OCCURRED2_RTC_19_MASK		0x0000000000080000UL
4413 #define UV3H_EVENT_OCCURRED2_RTC_20_MASK		0x0000000000100000UL
4414 #define UV3H_EVENT_OCCURRED2_RTC_21_MASK		0x0000000000200000UL
4415 #define UV3H_EVENT_OCCURRED2_RTC_22_MASK		0x0000000000400000UL
4416 #define UV3H_EVENT_OCCURRED2_RTC_23_MASK		0x0000000000800000UL
4417 #define UV3H_EVENT_OCCURRED2_RTC_24_MASK		0x0000000001000000UL
4418 #define UV3H_EVENT_OCCURRED2_RTC_25_MASK		0x0000000002000000UL
4419 #define UV3H_EVENT_OCCURRED2_RTC_26_MASK		0x0000000004000000UL
4420 #define UV3H_EVENT_OCCURRED2_RTC_27_MASK		0x0000000008000000UL
4421 #define UV3H_EVENT_OCCURRED2_RTC_28_MASK		0x0000000010000000UL
4422 #define UV3H_EVENT_OCCURRED2_RTC_29_MASK		0x0000000020000000UL
4423 #define UV3H_EVENT_OCCURRED2_RTC_30_MASK		0x0000000040000000UL
4424 #define UV3H_EVENT_OCCURRED2_RTC_31_MASK		0x0000000080000000UL
4425 
4426 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT0_SHFT 0
4427 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT1_SHFT 1
4428 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT2_SHFT 2
4429 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT3_SHFT 3
4430 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT4_SHFT 4
4431 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT5_SHFT 5
4432 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT6_SHFT 6
4433 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT7_SHFT 7
4434 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT8_SHFT 8
4435 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT9_SHFT 9
4436 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT10_SHFT 10
4437 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT11_SHFT 11
4438 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT12_SHFT 12
4439 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT13_SHFT 13
4440 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT14_SHFT 14
4441 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT15_SHFT 15
4442 #define UV4H_EVENT_OCCURRED2_RTC_INTERVAL_INT_SHFT	16
4443 #define UV4H_EVENT_OCCURRED2_BAU_DASHBOARD_INT_SHFT	17
4444 #define UV4H_EVENT_OCCURRED2_RTC_0_SHFT			18
4445 #define UV4H_EVENT_OCCURRED2_RTC_1_SHFT			19
4446 #define UV4H_EVENT_OCCURRED2_RTC_2_SHFT			20
4447 #define UV4H_EVENT_OCCURRED2_RTC_3_SHFT			21
4448 #define UV4H_EVENT_OCCURRED2_RTC_4_SHFT			22
4449 #define UV4H_EVENT_OCCURRED2_RTC_5_SHFT			23
4450 #define UV4H_EVENT_OCCURRED2_RTC_6_SHFT			24
4451 #define UV4H_EVENT_OCCURRED2_RTC_7_SHFT			25
4452 #define UV4H_EVENT_OCCURRED2_RTC_8_SHFT			26
4453 #define UV4H_EVENT_OCCURRED2_RTC_9_SHFT			27
4454 #define UV4H_EVENT_OCCURRED2_RTC_10_SHFT		28
4455 #define UV4H_EVENT_OCCURRED2_RTC_11_SHFT		29
4456 #define UV4H_EVENT_OCCURRED2_RTC_12_SHFT		30
4457 #define UV4H_EVENT_OCCURRED2_RTC_13_SHFT		31
4458 #define UV4H_EVENT_OCCURRED2_RTC_14_SHFT		32
4459 #define UV4H_EVENT_OCCURRED2_RTC_15_SHFT		33
4460 #define UV4H_EVENT_OCCURRED2_RTC_16_SHFT		34
4461 #define UV4H_EVENT_OCCURRED2_RTC_17_SHFT		35
4462 #define UV4H_EVENT_OCCURRED2_RTC_18_SHFT		36
4463 #define UV4H_EVENT_OCCURRED2_RTC_19_SHFT		37
4464 #define UV4H_EVENT_OCCURRED2_RTC_20_SHFT		38
4465 #define UV4H_EVENT_OCCURRED2_RTC_21_SHFT		39
4466 #define UV4H_EVENT_OCCURRED2_RTC_22_SHFT		40
4467 #define UV4H_EVENT_OCCURRED2_RTC_23_SHFT		41
4468 #define UV4H_EVENT_OCCURRED2_RTC_24_SHFT		42
4469 #define UV4H_EVENT_OCCURRED2_RTC_25_SHFT		43
4470 #define UV4H_EVENT_OCCURRED2_RTC_26_SHFT		44
4471 #define UV4H_EVENT_OCCURRED2_RTC_27_SHFT		45
4472 #define UV4H_EVENT_OCCURRED2_RTC_28_SHFT		46
4473 #define UV4H_EVENT_OCCURRED2_RTC_29_SHFT		47
4474 #define UV4H_EVENT_OCCURRED2_RTC_30_SHFT		48
4475 #define UV4H_EVENT_OCCURRED2_RTC_31_SHFT		49
4476 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT0_MASK 0x0000000000000001UL
4477 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT1_MASK 0x0000000000000002UL
4478 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT2_MASK 0x0000000000000004UL
4479 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT3_MASK 0x0000000000000008UL
4480 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT4_MASK 0x0000000000000010UL
4481 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT5_MASK 0x0000000000000020UL
4482 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT6_MASK 0x0000000000000040UL
4483 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT7_MASK 0x0000000000000080UL
4484 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT8_MASK 0x0000000000000100UL
4485 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT9_MASK 0x0000000000000200UL
4486 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT10_MASK 0x0000000000000400UL
4487 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT11_MASK 0x0000000000000800UL
4488 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT12_MASK 0x0000000000001000UL
4489 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT13_MASK 0x0000000000002000UL
4490 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT14_MASK 0x0000000000004000UL
4491 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT15_MASK 0x0000000000008000UL
4492 #define UV4H_EVENT_OCCURRED2_RTC_INTERVAL_INT_MASK	0x0000000000010000UL
4493 #define UV4H_EVENT_OCCURRED2_BAU_DASHBOARD_INT_MASK	0x0000000000020000UL
4494 #define UV4H_EVENT_OCCURRED2_RTC_0_MASK			0x0000000000040000UL
4495 #define UV4H_EVENT_OCCURRED2_RTC_1_MASK			0x0000000000080000UL
4496 #define UV4H_EVENT_OCCURRED2_RTC_2_MASK			0x0000000000100000UL
4497 #define UV4H_EVENT_OCCURRED2_RTC_3_MASK			0x0000000000200000UL
4498 #define UV4H_EVENT_OCCURRED2_RTC_4_MASK			0x0000000000400000UL
4499 #define UV4H_EVENT_OCCURRED2_RTC_5_MASK			0x0000000000800000UL
4500 #define UV4H_EVENT_OCCURRED2_RTC_6_MASK			0x0000000001000000UL
4501 #define UV4H_EVENT_OCCURRED2_RTC_7_MASK			0x0000000002000000UL
4502 #define UV4H_EVENT_OCCURRED2_RTC_8_MASK			0x0000000004000000UL
4503 #define UV4H_EVENT_OCCURRED2_RTC_9_MASK			0x0000000008000000UL
4504 #define UV4H_EVENT_OCCURRED2_RTC_10_MASK		0x0000000010000000UL
4505 #define UV4H_EVENT_OCCURRED2_RTC_11_MASK		0x0000000020000000UL
4506 #define UV4H_EVENT_OCCURRED2_RTC_12_MASK		0x0000000040000000UL
4507 #define UV4H_EVENT_OCCURRED2_RTC_13_MASK		0x0000000080000000UL
4508 #define UV4H_EVENT_OCCURRED2_RTC_14_MASK		0x0000000100000000UL
4509 #define UV4H_EVENT_OCCURRED2_RTC_15_MASK		0x0000000200000000UL
4510 #define UV4H_EVENT_OCCURRED2_RTC_16_MASK		0x0000000400000000UL
4511 #define UV4H_EVENT_OCCURRED2_RTC_17_MASK		0x0000000800000000UL
4512 #define UV4H_EVENT_OCCURRED2_RTC_18_MASK		0x0000001000000000UL
4513 #define UV4H_EVENT_OCCURRED2_RTC_19_MASK		0x0000002000000000UL
4514 #define UV4H_EVENT_OCCURRED2_RTC_20_MASK		0x0000004000000000UL
4515 #define UV4H_EVENT_OCCURRED2_RTC_21_MASK		0x0000008000000000UL
4516 #define UV4H_EVENT_OCCURRED2_RTC_22_MASK		0x0000010000000000UL
4517 #define UV4H_EVENT_OCCURRED2_RTC_23_MASK		0x0000020000000000UL
4518 #define UV4H_EVENT_OCCURRED2_RTC_24_MASK		0x0000040000000000UL
4519 #define UV4H_EVENT_OCCURRED2_RTC_25_MASK		0x0000080000000000UL
4520 #define UV4H_EVENT_OCCURRED2_RTC_26_MASK		0x0000100000000000UL
4521 #define UV4H_EVENT_OCCURRED2_RTC_27_MASK		0x0000200000000000UL
4522 #define UV4H_EVENT_OCCURRED2_RTC_28_MASK		0x0000400000000000UL
4523 #define UV4H_EVENT_OCCURRED2_RTC_29_MASK		0x0000800000000000UL
4524 #define UV4H_EVENT_OCCURRED2_RTC_30_MASK		0x0001000000000000UL
4525 #define UV4H_EVENT_OCCURRED2_RTC_31_MASK		0x0002000000000000UL
4526 
4527 #define UVXH_EVENT_OCCURRED2_RTC_1_MASK (				\
4528 	is_uv2_hub() ? UV2H_EVENT_OCCURRED2_RTC_1_MASK :		\
4529 	is_uv3_hub() ? UV3H_EVENT_OCCURRED2_RTC_1_MASK :		\
4530 	/*is_uv4_hub*/ UV4H_EVENT_OCCURRED2_RTC_1_MASK)
4531 
4532 union uvh_event_occurred2_u {
4533 	unsigned long	v;
4534 	struct uv2h_event_occurred2_s {
4535 		unsigned long	rtc_0:1;			/* RW */
4536 		unsigned long	rtc_1:1;			/* RW */
4537 		unsigned long	rtc_2:1;			/* RW */
4538 		unsigned long	rtc_3:1;			/* RW */
4539 		unsigned long	rtc_4:1;			/* RW */
4540 		unsigned long	rtc_5:1;			/* RW */
4541 		unsigned long	rtc_6:1;			/* RW */
4542 		unsigned long	rtc_7:1;			/* RW */
4543 		unsigned long	rtc_8:1;			/* RW */
4544 		unsigned long	rtc_9:1;			/* RW */
4545 		unsigned long	rtc_10:1;			/* RW */
4546 		unsigned long	rtc_11:1;			/* RW */
4547 		unsigned long	rtc_12:1;			/* RW */
4548 		unsigned long	rtc_13:1;			/* RW */
4549 		unsigned long	rtc_14:1;			/* RW */
4550 		unsigned long	rtc_15:1;			/* RW */
4551 		unsigned long	rtc_16:1;			/* RW */
4552 		unsigned long	rtc_17:1;			/* RW */
4553 		unsigned long	rtc_18:1;			/* RW */
4554 		unsigned long	rtc_19:1;			/* RW */
4555 		unsigned long	rtc_20:1;			/* RW */
4556 		unsigned long	rtc_21:1;			/* RW */
4557 		unsigned long	rtc_22:1;			/* RW */
4558 		unsigned long	rtc_23:1;			/* RW */
4559 		unsigned long	rtc_24:1;			/* RW */
4560 		unsigned long	rtc_25:1;			/* RW */
4561 		unsigned long	rtc_26:1;			/* RW */
4562 		unsigned long	rtc_27:1;			/* RW */
4563 		unsigned long	rtc_28:1;			/* RW */
4564 		unsigned long	rtc_29:1;			/* RW */
4565 		unsigned long	rtc_30:1;			/* RW */
4566 		unsigned long	rtc_31:1;			/* RW */
4567 		unsigned long	rsvd_32_63:32;
4568 	} s2;
4569 	struct uv3h_event_occurred2_s {
4570 		unsigned long	rtc_0:1;			/* RW */
4571 		unsigned long	rtc_1:1;			/* RW */
4572 		unsigned long	rtc_2:1;			/* RW */
4573 		unsigned long	rtc_3:1;			/* RW */
4574 		unsigned long	rtc_4:1;			/* RW */
4575 		unsigned long	rtc_5:1;			/* RW */
4576 		unsigned long	rtc_6:1;			/* RW */
4577 		unsigned long	rtc_7:1;			/* RW */
4578 		unsigned long	rtc_8:1;			/* RW */
4579 		unsigned long	rtc_9:1;			/* RW */
4580 		unsigned long	rtc_10:1;			/* RW */
4581 		unsigned long	rtc_11:1;			/* RW */
4582 		unsigned long	rtc_12:1;			/* RW */
4583 		unsigned long	rtc_13:1;			/* RW */
4584 		unsigned long	rtc_14:1;			/* RW */
4585 		unsigned long	rtc_15:1;			/* RW */
4586 		unsigned long	rtc_16:1;			/* RW */
4587 		unsigned long	rtc_17:1;			/* RW */
4588 		unsigned long	rtc_18:1;			/* RW */
4589 		unsigned long	rtc_19:1;			/* RW */
4590 		unsigned long	rtc_20:1;			/* RW */
4591 		unsigned long	rtc_21:1;			/* RW */
4592 		unsigned long	rtc_22:1;			/* RW */
4593 		unsigned long	rtc_23:1;			/* RW */
4594 		unsigned long	rtc_24:1;			/* RW */
4595 		unsigned long	rtc_25:1;			/* RW */
4596 		unsigned long	rtc_26:1;			/* RW */
4597 		unsigned long	rtc_27:1;			/* RW */
4598 		unsigned long	rtc_28:1;			/* RW */
4599 		unsigned long	rtc_29:1;			/* RW */
4600 		unsigned long	rtc_30:1;			/* RW */
4601 		unsigned long	rtc_31:1;			/* RW */
4602 		unsigned long	rsvd_32_63:32;
4603 	} s3;
4604 	struct uv4h_event_occurred2_s {
4605 		unsigned long	message_accelerator_int0:1;	/* RW */
4606 		unsigned long	message_accelerator_int1:1;	/* RW */
4607 		unsigned long	message_accelerator_int2:1;	/* RW */
4608 		unsigned long	message_accelerator_int3:1;	/* RW */
4609 		unsigned long	message_accelerator_int4:1;	/* RW */
4610 		unsigned long	message_accelerator_int5:1;	/* RW */
4611 		unsigned long	message_accelerator_int6:1;	/* RW */
4612 		unsigned long	message_accelerator_int7:1;	/* RW */
4613 		unsigned long	message_accelerator_int8:1;	/* RW */
4614 		unsigned long	message_accelerator_int9:1;	/* RW */
4615 		unsigned long	message_accelerator_int10:1;	/* RW */
4616 		unsigned long	message_accelerator_int11:1;	/* RW */
4617 		unsigned long	message_accelerator_int12:1;	/* RW */
4618 		unsigned long	message_accelerator_int13:1;	/* RW */
4619 		unsigned long	message_accelerator_int14:1;	/* RW */
4620 		unsigned long	message_accelerator_int15:1;	/* RW */
4621 		unsigned long	rtc_interval_int:1;		/* RW */
4622 		unsigned long	bau_dashboard_int:1;		/* RW */
4623 		unsigned long	rtc_0:1;			/* RW */
4624 		unsigned long	rtc_1:1;			/* RW */
4625 		unsigned long	rtc_2:1;			/* RW */
4626 		unsigned long	rtc_3:1;			/* RW */
4627 		unsigned long	rtc_4:1;			/* RW */
4628 		unsigned long	rtc_5:1;			/* RW */
4629 		unsigned long	rtc_6:1;			/* RW */
4630 		unsigned long	rtc_7:1;			/* RW */
4631 		unsigned long	rtc_8:1;			/* RW */
4632 		unsigned long	rtc_9:1;			/* RW */
4633 		unsigned long	rtc_10:1;			/* RW */
4634 		unsigned long	rtc_11:1;			/* RW */
4635 		unsigned long	rtc_12:1;			/* RW */
4636 		unsigned long	rtc_13:1;			/* RW */
4637 		unsigned long	rtc_14:1;			/* RW */
4638 		unsigned long	rtc_15:1;			/* RW */
4639 		unsigned long	rtc_16:1;			/* RW */
4640 		unsigned long	rtc_17:1;			/* RW */
4641 		unsigned long	rtc_18:1;			/* RW */
4642 		unsigned long	rtc_19:1;			/* RW */
4643 		unsigned long	rtc_20:1;			/* RW */
4644 		unsigned long	rtc_21:1;			/* RW */
4645 		unsigned long	rtc_22:1;			/* RW */
4646 		unsigned long	rtc_23:1;			/* RW */
4647 		unsigned long	rtc_24:1;			/* RW */
4648 		unsigned long	rtc_25:1;			/* RW */
4649 		unsigned long	rtc_26:1;			/* RW */
4650 		unsigned long	rtc_27:1;			/* RW */
4651 		unsigned long	rtc_28:1;			/* RW */
4652 		unsigned long	rtc_29:1;			/* RW */
4653 		unsigned long	rtc_30:1;			/* RW */
4654 		unsigned long	rtc_31:1;			/* RW */
4655 		unsigned long	rsvd_50_63:14;
4656 	} s4;
4657 };
4658 
4659 /* ========================================================================= */
4660 /*                       UVXH_EVENT_OCCURRED2_ALIAS                          */
4661 /* ========================================================================= */
4662 #define UVXH_EVENT_OCCURRED2_ALIAS 0x70108UL
4663 
4664 #define UV2H_EVENT_OCCURRED2_ALIAS_32 0xb70
4665 #define UV3H_EVENT_OCCURRED2_ALIAS_32 0xb70
4666 #define UV4H_EVENT_OCCURRED2_ALIAS_32 0x610
4667 #define UVH_EVENT_OCCURRED2_ALIAS_32 (					\
4668 	is_uv2_hub() ? UV2H_EVENT_OCCURRED2_ALIAS_32 :			\
4669 	is_uv3_hub() ? UV3H_EVENT_OCCURRED2_ALIAS_32 :			\
4670 	/*is_uv4_hub*/ UV4H_EVENT_OCCURRED2_ALIAS_32)
4671 
4672 
4673 /* ========================================================================= */
4674 /*                   UVXH_LB_BAU_SB_ACTIVATION_STATUS_2                      */
4675 /* ========================================================================= */
4676 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL
4677 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL
4678 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2 0xc8130UL
4679 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_2 (				\
4680 	is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 :		\
4681 	is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_2 :		\
4682 	/*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_2)
4683 
4684 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0
4685 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0
4686 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0xa10
4687 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_2_32 (				\
4688 	is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 :		\
4689 	is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_32 :		\
4690 	/*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_32)
4691 
4692 #define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0
4693 #define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL
4694 
4695 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0
4696 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL
4697 
4698 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0
4699 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL
4700 
4701 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0
4702 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL
4703 
4704 
4705 union uvxh_lb_bau_sb_activation_status_2_u {
4706 	unsigned long	v;
4707 	struct uvxh_lb_bau_sb_activation_status_2_s {
4708 		unsigned long	aux_error:64;			/* RW */
4709 	} sx;
4710 	struct uv2h_lb_bau_sb_activation_status_2_s {
4711 		unsigned long	aux_error:64;			/* RW */
4712 	} s2;
4713 	struct uv3h_lb_bau_sb_activation_status_2_s {
4714 		unsigned long	aux_error:64;			/* RW */
4715 	} s3;
4716 	struct uv4h_lb_bau_sb_activation_status_2_s {
4717 		unsigned long	aux_error:64;			/* RW */
4718 	} s4;
4719 };
4720 
4721 /* ========================================================================= */
4722 /*                   UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK                    */
4723 /* ========================================================================= */
4724 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK		0x320130UL
4725 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_32		0x9f0
4726 
4727 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_SHFT 0
4728 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_MASK 0x00000000ffffffffUL
4729 
4730 union uv1h_lb_target_physical_apic_id_mask_u {
4731 	unsigned long	v;
4732 	struct uv1h_lb_target_physical_apic_id_mask_s {
4733 		unsigned long	bit_enables:32;			/* RW */
4734 		unsigned long	rsvd_32_63:32;
4735 	} s1;
4736 };
4737 
4738 /* ========================================================================= */
4739 /*                          UV3H_GR0_GAM_GR_CONFIG                           */
4740 /* ========================================================================= */
4741 #define UV3H_GR0_GAM_GR_CONFIG				0xc00028UL
4742 
4743 #define UV3H_GR0_GAM_GR_CONFIG_M_SKT_SHFT		0
4744 #define UV3H_GR0_GAM_GR_CONFIG_SUBSPACE_SHFT		10
4745 #define UV3H_GR0_GAM_GR_CONFIG_M_SKT_MASK		0x000000000000003fUL
4746 #define UV3H_GR0_GAM_GR_CONFIG_SUBSPACE_MASK		0x0000000000000400UL
4747 
4748 union uv3h_gr0_gam_gr_config_u {
4749 	unsigned long	v;
4750 	struct uv3h_gr0_gam_gr_config_s {
4751 		unsigned long	m_skt:6;			/* RW */
4752 		unsigned long	undef_6_9:4;			/* Undefined */
4753 		unsigned long	subspace:1;			/* RW */
4754 		unsigned long	reserved:53;
4755 	} s3;
4756 };
4757 
4758 /* ========================================================================= */
4759 /*                       UV4H_LB_PROC_INTD_QUEUE_FIRST                       */
4760 /* ========================================================================= */
4761 #define UV4H_LB_PROC_INTD_QUEUE_FIRST			0xa4100UL
4762 
4763 #define UV4H_LB_PROC_INTD_QUEUE_FIRST_FIRST_PAYLOAD_ADDRESS_SHFT 6
4764 #define UV4H_LB_PROC_INTD_QUEUE_FIRST_FIRST_PAYLOAD_ADDRESS_MASK 0x00003fffffffffc0UL
4765 
4766 union uv4h_lb_proc_intd_queue_first_u {
4767 	unsigned long	v;
4768 	struct uv4h_lb_proc_intd_queue_first_s {
4769 		unsigned long	undef_0_5:6;			/* Undefined */
4770 		unsigned long	first_payload_address:40;	/* RW */
4771 	} s4;
4772 };
4773 
4774 /* ========================================================================= */
4775 /*                       UV4H_LB_PROC_INTD_QUEUE_LAST                        */
4776 /* ========================================================================= */
4777 #define UV4H_LB_PROC_INTD_QUEUE_LAST			0xa4108UL
4778 
4779 #define UV4H_LB_PROC_INTD_QUEUE_LAST_LAST_PAYLOAD_ADDRESS_SHFT 5
4780 #define UV4H_LB_PROC_INTD_QUEUE_LAST_LAST_PAYLOAD_ADDRESS_MASK 0x00003fffffffffe0UL
4781 
4782 union uv4h_lb_proc_intd_queue_last_u {
4783 	unsigned long	v;
4784 	struct uv4h_lb_proc_intd_queue_last_s {
4785 		unsigned long	undef_0_4:5;			/* Undefined */
4786 		unsigned long	last_payload_address:41;	/* RW */
4787 	} s4;
4788 };
4789 
4790 /* ========================================================================= */
4791 /*                     UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR                      */
4792 /* ========================================================================= */
4793 #define UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR		0xa4118UL
4794 
4795 #define UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR_SOFT_ACK_PENDING_FLAGS_SHFT 0
4796 #define UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR_SOFT_ACK_PENDING_FLAGS_MASK 0x00000000000000ffUL
4797 
4798 union uv4h_lb_proc_intd_soft_ack_clear_u {
4799 	unsigned long	v;
4800 	struct uv4h_lb_proc_intd_soft_ack_clear_s {
4801 		unsigned long	soft_ack_pending_flags:8;	/* WP */
4802 	} s4;
4803 };
4804 
4805 /* ========================================================================= */
4806 /*                    UV4H_LB_PROC_INTD_SOFT_ACK_PENDING                     */
4807 /* ========================================================================= */
4808 #define UV4H_LB_PROC_INTD_SOFT_ACK_PENDING		0xa4110UL
4809 
4810 #define UV4H_LB_PROC_INTD_SOFT_ACK_PENDING_SOFT_ACK_FLAGS_SHFT 0
4811 #define UV4H_LB_PROC_INTD_SOFT_ACK_PENDING_SOFT_ACK_FLAGS_MASK 0x00000000000000ffUL
4812 
4813 union uv4h_lb_proc_intd_soft_ack_pending_u {
4814 	unsigned long	v;
4815 	struct uv4h_lb_proc_intd_soft_ack_pending_s {
4816 		unsigned long	soft_ack_flags:8;		/* RW */
4817 	} s4;
4818 };
4819 
4820 
4821 #endif /* _ASM_X86_UV_UV_MMRS_H */
4822