1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * SGI UV MMR definitions 7 * 8 * Copyright (C) 2007-2016 Silicon Graphics, Inc. All rights reserved. 9 */ 10 11 #ifndef _ASM_X86_UV_UV_MMRS_H 12 #define _ASM_X86_UV_UV_MMRS_H 13 14 /* 15 * This file contains MMR definitions for all UV hubs types. 16 * 17 * To minimize coding differences between hub types, the symbols are 18 * grouped by architecture types. 19 * 20 * UVH - definitions common to all UV hub types. 21 * UVXH - definitions common to all UV eXtended hub types (currently 2, 3, 4). 22 * UV1H - definitions specific to UV type 1 hub. 23 * UV2H - definitions specific to UV type 2 hub. 24 * UV3H - definitions specific to UV type 3 hub. 25 * UV4H - definitions specific to UV type 4 hub. 26 * 27 * So in general, MMR addresses and structures are identical on all hubs types. 28 * These MMRs are identified as: 29 * #define UVH_xxx <address> 30 * union uvh_xxx { 31 * unsigned long v; 32 * struct uvh_int_cmpd_s { 33 * } s; 34 * }; 35 * 36 * If the MMR exists on all hub types but have different addresses, 37 * use a conditional operator to define the value at runtime. 38 * #define UV1Hxxx a 39 * #define UV2Hxxx b 40 * #define UV3Hxxx c 41 * #define UV4Hxxx d 42 * #define UVHxxx (is_uv1_hub() ? UV1Hxxx : 43 * (is_uv2_hub() ? UV2Hxxx : 44 * (is_uv3_hub() ? UV3Hxxx : 45 * UV4Hxxx)) 46 * 47 * If the MMR exists on all hub types > 1 but have different addresses, the 48 * variation using "UVX" as the prefix exists. 49 * #define UV2Hxxx b 50 * #define UV3Hxxx c 51 * #define UV4Hxxx d 52 * #define UVHxxx (is_uv2_hub() ? UV2Hxxx : 53 * (is_uv3_hub() ? UV3Hxxx : 54 * UV4Hxxx)) 55 * 56 * union uvh_xxx { 57 * unsigned long v; 58 * struct uvh_xxx_s { # Common fields only 59 * } s; 60 * struct uv1h_xxx_s { # Full UV1 definition (*) 61 * } s1; 62 * struct uv2h_xxx_s { # Full UV2 definition (*) 63 * } s2; 64 * struct uv3h_xxx_s { # Full UV3 definition (*) 65 * } s3; 66 * struct uv4h_xxx_s { # Full UV4 definition (*) 67 * } s4; 68 * }; 69 * (* - if present and different than the common struct) 70 * 71 * Only essential differences are enumerated. For example, if the address is 72 * the same for all UV's, only a single #define is generated. Likewise, 73 * if the contents is the same for all hubs, only the "s" structure is 74 * generated. 75 * 76 * If the MMR exists on ONLY 1 type of hub, no generic definition is 77 * generated: 78 * #define UVnH_xxx <uvn address> 79 * union uvnh_xxx { 80 * unsigned long v; 81 * struct uvh_int_cmpd_s { 82 * } sn; 83 * }; 84 * 85 * (GEN Flags: mflags_opt= undefs=function UV234=UVXH) 86 */ 87 88 #define UV_MMR_ENABLE (1UL << 63) 89 90 #define UV1_HUB_PART_NUMBER 0x88a5 91 #define UV2_HUB_PART_NUMBER 0x8eb8 92 #define UV2_HUB_PART_NUMBER_X 0x1111 93 #define UV3_HUB_PART_NUMBER 0x9578 94 #define UV3_HUB_PART_NUMBER_X 0x4321 95 #define UV4_HUB_PART_NUMBER 0x99a1 96 97 /* Compat: Indicate which UV Hubs are supported. */ 98 #define UV1_HUB_IS_SUPPORTED 1 99 #define UV2_HUB_IS_SUPPORTED 1 100 #define UV3_HUB_IS_SUPPORTED 1 101 #define UV4_HUB_IS_SUPPORTED 1 102 #define UV4A_HUB_IS_SUPPORTED 1 103 104 /* Error function to catch undefined references */ 105 extern unsigned long uv_undefined(char *str); 106 107 /* ========================================================================= */ 108 /* UVH_BAU_DATA_BROADCAST */ 109 /* ========================================================================= */ 110 #define UVH_BAU_DATA_BROADCAST 0x61688UL 111 112 #define UV1H_BAU_DATA_BROADCAST_32 0x440 113 #define UV2H_BAU_DATA_BROADCAST_32 0x440 114 #define UV3H_BAU_DATA_BROADCAST_32 0x440 115 #define UV4H_BAU_DATA_BROADCAST_32 0x360 116 #define UVH_BAU_DATA_BROADCAST_32 ( \ 117 is_uv1_hub() ? UV1H_BAU_DATA_BROADCAST_32 : \ 118 is_uv2_hub() ? UV2H_BAU_DATA_BROADCAST_32 : \ 119 is_uv3_hub() ? UV3H_BAU_DATA_BROADCAST_32 : \ 120 /*is_uv4_hub*/ UV4H_BAU_DATA_BROADCAST_32) 121 122 #define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT 0 123 #define UVH_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL 124 125 126 union uvh_bau_data_broadcast_u { 127 unsigned long v; 128 struct uvh_bau_data_broadcast_s { 129 unsigned long enable:1; /* RW */ 130 unsigned long rsvd_1_63:63; 131 } s; 132 }; 133 134 /* ========================================================================= */ 135 /* UVH_BAU_DATA_CONFIG */ 136 /* ========================================================================= */ 137 #define UVH_BAU_DATA_CONFIG 0x61680UL 138 139 #define UV1H_BAU_DATA_CONFIG_32 0x438 140 #define UV2H_BAU_DATA_CONFIG_32 0x438 141 #define UV3H_BAU_DATA_CONFIG_32 0x438 142 #define UV4H_BAU_DATA_CONFIG_32 0x358 143 #define UVH_BAU_DATA_CONFIG_32 ( \ 144 is_uv1_hub() ? UV1H_BAU_DATA_CONFIG_32 : \ 145 is_uv2_hub() ? UV2H_BAU_DATA_CONFIG_32 : \ 146 is_uv3_hub() ? UV3H_BAU_DATA_CONFIG_32 : \ 147 /*is_uv4_hub*/ UV4H_BAU_DATA_CONFIG_32) 148 149 #define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0 150 #define UVH_BAU_DATA_CONFIG_DM_SHFT 8 151 #define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT 11 152 #define UVH_BAU_DATA_CONFIG_STATUS_SHFT 12 153 #define UVH_BAU_DATA_CONFIG_P_SHFT 13 154 #define UVH_BAU_DATA_CONFIG_T_SHFT 15 155 #define UVH_BAU_DATA_CONFIG_M_SHFT 16 156 #define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT 32 157 #define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL 158 #define UVH_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL 159 #define UVH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL 160 #define UVH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL 161 #define UVH_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL 162 #define UVH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL 163 #define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL 164 #define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 165 166 167 union uvh_bau_data_config_u { 168 unsigned long v; 169 struct uvh_bau_data_config_s { 170 unsigned long vector_:8; /* RW */ 171 unsigned long dm:3; /* RW */ 172 unsigned long destmode:1; /* RW */ 173 unsigned long status:1; /* RO */ 174 unsigned long p:1; /* RO */ 175 unsigned long rsvd_14:1; 176 unsigned long t:1; /* RO */ 177 unsigned long m:1; /* RW */ 178 unsigned long rsvd_17_31:15; 179 unsigned long apic_id:32; /* RW */ 180 } s; 181 }; 182 183 /* ========================================================================= */ 184 /* UVH_EVENT_OCCURRED0 */ 185 /* ========================================================================= */ 186 #define UVH_EVENT_OCCURRED0 0x70000UL 187 #define UVH_EVENT_OCCURRED0_32 0x5e8 188 189 #define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT 0 190 #define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT 11 191 #define UVH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL 192 #define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL 193 194 #define UV1H_EVENT_OCCURRED0_GR0_HCERR_SHFT 1 195 #define UV1H_EVENT_OCCURRED0_GR1_HCERR_SHFT 2 196 #define UV1H_EVENT_OCCURRED0_LH_HCERR_SHFT 3 197 #define UV1H_EVENT_OCCURRED0_RH_HCERR_SHFT 4 198 #define UV1H_EVENT_OCCURRED0_XN_HCERR_SHFT 5 199 #define UV1H_EVENT_OCCURRED0_SI_HCERR_SHFT 6 200 #define UV1H_EVENT_OCCURRED0_LB_AOERR0_SHFT 7 201 #define UV1H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8 202 #define UV1H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9 203 #define UV1H_EVENT_OCCURRED0_LH_AOERR0_SHFT 10 204 #define UV1H_EVENT_OCCURRED0_XN_AOERR0_SHFT 12 205 #define UV1H_EVENT_OCCURRED0_SI_AOERR0_SHFT 13 206 #define UV1H_EVENT_OCCURRED0_LB_AOERR1_SHFT 14 207 #define UV1H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15 208 #define UV1H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16 209 #define UV1H_EVENT_OCCURRED0_LH_AOERR1_SHFT 17 210 #define UV1H_EVENT_OCCURRED0_RH_AOERR1_SHFT 18 211 #define UV1H_EVENT_OCCURRED0_XN_AOERR1_SHFT 19 212 #define UV1H_EVENT_OCCURRED0_SI_AOERR1_SHFT 20 213 #define UV1H_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21 214 #define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22 215 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23 216 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24 217 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25 218 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26 219 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27 220 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28 221 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29 222 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30 223 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31 224 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32 225 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33 226 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34 227 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35 228 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36 229 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37 230 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38 231 #define UV1H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39 232 #define UV1H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40 233 #define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41 234 #define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42 235 #define UV1H_EVENT_OCCURRED0_LTC_INT_SHFT 43 236 #define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44 237 #define UV1H_EVENT_OCCURRED0_IPI_INT_SHFT 45 238 #define UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46 239 #define UV1H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47 240 #define UV1H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48 241 #define UV1H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49 242 #define UV1H_EVENT_OCCURRED0_PROFILE_INT_SHFT 50 243 #define UV1H_EVENT_OCCURRED0_RTC0_SHFT 51 244 #define UV1H_EVENT_OCCURRED0_RTC1_SHFT 52 245 #define UV1H_EVENT_OCCURRED0_RTC2_SHFT 53 246 #define UV1H_EVENT_OCCURRED0_RTC3_SHFT 54 247 #define UV1H_EVENT_OCCURRED0_BAU_DATA_SHFT 55 248 #define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56 249 #define UV1H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL 250 #define UV1H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL 251 #define UV1H_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL 252 #define UV1H_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL 253 #define UV1H_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL 254 #define UV1H_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL 255 #define UV1H_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL 256 #define UV1H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL 257 #define UV1H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL 258 #define UV1H_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL 259 #define UV1H_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL 260 #define UV1H_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL 261 #define UV1H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL 262 #define UV1H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL 263 #define UV1H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL 264 #define UV1H_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL 265 #define UV1H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL 266 #define UV1H_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL 267 #define UV1H_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL 268 #define UV1H_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL 269 #define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL 270 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL 271 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL 272 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL 273 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL 274 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL 275 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL 276 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL 277 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL 278 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL 279 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL 280 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL 281 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL 282 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL 283 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL 284 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL 285 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL 286 #define UV1H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL 287 #define UV1H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL 288 #define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL 289 #define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL 290 #define UV1H_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL 291 #define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL 292 #define UV1H_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL 293 #define UV1H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL 294 #define UV1H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL 295 #define UV1H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL 296 #define UV1H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL 297 #define UV1H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL 298 #define UV1H_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL 299 #define UV1H_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL 300 #define UV1H_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL 301 #define UV1H_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL 302 #define UV1H_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL 303 #define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL 304 305 #define UVXH_EVENT_OCCURRED0_RH_HCERR_SHFT 2 306 #define UVXH_EVENT_OCCURRED0_LH0_HCERR_SHFT 3 307 #define UVXH_EVENT_OCCURRED0_LH1_HCERR_SHFT 4 308 #define UVXH_EVENT_OCCURRED0_GR0_HCERR_SHFT 5 309 #define UVXH_EVENT_OCCURRED0_GR1_HCERR_SHFT 6 310 #define UVXH_EVENT_OCCURRED0_NI0_HCERR_SHFT 7 311 #define UVXH_EVENT_OCCURRED0_NI1_HCERR_SHFT 8 312 #define UVXH_EVENT_OCCURRED0_LB_AOERR0_SHFT 9 313 #define UVXH_EVENT_OCCURRED0_LH0_AOERR0_SHFT 12 314 #define UVXH_EVENT_OCCURRED0_LH1_AOERR0_SHFT 13 315 #define UVXH_EVENT_OCCURRED0_GR0_AOERR0_SHFT 14 316 #define UVXH_EVENT_OCCURRED0_GR1_AOERR0_SHFT 15 317 #define UVXH_EVENT_OCCURRED0_XB_AOERR0_SHFT 16 318 #define UVXH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000004UL 319 #define UVXH_EVENT_OCCURRED0_LH0_HCERR_MASK 0x0000000000000008UL 320 #define UVXH_EVENT_OCCURRED0_LH1_HCERR_MASK 0x0000000000000010UL 321 #define UVXH_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000020UL 322 #define UVXH_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000040UL 323 #define UVXH_EVENT_OCCURRED0_NI0_HCERR_MASK 0x0000000000000080UL 324 #define UVXH_EVENT_OCCURRED0_NI1_HCERR_MASK 0x0000000000000100UL 325 #define UVXH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000200UL 326 #define UVXH_EVENT_OCCURRED0_LH0_AOERR0_MASK 0x0000000000001000UL 327 #define UVXH_EVENT_OCCURRED0_LH1_AOERR0_MASK 0x0000000000002000UL 328 #define UVXH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000004000UL 329 #define UVXH_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000008000UL 330 #define UVXH_EVENT_OCCURRED0_XB_AOERR0_MASK 0x0000000000010000UL 331 332 #define UV2H_EVENT_OCCURRED0_QP_HCERR_SHFT 1 333 #define UV2H_EVENT_OCCURRED0_QP_AOERR0_SHFT 10 334 #define UV2H_EVENT_OCCURRED0_RT_AOERR0_SHFT 17 335 #define UV2H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18 336 #define UV2H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19 337 #define UV2H_EVENT_OCCURRED0_LB_AOERR1_SHFT 20 338 #define UV2H_EVENT_OCCURRED0_QP_AOERR1_SHFT 21 339 #define UV2H_EVENT_OCCURRED0_RH_AOERR1_SHFT 22 340 #define UV2H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23 341 #define UV2H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24 342 #define UV2H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25 343 #define UV2H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26 344 #define UV2H_EVENT_OCCURRED0_XB_AOERR1_SHFT 27 345 #define UV2H_EVENT_OCCURRED0_RT_AOERR1_SHFT 28 346 #define UV2H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29 347 #define UV2H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30 348 #define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31 349 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32 350 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33 351 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34 352 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35 353 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36 354 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37 355 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38 356 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39 357 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40 358 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41 359 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42 360 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43 361 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44 362 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45 363 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46 364 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47 365 #define UV2H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48 366 #define UV2H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49 367 #define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50 368 #define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51 369 #define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52 370 #define UV2H_EVENT_OCCURRED0_IPI_INT_SHFT 53 371 #define UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54 372 #define UV2H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55 373 #define UV2H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56 374 #define UV2H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57 375 #define UV2H_EVENT_OCCURRED0_PROFILE_INT_SHFT 58 376 #define UV2H_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL 377 #define UV2H_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL 378 #define UV2H_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL 379 #define UV2H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL 380 #define UV2H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL 381 #define UV2H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL 382 #define UV2H_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL 383 #define UV2H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL 384 #define UV2H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL 385 #define UV2H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL 386 #define UV2H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL 387 #define UV2H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL 388 #define UV2H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL 389 #define UV2H_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL 390 #define UV2H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL 391 #define UV2H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL 392 #define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL 393 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL 394 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL 395 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL 396 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL 397 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL 398 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL 399 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL 400 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL 401 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL 402 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL 403 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL 404 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL 405 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL 406 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL 407 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL 408 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL 409 #define UV2H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL 410 #define UV2H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL 411 #define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL 412 #define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL 413 #define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL 414 #define UV2H_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL 415 #define UV2H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL 416 #define UV2H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL 417 #define UV2H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL 418 #define UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL 419 #define UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL 420 421 #define UV3H_EVENT_OCCURRED0_QP_HCERR_SHFT 1 422 #define UV3H_EVENT_OCCURRED0_QP_AOERR0_SHFT 10 423 #define UV3H_EVENT_OCCURRED0_RT_AOERR0_SHFT 17 424 #define UV3H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18 425 #define UV3H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19 426 #define UV3H_EVENT_OCCURRED0_LB_AOERR1_SHFT 20 427 #define UV3H_EVENT_OCCURRED0_QP_AOERR1_SHFT 21 428 #define UV3H_EVENT_OCCURRED0_RH_AOERR1_SHFT 22 429 #define UV3H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23 430 #define UV3H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24 431 #define UV3H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25 432 #define UV3H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26 433 #define UV3H_EVENT_OCCURRED0_XB_AOERR1_SHFT 27 434 #define UV3H_EVENT_OCCURRED0_RT_AOERR1_SHFT 28 435 #define UV3H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29 436 #define UV3H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30 437 #define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31 438 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32 439 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33 440 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34 441 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35 442 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36 443 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37 444 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38 445 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39 446 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40 447 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41 448 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42 449 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43 450 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44 451 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45 452 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46 453 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47 454 #define UV3H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48 455 #define UV3H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49 456 #define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50 457 #define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51 458 #define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52 459 #define UV3H_EVENT_OCCURRED0_IPI_INT_SHFT 53 460 #define UV3H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54 461 #define UV3H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55 462 #define UV3H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56 463 #define UV3H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57 464 #define UV3H_EVENT_OCCURRED0_PROFILE_INT_SHFT 58 465 #define UV3H_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL 466 #define UV3H_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL 467 #define UV3H_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL 468 #define UV3H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL 469 #define UV3H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL 470 #define UV3H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL 471 #define UV3H_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL 472 #define UV3H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL 473 #define UV3H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL 474 #define UV3H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL 475 #define UV3H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL 476 #define UV3H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL 477 #define UV3H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL 478 #define UV3H_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL 479 #define UV3H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL 480 #define UV3H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL 481 #define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL 482 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL 483 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL 484 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL 485 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL 486 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL 487 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL 488 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL 489 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL 490 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL 491 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL 492 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL 493 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL 494 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL 495 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL 496 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL 497 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL 498 #define UV3H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL 499 #define UV3H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL 500 #define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL 501 #define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL 502 #define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL 503 #define UV3H_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL 504 #define UV3H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL 505 #define UV3H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL 506 #define UV3H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL 507 #define UV3H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL 508 #define UV3H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL 509 510 #define UV4H_EVENT_OCCURRED0_KT_HCERR_SHFT 1 511 #define UV4H_EVENT_OCCURRED0_KT_AOERR0_SHFT 10 512 #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR0_SHFT 17 513 #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR0_SHFT 18 514 #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR0_SHFT 19 515 #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR0_SHFT 20 516 #define UV4H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 21 517 #define UV4H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 22 518 #define UV4H_EVENT_OCCURRED0_LB_AOERR1_SHFT 23 519 #define UV4H_EVENT_OCCURRED0_KT_AOERR1_SHFT 24 520 #define UV4H_EVENT_OCCURRED0_RH_AOERR1_SHFT 25 521 #define UV4H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 26 522 #define UV4H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 27 523 #define UV4H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 28 524 #define UV4H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 29 525 #define UV4H_EVENT_OCCURRED0_XB_AOERR1_SHFT 30 526 #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR1_SHFT 31 527 #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR1_SHFT 32 528 #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR1_SHFT 33 529 #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR1_SHFT 34 530 #define UV4H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 35 531 #define UV4H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 36 532 #define UV4H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 37 533 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 38 534 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 39 535 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 40 536 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 41 537 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 42 538 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 43 539 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 44 540 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 45 541 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 46 542 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 47 543 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 48 544 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 49 545 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 50 546 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 51 547 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 52 548 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 53 549 #define UV4H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 54 550 #define UV4H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 55 551 #define UV4H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 56 552 #define UV4H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 57 553 #define UV4H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 58 554 #define UV4H_EVENT_OCCURRED0_IPI_INT_SHFT 59 555 #define UV4H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 60 556 #define UV4H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 61 557 #define UV4H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 62 558 #define UV4H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 63 559 #define UV4H_EVENT_OCCURRED0_KT_HCERR_MASK 0x0000000000000002UL 560 #define UV4H_EVENT_OCCURRED0_KT_AOERR0_MASK 0x0000000000000400UL 561 #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR0_MASK 0x0000000000020000UL 562 #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR0_MASK 0x0000000000040000UL 563 #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR0_MASK 0x0000000000080000UL 564 #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR0_MASK 0x0000000000100000UL 565 #define UV4H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000200000UL 566 #define UV4H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000400000UL 567 #define UV4H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000800000UL 568 #define UV4H_EVENT_OCCURRED0_KT_AOERR1_MASK 0x0000000001000000UL 569 #define UV4H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000002000000UL 570 #define UV4H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000004000000UL 571 #define UV4H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000008000000UL 572 #define UV4H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000010000000UL 573 #define UV4H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000020000000UL 574 #define UV4H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000040000000UL 575 #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR1_MASK 0x0000000080000000UL 576 #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR1_MASK 0x0000000100000000UL 577 #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR1_MASK 0x0000000200000000UL 578 #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR1_MASK 0x0000000400000000UL 579 #define UV4H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000800000000UL 580 #define UV4H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000001000000000UL 581 #define UV4H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000002000000000UL 582 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000004000000000UL 583 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000008000000000UL 584 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000010000000000UL 585 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000020000000000UL 586 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000040000000000UL 587 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000080000000000UL 588 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000100000000000UL 589 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000200000000000UL 590 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000400000000000UL 591 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000800000000000UL 592 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0001000000000000UL 593 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0002000000000000UL 594 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0004000000000000UL 595 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0008000000000000UL 596 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0010000000000000UL 597 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0020000000000000UL 598 #define UV4H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0040000000000000UL 599 #define UV4H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0080000000000000UL 600 #define UV4H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0100000000000000UL 601 #define UV4H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0200000000000000UL 602 #define UV4H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0400000000000000UL 603 #define UV4H_EVENT_OCCURRED0_IPI_INT_MASK 0x0800000000000000UL 604 #define UV4H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x1000000000000000UL 605 #define UV4H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x2000000000000000UL 606 #define UV4H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x4000000000000000UL 607 #define UV4H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x8000000000000000UL 608 609 #define UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT ( \ 610 is_uv1_hub() ? UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT : \ 611 is_uv2_hub() ? UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT : \ 612 is_uv3_hub() ? UV3H_EVENT_OCCURRED0_EXTIO_INT0_SHFT : \ 613 /*is_uv4_hub*/ UV4H_EVENT_OCCURRED0_EXTIO_INT0_SHFT) 614 615 union uvh_event_occurred0_u { 616 unsigned long v; 617 struct uvh_event_occurred0_s { 618 unsigned long lb_hcerr:1; /* RW, W1C */ 619 unsigned long rsvd_1_10:10; 620 unsigned long rh_aoerr0:1; /* RW, W1C */ 621 unsigned long rsvd_12_63:52; 622 } s; 623 struct uvxh_event_occurred0_s { 624 unsigned long lb_hcerr:1; /* RW */ 625 unsigned long rsvd_1:1; 626 unsigned long rh_hcerr:1; /* RW */ 627 unsigned long lh0_hcerr:1; /* RW */ 628 unsigned long lh1_hcerr:1; /* RW */ 629 unsigned long gr0_hcerr:1; /* RW */ 630 unsigned long gr1_hcerr:1; /* RW */ 631 unsigned long ni0_hcerr:1; /* RW */ 632 unsigned long ni1_hcerr:1; /* RW */ 633 unsigned long lb_aoerr0:1; /* RW */ 634 unsigned long rsvd_10:1; 635 unsigned long rh_aoerr0:1; /* RW */ 636 unsigned long lh0_aoerr0:1; /* RW */ 637 unsigned long lh1_aoerr0:1; /* RW */ 638 unsigned long gr0_aoerr0:1; /* RW */ 639 unsigned long gr1_aoerr0:1; /* RW */ 640 unsigned long xb_aoerr0:1; /* RW */ 641 unsigned long rsvd_17_63:47; 642 } sx; 643 struct uv4h_event_occurred0_s { 644 unsigned long lb_hcerr:1; /* RW */ 645 unsigned long kt_hcerr:1; /* RW */ 646 unsigned long rh_hcerr:1; /* RW */ 647 unsigned long lh0_hcerr:1; /* RW */ 648 unsigned long lh1_hcerr:1; /* RW */ 649 unsigned long gr0_hcerr:1; /* RW */ 650 unsigned long gr1_hcerr:1; /* RW */ 651 unsigned long ni0_hcerr:1; /* RW */ 652 unsigned long ni1_hcerr:1; /* RW */ 653 unsigned long lb_aoerr0:1; /* RW */ 654 unsigned long kt_aoerr0:1; /* RW */ 655 unsigned long rh_aoerr0:1; /* RW */ 656 unsigned long lh0_aoerr0:1; /* RW */ 657 unsigned long lh1_aoerr0:1; /* RW */ 658 unsigned long gr0_aoerr0:1; /* RW */ 659 unsigned long gr1_aoerr0:1; /* RW */ 660 unsigned long xb_aoerr0:1; /* RW */ 661 unsigned long rtq0_aoerr0:1; /* RW */ 662 unsigned long rtq1_aoerr0:1; /* RW */ 663 unsigned long rtq2_aoerr0:1; /* RW */ 664 unsigned long rtq3_aoerr0:1; /* RW */ 665 unsigned long ni0_aoerr0:1; /* RW */ 666 unsigned long ni1_aoerr0:1; /* RW */ 667 unsigned long lb_aoerr1:1; /* RW */ 668 unsigned long kt_aoerr1:1; /* RW */ 669 unsigned long rh_aoerr1:1; /* RW */ 670 unsigned long lh0_aoerr1:1; /* RW */ 671 unsigned long lh1_aoerr1:1; /* RW */ 672 unsigned long gr0_aoerr1:1; /* RW */ 673 unsigned long gr1_aoerr1:1; /* RW */ 674 unsigned long xb_aoerr1:1; /* RW */ 675 unsigned long rtq0_aoerr1:1; /* RW */ 676 unsigned long rtq1_aoerr1:1; /* RW */ 677 unsigned long rtq2_aoerr1:1; /* RW */ 678 unsigned long rtq3_aoerr1:1; /* RW */ 679 unsigned long ni0_aoerr1:1; /* RW */ 680 unsigned long ni1_aoerr1:1; /* RW */ 681 unsigned long system_shutdown_int:1; /* RW */ 682 unsigned long lb_irq_int_0:1; /* RW */ 683 unsigned long lb_irq_int_1:1; /* RW */ 684 unsigned long lb_irq_int_2:1; /* RW */ 685 unsigned long lb_irq_int_3:1; /* RW */ 686 unsigned long lb_irq_int_4:1; /* RW */ 687 unsigned long lb_irq_int_5:1; /* RW */ 688 unsigned long lb_irq_int_6:1; /* RW */ 689 unsigned long lb_irq_int_7:1; /* RW */ 690 unsigned long lb_irq_int_8:1; /* RW */ 691 unsigned long lb_irq_int_9:1; /* RW */ 692 unsigned long lb_irq_int_10:1; /* RW */ 693 unsigned long lb_irq_int_11:1; /* RW */ 694 unsigned long lb_irq_int_12:1; /* RW */ 695 unsigned long lb_irq_int_13:1; /* RW */ 696 unsigned long lb_irq_int_14:1; /* RW */ 697 unsigned long lb_irq_int_15:1; /* RW */ 698 unsigned long l1_nmi_int:1; /* RW */ 699 unsigned long stop_clock:1; /* RW */ 700 unsigned long asic_to_l1:1; /* RW */ 701 unsigned long l1_to_asic:1; /* RW */ 702 unsigned long la_seq_trigger:1; /* RW */ 703 unsigned long ipi_int:1; /* RW */ 704 unsigned long extio_int0:1; /* RW */ 705 unsigned long extio_int1:1; /* RW */ 706 unsigned long extio_int2:1; /* RW */ 707 unsigned long extio_int3:1; /* RW */ 708 } s4; 709 }; 710 711 /* ========================================================================= */ 712 /* UVH_EVENT_OCCURRED0_ALIAS */ 713 /* ========================================================================= */ 714 #define UVH_EVENT_OCCURRED0_ALIAS 0x70008UL 715 #define UVH_EVENT_OCCURRED0_ALIAS_32 0x5f0 716 717 718 /* ========================================================================= */ 719 /* UVH_EXTIO_INT0_BROADCAST */ 720 /* ========================================================================= */ 721 #define UVH_EXTIO_INT0_BROADCAST 0x61448UL 722 723 #define UV1H_EXTIO_INT0_BROADCAST_32 0x3f0 724 #define UV2H_EXTIO_INT0_BROADCAST_32 0x3f0 725 #define UV3H_EXTIO_INT0_BROADCAST_32 0x3f0 726 #define UV4H_EXTIO_INT0_BROADCAST_32 0x310 727 #define UVH_EXTIO_INT0_BROADCAST_32 ( \ 728 is_uv1_hub() ? UV1H_EXTIO_INT0_BROADCAST_32 : \ 729 is_uv2_hub() ? UV2H_EXTIO_INT0_BROADCAST_32 : \ 730 is_uv3_hub() ? UV3H_EXTIO_INT0_BROADCAST_32 : \ 731 /*is_uv4_hub*/ UV4H_EXTIO_INT0_BROADCAST_32) 732 733 #define UVH_EXTIO_INT0_BROADCAST_ENABLE_SHFT 0 734 #define UVH_EXTIO_INT0_BROADCAST_ENABLE_MASK 0x0000000000000001UL 735 736 737 union uvh_extio_int0_broadcast_u { 738 unsigned long v; 739 struct uvh_extio_int0_broadcast_s { 740 unsigned long enable:1; /* RW */ 741 unsigned long rsvd_1_63:63; 742 } s; 743 }; 744 745 /* ========================================================================= */ 746 /* UVH_GR0_TLB_INT0_CONFIG */ 747 /* ========================================================================= */ 748 #define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL 749 750 #define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0 751 #define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT 8 752 #define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11 753 #define UVH_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12 754 #define UVH_GR0_TLB_INT0_CONFIG_P_SHFT 13 755 #define UVH_GR0_TLB_INT0_CONFIG_T_SHFT 15 756 #define UVH_GR0_TLB_INT0_CONFIG_M_SHFT 16 757 #define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32 758 #define UVH_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL 759 #define UVH_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL 760 #define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL 761 #define UVH_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL 762 #define UVH_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL 763 #define UVH_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL 764 #define UVH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL 765 #define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 766 767 768 union uvh_gr0_tlb_int0_config_u { 769 unsigned long v; 770 struct uvh_gr0_tlb_int0_config_s { 771 unsigned long vector_:8; /* RW */ 772 unsigned long dm:3; /* RW */ 773 unsigned long destmode:1; /* RW */ 774 unsigned long status:1; /* RO */ 775 unsigned long p:1; /* RO */ 776 unsigned long rsvd_14:1; 777 unsigned long t:1; /* RO */ 778 unsigned long m:1; /* RW */ 779 unsigned long rsvd_17_31:15; 780 unsigned long apic_id:32; /* RW */ 781 } s; 782 }; 783 784 /* ========================================================================= */ 785 /* UVH_GR0_TLB_INT1_CONFIG */ 786 /* ========================================================================= */ 787 #define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL 788 789 #define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0 790 #define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT 8 791 #define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT 11 792 #define UVH_GR0_TLB_INT1_CONFIG_STATUS_SHFT 12 793 #define UVH_GR0_TLB_INT1_CONFIG_P_SHFT 13 794 #define UVH_GR0_TLB_INT1_CONFIG_T_SHFT 15 795 #define UVH_GR0_TLB_INT1_CONFIG_M_SHFT 16 796 #define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT 32 797 #define UVH_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL 798 #define UVH_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL 799 #define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL 800 #define UVH_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL 801 #define UVH_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL 802 #define UVH_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL 803 #define UVH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL 804 #define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 805 806 807 union uvh_gr0_tlb_int1_config_u { 808 unsigned long v; 809 struct uvh_gr0_tlb_int1_config_s { 810 unsigned long vector_:8; /* RW */ 811 unsigned long dm:3; /* RW */ 812 unsigned long destmode:1; /* RW */ 813 unsigned long status:1; /* RO */ 814 unsigned long p:1; /* RO */ 815 unsigned long rsvd_14:1; 816 unsigned long t:1; /* RO */ 817 unsigned long m:1; /* RW */ 818 unsigned long rsvd_17_31:15; 819 unsigned long apic_id:32; /* RW */ 820 } s; 821 }; 822 823 /* ========================================================================= */ 824 /* UVH_GR0_TLB_MMR_CONTROL */ 825 /* ========================================================================= */ 826 #define UV1H_GR0_TLB_MMR_CONTROL 0x401080UL 827 #define UV2H_GR0_TLB_MMR_CONTROL 0xc01080UL 828 #define UV3H_GR0_TLB_MMR_CONTROL 0xc01080UL 829 #define UV4H_GR0_TLB_MMR_CONTROL 0x601080UL 830 #define UVH_GR0_TLB_MMR_CONTROL ( \ 831 is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL : \ 832 is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL : \ 833 is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL : \ 834 /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL) 835 836 #define UVH_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 837 #define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 838 #define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 839 #define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 840 #define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31 841 #define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 842 #define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 843 #define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 844 #define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 845 846 #define UV1H_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 847 #define UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 848 #define UV1H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 849 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 850 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 851 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31 852 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT 48 853 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT 52 854 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_SHFT 54 855 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_SHFT 56 856 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_SHFT 60 857 #define UV1H_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL 858 #define UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL 859 #define UV1H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 860 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 861 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 862 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 863 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL 864 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL 865 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_MASK 0x0040000000000000UL 866 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK 0x0100000000000000UL 867 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK 0x1000000000000000UL 868 869 #define UVXH_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 870 #define UVXH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 871 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 872 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 873 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31 874 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 875 #define UVXH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 876 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 877 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 878 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 879 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 880 881 #define UV2H_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 882 #define UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 883 #define UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 884 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 885 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 886 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31 887 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 888 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT 48 889 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT 52 890 #define UV2H_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL 891 #define UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL 892 #define UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 893 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 894 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 895 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 896 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 897 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL 898 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL 899 900 #define UV3H_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 901 #define UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 902 #define UV3H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 903 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 904 #define UV3H_GR0_TLB_MMR_CONTROL_ECC_SEL_SHFT 21 905 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 906 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31 907 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 908 #define UV3H_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL 909 #define UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL 910 #define UV3H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 911 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 912 #define UV3H_GR0_TLB_MMR_CONTROL_ECC_SEL_MASK 0x0000000000200000UL 913 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 914 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 915 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 916 917 #define UV4H_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 918 #define UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 13 919 #define UV4H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 920 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 921 #define UV4H_GR0_TLB_MMR_CONTROL_ECC_SEL_SHFT 21 922 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 923 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31 924 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 925 #define UV4H_GR0_TLB_MMR_CONTROL_PAGE_SIZE_SHFT 59 926 #define UV4H_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000001fffUL 927 #define UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000006000UL 928 #define UV4H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 929 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 930 #define UV4H_GR0_TLB_MMR_CONTROL_ECC_SEL_MASK 0x0000000000200000UL 931 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 932 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 933 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 934 #define UV4H_GR0_TLB_MMR_CONTROL_PAGE_SIZE_MASK 0xf800000000000000UL 935 936 #define UVH_GR0_TLB_MMR_CONTROL_INDEX_MASK ( \ 937 is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL_INDEX_MASK : \ 938 is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL_INDEX_MASK : \ 939 is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL_INDEX_MASK : \ 940 /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL_INDEX_MASK) 941 #define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK ( \ 942 is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK : \ 943 is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK : \ 944 is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK : \ 945 /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK) 946 #define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT ( \ 947 is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT : \ 948 is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT : \ 949 is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT : \ 950 /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT) 951 952 union uvh_gr0_tlb_mmr_control_u { 953 unsigned long v; 954 struct uvh_gr0_tlb_mmr_control_s { 955 unsigned long rsvd_0_15:16; 956 unsigned long auto_valid_en:1; /* RW */ 957 unsigned long rsvd_17_19:3; 958 unsigned long mmr_hash_index_en:1; /* RW */ 959 unsigned long rsvd_21_29:9; 960 unsigned long mmr_write:1; /* WP */ 961 unsigned long mmr_read:1; /* WP */ 962 unsigned long rsvd_32_48:17; 963 unsigned long rsvd_49_51:3; 964 unsigned long rsvd_52_63:12; 965 } s; 966 struct uv1h_gr0_tlb_mmr_control_s { 967 unsigned long index:12; /* RW */ 968 unsigned long mem_sel:2; /* RW */ 969 unsigned long rsvd_14_15:2; 970 unsigned long auto_valid_en:1; /* RW */ 971 unsigned long rsvd_17_19:3; 972 unsigned long mmr_hash_index_en:1; /* RW */ 973 unsigned long rsvd_21_29:9; 974 unsigned long mmr_write:1; /* WP */ 975 unsigned long mmr_read:1; /* WP */ 976 unsigned long rsvd_32_47:16; 977 unsigned long mmr_inj_con:1; /* RW */ 978 unsigned long rsvd_49_51:3; 979 unsigned long mmr_inj_tlbram:1; /* RW */ 980 unsigned long rsvd_53:1; 981 unsigned long mmr_inj_tlbpgsize:1; /* RW */ 982 unsigned long rsvd_55:1; 983 unsigned long mmr_inj_tlbrreg:1; /* RW */ 984 unsigned long rsvd_57_59:3; 985 unsigned long mmr_inj_tlblruv:1; /* RW */ 986 unsigned long rsvd_61_63:3; 987 } s1; 988 struct uvxh_gr0_tlb_mmr_control_s { 989 unsigned long rsvd_0_15:16; 990 unsigned long auto_valid_en:1; /* RW */ 991 unsigned long rsvd_17_19:3; 992 unsigned long mmr_hash_index_en:1; /* RW */ 993 unsigned long rsvd_21_29:9; 994 unsigned long mmr_write:1; /* WP */ 995 unsigned long mmr_read:1; /* WP */ 996 unsigned long mmr_op_done:1; /* RW */ 997 unsigned long rsvd_33_47:15; 998 unsigned long rsvd_48:1; 999 unsigned long rsvd_49_51:3; 1000 unsigned long rsvd_52_63:12; 1001 } sx; 1002 struct uv2h_gr0_tlb_mmr_control_s { 1003 unsigned long index:12; /* RW */ 1004 unsigned long mem_sel:2; /* RW */ 1005 unsigned long rsvd_14_15:2; 1006 unsigned long auto_valid_en:1; /* RW */ 1007 unsigned long rsvd_17_19:3; 1008 unsigned long mmr_hash_index_en:1; /* RW */ 1009 unsigned long rsvd_21_29:9; 1010 unsigned long mmr_write:1; /* WP */ 1011 unsigned long mmr_read:1; /* WP */ 1012 unsigned long mmr_op_done:1; /* RW */ 1013 unsigned long rsvd_33_47:15; 1014 unsigned long mmr_inj_con:1; /* RW */ 1015 unsigned long rsvd_49_51:3; 1016 unsigned long mmr_inj_tlbram:1; /* RW */ 1017 unsigned long rsvd_53_63:11; 1018 } s2; 1019 struct uv3h_gr0_tlb_mmr_control_s { 1020 unsigned long index:12; /* RW */ 1021 unsigned long mem_sel:2; /* RW */ 1022 unsigned long rsvd_14_15:2; 1023 unsigned long auto_valid_en:1; /* RW */ 1024 unsigned long rsvd_17_19:3; 1025 unsigned long mmr_hash_index_en:1; /* RW */ 1026 unsigned long ecc_sel:1; /* RW */ 1027 unsigned long rsvd_22_29:8; 1028 unsigned long mmr_write:1; /* WP */ 1029 unsigned long mmr_read:1; /* WP */ 1030 unsigned long mmr_op_done:1; /* RW */ 1031 unsigned long rsvd_33_47:15; 1032 unsigned long undef_48:1; /* Undefined */ 1033 unsigned long rsvd_49_51:3; 1034 unsigned long undef_52:1; /* Undefined */ 1035 unsigned long rsvd_53_63:11; 1036 } s3; 1037 struct uv4h_gr0_tlb_mmr_control_s { 1038 unsigned long index:13; /* RW */ 1039 unsigned long mem_sel:2; /* RW */ 1040 unsigned long rsvd_15:1; 1041 unsigned long auto_valid_en:1; /* RW */ 1042 unsigned long rsvd_17_19:3; 1043 unsigned long mmr_hash_index_en:1; /* RW */ 1044 unsigned long ecc_sel:1; /* RW */ 1045 unsigned long rsvd_22_29:8; 1046 unsigned long mmr_write:1; /* WP */ 1047 unsigned long mmr_read:1; /* WP */ 1048 unsigned long mmr_op_done:1; /* RW */ 1049 unsigned long rsvd_33_47:15; 1050 unsigned long undef_48:1; /* Undefined */ 1051 unsigned long rsvd_49_51:3; 1052 unsigned long rsvd_52_58:7; 1053 unsigned long page_size:5; /* RW */ 1054 } s4; 1055 }; 1056 1057 /* ========================================================================= */ 1058 /* UVH_GR0_TLB_MMR_READ_DATA_HI */ 1059 /* ========================================================================= */ 1060 #define UV1H_GR0_TLB_MMR_READ_DATA_HI 0x4010a0UL 1061 #define UV2H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL 1062 #define UV3H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL 1063 #define UV4H_GR0_TLB_MMR_READ_DATA_HI 0x6010a0UL 1064 #define UVH_GR0_TLB_MMR_READ_DATA_HI ( \ 1065 is_uv1_hub() ? UV1H_GR0_TLB_MMR_READ_DATA_HI : \ 1066 is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_HI : \ 1067 is_uv3_hub() ? UV3H_GR0_TLB_MMR_READ_DATA_HI : \ 1068 /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_READ_DATA_HI) 1069 1070 #define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1071 1072 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1073 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 1074 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 1075 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 1076 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL 1077 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL 1078 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL 1079 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 1080 1081 #define UVXH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1082 1083 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1084 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 1085 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 1086 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 1087 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL 1088 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL 1089 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL 1090 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 1091 1092 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1093 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 1094 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 1095 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 1096 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT 45 1097 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT 55 1098 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL 1099 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL 1100 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL 1101 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 1102 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_MASK 0x0000200000000000UL 1103 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK 0xff80000000000000UL 1104 1105 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1106 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_PNID_SHFT 34 1107 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 49 1108 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 51 1109 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT 52 1110 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT 53 1111 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT 55 1112 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK 0x00000003ffffffffUL 1113 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_PNID_MASK 0x0001fffc00000000UL 1114 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0006000000000000UL 1115 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0008000000000000UL 1116 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0010000000000000UL 1117 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_MASK 0x0020000000000000UL 1118 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK 0xff80000000000000UL 1119 1120 1121 union uvh_gr0_tlb_mmr_read_data_hi_u { 1122 unsigned long v; 1123 struct uv1h_gr0_tlb_mmr_read_data_hi_s { 1124 unsigned long pfn:41; /* RO */ 1125 unsigned long gaa:2; /* RO */ 1126 unsigned long dirty:1; /* RO */ 1127 unsigned long larger:1; /* RO */ 1128 unsigned long rsvd_45_63:19; 1129 } s1; 1130 struct uv2h_gr0_tlb_mmr_read_data_hi_s { 1131 unsigned long pfn:41; /* RO */ 1132 unsigned long gaa:2; /* RO */ 1133 unsigned long dirty:1; /* RO */ 1134 unsigned long larger:1; /* RO */ 1135 unsigned long rsvd_45_63:19; 1136 } s2; 1137 struct uv3h_gr0_tlb_mmr_read_data_hi_s { 1138 unsigned long pfn:41; /* RO */ 1139 unsigned long gaa:2; /* RO */ 1140 unsigned long dirty:1; /* RO */ 1141 unsigned long larger:1; /* RO */ 1142 unsigned long aa_ext:1; /* RO */ 1143 unsigned long undef_46_54:9; /* Undefined */ 1144 unsigned long way_ecc:9; /* RO */ 1145 } s3; 1146 struct uv4h_gr0_tlb_mmr_read_data_hi_s { 1147 unsigned long pfn:34; /* RO */ 1148 unsigned long pnid:15; /* RO */ 1149 unsigned long gaa:2; /* RO */ 1150 unsigned long dirty:1; /* RO */ 1151 unsigned long larger:1; /* RO */ 1152 unsigned long aa_ext:1; /* RO */ 1153 unsigned long undef_54:1; /* Undefined */ 1154 unsigned long way_ecc:9; /* RO */ 1155 } s4; 1156 }; 1157 1158 /* ========================================================================= */ 1159 /* UVH_GR0_TLB_MMR_READ_DATA_LO */ 1160 /* ========================================================================= */ 1161 #define UV1H_GR0_TLB_MMR_READ_DATA_LO 0x4010a8UL 1162 #define UV2H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL 1163 #define UV3H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL 1164 #define UV4H_GR0_TLB_MMR_READ_DATA_LO 0x6010a8UL 1165 #define UVH_GR0_TLB_MMR_READ_DATA_LO ( \ 1166 is_uv1_hub() ? UV1H_GR0_TLB_MMR_READ_DATA_LO : \ 1167 is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_LO : \ 1168 is_uv3_hub() ? UV3H_GR0_TLB_MMR_READ_DATA_LO : \ 1169 /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_READ_DATA_LO) 1170 1171 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1172 #define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1173 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1174 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1175 #define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1176 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1177 1178 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1179 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1180 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1181 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1182 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1183 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1184 1185 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1186 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1187 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1188 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1189 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1190 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1191 1192 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1193 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1194 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1195 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1196 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1197 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1198 1199 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1200 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1201 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1202 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1203 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1204 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1205 1206 #define UV4H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1207 #define UV4H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1208 #define UV4H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1209 #define UV4H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1210 #define UV4H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1211 #define UV4H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1212 1213 1214 union uvh_gr0_tlb_mmr_read_data_lo_u { 1215 unsigned long v; 1216 struct uvh_gr0_tlb_mmr_read_data_lo_s { 1217 unsigned long vpn:39; /* RO */ 1218 unsigned long asid:24; /* RO */ 1219 unsigned long valid:1; /* RO */ 1220 } s; 1221 struct uv1h_gr0_tlb_mmr_read_data_lo_s { 1222 unsigned long vpn:39; /* RO */ 1223 unsigned long asid:24; /* RO */ 1224 unsigned long valid:1; /* RO */ 1225 } s1; 1226 struct uvxh_gr0_tlb_mmr_read_data_lo_s { 1227 unsigned long vpn:39; /* RO */ 1228 unsigned long asid:24; /* RO */ 1229 unsigned long valid:1; /* RO */ 1230 } sx; 1231 struct uv2h_gr0_tlb_mmr_read_data_lo_s { 1232 unsigned long vpn:39; /* RO */ 1233 unsigned long asid:24; /* RO */ 1234 unsigned long valid:1; /* RO */ 1235 } s2; 1236 struct uv3h_gr0_tlb_mmr_read_data_lo_s { 1237 unsigned long vpn:39; /* RO */ 1238 unsigned long asid:24; /* RO */ 1239 unsigned long valid:1; /* RO */ 1240 } s3; 1241 struct uv4h_gr0_tlb_mmr_read_data_lo_s { 1242 unsigned long vpn:39; /* RO */ 1243 unsigned long asid:24; /* RO */ 1244 unsigned long valid:1; /* RO */ 1245 } s4; 1246 }; 1247 1248 /* ========================================================================= */ 1249 /* UVH_GR1_TLB_INT0_CONFIG */ 1250 /* ========================================================================= */ 1251 #define UV1H_GR1_TLB_INT0_CONFIG 0x61f00UL 1252 #define UV2H_GR1_TLB_INT0_CONFIG 0x61f00UL 1253 #define UV3H_GR1_TLB_INT0_CONFIG 0x61f00UL 1254 #define UV4H_GR1_TLB_INT0_CONFIG 0x62100UL 1255 #define UVH_GR1_TLB_INT0_CONFIG ( \ 1256 is_uv1_hub() ? UV1H_GR1_TLB_INT0_CONFIG : \ 1257 is_uv2_hub() ? UV2H_GR1_TLB_INT0_CONFIG : \ 1258 is_uv3_hub() ? UV3H_GR1_TLB_INT0_CONFIG : \ 1259 /*is_uv4_hub*/ UV4H_GR1_TLB_INT0_CONFIG) 1260 1261 #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0 1262 #define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT 8 1263 #define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT 11 1264 #define UVH_GR1_TLB_INT0_CONFIG_STATUS_SHFT 12 1265 #define UVH_GR1_TLB_INT0_CONFIG_P_SHFT 13 1266 #define UVH_GR1_TLB_INT0_CONFIG_T_SHFT 15 1267 #define UVH_GR1_TLB_INT0_CONFIG_M_SHFT 16 1268 #define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT 32 1269 #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL 1270 #define UVH_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL 1271 #define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL 1272 #define UVH_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL 1273 #define UVH_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL 1274 #define UVH_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL 1275 #define UVH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL 1276 #define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 1277 1278 1279 union uvh_gr1_tlb_int0_config_u { 1280 unsigned long v; 1281 struct uvh_gr1_tlb_int0_config_s { 1282 unsigned long vector_:8; /* RW */ 1283 unsigned long dm:3; /* RW */ 1284 unsigned long destmode:1; /* RW */ 1285 unsigned long status:1; /* RO */ 1286 unsigned long p:1; /* RO */ 1287 unsigned long rsvd_14:1; 1288 unsigned long t:1; /* RO */ 1289 unsigned long m:1; /* RW */ 1290 unsigned long rsvd_17_31:15; 1291 unsigned long apic_id:32; /* RW */ 1292 } s; 1293 }; 1294 1295 /* ========================================================================= */ 1296 /* UVH_GR1_TLB_INT1_CONFIG */ 1297 /* ========================================================================= */ 1298 #define UV1H_GR1_TLB_INT1_CONFIG 0x61f40UL 1299 #define UV2H_GR1_TLB_INT1_CONFIG 0x61f40UL 1300 #define UV3H_GR1_TLB_INT1_CONFIG 0x61f40UL 1301 #define UV4H_GR1_TLB_INT1_CONFIG 0x62140UL 1302 #define UVH_GR1_TLB_INT1_CONFIG ( \ 1303 is_uv1_hub() ? UV1H_GR1_TLB_INT1_CONFIG : \ 1304 is_uv2_hub() ? UV2H_GR1_TLB_INT1_CONFIG : \ 1305 is_uv3_hub() ? UV3H_GR1_TLB_INT1_CONFIG : \ 1306 /*is_uv4_hub*/ UV4H_GR1_TLB_INT1_CONFIG) 1307 1308 #define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0 1309 #define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT 8 1310 #define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT 11 1311 #define UVH_GR1_TLB_INT1_CONFIG_STATUS_SHFT 12 1312 #define UVH_GR1_TLB_INT1_CONFIG_P_SHFT 13 1313 #define UVH_GR1_TLB_INT1_CONFIG_T_SHFT 15 1314 #define UVH_GR1_TLB_INT1_CONFIG_M_SHFT 16 1315 #define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT 32 1316 #define UVH_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL 1317 #define UVH_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL 1318 #define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL 1319 #define UVH_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL 1320 #define UVH_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL 1321 #define UVH_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL 1322 #define UVH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL 1323 #define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 1324 1325 1326 union uvh_gr1_tlb_int1_config_u { 1327 unsigned long v; 1328 struct uvh_gr1_tlb_int1_config_s { 1329 unsigned long vector_:8; /* RW */ 1330 unsigned long dm:3; /* RW */ 1331 unsigned long destmode:1; /* RW */ 1332 unsigned long status:1; /* RO */ 1333 unsigned long p:1; /* RO */ 1334 unsigned long rsvd_14:1; 1335 unsigned long t:1; /* RO */ 1336 unsigned long m:1; /* RW */ 1337 unsigned long rsvd_17_31:15; 1338 unsigned long apic_id:32; /* RW */ 1339 } s; 1340 }; 1341 1342 /* ========================================================================= */ 1343 /* UVH_GR1_TLB_MMR_CONTROL */ 1344 /* ========================================================================= */ 1345 #define UV1H_GR1_TLB_MMR_CONTROL 0x801080UL 1346 #define UV2H_GR1_TLB_MMR_CONTROL 0x1001080UL 1347 #define UV3H_GR1_TLB_MMR_CONTROL 0x1001080UL 1348 #define UV4H_GR1_TLB_MMR_CONTROL 0x701080UL 1349 #define UVH_GR1_TLB_MMR_CONTROL ( \ 1350 is_uv1_hub() ? UV1H_GR1_TLB_MMR_CONTROL : \ 1351 is_uv2_hub() ? UV2H_GR1_TLB_MMR_CONTROL : \ 1352 is_uv3_hub() ? UV3H_GR1_TLB_MMR_CONTROL : \ 1353 /*is_uv4_hub*/ UV4H_GR1_TLB_MMR_CONTROL) 1354 1355 #define UVH_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 1356 #define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 1357 #define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 1358 #define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 1359 #define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31 1360 #define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 1361 #define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 1362 #define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 1363 #define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 1364 1365 #define UV1H_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 1366 #define UV1H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 1367 #define UV1H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 1368 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 1369 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 1370 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31 1371 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT 48 1372 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT 52 1373 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_SHFT 54 1374 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_SHFT 56 1375 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_SHFT 60 1376 #define UV1H_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL 1377 #define UV1H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL 1378 #define UV1H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 1379 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 1380 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 1381 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 1382 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL 1383 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL 1384 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_MASK 0x0040000000000000UL 1385 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK 0x0100000000000000UL 1386 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK 0x1000000000000000UL 1387 1388 #define UVXH_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 1389 #define UVXH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 1390 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 1391 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 1392 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31 1393 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 1394 #define UVXH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 1395 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 1396 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 1397 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 1398 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 1399 1400 #define UV2H_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 1401 #define UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 1402 #define UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 1403 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 1404 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 1405 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31 1406 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 1407 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT 48 1408 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT 52 1409 #define UV2H_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL 1410 #define UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL 1411 #define UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 1412 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 1413 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 1414 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 1415 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 1416 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL 1417 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL 1418 1419 #define UV3H_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 1420 #define UV3H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 1421 #define UV3H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 1422 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 1423 #define UV3H_GR1_TLB_MMR_CONTROL_ECC_SEL_SHFT 21 1424 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 1425 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31 1426 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 1427 #define UV3H_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL 1428 #define UV3H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL 1429 #define UV3H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 1430 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 1431 #define UV3H_GR1_TLB_MMR_CONTROL_ECC_SEL_MASK 0x0000000000200000UL 1432 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 1433 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 1434 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 1435 1436 #define UV4H_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 1437 #define UV4H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 13 1438 #define UV4H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 1439 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 1440 #define UV4H_GR1_TLB_MMR_CONTROL_ECC_SEL_SHFT 21 1441 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 1442 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31 1443 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 1444 #define UV4H_GR1_TLB_MMR_CONTROL_PAGE_SIZE_SHFT 59 1445 #define UV4H_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000001fffUL 1446 #define UV4H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000006000UL 1447 #define UV4H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 1448 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 1449 #define UV4H_GR1_TLB_MMR_CONTROL_ECC_SEL_MASK 0x0000000000200000UL 1450 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 1451 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 1452 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 1453 #define UV4H_GR1_TLB_MMR_CONTROL_PAGE_SIZE_MASK 0xf800000000000000UL 1454 1455 1456 union uvh_gr1_tlb_mmr_control_u { 1457 unsigned long v; 1458 struct uvh_gr1_tlb_mmr_control_s { 1459 unsigned long rsvd_0_15:16; 1460 unsigned long auto_valid_en:1; /* RW */ 1461 unsigned long rsvd_17_19:3; 1462 unsigned long mmr_hash_index_en:1; /* RW */ 1463 unsigned long rsvd_21_29:9; 1464 unsigned long mmr_write:1; /* WP */ 1465 unsigned long mmr_read:1; /* WP */ 1466 unsigned long rsvd_32_48:17; 1467 unsigned long rsvd_49_51:3; 1468 unsigned long rsvd_52_63:12; 1469 } s; 1470 struct uv1h_gr1_tlb_mmr_control_s { 1471 unsigned long index:12; /* RW */ 1472 unsigned long mem_sel:2; /* RW */ 1473 unsigned long rsvd_14_15:2; 1474 unsigned long auto_valid_en:1; /* RW */ 1475 unsigned long rsvd_17_19:3; 1476 unsigned long mmr_hash_index_en:1; /* RW */ 1477 unsigned long rsvd_21_29:9; 1478 unsigned long mmr_write:1; /* WP */ 1479 unsigned long mmr_read:1; /* WP */ 1480 unsigned long rsvd_32_47:16; 1481 unsigned long mmr_inj_con:1; /* RW */ 1482 unsigned long rsvd_49_51:3; 1483 unsigned long mmr_inj_tlbram:1; /* RW */ 1484 unsigned long rsvd_53:1; 1485 unsigned long mmr_inj_tlbpgsize:1; /* RW */ 1486 unsigned long rsvd_55:1; 1487 unsigned long mmr_inj_tlbrreg:1; /* RW */ 1488 unsigned long rsvd_57_59:3; 1489 unsigned long mmr_inj_tlblruv:1; /* RW */ 1490 unsigned long rsvd_61_63:3; 1491 } s1; 1492 struct uvxh_gr1_tlb_mmr_control_s { 1493 unsigned long rsvd_0_15:16; 1494 unsigned long auto_valid_en:1; /* RW */ 1495 unsigned long rsvd_17_19:3; 1496 unsigned long mmr_hash_index_en:1; /* RW */ 1497 unsigned long rsvd_21_29:9; 1498 unsigned long mmr_write:1; /* WP */ 1499 unsigned long mmr_read:1; /* WP */ 1500 unsigned long mmr_op_done:1; /* RW */ 1501 unsigned long rsvd_33_47:15; 1502 unsigned long rsvd_48:1; 1503 unsigned long rsvd_49_51:3; 1504 unsigned long rsvd_52_63:12; 1505 } sx; 1506 struct uv2h_gr1_tlb_mmr_control_s { 1507 unsigned long index:12; /* RW */ 1508 unsigned long mem_sel:2; /* RW */ 1509 unsigned long rsvd_14_15:2; 1510 unsigned long auto_valid_en:1; /* RW */ 1511 unsigned long rsvd_17_19:3; 1512 unsigned long mmr_hash_index_en:1; /* RW */ 1513 unsigned long rsvd_21_29:9; 1514 unsigned long mmr_write:1; /* WP */ 1515 unsigned long mmr_read:1; /* WP */ 1516 unsigned long mmr_op_done:1; /* RW */ 1517 unsigned long rsvd_33_47:15; 1518 unsigned long mmr_inj_con:1; /* RW */ 1519 unsigned long rsvd_49_51:3; 1520 unsigned long mmr_inj_tlbram:1; /* RW */ 1521 unsigned long rsvd_53_63:11; 1522 } s2; 1523 struct uv3h_gr1_tlb_mmr_control_s { 1524 unsigned long index:12; /* RW */ 1525 unsigned long mem_sel:2; /* RW */ 1526 unsigned long rsvd_14_15:2; 1527 unsigned long auto_valid_en:1; /* RW */ 1528 unsigned long rsvd_17_19:3; 1529 unsigned long mmr_hash_index_en:1; /* RW */ 1530 unsigned long ecc_sel:1; /* RW */ 1531 unsigned long rsvd_22_29:8; 1532 unsigned long mmr_write:1; /* WP */ 1533 unsigned long mmr_read:1; /* WP */ 1534 unsigned long mmr_op_done:1; /* RW */ 1535 unsigned long rsvd_33_47:15; 1536 unsigned long undef_48:1; /* Undefined */ 1537 unsigned long rsvd_49_51:3; 1538 unsigned long undef_52:1; /* Undefined */ 1539 unsigned long rsvd_53_63:11; 1540 } s3; 1541 struct uv4h_gr1_tlb_mmr_control_s { 1542 unsigned long index:13; /* RW */ 1543 unsigned long mem_sel:2; /* RW */ 1544 unsigned long rsvd_15:1; 1545 unsigned long auto_valid_en:1; /* RW */ 1546 unsigned long rsvd_17_19:3; 1547 unsigned long mmr_hash_index_en:1; /* RW */ 1548 unsigned long ecc_sel:1; /* RW */ 1549 unsigned long rsvd_22_29:8; 1550 unsigned long mmr_write:1; /* WP */ 1551 unsigned long mmr_read:1; /* WP */ 1552 unsigned long mmr_op_done:1; /* RW */ 1553 unsigned long rsvd_33_47:15; 1554 unsigned long undef_48:1; /* Undefined */ 1555 unsigned long rsvd_49_51:3; 1556 unsigned long rsvd_52_58:7; 1557 unsigned long page_size:5; /* RW */ 1558 } s4; 1559 }; 1560 1561 /* ========================================================================= */ 1562 /* UVH_GR1_TLB_MMR_READ_DATA_HI */ 1563 /* ========================================================================= */ 1564 #define UV1H_GR1_TLB_MMR_READ_DATA_HI 0x8010a0UL 1565 #define UV2H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL 1566 #define UV3H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL 1567 #define UV4H_GR1_TLB_MMR_READ_DATA_HI 0x7010a0UL 1568 #define UVH_GR1_TLB_MMR_READ_DATA_HI ( \ 1569 is_uv1_hub() ? UV1H_GR1_TLB_MMR_READ_DATA_HI : \ 1570 is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_HI : \ 1571 is_uv3_hub() ? UV3H_GR1_TLB_MMR_READ_DATA_HI : \ 1572 /*is_uv4_hub*/ UV4H_GR1_TLB_MMR_READ_DATA_HI) 1573 1574 #define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1575 1576 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1577 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 1578 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 1579 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 1580 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL 1581 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL 1582 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL 1583 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 1584 1585 #define UVXH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1586 1587 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1588 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 1589 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 1590 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 1591 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL 1592 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL 1593 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL 1594 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 1595 1596 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1597 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 1598 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 1599 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 1600 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT 45 1601 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT 55 1602 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL 1603 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL 1604 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL 1605 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 1606 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_MASK 0x0000200000000000UL 1607 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK 0xff80000000000000UL 1608 1609 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1610 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_PNID_SHFT 34 1611 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 49 1612 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 51 1613 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT 52 1614 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT 53 1615 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT 55 1616 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK 0x00000003ffffffffUL 1617 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_PNID_MASK 0x0001fffc00000000UL 1618 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0006000000000000UL 1619 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0008000000000000UL 1620 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0010000000000000UL 1621 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_MASK 0x0020000000000000UL 1622 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK 0xff80000000000000UL 1623 1624 1625 union uvh_gr1_tlb_mmr_read_data_hi_u { 1626 unsigned long v; 1627 struct uv1h_gr1_tlb_mmr_read_data_hi_s { 1628 unsigned long pfn:41; /* RO */ 1629 unsigned long gaa:2; /* RO */ 1630 unsigned long dirty:1; /* RO */ 1631 unsigned long larger:1; /* RO */ 1632 unsigned long rsvd_45_63:19; 1633 } s1; 1634 struct uv2h_gr1_tlb_mmr_read_data_hi_s { 1635 unsigned long pfn:41; /* RO */ 1636 unsigned long gaa:2; /* RO */ 1637 unsigned long dirty:1; /* RO */ 1638 unsigned long larger:1; /* RO */ 1639 unsigned long rsvd_45_63:19; 1640 } s2; 1641 struct uv3h_gr1_tlb_mmr_read_data_hi_s { 1642 unsigned long pfn:41; /* RO */ 1643 unsigned long gaa:2; /* RO */ 1644 unsigned long dirty:1; /* RO */ 1645 unsigned long larger:1; /* RO */ 1646 unsigned long aa_ext:1; /* RO */ 1647 unsigned long undef_46_54:9; /* Undefined */ 1648 unsigned long way_ecc:9; /* RO */ 1649 } s3; 1650 struct uv4h_gr1_tlb_mmr_read_data_hi_s { 1651 unsigned long pfn:34; /* RO */ 1652 unsigned long pnid:15; /* RO */ 1653 unsigned long gaa:2; /* RO */ 1654 unsigned long dirty:1; /* RO */ 1655 unsigned long larger:1; /* RO */ 1656 unsigned long aa_ext:1; /* RO */ 1657 unsigned long undef_54:1; /* Undefined */ 1658 unsigned long way_ecc:9; /* RO */ 1659 } s4; 1660 }; 1661 1662 /* ========================================================================= */ 1663 /* UVH_GR1_TLB_MMR_READ_DATA_LO */ 1664 /* ========================================================================= */ 1665 #define UV1H_GR1_TLB_MMR_READ_DATA_LO 0x8010a8UL 1666 #define UV2H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL 1667 #define UV3H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL 1668 #define UV4H_GR1_TLB_MMR_READ_DATA_LO 0x7010a8UL 1669 #define UVH_GR1_TLB_MMR_READ_DATA_LO ( \ 1670 is_uv1_hub() ? UV1H_GR1_TLB_MMR_READ_DATA_LO : \ 1671 is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_LO : \ 1672 is_uv3_hub() ? UV3H_GR1_TLB_MMR_READ_DATA_LO : \ 1673 /*is_uv4_hub*/ UV4H_GR1_TLB_MMR_READ_DATA_LO) 1674 1675 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1676 #define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1677 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1678 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1679 #define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1680 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1681 1682 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1683 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1684 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1685 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1686 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1687 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1688 1689 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1690 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1691 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1692 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1693 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1694 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1695 1696 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1697 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1698 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1699 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1700 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1701 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1702 1703 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1704 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1705 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1706 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1707 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1708 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1709 1710 #define UV4H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1711 #define UV4H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1712 #define UV4H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1713 #define UV4H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1714 #define UV4H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1715 #define UV4H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1716 1717 1718 union uvh_gr1_tlb_mmr_read_data_lo_u { 1719 unsigned long v; 1720 struct uvh_gr1_tlb_mmr_read_data_lo_s { 1721 unsigned long vpn:39; /* RO */ 1722 unsigned long asid:24; /* RO */ 1723 unsigned long valid:1; /* RO */ 1724 } s; 1725 struct uv1h_gr1_tlb_mmr_read_data_lo_s { 1726 unsigned long vpn:39; /* RO */ 1727 unsigned long asid:24; /* RO */ 1728 unsigned long valid:1; /* RO */ 1729 } s1; 1730 struct uvxh_gr1_tlb_mmr_read_data_lo_s { 1731 unsigned long vpn:39; /* RO */ 1732 unsigned long asid:24; /* RO */ 1733 unsigned long valid:1; /* RO */ 1734 } sx; 1735 struct uv2h_gr1_tlb_mmr_read_data_lo_s { 1736 unsigned long vpn:39; /* RO */ 1737 unsigned long asid:24; /* RO */ 1738 unsigned long valid:1; /* RO */ 1739 } s2; 1740 struct uv3h_gr1_tlb_mmr_read_data_lo_s { 1741 unsigned long vpn:39; /* RO */ 1742 unsigned long asid:24; /* RO */ 1743 unsigned long valid:1; /* RO */ 1744 } s3; 1745 struct uv4h_gr1_tlb_mmr_read_data_lo_s { 1746 unsigned long vpn:39; /* RO */ 1747 unsigned long asid:24; /* RO */ 1748 unsigned long valid:1; /* RO */ 1749 } s4; 1750 }; 1751 1752 /* ========================================================================= */ 1753 /* UVH_INT_CMPB */ 1754 /* ========================================================================= */ 1755 #define UVH_INT_CMPB 0x22080UL 1756 1757 #define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0 1758 #define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL 1759 1760 1761 union uvh_int_cmpb_u { 1762 unsigned long v; 1763 struct uvh_int_cmpb_s { 1764 unsigned long real_time_cmpb:56; /* RW */ 1765 unsigned long rsvd_56_63:8; 1766 } s; 1767 }; 1768 1769 /* ========================================================================= */ 1770 /* UVH_INT_CMPC */ 1771 /* ========================================================================= */ 1772 #define UVH_INT_CMPC 0x22100UL 1773 1774 1775 #define UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT 0 1776 #define UV1H_INT_CMPC_REAL_TIME_CMPC_MASK 0x00ffffffffffffffUL 1777 1778 #define UVXH_INT_CMPC_REAL_TIME_CMP_2_SHFT 0 1779 #define UVXH_INT_CMPC_REAL_TIME_CMP_2_MASK 0x00ffffffffffffffUL 1780 1781 1782 union uvh_int_cmpc_u { 1783 unsigned long v; 1784 struct uvh_int_cmpc_s { 1785 unsigned long real_time_cmpc:56; /* RW */ 1786 unsigned long rsvd_56_63:8; 1787 } s; 1788 }; 1789 1790 /* ========================================================================= */ 1791 /* UVH_INT_CMPD */ 1792 /* ========================================================================= */ 1793 #define UVH_INT_CMPD 0x22180UL 1794 1795 1796 #define UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT 0 1797 #define UV1H_INT_CMPD_REAL_TIME_CMPD_MASK 0x00ffffffffffffffUL 1798 1799 #define UVXH_INT_CMPD_REAL_TIME_CMP_3_SHFT 0 1800 #define UVXH_INT_CMPD_REAL_TIME_CMP_3_MASK 0x00ffffffffffffffUL 1801 1802 1803 union uvh_int_cmpd_u { 1804 unsigned long v; 1805 struct uvh_int_cmpd_s { 1806 unsigned long real_time_cmpd:56; /* RW */ 1807 unsigned long rsvd_56_63:8; 1808 } s; 1809 }; 1810 1811 /* ========================================================================= */ 1812 /* UVH_IPI_INT */ 1813 /* ========================================================================= */ 1814 #define UVH_IPI_INT 0x60500UL 1815 1816 #define UV1H_IPI_INT_32 0x348 1817 #define UV2H_IPI_INT_32 0x348 1818 #define UV3H_IPI_INT_32 0x348 1819 #define UV4H_IPI_INT_32 0x268 1820 #define UVH_IPI_INT_32 ( \ 1821 is_uv1_hub() ? UV1H_IPI_INT_32 : \ 1822 is_uv2_hub() ? UV2H_IPI_INT_32 : \ 1823 is_uv3_hub() ? UV3H_IPI_INT_32 : \ 1824 /*is_uv4_hub*/ UV4H_IPI_INT_32) 1825 1826 #define UVH_IPI_INT_VECTOR_SHFT 0 1827 #define UVH_IPI_INT_DELIVERY_MODE_SHFT 8 1828 #define UVH_IPI_INT_DESTMODE_SHFT 11 1829 #define UVH_IPI_INT_APIC_ID_SHFT 16 1830 #define UVH_IPI_INT_SEND_SHFT 63 1831 #define UVH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL 1832 #define UVH_IPI_INT_DELIVERY_MODE_MASK 0x0000000000000700UL 1833 #define UVH_IPI_INT_DESTMODE_MASK 0x0000000000000800UL 1834 #define UVH_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL 1835 #define UVH_IPI_INT_SEND_MASK 0x8000000000000000UL 1836 1837 1838 union uvh_ipi_int_u { 1839 unsigned long v; 1840 struct uvh_ipi_int_s { 1841 unsigned long vector_:8; /* RW */ 1842 unsigned long delivery_mode:3; /* RW */ 1843 unsigned long destmode:1; /* RW */ 1844 unsigned long rsvd_12_15:4; 1845 unsigned long apic_id:32; /* RW */ 1846 unsigned long rsvd_48_62:15; 1847 unsigned long send:1; /* WP */ 1848 } s; 1849 }; 1850 1851 /* ========================================================================= */ 1852 /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST */ 1853 /* ========================================================================= */ 1854 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL 1855 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL 1856 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL 1857 #define UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST uv_undefined("UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST") 1858 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST ( \ 1859 is_uv1_hub() ? UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST : \ 1860 is_uv2_hub() ? UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST : \ 1861 is_uv3_hub() ? UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST : \ 1862 /*is_uv4_hub*/ UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST) 1863 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x9c0 1864 1865 1866 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4 1867 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49 1868 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL 1869 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL 1870 1871 1872 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4 1873 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49 1874 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL 1875 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL 1876 1877 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4 1878 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49 1879 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL 1880 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL 1881 1882 1883 union uvh_lb_bau_intd_payload_queue_first_u { 1884 unsigned long v; 1885 struct uv1h_lb_bau_intd_payload_queue_first_s { 1886 unsigned long rsvd_0_3:4; 1887 unsigned long address:39; /* RW */ 1888 unsigned long rsvd_43_48:6; 1889 unsigned long node_id:14; /* RW */ 1890 unsigned long rsvd_63:1; 1891 } s1; 1892 struct uv2h_lb_bau_intd_payload_queue_first_s { 1893 unsigned long rsvd_0_3:4; 1894 unsigned long address:39; /* RW */ 1895 unsigned long rsvd_43_48:6; 1896 unsigned long node_id:14; /* RW */ 1897 unsigned long rsvd_63:1; 1898 } s2; 1899 struct uv3h_lb_bau_intd_payload_queue_first_s { 1900 unsigned long rsvd_0_3:4; 1901 unsigned long address:39; /* RW */ 1902 unsigned long rsvd_43_48:6; 1903 unsigned long node_id:14; /* RW */ 1904 unsigned long rsvd_63:1; 1905 } s3; 1906 }; 1907 1908 /* ========================================================================= */ 1909 /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST */ 1910 /* ========================================================================= */ 1911 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL 1912 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL 1913 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL 1914 #define UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST uv_undefined("UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST") 1915 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST ( \ 1916 is_uv1_hub() ? UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST : \ 1917 is_uv2_hub() ? UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST : \ 1918 is_uv3_hub() ? UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST : \ 1919 /*is_uv4_hub*/ UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST) 1920 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x9c8 1921 1922 1923 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4 1924 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL 1925 1926 1927 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4 1928 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL 1929 1930 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4 1931 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL 1932 1933 1934 union uvh_lb_bau_intd_payload_queue_last_u { 1935 unsigned long v; 1936 struct uv1h_lb_bau_intd_payload_queue_last_s { 1937 unsigned long rsvd_0_3:4; 1938 unsigned long address:39; /* RW */ 1939 unsigned long rsvd_43_63:21; 1940 } s1; 1941 struct uv2h_lb_bau_intd_payload_queue_last_s { 1942 unsigned long rsvd_0_3:4; 1943 unsigned long address:39; /* RW */ 1944 unsigned long rsvd_43_63:21; 1945 } s2; 1946 struct uv3h_lb_bau_intd_payload_queue_last_s { 1947 unsigned long rsvd_0_3:4; 1948 unsigned long address:39; /* RW */ 1949 unsigned long rsvd_43_63:21; 1950 } s3; 1951 }; 1952 1953 /* ========================================================================= */ 1954 /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL */ 1955 /* ========================================================================= */ 1956 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL 1957 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL 1958 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL 1959 #define UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL uv_undefined("UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL") 1960 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL ( \ 1961 is_uv1_hub() ? UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL : \ 1962 is_uv2_hub() ? UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL : \ 1963 is_uv3_hub() ? UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL : \ 1964 /*is_uv4_hub*/ UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL) 1965 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x9d0 1966 1967 1968 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4 1969 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL 1970 1971 1972 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4 1973 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL 1974 1975 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4 1976 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL 1977 1978 1979 union uvh_lb_bau_intd_payload_queue_tail_u { 1980 unsigned long v; 1981 struct uv1h_lb_bau_intd_payload_queue_tail_s { 1982 unsigned long rsvd_0_3:4; 1983 unsigned long address:39; /* RW */ 1984 unsigned long rsvd_43_63:21; 1985 } s1; 1986 struct uv2h_lb_bau_intd_payload_queue_tail_s { 1987 unsigned long rsvd_0_3:4; 1988 unsigned long address:39; /* RW */ 1989 unsigned long rsvd_43_63:21; 1990 } s2; 1991 struct uv3h_lb_bau_intd_payload_queue_tail_s { 1992 unsigned long rsvd_0_3:4; 1993 unsigned long address:39; /* RW */ 1994 unsigned long rsvd_43_63:21; 1995 } s3; 1996 }; 1997 1998 /* ========================================================================= */ 1999 /* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE */ 2000 /* ========================================================================= */ 2001 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL 2002 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL 2003 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL 2004 #define UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE uv_undefined("UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE") 2005 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE ( \ 2006 is_uv1_hub() ? UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE : \ 2007 is_uv2_hub() ? UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE : \ 2008 is_uv3_hub() ? UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE : \ 2009 /*is_uv4_hub*/ UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE) 2010 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0xa68 2011 2012 2013 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 2014 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1 2015 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2 2016 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3 2017 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4 2018 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5 2019 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6 2020 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7 2021 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8 2022 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9 2023 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10 2024 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11 2025 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12 2026 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13 2027 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14 2028 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15 2029 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL 2030 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL 2031 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL 2032 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL 2033 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL 2034 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL 2035 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL 2036 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL 2037 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL 2038 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL 2039 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL 2040 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL 2041 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL 2042 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL 2043 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL 2044 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL 2045 2046 2047 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 2048 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1 2049 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2 2050 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3 2051 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4 2052 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5 2053 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6 2054 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7 2055 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8 2056 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9 2057 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10 2058 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11 2059 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12 2060 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13 2061 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14 2062 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15 2063 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL 2064 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL 2065 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL 2066 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL 2067 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL 2068 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL 2069 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL 2070 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL 2071 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL 2072 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL 2073 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL 2074 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL 2075 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL 2076 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL 2077 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL 2078 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL 2079 2080 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 2081 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1 2082 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2 2083 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3 2084 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4 2085 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5 2086 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6 2087 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7 2088 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8 2089 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9 2090 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10 2091 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11 2092 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12 2093 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13 2094 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14 2095 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15 2096 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL 2097 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL 2098 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL 2099 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL 2100 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL 2101 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL 2102 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL 2103 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL 2104 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL 2105 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL 2106 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL 2107 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL 2108 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL 2109 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL 2110 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL 2111 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL 2112 2113 2114 union uvh_lb_bau_intd_software_acknowledge_u { 2115 unsigned long v; 2116 struct uv1h_lb_bau_intd_software_acknowledge_s { 2117 unsigned long pending_0:1; /* RW, W1C */ 2118 unsigned long pending_1:1; /* RW, W1C */ 2119 unsigned long pending_2:1; /* RW, W1C */ 2120 unsigned long pending_3:1; /* RW, W1C */ 2121 unsigned long pending_4:1; /* RW, W1C */ 2122 unsigned long pending_5:1; /* RW, W1C */ 2123 unsigned long pending_6:1; /* RW, W1C */ 2124 unsigned long pending_7:1; /* RW, W1C */ 2125 unsigned long timeout_0:1; /* RW, W1C */ 2126 unsigned long timeout_1:1; /* RW, W1C */ 2127 unsigned long timeout_2:1; /* RW, W1C */ 2128 unsigned long timeout_3:1; /* RW, W1C */ 2129 unsigned long timeout_4:1; /* RW, W1C */ 2130 unsigned long timeout_5:1; /* RW, W1C */ 2131 unsigned long timeout_6:1; /* RW, W1C */ 2132 unsigned long timeout_7:1; /* RW, W1C */ 2133 unsigned long rsvd_16_63:48; 2134 } s1; 2135 struct uv2h_lb_bau_intd_software_acknowledge_s { 2136 unsigned long pending_0:1; /* RW */ 2137 unsigned long pending_1:1; /* RW */ 2138 unsigned long pending_2:1; /* RW */ 2139 unsigned long pending_3:1; /* RW */ 2140 unsigned long pending_4:1; /* RW */ 2141 unsigned long pending_5:1; /* RW */ 2142 unsigned long pending_6:1; /* RW */ 2143 unsigned long pending_7:1; /* RW */ 2144 unsigned long timeout_0:1; /* RW */ 2145 unsigned long timeout_1:1; /* RW */ 2146 unsigned long timeout_2:1; /* RW */ 2147 unsigned long timeout_3:1; /* RW */ 2148 unsigned long timeout_4:1; /* RW */ 2149 unsigned long timeout_5:1; /* RW */ 2150 unsigned long timeout_6:1; /* RW */ 2151 unsigned long timeout_7:1; /* RW */ 2152 unsigned long rsvd_16_63:48; 2153 } s2; 2154 struct uv3h_lb_bau_intd_software_acknowledge_s { 2155 unsigned long pending_0:1; /* RW */ 2156 unsigned long pending_1:1; /* RW */ 2157 unsigned long pending_2:1; /* RW */ 2158 unsigned long pending_3:1; /* RW */ 2159 unsigned long pending_4:1; /* RW */ 2160 unsigned long pending_5:1; /* RW */ 2161 unsigned long pending_6:1; /* RW */ 2162 unsigned long pending_7:1; /* RW */ 2163 unsigned long timeout_0:1; /* RW */ 2164 unsigned long timeout_1:1; /* RW */ 2165 unsigned long timeout_2:1; /* RW */ 2166 unsigned long timeout_3:1; /* RW */ 2167 unsigned long timeout_4:1; /* RW */ 2168 unsigned long timeout_5:1; /* RW */ 2169 unsigned long timeout_6:1; /* RW */ 2170 unsigned long timeout_7:1; /* RW */ 2171 unsigned long rsvd_16_63:48; 2172 } s3; 2173 }; 2174 2175 /* ========================================================================= */ 2176 /* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS */ 2177 /* ========================================================================= */ 2178 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL 2179 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL 2180 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL 2181 #define UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS uv_undefined("UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS") 2182 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS ( \ 2183 is_uv1_hub() ? UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS : \ 2184 is_uv2_hub() ? UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS : \ 2185 is_uv3_hub() ? UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS : \ 2186 /*is_uv4_hub*/ UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS) 2187 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0xa70 2188 2189 2190 /* ========================================================================= */ 2191 /* UVH_LB_BAU_MISC_CONTROL */ 2192 /* ========================================================================= */ 2193 #define UV1H_LB_BAU_MISC_CONTROL 0x320170UL 2194 #define UV2H_LB_BAU_MISC_CONTROL 0x320170UL 2195 #define UV3H_LB_BAU_MISC_CONTROL 0x320170UL 2196 #define UV4H_LB_BAU_MISC_CONTROL 0xc8170UL 2197 #define UVH_LB_BAU_MISC_CONTROL ( \ 2198 is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL : \ 2199 is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL : \ 2200 is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL : \ 2201 /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL) 2202 2203 #define UV1H_LB_BAU_MISC_CONTROL_32 0xa10 2204 #define UV2H_LB_BAU_MISC_CONTROL_32 0xa10 2205 #define UV3H_LB_BAU_MISC_CONTROL_32 0xa10 2206 #define UV4H_LB_BAU_MISC_CONTROL_32 0xa18 2207 #define UVH_LB_BAU_MISC_CONTROL_32 ( \ 2208 is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_32 : \ 2209 is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_32 : \ 2210 is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_32 : \ 2211 /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_32) 2212 2213 #define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 2214 #define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 2215 #define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 2216 #define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 2217 #define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 2218 #define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 2219 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 2220 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 2221 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 2222 #define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 2223 #define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 2224 #define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 2225 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 2226 #define UVH_LB_BAU_MISC_CONTROL_FUN_SHFT 48 2227 #define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 2228 #define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL 2229 #define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL 2230 #define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 2231 #define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 2232 #define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 2233 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL 2234 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL 2235 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL 2236 #define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL 2237 #define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL 2238 #define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL 2239 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 2240 #define UVH_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 2241 2242 #define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 2243 #define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 2244 #define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 2245 #define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 2246 #define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 2247 #define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 2248 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15 2249 #define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16 2250 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 2251 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 2252 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 2253 #define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 2254 #define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 2255 #define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 2256 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 2257 #define UV1H_LB_BAU_MISC_CONTROL_FUN_SHFT 48 2258 #define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 2259 #define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL 2260 #define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL 2261 #define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 2262 #define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 2263 #define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 2264 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL 2265 #define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL 2266 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL 2267 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL 2268 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL 2269 #define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL 2270 #define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL 2271 #define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL 2272 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 2273 #define UV1H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 2274 2275 #define UVXH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 2276 #define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 2277 #define UVXH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 2278 #define UVXH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 2279 #define UVXH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 2280 #define UVXH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 2281 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 2282 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 2283 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 2284 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 2285 #define UVXH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 2286 #define UVXH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 2287 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 2288 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29 2289 #define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT 30 2290 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31 2291 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32 2292 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33 2293 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34 2294 #define UVXH_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35 2295 #define UVXH_LB_BAU_MISC_CONTROL_FUN_SHFT 48 2296 #define UVXH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 2297 #define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL 2298 #define UVXH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL 2299 #define UVXH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 2300 #define UVXH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 2301 #define UVXH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 2302 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL 2303 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL 2304 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL 2305 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL 2306 #define UVXH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL 2307 #define UVXH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL 2308 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 2309 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL 2310 #define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK 0x0000000040000000UL 2311 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL 2312 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL 2313 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL 2314 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL 2315 #define UVXH_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL 2316 #define UVXH_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 2317 2318 #define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 2319 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 2320 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 2321 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 2322 #define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 2323 #define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 2324 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15 2325 #define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16 2326 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 2327 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 2328 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 2329 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 2330 #define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 2331 #define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 2332 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 2333 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29 2334 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT 30 2335 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31 2336 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32 2337 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33 2338 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34 2339 #define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35 2340 #define UV2H_LB_BAU_MISC_CONTROL_FUN_SHFT 48 2341 #define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 2342 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL 2343 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL 2344 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 2345 #define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 2346 #define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 2347 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL 2348 #define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL 2349 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL 2350 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL 2351 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL 2352 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL 2353 #define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL 2354 #define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL 2355 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 2356 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL 2357 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK 0x0000000040000000UL 2358 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL 2359 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL 2360 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL 2361 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL 2362 #define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL 2363 #define UV2H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 2364 2365 #define UV3H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 2366 #define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 2367 #define UV3H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 2368 #define UV3H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 2369 #define UV3H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 2370 #define UV3H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 2371 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15 2372 #define UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16 2373 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 2374 #define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 2375 #define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 2376 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 2377 #define UV3H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 2378 #define UV3H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 2379 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 2380 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29 2381 #define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT 30 2382 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31 2383 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32 2384 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33 2385 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34 2386 #define UV3H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35 2387 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_SHFT 36 2388 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_PREFETCH_HINT_SHFT 37 2389 #define UV3H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_SHFT 38 2390 #define UV3H_LB_BAU_MISC_CONTROL_FUN_SHFT 48 2391 #define UV3H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 2392 #define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL 2393 #define UV3H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL 2394 #define UV3H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 2395 #define UV3H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 2396 #define UV3H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 2397 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL 2398 #define UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL 2399 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL 2400 #define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL 2401 #define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL 2402 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL 2403 #define UV3H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL 2404 #define UV3H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL 2405 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 2406 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL 2407 #define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK 0x0000000040000000UL 2408 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL 2409 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL 2410 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL 2411 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL 2412 #define UV3H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL 2413 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_MASK 0x0000001000000000UL 2414 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_PREFETCH_HINT_MASK 0x0000002000000000UL 2415 #define UV3H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_MASK 0x00003fc000000000UL 2416 #define UV3H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 2417 2418 #define UV4H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 2419 #define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 2420 #define UV4H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 2421 #define UV4H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 2422 #define UV4H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 2423 #define UV4H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 2424 #define UV4H_LB_BAU_MISC_CONTROL_RESERVED_15_19_SHFT 15 2425 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 2426 #define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 2427 #define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 2428 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 2429 #define UV4H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 2430 #define UV4H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 2431 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 2432 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29 2433 #define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT 30 2434 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31 2435 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32 2436 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33 2437 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34 2438 #define UV4H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35 2439 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_SHFT 36 2440 #define UV4H_LB_BAU_MISC_CONTROL_RESERVED_37_SHFT 37 2441 #define UV4H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_SHFT 38 2442 #define UV4H_LB_BAU_MISC_CONTROL_ADDRESS_INTERLEAVE_SELECT_SHFT 46 2443 #define UV4H_LB_BAU_MISC_CONTROL_FUN_SHFT 48 2444 #define UV4H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 2445 #define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL 2446 #define UV4H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL 2447 #define UV4H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 2448 #define UV4H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 2449 #define UV4H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 2450 #define UV4H_LB_BAU_MISC_CONTROL_RESERVED_15_19_MASK 0x00000000000f8000UL 2451 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL 2452 #define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL 2453 #define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL 2454 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL 2455 #define UV4H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL 2456 #define UV4H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL 2457 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 2458 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL 2459 #define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK 0x0000000040000000UL 2460 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL 2461 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL 2462 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL 2463 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL 2464 #define UV4H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL 2465 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_MASK 0x0000001000000000UL 2466 #define UV4H_LB_BAU_MISC_CONTROL_RESERVED_37_MASK 0x0000002000000000UL 2467 #define UV4H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_MASK 0x00003fc000000000UL 2468 #define UV4H_LB_BAU_MISC_CONTROL_ADDRESS_INTERLEAVE_SELECT_MASK 0x0000400000000000UL 2469 #define UV4H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 2470 2471 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK \ 2472 uv_undefined("UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK") 2473 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK ( \ 2474 is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK : \ 2475 is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK : \ 2476 is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK : \ 2477 /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK) 2478 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT \ 2479 uv_undefined("UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT") 2480 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT ( \ 2481 is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT : \ 2482 is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT : \ 2483 is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT : \ 2484 /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT) 2485 #define UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK \ 2486 uv_undefined("UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK") 2487 #define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK ( \ 2488 is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK : \ 2489 is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK : \ 2490 is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK : \ 2491 /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK) 2492 #define UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT \ 2493 uv_undefined("UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT") 2494 #define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT ( \ 2495 is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT : \ 2496 is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT : \ 2497 is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT : \ 2498 /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT) 2499 2500 union uvh_lb_bau_misc_control_u { 2501 unsigned long v; 2502 struct uvh_lb_bau_misc_control_s { 2503 unsigned long rejection_delay:8; /* RW */ 2504 unsigned long apic_mode:1; /* RW */ 2505 unsigned long force_broadcast:1; /* RW */ 2506 unsigned long force_lock_nop:1; /* RW */ 2507 unsigned long qpi_agent_presence_vector:3; /* RW */ 2508 unsigned long descriptor_fetch_mode:1; /* RW */ 2509 unsigned long rsvd_15_19:5; 2510 unsigned long enable_dual_mapping_mode:1; /* RW */ 2511 unsigned long vga_io_port_decode_enable:1; /* RW */ 2512 unsigned long vga_io_port_16_bit_decode:1; /* RW */ 2513 unsigned long suppress_dest_registration:1; /* RW */ 2514 unsigned long programmed_initial_priority:3; /* RW */ 2515 unsigned long use_incoming_priority:1; /* RW */ 2516 unsigned long enable_programmed_initial_priority:1;/* RW */ 2517 unsigned long rsvd_29_47:19; 2518 unsigned long fun:16; /* RW */ 2519 } s; 2520 struct uv1h_lb_bau_misc_control_s { 2521 unsigned long rejection_delay:8; /* RW */ 2522 unsigned long apic_mode:1; /* RW */ 2523 unsigned long force_broadcast:1; /* RW */ 2524 unsigned long force_lock_nop:1; /* RW */ 2525 unsigned long qpi_agent_presence_vector:3; /* RW */ 2526 unsigned long descriptor_fetch_mode:1; /* RW */ 2527 unsigned long enable_intd_soft_ack_mode:1; /* RW */ 2528 unsigned long intd_soft_ack_timeout_period:4; /* RW */ 2529 unsigned long enable_dual_mapping_mode:1; /* RW */ 2530 unsigned long vga_io_port_decode_enable:1; /* RW */ 2531 unsigned long vga_io_port_16_bit_decode:1; /* RW */ 2532 unsigned long suppress_dest_registration:1; /* RW */ 2533 unsigned long programmed_initial_priority:3; /* RW */ 2534 unsigned long use_incoming_priority:1; /* RW */ 2535 unsigned long enable_programmed_initial_priority:1;/* RW */ 2536 unsigned long rsvd_29_47:19; 2537 unsigned long fun:16; /* RW */ 2538 } s1; 2539 struct uvxh_lb_bau_misc_control_s { 2540 unsigned long rejection_delay:8; /* RW */ 2541 unsigned long apic_mode:1; /* RW */ 2542 unsigned long force_broadcast:1; /* RW */ 2543 unsigned long force_lock_nop:1; /* RW */ 2544 unsigned long qpi_agent_presence_vector:3; /* RW */ 2545 unsigned long descriptor_fetch_mode:1; /* RW */ 2546 unsigned long rsvd_15_19:5; 2547 unsigned long enable_dual_mapping_mode:1; /* RW */ 2548 unsigned long vga_io_port_decode_enable:1; /* RW */ 2549 unsigned long vga_io_port_16_bit_decode:1; /* RW */ 2550 unsigned long suppress_dest_registration:1; /* RW */ 2551 unsigned long programmed_initial_priority:3; /* RW */ 2552 unsigned long use_incoming_priority:1; /* RW */ 2553 unsigned long enable_programmed_initial_priority:1;/* RW */ 2554 unsigned long enable_automatic_apic_mode_selection:1;/* RW */ 2555 unsigned long apic_mode_status:1; /* RO */ 2556 unsigned long suppress_interrupts_to_self:1; /* RW */ 2557 unsigned long enable_lock_based_system_flush:1;/* RW */ 2558 unsigned long enable_extended_sb_status:1; /* RW */ 2559 unsigned long suppress_int_prio_udt_to_self:1;/* RW */ 2560 unsigned long use_legacy_descriptor_formats:1;/* RW */ 2561 unsigned long rsvd_36_47:12; 2562 unsigned long fun:16; /* RW */ 2563 } sx; 2564 struct uv2h_lb_bau_misc_control_s { 2565 unsigned long rejection_delay:8; /* RW */ 2566 unsigned long apic_mode:1; /* RW */ 2567 unsigned long force_broadcast:1; /* RW */ 2568 unsigned long force_lock_nop:1; /* RW */ 2569 unsigned long qpi_agent_presence_vector:3; /* RW */ 2570 unsigned long descriptor_fetch_mode:1; /* RW */ 2571 unsigned long enable_intd_soft_ack_mode:1; /* RW */ 2572 unsigned long intd_soft_ack_timeout_period:4; /* RW */ 2573 unsigned long enable_dual_mapping_mode:1; /* RW */ 2574 unsigned long vga_io_port_decode_enable:1; /* RW */ 2575 unsigned long vga_io_port_16_bit_decode:1; /* RW */ 2576 unsigned long suppress_dest_registration:1; /* RW */ 2577 unsigned long programmed_initial_priority:3; /* RW */ 2578 unsigned long use_incoming_priority:1; /* RW */ 2579 unsigned long enable_programmed_initial_priority:1;/* RW */ 2580 unsigned long enable_automatic_apic_mode_selection:1;/* RW */ 2581 unsigned long apic_mode_status:1; /* RO */ 2582 unsigned long suppress_interrupts_to_self:1; /* RW */ 2583 unsigned long enable_lock_based_system_flush:1;/* RW */ 2584 unsigned long enable_extended_sb_status:1; /* RW */ 2585 unsigned long suppress_int_prio_udt_to_self:1;/* RW */ 2586 unsigned long use_legacy_descriptor_formats:1;/* RW */ 2587 unsigned long rsvd_36_47:12; 2588 unsigned long fun:16; /* RW */ 2589 } s2; 2590 struct uv3h_lb_bau_misc_control_s { 2591 unsigned long rejection_delay:8; /* RW */ 2592 unsigned long apic_mode:1; /* RW */ 2593 unsigned long force_broadcast:1; /* RW */ 2594 unsigned long force_lock_nop:1; /* RW */ 2595 unsigned long qpi_agent_presence_vector:3; /* RW */ 2596 unsigned long descriptor_fetch_mode:1; /* RW */ 2597 unsigned long enable_intd_soft_ack_mode:1; /* RW */ 2598 unsigned long intd_soft_ack_timeout_period:4; /* RW */ 2599 unsigned long enable_dual_mapping_mode:1; /* RW */ 2600 unsigned long vga_io_port_decode_enable:1; /* RW */ 2601 unsigned long vga_io_port_16_bit_decode:1; /* RW */ 2602 unsigned long suppress_dest_registration:1; /* RW */ 2603 unsigned long programmed_initial_priority:3; /* RW */ 2604 unsigned long use_incoming_priority:1; /* RW */ 2605 unsigned long enable_programmed_initial_priority:1;/* RW */ 2606 unsigned long enable_automatic_apic_mode_selection:1;/* RW */ 2607 unsigned long apic_mode_status:1; /* RO */ 2608 unsigned long suppress_interrupts_to_self:1; /* RW */ 2609 unsigned long enable_lock_based_system_flush:1;/* RW */ 2610 unsigned long enable_extended_sb_status:1; /* RW */ 2611 unsigned long suppress_int_prio_udt_to_self:1;/* RW */ 2612 unsigned long use_legacy_descriptor_formats:1;/* RW */ 2613 unsigned long suppress_quiesce_msgs_to_qpi:1; /* RW */ 2614 unsigned long enable_intd_prefetch_hint:1; /* RW */ 2615 unsigned long thread_kill_timebase:8; /* RW */ 2616 unsigned long rsvd_46_47:2; 2617 unsigned long fun:16; /* RW */ 2618 } s3; 2619 struct uv4h_lb_bau_misc_control_s { 2620 unsigned long rejection_delay:8; /* RW */ 2621 unsigned long apic_mode:1; /* RW */ 2622 unsigned long force_broadcast:1; /* RW */ 2623 unsigned long force_lock_nop:1; /* RW */ 2624 unsigned long qpi_agent_presence_vector:3; /* RW */ 2625 unsigned long descriptor_fetch_mode:1; /* RW */ 2626 unsigned long rsvd_15_19:5; 2627 unsigned long enable_dual_mapping_mode:1; /* RW */ 2628 unsigned long vga_io_port_decode_enable:1; /* RW */ 2629 unsigned long vga_io_port_16_bit_decode:1; /* RW */ 2630 unsigned long suppress_dest_registration:1; /* RW */ 2631 unsigned long programmed_initial_priority:3; /* RW */ 2632 unsigned long use_incoming_priority:1; /* RW */ 2633 unsigned long enable_programmed_initial_priority:1;/* RW */ 2634 unsigned long enable_automatic_apic_mode_selection:1;/* RW */ 2635 unsigned long apic_mode_status:1; /* RO */ 2636 unsigned long suppress_interrupts_to_self:1; /* RW */ 2637 unsigned long enable_lock_based_system_flush:1;/* RW */ 2638 unsigned long enable_extended_sb_status:1; /* RW */ 2639 unsigned long suppress_int_prio_udt_to_self:1;/* RW */ 2640 unsigned long use_legacy_descriptor_formats:1;/* RW */ 2641 unsigned long suppress_quiesce_msgs_to_qpi:1; /* RW */ 2642 unsigned long rsvd_37:1; 2643 unsigned long thread_kill_timebase:8; /* RW */ 2644 unsigned long address_interleave_select:1; /* RW */ 2645 unsigned long rsvd_47:1; 2646 unsigned long fun:16; /* RW */ 2647 } s4; 2648 }; 2649 2650 /* ========================================================================= */ 2651 /* UVH_LB_BAU_SB_ACTIVATION_CONTROL */ 2652 /* ========================================================================= */ 2653 #define UV1H_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL 2654 #define UV2H_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL 2655 #define UV3H_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL 2656 #define UV4H_LB_BAU_SB_ACTIVATION_CONTROL 0xc8020UL 2657 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL ( \ 2658 is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_CONTROL : \ 2659 is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_CONTROL : \ 2660 is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_CONTROL : \ 2661 /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_CONTROL) 2662 2663 #define UV1H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8 2664 #define UV2H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8 2665 #define UV3H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8 2666 #define UV4H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9c8 2667 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 ( \ 2668 is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_CONTROL_32 : \ 2669 is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_CONTROL_32 : \ 2670 is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_CONTROL_32 : \ 2671 /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_CONTROL_32) 2672 2673 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0 2674 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62 2675 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT 63 2676 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL 2677 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL 2678 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL 2679 2680 2681 union uvh_lb_bau_sb_activation_control_u { 2682 unsigned long v; 2683 struct uvh_lb_bau_sb_activation_control_s { 2684 unsigned long index:6; /* RW */ 2685 unsigned long rsvd_6_61:56; 2686 unsigned long push:1; /* WP */ 2687 unsigned long init:1; /* WP */ 2688 } s; 2689 }; 2690 2691 /* ========================================================================= */ 2692 /* UVH_LB_BAU_SB_ACTIVATION_STATUS_0 */ 2693 /* ========================================================================= */ 2694 #define UV1H_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL 2695 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL 2696 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL 2697 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_0 0xc8030UL 2698 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 ( \ 2699 is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_STATUS_0 : \ 2700 is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_0 : \ 2701 is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_0 : \ 2702 /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_0) 2703 2704 #define UV1H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0 2705 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0 2706 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0 2707 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9d0 2708 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 ( \ 2709 is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_STATUS_0_32 : \ 2710 is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_0_32 : \ 2711 is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_0_32 : \ 2712 /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_0_32) 2713 2714 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0 2715 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL 2716 2717 2718 union uvh_lb_bau_sb_activation_status_0_u { 2719 unsigned long v; 2720 struct uvh_lb_bau_sb_activation_status_0_s { 2721 unsigned long status:64; /* RW */ 2722 } s; 2723 }; 2724 2725 /* ========================================================================= */ 2726 /* UVH_LB_BAU_SB_ACTIVATION_STATUS_1 */ 2727 /* ========================================================================= */ 2728 #define UV1H_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL 2729 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL 2730 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL 2731 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_1 0xc8040UL 2732 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 ( \ 2733 is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_STATUS_1 : \ 2734 is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_1 : \ 2735 is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_1 : \ 2736 /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_1) 2737 2738 #define UV1H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8 2739 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8 2740 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8 2741 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9d8 2742 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 ( \ 2743 is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_STATUS_1_32 : \ 2744 is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_1_32 : \ 2745 is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_1_32 : \ 2746 /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_1_32) 2747 2748 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0 2749 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL 2750 2751 2752 union uvh_lb_bau_sb_activation_status_1_u { 2753 unsigned long v; 2754 struct uvh_lb_bau_sb_activation_status_1_s { 2755 unsigned long status:64; /* RW */ 2756 } s; 2757 }; 2758 2759 /* ========================================================================= */ 2760 /* UVH_LB_BAU_SB_DESCRIPTOR_BASE */ 2761 /* ========================================================================= */ 2762 #define UV1H_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL 2763 #define UV2H_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL 2764 #define UV3H_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL 2765 #define UV4H_LB_BAU_SB_DESCRIPTOR_BASE 0xc8010UL 2766 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE ( \ 2767 is_uv1_hub() ? UV1H_LB_BAU_SB_DESCRIPTOR_BASE : \ 2768 is_uv2_hub() ? UV2H_LB_BAU_SB_DESCRIPTOR_BASE : \ 2769 is_uv3_hub() ? UV3H_LB_BAU_SB_DESCRIPTOR_BASE : \ 2770 /*is_uv4_hub*/ UV4H_LB_BAU_SB_DESCRIPTOR_BASE) 2771 2772 #define UV1H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0 2773 #define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0 2774 #define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0 2775 #define UV4H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9c0 2776 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 ( \ 2777 is_uv1_hub() ? UV1H_LB_BAU_SB_DESCRIPTOR_BASE_32 : \ 2778 is_uv2_hub() ? UV2H_LB_BAU_SB_DESCRIPTOR_BASE_32 : \ 2779 is_uv3_hub() ? UV3H_LB_BAU_SB_DESCRIPTOR_BASE_32 : \ 2780 /*is_uv4_hub*/ UV4H_LB_BAU_SB_DESCRIPTOR_BASE_32) 2781 2782 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12 2783 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49 2784 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL 2785 2786 #define UV1H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL 2787 2788 2789 #define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL 2790 2791 #define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL 2792 2793 #define UV4H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x00003ffffffff000UL 2794 2795 2796 union uvh_lb_bau_sb_descriptor_base_u { 2797 unsigned long v; 2798 struct uvh_lb_bau_sb_descriptor_base_s { 2799 unsigned long rsvd_0_11:12; 2800 unsigned long rsvd_12_48:37; 2801 unsigned long node_id:14; /* RW */ 2802 unsigned long rsvd_63:1; 2803 } s; 2804 struct uv4h_lb_bau_sb_descriptor_base_s { 2805 unsigned long rsvd_0_11:12; 2806 unsigned long page_address:34; /* RW */ 2807 unsigned long rsvd_46_48:3; 2808 unsigned long node_id:14; /* RW */ 2809 unsigned long rsvd_63:1; 2810 } s4; 2811 }; 2812 2813 /* ========================================================================= */ 2814 /* UVH_NODE_ID */ 2815 /* ========================================================================= */ 2816 #define UVH_NODE_ID 0x0UL 2817 #define UV1H_NODE_ID 0x0UL 2818 #define UV2H_NODE_ID 0x0UL 2819 #define UV3H_NODE_ID 0x0UL 2820 #define UV4H_NODE_ID 0x0UL 2821 2822 #define UVH_NODE_ID_FORCE1_SHFT 0 2823 #define UVH_NODE_ID_MANUFACTURER_SHFT 1 2824 #define UVH_NODE_ID_PART_NUMBER_SHFT 12 2825 #define UVH_NODE_ID_REVISION_SHFT 28 2826 #define UVH_NODE_ID_NODE_ID_SHFT 32 2827 #define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL 2828 #define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL 2829 #define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL 2830 #define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL 2831 #define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 2832 2833 #define UV1H_NODE_ID_FORCE1_SHFT 0 2834 #define UV1H_NODE_ID_MANUFACTURER_SHFT 1 2835 #define UV1H_NODE_ID_PART_NUMBER_SHFT 12 2836 #define UV1H_NODE_ID_REVISION_SHFT 28 2837 #define UV1H_NODE_ID_NODE_ID_SHFT 32 2838 #define UV1H_NODE_ID_NODES_PER_BIT_SHFT 48 2839 #define UV1H_NODE_ID_NI_PORT_SHFT 56 2840 #define UV1H_NODE_ID_FORCE1_MASK 0x0000000000000001UL 2841 #define UV1H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL 2842 #define UV1H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL 2843 #define UV1H_NODE_ID_REVISION_MASK 0x00000000f0000000UL 2844 #define UV1H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 2845 #define UV1H_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL 2846 #define UV1H_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL 2847 2848 #define UVXH_NODE_ID_FORCE1_SHFT 0 2849 #define UVXH_NODE_ID_MANUFACTURER_SHFT 1 2850 #define UVXH_NODE_ID_PART_NUMBER_SHFT 12 2851 #define UVXH_NODE_ID_REVISION_SHFT 28 2852 #define UVXH_NODE_ID_NODE_ID_SHFT 32 2853 #define UVXH_NODE_ID_NODES_PER_BIT_SHFT 50 2854 #define UVXH_NODE_ID_NI_PORT_SHFT 57 2855 #define UVXH_NODE_ID_FORCE1_MASK 0x0000000000000001UL 2856 #define UVXH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL 2857 #define UVXH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL 2858 #define UVXH_NODE_ID_REVISION_MASK 0x00000000f0000000UL 2859 #define UVXH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 2860 #define UVXH_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL 2861 #define UVXH_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL 2862 2863 #define UV2H_NODE_ID_FORCE1_SHFT 0 2864 #define UV2H_NODE_ID_MANUFACTURER_SHFT 1 2865 #define UV2H_NODE_ID_PART_NUMBER_SHFT 12 2866 #define UV2H_NODE_ID_REVISION_SHFT 28 2867 #define UV2H_NODE_ID_NODE_ID_SHFT 32 2868 #define UV2H_NODE_ID_NODES_PER_BIT_SHFT 50 2869 #define UV2H_NODE_ID_NI_PORT_SHFT 57 2870 #define UV2H_NODE_ID_FORCE1_MASK 0x0000000000000001UL 2871 #define UV2H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL 2872 #define UV2H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL 2873 #define UV2H_NODE_ID_REVISION_MASK 0x00000000f0000000UL 2874 #define UV2H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 2875 #define UV2H_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL 2876 #define UV2H_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL 2877 2878 #define UV3H_NODE_ID_FORCE1_SHFT 0 2879 #define UV3H_NODE_ID_MANUFACTURER_SHFT 1 2880 #define UV3H_NODE_ID_PART_NUMBER_SHFT 12 2881 #define UV3H_NODE_ID_REVISION_SHFT 28 2882 #define UV3H_NODE_ID_NODE_ID_SHFT 32 2883 #define UV3H_NODE_ID_ROUTER_SELECT_SHFT 48 2884 #define UV3H_NODE_ID_RESERVED_2_SHFT 49 2885 #define UV3H_NODE_ID_NODES_PER_BIT_SHFT 50 2886 #define UV3H_NODE_ID_NI_PORT_SHFT 57 2887 #define UV3H_NODE_ID_FORCE1_MASK 0x0000000000000001UL 2888 #define UV3H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL 2889 #define UV3H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL 2890 #define UV3H_NODE_ID_REVISION_MASK 0x00000000f0000000UL 2891 #define UV3H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 2892 #define UV3H_NODE_ID_ROUTER_SELECT_MASK 0x0001000000000000UL 2893 #define UV3H_NODE_ID_RESERVED_2_MASK 0x0002000000000000UL 2894 #define UV3H_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL 2895 #define UV3H_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL 2896 2897 #define UV4H_NODE_ID_FORCE1_SHFT 0 2898 #define UV4H_NODE_ID_MANUFACTURER_SHFT 1 2899 #define UV4H_NODE_ID_PART_NUMBER_SHFT 12 2900 #define UV4H_NODE_ID_REVISION_SHFT 28 2901 #define UV4H_NODE_ID_NODE_ID_SHFT 32 2902 #define UV4H_NODE_ID_ROUTER_SELECT_SHFT 48 2903 #define UV4H_NODE_ID_RESERVED_2_SHFT 49 2904 #define UV4H_NODE_ID_NODES_PER_BIT_SHFT 50 2905 #define UV4H_NODE_ID_NI_PORT_SHFT 57 2906 #define UV4H_NODE_ID_FORCE1_MASK 0x0000000000000001UL 2907 #define UV4H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL 2908 #define UV4H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL 2909 #define UV4H_NODE_ID_REVISION_MASK 0x00000000f0000000UL 2910 #define UV4H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 2911 #define UV4H_NODE_ID_ROUTER_SELECT_MASK 0x0001000000000000UL 2912 #define UV4H_NODE_ID_RESERVED_2_MASK 0x0002000000000000UL 2913 #define UV4H_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL 2914 #define UV4H_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL 2915 2916 2917 union uvh_node_id_u { 2918 unsigned long v; 2919 struct uvh_node_id_s { 2920 unsigned long force1:1; /* RO */ 2921 unsigned long manufacturer:11; /* RO */ 2922 unsigned long part_number:16; /* RO */ 2923 unsigned long revision:4; /* RO */ 2924 unsigned long node_id:15; /* RW */ 2925 unsigned long rsvd_47_63:17; 2926 } s; 2927 struct uv1h_node_id_s { 2928 unsigned long force1:1; /* RO */ 2929 unsigned long manufacturer:11; /* RO */ 2930 unsigned long part_number:16; /* RO */ 2931 unsigned long revision:4; /* RO */ 2932 unsigned long node_id:15; /* RW */ 2933 unsigned long rsvd_47:1; 2934 unsigned long nodes_per_bit:7; /* RW */ 2935 unsigned long rsvd_55:1; 2936 unsigned long ni_port:4; /* RO */ 2937 unsigned long rsvd_60_63:4; 2938 } s1; 2939 struct uvxh_node_id_s { 2940 unsigned long force1:1; /* RO */ 2941 unsigned long manufacturer:11; /* RO */ 2942 unsigned long part_number:16; /* RO */ 2943 unsigned long revision:4; /* RO */ 2944 unsigned long node_id:15; /* RW */ 2945 unsigned long rsvd_47_49:3; 2946 unsigned long nodes_per_bit:7; /* RO */ 2947 unsigned long ni_port:5; /* RO */ 2948 unsigned long rsvd_62_63:2; 2949 } sx; 2950 struct uv2h_node_id_s { 2951 unsigned long force1:1; /* RO */ 2952 unsigned long manufacturer:11; /* RO */ 2953 unsigned long part_number:16; /* RO */ 2954 unsigned long revision:4; /* RO */ 2955 unsigned long node_id:15; /* RW */ 2956 unsigned long rsvd_47_49:3; 2957 unsigned long nodes_per_bit:7; /* RO */ 2958 unsigned long ni_port:5; /* RO */ 2959 unsigned long rsvd_62_63:2; 2960 } s2; 2961 struct uv3h_node_id_s { 2962 unsigned long force1:1; /* RO */ 2963 unsigned long manufacturer:11; /* RO */ 2964 unsigned long part_number:16; /* RO */ 2965 unsigned long revision:4; /* RO */ 2966 unsigned long node_id:15; /* RW */ 2967 unsigned long rsvd_47:1; 2968 unsigned long router_select:1; /* RO */ 2969 unsigned long rsvd_49:1; 2970 unsigned long nodes_per_bit:7; /* RO */ 2971 unsigned long ni_port:5; /* RO */ 2972 unsigned long rsvd_62_63:2; 2973 } s3; 2974 struct uv4h_node_id_s { 2975 unsigned long force1:1; /* RO */ 2976 unsigned long manufacturer:11; /* RO */ 2977 unsigned long part_number:16; /* RO */ 2978 unsigned long revision:4; /* RO */ 2979 unsigned long node_id:15; /* RW */ 2980 unsigned long rsvd_47:1; 2981 unsigned long router_select:1; /* RO */ 2982 unsigned long rsvd_49:1; 2983 unsigned long nodes_per_bit:7; /* RO */ 2984 unsigned long ni_port:5; /* RO */ 2985 unsigned long rsvd_62_63:2; 2986 } s4; 2987 }; 2988 2989 /* ========================================================================= */ 2990 /* UVH_NODE_PRESENT_TABLE */ 2991 /* ========================================================================= */ 2992 #define UVH_NODE_PRESENT_TABLE 0x1400UL 2993 2994 #define UV1H_NODE_PRESENT_TABLE_DEPTH 16 2995 #define UV2H_NODE_PRESENT_TABLE_DEPTH 16 2996 #define UV3H_NODE_PRESENT_TABLE_DEPTH 16 2997 #define UV4H_NODE_PRESENT_TABLE_DEPTH 4 2998 #define UVH_NODE_PRESENT_TABLE_DEPTH ( \ 2999 is_uv1_hub() ? UV1H_NODE_PRESENT_TABLE_DEPTH : \ 3000 is_uv2_hub() ? UV2H_NODE_PRESENT_TABLE_DEPTH : \ 3001 is_uv3_hub() ? UV3H_NODE_PRESENT_TABLE_DEPTH : \ 3002 /*is_uv4_hub*/ UV4H_NODE_PRESENT_TABLE_DEPTH) 3003 3004 #define UVH_NODE_PRESENT_TABLE_NODES_SHFT 0 3005 #define UVH_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL 3006 3007 3008 union uvh_node_present_table_u { 3009 unsigned long v; 3010 struct uvh_node_present_table_s { 3011 unsigned long nodes:64; /* RW */ 3012 } s; 3013 }; 3014 3015 /* ========================================================================= */ 3016 /* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR */ 3017 /* ========================================================================= */ 3018 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL 3019 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL 3020 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL 3021 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x4800c8UL 3022 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR ( \ 3023 is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR : \ 3024 is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR : \ 3025 is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR : \ 3026 /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR) 3027 3028 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24 3029 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48 3030 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63 3031 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL 3032 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL 3033 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL 3034 3035 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24 3036 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48 3037 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63 3038 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL 3039 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL 3040 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL 3041 3042 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24 3043 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48 3044 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63 3045 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL 3046 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL 3047 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL 3048 3049 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24 3050 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48 3051 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63 3052 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL 3053 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL 3054 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL 3055 3056 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24 3057 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48 3058 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63 3059 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL 3060 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL 3061 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL 3062 3063 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24 3064 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48 3065 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63 3066 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL 3067 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL 3068 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL 3069 3070 3071 union uvh_rh_gam_alias210_overlay_config_0_mmr_u { 3072 unsigned long v; 3073 struct uvh_rh_gam_alias210_overlay_config_0_mmr_s { 3074 unsigned long rsvd_0_23:24; 3075 unsigned long base:8; /* RW */ 3076 unsigned long rsvd_32_47:16; 3077 unsigned long m_alias:5; /* RW */ 3078 unsigned long rsvd_53_62:10; 3079 unsigned long enable:1; /* RW */ 3080 } s; 3081 struct uv1h_rh_gam_alias210_overlay_config_0_mmr_s { 3082 unsigned long rsvd_0_23:24; 3083 unsigned long base:8; /* RW */ 3084 unsigned long rsvd_32_47:16; 3085 unsigned long m_alias:5; /* RW */ 3086 unsigned long rsvd_53_62:10; 3087 unsigned long enable:1; /* RW */ 3088 } s1; 3089 struct uvxh_rh_gam_alias210_overlay_config_0_mmr_s { 3090 unsigned long rsvd_0_23:24; 3091 unsigned long base:8; /* RW */ 3092 unsigned long rsvd_32_47:16; 3093 unsigned long m_alias:5; /* RW */ 3094 unsigned long rsvd_53_62:10; 3095 unsigned long enable:1; /* RW */ 3096 } sx; 3097 struct uv2h_rh_gam_alias210_overlay_config_0_mmr_s { 3098 unsigned long rsvd_0_23:24; 3099 unsigned long base:8; /* RW */ 3100 unsigned long rsvd_32_47:16; 3101 unsigned long m_alias:5; /* RW */ 3102 unsigned long rsvd_53_62:10; 3103 unsigned long enable:1; /* RW */ 3104 } s2; 3105 struct uv3h_rh_gam_alias210_overlay_config_0_mmr_s { 3106 unsigned long rsvd_0_23:24; 3107 unsigned long base:8; /* RW */ 3108 unsigned long rsvd_32_47:16; 3109 unsigned long m_alias:5; /* RW */ 3110 unsigned long rsvd_53_62:10; 3111 unsigned long enable:1; /* RW */ 3112 } s3; 3113 struct uv4h_rh_gam_alias210_overlay_config_0_mmr_s { 3114 unsigned long rsvd_0_23:24; 3115 unsigned long base:8; /* RW */ 3116 unsigned long rsvd_32_47:16; 3117 unsigned long m_alias:5; /* RW */ 3118 unsigned long rsvd_53_62:10; 3119 unsigned long enable:1; /* RW */ 3120 } s4; 3121 }; 3122 3123 /* ========================================================================= */ 3124 /* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR */ 3125 /* ========================================================================= */ 3126 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL 3127 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL 3128 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL 3129 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x4800d8UL 3130 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR ( \ 3131 is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR : \ 3132 is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR : \ 3133 is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR : \ 3134 /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR) 3135 3136 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24 3137 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48 3138 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63 3139 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL 3140 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL 3141 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL 3142 3143 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24 3144 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48 3145 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63 3146 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL 3147 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL 3148 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL 3149 3150 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24 3151 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48 3152 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63 3153 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL 3154 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL 3155 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL 3156 3157 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24 3158 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48 3159 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63 3160 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL 3161 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL 3162 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL 3163 3164 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24 3165 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48 3166 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63 3167 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL 3168 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL 3169 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL 3170 3171 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24 3172 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48 3173 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63 3174 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL 3175 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL 3176 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL 3177 3178 3179 union uvh_rh_gam_alias210_overlay_config_1_mmr_u { 3180 unsigned long v; 3181 struct uvh_rh_gam_alias210_overlay_config_1_mmr_s { 3182 unsigned long rsvd_0_23:24; 3183 unsigned long base:8; /* RW */ 3184 unsigned long rsvd_32_47:16; 3185 unsigned long m_alias:5; /* RW */ 3186 unsigned long rsvd_53_62:10; 3187 unsigned long enable:1; /* RW */ 3188 } s; 3189 struct uv1h_rh_gam_alias210_overlay_config_1_mmr_s { 3190 unsigned long rsvd_0_23:24; 3191 unsigned long base:8; /* RW */ 3192 unsigned long rsvd_32_47:16; 3193 unsigned long m_alias:5; /* RW */ 3194 unsigned long rsvd_53_62:10; 3195 unsigned long enable:1; /* RW */ 3196 } s1; 3197 struct uvxh_rh_gam_alias210_overlay_config_1_mmr_s { 3198 unsigned long rsvd_0_23:24; 3199 unsigned long base:8; /* RW */ 3200 unsigned long rsvd_32_47:16; 3201 unsigned long m_alias:5; /* RW */ 3202 unsigned long rsvd_53_62:10; 3203 unsigned long enable:1; /* RW */ 3204 } sx; 3205 struct uv2h_rh_gam_alias210_overlay_config_1_mmr_s { 3206 unsigned long rsvd_0_23:24; 3207 unsigned long base:8; /* RW */ 3208 unsigned long rsvd_32_47:16; 3209 unsigned long m_alias:5; /* RW */ 3210 unsigned long rsvd_53_62:10; 3211 unsigned long enable:1; /* RW */ 3212 } s2; 3213 struct uv3h_rh_gam_alias210_overlay_config_1_mmr_s { 3214 unsigned long rsvd_0_23:24; 3215 unsigned long base:8; /* RW */ 3216 unsigned long rsvd_32_47:16; 3217 unsigned long m_alias:5; /* RW */ 3218 unsigned long rsvd_53_62:10; 3219 unsigned long enable:1; /* RW */ 3220 } s3; 3221 struct uv4h_rh_gam_alias210_overlay_config_1_mmr_s { 3222 unsigned long rsvd_0_23:24; 3223 unsigned long base:8; /* RW */ 3224 unsigned long rsvd_32_47:16; 3225 unsigned long m_alias:5; /* RW */ 3226 unsigned long rsvd_53_62:10; 3227 unsigned long enable:1; /* RW */ 3228 } s4; 3229 }; 3230 3231 /* ========================================================================= */ 3232 /* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR */ 3233 /* ========================================================================= */ 3234 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL 3235 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL 3236 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL 3237 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x4800e8UL 3238 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR ( \ 3239 is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR : \ 3240 is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR : \ 3241 is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR : \ 3242 /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR) 3243 3244 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24 3245 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48 3246 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63 3247 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL 3248 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL 3249 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL 3250 3251 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24 3252 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48 3253 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63 3254 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL 3255 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL 3256 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL 3257 3258 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24 3259 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48 3260 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63 3261 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL 3262 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL 3263 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL 3264 3265 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24 3266 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48 3267 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63 3268 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL 3269 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL 3270 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL 3271 3272 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24 3273 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48 3274 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63 3275 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL 3276 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL 3277 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL 3278 3279 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24 3280 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48 3281 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63 3282 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL 3283 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL 3284 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL 3285 3286 3287 union uvh_rh_gam_alias210_overlay_config_2_mmr_u { 3288 unsigned long v; 3289 struct uvh_rh_gam_alias210_overlay_config_2_mmr_s { 3290 unsigned long rsvd_0_23:24; 3291 unsigned long base:8; /* RW */ 3292 unsigned long rsvd_32_47:16; 3293 unsigned long m_alias:5; /* RW */ 3294 unsigned long rsvd_53_62:10; 3295 unsigned long enable:1; /* RW */ 3296 } s; 3297 struct uv1h_rh_gam_alias210_overlay_config_2_mmr_s { 3298 unsigned long rsvd_0_23:24; 3299 unsigned long base:8; /* RW */ 3300 unsigned long rsvd_32_47:16; 3301 unsigned long m_alias:5; /* RW */ 3302 unsigned long rsvd_53_62:10; 3303 unsigned long enable:1; /* RW */ 3304 } s1; 3305 struct uvxh_rh_gam_alias210_overlay_config_2_mmr_s { 3306 unsigned long rsvd_0_23:24; 3307 unsigned long base:8; /* RW */ 3308 unsigned long rsvd_32_47:16; 3309 unsigned long m_alias:5; /* RW */ 3310 unsigned long rsvd_53_62:10; 3311 unsigned long enable:1; /* RW */ 3312 } sx; 3313 struct uv2h_rh_gam_alias210_overlay_config_2_mmr_s { 3314 unsigned long rsvd_0_23:24; 3315 unsigned long base:8; /* RW */ 3316 unsigned long rsvd_32_47:16; 3317 unsigned long m_alias:5; /* RW */ 3318 unsigned long rsvd_53_62:10; 3319 unsigned long enable:1; /* RW */ 3320 } s2; 3321 struct uv3h_rh_gam_alias210_overlay_config_2_mmr_s { 3322 unsigned long rsvd_0_23:24; 3323 unsigned long base:8; /* RW */ 3324 unsigned long rsvd_32_47:16; 3325 unsigned long m_alias:5; /* RW */ 3326 unsigned long rsvd_53_62:10; 3327 unsigned long enable:1; /* RW */ 3328 } s3; 3329 struct uv4h_rh_gam_alias210_overlay_config_2_mmr_s { 3330 unsigned long rsvd_0_23:24; 3331 unsigned long base:8; /* RW */ 3332 unsigned long rsvd_32_47:16; 3333 unsigned long m_alias:5; /* RW */ 3334 unsigned long rsvd_53_62:10; 3335 unsigned long enable:1; /* RW */ 3336 } s4; 3337 }; 3338 3339 /* ========================================================================= */ 3340 /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */ 3341 /* ========================================================================= */ 3342 #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL 3343 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL 3344 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL 3345 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x4800d0UL 3346 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR ( \ 3347 is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR : \ 3348 is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR : \ 3349 is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR : \ 3350 /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR) 3351 3352 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 3353 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL 3354 3355 #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 3356 #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL 3357 3358 #define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 3359 #define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL 3360 3361 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 3362 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL 3363 3364 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 3365 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL 3366 3367 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 3368 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL 3369 3370 3371 union uvh_rh_gam_alias210_redirect_config_0_mmr_u { 3372 unsigned long v; 3373 struct uvh_rh_gam_alias210_redirect_config_0_mmr_s { 3374 unsigned long rsvd_0_23:24; 3375 unsigned long dest_base:22; /* RW */ 3376 unsigned long rsvd_46_63:18; 3377 } s; 3378 struct uv1h_rh_gam_alias210_redirect_config_0_mmr_s { 3379 unsigned long rsvd_0_23:24; 3380 unsigned long dest_base:22; /* RW */ 3381 unsigned long rsvd_46_63:18; 3382 } s1; 3383 struct uvxh_rh_gam_alias210_redirect_config_0_mmr_s { 3384 unsigned long rsvd_0_23:24; 3385 unsigned long dest_base:22; /* RW */ 3386 unsigned long rsvd_46_63:18; 3387 } sx; 3388 struct uv2h_rh_gam_alias210_redirect_config_0_mmr_s { 3389 unsigned long rsvd_0_23:24; 3390 unsigned long dest_base:22; /* RW */ 3391 unsigned long rsvd_46_63:18; 3392 } s2; 3393 struct uv3h_rh_gam_alias210_redirect_config_0_mmr_s { 3394 unsigned long rsvd_0_23:24; 3395 unsigned long dest_base:22; /* RW */ 3396 unsigned long rsvd_46_63:18; 3397 } s3; 3398 struct uv4h_rh_gam_alias210_redirect_config_0_mmr_s { 3399 unsigned long rsvd_0_23:24; 3400 unsigned long dest_base:22; /* RW */ 3401 unsigned long rsvd_46_63:18; 3402 } s4; 3403 }; 3404 3405 /* ========================================================================= */ 3406 /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */ 3407 /* ========================================================================= */ 3408 #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL 3409 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL 3410 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL 3411 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x4800e0UL 3412 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR ( \ 3413 is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR : \ 3414 is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR : \ 3415 is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR : \ 3416 /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR) 3417 3418 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 3419 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL 3420 3421 #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 3422 #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL 3423 3424 #define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 3425 #define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL 3426 3427 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 3428 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL 3429 3430 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 3431 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL 3432 3433 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 3434 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL 3435 3436 3437 union uvh_rh_gam_alias210_redirect_config_1_mmr_u { 3438 unsigned long v; 3439 struct uvh_rh_gam_alias210_redirect_config_1_mmr_s { 3440 unsigned long rsvd_0_23:24; 3441 unsigned long dest_base:22; /* RW */ 3442 unsigned long rsvd_46_63:18; 3443 } s; 3444 struct uv1h_rh_gam_alias210_redirect_config_1_mmr_s { 3445 unsigned long rsvd_0_23:24; 3446 unsigned long dest_base:22; /* RW */ 3447 unsigned long rsvd_46_63:18; 3448 } s1; 3449 struct uvxh_rh_gam_alias210_redirect_config_1_mmr_s { 3450 unsigned long rsvd_0_23:24; 3451 unsigned long dest_base:22; /* RW */ 3452 unsigned long rsvd_46_63:18; 3453 } sx; 3454 struct uv2h_rh_gam_alias210_redirect_config_1_mmr_s { 3455 unsigned long rsvd_0_23:24; 3456 unsigned long dest_base:22; /* RW */ 3457 unsigned long rsvd_46_63:18; 3458 } s2; 3459 struct uv3h_rh_gam_alias210_redirect_config_1_mmr_s { 3460 unsigned long rsvd_0_23:24; 3461 unsigned long dest_base:22; /* RW */ 3462 unsigned long rsvd_46_63:18; 3463 } s3; 3464 struct uv4h_rh_gam_alias210_redirect_config_1_mmr_s { 3465 unsigned long rsvd_0_23:24; 3466 unsigned long dest_base:22; /* RW */ 3467 unsigned long rsvd_46_63:18; 3468 } s4; 3469 }; 3470 3471 /* ========================================================================= */ 3472 /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */ 3473 /* ========================================================================= */ 3474 #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL 3475 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL 3476 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL 3477 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x4800f0UL 3478 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR ( \ 3479 is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR : \ 3480 is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR : \ 3481 is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR : \ 3482 /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR) 3483 3484 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 3485 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL 3486 3487 #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 3488 #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL 3489 3490 #define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 3491 #define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL 3492 3493 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 3494 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL 3495 3496 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 3497 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL 3498 3499 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 3500 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL 3501 3502 3503 union uvh_rh_gam_alias210_redirect_config_2_mmr_u { 3504 unsigned long v; 3505 struct uvh_rh_gam_alias210_redirect_config_2_mmr_s { 3506 unsigned long rsvd_0_23:24; 3507 unsigned long dest_base:22; /* RW */ 3508 unsigned long rsvd_46_63:18; 3509 } s; 3510 struct uv1h_rh_gam_alias210_redirect_config_2_mmr_s { 3511 unsigned long rsvd_0_23:24; 3512 unsigned long dest_base:22; /* RW */ 3513 unsigned long rsvd_46_63:18; 3514 } s1; 3515 struct uvxh_rh_gam_alias210_redirect_config_2_mmr_s { 3516 unsigned long rsvd_0_23:24; 3517 unsigned long dest_base:22; /* RW */ 3518 unsigned long rsvd_46_63:18; 3519 } sx; 3520 struct uv2h_rh_gam_alias210_redirect_config_2_mmr_s { 3521 unsigned long rsvd_0_23:24; 3522 unsigned long dest_base:22; /* RW */ 3523 unsigned long rsvd_46_63:18; 3524 } s2; 3525 struct uv3h_rh_gam_alias210_redirect_config_2_mmr_s { 3526 unsigned long rsvd_0_23:24; 3527 unsigned long dest_base:22; /* RW */ 3528 unsigned long rsvd_46_63:18; 3529 } s3; 3530 struct uv4h_rh_gam_alias210_redirect_config_2_mmr_s { 3531 unsigned long rsvd_0_23:24; 3532 unsigned long dest_base:22; /* RW */ 3533 unsigned long rsvd_46_63:18; 3534 } s4; 3535 }; 3536 3537 /* ========================================================================= */ 3538 /* UVH_RH_GAM_CONFIG_MMR */ 3539 /* ========================================================================= */ 3540 #define UV1H_RH_GAM_CONFIG_MMR 0x1600000UL 3541 #define UV2H_RH_GAM_CONFIG_MMR 0x1600000UL 3542 #define UV3H_RH_GAM_CONFIG_MMR 0x1600000UL 3543 #define UV4H_RH_GAM_CONFIG_MMR 0x480000UL 3544 #define UVH_RH_GAM_CONFIG_MMR ( \ 3545 is_uv1_hub() ? UV1H_RH_GAM_CONFIG_MMR : \ 3546 is_uv2_hub() ? UV2H_RH_GAM_CONFIG_MMR : \ 3547 is_uv3_hub() ? UV3H_RH_GAM_CONFIG_MMR : \ 3548 /*is_uv4_hub*/ UV4H_RH_GAM_CONFIG_MMR) 3549 3550 #define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 3551 #define UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 3552 3553 #define UV1H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 3554 #define UV1H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 3555 #define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_SHFT 12 3556 #define UV1H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL 3557 #define UV1H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 3558 #define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK 0x0000000000001000UL 3559 3560 #define UVXH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 3561 #define UVXH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 3562 3563 #define UV2H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 3564 #define UV2H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 3565 #define UV2H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL 3566 #define UV2H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 3567 3568 #define UV3H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 3569 #define UV3H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 3570 #define UV3H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL 3571 #define UV3H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 3572 3573 #define UV4H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 3574 #define UV4H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 3575 3576 3577 union uvh_rh_gam_config_mmr_u { 3578 unsigned long v; 3579 struct uvh_rh_gam_config_mmr_s { 3580 unsigned long rsvd_0_5:6; 3581 unsigned long n_skt:4; /* RW */ 3582 unsigned long rsvd_10_63:54; 3583 } s; 3584 struct uv1h_rh_gam_config_mmr_s { 3585 unsigned long m_skt:6; /* RW */ 3586 unsigned long n_skt:4; /* RW */ 3587 unsigned long rsvd_10_11:2; 3588 unsigned long mmiol_cfg:1; /* RW */ 3589 unsigned long rsvd_13_63:51; 3590 } s1; 3591 struct uvxh_rh_gam_config_mmr_s { 3592 unsigned long rsvd_0_5:6; 3593 unsigned long n_skt:4; /* RW */ 3594 unsigned long rsvd_10_63:54; 3595 } sx; 3596 struct uv2h_rh_gam_config_mmr_s { 3597 unsigned long m_skt:6; /* RW */ 3598 unsigned long n_skt:4; /* RW */ 3599 unsigned long rsvd_10_63:54; 3600 } s2; 3601 struct uv3h_rh_gam_config_mmr_s { 3602 unsigned long m_skt:6; /* RW */ 3603 unsigned long n_skt:4; /* RW */ 3604 unsigned long rsvd_10_63:54; 3605 } s3; 3606 struct uv4h_rh_gam_config_mmr_s { 3607 unsigned long rsvd_0_5:6; 3608 unsigned long n_skt:4; /* RW */ 3609 unsigned long rsvd_10_63:54; 3610 } s4; 3611 }; 3612 3613 /* ========================================================================= */ 3614 /* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */ 3615 /* ========================================================================= */ 3616 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL 3617 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL 3618 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL 3619 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x480010UL 3620 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR ( \ 3621 is_uv1_hub() ? UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR : \ 3622 is_uv2_hub() ? UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR : \ 3623 is_uv3_hub() ? UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR : \ 3624 /*is_uv4_hub*/ UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR) 3625 3626 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 3627 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3628 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 3629 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3630 3631 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 3632 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48 3633 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 3634 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3635 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL 3636 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL 3637 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 3638 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3639 3640 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 3641 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3642 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 3643 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3644 3645 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 3646 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 3647 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3648 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL 3649 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 3650 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3651 3652 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 3653 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 3654 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_MODE_SHFT 62 3655 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3656 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL 3657 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 3658 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_MODE_MASK 0x4000000000000000UL 3659 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3660 3661 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 26 3662 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 3663 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3664 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 3665 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 3666 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3667 3668 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK ( \ 3669 is_uv1_hub() ? UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK : \ 3670 is_uv2_hub() ? UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK : \ 3671 is_uv3_hub() ? UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK : \ 3672 /*is_uv4_hub*/ UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK) 3673 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT ( \ 3674 is_uv1_hub() ? UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT : \ 3675 is_uv2_hub() ? UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT : \ 3676 is_uv3_hub() ? UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT : \ 3677 /*is_uv4_hub*/ UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT) 3678 3679 union uvh_rh_gam_gru_overlay_config_mmr_u { 3680 unsigned long v; 3681 struct uvh_rh_gam_gru_overlay_config_mmr_s { 3682 unsigned long rsvd_0_51:52; 3683 unsigned long n_gru:4; /* RW */ 3684 unsigned long rsvd_56_62:7; 3685 unsigned long enable:1; /* RW */ 3686 } s; 3687 struct uv1h_rh_gam_gru_overlay_config_mmr_s { 3688 unsigned long rsvd_0_27:28; 3689 unsigned long base:18; /* RW */ 3690 unsigned long rsvd_46_47:2; 3691 unsigned long gr4:1; /* RW */ 3692 unsigned long rsvd_49_51:3; 3693 unsigned long n_gru:4; /* RW */ 3694 unsigned long rsvd_56_62:7; 3695 unsigned long enable:1; /* RW */ 3696 } s1; 3697 struct uvxh_rh_gam_gru_overlay_config_mmr_s { 3698 unsigned long rsvd_0_45:46; 3699 unsigned long rsvd_46_51:6; 3700 unsigned long n_gru:4; /* RW */ 3701 unsigned long rsvd_56_62:7; 3702 unsigned long enable:1; /* RW */ 3703 } sx; 3704 struct uv2h_rh_gam_gru_overlay_config_mmr_s { 3705 unsigned long rsvd_0_27:28; 3706 unsigned long base:18; /* RW */ 3707 unsigned long rsvd_46_51:6; 3708 unsigned long n_gru:4; /* RW */ 3709 unsigned long rsvd_56_62:7; 3710 unsigned long enable:1; /* RW */ 3711 } s2; 3712 struct uv3h_rh_gam_gru_overlay_config_mmr_s { 3713 unsigned long rsvd_0_27:28; 3714 unsigned long base:18; /* RW */ 3715 unsigned long rsvd_46_51:6; 3716 unsigned long n_gru:4; /* RW */ 3717 unsigned long rsvd_56_61:6; 3718 unsigned long mode:1; /* RW */ 3719 unsigned long enable:1; /* RW */ 3720 } s3; 3721 struct uv4h_rh_gam_gru_overlay_config_mmr_s { 3722 unsigned long rsvd_0_24:25; 3723 unsigned long undef_25:1; /* Undefined */ 3724 unsigned long base:20; /* RW */ 3725 unsigned long rsvd_46_51:6; 3726 unsigned long n_gru:4; /* RW */ 3727 unsigned long rsvd_56_62:7; 3728 unsigned long enable:1; /* RW */ 3729 } s4; 3730 }; 3731 3732 /* ========================================================================= */ 3733 /* UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR */ 3734 /* ========================================================================= */ 3735 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR uv_undefined("UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR") 3736 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR uv_undefined("UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR") 3737 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR 0x1603000UL 3738 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR 0x483000UL 3739 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR ( \ 3740 is_uv1_hub() ? UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR : \ 3741 is_uv2_hub() ? UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR : \ 3742 is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR : \ 3743 /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR) 3744 3745 3746 3747 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT 26 3748 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT 46 3749 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_SHFT 63 3750 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK 0x00003ffffc000000UL 3751 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK 0x000fc00000000000UL 3752 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK 0x8000000000000000UL 3753 3754 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT 26 3755 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT 46 3756 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_SHFT 63 3757 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK 0x00003ffffc000000UL 3758 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK 0x000fc00000000000UL 3759 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK 0x8000000000000000UL 3760 3761 3762 union uvh_rh_gam_mmioh_overlay_config0_mmr_u { 3763 unsigned long v; 3764 struct uv3h_rh_gam_mmioh_overlay_config0_mmr_s { 3765 unsigned long rsvd_0_25:26; 3766 unsigned long base:20; /* RW */ 3767 unsigned long m_io:6; /* RW */ 3768 unsigned long n_io:4; 3769 unsigned long rsvd_56_62:7; 3770 unsigned long enable:1; /* RW */ 3771 } s3; 3772 struct uv4h_rh_gam_mmioh_overlay_config0_mmr_s { 3773 unsigned long rsvd_0_25:26; 3774 unsigned long base:20; /* RW */ 3775 unsigned long m_io:6; /* RW */ 3776 unsigned long n_io:4; 3777 unsigned long rsvd_56_62:7; 3778 unsigned long enable:1; /* RW */ 3779 } s4; 3780 }; 3781 3782 /* ========================================================================= */ 3783 /* UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR */ 3784 /* ========================================================================= */ 3785 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR uv_undefined("UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR") 3786 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR uv_undefined("UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR") 3787 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR 0x1604000UL 3788 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR 0x484000UL 3789 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR ( \ 3790 is_uv1_hub() ? UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR : \ 3791 is_uv2_hub() ? UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR : \ 3792 is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR : \ 3793 /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR) 3794 3795 3796 3797 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_SHFT 26 3798 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT 46 3799 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_SHFT 63 3800 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK 0x00003ffffc000000UL 3801 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK 0x000fc00000000000UL 3802 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_MASK 0x8000000000000000UL 3803 3804 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_SHFT 26 3805 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT 46 3806 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_SHFT 63 3807 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK 0x00003ffffc000000UL 3808 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK 0x000fc00000000000UL 3809 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_MASK 0x8000000000000000UL 3810 3811 3812 union uvh_rh_gam_mmioh_overlay_config1_mmr_u { 3813 unsigned long v; 3814 struct uv3h_rh_gam_mmioh_overlay_config1_mmr_s { 3815 unsigned long rsvd_0_25:26; 3816 unsigned long base:20; /* RW */ 3817 unsigned long m_io:6; /* RW */ 3818 unsigned long n_io:4; 3819 unsigned long rsvd_56_62:7; 3820 unsigned long enable:1; /* RW */ 3821 } s3; 3822 struct uv4h_rh_gam_mmioh_overlay_config1_mmr_s { 3823 unsigned long rsvd_0_25:26; 3824 unsigned long base:20; /* RW */ 3825 unsigned long m_io:6; /* RW */ 3826 unsigned long n_io:4; 3827 unsigned long rsvd_56_62:7; 3828 unsigned long enable:1; /* RW */ 3829 } s4; 3830 }; 3831 3832 /* ========================================================================= */ 3833 /* UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR */ 3834 /* ========================================================================= */ 3835 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL 3836 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL 3837 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR uv_undefined("UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR") 3838 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR uv_undefined("UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR") 3839 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR ( \ 3840 is_uv1_hub() ? UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR : \ 3841 is_uv2_hub() ? UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR : \ 3842 is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR : \ 3843 /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR) 3844 3845 3846 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30 3847 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46 3848 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52 3849 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3850 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003fffc0000000UL 3851 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL 3852 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL 3853 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3854 3855 3856 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 27 3857 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46 3858 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52 3859 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3860 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff8000000UL 3861 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL 3862 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL 3863 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3864 3865 3866 union uvh_rh_gam_mmioh_overlay_config_mmr_u { 3867 unsigned long v; 3868 struct uv1h_rh_gam_mmioh_overlay_config_mmr_s { 3869 unsigned long rsvd_0_29:30; 3870 unsigned long base:16; /* RW */ 3871 unsigned long m_io:6; /* RW */ 3872 unsigned long n_io:4; /* RW */ 3873 unsigned long rsvd_56_62:7; 3874 unsigned long enable:1; /* RW */ 3875 } s1; 3876 struct uv2h_rh_gam_mmioh_overlay_config_mmr_s { 3877 unsigned long rsvd_0_26:27; 3878 unsigned long base:19; /* RW */ 3879 unsigned long m_io:6; /* RW */ 3880 unsigned long n_io:4; /* RW */ 3881 unsigned long rsvd_56_62:7; 3882 unsigned long enable:1; /* RW */ 3883 } s2; 3884 }; 3885 3886 /* ========================================================================= */ 3887 /* UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR */ 3888 /* ========================================================================= */ 3889 #define UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR uv_undefined("UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR") 3890 #define UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR uv_undefined("UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR") 3891 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR 0x1603800UL 3892 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR 0x483800UL 3893 #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR ( \ 3894 is_uv1_hub() ? UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR : \ 3895 is_uv2_hub() ? UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR : \ 3896 is_uv3_hub() ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR : \ 3897 /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR) 3898 3899 #define UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH uv_undefined("UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH") 3900 #define UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH uv_undefined("UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH") 3901 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH 128 3902 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH 128 3903 #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH ( \ 3904 is_uv1_hub() ? UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH : \ 3905 is_uv2_hub() ? UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH : \ 3906 is_uv3_hub() ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH : \ 3907 /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH) 3908 3909 3910 3911 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_SHFT 0 3912 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK 0x0000000000007fffUL 3913 3914 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_SHFT 0 3915 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK 0x0000000000007fffUL 3916 3917 3918 union uvh_rh_gam_mmioh_redirect_config0_mmr_u { 3919 unsigned long v; 3920 struct uv3h_rh_gam_mmioh_redirect_config0_mmr_s { 3921 unsigned long nasid:15; /* RW */ 3922 unsigned long rsvd_15_63:49; 3923 } s3; 3924 struct uv4h_rh_gam_mmioh_redirect_config0_mmr_s { 3925 unsigned long nasid:15; /* RW */ 3926 unsigned long rsvd_15_63:49; 3927 } s4; 3928 }; 3929 3930 /* ========================================================================= */ 3931 /* UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR */ 3932 /* ========================================================================= */ 3933 #define UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR uv_undefined("UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR") 3934 #define UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR uv_undefined("UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR") 3935 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR 0x1604800UL 3936 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR 0x484800UL 3937 #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR ( \ 3938 is_uv1_hub() ? UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR : \ 3939 is_uv2_hub() ? UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR : \ 3940 is_uv3_hub() ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR : \ 3941 /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR) 3942 3943 #define UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH uv_undefined("UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH") 3944 #define UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH uv_undefined("UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH") 3945 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH 128 3946 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH 128 3947 #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH ( \ 3948 is_uv1_hub() ? UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH : \ 3949 is_uv2_hub() ? UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH : \ 3950 is_uv3_hub() ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH : \ 3951 /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH) 3952 3953 3954 3955 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_SHFT 0 3956 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK 0x0000000000007fffUL 3957 3958 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_SHFT 0 3959 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK 0x0000000000007fffUL 3960 3961 3962 union uvh_rh_gam_mmioh_redirect_config1_mmr_u { 3963 unsigned long v; 3964 struct uv3h_rh_gam_mmioh_redirect_config1_mmr_s { 3965 unsigned long nasid:15; /* RW */ 3966 unsigned long rsvd_15_63:49; 3967 } s3; 3968 struct uv4h_rh_gam_mmioh_redirect_config1_mmr_s { 3969 unsigned long nasid:15; /* RW */ 3970 unsigned long rsvd_15_63:49; 3971 } s4; 3972 }; 3973 3974 /* ========================================================================= */ 3975 /* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */ 3976 /* ========================================================================= */ 3977 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL 3978 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL 3979 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL 3980 #define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x480028UL 3981 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR ( \ 3982 is_uv1_hub() ? UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR : \ 3983 is_uv2_hub() ? UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR : \ 3984 is_uv3_hub() ? UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR : \ 3985 /*is_uv4_hub*/ UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR) 3986 3987 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 3988 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3989 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 3990 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3991 3992 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 3993 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46 3994 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3995 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 3996 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL 3997 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3998 3999 #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 4000 #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 4001 #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 4002 #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 4003 4004 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 4005 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 4006 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 4007 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 4008 4009 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 4010 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 4011 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 4012 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 4013 4014 #define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 4015 #define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 4016 #define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 4017 #define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 4018 4019 4020 union uvh_rh_gam_mmr_overlay_config_mmr_u { 4021 unsigned long v; 4022 struct uvh_rh_gam_mmr_overlay_config_mmr_s { 4023 unsigned long rsvd_0_25:26; 4024 unsigned long base:20; /* RW */ 4025 unsigned long rsvd_46_62:17; 4026 unsigned long enable:1; /* RW */ 4027 } s; 4028 struct uv1h_rh_gam_mmr_overlay_config_mmr_s { 4029 unsigned long rsvd_0_25:26; 4030 unsigned long base:20; /* RW */ 4031 unsigned long dual_hub:1; /* RW */ 4032 unsigned long rsvd_47_62:16; 4033 unsigned long enable:1; /* RW */ 4034 } s1; 4035 struct uvxh_rh_gam_mmr_overlay_config_mmr_s { 4036 unsigned long rsvd_0_25:26; 4037 unsigned long base:20; /* RW */ 4038 unsigned long rsvd_46_62:17; 4039 unsigned long enable:1; /* RW */ 4040 } sx; 4041 struct uv2h_rh_gam_mmr_overlay_config_mmr_s { 4042 unsigned long rsvd_0_25:26; 4043 unsigned long base:20; /* RW */ 4044 unsigned long rsvd_46_62:17; 4045 unsigned long enable:1; /* RW */ 4046 } s2; 4047 struct uv3h_rh_gam_mmr_overlay_config_mmr_s { 4048 unsigned long rsvd_0_25:26; 4049 unsigned long base:20; /* RW */ 4050 unsigned long rsvd_46_62:17; 4051 unsigned long enable:1; /* RW */ 4052 } s3; 4053 struct uv4h_rh_gam_mmr_overlay_config_mmr_s { 4054 unsigned long rsvd_0_25:26; 4055 unsigned long base:20; /* RW */ 4056 unsigned long rsvd_46_62:17; 4057 unsigned long enable:1; /* RW */ 4058 } s4; 4059 }; 4060 4061 /* ========================================================================= */ 4062 /* UVH_RTC */ 4063 /* ========================================================================= */ 4064 #define UV1H_RTC 0x340000UL 4065 #define UV2H_RTC 0x340000UL 4066 #define UV3H_RTC 0x340000UL 4067 #define UV4H_RTC 0xe0000UL 4068 #define UVH_RTC ( \ 4069 is_uv1_hub() ? UV1H_RTC : \ 4070 is_uv2_hub() ? UV2H_RTC : \ 4071 is_uv3_hub() ? UV3H_RTC : \ 4072 /*is_uv4_hub*/ UV4H_RTC) 4073 4074 #define UVH_RTC_REAL_TIME_CLOCK_SHFT 0 4075 #define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL 4076 4077 4078 union uvh_rtc_u { 4079 unsigned long v; 4080 struct uvh_rtc_s { 4081 unsigned long real_time_clock:56; /* RW */ 4082 unsigned long rsvd_56_63:8; 4083 } s; 4084 }; 4085 4086 /* ========================================================================= */ 4087 /* UVH_RTC1_INT_CONFIG */ 4088 /* ========================================================================= */ 4089 #define UVH_RTC1_INT_CONFIG 0x615c0UL 4090 4091 #define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0 4092 #define UVH_RTC1_INT_CONFIG_DM_SHFT 8 4093 #define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT 11 4094 #define UVH_RTC1_INT_CONFIG_STATUS_SHFT 12 4095 #define UVH_RTC1_INT_CONFIG_P_SHFT 13 4096 #define UVH_RTC1_INT_CONFIG_T_SHFT 15 4097 #define UVH_RTC1_INT_CONFIG_M_SHFT 16 4098 #define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT 32 4099 #define UVH_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL 4100 #define UVH_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL 4101 #define UVH_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL 4102 #define UVH_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL 4103 #define UVH_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL 4104 #define UVH_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL 4105 #define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL 4106 #define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 4107 4108 4109 union uvh_rtc1_int_config_u { 4110 unsigned long v; 4111 struct uvh_rtc1_int_config_s { 4112 unsigned long vector_:8; /* RW */ 4113 unsigned long dm:3; /* RW */ 4114 unsigned long destmode:1; /* RW */ 4115 unsigned long status:1; /* RO */ 4116 unsigned long p:1; /* RO */ 4117 unsigned long rsvd_14:1; 4118 unsigned long t:1; /* RO */ 4119 unsigned long m:1; /* RW */ 4120 unsigned long rsvd_17_31:15; 4121 unsigned long apic_id:32; /* RW */ 4122 } s; 4123 }; 4124 4125 /* ========================================================================= */ 4126 /* UVH_SCRATCH5 */ 4127 /* ========================================================================= */ 4128 #define UV1H_SCRATCH5 0x2d0200UL 4129 #define UV2H_SCRATCH5 0x2d0200UL 4130 #define UV3H_SCRATCH5 0x2d0200UL 4131 #define UV4H_SCRATCH5 0xb0200UL 4132 #define UVH_SCRATCH5 ( \ 4133 is_uv1_hub() ? UV1H_SCRATCH5 : \ 4134 is_uv2_hub() ? UV2H_SCRATCH5 : \ 4135 is_uv3_hub() ? UV3H_SCRATCH5 : \ 4136 /*is_uv4_hub*/ UV4H_SCRATCH5) 4137 4138 #define UV1H_SCRATCH5_32 0x778 4139 #define UV2H_SCRATCH5_32 0x778 4140 #define UV3H_SCRATCH5_32 0x778 4141 #define UV4H_SCRATCH5_32 0x798 4142 #define UVH_SCRATCH5_32 ( \ 4143 is_uv1_hub() ? UV1H_SCRATCH5_32 : \ 4144 is_uv2_hub() ? UV2H_SCRATCH5_32 : \ 4145 is_uv3_hub() ? UV3H_SCRATCH5_32 : \ 4146 /*is_uv4_hub*/ UV4H_SCRATCH5_32) 4147 4148 #define UVH_SCRATCH5_SCRATCH5_SHFT 0 4149 #define UVH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL 4150 4151 4152 union uvh_scratch5_u { 4153 unsigned long v; 4154 struct uvh_scratch5_s { 4155 unsigned long scratch5:64; /* RW, W1CS */ 4156 } s; 4157 }; 4158 4159 /* ========================================================================= */ 4160 /* UVH_SCRATCH5_ALIAS */ 4161 /* ========================================================================= */ 4162 #define UV1H_SCRATCH5_ALIAS 0x2d0208UL 4163 #define UV2H_SCRATCH5_ALIAS 0x2d0208UL 4164 #define UV3H_SCRATCH5_ALIAS 0x2d0208UL 4165 #define UV4H_SCRATCH5_ALIAS 0xb0208UL 4166 #define UVH_SCRATCH5_ALIAS ( \ 4167 is_uv1_hub() ? UV1H_SCRATCH5_ALIAS : \ 4168 is_uv2_hub() ? UV2H_SCRATCH5_ALIAS : \ 4169 is_uv3_hub() ? UV3H_SCRATCH5_ALIAS : \ 4170 /*is_uv4_hub*/ UV4H_SCRATCH5_ALIAS) 4171 4172 #define UV1H_SCRATCH5_ALIAS_32 0x780 4173 #define UV2H_SCRATCH5_ALIAS_32 0x780 4174 #define UV3H_SCRATCH5_ALIAS_32 0x780 4175 #define UV4H_SCRATCH5_ALIAS_32 0x7a0 4176 #define UVH_SCRATCH5_ALIAS_32 ( \ 4177 is_uv1_hub() ? UV1H_SCRATCH5_ALIAS_32 : \ 4178 is_uv2_hub() ? UV2H_SCRATCH5_ALIAS_32 : \ 4179 is_uv3_hub() ? UV3H_SCRATCH5_ALIAS_32 : \ 4180 /*is_uv4_hub*/ UV4H_SCRATCH5_ALIAS_32) 4181 4182 4183 /* ========================================================================= */ 4184 /* UVH_SCRATCH5_ALIAS_2 */ 4185 /* ========================================================================= */ 4186 #define UV1H_SCRATCH5_ALIAS_2 0x2d0210UL 4187 #define UV2H_SCRATCH5_ALIAS_2 0x2d0210UL 4188 #define UV3H_SCRATCH5_ALIAS_2 0x2d0210UL 4189 #define UV4H_SCRATCH5_ALIAS_2 0xb0210UL 4190 #define UVH_SCRATCH5_ALIAS_2 ( \ 4191 is_uv1_hub() ? UV1H_SCRATCH5_ALIAS_2 : \ 4192 is_uv2_hub() ? UV2H_SCRATCH5_ALIAS_2 : \ 4193 is_uv3_hub() ? UV3H_SCRATCH5_ALIAS_2 : \ 4194 /*is_uv4_hub*/ UV4H_SCRATCH5_ALIAS_2) 4195 #define UVH_SCRATCH5_ALIAS_2_32 0x788 4196 4197 4198 /* ========================================================================= */ 4199 /* UVXH_EVENT_OCCURRED2 */ 4200 /* ========================================================================= */ 4201 #define UVXH_EVENT_OCCURRED2 0x70100UL 4202 4203 #define UV2H_EVENT_OCCURRED2_32 0xb68 4204 #define UV3H_EVENT_OCCURRED2_32 0xb68 4205 #define UV4H_EVENT_OCCURRED2_32 0x608 4206 #define UVH_EVENT_OCCURRED2_32 ( \ 4207 is_uv2_hub() ? UV2H_EVENT_OCCURRED2_32 : \ 4208 is_uv3_hub() ? UV3H_EVENT_OCCURRED2_32 : \ 4209 /*is_uv4_hub*/ UV4H_EVENT_OCCURRED2_32) 4210 4211 4212 #define UV2H_EVENT_OCCURRED2_RTC_0_SHFT 0 4213 #define UV2H_EVENT_OCCURRED2_RTC_1_SHFT 1 4214 #define UV2H_EVENT_OCCURRED2_RTC_2_SHFT 2 4215 #define UV2H_EVENT_OCCURRED2_RTC_3_SHFT 3 4216 #define UV2H_EVENT_OCCURRED2_RTC_4_SHFT 4 4217 #define UV2H_EVENT_OCCURRED2_RTC_5_SHFT 5 4218 #define UV2H_EVENT_OCCURRED2_RTC_6_SHFT 6 4219 #define UV2H_EVENT_OCCURRED2_RTC_7_SHFT 7 4220 #define UV2H_EVENT_OCCURRED2_RTC_8_SHFT 8 4221 #define UV2H_EVENT_OCCURRED2_RTC_9_SHFT 9 4222 #define UV2H_EVENT_OCCURRED2_RTC_10_SHFT 10 4223 #define UV2H_EVENT_OCCURRED2_RTC_11_SHFT 11 4224 #define UV2H_EVENT_OCCURRED2_RTC_12_SHFT 12 4225 #define UV2H_EVENT_OCCURRED2_RTC_13_SHFT 13 4226 #define UV2H_EVENT_OCCURRED2_RTC_14_SHFT 14 4227 #define UV2H_EVENT_OCCURRED2_RTC_15_SHFT 15 4228 #define UV2H_EVENT_OCCURRED2_RTC_16_SHFT 16 4229 #define UV2H_EVENT_OCCURRED2_RTC_17_SHFT 17 4230 #define UV2H_EVENT_OCCURRED2_RTC_18_SHFT 18 4231 #define UV2H_EVENT_OCCURRED2_RTC_19_SHFT 19 4232 #define UV2H_EVENT_OCCURRED2_RTC_20_SHFT 20 4233 #define UV2H_EVENT_OCCURRED2_RTC_21_SHFT 21 4234 #define UV2H_EVENT_OCCURRED2_RTC_22_SHFT 22 4235 #define UV2H_EVENT_OCCURRED2_RTC_23_SHFT 23 4236 #define UV2H_EVENT_OCCURRED2_RTC_24_SHFT 24 4237 #define UV2H_EVENT_OCCURRED2_RTC_25_SHFT 25 4238 #define UV2H_EVENT_OCCURRED2_RTC_26_SHFT 26 4239 #define UV2H_EVENT_OCCURRED2_RTC_27_SHFT 27 4240 #define UV2H_EVENT_OCCURRED2_RTC_28_SHFT 28 4241 #define UV2H_EVENT_OCCURRED2_RTC_29_SHFT 29 4242 #define UV2H_EVENT_OCCURRED2_RTC_30_SHFT 30 4243 #define UV2H_EVENT_OCCURRED2_RTC_31_SHFT 31 4244 #define UV2H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL 4245 #define UV2H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL 4246 #define UV2H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL 4247 #define UV2H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL 4248 #define UV2H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL 4249 #define UV2H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL 4250 #define UV2H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL 4251 #define UV2H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL 4252 #define UV2H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL 4253 #define UV2H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL 4254 #define UV2H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL 4255 #define UV2H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL 4256 #define UV2H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL 4257 #define UV2H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL 4258 #define UV2H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL 4259 #define UV2H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL 4260 #define UV2H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL 4261 #define UV2H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL 4262 #define UV2H_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL 4263 #define UV2H_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL 4264 #define UV2H_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL 4265 #define UV2H_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL 4266 #define UV2H_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL 4267 #define UV2H_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL 4268 #define UV2H_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL 4269 #define UV2H_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL 4270 #define UV2H_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL 4271 #define UV2H_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL 4272 #define UV2H_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL 4273 #define UV2H_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL 4274 #define UV2H_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL 4275 #define UV2H_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL 4276 4277 #define UV3H_EVENT_OCCURRED2_RTC_0_SHFT 0 4278 #define UV3H_EVENT_OCCURRED2_RTC_1_SHFT 1 4279 #define UV3H_EVENT_OCCURRED2_RTC_2_SHFT 2 4280 #define UV3H_EVENT_OCCURRED2_RTC_3_SHFT 3 4281 #define UV3H_EVENT_OCCURRED2_RTC_4_SHFT 4 4282 #define UV3H_EVENT_OCCURRED2_RTC_5_SHFT 5 4283 #define UV3H_EVENT_OCCURRED2_RTC_6_SHFT 6 4284 #define UV3H_EVENT_OCCURRED2_RTC_7_SHFT 7 4285 #define UV3H_EVENT_OCCURRED2_RTC_8_SHFT 8 4286 #define UV3H_EVENT_OCCURRED2_RTC_9_SHFT 9 4287 #define UV3H_EVENT_OCCURRED2_RTC_10_SHFT 10 4288 #define UV3H_EVENT_OCCURRED2_RTC_11_SHFT 11 4289 #define UV3H_EVENT_OCCURRED2_RTC_12_SHFT 12 4290 #define UV3H_EVENT_OCCURRED2_RTC_13_SHFT 13 4291 #define UV3H_EVENT_OCCURRED2_RTC_14_SHFT 14 4292 #define UV3H_EVENT_OCCURRED2_RTC_15_SHFT 15 4293 #define UV3H_EVENT_OCCURRED2_RTC_16_SHFT 16 4294 #define UV3H_EVENT_OCCURRED2_RTC_17_SHFT 17 4295 #define UV3H_EVENT_OCCURRED2_RTC_18_SHFT 18 4296 #define UV3H_EVENT_OCCURRED2_RTC_19_SHFT 19 4297 #define UV3H_EVENT_OCCURRED2_RTC_20_SHFT 20 4298 #define UV3H_EVENT_OCCURRED2_RTC_21_SHFT 21 4299 #define UV3H_EVENT_OCCURRED2_RTC_22_SHFT 22 4300 #define UV3H_EVENT_OCCURRED2_RTC_23_SHFT 23 4301 #define UV3H_EVENT_OCCURRED2_RTC_24_SHFT 24 4302 #define UV3H_EVENT_OCCURRED2_RTC_25_SHFT 25 4303 #define UV3H_EVENT_OCCURRED2_RTC_26_SHFT 26 4304 #define UV3H_EVENT_OCCURRED2_RTC_27_SHFT 27 4305 #define UV3H_EVENT_OCCURRED2_RTC_28_SHFT 28 4306 #define UV3H_EVENT_OCCURRED2_RTC_29_SHFT 29 4307 #define UV3H_EVENT_OCCURRED2_RTC_30_SHFT 30 4308 #define UV3H_EVENT_OCCURRED2_RTC_31_SHFT 31 4309 #define UV3H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL 4310 #define UV3H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL 4311 #define UV3H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL 4312 #define UV3H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL 4313 #define UV3H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL 4314 #define UV3H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL 4315 #define UV3H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL 4316 #define UV3H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL 4317 #define UV3H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL 4318 #define UV3H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL 4319 #define UV3H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL 4320 #define UV3H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL 4321 #define UV3H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL 4322 #define UV3H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL 4323 #define UV3H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL 4324 #define UV3H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL 4325 #define UV3H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL 4326 #define UV3H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL 4327 #define UV3H_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL 4328 #define UV3H_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL 4329 #define UV3H_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL 4330 #define UV3H_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL 4331 #define UV3H_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL 4332 #define UV3H_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL 4333 #define UV3H_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL 4334 #define UV3H_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL 4335 #define UV3H_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL 4336 #define UV3H_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL 4337 #define UV3H_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL 4338 #define UV3H_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL 4339 #define UV3H_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL 4340 #define UV3H_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL 4341 4342 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT0_SHFT 0 4343 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT1_SHFT 1 4344 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT2_SHFT 2 4345 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT3_SHFT 3 4346 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT4_SHFT 4 4347 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT5_SHFT 5 4348 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT6_SHFT 6 4349 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT7_SHFT 7 4350 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT8_SHFT 8 4351 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT9_SHFT 9 4352 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT10_SHFT 10 4353 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT11_SHFT 11 4354 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT12_SHFT 12 4355 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT13_SHFT 13 4356 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT14_SHFT 14 4357 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT15_SHFT 15 4358 #define UV4H_EVENT_OCCURRED2_RTC_INTERVAL_INT_SHFT 16 4359 #define UV4H_EVENT_OCCURRED2_BAU_DASHBOARD_INT_SHFT 17 4360 #define UV4H_EVENT_OCCURRED2_RTC_0_SHFT 18 4361 #define UV4H_EVENT_OCCURRED2_RTC_1_SHFT 19 4362 #define UV4H_EVENT_OCCURRED2_RTC_2_SHFT 20 4363 #define UV4H_EVENT_OCCURRED2_RTC_3_SHFT 21 4364 #define UV4H_EVENT_OCCURRED2_RTC_4_SHFT 22 4365 #define UV4H_EVENT_OCCURRED2_RTC_5_SHFT 23 4366 #define UV4H_EVENT_OCCURRED2_RTC_6_SHFT 24 4367 #define UV4H_EVENT_OCCURRED2_RTC_7_SHFT 25 4368 #define UV4H_EVENT_OCCURRED2_RTC_8_SHFT 26 4369 #define UV4H_EVENT_OCCURRED2_RTC_9_SHFT 27 4370 #define UV4H_EVENT_OCCURRED2_RTC_10_SHFT 28 4371 #define UV4H_EVENT_OCCURRED2_RTC_11_SHFT 29 4372 #define UV4H_EVENT_OCCURRED2_RTC_12_SHFT 30 4373 #define UV4H_EVENT_OCCURRED2_RTC_13_SHFT 31 4374 #define UV4H_EVENT_OCCURRED2_RTC_14_SHFT 32 4375 #define UV4H_EVENT_OCCURRED2_RTC_15_SHFT 33 4376 #define UV4H_EVENT_OCCURRED2_RTC_16_SHFT 34 4377 #define UV4H_EVENT_OCCURRED2_RTC_17_SHFT 35 4378 #define UV4H_EVENT_OCCURRED2_RTC_18_SHFT 36 4379 #define UV4H_EVENT_OCCURRED2_RTC_19_SHFT 37 4380 #define UV4H_EVENT_OCCURRED2_RTC_20_SHFT 38 4381 #define UV4H_EVENT_OCCURRED2_RTC_21_SHFT 39 4382 #define UV4H_EVENT_OCCURRED2_RTC_22_SHFT 40 4383 #define UV4H_EVENT_OCCURRED2_RTC_23_SHFT 41 4384 #define UV4H_EVENT_OCCURRED2_RTC_24_SHFT 42 4385 #define UV4H_EVENT_OCCURRED2_RTC_25_SHFT 43 4386 #define UV4H_EVENT_OCCURRED2_RTC_26_SHFT 44 4387 #define UV4H_EVENT_OCCURRED2_RTC_27_SHFT 45 4388 #define UV4H_EVENT_OCCURRED2_RTC_28_SHFT 46 4389 #define UV4H_EVENT_OCCURRED2_RTC_29_SHFT 47 4390 #define UV4H_EVENT_OCCURRED2_RTC_30_SHFT 48 4391 #define UV4H_EVENT_OCCURRED2_RTC_31_SHFT 49 4392 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT0_MASK 0x0000000000000001UL 4393 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT1_MASK 0x0000000000000002UL 4394 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT2_MASK 0x0000000000000004UL 4395 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT3_MASK 0x0000000000000008UL 4396 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT4_MASK 0x0000000000000010UL 4397 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT5_MASK 0x0000000000000020UL 4398 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT6_MASK 0x0000000000000040UL 4399 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT7_MASK 0x0000000000000080UL 4400 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT8_MASK 0x0000000000000100UL 4401 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT9_MASK 0x0000000000000200UL 4402 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT10_MASK 0x0000000000000400UL 4403 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT11_MASK 0x0000000000000800UL 4404 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT12_MASK 0x0000000000001000UL 4405 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT13_MASK 0x0000000000002000UL 4406 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT14_MASK 0x0000000000004000UL 4407 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT15_MASK 0x0000000000008000UL 4408 #define UV4H_EVENT_OCCURRED2_RTC_INTERVAL_INT_MASK 0x0000000000010000UL 4409 #define UV4H_EVENT_OCCURRED2_BAU_DASHBOARD_INT_MASK 0x0000000000020000UL 4410 #define UV4H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000040000UL 4411 #define UV4H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000080000UL 4412 #define UV4H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000100000UL 4413 #define UV4H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000200000UL 4414 #define UV4H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000400000UL 4415 #define UV4H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000800000UL 4416 #define UV4H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000001000000UL 4417 #define UV4H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000002000000UL 4418 #define UV4H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000004000000UL 4419 #define UV4H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000008000000UL 4420 #define UV4H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000010000000UL 4421 #define UV4H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000020000000UL 4422 #define UV4H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000040000000UL 4423 #define UV4H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000080000000UL 4424 #define UV4H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000100000000UL 4425 #define UV4H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000200000000UL 4426 #define UV4H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000400000000UL 4427 #define UV4H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000800000000UL 4428 #define UV4H_EVENT_OCCURRED2_RTC_18_MASK 0x0000001000000000UL 4429 #define UV4H_EVENT_OCCURRED2_RTC_19_MASK 0x0000002000000000UL 4430 #define UV4H_EVENT_OCCURRED2_RTC_20_MASK 0x0000004000000000UL 4431 #define UV4H_EVENT_OCCURRED2_RTC_21_MASK 0x0000008000000000UL 4432 #define UV4H_EVENT_OCCURRED2_RTC_22_MASK 0x0000010000000000UL 4433 #define UV4H_EVENT_OCCURRED2_RTC_23_MASK 0x0000020000000000UL 4434 #define UV4H_EVENT_OCCURRED2_RTC_24_MASK 0x0000040000000000UL 4435 #define UV4H_EVENT_OCCURRED2_RTC_25_MASK 0x0000080000000000UL 4436 #define UV4H_EVENT_OCCURRED2_RTC_26_MASK 0x0000100000000000UL 4437 #define UV4H_EVENT_OCCURRED2_RTC_27_MASK 0x0000200000000000UL 4438 #define UV4H_EVENT_OCCURRED2_RTC_28_MASK 0x0000400000000000UL 4439 #define UV4H_EVENT_OCCURRED2_RTC_29_MASK 0x0000800000000000UL 4440 #define UV4H_EVENT_OCCURRED2_RTC_30_MASK 0x0001000000000000UL 4441 #define UV4H_EVENT_OCCURRED2_RTC_31_MASK 0x0002000000000000UL 4442 4443 #define UVXH_EVENT_OCCURRED2_RTC_1_MASK ( \ 4444 is_uv2_hub() ? UV2H_EVENT_OCCURRED2_RTC_1_MASK : \ 4445 is_uv3_hub() ? UV3H_EVENT_OCCURRED2_RTC_1_MASK : \ 4446 /*is_uv4_hub*/ UV4H_EVENT_OCCURRED2_RTC_1_MASK) 4447 4448 union uvh_event_occurred2_u { 4449 unsigned long v; 4450 struct uv2h_event_occurred2_s { 4451 unsigned long rtc_0:1; /* RW */ 4452 unsigned long rtc_1:1; /* RW */ 4453 unsigned long rtc_2:1; /* RW */ 4454 unsigned long rtc_3:1; /* RW */ 4455 unsigned long rtc_4:1; /* RW */ 4456 unsigned long rtc_5:1; /* RW */ 4457 unsigned long rtc_6:1; /* RW */ 4458 unsigned long rtc_7:1; /* RW */ 4459 unsigned long rtc_8:1; /* RW */ 4460 unsigned long rtc_9:1; /* RW */ 4461 unsigned long rtc_10:1; /* RW */ 4462 unsigned long rtc_11:1; /* RW */ 4463 unsigned long rtc_12:1; /* RW */ 4464 unsigned long rtc_13:1; /* RW */ 4465 unsigned long rtc_14:1; /* RW */ 4466 unsigned long rtc_15:1; /* RW */ 4467 unsigned long rtc_16:1; /* RW */ 4468 unsigned long rtc_17:1; /* RW */ 4469 unsigned long rtc_18:1; /* RW */ 4470 unsigned long rtc_19:1; /* RW */ 4471 unsigned long rtc_20:1; /* RW */ 4472 unsigned long rtc_21:1; /* RW */ 4473 unsigned long rtc_22:1; /* RW */ 4474 unsigned long rtc_23:1; /* RW */ 4475 unsigned long rtc_24:1; /* RW */ 4476 unsigned long rtc_25:1; /* RW */ 4477 unsigned long rtc_26:1; /* RW */ 4478 unsigned long rtc_27:1; /* RW */ 4479 unsigned long rtc_28:1; /* RW */ 4480 unsigned long rtc_29:1; /* RW */ 4481 unsigned long rtc_30:1; /* RW */ 4482 unsigned long rtc_31:1; /* RW */ 4483 unsigned long rsvd_32_63:32; 4484 } s2; 4485 struct uv3h_event_occurred2_s { 4486 unsigned long rtc_0:1; /* RW */ 4487 unsigned long rtc_1:1; /* RW */ 4488 unsigned long rtc_2:1; /* RW */ 4489 unsigned long rtc_3:1; /* RW */ 4490 unsigned long rtc_4:1; /* RW */ 4491 unsigned long rtc_5:1; /* RW */ 4492 unsigned long rtc_6:1; /* RW */ 4493 unsigned long rtc_7:1; /* RW */ 4494 unsigned long rtc_8:1; /* RW */ 4495 unsigned long rtc_9:1; /* RW */ 4496 unsigned long rtc_10:1; /* RW */ 4497 unsigned long rtc_11:1; /* RW */ 4498 unsigned long rtc_12:1; /* RW */ 4499 unsigned long rtc_13:1; /* RW */ 4500 unsigned long rtc_14:1; /* RW */ 4501 unsigned long rtc_15:1; /* RW */ 4502 unsigned long rtc_16:1; /* RW */ 4503 unsigned long rtc_17:1; /* RW */ 4504 unsigned long rtc_18:1; /* RW */ 4505 unsigned long rtc_19:1; /* RW */ 4506 unsigned long rtc_20:1; /* RW */ 4507 unsigned long rtc_21:1; /* RW */ 4508 unsigned long rtc_22:1; /* RW */ 4509 unsigned long rtc_23:1; /* RW */ 4510 unsigned long rtc_24:1; /* RW */ 4511 unsigned long rtc_25:1; /* RW */ 4512 unsigned long rtc_26:1; /* RW */ 4513 unsigned long rtc_27:1; /* RW */ 4514 unsigned long rtc_28:1; /* RW */ 4515 unsigned long rtc_29:1; /* RW */ 4516 unsigned long rtc_30:1; /* RW */ 4517 unsigned long rtc_31:1; /* RW */ 4518 unsigned long rsvd_32_63:32; 4519 } s3; 4520 struct uv4h_event_occurred2_s { 4521 unsigned long message_accelerator_int0:1; /* RW */ 4522 unsigned long message_accelerator_int1:1; /* RW */ 4523 unsigned long message_accelerator_int2:1; /* RW */ 4524 unsigned long message_accelerator_int3:1; /* RW */ 4525 unsigned long message_accelerator_int4:1; /* RW */ 4526 unsigned long message_accelerator_int5:1; /* RW */ 4527 unsigned long message_accelerator_int6:1; /* RW */ 4528 unsigned long message_accelerator_int7:1; /* RW */ 4529 unsigned long message_accelerator_int8:1; /* RW */ 4530 unsigned long message_accelerator_int9:1; /* RW */ 4531 unsigned long message_accelerator_int10:1; /* RW */ 4532 unsigned long message_accelerator_int11:1; /* RW */ 4533 unsigned long message_accelerator_int12:1; /* RW */ 4534 unsigned long message_accelerator_int13:1; /* RW */ 4535 unsigned long message_accelerator_int14:1; /* RW */ 4536 unsigned long message_accelerator_int15:1; /* RW */ 4537 unsigned long rtc_interval_int:1; /* RW */ 4538 unsigned long bau_dashboard_int:1; /* RW */ 4539 unsigned long rtc_0:1; /* RW */ 4540 unsigned long rtc_1:1; /* RW */ 4541 unsigned long rtc_2:1; /* RW */ 4542 unsigned long rtc_3:1; /* RW */ 4543 unsigned long rtc_4:1; /* RW */ 4544 unsigned long rtc_5:1; /* RW */ 4545 unsigned long rtc_6:1; /* RW */ 4546 unsigned long rtc_7:1; /* RW */ 4547 unsigned long rtc_8:1; /* RW */ 4548 unsigned long rtc_9:1; /* RW */ 4549 unsigned long rtc_10:1; /* RW */ 4550 unsigned long rtc_11:1; /* RW */ 4551 unsigned long rtc_12:1; /* RW */ 4552 unsigned long rtc_13:1; /* RW */ 4553 unsigned long rtc_14:1; /* RW */ 4554 unsigned long rtc_15:1; /* RW */ 4555 unsigned long rtc_16:1; /* RW */ 4556 unsigned long rtc_17:1; /* RW */ 4557 unsigned long rtc_18:1; /* RW */ 4558 unsigned long rtc_19:1; /* RW */ 4559 unsigned long rtc_20:1; /* RW */ 4560 unsigned long rtc_21:1; /* RW */ 4561 unsigned long rtc_22:1; /* RW */ 4562 unsigned long rtc_23:1; /* RW */ 4563 unsigned long rtc_24:1; /* RW */ 4564 unsigned long rtc_25:1; /* RW */ 4565 unsigned long rtc_26:1; /* RW */ 4566 unsigned long rtc_27:1; /* RW */ 4567 unsigned long rtc_28:1; /* RW */ 4568 unsigned long rtc_29:1; /* RW */ 4569 unsigned long rtc_30:1; /* RW */ 4570 unsigned long rtc_31:1; /* RW */ 4571 unsigned long rsvd_50_63:14; 4572 } s4; 4573 }; 4574 4575 /* ========================================================================= */ 4576 /* UVXH_EVENT_OCCURRED2_ALIAS */ 4577 /* ========================================================================= */ 4578 #define UVXH_EVENT_OCCURRED2_ALIAS 0x70108UL 4579 4580 #define UV2H_EVENT_OCCURRED2_ALIAS_32 0xb70 4581 #define UV3H_EVENT_OCCURRED2_ALIAS_32 0xb70 4582 #define UV4H_EVENT_OCCURRED2_ALIAS_32 0x610 4583 #define UVH_EVENT_OCCURRED2_ALIAS_32 ( \ 4584 is_uv2_hub() ? UV2H_EVENT_OCCURRED2_ALIAS_32 : \ 4585 is_uv3_hub() ? UV3H_EVENT_OCCURRED2_ALIAS_32 : \ 4586 /*is_uv4_hub*/ UV4H_EVENT_OCCURRED2_ALIAS_32) 4587 4588 4589 /* ========================================================================= */ 4590 /* UVXH_LB_BAU_SB_ACTIVATION_STATUS_2 */ 4591 /* ========================================================================= */ 4592 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL 4593 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL 4594 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2 0xc8130UL 4595 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_2 ( \ 4596 is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 : \ 4597 is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_2 : \ 4598 /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_2) 4599 4600 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0 4601 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0 4602 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0xa10 4603 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_2_32 ( \ 4604 is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 : \ 4605 is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_32 : \ 4606 /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_32) 4607 4608 #define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0 4609 #define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL 4610 4611 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0 4612 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL 4613 4614 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0 4615 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL 4616 4617 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0 4618 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL 4619 4620 4621 union uvxh_lb_bau_sb_activation_status_2_u { 4622 unsigned long v; 4623 struct uvxh_lb_bau_sb_activation_status_2_s { 4624 unsigned long aux_error:64; /* RW */ 4625 } sx; 4626 struct uv2h_lb_bau_sb_activation_status_2_s { 4627 unsigned long aux_error:64; /* RW */ 4628 } s2; 4629 struct uv3h_lb_bau_sb_activation_status_2_s { 4630 unsigned long aux_error:64; /* RW */ 4631 } s3; 4632 struct uv4h_lb_bau_sb_activation_status_2_s { 4633 unsigned long aux_error:64; /* RW */ 4634 } s4; 4635 }; 4636 4637 /* ========================================================================= */ 4638 /* UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK */ 4639 /* ========================================================================= */ 4640 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK 0x320130UL 4641 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_32 0x9f0 4642 4643 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_SHFT 0 4644 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_MASK 0x00000000ffffffffUL 4645 4646 union uv1h_lb_target_physical_apic_id_mask_u { 4647 unsigned long v; 4648 struct uv1h_lb_target_physical_apic_id_mask_s { 4649 unsigned long bit_enables:32; /* RW */ 4650 unsigned long rsvd_32_63:32; 4651 } s1; 4652 }; 4653 4654 /* ========================================================================= */ 4655 /* UV3H_GR0_GAM_GR_CONFIG */ 4656 /* ========================================================================= */ 4657 #define UV3H_GR0_GAM_GR_CONFIG 0xc00028UL 4658 4659 #define UV3H_GR0_GAM_GR_CONFIG_M_SKT_SHFT 0 4660 #define UV3H_GR0_GAM_GR_CONFIG_SUBSPACE_SHFT 10 4661 #define UV3H_GR0_GAM_GR_CONFIG_M_SKT_MASK 0x000000000000003fUL 4662 #define UV3H_GR0_GAM_GR_CONFIG_SUBSPACE_MASK 0x0000000000000400UL 4663 4664 union uv3h_gr0_gam_gr_config_u { 4665 unsigned long v; 4666 struct uv3h_gr0_gam_gr_config_s { 4667 unsigned long m_skt:6; /* RW */ 4668 unsigned long undef_6_9:4; /* Undefined */ 4669 unsigned long subspace:1; /* RW */ 4670 unsigned long reserved:53; 4671 } s3; 4672 }; 4673 4674 /* ========================================================================= */ 4675 /* UV4H_LB_PROC_INTD_QUEUE_FIRST */ 4676 /* ========================================================================= */ 4677 #define UV4H_LB_PROC_INTD_QUEUE_FIRST 0xa4100UL 4678 4679 #define UV4H_LB_PROC_INTD_QUEUE_FIRST_FIRST_PAYLOAD_ADDRESS_SHFT 6 4680 #define UV4H_LB_PROC_INTD_QUEUE_FIRST_FIRST_PAYLOAD_ADDRESS_MASK 0x00003fffffffffc0UL 4681 4682 union uv4h_lb_proc_intd_queue_first_u { 4683 unsigned long v; 4684 struct uv4h_lb_proc_intd_queue_first_s { 4685 unsigned long undef_0_5:6; /* Undefined */ 4686 unsigned long first_payload_address:40; /* RW */ 4687 } s4; 4688 }; 4689 4690 /* ========================================================================= */ 4691 /* UV4H_LB_PROC_INTD_QUEUE_LAST */ 4692 /* ========================================================================= */ 4693 #define UV4H_LB_PROC_INTD_QUEUE_LAST 0xa4108UL 4694 4695 #define UV4H_LB_PROC_INTD_QUEUE_LAST_LAST_PAYLOAD_ADDRESS_SHFT 5 4696 #define UV4H_LB_PROC_INTD_QUEUE_LAST_LAST_PAYLOAD_ADDRESS_MASK 0x00003fffffffffe0UL 4697 4698 union uv4h_lb_proc_intd_queue_last_u { 4699 unsigned long v; 4700 struct uv4h_lb_proc_intd_queue_last_s { 4701 unsigned long undef_0_4:5; /* Undefined */ 4702 unsigned long last_payload_address:41; /* RW */ 4703 } s4; 4704 }; 4705 4706 /* ========================================================================= */ 4707 /* UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR */ 4708 /* ========================================================================= */ 4709 #define UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR 0xa4118UL 4710 4711 #define UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR_SOFT_ACK_PENDING_FLAGS_SHFT 0 4712 #define UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR_SOFT_ACK_PENDING_FLAGS_MASK 0x00000000000000ffUL 4713 4714 union uv4h_lb_proc_intd_soft_ack_clear_u { 4715 unsigned long v; 4716 struct uv4h_lb_proc_intd_soft_ack_clear_s { 4717 unsigned long soft_ack_pending_flags:8; /* WP */ 4718 } s4; 4719 }; 4720 4721 /* ========================================================================= */ 4722 /* UV4H_LB_PROC_INTD_SOFT_ACK_PENDING */ 4723 /* ========================================================================= */ 4724 #define UV4H_LB_PROC_INTD_SOFT_ACK_PENDING 0xa4110UL 4725 4726 #define UV4H_LB_PROC_INTD_SOFT_ACK_PENDING_SOFT_ACK_FLAGS_SHFT 0 4727 #define UV4H_LB_PROC_INTD_SOFT_ACK_PENDING_SOFT_ACK_FLAGS_MASK 0x00000000000000ffUL 4728 4729 union uv4h_lb_proc_intd_soft_ack_pending_u { 4730 unsigned long v; 4731 struct uv4h_lb_proc_intd_soft_ack_pending_s { 4732 unsigned long soft_ack_flags:8; /* RW */ 4733 } s4; 4734 }; 4735 4736 4737 #endif /* _ASM_X86_UV_UV_MMRS_H */ 4738