1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * SGI UV MMR definitions 7 * 8 * Copyright (C) 2007-2013 Silicon Graphics, Inc. All rights reserved. 9 */ 10 11 #ifndef _ASM_X86_UV_UV_MMRS_H 12 #define _ASM_X86_UV_UV_MMRS_H 13 14 /* 15 * This file contains MMR definitions for all UV hubs types. 16 * 17 * To minimize coding differences between hub types, the symbols are 18 * grouped by architecture types. 19 * 20 * UVH - definitions common to all UV hub types. 21 * UVXH - definitions common to all UV eXtended hub types (currently 2 & 3). 22 * UV1H - definitions specific to UV type 1 hub. 23 * UV2H - definitions specific to UV type 2 hub. 24 * UV3H - definitions specific to UV type 3 hub. 25 * 26 * So in general, MMR addresses and structures are identical on all hubs types. 27 * These MMRs are identified as: 28 * #define UVH_xxx <address> 29 * union uvh_xxx { 30 * unsigned long v; 31 * struct uvh_int_cmpd_s { 32 * } s; 33 * }; 34 * 35 * If the MMR exists on all hub types but have different addresses: 36 * #define UV1Hxxx a 37 * #define UV2Hxxx b 38 * #define UV3Hxxx c 39 * #define UVHxxx (is_uv1_hub() ? UV1Hxxx : 40 * (is_uv2_hub() ? UV2Hxxx : 41 * UV3Hxxx)) 42 * 43 * If the MMR exists on all hub types > 1 but have different addresses: 44 * #define UV2Hxxx b 45 * #define UV3Hxxx c 46 * #define UVXHxxx (is_uv2_hub() ? UV2Hxxx : 47 * UV3Hxxx)) 48 * 49 * union uvh_xxx { 50 * unsigned long v; 51 * struct uvh_xxx_s { # Common fields only 52 * } s; 53 * struct uv1h_xxx_s { # Full UV1 definition (*) 54 * } s1; 55 * struct uv2h_xxx_s { # Full UV2 definition (*) 56 * } s2; 57 * struct uv3h_xxx_s { # Full UV3 definition (*) 58 * } s3; 59 * }; 60 * (* - if present and different than the common struct) 61 * 62 * Only essential differences are enumerated. For example, if the address is 63 * the same for all UV's, only a single #define is generated. Likewise, 64 * if the contents is the same for all hubs, only the "s" structure is 65 * generated. 66 * 67 * If the MMR exists on ONLY 1 type of hub, no generic definition is 68 * generated: 69 * #define UVnH_xxx <uvn address> 70 * union uvnh_xxx { 71 * unsigned long v; 72 * struct uvh_int_cmpd_s { 73 * } sn; 74 * }; 75 * 76 * (GEN Flags: mflags_opt= undefs=0 UV23=UVXH) 77 */ 78 79 #define UV_MMR_ENABLE (1UL << 63) 80 81 #define UV1_HUB_PART_NUMBER 0x88a5 82 #define UV2_HUB_PART_NUMBER 0x8eb8 83 #define UV2_HUB_PART_NUMBER_X 0x1111 84 #define UV3_HUB_PART_NUMBER 0x9578 85 #define UV3_HUB_PART_NUMBER_X 0x4321 86 87 /* Compat: Indicate which UV Hubs are supported. */ 88 #define UV2_HUB_IS_SUPPORTED 1 89 #define UV3_HUB_IS_SUPPORTED 1 90 91 /* ========================================================================= */ 92 /* UVH_BAU_DATA_BROADCAST */ 93 /* ========================================================================= */ 94 #define UVH_BAU_DATA_BROADCAST 0x61688UL 95 #define UVH_BAU_DATA_BROADCAST_32 0x440 96 97 #define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT 0 98 #define UVH_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL 99 100 union uvh_bau_data_broadcast_u { 101 unsigned long v; 102 struct uvh_bau_data_broadcast_s { 103 unsigned long enable:1; /* RW */ 104 unsigned long rsvd_1_63:63; 105 } s; 106 }; 107 108 /* ========================================================================= */ 109 /* UVH_BAU_DATA_CONFIG */ 110 /* ========================================================================= */ 111 #define UVH_BAU_DATA_CONFIG 0x61680UL 112 #define UVH_BAU_DATA_CONFIG_32 0x438 113 114 #define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0 115 #define UVH_BAU_DATA_CONFIG_DM_SHFT 8 116 #define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT 11 117 #define UVH_BAU_DATA_CONFIG_STATUS_SHFT 12 118 #define UVH_BAU_DATA_CONFIG_P_SHFT 13 119 #define UVH_BAU_DATA_CONFIG_T_SHFT 15 120 #define UVH_BAU_DATA_CONFIG_M_SHFT 16 121 #define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT 32 122 #define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL 123 #define UVH_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL 124 #define UVH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL 125 #define UVH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL 126 #define UVH_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL 127 #define UVH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL 128 #define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL 129 #define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 130 131 union uvh_bau_data_config_u { 132 unsigned long v; 133 struct uvh_bau_data_config_s { 134 unsigned long vector_:8; /* RW */ 135 unsigned long dm:3; /* RW */ 136 unsigned long destmode:1; /* RW */ 137 unsigned long status:1; /* RO */ 138 unsigned long p:1; /* RO */ 139 unsigned long rsvd_14:1; 140 unsigned long t:1; /* RO */ 141 unsigned long m:1; /* RW */ 142 unsigned long rsvd_17_31:15; 143 unsigned long apic_id:32; /* RW */ 144 } s; 145 }; 146 147 /* ========================================================================= */ 148 /* UVH_EVENT_OCCURRED0 */ 149 /* ========================================================================= */ 150 #define UVH_EVENT_OCCURRED0 0x70000UL 151 #define UVH_EVENT_OCCURRED0_32 0x5e8 152 153 #define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT 0 154 #define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT 11 155 #define UVH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL 156 #define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL 157 158 #define UV1H_EVENT_OCCURRED0_GR0_HCERR_SHFT 1 159 #define UV1H_EVENT_OCCURRED0_GR1_HCERR_SHFT 2 160 #define UV1H_EVENT_OCCURRED0_LH_HCERR_SHFT 3 161 #define UV1H_EVENT_OCCURRED0_RH_HCERR_SHFT 4 162 #define UV1H_EVENT_OCCURRED0_XN_HCERR_SHFT 5 163 #define UV1H_EVENT_OCCURRED0_SI_HCERR_SHFT 6 164 #define UV1H_EVENT_OCCURRED0_LB_AOERR0_SHFT 7 165 #define UV1H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8 166 #define UV1H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9 167 #define UV1H_EVENT_OCCURRED0_LH_AOERR0_SHFT 10 168 #define UV1H_EVENT_OCCURRED0_XN_AOERR0_SHFT 12 169 #define UV1H_EVENT_OCCURRED0_SI_AOERR0_SHFT 13 170 #define UV1H_EVENT_OCCURRED0_LB_AOERR1_SHFT 14 171 #define UV1H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15 172 #define UV1H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16 173 #define UV1H_EVENT_OCCURRED0_LH_AOERR1_SHFT 17 174 #define UV1H_EVENT_OCCURRED0_RH_AOERR1_SHFT 18 175 #define UV1H_EVENT_OCCURRED0_XN_AOERR1_SHFT 19 176 #define UV1H_EVENT_OCCURRED0_SI_AOERR1_SHFT 20 177 #define UV1H_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21 178 #define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22 179 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23 180 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24 181 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25 182 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26 183 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27 184 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28 185 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29 186 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30 187 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31 188 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32 189 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33 190 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34 191 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35 192 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36 193 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37 194 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38 195 #define UV1H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39 196 #define UV1H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40 197 #define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41 198 #define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42 199 #define UV1H_EVENT_OCCURRED0_LTC_INT_SHFT 43 200 #define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44 201 #define UV1H_EVENT_OCCURRED0_IPI_INT_SHFT 45 202 #define UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46 203 #define UV1H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47 204 #define UV1H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48 205 #define UV1H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49 206 #define UV1H_EVENT_OCCURRED0_PROFILE_INT_SHFT 50 207 #define UV1H_EVENT_OCCURRED0_RTC0_SHFT 51 208 #define UV1H_EVENT_OCCURRED0_RTC1_SHFT 52 209 #define UV1H_EVENT_OCCURRED0_RTC2_SHFT 53 210 #define UV1H_EVENT_OCCURRED0_RTC3_SHFT 54 211 #define UV1H_EVENT_OCCURRED0_BAU_DATA_SHFT 55 212 #define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56 213 #define UV1H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL 214 #define UV1H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL 215 #define UV1H_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL 216 #define UV1H_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL 217 #define UV1H_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL 218 #define UV1H_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL 219 #define UV1H_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL 220 #define UV1H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL 221 #define UV1H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL 222 #define UV1H_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL 223 #define UV1H_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL 224 #define UV1H_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL 225 #define UV1H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL 226 #define UV1H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL 227 #define UV1H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL 228 #define UV1H_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL 229 #define UV1H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL 230 #define UV1H_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL 231 #define UV1H_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL 232 #define UV1H_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL 233 #define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL 234 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL 235 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL 236 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL 237 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL 238 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL 239 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL 240 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL 241 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL 242 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL 243 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL 244 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL 245 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL 246 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL 247 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL 248 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL 249 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL 250 #define UV1H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL 251 #define UV1H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL 252 #define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL 253 #define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL 254 #define UV1H_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL 255 #define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL 256 #define UV1H_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL 257 #define UV1H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL 258 #define UV1H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL 259 #define UV1H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL 260 #define UV1H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL 261 #define UV1H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL 262 #define UV1H_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL 263 #define UV1H_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL 264 #define UV1H_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL 265 #define UV1H_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL 266 #define UV1H_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL 267 #define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL 268 269 #define UVXH_EVENT_OCCURRED0_QP_HCERR_SHFT 1 270 #define UVXH_EVENT_OCCURRED0_RH_HCERR_SHFT 2 271 #define UVXH_EVENT_OCCURRED0_LH0_HCERR_SHFT 3 272 #define UVXH_EVENT_OCCURRED0_LH1_HCERR_SHFT 4 273 #define UVXH_EVENT_OCCURRED0_GR0_HCERR_SHFT 5 274 #define UVXH_EVENT_OCCURRED0_GR1_HCERR_SHFT 6 275 #define UVXH_EVENT_OCCURRED0_NI0_HCERR_SHFT 7 276 #define UVXH_EVENT_OCCURRED0_NI1_HCERR_SHFT 8 277 #define UVXH_EVENT_OCCURRED0_LB_AOERR0_SHFT 9 278 #define UVXH_EVENT_OCCURRED0_QP_AOERR0_SHFT 10 279 #define UVXH_EVENT_OCCURRED0_LH0_AOERR0_SHFT 12 280 #define UVXH_EVENT_OCCURRED0_LH1_AOERR0_SHFT 13 281 #define UVXH_EVENT_OCCURRED0_GR0_AOERR0_SHFT 14 282 #define UVXH_EVENT_OCCURRED0_GR1_AOERR0_SHFT 15 283 #define UVXH_EVENT_OCCURRED0_XB_AOERR0_SHFT 16 284 #define UVXH_EVENT_OCCURRED0_RT_AOERR0_SHFT 17 285 #define UVXH_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18 286 #define UVXH_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19 287 #define UVXH_EVENT_OCCURRED0_LB_AOERR1_SHFT 20 288 #define UVXH_EVENT_OCCURRED0_QP_AOERR1_SHFT 21 289 #define UVXH_EVENT_OCCURRED0_RH_AOERR1_SHFT 22 290 #define UVXH_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23 291 #define UVXH_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24 292 #define UVXH_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25 293 #define UVXH_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26 294 #define UVXH_EVENT_OCCURRED0_XB_AOERR1_SHFT 27 295 #define UVXH_EVENT_OCCURRED0_RT_AOERR1_SHFT 28 296 #define UVXH_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29 297 #define UVXH_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30 298 #define UVXH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31 299 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32 300 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33 301 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34 302 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35 303 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36 304 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37 305 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38 306 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39 307 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40 308 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41 309 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42 310 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43 311 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44 312 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45 313 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46 314 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47 315 #define UVXH_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48 316 #define UVXH_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49 317 #define UVXH_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50 318 #define UVXH_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51 319 #define UVXH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52 320 #define UVXH_EVENT_OCCURRED0_IPI_INT_SHFT 53 321 #define UVXH_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54 322 #define UVXH_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55 323 #define UVXH_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56 324 #define UVXH_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57 325 #define UVXH_EVENT_OCCURRED0_PROFILE_INT_SHFT 58 326 #define UVXH_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL 327 #define UVXH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000004UL 328 #define UVXH_EVENT_OCCURRED0_LH0_HCERR_MASK 0x0000000000000008UL 329 #define UVXH_EVENT_OCCURRED0_LH1_HCERR_MASK 0x0000000000000010UL 330 #define UVXH_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000020UL 331 #define UVXH_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000040UL 332 #define UVXH_EVENT_OCCURRED0_NI0_HCERR_MASK 0x0000000000000080UL 333 #define UVXH_EVENT_OCCURRED0_NI1_HCERR_MASK 0x0000000000000100UL 334 #define UVXH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000200UL 335 #define UVXH_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL 336 #define UVXH_EVENT_OCCURRED0_LH0_AOERR0_MASK 0x0000000000001000UL 337 #define UVXH_EVENT_OCCURRED0_LH1_AOERR0_MASK 0x0000000000002000UL 338 #define UVXH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000004000UL 339 #define UVXH_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000008000UL 340 #define UVXH_EVENT_OCCURRED0_XB_AOERR0_MASK 0x0000000000010000UL 341 #define UVXH_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL 342 #define UVXH_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL 343 #define UVXH_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL 344 #define UVXH_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL 345 #define UVXH_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL 346 #define UVXH_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL 347 #define UVXH_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL 348 #define UVXH_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL 349 #define UVXH_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL 350 #define UVXH_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL 351 #define UVXH_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL 352 #define UVXH_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL 353 #define UVXH_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL 354 #define UVXH_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL 355 #define UVXH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL 356 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL 357 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL 358 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL 359 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL 360 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL 361 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL 362 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL 363 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL 364 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL 365 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL 366 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL 367 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL 368 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL 369 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL 370 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL 371 #define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL 372 #define UVXH_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL 373 #define UVXH_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL 374 #define UVXH_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL 375 #define UVXH_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL 376 #define UVXH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL 377 #define UVXH_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL 378 #define UVXH_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL 379 #define UVXH_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL 380 #define UVXH_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL 381 #define UVXH_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL 382 #define UVXH_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL 383 384 union uvh_event_occurred0_u { 385 unsigned long v; 386 struct uvh_event_occurred0_s { 387 unsigned long lb_hcerr:1; /* RW, W1C */ 388 unsigned long rsvd_1_10:10; 389 unsigned long rh_aoerr0:1; /* RW, W1C */ 390 unsigned long rsvd_12_63:52; 391 } s; 392 struct uvxh_event_occurred0_s { 393 unsigned long lb_hcerr:1; /* RW */ 394 unsigned long qp_hcerr:1; /* RW */ 395 unsigned long rh_hcerr:1; /* RW */ 396 unsigned long lh0_hcerr:1; /* RW */ 397 unsigned long lh1_hcerr:1; /* RW */ 398 unsigned long gr0_hcerr:1; /* RW */ 399 unsigned long gr1_hcerr:1; /* RW */ 400 unsigned long ni0_hcerr:1; /* RW */ 401 unsigned long ni1_hcerr:1; /* RW */ 402 unsigned long lb_aoerr0:1; /* RW */ 403 unsigned long qp_aoerr0:1; /* RW */ 404 unsigned long rh_aoerr0:1; /* RW */ 405 unsigned long lh0_aoerr0:1; /* RW */ 406 unsigned long lh1_aoerr0:1; /* RW */ 407 unsigned long gr0_aoerr0:1; /* RW */ 408 unsigned long gr1_aoerr0:1; /* RW */ 409 unsigned long xb_aoerr0:1; /* RW */ 410 unsigned long rt_aoerr0:1; /* RW */ 411 unsigned long ni0_aoerr0:1; /* RW */ 412 unsigned long ni1_aoerr0:1; /* RW */ 413 unsigned long lb_aoerr1:1; /* RW */ 414 unsigned long qp_aoerr1:1; /* RW */ 415 unsigned long rh_aoerr1:1; /* RW */ 416 unsigned long lh0_aoerr1:1; /* RW */ 417 unsigned long lh1_aoerr1:1; /* RW */ 418 unsigned long gr0_aoerr1:1; /* RW */ 419 unsigned long gr1_aoerr1:1; /* RW */ 420 unsigned long xb_aoerr1:1; /* RW */ 421 unsigned long rt_aoerr1:1; /* RW */ 422 unsigned long ni0_aoerr1:1; /* RW */ 423 unsigned long ni1_aoerr1:1; /* RW */ 424 unsigned long system_shutdown_int:1; /* RW */ 425 unsigned long lb_irq_int_0:1; /* RW */ 426 unsigned long lb_irq_int_1:1; /* RW */ 427 unsigned long lb_irq_int_2:1; /* RW */ 428 unsigned long lb_irq_int_3:1; /* RW */ 429 unsigned long lb_irq_int_4:1; /* RW */ 430 unsigned long lb_irq_int_5:1; /* RW */ 431 unsigned long lb_irq_int_6:1; /* RW */ 432 unsigned long lb_irq_int_7:1; /* RW */ 433 unsigned long lb_irq_int_8:1; /* RW */ 434 unsigned long lb_irq_int_9:1; /* RW */ 435 unsigned long lb_irq_int_10:1; /* RW */ 436 unsigned long lb_irq_int_11:1; /* RW */ 437 unsigned long lb_irq_int_12:1; /* RW */ 438 unsigned long lb_irq_int_13:1; /* RW */ 439 unsigned long lb_irq_int_14:1; /* RW */ 440 unsigned long lb_irq_int_15:1; /* RW */ 441 unsigned long l1_nmi_int:1; /* RW */ 442 unsigned long stop_clock:1; /* RW */ 443 unsigned long asic_to_l1:1; /* RW */ 444 unsigned long l1_to_asic:1; /* RW */ 445 unsigned long la_seq_trigger:1; /* RW */ 446 unsigned long ipi_int:1; /* RW */ 447 unsigned long extio_int0:1; /* RW */ 448 unsigned long extio_int1:1; /* RW */ 449 unsigned long extio_int2:1; /* RW */ 450 unsigned long extio_int3:1; /* RW */ 451 unsigned long profile_int:1; /* RW */ 452 unsigned long rsvd_59_63:5; 453 } sx; 454 }; 455 456 /* ========================================================================= */ 457 /* UVH_EVENT_OCCURRED0_ALIAS */ 458 /* ========================================================================= */ 459 #define UVH_EVENT_OCCURRED0_ALIAS 0x70008UL 460 #define UVH_EVENT_OCCURRED0_ALIAS_32 0x5f0 461 462 463 /* ========================================================================= */ 464 /* UVH_EXTIO_INT0_BROADCAST */ 465 /* ========================================================================= */ 466 #define UVH_EXTIO_INT0_BROADCAST 0x61448UL 467 #define UVH_EXTIO_INT0_BROADCAST_32 0x3f0 468 469 #define UVH_EXTIO_INT0_BROADCAST_ENABLE_SHFT 0 470 #define UVH_EXTIO_INT0_BROADCAST_ENABLE_MASK 0x0000000000000001UL 471 472 union uvh_extio_int0_broadcast_u { 473 unsigned long v; 474 struct uvh_extio_int0_broadcast_s { 475 unsigned long enable:1; /* RW */ 476 unsigned long rsvd_1_63:63; 477 } s; 478 }; 479 480 /* ========================================================================= */ 481 /* UVH_GR0_TLB_INT0_CONFIG */ 482 /* ========================================================================= */ 483 #define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL 484 485 #define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0 486 #define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT 8 487 #define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11 488 #define UVH_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12 489 #define UVH_GR0_TLB_INT0_CONFIG_P_SHFT 13 490 #define UVH_GR0_TLB_INT0_CONFIG_T_SHFT 15 491 #define UVH_GR0_TLB_INT0_CONFIG_M_SHFT 16 492 #define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32 493 #define UVH_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL 494 #define UVH_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL 495 #define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL 496 #define UVH_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL 497 #define UVH_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL 498 #define UVH_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL 499 #define UVH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL 500 #define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 501 502 union uvh_gr0_tlb_int0_config_u { 503 unsigned long v; 504 struct uvh_gr0_tlb_int0_config_s { 505 unsigned long vector_:8; /* RW */ 506 unsigned long dm:3; /* RW */ 507 unsigned long destmode:1; /* RW */ 508 unsigned long status:1; /* RO */ 509 unsigned long p:1; /* RO */ 510 unsigned long rsvd_14:1; 511 unsigned long t:1; /* RO */ 512 unsigned long m:1; /* RW */ 513 unsigned long rsvd_17_31:15; 514 unsigned long apic_id:32; /* RW */ 515 } s; 516 }; 517 518 /* ========================================================================= */ 519 /* UVH_GR0_TLB_INT1_CONFIG */ 520 /* ========================================================================= */ 521 #define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL 522 523 #define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0 524 #define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT 8 525 #define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT 11 526 #define UVH_GR0_TLB_INT1_CONFIG_STATUS_SHFT 12 527 #define UVH_GR0_TLB_INT1_CONFIG_P_SHFT 13 528 #define UVH_GR0_TLB_INT1_CONFIG_T_SHFT 15 529 #define UVH_GR0_TLB_INT1_CONFIG_M_SHFT 16 530 #define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT 32 531 #define UVH_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL 532 #define UVH_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL 533 #define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL 534 #define UVH_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL 535 #define UVH_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL 536 #define UVH_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL 537 #define UVH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL 538 #define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 539 540 union uvh_gr0_tlb_int1_config_u { 541 unsigned long v; 542 struct uvh_gr0_tlb_int1_config_s { 543 unsigned long vector_:8; /* RW */ 544 unsigned long dm:3; /* RW */ 545 unsigned long destmode:1; /* RW */ 546 unsigned long status:1; /* RO */ 547 unsigned long p:1; /* RO */ 548 unsigned long rsvd_14:1; 549 unsigned long t:1; /* RO */ 550 unsigned long m:1; /* RW */ 551 unsigned long rsvd_17_31:15; 552 unsigned long apic_id:32; /* RW */ 553 } s; 554 }; 555 556 /* ========================================================================= */ 557 /* UVH_GR0_TLB_MMR_CONTROL */ 558 /* ========================================================================= */ 559 #define UV1H_GR0_TLB_MMR_CONTROL 0x401080UL 560 #define UV2H_GR0_TLB_MMR_CONTROL 0xc01080UL 561 #define UV3H_GR0_TLB_MMR_CONTROL 0xc01080UL 562 #define UVH_GR0_TLB_MMR_CONTROL \ 563 (is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL : \ 564 (is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL : \ 565 UV3H_GR0_TLB_MMR_CONTROL)) 566 567 #define UVH_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 568 #define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 569 #define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 570 #define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 571 #define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 572 #define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31 573 #define UVH_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL 574 #define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL 575 #define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 576 #define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 577 #define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 578 #define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 579 580 #define UV1H_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 581 #define UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 582 #define UV1H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 583 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 584 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 585 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31 586 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT 48 587 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT 52 588 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_SHFT 54 589 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_SHFT 56 590 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_SHFT 60 591 #define UV1H_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL 592 #define UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL 593 #define UV1H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 594 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 595 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 596 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 597 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL 598 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL 599 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_MASK 0x0040000000000000UL 600 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK 0x0100000000000000UL 601 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK 0x1000000000000000UL 602 603 #define UVXH_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 604 #define UVXH_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 605 #define UVXH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 606 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 607 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 608 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31 609 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 610 #define UVXH_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL 611 #define UVXH_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL 612 #define UVXH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 613 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 614 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 615 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 616 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 617 618 #define UV2H_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 619 #define UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 620 #define UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 621 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 622 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 623 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31 624 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 625 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT 48 626 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT 52 627 #define UV2H_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL 628 #define UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL 629 #define UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 630 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 631 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 632 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 633 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 634 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL 635 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL 636 637 #define UV3H_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 638 #define UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 639 #define UV3H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 640 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 641 #define UV3H_GR0_TLB_MMR_CONTROL_ECC_SEL_SHFT 21 642 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 643 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31 644 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 645 #define UV3H_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL 646 #define UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL 647 #define UV3H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 648 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 649 #define UV3H_GR0_TLB_MMR_CONTROL_ECC_SEL_MASK 0x0000000000200000UL 650 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 651 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 652 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 653 654 union uvh_gr0_tlb_mmr_control_u { 655 unsigned long v; 656 struct uvh_gr0_tlb_mmr_control_s { 657 unsigned long index:12; /* RW */ 658 unsigned long mem_sel:2; /* RW */ 659 unsigned long rsvd_14_15:2; 660 unsigned long auto_valid_en:1; /* RW */ 661 unsigned long rsvd_17_19:3; 662 unsigned long mmr_hash_index_en:1; /* RW */ 663 unsigned long rsvd_21_29:9; 664 unsigned long mmr_write:1; /* WP */ 665 unsigned long mmr_read:1; /* WP */ 666 unsigned long rsvd_32_48:17; 667 unsigned long rsvd_49_51:3; 668 unsigned long rsvd_52_63:12; 669 } s; 670 struct uv1h_gr0_tlb_mmr_control_s { 671 unsigned long index:12; /* RW */ 672 unsigned long mem_sel:2; /* RW */ 673 unsigned long rsvd_14_15:2; 674 unsigned long auto_valid_en:1; /* RW */ 675 unsigned long rsvd_17_19:3; 676 unsigned long mmr_hash_index_en:1; /* RW */ 677 unsigned long rsvd_21_29:9; 678 unsigned long mmr_write:1; /* WP */ 679 unsigned long mmr_read:1; /* WP */ 680 unsigned long rsvd_32_47:16; 681 unsigned long mmr_inj_con:1; /* RW */ 682 unsigned long rsvd_49_51:3; 683 unsigned long mmr_inj_tlbram:1; /* RW */ 684 unsigned long rsvd_53:1; 685 unsigned long mmr_inj_tlbpgsize:1; /* RW */ 686 unsigned long rsvd_55:1; 687 unsigned long mmr_inj_tlbrreg:1; /* RW */ 688 unsigned long rsvd_57_59:3; 689 unsigned long mmr_inj_tlblruv:1; /* RW */ 690 unsigned long rsvd_61_63:3; 691 } s1; 692 struct uvxh_gr0_tlb_mmr_control_s { 693 unsigned long index:12; /* RW */ 694 unsigned long mem_sel:2; /* RW */ 695 unsigned long rsvd_14_15:2; 696 unsigned long auto_valid_en:1; /* RW */ 697 unsigned long rsvd_17_19:3; 698 unsigned long mmr_hash_index_en:1; /* RW */ 699 unsigned long rsvd_21_29:9; 700 unsigned long mmr_write:1; /* WP */ 701 unsigned long mmr_read:1; /* WP */ 702 unsigned long mmr_op_done:1; /* RW */ 703 unsigned long rsvd_33_47:15; 704 unsigned long rsvd_48:1; 705 unsigned long rsvd_49_51:3; 706 unsigned long rsvd_52:1; 707 unsigned long rsvd_53_63:11; 708 } sx; 709 struct uv2h_gr0_tlb_mmr_control_s { 710 unsigned long index:12; /* RW */ 711 unsigned long mem_sel:2; /* RW */ 712 unsigned long rsvd_14_15:2; 713 unsigned long auto_valid_en:1; /* RW */ 714 unsigned long rsvd_17_19:3; 715 unsigned long mmr_hash_index_en:1; /* RW */ 716 unsigned long rsvd_21_29:9; 717 unsigned long mmr_write:1; /* WP */ 718 unsigned long mmr_read:1; /* WP */ 719 unsigned long mmr_op_done:1; /* RW */ 720 unsigned long rsvd_33_47:15; 721 unsigned long mmr_inj_con:1; /* RW */ 722 unsigned long rsvd_49_51:3; 723 unsigned long mmr_inj_tlbram:1; /* RW */ 724 unsigned long rsvd_53_63:11; 725 } s2; 726 struct uv3h_gr0_tlb_mmr_control_s { 727 unsigned long index:12; /* RW */ 728 unsigned long mem_sel:2; /* RW */ 729 unsigned long rsvd_14_15:2; 730 unsigned long auto_valid_en:1; /* RW */ 731 unsigned long rsvd_17_19:3; 732 unsigned long mmr_hash_index_en:1; /* RW */ 733 unsigned long ecc_sel:1; /* RW */ 734 unsigned long rsvd_22_29:8; 735 unsigned long mmr_write:1; /* WP */ 736 unsigned long mmr_read:1; /* WP */ 737 unsigned long mmr_op_done:1; /* RW */ 738 unsigned long rsvd_33_47:15; 739 unsigned long undef_48:1; /* Undefined */ 740 unsigned long rsvd_49_51:3; 741 unsigned long undef_52:1; /* Undefined */ 742 unsigned long rsvd_53_63:11; 743 } s3; 744 }; 745 746 /* ========================================================================= */ 747 /* UVH_GR0_TLB_MMR_READ_DATA_HI */ 748 /* ========================================================================= */ 749 #define UV1H_GR0_TLB_MMR_READ_DATA_HI 0x4010a0UL 750 #define UV2H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL 751 #define UV3H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL 752 #define UVH_GR0_TLB_MMR_READ_DATA_HI \ 753 (is_uv1_hub() ? UV1H_GR0_TLB_MMR_READ_DATA_HI : \ 754 (is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_HI : \ 755 UV3H_GR0_TLB_MMR_READ_DATA_HI)) 756 757 #define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 758 #define UVH_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 759 #define UVH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 760 #define UVH_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 761 #define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL 762 #define UVH_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL 763 #define UVH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL 764 #define UVH_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 765 766 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 767 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 768 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 769 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 770 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL 771 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL 772 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL 773 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 774 775 #define UVXH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 776 #define UVXH_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 777 #define UVXH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 778 #define UVXH_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 779 #define UVXH_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL 780 #define UVXH_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL 781 #define UVXH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL 782 #define UVXH_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 783 784 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 785 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 786 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 787 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 788 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL 789 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL 790 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL 791 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 792 793 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 794 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 795 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 796 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 797 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT 45 798 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT 55 799 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL 800 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL 801 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL 802 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 803 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_MASK 0x0000200000000000UL 804 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK 0xff80000000000000UL 805 806 union uvh_gr0_tlb_mmr_read_data_hi_u { 807 unsigned long v; 808 struct uvh_gr0_tlb_mmr_read_data_hi_s { 809 unsigned long pfn:41; /* RO */ 810 unsigned long gaa:2; /* RO */ 811 unsigned long dirty:1; /* RO */ 812 unsigned long larger:1; /* RO */ 813 unsigned long rsvd_45_63:19; 814 } s; 815 struct uv1h_gr0_tlb_mmr_read_data_hi_s { 816 unsigned long pfn:41; /* RO */ 817 unsigned long gaa:2; /* RO */ 818 unsigned long dirty:1; /* RO */ 819 unsigned long larger:1; /* RO */ 820 unsigned long rsvd_45_63:19; 821 } s1; 822 struct uvxh_gr0_tlb_mmr_read_data_hi_s { 823 unsigned long pfn:41; /* RO */ 824 unsigned long gaa:2; /* RO */ 825 unsigned long dirty:1; /* RO */ 826 unsigned long larger:1; /* RO */ 827 unsigned long rsvd_45_63:19; 828 } sx; 829 struct uv2h_gr0_tlb_mmr_read_data_hi_s { 830 unsigned long pfn:41; /* RO */ 831 unsigned long gaa:2; /* RO */ 832 unsigned long dirty:1; /* RO */ 833 unsigned long larger:1; /* RO */ 834 unsigned long rsvd_45_63:19; 835 } s2; 836 struct uv3h_gr0_tlb_mmr_read_data_hi_s { 837 unsigned long pfn:41; /* RO */ 838 unsigned long gaa:2; /* RO */ 839 unsigned long dirty:1; /* RO */ 840 unsigned long larger:1; /* RO */ 841 unsigned long aa_ext:1; /* RO */ 842 unsigned long undef_46_54:9; /* Undefined */ 843 unsigned long way_ecc:9; /* RO */ 844 } s3; 845 }; 846 847 /* ========================================================================= */ 848 /* UVH_GR0_TLB_MMR_READ_DATA_LO */ 849 /* ========================================================================= */ 850 #define UV1H_GR0_TLB_MMR_READ_DATA_LO 0x4010a8UL 851 #define UV2H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL 852 #define UV3H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL 853 #define UVH_GR0_TLB_MMR_READ_DATA_LO \ 854 (is_uv1_hub() ? UV1H_GR0_TLB_MMR_READ_DATA_LO : \ 855 (is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_LO : \ 856 UV3H_GR0_TLB_MMR_READ_DATA_LO)) 857 858 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 859 #define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 860 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 861 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 862 #define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 863 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 864 865 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 866 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 867 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 868 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 869 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 870 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 871 872 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 873 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 874 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 875 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 876 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 877 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 878 879 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 880 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 881 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 882 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 883 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 884 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 885 886 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 887 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 888 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 889 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 890 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 891 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 892 893 union uvh_gr0_tlb_mmr_read_data_lo_u { 894 unsigned long v; 895 struct uvh_gr0_tlb_mmr_read_data_lo_s { 896 unsigned long vpn:39; /* RO */ 897 unsigned long asid:24; /* RO */ 898 unsigned long valid:1; /* RO */ 899 } s; 900 struct uv1h_gr0_tlb_mmr_read_data_lo_s { 901 unsigned long vpn:39; /* RO */ 902 unsigned long asid:24; /* RO */ 903 unsigned long valid:1; /* RO */ 904 } s1; 905 struct uvxh_gr0_tlb_mmr_read_data_lo_s { 906 unsigned long vpn:39; /* RO */ 907 unsigned long asid:24; /* RO */ 908 unsigned long valid:1; /* RO */ 909 } sx; 910 struct uv2h_gr0_tlb_mmr_read_data_lo_s { 911 unsigned long vpn:39; /* RO */ 912 unsigned long asid:24; /* RO */ 913 unsigned long valid:1; /* RO */ 914 } s2; 915 struct uv3h_gr0_tlb_mmr_read_data_lo_s { 916 unsigned long vpn:39; /* RO */ 917 unsigned long asid:24; /* RO */ 918 unsigned long valid:1; /* RO */ 919 } s3; 920 }; 921 922 /* ========================================================================= */ 923 /* UVH_GR1_TLB_INT0_CONFIG */ 924 /* ========================================================================= */ 925 #define UVH_GR1_TLB_INT0_CONFIG 0x61f00UL 926 927 #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0 928 #define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT 8 929 #define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT 11 930 #define UVH_GR1_TLB_INT0_CONFIG_STATUS_SHFT 12 931 #define UVH_GR1_TLB_INT0_CONFIG_P_SHFT 13 932 #define UVH_GR1_TLB_INT0_CONFIG_T_SHFT 15 933 #define UVH_GR1_TLB_INT0_CONFIG_M_SHFT 16 934 #define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT 32 935 #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL 936 #define UVH_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL 937 #define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL 938 #define UVH_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL 939 #define UVH_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL 940 #define UVH_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL 941 #define UVH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL 942 #define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 943 944 union uvh_gr1_tlb_int0_config_u { 945 unsigned long v; 946 struct uvh_gr1_tlb_int0_config_s { 947 unsigned long vector_:8; /* RW */ 948 unsigned long dm:3; /* RW */ 949 unsigned long destmode:1; /* RW */ 950 unsigned long status:1; /* RO */ 951 unsigned long p:1; /* RO */ 952 unsigned long rsvd_14:1; 953 unsigned long t:1; /* RO */ 954 unsigned long m:1; /* RW */ 955 unsigned long rsvd_17_31:15; 956 unsigned long apic_id:32; /* RW */ 957 } s; 958 }; 959 960 /* ========================================================================= */ 961 /* UVH_GR1_TLB_INT1_CONFIG */ 962 /* ========================================================================= */ 963 #define UVH_GR1_TLB_INT1_CONFIG 0x61f40UL 964 965 #define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0 966 #define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT 8 967 #define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT 11 968 #define UVH_GR1_TLB_INT1_CONFIG_STATUS_SHFT 12 969 #define UVH_GR1_TLB_INT1_CONFIG_P_SHFT 13 970 #define UVH_GR1_TLB_INT1_CONFIG_T_SHFT 15 971 #define UVH_GR1_TLB_INT1_CONFIG_M_SHFT 16 972 #define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT 32 973 #define UVH_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL 974 #define UVH_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL 975 #define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL 976 #define UVH_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL 977 #define UVH_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL 978 #define UVH_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL 979 #define UVH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL 980 #define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 981 982 union uvh_gr1_tlb_int1_config_u { 983 unsigned long v; 984 struct uvh_gr1_tlb_int1_config_s { 985 unsigned long vector_:8; /* RW */ 986 unsigned long dm:3; /* RW */ 987 unsigned long destmode:1; /* RW */ 988 unsigned long status:1; /* RO */ 989 unsigned long p:1; /* RO */ 990 unsigned long rsvd_14:1; 991 unsigned long t:1; /* RO */ 992 unsigned long m:1; /* RW */ 993 unsigned long rsvd_17_31:15; 994 unsigned long apic_id:32; /* RW */ 995 } s; 996 }; 997 998 /* ========================================================================= */ 999 /* UVH_GR1_TLB_MMR_CONTROL */ 1000 /* ========================================================================= */ 1001 #define UV1H_GR1_TLB_MMR_CONTROL 0x801080UL 1002 #define UV2H_GR1_TLB_MMR_CONTROL 0x1001080UL 1003 #define UV3H_GR1_TLB_MMR_CONTROL 0x1001080UL 1004 #define UVH_GR1_TLB_MMR_CONTROL \ 1005 (is_uv1_hub() ? UV1H_GR1_TLB_MMR_CONTROL : \ 1006 (is_uv2_hub() ? UV2H_GR1_TLB_MMR_CONTROL : \ 1007 UV3H_GR1_TLB_MMR_CONTROL)) 1008 1009 #define UVH_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 1010 #define UVH_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 1011 #define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 1012 #define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 1013 #define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 1014 #define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31 1015 #define UVH_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL 1016 #define UVH_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL 1017 #define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 1018 #define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 1019 #define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 1020 #define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 1021 1022 #define UV1H_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 1023 #define UV1H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 1024 #define UV1H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 1025 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 1026 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 1027 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31 1028 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT 48 1029 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT 52 1030 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_SHFT 54 1031 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_SHFT 56 1032 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_SHFT 60 1033 #define UV1H_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL 1034 #define UV1H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL 1035 #define UV1H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 1036 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 1037 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 1038 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 1039 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL 1040 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL 1041 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_MASK 0x0040000000000000UL 1042 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK 0x0100000000000000UL 1043 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK 0x1000000000000000UL 1044 1045 #define UVXH_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 1046 #define UVXH_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 1047 #define UVXH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 1048 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 1049 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 1050 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31 1051 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 1052 #define UVXH_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL 1053 #define UVXH_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL 1054 #define UVXH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 1055 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 1056 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 1057 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 1058 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 1059 1060 #define UV2H_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 1061 #define UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 1062 #define UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 1063 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 1064 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 1065 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31 1066 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 1067 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT 48 1068 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT 52 1069 #define UV2H_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL 1070 #define UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL 1071 #define UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 1072 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 1073 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 1074 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 1075 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 1076 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL 1077 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL 1078 1079 #define UV3H_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 1080 #define UV3H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 1081 #define UV3H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 1082 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 1083 #define UV3H_GR1_TLB_MMR_CONTROL_ECC_SEL_SHFT 21 1084 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 1085 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31 1086 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 1087 #define UV3H_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL 1088 #define UV3H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL 1089 #define UV3H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 1090 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 1091 #define UV3H_GR1_TLB_MMR_CONTROL_ECC_SEL_MASK 0x0000000000200000UL 1092 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 1093 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 1094 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 1095 1096 union uvh_gr1_tlb_mmr_control_u { 1097 unsigned long v; 1098 struct uvh_gr1_tlb_mmr_control_s { 1099 unsigned long index:12; /* RW */ 1100 unsigned long mem_sel:2; /* RW */ 1101 unsigned long rsvd_14_15:2; 1102 unsigned long auto_valid_en:1; /* RW */ 1103 unsigned long rsvd_17_19:3; 1104 unsigned long mmr_hash_index_en:1; /* RW */ 1105 unsigned long rsvd_21_29:9; 1106 unsigned long mmr_write:1; /* WP */ 1107 unsigned long mmr_read:1; /* WP */ 1108 unsigned long rsvd_32_48:17; 1109 unsigned long rsvd_49_51:3; 1110 unsigned long rsvd_52_63:12; 1111 } s; 1112 struct uv1h_gr1_tlb_mmr_control_s { 1113 unsigned long index:12; /* RW */ 1114 unsigned long mem_sel:2; /* RW */ 1115 unsigned long rsvd_14_15:2; 1116 unsigned long auto_valid_en:1; /* RW */ 1117 unsigned long rsvd_17_19:3; 1118 unsigned long mmr_hash_index_en:1; /* RW */ 1119 unsigned long rsvd_21_29:9; 1120 unsigned long mmr_write:1; /* WP */ 1121 unsigned long mmr_read:1; /* WP */ 1122 unsigned long rsvd_32_47:16; 1123 unsigned long mmr_inj_con:1; /* RW */ 1124 unsigned long rsvd_49_51:3; 1125 unsigned long mmr_inj_tlbram:1; /* RW */ 1126 unsigned long rsvd_53:1; 1127 unsigned long mmr_inj_tlbpgsize:1; /* RW */ 1128 unsigned long rsvd_55:1; 1129 unsigned long mmr_inj_tlbrreg:1; /* RW */ 1130 unsigned long rsvd_57_59:3; 1131 unsigned long mmr_inj_tlblruv:1; /* RW */ 1132 unsigned long rsvd_61_63:3; 1133 } s1; 1134 struct uvxh_gr1_tlb_mmr_control_s { 1135 unsigned long index:12; /* RW */ 1136 unsigned long mem_sel:2; /* RW */ 1137 unsigned long rsvd_14_15:2; 1138 unsigned long auto_valid_en:1; /* RW */ 1139 unsigned long rsvd_17_19:3; 1140 unsigned long mmr_hash_index_en:1; /* RW */ 1141 unsigned long rsvd_21_29:9; 1142 unsigned long mmr_write:1; /* WP */ 1143 unsigned long mmr_read:1; /* WP */ 1144 unsigned long mmr_op_done:1; /* RW */ 1145 unsigned long rsvd_33_47:15; 1146 unsigned long rsvd_48:1; 1147 unsigned long rsvd_49_51:3; 1148 unsigned long rsvd_52:1; 1149 unsigned long rsvd_53_63:11; 1150 } sx; 1151 struct uv2h_gr1_tlb_mmr_control_s { 1152 unsigned long index:12; /* RW */ 1153 unsigned long mem_sel:2; /* RW */ 1154 unsigned long rsvd_14_15:2; 1155 unsigned long auto_valid_en:1; /* RW */ 1156 unsigned long rsvd_17_19:3; 1157 unsigned long mmr_hash_index_en:1; /* RW */ 1158 unsigned long rsvd_21_29:9; 1159 unsigned long mmr_write:1; /* WP */ 1160 unsigned long mmr_read:1; /* WP */ 1161 unsigned long mmr_op_done:1; /* RW */ 1162 unsigned long rsvd_33_47:15; 1163 unsigned long mmr_inj_con:1; /* RW */ 1164 unsigned long rsvd_49_51:3; 1165 unsigned long mmr_inj_tlbram:1; /* RW */ 1166 unsigned long rsvd_53_63:11; 1167 } s2; 1168 struct uv3h_gr1_tlb_mmr_control_s { 1169 unsigned long index:12; /* RW */ 1170 unsigned long mem_sel:2; /* RW */ 1171 unsigned long rsvd_14_15:2; 1172 unsigned long auto_valid_en:1; /* RW */ 1173 unsigned long rsvd_17_19:3; 1174 unsigned long mmr_hash_index_en:1; /* RW */ 1175 unsigned long ecc_sel:1; /* RW */ 1176 unsigned long rsvd_22_29:8; 1177 unsigned long mmr_write:1; /* WP */ 1178 unsigned long mmr_read:1; /* WP */ 1179 unsigned long mmr_op_done:1; /* RW */ 1180 unsigned long rsvd_33_47:15; 1181 unsigned long undef_48:1; /* Undefined */ 1182 unsigned long rsvd_49_51:3; 1183 unsigned long undef_52:1; /* Undefined */ 1184 unsigned long rsvd_53_63:11; 1185 } s3; 1186 }; 1187 1188 /* ========================================================================= */ 1189 /* UVH_GR1_TLB_MMR_READ_DATA_HI */ 1190 /* ========================================================================= */ 1191 #define UV1H_GR1_TLB_MMR_READ_DATA_HI 0x8010a0UL 1192 #define UV2H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL 1193 #define UV3H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL 1194 #define UVH_GR1_TLB_MMR_READ_DATA_HI \ 1195 (is_uv1_hub() ? UV1H_GR1_TLB_MMR_READ_DATA_HI : \ 1196 (is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_HI : \ 1197 UV3H_GR1_TLB_MMR_READ_DATA_HI)) 1198 1199 #define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1200 #define UVH_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 1201 #define UVH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 1202 #define UVH_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 1203 #define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL 1204 #define UVH_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL 1205 #define UVH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL 1206 #define UVH_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 1207 1208 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1209 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 1210 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 1211 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 1212 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL 1213 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL 1214 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL 1215 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 1216 1217 #define UVXH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1218 #define UVXH_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 1219 #define UVXH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 1220 #define UVXH_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 1221 #define UVXH_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL 1222 #define UVXH_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL 1223 #define UVXH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL 1224 #define UVXH_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 1225 1226 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1227 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 1228 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 1229 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 1230 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL 1231 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL 1232 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL 1233 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 1234 1235 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1236 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 1237 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 1238 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 1239 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT 45 1240 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT 55 1241 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL 1242 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL 1243 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL 1244 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 1245 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_MASK 0x0000200000000000UL 1246 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK 0xff80000000000000UL 1247 1248 union uvh_gr1_tlb_mmr_read_data_hi_u { 1249 unsigned long v; 1250 struct uvh_gr1_tlb_mmr_read_data_hi_s { 1251 unsigned long pfn:41; /* RO */ 1252 unsigned long gaa:2; /* RO */ 1253 unsigned long dirty:1; /* RO */ 1254 unsigned long larger:1; /* RO */ 1255 unsigned long rsvd_45_63:19; 1256 } s; 1257 struct uv1h_gr1_tlb_mmr_read_data_hi_s { 1258 unsigned long pfn:41; /* RO */ 1259 unsigned long gaa:2; /* RO */ 1260 unsigned long dirty:1; /* RO */ 1261 unsigned long larger:1; /* RO */ 1262 unsigned long rsvd_45_63:19; 1263 } s1; 1264 struct uvxh_gr1_tlb_mmr_read_data_hi_s { 1265 unsigned long pfn:41; /* RO */ 1266 unsigned long gaa:2; /* RO */ 1267 unsigned long dirty:1; /* RO */ 1268 unsigned long larger:1; /* RO */ 1269 unsigned long rsvd_45_63:19; 1270 } sx; 1271 struct uv2h_gr1_tlb_mmr_read_data_hi_s { 1272 unsigned long pfn:41; /* RO */ 1273 unsigned long gaa:2; /* RO */ 1274 unsigned long dirty:1; /* RO */ 1275 unsigned long larger:1; /* RO */ 1276 unsigned long rsvd_45_63:19; 1277 } s2; 1278 struct uv3h_gr1_tlb_mmr_read_data_hi_s { 1279 unsigned long pfn:41; /* RO */ 1280 unsigned long gaa:2; /* RO */ 1281 unsigned long dirty:1; /* RO */ 1282 unsigned long larger:1; /* RO */ 1283 unsigned long aa_ext:1; /* RO */ 1284 unsigned long undef_46_54:9; /* Undefined */ 1285 unsigned long way_ecc:9; /* RO */ 1286 } s3; 1287 }; 1288 1289 /* ========================================================================= */ 1290 /* UVH_GR1_TLB_MMR_READ_DATA_LO */ 1291 /* ========================================================================= */ 1292 #define UV1H_GR1_TLB_MMR_READ_DATA_LO 0x8010a8UL 1293 #define UV2H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL 1294 #define UV3H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL 1295 #define UVH_GR1_TLB_MMR_READ_DATA_LO \ 1296 (is_uv1_hub() ? UV1H_GR1_TLB_MMR_READ_DATA_LO : \ 1297 (is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_LO : \ 1298 UV3H_GR1_TLB_MMR_READ_DATA_LO)) 1299 1300 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1301 #define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1302 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1303 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1304 #define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1305 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1306 1307 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1308 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1309 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1310 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1311 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1312 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1313 1314 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1315 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1316 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1317 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1318 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1319 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1320 1321 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1322 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1323 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1324 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1325 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1326 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1327 1328 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1329 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1330 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1331 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1332 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1333 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1334 1335 union uvh_gr1_tlb_mmr_read_data_lo_u { 1336 unsigned long v; 1337 struct uvh_gr1_tlb_mmr_read_data_lo_s { 1338 unsigned long vpn:39; /* RO */ 1339 unsigned long asid:24; /* RO */ 1340 unsigned long valid:1; /* RO */ 1341 } s; 1342 struct uv1h_gr1_tlb_mmr_read_data_lo_s { 1343 unsigned long vpn:39; /* RO */ 1344 unsigned long asid:24; /* RO */ 1345 unsigned long valid:1; /* RO */ 1346 } s1; 1347 struct uvxh_gr1_tlb_mmr_read_data_lo_s { 1348 unsigned long vpn:39; /* RO */ 1349 unsigned long asid:24; /* RO */ 1350 unsigned long valid:1; /* RO */ 1351 } sx; 1352 struct uv2h_gr1_tlb_mmr_read_data_lo_s { 1353 unsigned long vpn:39; /* RO */ 1354 unsigned long asid:24; /* RO */ 1355 unsigned long valid:1; /* RO */ 1356 } s2; 1357 struct uv3h_gr1_tlb_mmr_read_data_lo_s { 1358 unsigned long vpn:39; /* RO */ 1359 unsigned long asid:24; /* RO */ 1360 unsigned long valid:1; /* RO */ 1361 } s3; 1362 }; 1363 1364 /* ========================================================================= */ 1365 /* UVH_INT_CMPB */ 1366 /* ========================================================================= */ 1367 #define UVH_INT_CMPB 0x22080UL 1368 1369 #define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0 1370 #define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL 1371 1372 union uvh_int_cmpb_u { 1373 unsigned long v; 1374 struct uvh_int_cmpb_s { 1375 unsigned long real_time_cmpb:56; /* RW */ 1376 unsigned long rsvd_56_63:8; 1377 } s; 1378 }; 1379 1380 /* ========================================================================= */ 1381 /* UVH_INT_CMPC */ 1382 /* ========================================================================= */ 1383 #define UVH_INT_CMPC 0x22100UL 1384 1385 #define UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT 0 1386 #define UV1H_INT_CMPC_REAL_TIME_CMPC_MASK 0x00ffffffffffffffUL 1387 1388 #define UVXH_INT_CMPC_REAL_TIME_CMP_2_SHFT 0 1389 #define UVXH_INT_CMPC_REAL_TIME_CMP_2_MASK 0x00ffffffffffffffUL 1390 1391 union uvh_int_cmpc_u { 1392 unsigned long v; 1393 struct uvh_int_cmpc_s { 1394 unsigned long real_time_cmpc:56; /* RW */ 1395 unsigned long rsvd_56_63:8; 1396 } s; 1397 }; 1398 1399 /* ========================================================================= */ 1400 /* UVH_INT_CMPD */ 1401 /* ========================================================================= */ 1402 #define UVH_INT_CMPD 0x22180UL 1403 1404 #define UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT 0 1405 #define UV1H_INT_CMPD_REAL_TIME_CMPD_MASK 0x00ffffffffffffffUL 1406 1407 #define UVXH_INT_CMPD_REAL_TIME_CMP_3_SHFT 0 1408 #define UVXH_INT_CMPD_REAL_TIME_CMP_3_MASK 0x00ffffffffffffffUL 1409 1410 union uvh_int_cmpd_u { 1411 unsigned long v; 1412 struct uvh_int_cmpd_s { 1413 unsigned long real_time_cmpd:56; /* RW */ 1414 unsigned long rsvd_56_63:8; 1415 } s; 1416 }; 1417 1418 /* ========================================================================= */ 1419 /* UVH_IPI_INT */ 1420 /* ========================================================================= */ 1421 #define UVH_IPI_INT 0x60500UL 1422 #define UVH_IPI_INT_32 0x348 1423 1424 #define UVH_IPI_INT_VECTOR_SHFT 0 1425 #define UVH_IPI_INT_DELIVERY_MODE_SHFT 8 1426 #define UVH_IPI_INT_DESTMODE_SHFT 11 1427 #define UVH_IPI_INT_APIC_ID_SHFT 16 1428 #define UVH_IPI_INT_SEND_SHFT 63 1429 #define UVH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL 1430 #define UVH_IPI_INT_DELIVERY_MODE_MASK 0x0000000000000700UL 1431 #define UVH_IPI_INT_DESTMODE_MASK 0x0000000000000800UL 1432 #define UVH_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL 1433 #define UVH_IPI_INT_SEND_MASK 0x8000000000000000UL 1434 1435 union uvh_ipi_int_u { 1436 unsigned long v; 1437 struct uvh_ipi_int_s { 1438 unsigned long vector_:8; /* RW */ 1439 unsigned long delivery_mode:3; /* RW */ 1440 unsigned long destmode:1; /* RW */ 1441 unsigned long rsvd_12_15:4; 1442 unsigned long apic_id:32; /* RW */ 1443 unsigned long rsvd_48_62:15; 1444 unsigned long send:1; /* WP */ 1445 } s; 1446 }; 1447 1448 /* ========================================================================= */ 1449 /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST */ 1450 /* ========================================================================= */ 1451 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL 1452 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x9c0 1453 1454 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4 1455 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49 1456 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL 1457 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL 1458 1459 union uvh_lb_bau_intd_payload_queue_first_u { 1460 unsigned long v; 1461 struct uvh_lb_bau_intd_payload_queue_first_s { 1462 unsigned long rsvd_0_3:4; 1463 unsigned long address:39; /* RW */ 1464 unsigned long rsvd_43_48:6; 1465 unsigned long node_id:14; /* RW */ 1466 unsigned long rsvd_63:1; 1467 } s; 1468 }; 1469 1470 /* ========================================================================= */ 1471 /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST */ 1472 /* ========================================================================= */ 1473 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL 1474 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x9c8 1475 1476 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4 1477 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL 1478 1479 union uvh_lb_bau_intd_payload_queue_last_u { 1480 unsigned long v; 1481 struct uvh_lb_bau_intd_payload_queue_last_s { 1482 unsigned long rsvd_0_3:4; 1483 unsigned long address:39; /* RW */ 1484 unsigned long rsvd_43_63:21; 1485 } s; 1486 }; 1487 1488 /* ========================================================================= */ 1489 /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL */ 1490 /* ========================================================================= */ 1491 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL 1492 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x9d0 1493 1494 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4 1495 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL 1496 1497 union uvh_lb_bau_intd_payload_queue_tail_u { 1498 unsigned long v; 1499 struct uvh_lb_bau_intd_payload_queue_tail_s { 1500 unsigned long rsvd_0_3:4; 1501 unsigned long address:39; /* RW */ 1502 unsigned long rsvd_43_63:21; 1503 } s; 1504 }; 1505 1506 /* ========================================================================= */ 1507 /* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE */ 1508 /* ========================================================================= */ 1509 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL 1510 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0xa68 1511 1512 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 1513 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1 1514 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2 1515 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3 1516 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4 1517 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5 1518 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6 1519 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7 1520 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8 1521 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9 1522 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10 1523 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11 1524 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12 1525 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13 1526 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14 1527 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15 1528 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL 1529 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL 1530 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL 1531 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL 1532 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL 1533 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL 1534 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL 1535 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL 1536 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL 1537 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL 1538 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL 1539 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL 1540 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL 1541 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL 1542 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL 1543 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL 1544 1545 union uvh_lb_bau_intd_software_acknowledge_u { 1546 unsigned long v; 1547 struct uvh_lb_bau_intd_software_acknowledge_s { 1548 unsigned long pending_0:1; /* RW, W1C */ 1549 unsigned long pending_1:1; /* RW, W1C */ 1550 unsigned long pending_2:1; /* RW, W1C */ 1551 unsigned long pending_3:1; /* RW, W1C */ 1552 unsigned long pending_4:1; /* RW, W1C */ 1553 unsigned long pending_5:1; /* RW, W1C */ 1554 unsigned long pending_6:1; /* RW, W1C */ 1555 unsigned long pending_7:1; /* RW, W1C */ 1556 unsigned long timeout_0:1; /* RW, W1C */ 1557 unsigned long timeout_1:1; /* RW, W1C */ 1558 unsigned long timeout_2:1; /* RW, W1C */ 1559 unsigned long timeout_3:1; /* RW, W1C */ 1560 unsigned long timeout_4:1; /* RW, W1C */ 1561 unsigned long timeout_5:1; /* RW, W1C */ 1562 unsigned long timeout_6:1; /* RW, W1C */ 1563 unsigned long timeout_7:1; /* RW, W1C */ 1564 unsigned long rsvd_16_63:48; 1565 } s; 1566 }; 1567 1568 /* ========================================================================= */ 1569 /* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS */ 1570 /* ========================================================================= */ 1571 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL 1572 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0xa70 1573 1574 1575 /* ========================================================================= */ 1576 /* UVH_LB_BAU_MISC_CONTROL */ 1577 /* ========================================================================= */ 1578 #define UVH_LB_BAU_MISC_CONTROL 0x320170UL 1579 #define UV1H_LB_BAU_MISC_CONTROL 0x320170UL 1580 #define UV2H_LB_BAU_MISC_CONTROL 0x320170UL 1581 #define UV3H_LB_BAU_MISC_CONTROL 0x320170UL 1582 #define UVH_LB_BAU_MISC_CONTROL_32 0xa10 1583 #define UV1H_LB_BAU_MISC_CONTROL_32 0x320170UL 1584 #define UV2H_LB_BAU_MISC_CONTROL_32 0x320170UL 1585 #define UV3H_LB_BAU_MISC_CONTROL_32 0x320170UL 1586 1587 #define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 1588 #define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 1589 #define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 1590 #define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 1591 #define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 1592 #define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 1593 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15 1594 #define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16 1595 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 1596 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 1597 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 1598 #define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 1599 #define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 1600 #define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 1601 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 1602 #define UVH_LB_BAU_MISC_CONTROL_FUN_SHFT 48 1603 #define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 1604 #define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL 1605 #define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL 1606 #define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 1607 #define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 1608 #define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 1609 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL 1610 #define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL 1611 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL 1612 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL 1613 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL 1614 #define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL 1615 #define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL 1616 #define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL 1617 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 1618 #define UVH_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 1619 1620 #define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 1621 #define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 1622 #define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 1623 #define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 1624 #define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 1625 #define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 1626 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15 1627 #define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16 1628 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 1629 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 1630 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 1631 #define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 1632 #define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 1633 #define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 1634 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 1635 #define UV1H_LB_BAU_MISC_CONTROL_FUN_SHFT 48 1636 #define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 1637 #define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL 1638 #define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL 1639 #define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 1640 #define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 1641 #define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 1642 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL 1643 #define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL 1644 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL 1645 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL 1646 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL 1647 #define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL 1648 #define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL 1649 #define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL 1650 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 1651 #define UV1H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 1652 1653 #define UVXH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 1654 #define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 1655 #define UVXH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 1656 #define UVXH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 1657 #define UVXH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 1658 #define UVXH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 1659 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15 1660 #define UVXH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16 1661 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 1662 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 1663 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 1664 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 1665 #define UVXH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 1666 #define UVXH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 1667 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 1668 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29 1669 #define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT 30 1670 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31 1671 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32 1672 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33 1673 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34 1674 #define UVXH_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35 1675 #define UVXH_LB_BAU_MISC_CONTROL_FUN_SHFT 48 1676 #define UVXH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 1677 #define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL 1678 #define UVXH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL 1679 #define UVXH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 1680 #define UVXH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 1681 #define UVXH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 1682 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL 1683 #define UVXH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL 1684 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL 1685 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL 1686 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL 1687 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL 1688 #define UVXH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL 1689 #define UVXH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL 1690 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 1691 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL 1692 #define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK 0x0000000040000000UL 1693 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL 1694 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL 1695 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL 1696 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL 1697 #define UVXH_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL 1698 #define UVXH_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 1699 1700 #define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 1701 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 1702 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 1703 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 1704 #define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 1705 #define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 1706 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15 1707 #define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16 1708 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 1709 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 1710 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 1711 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 1712 #define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 1713 #define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 1714 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 1715 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29 1716 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT 30 1717 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31 1718 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32 1719 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33 1720 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34 1721 #define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35 1722 #define UV2H_LB_BAU_MISC_CONTROL_FUN_SHFT 48 1723 #define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 1724 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL 1725 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL 1726 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 1727 #define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 1728 #define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 1729 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL 1730 #define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL 1731 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL 1732 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL 1733 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL 1734 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL 1735 #define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL 1736 #define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL 1737 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 1738 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL 1739 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK 0x0000000040000000UL 1740 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL 1741 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL 1742 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL 1743 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL 1744 #define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL 1745 #define UV2H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 1746 1747 #define UV3H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 1748 #define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 1749 #define UV3H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 1750 #define UV3H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 1751 #define UV3H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 1752 #define UV3H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 1753 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15 1754 #define UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16 1755 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 1756 #define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 1757 #define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 1758 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 1759 #define UV3H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 1760 #define UV3H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 1761 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 1762 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29 1763 #define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT 30 1764 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31 1765 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32 1766 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33 1767 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34 1768 #define UV3H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35 1769 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_SHFT 36 1770 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_PREFETCH_HINT_SHFT 37 1771 #define UV3H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_SHFT 38 1772 #define UV3H_LB_BAU_MISC_CONTROL_FUN_SHFT 48 1773 #define UV3H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 1774 #define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL 1775 #define UV3H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL 1776 #define UV3H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 1777 #define UV3H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 1778 #define UV3H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 1779 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL 1780 #define UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL 1781 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL 1782 #define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL 1783 #define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL 1784 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL 1785 #define UV3H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL 1786 #define UV3H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL 1787 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 1788 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL 1789 #define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK 0x0000000040000000UL 1790 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL 1791 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL 1792 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL 1793 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL 1794 #define UV3H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL 1795 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_MASK 0x0000001000000000UL 1796 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_PREFETCH_HINT_MASK 0x0000002000000000UL 1797 #define UV3H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_MASK 0x00003fc000000000UL 1798 #define UV3H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 1799 1800 union uvh_lb_bau_misc_control_u { 1801 unsigned long v; 1802 struct uvh_lb_bau_misc_control_s { 1803 unsigned long rejection_delay:8; /* RW */ 1804 unsigned long apic_mode:1; /* RW */ 1805 unsigned long force_broadcast:1; /* RW */ 1806 unsigned long force_lock_nop:1; /* RW */ 1807 unsigned long qpi_agent_presence_vector:3; /* RW */ 1808 unsigned long descriptor_fetch_mode:1; /* RW */ 1809 unsigned long enable_intd_soft_ack_mode:1; /* RW */ 1810 unsigned long intd_soft_ack_timeout_period:4; /* RW */ 1811 unsigned long enable_dual_mapping_mode:1; /* RW */ 1812 unsigned long vga_io_port_decode_enable:1; /* RW */ 1813 unsigned long vga_io_port_16_bit_decode:1; /* RW */ 1814 unsigned long suppress_dest_registration:1; /* RW */ 1815 unsigned long programmed_initial_priority:3; /* RW */ 1816 unsigned long use_incoming_priority:1; /* RW */ 1817 unsigned long enable_programmed_initial_priority:1;/* RW */ 1818 unsigned long rsvd_29_47:19; 1819 unsigned long fun:16; /* RW */ 1820 } s; 1821 struct uv1h_lb_bau_misc_control_s { 1822 unsigned long rejection_delay:8; /* RW */ 1823 unsigned long apic_mode:1; /* RW */ 1824 unsigned long force_broadcast:1; /* RW */ 1825 unsigned long force_lock_nop:1; /* RW */ 1826 unsigned long qpi_agent_presence_vector:3; /* RW */ 1827 unsigned long descriptor_fetch_mode:1; /* RW */ 1828 unsigned long enable_intd_soft_ack_mode:1; /* RW */ 1829 unsigned long intd_soft_ack_timeout_period:4; /* RW */ 1830 unsigned long enable_dual_mapping_mode:1; /* RW */ 1831 unsigned long vga_io_port_decode_enable:1; /* RW */ 1832 unsigned long vga_io_port_16_bit_decode:1; /* RW */ 1833 unsigned long suppress_dest_registration:1; /* RW */ 1834 unsigned long programmed_initial_priority:3; /* RW */ 1835 unsigned long use_incoming_priority:1; /* RW */ 1836 unsigned long enable_programmed_initial_priority:1;/* RW */ 1837 unsigned long rsvd_29_47:19; 1838 unsigned long fun:16; /* RW */ 1839 } s1; 1840 struct uvxh_lb_bau_misc_control_s { 1841 unsigned long rejection_delay:8; /* RW */ 1842 unsigned long apic_mode:1; /* RW */ 1843 unsigned long force_broadcast:1; /* RW */ 1844 unsigned long force_lock_nop:1; /* RW */ 1845 unsigned long qpi_agent_presence_vector:3; /* RW */ 1846 unsigned long descriptor_fetch_mode:1; /* RW */ 1847 unsigned long enable_intd_soft_ack_mode:1; /* RW */ 1848 unsigned long intd_soft_ack_timeout_period:4; /* RW */ 1849 unsigned long enable_dual_mapping_mode:1; /* RW */ 1850 unsigned long vga_io_port_decode_enable:1; /* RW */ 1851 unsigned long vga_io_port_16_bit_decode:1; /* RW */ 1852 unsigned long suppress_dest_registration:1; /* RW */ 1853 unsigned long programmed_initial_priority:3; /* RW */ 1854 unsigned long use_incoming_priority:1; /* RW */ 1855 unsigned long enable_programmed_initial_priority:1;/* RW */ 1856 unsigned long enable_automatic_apic_mode_selection:1;/* RW */ 1857 unsigned long apic_mode_status:1; /* RO */ 1858 unsigned long suppress_interrupts_to_self:1; /* RW */ 1859 unsigned long enable_lock_based_system_flush:1;/* RW */ 1860 unsigned long enable_extended_sb_status:1; /* RW */ 1861 unsigned long suppress_int_prio_udt_to_self:1;/* RW */ 1862 unsigned long use_legacy_descriptor_formats:1;/* RW */ 1863 unsigned long rsvd_36_47:12; 1864 unsigned long fun:16; /* RW */ 1865 } sx; 1866 struct uv2h_lb_bau_misc_control_s { 1867 unsigned long rejection_delay:8; /* RW */ 1868 unsigned long apic_mode:1; /* RW */ 1869 unsigned long force_broadcast:1; /* RW */ 1870 unsigned long force_lock_nop:1; /* RW */ 1871 unsigned long qpi_agent_presence_vector:3; /* RW */ 1872 unsigned long descriptor_fetch_mode:1; /* RW */ 1873 unsigned long enable_intd_soft_ack_mode:1; /* RW */ 1874 unsigned long intd_soft_ack_timeout_period:4; /* RW */ 1875 unsigned long enable_dual_mapping_mode:1; /* RW */ 1876 unsigned long vga_io_port_decode_enable:1; /* RW */ 1877 unsigned long vga_io_port_16_bit_decode:1; /* RW */ 1878 unsigned long suppress_dest_registration:1; /* RW */ 1879 unsigned long programmed_initial_priority:3; /* RW */ 1880 unsigned long use_incoming_priority:1; /* RW */ 1881 unsigned long enable_programmed_initial_priority:1;/* RW */ 1882 unsigned long enable_automatic_apic_mode_selection:1;/* RW */ 1883 unsigned long apic_mode_status:1; /* RO */ 1884 unsigned long suppress_interrupts_to_self:1; /* RW */ 1885 unsigned long enable_lock_based_system_flush:1;/* RW */ 1886 unsigned long enable_extended_sb_status:1; /* RW */ 1887 unsigned long suppress_int_prio_udt_to_self:1;/* RW */ 1888 unsigned long use_legacy_descriptor_formats:1;/* RW */ 1889 unsigned long rsvd_36_47:12; 1890 unsigned long fun:16; /* RW */ 1891 } s2; 1892 struct uv3h_lb_bau_misc_control_s { 1893 unsigned long rejection_delay:8; /* RW */ 1894 unsigned long apic_mode:1; /* RW */ 1895 unsigned long force_broadcast:1; /* RW */ 1896 unsigned long force_lock_nop:1; /* RW */ 1897 unsigned long qpi_agent_presence_vector:3; /* RW */ 1898 unsigned long descriptor_fetch_mode:1; /* RW */ 1899 unsigned long enable_intd_soft_ack_mode:1; /* RW */ 1900 unsigned long intd_soft_ack_timeout_period:4; /* RW */ 1901 unsigned long enable_dual_mapping_mode:1; /* RW */ 1902 unsigned long vga_io_port_decode_enable:1; /* RW */ 1903 unsigned long vga_io_port_16_bit_decode:1; /* RW */ 1904 unsigned long suppress_dest_registration:1; /* RW */ 1905 unsigned long programmed_initial_priority:3; /* RW */ 1906 unsigned long use_incoming_priority:1; /* RW */ 1907 unsigned long enable_programmed_initial_priority:1;/* RW */ 1908 unsigned long enable_automatic_apic_mode_selection:1;/* RW */ 1909 unsigned long apic_mode_status:1; /* RO */ 1910 unsigned long suppress_interrupts_to_self:1; /* RW */ 1911 unsigned long enable_lock_based_system_flush:1;/* RW */ 1912 unsigned long enable_extended_sb_status:1; /* RW */ 1913 unsigned long suppress_int_prio_udt_to_self:1;/* RW */ 1914 unsigned long use_legacy_descriptor_formats:1;/* RW */ 1915 unsigned long suppress_quiesce_msgs_to_qpi:1; /* RW */ 1916 unsigned long enable_intd_prefetch_hint:1; /* RW */ 1917 unsigned long thread_kill_timebase:8; /* RW */ 1918 unsigned long rsvd_46_47:2; 1919 unsigned long fun:16; /* RW */ 1920 } s3; 1921 }; 1922 1923 /* ========================================================================= */ 1924 /* UVH_LB_BAU_SB_ACTIVATION_CONTROL */ 1925 /* ========================================================================= */ 1926 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL 1927 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8 1928 1929 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0 1930 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62 1931 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT 63 1932 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL 1933 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL 1934 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL 1935 1936 union uvh_lb_bau_sb_activation_control_u { 1937 unsigned long v; 1938 struct uvh_lb_bau_sb_activation_control_s { 1939 unsigned long index:6; /* RW */ 1940 unsigned long rsvd_6_61:56; 1941 unsigned long push:1; /* WP */ 1942 unsigned long init:1; /* WP */ 1943 } s; 1944 }; 1945 1946 /* ========================================================================= */ 1947 /* UVH_LB_BAU_SB_ACTIVATION_STATUS_0 */ 1948 /* ========================================================================= */ 1949 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL 1950 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0 1951 1952 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0 1953 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL 1954 1955 union uvh_lb_bau_sb_activation_status_0_u { 1956 unsigned long v; 1957 struct uvh_lb_bau_sb_activation_status_0_s { 1958 unsigned long status:64; /* RW */ 1959 } s; 1960 }; 1961 1962 /* ========================================================================= */ 1963 /* UVH_LB_BAU_SB_ACTIVATION_STATUS_1 */ 1964 /* ========================================================================= */ 1965 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL 1966 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8 1967 1968 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0 1969 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL 1970 1971 union uvh_lb_bau_sb_activation_status_1_u { 1972 unsigned long v; 1973 struct uvh_lb_bau_sb_activation_status_1_s { 1974 unsigned long status:64; /* RW */ 1975 } s; 1976 }; 1977 1978 /* ========================================================================= */ 1979 /* UVH_LB_BAU_SB_DESCRIPTOR_BASE */ 1980 /* ========================================================================= */ 1981 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL 1982 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0 1983 1984 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12 1985 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49 1986 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL 1987 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL 1988 1989 union uvh_lb_bau_sb_descriptor_base_u { 1990 unsigned long v; 1991 struct uvh_lb_bau_sb_descriptor_base_s { 1992 unsigned long rsvd_0_11:12; 1993 unsigned long page_address:31; /* RW */ 1994 unsigned long rsvd_43_48:6; 1995 unsigned long node_id:14; /* RW */ 1996 unsigned long rsvd_63:1; 1997 } s; 1998 }; 1999 2000 /* ========================================================================= */ 2001 /* UVH_NODE_ID */ 2002 /* ========================================================================= */ 2003 #define UVH_NODE_ID 0x0UL 2004 #define UV1H_NODE_ID 0x0UL 2005 #define UV2H_NODE_ID 0x0UL 2006 #define UV3H_NODE_ID 0x0UL 2007 2008 #define UVH_NODE_ID_FORCE1_SHFT 0 2009 #define UVH_NODE_ID_MANUFACTURER_SHFT 1 2010 #define UVH_NODE_ID_PART_NUMBER_SHFT 12 2011 #define UVH_NODE_ID_REVISION_SHFT 28 2012 #define UVH_NODE_ID_NODE_ID_SHFT 32 2013 #define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL 2014 #define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL 2015 #define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL 2016 #define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL 2017 #define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 2018 2019 #define UV1H_NODE_ID_FORCE1_SHFT 0 2020 #define UV1H_NODE_ID_MANUFACTURER_SHFT 1 2021 #define UV1H_NODE_ID_PART_NUMBER_SHFT 12 2022 #define UV1H_NODE_ID_REVISION_SHFT 28 2023 #define UV1H_NODE_ID_NODE_ID_SHFT 32 2024 #define UV1H_NODE_ID_NODES_PER_BIT_SHFT 48 2025 #define UV1H_NODE_ID_NI_PORT_SHFT 56 2026 #define UV1H_NODE_ID_FORCE1_MASK 0x0000000000000001UL 2027 #define UV1H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL 2028 #define UV1H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL 2029 #define UV1H_NODE_ID_REVISION_MASK 0x00000000f0000000UL 2030 #define UV1H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 2031 #define UV1H_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL 2032 #define UV1H_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL 2033 2034 #define UVXH_NODE_ID_FORCE1_SHFT 0 2035 #define UVXH_NODE_ID_MANUFACTURER_SHFT 1 2036 #define UVXH_NODE_ID_PART_NUMBER_SHFT 12 2037 #define UVXH_NODE_ID_REVISION_SHFT 28 2038 #define UVXH_NODE_ID_NODE_ID_SHFT 32 2039 #define UVXH_NODE_ID_NODES_PER_BIT_SHFT 50 2040 #define UVXH_NODE_ID_NI_PORT_SHFT 57 2041 #define UVXH_NODE_ID_FORCE1_MASK 0x0000000000000001UL 2042 #define UVXH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL 2043 #define UVXH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL 2044 #define UVXH_NODE_ID_REVISION_MASK 0x00000000f0000000UL 2045 #define UVXH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 2046 #define UVXH_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL 2047 #define UVXH_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL 2048 2049 #define UV2H_NODE_ID_FORCE1_SHFT 0 2050 #define UV2H_NODE_ID_MANUFACTURER_SHFT 1 2051 #define UV2H_NODE_ID_PART_NUMBER_SHFT 12 2052 #define UV2H_NODE_ID_REVISION_SHFT 28 2053 #define UV2H_NODE_ID_NODE_ID_SHFT 32 2054 #define UV2H_NODE_ID_NODES_PER_BIT_SHFT 50 2055 #define UV2H_NODE_ID_NI_PORT_SHFT 57 2056 #define UV2H_NODE_ID_FORCE1_MASK 0x0000000000000001UL 2057 #define UV2H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL 2058 #define UV2H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL 2059 #define UV2H_NODE_ID_REVISION_MASK 0x00000000f0000000UL 2060 #define UV2H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 2061 #define UV2H_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL 2062 #define UV2H_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL 2063 2064 #define UV3H_NODE_ID_FORCE1_SHFT 0 2065 #define UV3H_NODE_ID_MANUFACTURER_SHFT 1 2066 #define UV3H_NODE_ID_PART_NUMBER_SHFT 12 2067 #define UV3H_NODE_ID_REVISION_SHFT 28 2068 #define UV3H_NODE_ID_NODE_ID_SHFT 32 2069 #define UV3H_NODE_ID_ROUTER_SELECT_SHFT 48 2070 #define UV3H_NODE_ID_RESERVED_2_SHFT 49 2071 #define UV3H_NODE_ID_NODES_PER_BIT_SHFT 50 2072 #define UV3H_NODE_ID_NI_PORT_SHFT 57 2073 #define UV3H_NODE_ID_FORCE1_MASK 0x0000000000000001UL 2074 #define UV3H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL 2075 #define UV3H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL 2076 #define UV3H_NODE_ID_REVISION_MASK 0x00000000f0000000UL 2077 #define UV3H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 2078 #define UV3H_NODE_ID_ROUTER_SELECT_MASK 0x0001000000000000UL 2079 #define UV3H_NODE_ID_RESERVED_2_MASK 0x0002000000000000UL 2080 #define UV3H_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL 2081 #define UV3H_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL 2082 2083 union uvh_node_id_u { 2084 unsigned long v; 2085 struct uvh_node_id_s { 2086 unsigned long force1:1; /* RO */ 2087 unsigned long manufacturer:11; /* RO */ 2088 unsigned long part_number:16; /* RO */ 2089 unsigned long revision:4; /* RO */ 2090 unsigned long node_id:15; /* RW */ 2091 unsigned long rsvd_47_63:17; 2092 } s; 2093 struct uv1h_node_id_s { 2094 unsigned long force1:1; /* RO */ 2095 unsigned long manufacturer:11; /* RO */ 2096 unsigned long part_number:16; /* RO */ 2097 unsigned long revision:4; /* RO */ 2098 unsigned long node_id:15; /* RW */ 2099 unsigned long rsvd_47:1; 2100 unsigned long nodes_per_bit:7; /* RW */ 2101 unsigned long rsvd_55:1; 2102 unsigned long ni_port:4; /* RO */ 2103 unsigned long rsvd_60_63:4; 2104 } s1; 2105 struct uvxh_node_id_s { 2106 unsigned long force1:1; /* RO */ 2107 unsigned long manufacturer:11; /* RO */ 2108 unsigned long part_number:16; /* RO */ 2109 unsigned long revision:4; /* RO */ 2110 unsigned long node_id:15; /* RW */ 2111 unsigned long rsvd_47_49:3; 2112 unsigned long nodes_per_bit:7; /* RO */ 2113 unsigned long ni_port:5; /* RO */ 2114 unsigned long rsvd_62_63:2; 2115 } sx; 2116 struct uv2h_node_id_s { 2117 unsigned long force1:1; /* RO */ 2118 unsigned long manufacturer:11; /* RO */ 2119 unsigned long part_number:16; /* RO */ 2120 unsigned long revision:4; /* RO */ 2121 unsigned long node_id:15; /* RW */ 2122 unsigned long rsvd_47_49:3; 2123 unsigned long nodes_per_bit:7; /* RO */ 2124 unsigned long ni_port:5; /* RO */ 2125 unsigned long rsvd_62_63:2; 2126 } s2; 2127 struct uv3h_node_id_s { 2128 unsigned long force1:1; /* RO */ 2129 unsigned long manufacturer:11; /* RO */ 2130 unsigned long part_number:16; /* RO */ 2131 unsigned long revision:4; /* RO */ 2132 unsigned long node_id:15; /* RW */ 2133 unsigned long rsvd_47:1; 2134 unsigned long router_select:1; /* RO */ 2135 unsigned long rsvd_49:1; 2136 unsigned long nodes_per_bit:7; /* RO */ 2137 unsigned long ni_port:5; /* RO */ 2138 unsigned long rsvd_62_63:2; 2139 } s3; 2140 }; 2141 2142 /* ========================================================================= */ 2143 /* UVH_NODE_PRESENT_TABLE */ 2144 /* ========================================================================= */ 2145 #define UVH_NODE_PRESENT_TABLE 0x1400UL 2146 #define UVH_NODE_PRESENT_TABLE_DEPTH 16 2147 2148 #define UVH_NODE_PRESENT_TABLE_NODES_SHFT 0 2149 #define UVH_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL 2150 2151 union uvh_node_present_table_u { 2152 unsigned long v; 2153 struct uvh_node_present_table_s { 2154 unsigned long nodes:64; /* RW */ 2155 } s; 2156 }; 2157 2158 /* ========================================================================= */ 2159 /* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR */ 2160 /* ========================================================================= */ 2161 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL 2162 2163 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24 2164 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48 2165 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63 2166 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL 2167 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL 2168 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL 2169 2170 union uvh_rh_gam_alias210_overlay_config_0_mmr_u { 2171 unsigned long v; 2172 struct uvh_rh_gam_alias210_overlay_config_0_mmr_s { 2173 unsigned long rsvd_0_23:24; 2174 unsigned long base:8; /* RW */ 2175 unsigned long rsvd_32_47:16; 2176 unsigned long m_alias:5; /* RW */ 2177 unsigned long rsvd_53_62:10; 2178 unsigned long enable:1; /* RW */ 2179 } s; 2180 }; 2181 2182 /* ========================================================================= */ 2183 /* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR */ 2184 /* ========================================================================= */ 2185 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL 2186 2187 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24 2188 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48 2189 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63 2190 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL 2191 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL 2192 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL 2193 2194 union uvh_rh_gam_alias210_overlay_config_1_mmr_u { 2195 unsigned long v; 2196 struct uvh_rh_gam_alias210_overlay_config_1_mmr_s { 2197 unsigned long rsvd_0_23:24; 2198 unsigned long base:8; /* RW */ 2199 unsigned long rsvd_32_47:16; 2200 unsigned long m_alias:5; /* RW */ 2201 unsigned long rsvd_53_62:10; 2202 unsigned long enable:1; /* RW */ 2203 } s; 2204 }; 2205 2206 /* ========================================================================= */ 2207 /* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR */ 2208 /* ========================================================================= */ 2209 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL 2210 2211 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24 2212 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48 2213 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63 2214 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL 2215 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL 2216 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL 2217 2218 union uvh_rh_gam_alias210_overlay_config_2_mmr_u { 2219 unsigned long v; 2220 struct uvh_rh_gam_alias210_overlay_config_2_mmr_s { 2221 unsigned long rsvd_0_23:24; 2222 unsigned long base:8; /* RW */ 2223 unsigned long rsvd_32_47:16; 2224 unsigned long m_alias:5; /* RW */ 2225 unsigned long rsvd_53_62:10; 2226 unsigned long enable:1; /* RW */ 2227 } s; 2228 }; 2229 2230 /* ========================================================================= */ 2231 /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */ 2232 /* ========================================================================= */ 2233 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL 2234 2235 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 2236 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL 2237 2238 union uvh_rh_gam_alias210_redirect_config_0_mmr_u { 2239 unsigned long v; 2240 struct uvh_rh_gam_alias210_redirect_config_0_mmr_s { 2241 unsigned long rsvd_0_23:24; 2242 unsigned long dest_base:22; /* RW */ 2243 unsigned long rsvd_46_63:18; 2244 } s; 2245 }; 2246 2247 /* ========================================================================= */ 2248 /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */ 2249 /* ========================================================================= */ 2250 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL 2251 2252 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 2253 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL 2254 2255 union uvh_rh_gam_alias210_redirect_config_1_mmr_u { 2256 unsigned long v; 2257 struct uvh_rh_gam_alias210_redirect_config_1_mmr_s { 2258 unsigned long rsvd_0_23:24; 2259 unsigned long dest_base:22; /* RW */ 2260 unsigned long rsvd_46_63:18; 2261 } s; 2262 }; 2263 2264 /* ========================================================================= */ 2265 /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */ 2266 /* ========================================================================= */ 2267 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL 2268 2269 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 2270 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL 2271 2272 union uvh_rh_gam_alias210_redirect_config_2_mmr_u { 2273 unsigned long v; 2274 struct uvh_rh_gam_alias210_redirect_config_2_mmr_s { 2275 unsigned long rsvd_0_23:24; 2276 unsigned long dest_base:22; /* RW */ 2277 unsigned long rsvd_46_63:18; 2278 } s; 2279 }; 2280 2281 /* ========================================================================= */ 2282 /* UVH_RH_GAM_CONFIG_MMR */ 2283 /* ========================================================================= */ 2284 #define UVH_RH_GAM_CONFIG_MMR 0x1600000UL 2285 #define UV1H_RH_GAM_CONFIG_MMR 0x1600000UL 2286 #define UV2H_RH_GAM_CONFIG_MMR 0x1600000UL 2287 #define UV3H_RH_GAM_CONFIG_MMR 0x1600000UL 2288 2289 #define UVH_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 2290 #define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 2291 #define UVH_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL 2292 #define UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 2293 2294 #define UV1H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 2295 #define UV1H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 2296 #define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_SHFT 12 2297 #define UV1H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL 2298 #define UV1H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 2299 #define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK 0x0000000000001000UL 2300 2301 #define UVXH_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 2302 #define UVXH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 2303 #define UVXH_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL 2304 #define UVXH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 2305 2306 #define UV2H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 2307 #define UV2H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 2308 #define UV2H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL 2309 #define UV2H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 2310 2311 #define UV3H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 2312 #define UV3H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 2313 #define UV3H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL 2314 #define UV3H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 2315 2316 union uvh_rh_gam_config_mmr_u { 2317 unsigned long v; 2318 struct uvh_rh_gam_config_mmr_s { 2319 unsigned long m_skt:6; /* RW */ 2320 unsigned long n_skt:4; /* RW */ 2321 unsigned long rsvd_10_63:54; 2322 } s; 2323 struct uv1h_rh_gam_config_mmr_s { 2324 unsigned long m_skt:6; /* RW */ 2325 unsigned long n_skt:4; /* RW */ 2326 unsigned long rsvd_10_11:2; 2327 unsigned long mmiol_cfg:1; /* RW */ 2328 unsigned long rsvd_13_63:51; 2329 } s1; 2330 struct uvxh_rh_gam_config_mmr_s { 2331 unsigned long m_skt:6; /* RW */ 2332 unsigned long n_skt:4; /* RW */ 2333 unsigned long rsvd_10_63:54; 2334 } sx; 2335 struct uv2h_rh_gam_config_mmr_s { 2336 unsigned long m_skt:6; /* RW */ 2337 unsigned long n_skt:4; /* RW */ 2338 unsigned long rsvd_10_63:54; 2339 } s2; 2340 struct uv3h_rh_gam_config_mmr_s { 2341 unsigned long m_skt:6; /* RW */ 2342 unsigned long n_skt:4; /* RW */ 2343 unsigned long rsvd_10_63:54; 2344 } s3; 2345 }; 2346 2347 /* ========================================================================= */ 2348 /* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */ 2349 /* ========================================================================= */ 2350 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL 2351 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL 2352 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL 2353 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL 2354 2355 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 2356 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 2357 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 2358 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL 2359 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 2360 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 2361 2362 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 2363 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48 2364 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 2365 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 2366 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL 2367 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL 2368 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 2369 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 2370 2371 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 2372 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 2373 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 2374 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL 2375 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 2376 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 2377 2378 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 2379 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 2380 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 2381 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL 2382 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 2383 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 2384 2385 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 2386 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 2387 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_MODE_SHFT 62 2388 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 2389 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL 2390 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 2391 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_MODE_MASK 0x4000000000000000UL 2392 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 2393 2394 union uvh_rh_gam_gru_overlay_config_mmr_u { 2395 unsigned long v; 2396 struct uvh_rh_gam_gru_overlay_config_mmr_s { 2397 unsigned long rsvd_0_27:28; 2398 unsigned long base:18; /* RW */ 2399 unsigned long rsvd_46_51:6; 2400 unsigned long n_gru:4; /* RW */ 2401 unsigned long rsvd_56_62:7; 2402 unsigned long enable:1; /* RW */ 2403 } s; 2404 struct uv1h_rh_gam_gru_overlay_config_mmr_s { 2405 unsigned long rsvd_0_27:28; 2406 unsigned long base:18; /* RW */ 2407 unsigned long rsvd_46_47:2; 2408 unsigned long gr4:1; /* RW */ 2409 unsigned long rsvd_49_51:3; 2410 unsigned long n_gru:4; /* RW */ 2411 unsigned long rsvd_56_62:7; 2412 unsigned long enable:1; /* RW */ 2413 } s1; 2414 struct uvxh_rh_gam_gru_overlay_config_mmr_s { 2415 unsigned long rsvd_0_27:28; 2416 unsigned long base:18; /* RW */ 2417 unsigned long rsvd_46_51:6; 2418 unsigned long n_gru:4; /* RW */ 2419 unsigned long rsvd_56_62:7; 2420 unsigned long enable:1; /* RW */ 2421 } sx; 2422 struct uv2h_rh_gam_gru_overlay_config_mmr_s { 2423 unsigned long rsvd_0_27:28; 2424 unsigned long base:18; /* RW */ 2425 unsigned long rsvd_46_51:6; 2426 unsigned long n_gru:4; /* RW */ 2427 unsigned long rsvd_56_62:7; 2428 unsigned long enable:1; /* RW */ 2429 } s2; 2430 struct uv3h_rh_gam_gru_overlay_config_mmr_s { 2431 unsigned long rsvd_0_27:28; 2432 unsigned long base:18; /* RW */ 2433 unsigned long rsvd_46_51:6; 2434 unsigned long n_gru:4; /* RW */ 2435 unsigned long rsvd_56_61:6; 2436 unsigned long mode:1; /* RW */ 2437 unsigned long enable:1; /* RW */ 2438 } s3; 2439 }; 2440 2441 /* ========================================================================= */ 2442 /* UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR */ 2443 /* ========================================================================= */ 2444 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL 2445 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL 2446 2447 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30 2448 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46 2449 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52 2450 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 2451 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003fffc0000000UL 2452 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL 2453 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL 2454 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 2455 2456 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 27 2457 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46 2458 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52 2459 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 2460 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff8000000UL 2461 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL 2462 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL 2463 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 2464 2465 union uvh_rh_gam_mmioh_overlay_config_mmr_u { 2466 unsigned long v; 2467 struct uv1h_rh_gam_mmioh_overlay_config_mmr_s { 2468 unsigned long rsvd_0_29:30; 2469 unsigned long base:16; /* RW */ 2470 unsigned long m_io:6; /* RW */ 2471 unsigned long n_io:4; /* RW */ 2472 unsigned long rsvd_56_62:7; 2473 unsigned long enable:1; /* RW */ 2474 } s1; 2475 struct uv2h_rh_gam_mmioh_overlay_config_mmr_s { 2476 unsigned long rsvd_0_26:27; 2477 unsigned long base:19; /* RW */ 2478 unsigned long m_io:6; /* RW */ 2479 unsigned long n_io:4; /* RW */ 2480 unsigned long rsvd_56_62:7; 2481 unsigned long enable:1; /* RW */ 2482 } s2; 2483 }; 2484 2485 /* ========================================================================= */ 2486 /* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */ 2487 /* ========================================================================= */ 2488 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL 2489 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL 2490 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL 2491 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL 2492 2493 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 2494 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 2495 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 2496 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 2497 2498 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 2499 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46 2500 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 2501 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 2502 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL 2503 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 2504 2505 #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 2506 #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 2507 #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 2508 #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 2509 2510 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 2511 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 2512 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 2513 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 2514 2515 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 2516 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 2517 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 2518 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 2519 2520 union uvh_rh_gam_mmr_overlay_config_mmr_u { 2521 unsigned long v; 2522 struct uvh_rh_gam_mmr_overlay_config_mmr_s { 2523 unsigned long rsvd_0_25:26; 2524 unsigned long base:20; /* RW */ 2525 unsigned long rsvd_46_62:17; 2526 unsigned long enable:1; /* RW */ 2527 } s; 2528 struct uv1h_rh_gam_mmr_overlay_config_mmr_s { 2529 unsigned long rsvd_0_25:26; 2530 unsigned long base:20; /* RW */ 2531 unsigned long dual_hub:1; /* RW */ 2532 unsigned long rsvd_47_62:16; 2533 unsigned long enable:1; /* RW */ 2534 } s1; 2535 struct uvxh_rh_gam_mmr_overlay_config_mmr_s { 2536 unsigned long rsvd_0_25:26; 2537 unsigned long base:20; /* RW */ 2538 unsigned long rsvd_46_62:17; 2539 unsigned long enable:1; /* RW */ 2540 } sx; 2541 struct uv2h_rh_gam_mmr_overlay_config_mmr_s { 2542 unsigned long rsvd_0_25:26; 2543 unsigned long base:20; /* RW */ 2544 unsigned long rsvd_46_62:17; 2545 unsigned long enable:1; /* RW */ 2546 } s2; 2547 struct uv3h_rh_gam_mmr_overlay_config_mmr_s { 2548 unsigned long rsvd_0_25:26; 2549 unsigned long base:20; /* RW */ 2550 unsigned long rsvd_46_62:17; 2551 unsigned long enable:1; /* RW */ 2552 } s3; 2553 }; 2554 2555 /* ========================================================================= */ 2556 /* UVH_RTC */ 2557 /* ========================================================================= */ 2558 #define UVH_RTC 0x340000UL 2559 2560 #define UVH_RTC_REAL_TIME_CLOCK_SHFT 0 2561 #define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL 2562 2563 union uvh_rtc_u { 2564 unsigned long v; 2565 struct uvh_rtc_s { 2566 unsigned long real_time_clock:56; /* RW */ 2567 unsigned long rsvd_56_63:8; 2568 } s; 2569 }; 2570 2571 /* ========================================================================= */ 2572 /* UVH_RTC1_INT_CONFIG */ 2573 /* ========================================================================= */ 2574 #define UVH_RTC1_INT_CONFIG 0x615c0UL 2575 2576 #define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0 2577 #define UVH_RTC1_INT_CONFIG_DM_SHFT 8 2578 #define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT 11 2579 #define UVH_RTC1_INT_CONFIG_STATUS_SHFT 12 2580 #define UVH_RTC1_INT_CONFIG_P_SHFT 13 2581 #define UVH_RTC1_INT_CONFIG_T_SHFT 15 2582 #define UVH_RTC1_INT_CONFIG_M_SHFT 16 2583 #define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT 32 2584 #define UVH_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL 2585 #define UVH_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL 2586 #define UVH_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL 2587 #define UVH_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL 2588 #define UVH_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL 2589 #define UVH_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL 2590 #define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL 2591 #define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 2592 2593 union uvh_rtc1_int_config_u { 2594 unsigned long v; 2595 struct uvh_rtc1_int_config_s { 2596 unsigned long vector_:8; /* RW */ 2597 unsigned long dm:3; /* RW */ 2598 unsigned long destmode:1; /* RW */ 2599 unsigned long status:1; /* RO */ 2600 unsigned long p:1; /* RO */ 2601 unsigned long rsvd_14:1; 2602 unsigned long t:1; /* RO */ 2603 unsigned long m:1; /* RW */ 2604 unsigned long rsvd_17_31:15; 2605 unsigned long apic_id:32; /* RW */ 2606 } s; 2607 }; 2608 2609 /* ========================================================================= */ 2610 /* UVH_SCRATCH5 */ 2611 /* ========================================================================= */ 2612 #define UVH_SCRATCH5 0x2d0200UL 2613 #define UVH_SCRATCH5_32 0x778 2614 2615 #define UVH_SCRATCH5_SCRATCH5_SHFT 0 2616 #define UVH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL 2617 2618 union uvh_scratch5_u { 2619 unsigned long v; 2620 struct uvh_scratch5_s { 2621 unsigned long scratch5:64; /* RW, W1CS */ 2622 } s; 2623 }; 2624 2625 /* ========================================================================= */ 2626 /* UVH_SCRATCH5_ALIAS */ 2627 /* ========================================================================= */ 2628 #define UVH_SCRATCH5_ALIAS 0x2d0208UL 2629 #define UVH_SCRATCH5_ALIAS_32 0x780 2630 2631 2632 /* ========================================================================= */ 2633 /* UVH_SCRATCH5_ALIAS_2 */ 2634 /* ========================================================================= */ 2635 #define UVH_SCRATCH5_ALIAS_2 0x2d0210UL 2636 #define UVH_SCRATCH5_ALIAS_2_32 0x788 2637 2638 2639 /* ========================================================================= */ 2640 /* UVXH_EVENT_OCCURRED2 */ 2641 /* ========================================================================= */ 2642 #define UVXH_EVENT_OCCURRED2 0x70100UL 2643 #define UVXH_EVENT_OCCURRED2_32 0xb68 2644 2645 #define UVXH_EVENT_OCCURRED2_RTC_0_SHFT 0 2646 #define UVXH_EVENT_OCCURRED2_RTC_1_SHFT 1 2647 #define UVXH_EVENT_OCCURRED2_RTC_2_SHFT 2 2648 #define UVXH_EVENT_OCCURRED2_RTC_3_SHFT 3 2649 #define UVXH_EVENT_OCCURRED2_RTC_4_SHFT 4 2650 #define UVXH_EVENT_OCCURRED2_RTC_5_SHFT 5 2651 #define UVXH_EVENT_OCCURRED2_RTC_6_SHFT 6 2652 #define UVXH_EVENT_OCCURRED2_RTC_7_SHFT 7 2653 #define UVXH_EVENT_OCCURRED2_RTC_8_SHFT 8 2654 #define UVXH_EVENT_OCCURRED2_RTC_9_SHFT 9 2655 #define UVXH_EVENT_OCCURRED2_RTC_10_SHFT 10 2656 #define UVXH_EVENT_OCCURRED2_RTC_11_SHFT 11 2657 #define UVXH_EVENT_OCCURRED2_RTC_12_SHFT 12 2658 #define UVXH_EVENT_OCCURRED2_RTC_13_SHFT 13 2659 #define UVXH_EVENT_OCCURRED2_RTC_14_SHFT 14 2660 #define UVXH_EVENT_OCCURRED2_RTC_15_SHFT 15 2661 #define UVXH_EVENT_OCCURRED2_RTC_16_SHFT 16 2662 #define UVXH_EVENT_OCCURRED2_RTC_17_SHFT 17 2663 #define UVXH_EVENT_OCCURRED2_RTC_18_SHFT 18 2664 #define UVXH_EVENT_OCCURRED2_RTC_19_SHFT 19 2665 #define UVXH_EVENT_OCCURRED2_RTC_20_SHFT 20 2666 #define UVXH_EVENT_OCCURRED2_RTC_21_SHFT 21 2667 #define UVXH_EVENT_OCCURRED2_RTC_22_SHFT 22 2668 #define UVXH_EVENT_OCCURRED2_RTC_23_SHFT 23 2669 #define UVXH_EVENT_OCCURRED2_RTC_24_SHFT 24 2670 #define UVXH_EVENT_OCCURRED2_RTC_25_SHFT 25 2671 #define UVXH_EVENT_OCCURRED2_RTC_26_SHFT 26 2672 #define UVXH_EVENT_OCCURRED2_RTC_27_SHFT 27 2673 #define UVXH_EVENT_OCCURRED2_RTC_28_SHFT 28 2674 #define UVXH_EVENT_OCCURRED2_RTC_29_SHFT 29 2675 #define UVXH_EVENT_OCCURRED2_RTC_30_SHFT 30 2676 #define UVXH_EVENT_OCCURRED2_RTC_31_SHFT 31 2677 #define UVXH_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL 2678 #define UVXH_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL 2679 #define UVXH_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL 2680 #define UVXH_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL 2681 #define UVXH_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL 2682 #define UVXH_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL 2683 #define UVXH_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL 2684 #define UVXH_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL 2685 #define UVXH_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL 2686 #define UVXH_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL 2687 #define UVXH_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL 2688 #define UVXH_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL 2689 #define UVXH_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL 2690 #define UVXH_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL 2691 #define UVXH_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL 2692 #define UVXH_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL 2693 #define UVXH_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL 2694 #define UVXH_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL 2695 #define UVXH_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL 2696 #define UVXH_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL 2697 #define UVXH_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL 2698 #define UVXH_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL 2699 #define UVXH_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL 2700 #define UVXH_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL 2701 #define UVXH_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL 2702 #define UVXH_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL 2703 #define UVXH_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL 2704 #define UVXH_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL 2705 #define UVXH_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL 2706 #define UVXH_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL 2707 #define UVXH_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL 2708 #define UVXH_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL 2709 2710 union uvxh_event_occurred2_u { 2711 unsigned long v; 2712 struct uvxh_event_occurred2_s { 2713 unsigned long rtc_0:1; /* RW */ 2714 unsigned long rtc_1:1; /* RW */ 2715 unsigned long rtc_2:1; /* RW */ 2716 unsigned long rtc_3:1; /* RW */ 2717 unsigned long rtc_4:1; /* RW */ 2718 unsigned long rtc_5:1; /* RW */ 2719 unsigned long rtc_6:1; /* RW */ 2720 unsigned long rtc_7:1; /* RW */ 2721 unsigned long rtc_8:1; /* RW */ 2722 unsigned long rtc_9:1; /* RW */ 2723 unsigned long rtc_10:1; /* RW */ 2724 unsigned long rtc_11:1; /* RW */ 2725 unsigned long rtc_12:1; /* RW */ 2726 unsigned long rtc_13:1; /* RW */ 2727 unsigned long rtc_14:1; /* RW */ 2728 unsigned long rtc_15:1; /* RW */ 2729 unsigned long rtc_16:1; /* RW */ 2730 unsigned long rtc_17:1; /* RW */ 2731 unsigned long rtc_18:1; /* RW */ 2732 unsigned long rtc_19:1; /* RW */ 2733 unsigned long rtc_20:1; /* RW */ 2734 unsigned long rtc_21:1; /* RW */ 2735 unsigned long rtc_22:1; /* RW */ 2736 unsigned long rtc_23:1; /* RW */ 2737 unsigned long rtc_24:1; /* RW */ 2738 unsigned long rtc_25:1; /* RW */ 2739 unsigned long rtc_26:1; /* RW */ 2740 unsigned long rtc_27:1; /* RW */ 2741 unsigned long rtc_28:1; /* RW */ 2742 unsigned long rtc_29:1; /* RW */ 2743 unsigned long rtc_30:1; /* RW */ 2744 unsigned long rtc_31:1; /* RW */ 2745 unsigned long rsvd_32_63:32; 2746 } sx; 2747 }; 2748 2749 /* ========================================================================= */ 2750 /* UVXH_EVENT_OCCURRED2_ALIAS */ 2751 /* ========================================================================= */ 2752 #define UVXH_EVENT_OCCURRED2_ALIAS 0x70108UL 2753 #define UVXH_EVENT_OCCURRED2_ALIAS_32 0xb70 2754 2755 2756 /* ========================================================================= */ 2757 /* UVXH_LB_BAU_SB_ACTIVATION_STATUS_2 */ 2758 /* ========================================================================= */ 2759 #define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL 2760 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL 2761 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL 2762 #define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0 2763 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x320130UL 2764 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x320130UL 2765 2766 #define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0 2767 #define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL 2768 2769 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0 2770 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL 2771 2772 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0 2773 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL 2774 2775 union uvxh_lb_bau_sb_activation_status_2_u { 2776 unsigned long v; 2777 struct uvxh_lb_bau_sb_activation_status_2_s { 2778 unsigned long aux_error:64; /* RW */ 2779 } sx; 2780 struct uv2h_lb_bau_sb_activation_status_2_s { 2781 unsigned long aux_error:64; /* RW */ 2782 } s2; 2783 struct uv3h_lb_bau_sb_activation_status_2_s { 2784 unsigned long aux_error:64; /* RW */ 2785 } s3; 2786 }; 2787 2788 /* ========================================================================= */ 2789 /* UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK */ 2790 /* ========================================================================= */ 2791 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK 0x320130UL 2792 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_32 0x9f0 2793 2794 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_SHFT 0 2795 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_MASK 0x00000000ffffffffUL 2796 2797 union uv1h_lb_target_physical_apic_id_mask_u { 2798 unsigned long v; 2799 struct uv1h_lb_target_physical_apic_id_mask_s { 2800 unsigned long bit_enables:32; /* RW */ 2801 unsigned long rsvd_32_63:32; 2802 } s1; 2803 }; 2804 2805 /* ========================================================================= */ 2806 /* UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR */ 2807 /* ========================================================================= */ 2808 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR 0x1603000UL 2809 2810 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT 26 2811 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT 46 2812 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_SHFT 63 2813 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK 0x00003ffffc000000UL 2814 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK 0x000fc00000000000UL 2815 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK 0x8000000000000000UL 2816 2817 union uv3h_rh_gam_mmioh_overlay_config0_mmr_u { 2818 unsigned long v; 2819 struct uv3h_rh_gam_mmioh_overlay_config0_mmr_s { 2820 unsigned long rsvd_0_25:26; 2821 unsigned long base:20; /* RW */ 2822 unsigned long m_io:6; /* RW */ 2823 unsigned long n_io:4; 2824 unsigned long rsvd_56_62:7; 2825 unsigned long enable:1; /* RW */ 2826 } s3; 2827 }; 2828 2829 /* ========================================================================= */ 2830 /* UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR */ 2831 /* ========================================================================= */ 2832 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR 0x1604000UL 2833 2834 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_SHFT 26 2835 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT 46 2836 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_SHFT 63 2837 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK 0x00003ffffc000000UL 2838 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK 0x000fc00000000000UL 2839 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_MASK 0x8000000000000000UL 2840 2841 union uv3h_rh_gam_mmioh_overlay_config1_mmr_u { 2842 unsigned long v; 2843 struct uv3h_rh_gam_mmioh_overlay_config1_mmr_s { 2844 unsigned long rsvd_0_25:26; 2845 unsigned long base:20; /* RW */ 2846 unsigned long m_io:6; /* RW */ 2847 unsigned long n_io:4; 2848 unsigned long rsvd_56_62:7; 2849 unsigned long enable:1; /* RW */ 2850 } s3; 2851 }; 2852 2853 /* ========================================================================= */ 2854 /* UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR */ 2855 /* ========================================================================= */ 2856 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR 0x1603800UL 2857 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH 128 2858 2859 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_SHFT 0 2860 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK 0x0000000000007fffUL 2861 2862 union uv3h_rh_gam_mmioh_redirect_config0_mmr_u { 2863 unsigned long v; 2864 struct uv3h_rh_gam_mmioh_redirect_config0_mmr_s { 2865 unsigned long nasid:15; /* RW */ 2866 unsigned long rsvd_15_63:49; 2867 } s3; 2868 }; 2869 2870 /* ========================================================================= */ 2871 /* UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR */ 2872 /* ========================================================================= */ 2873 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR 0x1604800UL 2874 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH 128 2875 2876 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_SHFT 0 2877 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK 0x0000000000007fffUL 2878 2879 union uv3h_rh_gam_mmioh_redirect_config1_mmr_u { 2880 unsigned long v; 2881 struct uv3h_rh_gam_mmioh_redirect_config1_mmr_s { 2882 unsigned long nasid:15; /* RW */ 2883 unsigned long rsvd_15_63:49; 2884 } s3; 2885 }; 2886 2887 2888 #endif /* _ASM_X86_UV_UV_MMRS_H */ 2889