1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * SGI UV MMR definitions 7 * 8 * Copyright (C) 2007-2016 Silicon Graphics, Inc. All rights reserved. 9 */ 10 11 #ifndef _ASM_X86_UV_UV_MMRS_H 12 #define _ASM_X86_UV_UV_MMRS_H 13 14 /* 15 * This file contains MMR definitions for all UV hubs types. 16 * 17 * To minimize coding differences between hub types, the symbols are 18 * grouped by architecture types. 19 * 20 * UVH - definitions common to all UV hub types. 21 * UVXH - definitions common to all UV eXtended hub types (currently 2, 3, 4). 22 * UV2H - definitions specific to UV type 2 hub. 23 * UV3H - definitions specific to UV type 3 hub. 24 * UV4H - definitions specific to UV type 4 hub. 25 * 26 * So in general, MMR addresses and structures are identical on all hubs types. 27 * These MMRs are identified as: 28 * #define UVH_xxx <address> 29 * union uvh_xxx { 30 * unsigned long v; 31 * struct uvh_int_cmpd_s { 32 * } s; 33 * }; 34 * 35 * If the MMR exists on all hub types but have different addresses, 36 * use a conditional operator to define the value at runtime. 37 * #define UV2Hxxx b 38 * #define UV3Hxxx c 39 * #define UV4Hxxx d 40 * #define UV4AHxxx e 41 * #define UVHxxx (is_uv2_hub() ? UV2Hxxx : 42 * (is_uv3_hub() ? UV3Hxxx : 43 * (is_uv4a_hub() ? UV4AHxxx : 44 * UV4Hxxx)) 45 * 46 * union uvh_xxx { 47 * unsigned long v; 48 * struct uvh_xxx_s { # Common fields only 49 * } s; 50 * struct uv2h_xxx_s { # Full UV2 definition (*) 51 * } s2; 52 * struct uv3h_xxx_s { # Full UV3 definition (*) 53 * } s3; 54 * (NOTE: No struct uv4ah_xxx_s members exist) 55 * struct uv4h_xxx_s { # Full UV4 definition (*) 56 * } s4; 57 * }; 58 * (* - if present and different than the common struct) 59 * 60 * Only essential differences are enumerated. For example, if the address is 61 * the same for all UV's, only a single #define is generated. Likewise, 62 * if the contents is the same for all hubs, only the "s" structure is 63 * generated. 64 * 65 * If the MMR exists on ONLY 1 type of hub, no generic definition is 66 * generated: 67 * #define UVnH_xxx <uvn address> 68 * union uvnh_xxx { 69 * unsigned long v; 70 * struct uvh_int_cmpd_s { 71 * } sn; 72 * }; 73 * 74 * (GEN Flags: mflags_opt= undefs=function UV234=UVXH) 75 */ 76 77 #define UV_MMR_ENABLE (1UL << 63) 78 79 #define UV2_HUB_PART_NUMBER 0x8eb8 80 #define UV2_HUB_PART_NUMBER_X 0x1111 81 #define UV3_HUB_PART_NUMBER 0x9578 82 #define UV3_HUB_PART_NUMBER_X 0x4321 83 #define UV4_HUB_PART_NUMBER 0x99a1 84 85 /* Error function to catch undefined references */ 86 extern unsigned long uv_undefined(char *str); 87 88 /* ========================================================================= */ 89 /* UVH_BAU_DATA_BROADCAST */ 90 /* ========================================================================= */ 91 #define UVH_BAU_DATA_BROADCAST 0x61688UL 92 93 #define UV2H_BAU_DATA_BROADCAST_32 0x440 94 #define UV3H_BAU_DATA_BROADCAST_32 0x440 95 #define UV4H_BAU_DATA_BROADCAST_32 0x360 96 #define UVH_BAU_DATA_BROADCAST_32 ( \ 97 is_uv2_hub() ? UV2H_BAU_DATA_BROADCAST_32 : \ 98 is_uv3_hub() ? UV3H_BAU_DATA_BROADCAST_32 : \ 99 /*is_uv4_hub*/ UV4H_BAU_DATA_BROADCAST_32) 100 101 #define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT 0 102 #define UVH_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL 103 104 105 union uvh_bau_data_broadcast_u { 106 unsigned long v; 107 struct uvh_bau_data_broadcast_s { 108 unsigned long enable:1; /* RW */ 109 unsigned long rsvd_1_63:63; 110 } s; 111 }; 112 113 /* ========================================================================= */ 114 /* UVH_BAU_DATA_CONFIG */ 115 /* ========================================================================= */ 116 #define UVH_BAU_DATA_CONFIG 0x61680UL 117 118 #define UV2H_BAU_DATA_CONFIG_32 0x438 119 #define UV3H_BAU_DATA_CONFIG_32 0x438 120 #define UV4H_BAU_DATA_CONFIG_32 0x358 121 #define UVH_BAU_DATA_CONFIG_32 ( \ 122 is_uv2_hub() ? UV2H_BAU_DATA_CONFIG_32 : \ 123 is_uv3_hub() ? UV3H_BAU_DATA_CONFIG_32 : \ 124 /*is_uv4_hub*/ UV4H_BAU_DATA_CONFIG_32) 125 126 #define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0 127 #define UVH_BAU_DATA_CONFIG_DM_SHFT 8 128 #define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT 11 129 #define UVH_BAU_DATA_CONFIG_STATUS_SHFT 12 130 #define UVH_BAU_DATA_CONFIG_P_SHFT 13 131 #define UVH_BAU_DATA_CONFIG_T_SHFT 15 132 #define UVH_BAU_DATA_CONFIG_M_SHFT 16 133 #define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT 32 134 #define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL 135 #define UVH_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL 136 #define UVH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL 137 #define UVH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL 138 #define UVH_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL 139 #define UVH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL 140 #define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL 141 #define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 142 143 144 union uvh_bau_data_config_u { 145 unsigned long v; 146 struct uvh_bau_data_config_s { 147 unsigned long vector_:8; /* RW */ 148 unsigned long dm:3; /* RW */ 149 unsigned long destmode:1; /* RW */ 150 unsigned long status:1; /* RO */ 151 unsigned long p:1; /* RO */ 152 unsigned long rsvd_14:1; 153 unsigned long t:1; /* RO */ 154 unsigned long m:1; /* RW */ 155 unsigned long rsvd_17_31:15; 156 unsigned long apic_id:32; /* RW */ 157 } s; 158 }; 159 160 /* ========================================================================= */ 161 /* UVH_EVENT_OCCURRED0 */ 162 /* ========================================================================= */ 163 #define UVH_EVENT_OCCURRED0 0x70000UL 164 #define UVH_EVENT_OCCURRED0_32 0x5e8 165 166 #define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT 0 167 #define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT 11 168 #define UVH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL 169 #define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL 170 171 #define UVXH_EVENT_OCCURRED0_RH_HCERR_SHFT 2 172 #define UVXH_EVENT_OCCURRED0_LH0_HCERR_SHFT 3 173 #define UVXH_EVENT_OCCURRED0_LH1_HCERR_SHFT 4 174 #define UVXH_EVENT_OCCURRED0_GR0_HCERR_SHFT 5 175 #define UVXH_EVENT_OCCURRED0_GR1_HCERR_SHFT 6 176 #define UVXH_EVENT_OCCURRED0_NI0_HCERR_SHFT 7 177 #define UVXH_EVENT_OCCURRED0_NI1_HCERR_SHFT 8 178 #define UVXH_EVENT_OCCURRED0_LB_AOERR0_SHFT 9 179 #define UVXH_EVENT_OCCURRED0_LH0_AOERR0_SHFT 12 180 #define UVXH_EVENT_OCCURRED0_LH1_AOERR0_SHFT 13 181 #define UVXH_EVENT_OCCURRED0_GR0_AOERR0_SHFT 14 182 #define UVXH_EVENT_OCCURRED0_GR1_AOERR0_SHFT 15 183 #define UVXH_EVENT_OCCURRED0_XB_AOERR0_SHFT 16 184 #define UVXH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000004UL 185 #define UVXH_EVENT_OCCURRED0_LH0_HCERR_MASK 0x0000000000000008UL 186 #define UVXH_EVENT_OCCURRED0_LH1_HCERR_MASK 0x0000000000000010UL 187 #define UVXH_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000020UL 188 #define UVXH_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000040UL 189 #define UVXH_EVENT_OCCURRED0_NI0_HCERR_MASK 0x0000000000000080UL 190 #define UVXH_EVENT_OCCURRED0_NI1_HCERR_MASK 0x0000000000000100UL 191 #define UVXH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000200UL 192 #define UVXH_EVENT_OCCURRED0_LH0_AOERR0_MASK 0x0000000000001000UL 193 #define UVXH_EVENT_OCCURRED0_LH1_AOERR0_MASK 0x0000000000002000UL 194 #define UVXH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000004000UL 195 #define UVXH_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000008000UL 196 #define UVXH_EVENT_OCCURRED0_XB_AOERR0_MASK 0x0000000000010000UL 197 198 #define UV2H_EVENT_OCCURRED0_QP_HCERR_SHFT 1 199 #define UV2H_EVENT_OCCURRED0_QP_AOERR0_SHFT 10 200 #define UV2H_EVENT_OCCURRED0_RT_AOERR0_SHFT 17 201 #define UV2H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18 202 #define UV2H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19 203 #define UV2H_EVENT_OCCURRED0_LB_AOERR1_SHFT 20 204 #define UV2H_EVENT_OCCURRED0_QP_AOERR1_SHFT 21 205 #define UV2H_EVENT_OCCURRED0_RH_AOERR1_SHFT 22 206 #define UV2H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23 207 #define UV2H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24 208 #define UV2H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25 209 #define UV2H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26 210 #define UV2H_EVENT_OCCURRED0_XB_AOERR1_SHFT 27 211 #define UV2H_EVENT_OCCURRED0_RT_AOERR1_SHFT 28 212 #define UV2H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29 213 #define UV2H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30 214 #define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31 215 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32 216 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33 217 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34 218 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35 219 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36 220 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37 221 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38 222 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39 223 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40 224 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41 225 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42 226 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43 227 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44 228 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45 229 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46 230 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47 231 #define UV2H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48 232 #define UV2H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49 233 #define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50 234 #define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51 235 #define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52 236 #define UV2H_EVENT_OCCURRED0_IPI_INT_SHFT 53 237 #define UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54 238 #define UV2H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55 239 #define UV2H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56 240 #define UV2H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57 241 #define UV2H_EVENT_OCCURRED0_PROFILE_INT_SHFT 58 242 #define UV2H_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL 243 #define UV2H_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL 244 #define UV2H_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL 245 #define UV2H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL 246 #define UV2H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL 247 #define UV2H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL 248 #define UV2H_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL 249 #define UV2H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL 250 #define UV2H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL 251 #define UV2H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL 252 #define UV2H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL 253 #define UV2H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL 254 #define UV2H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL 255 #define UV2H_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL 256 #define UV2H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL 257 #define UV2H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL 258 #define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL 259 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL 260 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL 261 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL 262 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL 263 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL 264 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL 265 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL 266 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL 267 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL 268 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL 269 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL 270 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL 271 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL 272 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL 273 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL 274 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL 275 #define UV2H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL 276 #define UV2H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL 277 #define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL 278 #define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL 279 #define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL 280 #define UV2H_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL 281 #define UV2H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL 282 #define UV2H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL 283 #define UV2H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL 284 #define UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL 285 #define UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL 286 287 #define UV3H_EVENT_OCCURRED0_QP_HCERR_SHFT 1 288 #define UV3H_EVENT_OCCURRED0_QP_AOERR0_SHFT 10 289 #define UV3H_EVENT_OCCURRED0_RT_AOERR0_SHFT 17 290 #define UV3H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18 291 #define UV3H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19 292 #define UV3H_EVENT_OCCURRED0_LB_AOERR1_SHFT 20 293 #define UV3H_EVENT_OCCURRED0_QP_AOERR1_SHFT 21 294 #define UV3H_EVENT_OCCURRED0_RH_AOERR1_SHFT 22 295 #define UV3H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23 296 #define UV3H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24 297 #define UV3H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25 298 #define UV3H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26 299 #define UV3H_EVENT_OCCURRED0_XB_AOERR1_SHFT 27 300 #define UV3H_EVENT_OCCURRED0_RT_AOERR1_SHFT 28 301 #define UV3H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29 302 #define UV3H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30 303 #define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31 304 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32 305 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33 306 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34 307 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35 308 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36 309 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37 310 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38 311 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39 312 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40 313 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41 314 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42 315 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43 316 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44 317 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45 318 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46 319 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47 320 #define UV3H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48 321 #define UV3H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49 322 #define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50 323 #define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51 324 #define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52 325 #define UV3H_EVENT_OCCURRED0_IPI_INT_SHFT 53 326 #define UV3H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54 327 #define UV3H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55 328 #define UV3H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56 329 #define UV3H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57 330 #define UV3H_EVENT_OCCURRED0_PROFILE_INT_SHFT 58 331 #define UV3H_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL 332 #define UV3H_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL 333 #define UV3H_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL 334 #define UV3H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL 335 #define UV3H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL 336 #define UV3H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL 337 #define UV3H_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL 338 #define UV3H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL 339 #define UV3H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL 340 #define UV3H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL 341 #define UV3H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL 342 #define UV3H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL 343 #define UV3H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL 344 #define UV3H_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL 345 #define UV3H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL 346 #define UV3H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL 347 #define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL 348 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL 349 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL 350 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL 351 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL 352 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL 353 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL 354 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL 355 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL 356 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL 357 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL 358 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL 359 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL 360 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL 361 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL 362 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL 363 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL 364 #define UV3H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL 365 #define UV3H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL 366 #define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL 367 #define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL 368 #define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL 369 #define UV3H_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL 370 #define UV3H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL 371 #define UV3H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL 372 #define UV3H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL 373 #define UV3H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL 374 #define UV3H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL 375 376 #define UV4H_EVENT_OCCURRED0_KT_HCERR_SHFT 1 377 #define UV4H_EVENT_OCCURRED0_KT_AOERR0_SHFT 10 378 #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR0_SHFT 17 379 #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR0_SHFT 18 380 #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR0_SHFT 19 381 #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR0_SHFT 20 382 #define UV4H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 21 383 #define UV4H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 22 384 #define UV4H_EVENT_OCCURRED0_LB_AOERR1_SHFT 23 385 #define UV4H_EVENT_OCCURRED0_KT_AOERR1_SHFT 24 386 #define UV4H_EVENT_OCCURRED0_RH_AOERR1_SHFT 25 387 #define UV4H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 26 388 #define UV4H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 27 389 #define UV4H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 28 390 #define UV4H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 29 391 #define UV4H_EVENT_OCCURRED0_XB_AOERR1_SHFT 30 392 #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR1_SHFT 31 393 #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR1_SHFT 32 394 #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR1_SHFT 33 395 #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR1_SHFT 34 396 #define UV4H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 35 397 #define UV4H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 36 398 #define UV4H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 37 399 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 38 400 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 39 401 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 40 402 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 41 403 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 42 404 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 43 405 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 44 406 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 45 407 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 46 408 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 47 409 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 48 410 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 49 411 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 50 412 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 51 413 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 52 414 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 53 415 #define UV4H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 54 416 #define UV4H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 55 417 #define UV4H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 56 418 #define UV4H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 57 419 #define UV4H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 58 420 #define UV4H_EVENT_OCCURRED0_IPI_INT_SHFT 59 421 #define UV4H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 60 422 #define UV4H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 61 423 #define UV4H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 62 424 #define UV4H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 63 425 #define UV4H_EVENT_OCCURRED0_KT_HCERR_MASK 0x0000000000000002UL 426 #define UV4H_EVENT_OCCURRED0_KT_AOERR0_MASK 0x0000000000000400UL 427 #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR0_MASK 0x0000000000020000UL 428 #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR0_MASK 0x0000000000040000UL 429 #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR0_MASK 0x0000000000080000UL 430 #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR0_MASK 0x0000000000100000UL 431 #define UV4H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000200000UL 432 #define UV4H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000400000UL 433 #define UV4H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000800000UL 434 #define UV4H_EVENT_OCCURRED0_KT_AOERR1_MASK 0x0000000001000000UL 435 #define UV4H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000002000000UL 436 #define UV4H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000004000000UL 437 #define UV4H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000008000000UL 438 #define UV4H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000010000000UL 439 #define UV4H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000020000000UL 440 #define UV4H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000040000000UL 441 #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR1_MASK 0x0000000080000000UL 442 #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR1_MASK 0x0000000100000000UL 443 #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR1_MASK 0x0000000200000000UL 444 #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR1_MASK 0x0000000400000000UL 445 #define UV4H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000800000000UL 446 #define UV4H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000001000000000UL 447 #define UV4H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000002000000000UL 448 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000004000000000UL 449 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000008000000000UL 450 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000010000000000UL 451 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000020000000000UL 452 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000040000000000UL 453 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000080000000000UL 454 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000100000000000UL 455 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000200000000000UL 456 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000400000000000UL 457 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000800000000000UL 458 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0001000000000000UL 459 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0002000000000000UL 460 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0004000000000000UL 461 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0008000000000000UL 462 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0010000000000000UL 463 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0020000000000000UL 464 #define UV4H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0040000000000000UL 465 #define UV4H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0080000000000000UL 466 #define UV4H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0100000000000000UL 467 #define UV4H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0200000000000000UL 468 #define UV4H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0400000000000000UL 469 #define UV4H_EVENT_OCCURRED0_IPI_INT_MASK 0x0800000000000000UL 470 #define UV4H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x1000000000000000UL 471 #define UV4H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x2000000000000000UL 472 #define UV4H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x4000000000000000UL 473 #define UV4H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x8000000000000000UL 474 475 #define UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT ( \ 476 is_uv2_hub() ? UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT : \ 477 is_uv3_hub() ? UV3H_EVENT_OCCURRED0_EXTIO_INT0_SHFT : \ 478 /*is_uv4_hub*/ UV4H_EVENT_OCCURRED0_EXTIO_INT0_SHFT) 479 480 union uvh_event_occurred0_u { 481 unsigned long v; 482 struct uvh_event_occurred0_s { 483 unsigned long lb_hcerr:1; /* RW, W1C */ 484 unsigned long rsvd_1_10:10; 485 unsigned long rh_aoerr0:1; /* RW, W1C */ 486 unsigned long rsvd_12_63:52; 487 } s; 488 struct uvxh_event_occurred0_s { 489 unsigned long lb_hcerr:1; /* RW */ 490 unsigned long rsvd_1:1; 491 unsigned long rh_hcerr:1; /* RW */ 492 unsigned long lh0_hcerr:1; /* RW */ 493 unsigned long lh1_hcerr:1; /* RW */ 494 unsigned long gr0_hcerr:1; /* RW */ 495 unsigned long gr1_hcerr:1; /* RW */ 496 unsigned long ni0_hcerr:1; /* RW */ 497 unsigned long ni1_hcerr:1; /* RW */ 498 unsigned long lb_aoerr0:1; /* RW */ 499 unsigned long rsvd_10:1; 500 unsigned long rh_aoerr0:1; /* RW */ 501 unsigned long lh0_aoerr0:1; /* RW */ 502 unsigned long lh1_aoerr0:1; /* RW */ 503 unsigned long gr0_aoerr0:1; /* RW */ 504 unsigned long gr1_aoerr0:1; /* RW */ 505 unsigned long xb_aoerr0:1; /* RW */ 506 unsigned long rsvd_17_63:47; 507 } sx; 508 struct uv4h_event_occurred0_s { 509 unsigned long lb_hcerr:1; /* RW */ 510 unsigned long kt_hcerr:1; /* RW */ 511 unsigned long rh_hcerr:1; /* RW */ 512 unsigned long lh0_hcerr:1; /* RW */ 513 unsigned long lh1_hcerr:1; /* RW */ 514 unsigned long gr0_hcerr:1; /* RW */ 515 unsigned long gr1_hcerr:1; /* RW */ 516 unsigned long ni0_hcerr:1; /* RW */ 517 unsigned long ni1_hcerr:1; /* RW */ 518 unsigned long lb_aoerr0:1; /* RW */ 519 unsigned long kt_aoerr0:1; /* RW */ 520 unsigned long rh_aoerr0:1; /* RW */ 521 unsigned long lh0_aoerr0:1; /* RW */ 522 unsigned long lh1_aoerr0:1; /* RW */ 523 unsigned long gr0_aoerr0:1; /* RW */ 524 unsigned long gr1_aoerr0:1; /* RW */ 525 unsigned long xb_aoerr0:1; /* RW */ 526 unsigned long rtq0_aoerr0:1; /* RW */ 527 unsigned long rtq1_aoerr0:1; /* RW */ 528 unsigned long rtq2_aoerr0:1; /* RW */ 529 unsigned long rtq3_aoerr0:1; /* RW */ 530 unsigned long ni0_aoerr0:1; /* RW */ 531 unsigned long ni1_aoerr0:1; /* RW */ 532 unsigned long lb_aoerr1:1; /* RW */ 533 unsigned long kt_aoerr1:1; /* RW */ 534 unsigned long rh_aoerr1:1; /* RW */ 535 unsigned long lh0_aoerr1:1; /* RW */ 536 unsigned long lh1_aoerr1:1; /* RW */ 537 unsigned long gr0_aoerr1:1; /* RW */ 538 unsigned long gr1_aoerr1:1; /* RW */ 539 unsigned long xb_aoerr1:1; /* RW */ 540 unsigned long rtq0_aoerr1:1; /* RW */ 541 unsigned long rtq1_aoerr1:1; /* RW */ 542 unsigned long rtq2_aoerr1:1; /* RW */ 543 unsigned long rtq3_aoerr1:1; /* RW */ 544 unsigned long ni0_aoerr1:1; /* RW */ 545 unsigned long ni1_aoerr1:1; /* RW */ 546 unsigned long system_shutdown_int:1; /* RW */ 547 unsigned long lb_irq_int_0:1; /* RW */ 548 unsigned long lb_irq_int_1:1; /* RW */ 549 unsigned long lb_irq_int_2:1; /* RW */ 550 unsigned long lb_irq_int_3:1; /* RW */ 551 unsigned long lb_irq_int_4:1; /* RW */ 552 unsigned long lb_irq_int_5:1; /* RW */ 553 unsigned long lb_irq_int_6:1; /* RW */ 554 unsigned long lb_irq_int_7:1; /* RW */ 555 unsigned long lb_irq_int_8:1; /* RW */ 556 unsigned long lb_irq_int_9:1; /* RW */ 557 unsigned long lb_irq_int_10:1; /* RW */ 558 unsigned long lb_irq_int_11:1; /* RW */ 559 unsigned long lb_irq_int_12:1; /* RW */ 560 unsigned long lb_irq_int_13:1; /* RW */ 561 unsigned long lb_irq_int_14:1; /* RW */ 562 unsigned long lb_irq_int_15:1; /* RW */ 563 unsigned long l1_nmi_int:1; /* RW */ 564 unsigned long stop_clock:1; /* RW */ 565 unsigned long asic_to_l1:1; /* RW */ 566 unsigned long l1_to_asic:1; /* RW */ 567 unsigned long la_seq_trigger:1; /* RW */ 568 unsigned long ipi_int:1; /* RW */ 569 unsigned long extio_int0:1; /* RW */ 570 unsigned long extio_int1:1; /* RW */ 571 unsigned long extio_int2:1; /* RW */ 572 unsigned long extio_int3:1; /* RW */ 573 } s4; 574 }; 575 576 /* ========================================================================= */ 577 /* UVH_EVENT_OCCURRED0_ALIAS */ 578 /* ========================================================================= */ 579 #define UVH_EVENT_OCCURRED0_ALIAS 0x70008UL 580 #define UVH_EVENT_OCCURRED0_ALIAS_32 0x5f0 581 582 583 /* ========================================================================= */ 584 /* UVH_EXTIO_INT0_BROADCAST */ 585 /* ========================================================================= */ 586 #define UVH_EXTIO_INT0_BROADCAST 0x61448UL 587 588 #define UV2H_EXTIO_INT0_BROADCAST_32 0x3f0 589 #define UV3H_EXTIO_INT0_BROADCAST_32 0x3f0 590 #define UV4H_EXTIO_INT0_BROADCAST_32 0x310 591 #define UVH_EXTIO_INT0_BROADCAST_32 ( \ 592 is_uv2_hub() ? UV2H_EXTIO_INT0_BROADCAST_32 : \ 593 is_uv3_hub() ? UV3H_EXTIO_INT0_BROADCAST_32 : \ 594 /*is_uv4_hub*/ UV4H_EXTIO_INT0_BROADCAST_32) 595 596 #define UVH_EXTIO_INT0_BROADCAST_ENABLE_SHFT 0 597 #define UVH_EXTIO_INT0_BROADCAST_ENABLE_MASK 0x0000000000000001UL 598 599 600 union uvh_extio_int0_broadcast_u { 601 unsigned long v; 602 struct uvh_extio_int0_broadcast_s { 603 unsigned long enable:1; /* RW */ 604 unsigned long rsvd_1_63:63; 605 } s; 606 }; 607 608 /* ========================================================================= */ 609 /* UVH_GR0_TLB_INT0_CONFIG */ 610 /* ========================================================================= */ 611 #define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL 612 613 #define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0 614 #define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT 8 615 #define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11 616 #define UVH_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12 617 #define UVH_GR0_TLB_INT0_CONFIG_P_SHFT 13 618 #define UVH_GR0_TLB_INT0_CONFIG_T_SHFT 15 619 #define UVH_GR0_TLB_INT0_CONFIG_M_SHFT 16 620 #define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32 621 #define UVH_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL 622 #define UVH_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL 623 #define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL 624 #define UVH_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL 625 #define UVH_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL 626 #define UVH_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL 627 #define UVH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL 628 #define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 629 630 631 union uvh_gr0_tlb_int0_config_u { 632 unsigned long v; 633 struct uvh_gr0_tlb_int0_config_s { 634 unsigned long vector_:8; /* RW */ 635 unsigned long dm:3; /* RW */ 636 unsigned long destmode:1; /* RW */ 637 unsigned long status:1; /* RO */ 638 unsigned long p:1; /* RO */ 639 unsigned long rsvd_14:1; 640 unsigned long t:1; /* RO */ 641 unsigned long m:1; /* RW */ 642 unsigned long rsvd_17_31:15; 643 unsigned long apic_id:32; /* RW */ 644 } s; 645 }; 646 647 /* ========================================================================= */ 648 /* UVH_GR0_TLB_INT1_CONFIG */ 649 /* ========================================================================= */ 650 #define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL 651 652 #define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0 653 #define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT 8 654 #define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT 11 655 #define UVH_GR0_TLB_INT1_CONFIG_STATUS_SHFT 12 656 #define UVH_GR0_TLB_INT1_CONFIG_P_SHFT 13 657 #define UVH_GR0_TLB_INT1_CONFIG_T_SHFT 15 658 #define UVH_GR0_TLB_INT1_CONFIG_M_SHFT 16 659 #define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT 32 660 #define UVH_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL 661 #define UVH_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL 662 #define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL 663 #define UVH_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL 664 #define UVH_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL 665 #define UVH_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL 666 #define UVH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL 667 #define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 668 669 670 union uvh_gr0_tlb_int1_config_u { 671 unsigned long v; 672 struct uvh_gr0_tlb_int1_config_s { 673 unsigned long vector_:8; /* RW */ 674 unsigned long dm:3; /* RW */ 675 unsigned long destmode:1; /* RW */ 676 unsigned long status:1; /* RO */ 677 unsigned long p:1; /* RO */ 678 unsigned long rsvd_14:1; 679 unsigned long t:1; /* RO */ 680 unsigned long m:1; /* RW */ 681 unsigned long rsvd_17_31:15; 682 unsigned long apic_id:32; /* RW */ 683 } s; 684 }; 685 686 /* ========================================================================= */ 687 /* UVH_GR0_TLB_MMR_CONTROL */ 688 /* ========================================================================= */ 689 #define UV2H_GR0_TLB_MMR_CONTROL 0xc01080UL 690 #define UV3H_GR0_TLB_MMR_CONTROL 0xc01080UL 691 #define UV4H_GR0_TLB_MMR_CONTROL 0x601080UL 692 #define UVH_GR0_TLB_MMR_CONTROL ( \ 693 is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL : \ 694 is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL : \ 695 /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL) 696 697 #define UVH_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 698 #define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 699 #define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 700 #define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 701 #define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31 702 #define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 703 #define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 704 #define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 705 #define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 706 707 #define UVXH_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 708 #define UVXH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 709 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 710 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 711 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31 712 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 713 #define UVXH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 714 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 715 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 716 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 717 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 718 719 #define UV2H_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 720 #define UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 721 #define UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 722 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 723 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 724 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31 725 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 726 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT 48 727 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT 52 728 #define UV2H_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL 729 #define UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL 730 #define UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 731 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 732 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 733 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 734 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 735 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL 736 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL 737 738 #define UV3H_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 739 #define UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 740 #define UV3H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 741 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 742 #define UV3H_GR0_TLB_MMR_CONTROL_ECC_SEL_SHFT 21 743 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 744 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31 745 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 746 #define UV3H_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL 747 #define UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL 748 #define UV3H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 749 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 750 #define UV3H_GR0_TLB_MMR_CONTROL_ECC_SEL_MASK 0x0000000000200000UL 751 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 752 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 753 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 754 755 #define UV4H_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 756 #define UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 13 757 #define UV4H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 758 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 759 #define UV4H_GR0_TLB_MMR_CONTROL_ECC_SEL_SHFT 21 760 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 761 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31 762 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 763 #define UV4H_GR0_TLB_MMR_CONTROL_PAGE_SIZE_SHFT 59 764 #define UV4H_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000001fffUL 765 #define UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000006000UL 766 #define UV4H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 767 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 768 #define UV4H_GR0_TLB_MMR_CONTROL_ECC_SEL_MASK 0x0000000000200000UL 769 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 770 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 771 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 772 #define UV4H_GR0_TLB_MMR_CONTROL_PAGE_SIZE_MASK 0xf800000000000000UL 773 774 #define UVH_GR0_TLB_MMR_CONTROL_INDEX_MASK ( \ 775 is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL_INDEX_MASK : \ 776 is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL_INDEX_MASK : \ 777 /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL_INDEX_MASK) 778 #define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK ( \ 779 is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK : \ 780 is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK : \ 781 /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK) 782 #define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT ( \ 783 is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT : \ 784 is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT : \ 785 /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT) 786 787 union uvh_gr0_tlb_mmr_control_u { 788 unsigned long v; 789 struct uvh_gr0_tlb_mmr_control_s { 790 unsigned long rsvd_0_15:16; 791 unsigned long auto_valid_en:1; /* RW */ 792 unsigned long rsvd_17_19:3; 793 unsigned long mmr_hash_index_en:1; /* RW */ 794 unsigned long rsvd_21_29:9; 795 unsigned long mmr_write:1; /* WP */ 796 unsigned long mmr_read:1; /* WP */ 797 unsigned long rsvd_32_48:17; 798 unsigned long rsvd_49_51:3; 799 unsigned long rsvd_52_63:12; 800 } s; 801 struct uvxh_gr0_tlb_mmr_control_s { 802 unsigned long rsvd_0_15:16; 803 unsigned long auto_valid_en:1; /* RW */ 804 unsigned long rsvd_17_19:3; 805 unsigned long mmr_hash_index_en:1; /* RW */ 806 unsigned long rsvd_21_29:9; 807 unsigned long mmr_write:1; /* WP */ 808 unsigned long mmr_read:1; /* WP */ 809 unsigned long mmr_op_done:1; /* RW */ 810 unsigned long rsvd_33_47:15; 811 unsigned long rsvd_48:1; 812 unsigned long rsvd_49_51:3; 813 unsigned long rsvd_52_63:12; 814 } sx; 815 struct uv2h_gr0_tlb_mmr_control_s { 816 unsigned long index:12; /* RW */ 817 unsigned long mem_sel:2; /* RW */ 818 unsigned long rsvd_14_15:2; 819 unsigned long auto_valid_en:1; /* RW */ 820 unsigned long rsvd_17_19:3; 821 unsigned long mmr_hash_index_en:1; /* RW */ 822 unsigned long rsvd_21_29:9; 823 unsigned long mmr_write:1; /* WP */ 824 unsigned long mmr_read:1; /* WP */ 825 unsigned long mmr_op_done:1; /* RW */ 826 unsigned long rsvd_33_47:15; 827 unsigned long mmr_inj_con:1; /* RW */ 828 unsigned long rsvd_49_51:3; 829 unsigned long mmr_inj_tlbram:1; /* RW */ 830 unsigned long rsvd_53_63:11; 831 } s2; 832 struct uv3h_gr0_tlb_mmr_control_s { 833 unsigned long index:12; /* RW */ 834 unsigned long mem_sel:2; /* RW */ 835 unsigned long rsvd_14_15:2; 836 unsigned long auto_valid_en:1; /* RW */ 837 unsigned long rsvd_17_19:3; 838 unsigned long mmr_hash_index_en:1; /* RW */ 839 unsigned long ecc_sel:1; /* RW */ 840 unsigned long rsvd_22_29:8; 841 unsigned long mmr_write:1; /* WP */ 842 unsigned long mmr_read:1; /* WP */ 843 unsigned long mmr_op_done:1; /* RW */ 844 unsigned long rsvd_33_47:15; 845 unsigned long undef_48:1; /* Undefined */ 846 unsigned long rsvd_49_51:3; 847 unsigned long undef_52:1; /* Undefined */ 848 unsigned long rsvd_53_63:11; 849 } s3; 850 struct uv4h_gr0_tlb_mmr_control_s { 851 unsigned long index:13; /* RW */ 852 unsigned long mem_sel:2; /* RW */ 853 unsigned long rsvd_15:1; 854 unsigned long auto_valid_en:1; /* RW */ 855 unsigned long rsvd_17_19:3; 856 unsigned long mmr_hash_index_en:1; /* RW */ 857 unsigned long ecc_sel:1; /* RW */ 858 unsigned long rsvd_22_29:8; 859 unsigned long mmr_write:1; /* WP */ 860 unsigned long mmr_read:1; /* WP */ 861 unsigned long mmr_op_done:1; /* RW */ 862 unsigned long rsvd_33_47:15; 863 unsigned long undef_48:1; /* Undefined */ 864 unsigned long rsvd_49_51:3; 865 unsigned long rsvd_52_58:7; 866 unsigned long page_size:5; /* RW */ 867 } s4; 868 }; 869 870 /* ========================================================================= */ 871 /* UVH_GR0_TLB_MMR_READ_DATA_HI */ 872 /* ========================================================================= */ 873 #define UV2H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL 874 #define UV3H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL 875 #define UV4H_GR0_TLB_MMR_READ_DATA_HI 0x6010a0UL 876 #define UVH_GR0_TLB_MMR_READ_DATA_HI ( \ 877 is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_HI : \ 878 is_uv3_hub() ? UV3H_GR0_TLB_MMR_READ_DATA_HI : \ 879 /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_READ_DATA_HI) 880 881 #define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 882 883 #define UVXH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 884 885 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 886 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 887 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 888 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 889 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL 890 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL 891 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL 892 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 893 894 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 895 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 896 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 897 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 898 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT 45 899 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT 55 900 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL 901 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL 902 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL 903 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 904 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_MASK 0x0000200000000000UL 905 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK 0xff80000000000000UL 906 907 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 908 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_PNID_SHFT 34 909 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 49 910 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 51 911 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT 52 912 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT 53 913 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT 55 914 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK 0x00000003ffffffffUL 915 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_PNID_MASK 0x0001fffc00000000UL 916 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0006000000000000UL 917 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0008000000000000UL 918 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0010000000000000UL 919 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_MASK 0x0020000000000000UL 920 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK 0xff80000000000000UL 921 922 923 union uvh_gr0_tlb_mmr_read_data_hi_u { 924 unsigned long v; 925 struct uv2h_gr0_tlb_mmr_read_data_hi_s { 926 unsigned long pfn:41; /* RO */ 927 unsigned long gaa:2; /* RO */ 928 unsigned long dirty:1; /* RO */ 929 unsigned long larger:1; /* RO */ 930 unsigned long rsvd_45_63:19; 931 } s2; 932 struct uv3h_gr0_tlb_mmr_read_data_hi_s { 933 unsigned long pfn:41; /* RO */ 934 unsigned long gaa:2; /* RO */ 935 unsigned long dirty:1; /* RO */ 936 unsigned long larger:1; /* RO */ 937 unsigned long aa_ext:1; /* RO */ 938 unsigned long undef_46_54:9; /* Undefined */ 939 unsigned long way_ecc:9; /* RO */ 940 } s3; 941 struct uv4h_gr0_tlb_mmr_read_data_hi_s { 942 unsigned long pfn:34; /* RO */ 943 unsigned long pnid:15; /* RO */ 944 unsigned long gaa:2; /* RO */ 945 unsigned long dirty:1; /* RO */ 946 unsigned long larger:1; /* RO */ 947 unsigned long aa_ext:1; /* RO */ 948 unsigned long undef_54:1; /* Undefined */ 949 unsigned long way_ecc:9; /* RO */ 950 } s4; 951 }; 952 953 /* ========================================================================= */ 954 /* UVH_GR0_TLB_MMR_READ_DATA_LO */ 955 /* ========================================================================= */ 956 #define UV2H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL 957 #define UV3H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL 958 #define UV4H_GR0_TLB_MMR_READ_DATA_LO 0x6010a8UL 959 #define UVH_GR0_TLB_MMR_READ_DATA_LO ( \ 960 is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_LO : \ 961 is_uv3_hub() ? UV3H_GR0_TLB_MMR_READ_DATA_LO : \ 962 /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_READ_DATA_LO) 963 964 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 965 #define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 966 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 967 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 968 #define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 969 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 970 971 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 972 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 973 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 974 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 975 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 976 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 977 978 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 979 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 980 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 981 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 982 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 983 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 984 985 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 986 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 987 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 988 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 989 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 990 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 991 992 #define UV4H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 993 #define UV4H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 994 #define UV4H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 995 #define UV4H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 996 #define UV4H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 997 #define UV4H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 998 999 1000 union uvh_gr0_tlb_mmr_read_data_lo_u { 1001 unsigned long v; 1002 struct uvh_gr0_tlb_mmr_read_data_lo_s { 1003 unsigned long vpn:39; /* RO */ 1004 unsigned long asid:24; /* RO */ 1005 unsigned long valid:1; /* RO */ 1006 } s; 1007 struct uvxh_gr0_tlb_mmr_read_data_lo_s { 1008 unsigned long vpn:39; /* RO */ 1009 unsigned long asid:24; /* RO */ 1010 unsigned long valid:1; /* RO */ 1011 } sx; 1012 struct uv2h_gr0_tlb_mmr_read_data_lo_s { 1013 unsigned long vpn:39; /* RO */ 1014 unsigned long asid:24; /* RO */ 1015 unsigned long valid:1; /* RO */ 1016 } s2; 1017 struct uv3h_gr0_tlb_mmr_read_data_lo_s { 1018 unsigned long vpn:39; /* RO */ 1019 unsigned long asid:24; /* RO */ 1020 unsigned long valid:1; /* RO */ 1021 } s3; 1022 struct uv4h_gr0_tlb_mmr_read_data_lo_s { 1023 unsigned long vpn:39; /* RO */ 1024 unsigned long asid:24; /* RO */ 1025 unsigned long valid:1; /* RO */ 1026 } s4; 1027 }; 1028 1029 /* ========================================================================= */ 1030 /* UVH_GR1_TLB_INT0_CONFIG */ 1031 /* ========================================================================= */ 1032 #define UV2H_GR1_TLB_INT0_CONFIG 0x61f00UL 1033 #define UV3H_GR1_TLB_INT0_CONFIG 0x61f00UL 1034 #define UV4H_GR1_TLB_INT0_CONFIG 0x62100UL 1035 #define UVH_GR1_TLB_INT0_CONFIG ( \ 1036 is_uv2_hub() ? UV2H_GR1_TLB_INT0_CONFIG : \ 1037 is_uv3_hub() ? UV3H_GR1_TLB_INT0_CONFIG : \ 1038 /*is_uv4_hub*/ UV4H_GR1_TLB_INT0_CONFIG) 1039 1040 #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0 1041 #define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT 8 1042 #define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT 11 1043 #define UVH_GR1_TLB_INT0_CONFIG_STATUS_SHFT 12 1044 #define UVH_GR1_TLB_INT0_CONFIG_P_SHFT 13 1045 #define UVH_GR1_TLB_INT0_CONFIG_T_SHFT 15 1046 #define UVH_GR1_TLB_INT0_CONFIG_M_SHFT 16 1047 #define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT 32 1048 #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL 1049 #define UVH_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL 1050 #define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL 1051 #define UVH_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL 1052 #define UVH_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL 1053 #define UVH_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL 1054 #define UVH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL 1055 #define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 1056 1057 1058 union uvh_gr1_tlb_int0_config_u { 1059 unsigned long v; 1060 struct uvh_gr1_tlb_int0_config_s { 1061 unsigned long vector_:8; /* RW */ 1062 unsigned long dm:3; /* RW */ 1063 unsigned long destmode:1; /* RW */ 1064 unsigned long status:1; /* RO */ 1065 unsigned long p:1; /* RO */ 1066 unsigned long rsvd_14:1; 1067 unsigned long t:1; /* RO */ 1068 unsigned long m:1; /* RW */ 1069 unsigned long rsvd_17_31:15; 1070 unsigned long apic_id:32; /* RW */ 1071 } s; 1072 }; 1073 1074 /* ========================================================================= */ 1075 /* UVH_GR1_TLB_INT1_CONFIG */ 1076 /* ========================================================================= */ 1077 #define UV2H_GR1_TLB_INT1_CONFIG 0x61f40UL 1078 #define UV3H_GR1_TLB_INT1_CONFIG 0x61f40UL 1079 #define UV4H_GR1_TLB_INT1_CONFIG 0x62140UL 1080 #define UVH_GR1_TLB_INT1_CONFIG ( \ 1081 is_uv2_hub() ? UV2H_GR1_TLB_INT1_CONFIG : \ 1082 is_uv3_hub() ? UV3H_GR1_TLB_INT1_CONFIG : \ 1083 /*is_uv4_hub*/ UV4H_GR1_TLB_INT1_CONFIG) 1084 1085 #define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0 1086 #define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT 8 1087 #define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT 11 1088 #define UVH_GR1_TLB_INT1_CONFIG_STATUS_SHFT 12 1089 #define UVH_GR1_TLB_INT1_CONFIG_P_SHFT 13 1090 #define UVH_GR1_TLB_INT1_CONFIG_T_SHFT 15 1091 #define UVH_GR1_TLB_INT1_CONFIG_M_SHFT 16 1092 #define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT 32 1093 #define UVH_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL 1094 #define UVH_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL 1095 #define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL 1096 #define UVH_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL 1097 #define UVH_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL 1098 #define UVH_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL 1099 #define UVH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL 1100 #define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 1101 1102 1103 union uvh_gr1_tlb_int1_config_u { 1104 unsigned long v; 1105 struct uvh_gr1_tlb_int1_config_s { 1106 unsigned long vector_:8; /* RW */ 1107 unsigned long dm:3; /* RW */ 1108 unsigned long destmode:1; /* RW */ 1109 unsigned long status:1; /* RO */ 1110 unsigned long p:1; /* RO */ 1111 unsigned long rsvd_14:1; 1112 unsigned long t:1; /* RO */ 1113 unsigned long m:1; /* RW */ 1114 unsigned long rsvd_17_31:15; 1115 unsigned long apic_id:32; /* RW */ 1116 } s; 1117 }; 1118 1119 /* ========================================================================= */ 1120 /* UVH_GR1_TLB_MMR_CONTROL */ 1121 /* ========================================================================= */ 1122 #define UV2H_GR1_TLB_MMR_CONTROL 0x1001080UL 1123 #define UV3H_GR1_TLB_MMR_CONTROL 0x1001080UL 1124 #define UV4H_GR1_TLB_MMR_CONTROL 0x701080UL 1125 #define UVH_GR1_TLB_MMR_CONTROL ( \ 1126 is_uv2_hub() ? UV2H_GR1_TLB_MMR_CONTROL : \ 1127 is_uv3_hub() ? UV3H_GR1_TLB_MMR_CONTROL : \ 1128 /*is_uv4_hub*/ UV4H_GR1_TLB_MMR_CONTROL) 1129 1130 #define UVH_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 1131 #define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 1132 #define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 1133 #define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 1134 #define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31 1135 #define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 1136 #define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 1137 #define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 1138 #define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 1139 1140 #define UVXH_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 1141 #define UVXH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 1142 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 1143 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 1144 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31 1145 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 1146 #define UVXH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 1147 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 1148 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 1149 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 1150 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 1151 1152 #define UV2H_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 1153 #define UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 1154 #define UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 1155 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 1156 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 1157 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31 1158 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 1159 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT 48 1160 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT 52 1161 #define UV2H_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL 1162 #define UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL 1163 #define UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 1164 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 1165 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 1166 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 1167 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 1168 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL 1169 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL 1170 1171 #define UV3H_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 1172 #define UV3H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 1173 #define UV3H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 1174 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 1175 #define UV3H_GR1_TLB_MMR_CONTROL_ECC_SEL_SHFT 21 1176 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 1177 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31 1178 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 1179 #define UV3H_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL 1180 #define UV3H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL 1181 #define UV3H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 1182 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 1183 #define UV3H_GR1_TLB_MMR_CONTROL_ECC_SEL_MASK 0x0000000000200000UL 1184 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 1185 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 1186 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 1187 1188 #define UV4H_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 1189 #define UV4H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 13 1190 #define UV4H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 1191 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 1192 #define UV4H_GR1_TLB_MMR_CONTROL_ECC_SEL_SHFT 21 1193 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 1194 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31 1195 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 1196 #define UV4H_GR1_TLB_MMR_CONTROL_PAGE_SIZE_SHFT 59 1197 #define UV4H_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000001fffUL 1198 #define UV4H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000006000UL 1199 #define UV4H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 1200 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 1201 #define UV4H_GR1_TLB_MMR_CONTROL_ECC_SEL_MASK 0x0000000000200000UL 1202 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 1203 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 1204 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 1205 #define UV4H_GR1_TLB_MMR_CONTROL_PAGE_SIZE_MASK 0xf800000000000000UL 1206 1207 1208 union uvh_gr1_tlb_mmr_control_u { 1209 unsigned long v; 1210 struct uvh_gr1_tlb_mmr_control_s { 1211 unsigned long rsvd_0_15:16; 1212 unsigned long auto_valid_en:1; /* RW */ 1213 unsigned long rsvd_17_19:3; 1214 unsigned long mmr_hash_index_en:1; /* RW */ 1215 unsigned long rsvd_21_29:9; 1216 unsigned long mmr_write:1; /* WP */ 1217 unsigned long mmr_read:1; /* WP */ 1218 unsigned long rsvd_32_48:17; 1219 unsigned long rsvd_49_51:3; 1220 unsigned long rsvd_52_63:12; 1221 } s; 1222 struct uvxh_gr1_tlb_mmr_control_s { 1223 unsigned long rsvd_0_15:16; 1224 unsigned long auto_valid_en:1; /* RW */ 1225 unsigned long rsvd_17_19:3; 1226 unsigned long mmr_hash_index_en:1; /* RW */ 1227 unsigned long rsvd_21_29:9; 1228 unsigned long mmr_write:1; /* WP */ 1229 unsigned long mmr_read:1; /* WP */ 1230 unsigned long mmr_op_done:1; /* RW */ 1231 unsigned long rsvd_33_47:15; 1232 unsigned long rsvd_48:1; 1233 unsigned long rsvd_49_51:3; 1234 unsigned long rsvd_52_63:12; 1235 } sx; 1236 struct uv2h_gr1_tlb_mmr_control_s { 1237 unsigned long index:12; /* RW */ 1238 unsigned long mem_sel:2; /* RW */ 1239 unsigned long rsvd_14_15:2; 1240 unsigned long auto_valid_en:1; /* RW */ 1241 unsigned long rsvd_17_19:3; 1242 unsigned long mmr_hash_index_en:1; /* RW */ 1243 unsigned long rsvd_21_29:9; 1244 unsigned long mmr_write:1; /* WP */ 1245 unsigned long mmr_read:1; /* WP */ 1246 unsigned long mmr_op_done:1; /* RW */ 1247 unsigned long rsvd_33_47:15; 1248 unsigned long mmr_inj_con:1; /* RW */ 1249 unsigned long rsvd_49_51:3; 1250 unsigned long mmr_inj_tlbram:1; /* RW */ 1251 unsigned long rsvd_53_63:11; 1252 } s2; 1253 struct uv3h_gr1_tlb_mmr_control_s { 1254 unsigned long index:12; /* RW */ 1255 unsigned long mem_sel:2; /* RW */ 1256 unsigned long rsvd_14_15:2; 1257 unsigned long auto_valid_en:1; /* RW */ 1258 unsigned long rsvd_17_19:3; 1259 unsigned long mmr_hash_index_en:1; /* RW */ 1260 unsigned long ecc_sel:1; /* RW */ 1261 unsigned long rsvd_22_29:8; 1262 unsigned long mmr_write:1; /* WP */ 1263 unsigned long mmr_read:1; /* WP */ 1264 unsigned long mmr_op_done:1; /* RW */ 1265 unsigned long rsvd_33_47:15; 1266 unsigned long undef_48:1; /* Undefined */ 1267 unsigned long rsvd_49_51:3; 1268 unsigned long undef_52:1; /* Undefined */ 1269 unsigned long rsvd_53_63:11; 1270 } s3; 1271 struct uv4h_gr1_tlb_mmr_control_s { 1272 unsigned long index:13; /* RW */ 1273 unsigned long mem_sel:2; /* RW */ 1274 unsigned long rsvd_15:1; 1275 unsigned long auto_valid_en:1; /* RW */ 1276 unsigned long rsvd_17_19:3; 1277 unsigned long mmr_hash_index_en:1; /* RW */ 1278 unsigned long ecc_sel:1; /* RW */ 1279 unsigned long rsvd_22_29:8; 1280 unsigned long mmr_write:1; /* WP */ 1281 unsigned long mmr_read:1; /* WP */ 1282 unsigned long mmr_op_done:1; /* RW */ 1283 unsigned long rsvd_33_47:15; 1284 unsigned long undef_48:1; /* Undefined */ 1285 unsigned long rsvd_49_51:3; 1286 unsigned long rsvd_52_58:7; 1287 unsigned long page_size:5; /* RW */ 1288 } s4; 1289 }; 1290 1291 /* ========================================================================= */ 1292 /* UVH_GR1_TLB_MMR_READ_DATA_HI */ 1293 /* ========================================================================= */ 1294 #define UV2H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL 1295 #define UV3H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL 1296 #define UV4H_GR1_TLB_MMR_READ_DATA_HI 0x7010a0UL 1297 #define UVH_GR1_TLB_MMR_READ_DATA_HI ( \ 1298 is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_HI : \ 1299 is_uv3_hub() ? UV3H_GR1_TLB_MMR_READ_DATA_HI : \ 1300 /*is_uv4_hub*/ UV4H_GR1_TLB_MMR_READ_DATA_HI) 1301 1302 #define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1303 1304 #define UVXH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1305 1306 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1307 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 1308 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 1309 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 1310 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL 1311 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL 1312 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL 1313 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 1314 1315 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1316 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 1317 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 1318 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 1319 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT 45 1320 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT 55 1321 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL 1322 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL 1323 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL 1324 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 1325 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_MASK 0x0000200000000000UL 1326 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK 0xff80000000000000UL 1327 1328 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1329 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_PNID_SHFT 34 1330 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 49 1331 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 51 1332 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT 52 1333 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT 53 1334 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT 55 1335 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK 0x00000003ffffffffUL 1336 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_PNID_MASK 0x0001fffc00000000UL 1337 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0006000000000000UL 1338 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0008000000000000UL 1339 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0010000000000000UL 1340 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_MASK 0x0020000000000000UL 1341 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK 0xff80000000000000UL 1342 1343 1344 union uvh_gr1_tlb_mmr_read_data_hi_u { 1345 unsigned long v; 1346 struct uv2h_gr1_tlb_mmr_read_data_hi_s { 1347 unsigned long pfn:41; /* RO */ 1348 unsigned long gaa:2; /* RO */ 1349 unsigned long dirty:1; /* RO */ 1350 unsigned long larger:1; /* RO */ 1351 unsigned long rsvd_45_63:19; 1352 } s2; 1353 struct uv3h_gr1_tlb_mmr_read_data_hi_s { 1354 unsigned long pfn:41; /* RO */ 1355 unsigned long gaa:2; /* RO */ 1356 unsigned long dirty:1; /* RO */ 1357 unsigned long larger:1; /* RO */ 1358 unsigned long aa_ext:1; /* RO */ 1359 unsigned long undef_46_54:9; /* Undefined */ 1360 unsigned long way_ecc:9; /* RO */ 1361 } s3; 1362 struct uv4h_gr1_tlb_mmr_read_data_hi_s { 1363 unsigned long pfn:34; /* RO */ 1364 unsigned long pnid:15; /* RO */ 1365 unsigned long gaa:2; /* RO */ 1366 unsigned long dirty:1; /* RO */ 1367 unsigned long larger:1; /* RO */ 1368 unsigned long aa_ext:1; /* RO */ 1369 unsigned long undef_54:1; /* Undefined */ 1370 unsigned long way_ecc:9; /* RO */ 1371 } s4; 1372 }; 1373 1374 /* ========================================================================= */ 1375 /* UVH_GR1_TLB_MMR_READ_DATA_LO */ 1376 /* ========================================================================= */ 1377 #define UV2H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL 1378 #define UV3H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL 1379 #define UV4H_GR1_TLB_MMR_READ_DATA_LO 0x7010a8UL 1380 #define UVH_GR1_TLB_MMR_READ_DATA_LO ( \ 1381 is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_LO : \ 1382 is_uv3_hub() ? UV3H_GR1_TLB_MMR_READ_DATA_LO : \ 1383 /*is_uv4_hub*/ UV4H_GR1_TLB_MMR_READ_DATA_LO) 1384 1385 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1386 #define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1387 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1388 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1389 #define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1390 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1391 1392 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1393 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1394 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1395 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1396 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1397 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1398 1399 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1400 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1401 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1402 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1403 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1404 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1405 1406 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1407 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1408 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1409 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1410 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1411 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1412 1413 #define UV4H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1414 #define UV4H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1415 #define UV4H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1416 #define UV4H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1417 #define UV4H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1418 #define UV4H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1419 1420 1421 union uvh_gr1_tlb_mmr_read_data_lo_u { 1422 unsigned long v; 1423 struct uvh_gr1_tlb_mmr_read_data_lo_s { 1424 unsigned long vpn:39; /* RO */ 1425 unsigned long asid:24; /* RO */ 1426 unsigned long valid:1; /* RO */ 1427 } s; 1428 struct uvxh_gr1_tlb_mmr_read_data_lo_s { 1429 unsigned long vpn:39; /* RO */ 1430 unsigned long asid:24; /* RO */ 1431 unsigned long valid:1; /* RO */ 1432 } sx; 1433 struct uv2h_gr1_tlb_mmr_read_data_lo_s { 1434 unsigned long vpn:39; /* RO */ 1435 unsigned long asid:24; /* RO */ 1436 unsigned long valid:1; /* RO */ 1437 } s2; 1438 struct uv3h_gr1_tlb_mmr_read_data_lo_s { 1439 unsigned long vpn:39; /* RO */ 1440 unsigned long asid:24; /* RO */ 1441 unsigned long valid:1; /* RO */ 1442 } s3; 1443 struct uv4h_gr1_tlb_mmr_read_data_lo_s { 1444 unsigned long vpn:39; /* RO */ 1445 unsigned long asid:24; /* RO */ 1446 unsigned long valid:1; /* RO */ 1447 } s4; 1448 }; 1449 1450 /* ========================================================================= */ 1451 /* UVH_INT_CMPB */ 1452 /* ========================================================================= */ 1453 #define UVH_INT_CMPB 0x22080UL 1454 1455 #define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0 1456 #define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL 1457 1458 1459 union uvh_int_cmpb_u { 1460 unsigned long v; 1461 struct uvh_int_cmpb_s { 1462 unsigned long real_time_cmpb:56; /* RW */ 1463 unsigned long rsvd_56_63:8; 1464 } s; 1465 }; 1466 1467 /* ========================================================================= */ 1468 /* UVH_INT_CMPC */ 1469 /* ========================================================================= */ 1470 #define UVH_INT_CMPC 0x22100UL 1471 1472 1473 #define UVXH_INT_CMPC_REAL_TIME_CMP_2_SHFT 0 1474 #define UVXH_INT_CMPC_REAL_TIME_CMP_2_MASK 0x00ffffffffffffffUL 1475 1476 1477 union uvh_int_cmpc_u { 1478 unsigned long v; 1479 struct uvh_int_cmpc_s { 1480 unsigned long real_time_cmpc:56; /* RW */ 1481 unsigned long rsvd_56_63:8; 1482 } s; 1483 }; 1484 1485 /* ========================================================================= */ 1486 /* UVH_INT_CMPD */ 1487 /* ========================================================================= */ 1488 #define UVH_INT_CMPD 0x22180UL 1489 1490 1491 #define UVXH_INT_CMPD_REAL_TIME_CMP_3_SHFT 0 1492 #define UVXH_INT_CMPD_REAL_TIME_CMP_3_MASK 0x00ffffffffffffffUL 1493 1494 1495 union uvh_int_cmpd_u { 1496 unsigned long v; 1497 struct uvh_int_cmpd_s { 1498 unsigned long real_time_cmpd:56; /* RW */ 1499 unsigned long rsvd_56_63:8; 1500 } s; 1501 }; 1502 1503 /* ========================================================================= */ 1504 /* UVH_IPI_INT */ 1505 /* ========================================================================= */ 1506 #define UVH_IPI_INT 0x60500UL 1507 1508 #define UV2H_IPI_INT_32 0x348 1509 #define UV3H_IPI_INT_32 0x348 1510 #define UV4H_IPI_INT_32 0x268 1511 #define UVH_IPI_INT_32 ( \ 1512 is_uv2_hub() ? UV2H_IPI_INT_32 : \ 1513 is_uv3_hub() ? UV3H_IPI_INT_32 : \ 1514 /*is_uv4_hub*/ UV4H_IPI_INT_32) 1515 1516 #define UVH_IPI_INT_VECTOR_SHFT 0 1517 #define UVH_IPI_INT_DELIVERY_MODE_SHFT 8 1518 #define UVH_IPI_INT_DESTMODE_SHFT 11 1519 #define UVH_IPI_INT_APIC_ID_SHFT 16 1520 #define UVH_IPI_INT_SEND_SHFT 63 1521 #define UVH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL 1522 #define UVH_IPI_INT_DELIVERY_MODE_MASK 0x0000000000000700UL 1523 #define UVH_IPI_INT_DESTMODE_MASK 0x0000000000000800UL 1524 #define UVH_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL 1525 #define UVH_IPI_INT_SEND_MASK 0x8000000000000000UL 1526 1527 1528 union uvh_ipi_int_u { 1529 unsigned long v; 1530 struct uvh_ipi_int_s { 1531 unsigned long vector_:8; /* RW */ 1532 unsigned long delivery_mode:3; /* RW */ 1533 unsigned long destmode:1; /* RW */ 1534 unsigned long rsvd_12_15:4; 1535 unsigned long apic_id:32; /* RW */ 1536 unsigned long rsvd_48_62:15; 1537 unsigned long send:1; /* WP */ 1538 } s; 1539 }; 1540 1541 /* ========================================================================= */ 1542 /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST */ 1543 /* ========================================================================= */ 1544 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL 1545 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL 1546 #define UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST uv_undefined("UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST") 1547 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST ( \ 1548 is_uv2_hub() ? UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST : \ 1549 is_uv3_hub() ? UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST : \ 1550 /*is_uv4_hub*/ UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST) 1551 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x9c0 1552 1553 1554 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4 1555 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49 1556 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL 1557 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL 1558 1559 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4 1560 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49 1561 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL 1562 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL 1563 1564 1565 union uvh_lb_bau_intd_payload_queue_first_u { 1566 unsigned long v; 1567 struct uv2h_lb_bau_intd_payload_queue_first_s { 1568 unsigned long rsvd_0_3:4; 1569 unsigned long address:39; /* RW */ 1570 unsigned long rsvd_43_48:6; 1571 unsigned long node_id:14; /* RW */ 1572 unsigned long rsvd_63:1; 1573 } s2; 1574 struct uv3h_lb_bau_intd_payload_queue_first_s { 1575 unsigned long rsvd_0_3:4; 1576 unsigned long address:39; /* RW */ 1577 unsigned long rsvd_43_48:6; 1578 unsigned long node_id:14; /* RW */ 1579 unsigned long rsvd_63:1; 1580 } s3; 1581 }; 1582 1583 /* ========================================================================= */ 1584 /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST */ 1585 /* ========================================================================= */ 1586 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL 1587 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL 1588 #define UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST uv_undefined("UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST") 1589 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST ( \ 1590 is_uv2_hub() ? UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST : \ 1591 is_uv3_hub() ? UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST : \ 1592 /*is_uv4_hub*/ UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST) 1593 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x9c8 1594 1595 1596 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4 1597 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL 1598 1599 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4 1600 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL 1601 1602 1603 union uvh_lb_bau_intd_payload_queue_last_u { 1604 unsigned long v; 1605 struct uv2h_lb_bau_intd_payload_queue_last_s { 1606 unsigned long rsvd_0_3:4; 1607 unsigned long address:39; /* RW */ 1608 unsigned long rsvd_43_63:21; 1609 } s2; 1610 struct uv3h_lb_bau_intd_payload_queue_last_s { 1611 unsigned long rsvd_0_3:4; 1612 unsigned long address:39; /* RW */ 1613 unsigned long rsvd_43_63:21; 1614 } s3; 1615 }; 1616 1617 /* ========================================================================= */ 1618 /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL */ 1619 /* ========================================================================= */ 1620 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL 1621 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL 1622 #define UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL uv_undefined("UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL") 1623 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL ( \ 1624 is_uv2_hub() ? UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL : \ 1625 is_uv3_hub() ? UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL : \ 1626 /*is_uv4_hub*/ UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL) 1627 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x9d0 1628 1629 1630 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4 1631 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL 1632 1633 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4 1634 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL 1635 1636 1637 union uvh_lb_bau_intd_payload_queue_tail_u { 1638 unsigned long v; 1639 struct uv2h_lb_bau_intd_payload_queue_tail_s { 1640 unsigned long rsvd_0_3:4; 1641 unsigned long address:39; /* RW */ 1642 unsigned long rsvd_43_63:21; 1643 } s2; 1644 struct uv3h_lb_bau_intd_payload_queue_tail_s { 1645 unsigned long rsvd_0_3:4; 1646 unsigned long address:39; /* RW */ 1647 unsigned long rsvd_43_63:21; 1648 } s3; 1649 }; 1650 1651 /* ========================================================================= */ 1652 /* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE */ 1653 /* ========================================================================= */ 1654 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL 1655 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL 1656 #define UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE uv_undefined("UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE") 1657 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE ( \ 1658 is_uv2_hub() ? UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE : \ 1659 is_uv3_hub() ? UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE : \ 1660 /*is_uv4_hub*/ UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE) 1661 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0xa68 1662 1663 1664 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 1665 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1 1666 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2 1667 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3 1668 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4 1669 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5 1670 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6 1671 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7 1672 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8 1673 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9 1674 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10 1675 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11 1676 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12 1677 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13 1678 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14 1679 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15 1680 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL 1681 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL 1682 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL 1683 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL 1684 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL 1685 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL 1686 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL 1687 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL 1688 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL 1689 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL 1690 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL 1691 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL 1692 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL 1693 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL 1694 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL 1695 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL 1696 1697 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 1698 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1 1699 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2 1700 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3 1701 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4 1702 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5 1703 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6 1704 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7 1705 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8 1706 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9 1707 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10 1708 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11 1709 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12 1710 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13 1711 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14 1712 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15 1713 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL 1714 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL 1715 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL 1716 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL 1717 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL 1718 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL 1719 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL 1720 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL 1721 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL 1722 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL 1723 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL 1724 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL 1725 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL 1726 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL 1727 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL 1728 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL 1729 1730 1731 union uvh_lb_bau_intd_software_acknowledge_u { 1732 unsigned long v; 1733 struct uv2h_lb_bau_intd_software_acknowledge_s { 1734 unsigned long pending_0:1; /* RW */ 1735 unsigned long pending_1:1; /* RW */ 1736 unsigned long pending_2:1; /* RW */ 1737 unsigned long pending_3:1; /* RW */ 1738 unsigned long pending_4:1; /* RW */ 1739 unsigned long pending_5:1; /* RW */ 1740 unsigned long pending_6:1; /* RW */ 1741 unsigned long pending_7:1; /* RW */ 1742 unsigned long timeout_0:1; /* RW */ 1743 unsigned long timeout_1:1; /* RW */ 1744 unsigned long timeout_2:1; /* RW */ 1745 unsigned long timeout_3:1; /* RW */ 1746 unsigned long timeout_4:1; /* RW */ 1747 unsigned long timeout_5:1; /* RW */ 1748 unsigned long timeout_6:1; /* RW */ 1749 unsigned long timeout_7:1; /* RW */ 1750 unsigned long rsvd_16_63:48; 1751 } s2; 1752 struct uv3h_lb_bau_intd_software_acknowledge_s { 1753 unsigned long pending_0:1; /* RW */ 1754 unsigned long pending_1:1; /* RW */ 1755 unsigned long pending_2:1; /* RW */ 1756 unsigned long pending_3:1; /* RW */ 1757 unsigned long pending_4:1; /* RW */ 1758 unsigned long pending_5:1; /* RW */ 1759 unsigned long pending_6:1; /* RW */ 1760 unsigned long pending_7:1; /* RW */ 1761 unsigned long timeout_0:1; /* RW */ 1762 unsigned long timeout_1:1; /* RW */ 1763 unsigned long timeout_2:1; /* RW */ 1764 unsigned long timeout_3:1; /* RW */ 1765 unsigned long timeout_4:1; /* RW */ 1766 unsigned long timeout_5:1; /* RW */ 1767 unsigned long timeout_6:1; /* RW */ 1768 unsigned long timeout_7:1; /* RW */ 1769 unsigned long rsvd_16_63:48; 1770 } s3; 1771 }; 1772 1773 /* ========================================================================= */ 1774 /* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS */ 1775 /* ========================================================================= */ 1776 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL 1777 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL 1778 #define UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS uv_undefined("UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS") 1779 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS ( \ 1780 is_uv2_hub() ? UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS : \ 1781 is_uv3_hub() ? UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS : \ 1782 /*is_uv4_hub*/ UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS) 1783 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0xa70 1784 1785 1786 /* ========================================================================= */ 1787 /* UVH_LB_BAU_MISC_CONTROL */ 1788 /* ========================================================================= */ 1789 #define UV2H_LB_BAU_MISC_CONTROL 0x320170UL 1790 #define UV3H_LB_BAU_MISC_CONTROL 0x320170UL 1791 #define UV4H_LB_BAU_MISC_CONTROL 0xc8170UL 1792 #define UVH_LB_BAU_MISC_CONTROL ( \ 1793 is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL : \ 1794 is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL : \ 1795 /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL) 1796 1797 #define UV2H_LB_BAU_MISC_CONTROL_32 0xa10 1798 #define UV3H_LB_BAU_MISC_CONTROL_32 0xa10 1799 #define UV4H_LB_BAU_MISC_CONTROL_32 0xa18 1800 #define UVH_LB_BAU_MISC_CONTROL_32 ( \ 1801 is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_32 : \ 1802 is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_32 : \ 1803 /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_32) 1804 1805 #define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 1806 #define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 1807 #define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 1808 #define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 1809 #define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 1810 #define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 1811 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 1812 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 1813 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 1814 #define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 1815 #define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 1816 #define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 1817 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 1818 #define UVH_LB_BAU_MISC_CONTROL_FUN_SHFT 48 1819 #define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 1820 #define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL 1821 #define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL 1822 #define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 1823 #define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 1824 #define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 1825 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL 1826 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL 1827 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL 1828 #define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL 1829 #define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL 1830 #define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL 1831 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 1832 #define UVH_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 1833 1834 #define UVXH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 1835 #define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 1836 #define UVXH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 1837 #define UVXH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 1838 #define UVXH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 1839 #define UVXH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 1840 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 1841 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 1842 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 1843 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 1844 #define UVXH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 1845 #define UVXH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 1846 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 1847 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29 1848 #define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT 30 1849 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31 1850 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32 1851 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33 1852 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34 1853 #define UVXH_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35 1854 #define UVXH_LB_BAU_MISC_CONTROL_FUN_SHFT 48 1855 #define UVXH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 1856 #define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL 1857 #define UVXH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL 1858 #define UVXH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 1859 #define UVXH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 1860 #define UVXH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 1861 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL 1862 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL 1863 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL 1864 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL 1865 #define UVXH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL 1866 #define UVXH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL 1867 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 1868 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL 1869 #define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK 0x0000000040000000UL 1870 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL 1871 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL 1872 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL 1873 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL 1874 #define UVXH_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL 1875 #define UVXH_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 1876 1877 #define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 1878 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 1879 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 1880 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 1881 #define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 1882 #define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 1883 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15 1884 #define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16 1885 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 1886 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 1887 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 1888 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 1889 #define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 1890 #define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 1891 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 1892 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29 1893 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT 30 1894 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31 1895 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32 1896 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33 1897 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34 1898 #define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35 1899 #define UV2H_LB_BAU_MISC_CONTROL_FUN_SHFT 48 1900 #define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 1901 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL 1902 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL 1903 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 1904 #define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 1905 #define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 1906 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL 1907 #define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL 1908 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL 1909 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL 1910 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL 1911 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL 1912 #define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL 1913 #define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL 1914 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 1915 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL 1916 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK 0x0000000040000000UL 1917 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL 1918 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL 1919 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL 1920 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL 1921 #define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL 1922 #define UV2H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 1923 1924 #define UV3H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 1925 #define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 1926 #define UV3H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 1927 #define UV3H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 1928 #define UV3H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 1929 #define UV3H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 1930 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15 1931 #define UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16 1932 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 1933 #define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 1934 #define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 1935 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 1936 #define UV3H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 1937 #define UV3H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 1938 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 1939 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29 1940 #define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT 30 1941 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31 1942 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32 1943 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33 1944 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34 1945 #define UV3H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35 1946 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_SHFT 36 1947 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_PREFETCH_HINT_SHFT 37 1948 #define UV3H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_SHFT 38 1949 #define UV3H_LB_BAU_MISC_CONTROL_FUN_SHFT 48 1950 #define UV3H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 1951 #define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL 1952 #define UV3H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL 1953 #define UV3H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 1954 #define UV3H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 1955 #define UV3H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 1956 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL 1957 #define UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL 1958 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL 1959 #define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL 1960 #define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL 1961 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL 1962 #define UV3H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL 1963 #define UV3H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL 1964 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 1965 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL 1966 #define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK 0x0000000040000000UL 1967 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL 1968 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL 1969 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL 1970 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL 1971 #define UV3H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL 1972 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_MASK 0x0000001000000000UL 1973 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_PREFETCH_HINT_MASK 0x0000002000000000UL 1974 #define UV3H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_MASK 0x00003fc000000000UL 1975 #define UV3H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 1976 1977 #define UV4H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 1978 #define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 1979 #define UV4H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 1980 #define UV4H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 1981 #define UV4H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 1982 #define UV4H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 1983 #define UV4H_LB_BAU_MISC_CONTROL_RESERVED_15_19_SHFT 15 1984 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 1985 #define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 1986 #define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 1987 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 1988 #define UV4H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 1989 #define UV4H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 1990 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 1991 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29 1992 #define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT 30 1993 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31 1994 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32 1995 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33 1996 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34 1997 #define UV4H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35 1998 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_SHFT 36 1999 #define UV4H_LB_BAU_MISC_CONTROL_RESERVED_37_SHFT 37 2000 #define UV4H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_SHFT 38 2001 #define UV4H_LB_BAU_MISC_CONTROL_ADDRESS_INTERLEAVE_SELECT_SHFT 46 2002 #define UV4H_LB_BAU_MISC_CONTROL_FUN_SHFT 48 2003 #define UV4H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 2004 #define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL 2005 #define UV4H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL 2006 #define UV4H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 2007 #define UV4H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 2008 #define UV4H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 2009 #define UV4H_LB_BAU_MISC_CONTROL_RESERVED_15_19_MASK 0x00000000000f8000UL 2010 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL 2011 #define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL 2012 #define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL 2013 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL 2014 #define UV4H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL 2015 #define UV4H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL 2016 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 2017 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL 2018 #define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK 0x0000000040000000UL 2019 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL 2020 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL 2021 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL 2022 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL 2023 #define UV4H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL 2024 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_MASK 0x0000001000000000UL 2025 #define UV4H_LB_BAU_MISC_CONTROL_RESERVED_37_MASK 0x0000002000000000UL 2026 #define UV4H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_MASK 0x00003fc000000000UL 2027 #define UV4H_LB_BAU_MISC_CONTROL_ADDRESS_INTERLEAVE_SELECT_MASK 0x0000400000000000UL 2028 #define UV4H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 2029 2030 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK \ 2031 uv_undefined("UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK") 2032 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK ( \ 2033 is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK : \ 2034 is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK : \ 2035 /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK) 2036 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT \ 2037 uv_undefined("UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT") 2038 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT ( \ 2039 is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT : \ 2040 is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT : \ 2041 /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT) 2042 #define UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK \ 2043 uv_undefined("UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK") 2044 #define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK ( \ 2045 is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK : \ 2046 is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK : \ 2047 /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK) 2048 #define UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT \ 2049 uv_undefined("UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT") 2050 #define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT ( \ 2051 is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT : \ 2052 is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT : \ 2053 /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT) 2054 2055 union uvh_lb_bau_misc_control_u { 2056 unsigned long v; 2057 struct uvh_lb_bau_misc_control_s { 2058 unsigned long rejection_delay:8; /* RW */ 2059 unsigned long apic_mode:1; /* RW */ 2060 unsigned long force_broadcast:1; /* RW */ 2061 unsigned long force_lock_nop:1; /* RW */ 2062 unsigned long qpi_agent_presence_vector:3; /* RW */ 2063 unsigned long descriptor_fetch_mode:1; /* RW */ 2064 unsigned long rsvd_15_19:5; 2065 unsigned long enable_dual_mapping_mode:1; /* RW */ 2066 unsigned long vga_io_port_decode_enable:1; /* RW */ 2067 unsigned long vga_io_port_16_bit_decode:1; /* RW */ 2068 unsigned long suppress_dest_registration:1; /* RW */ 2069 unsigned long programmed_initial_priority:3; /* RW */ 2070 unsigned long use_incoming_priority:1; /* RW */ 2071 unsigned long enable_programmed_initial_priority:1;/* RW */ 2072 unsigned long rsvd_29_47:19; 2073 unsigned long fun:16; /* RW */ 2074 } s; 2075 struct uvxh_lb_bau_misc_control_s { 2076 unsigned long rejection_delay:8; /* RW */ 2077 unsigned long apic_mode:1; /* RW */ 2078 unsigned long force_broadcast:1; /* RW */ 2079 unsigned long force_lock_nop:1; /* RW */ 2080 unsigned long qpi_agent_presence_vector:3; /* RW */ 2081 unsigned long descriptor_fetch_mode:1; /* RW */ 2082 unsigned long rsvd_15_19:5; 2083 unsigned long enable_dual_mapping_mode:1; /* RW */ 2084 unsigned long vga_io_port_decode_enable:1; /* RW */ 2085 unsigned long vga_io_port_16_bit_decode:1; /* RW */ 2086 unsigned long suppress_dest_registration:1; /* RW */ 2087 unsigned long programmed_initial_priority:3; /* RW */ 2088 unsigned long use_incoming_priority:1; /* RW */ 2089 unsigned long enable_programmed_initial_priority:1;/* RW */ 2090 unsigned long enable_automatic_apic_mode_selection:1;/* RW */ 2091 unsigned long apic_mode_status:1; /* RO */ 2092 unsigned long suppress_interrupts_to_self:1; /* RW */ 2093 unsigned long enable_lock_based_system_flush:1;/* RW */ 2094 unsigned long enable_extended_sb_status:1; /* RW */ 2095 unsigned long suppress_int_prio_udt_to_self:1;/* RW */ 2096 unsigned long use_legacy_descriptor_formats:1;/* RW */ 2097 unsigned long rsvd_36_47:12; 2098 unsigned long fun:16; /* RW */ 2099 } sx; 2100 struct uv2h_lb_bau_misc_control_s { 2101 unsigned long rejection_delay:8; /* RW */ 2102 unsigned long apic_mode:1; /* RW */ 2103 unsigned long force_broadcast:1; /* RW */ 2104 unsigned long force_lock_nop:1; /* RW */ 2105 unsigned long qpi_agent_presence_vector:3; /* RW */ 2106 unsigned long descriptor_fetch_mode:1; /* RW */ 2107 unsigned long enable_intd_soft_ack_mode:1; /* RW */ 2108 unsigned long intd_soft_ack_timeout_period:4; /* RW */ 2109 unsigned long enable_dual_mapping_mode:1; /* RW */ 2110 unsigned long vga_io_port_decode_enable:1; /* RW */ 2111 unsigned long vga_io_port_16_bit_decode:1; /* RW */ 2112 unsigned long suppress_dest_registration:1; /* RW */ 2113 unsigned long programmed_initial_priority:3; /* RW */ 2114 unsigned long use_incoming_priority:1; /* RW */ 2115 unsigned long enable_programmed_initial_priority:1;/* RW */ 2116 unsigned long enable_automatic_apic_mode_selection:1;/* RW */ 2117 unsigned long apic_mode_status:1; /* RO */ 2118 unsigned long suppress_interrupts_to_self:1; /* RW */ 2119 unsigned long enable_lock_based_system_flush:1;/* RW */ 2120 unsigned long enable_extended_sb_status:1; /* RW */ 2121 unsigned long suppress_int_prio_udt_to_self:1;/* RW */ 2122 unsigned long use_legacy_descriptor_formats:1;/* RW */ 2123 unsigned long rsvd_36_47:12; 2124 unsigned long fun:16; /* RW */ 2125 } s2; 2126 struct uv3h_lb_bau_misc_control_s { 2127 unsigned long rejection_delay:8; /* RW */ 2128 unsigned long apic_mode:1; /* RW */ 2129 unsigned long force_broadcast:1; /* RW */ 2130 unsigned long force_lock_nop:1; /* RW */ 2131 unsigned long qpi_agent_presence_vector:3; /* RW */ 2132 unsigned long descriptor_fetch_mode:1; /* RW */ 2133 unsigned long enable_intd_soft_ack_mode:1; /* RW */ 2134 unsigned long intd_soft_ack_timeout_period:4; /* RW */ 2135 unsigned long enable_dual_mapping_mode:1; /* RW */ 2136 unsigned long vga_io_port_decode_enable:1; /* RW */ 2137 unsigned long vga_io_port_16_bit_decode:1; /* RW */ 2138 unsigned long suppress_dest_registration:1; /* RW */ 2139 unsigned long programmed_initial_priority:3; /* RW */ 2140 unsigned long use_incoming_priority:1; /* RW */ 2141 unsigned long enable_programmed_initial_priority:1;/* RW */ 2142 unsigned long enable_automatic_apic_mode_selection:1;/* RW */ 2143 unsigned long apic_mode_status:1; /* RO */ 2144 unsigned long suppress_interrupts_to_self:1; /* RW */ 2145 unsigned long enable_lock_based_system_flush:1;/* RW */ 2146 unsigned long enable_extended_sb_status:1; /* RW */ 2147 unsigned long suppress_int_prio_udt_to_self:1;/* RW */ 2148 unsigned long use_legacy_descriptor_formats:1;/* RW */ 2149 unsigned long suppress_quiesce_msgs_to_qpi:1; /* RW */ 2150 unsigned long enable_intd_prefetch_hint:1; /* RW */ 2151 unsigned long thread_kill_timebase:8; /* RW */ 2152 unsigned long rsvd_46_47:2; 2153 unsigned long fun:16; /* RW */ 2154 } s3; 2155 struct uv4h_lb_bau_misc_control_s { 2156 unsigned long rejection_delay:8; /* RW */ 2157 unsigned long apic_mode:1; /* RW */ 2158 unsigned long force_broadcast:1; /* RW */ 2159 unsigned long force_lock_nop:1; /* RW */ 2160 unsigned long qpi_agent_presence_vector:3; /* RW */ 2161 unsigned long descriptor_fetch_mode:1; /* RW */ 2162 unsigned long rsvd_15_19:5; 2163 unsigned long enable_dual_mapping_mode:1; /* RW */ 2164 unsigned long vga_io_port_decode_enable:1; /* RW */ 2165 unsigned long vga_io_port_16_bit_decode:1; /* RW */ 2166 unsigned long suppress_dest_registration:1; /* RW */ 2167 unsigned long programmed_initial_priority:3; /* RW */ 2168 unsigned long use_incoming_priority:1; /* RW */ 2169 unsigned long enable_programmed_initial_priority:1;/* RW */ 2170 unsigned long enable_automatic_apic_mode_selection:1;/* RW */ 2171 unsigned long apic_mode_status:1; /* RO */ 2172 unsigned long suppress_interrupts_to_self:1; /* RW */ 2173 unsigned long enable_lock_based_system_flush:1;/* RW */ 2174 unsigned long enable_extended_sb_status:1; /* RW */ 2175 unsigned long suppress_int_prio_udt_to_self:1;/* RW */ 2176 unsigned long use_legacy_descriptor_formats:1;/* RW */ 2177 unsigned long suppress_quiesce_msgs_to_qpi:1; /* RW */ 2178 unsigned long rsvd_37:1; 2179 unsigned long thread_kill_timebase:8; /* RW */ 2180 unsigned long address_interleave_select:1; /* RW */ 2181 unsigned long rsvd_47:1; 2182 unsigned long fun:16; /* RW */ 2183 } s4; 2184 }; 2185 2186 /* ========================================================================= */ 2187 /* UVH_LB_BAU_SB_ACTIVATION_CONTROL */ 2188 /* ========================================================================= */ 2189 #define UV2H_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL 2190 #define UV3H_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL 2191 #define UV4H_LB_BAU_SB_ACTIVATION_CONTROL 0xc8020UL 2192 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL ( \ 2193 is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_CONTROL : \ 2194 is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_CONTROL : \ 2195 /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_CONTROL) 2196 2197 #define UV2H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8 2198 #define UV3H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8 2199 #define UV4H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9c8 2200 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 ( \ 2201 is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_CONTROL_32 : \ 2202 is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_CONTROL_32 : \ 2203 /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_CONTROL_32) 2204 2205 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0 2206 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62 2207 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT 63 2208 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL 2209 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL 2210 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL 2211 2212 2213 union uvh_lb_bau_sb_activation_control_u { 2214 unsigned long v; 2215 struct uvh_lb_bau_sb_activation_control_s { 2216 unsigned long index:6; /* RW */ 2217 unsigned long rsvd_6_61:56; 2218 unsigned long push:1; /* WP */ 2219 unsigned long init:1; /* WP */ 2220 } s; 2221 }; 2222 2223 /* ========================================================================= */ 2224 /* UVH_LB_BAU_SB_ACTIVATION_STATUS_0 */ 2225 /* ========================================================================= */ 2226 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL 2227 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL 2228 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_0 0xc8030UL 2229 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 ( \ 2230 is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_0 : \ 2231 is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_0 : \ 2232 /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_0) 2233 2234 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0 2235 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0 2236 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9d0 2237 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 ( \ 2238 is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_0_32 : \ 2239 is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_0_32 : \ 2240 /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_0_32) 2241 2242 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0 2243 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL 2244 2245 2246 union uvh_lb_bau_sb_activation_status_0_u { 2247 unsigned long v; 2248 struct uvh_lb_bau_sb_activation_status_0_s { 2249 unsigned long status:64; /* RW */ 2250 } s; 2251 }; 2252 2253 /* ========================================================================= */ 2254 /* UVH_LB_BAU_SB_ACTIVATION_STATUS_1 */ 2255 /* ========================================================================= */ 2256 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL 2257 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL 2258 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_1 0xc8040UL 2259 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 ( \ 2260 is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_1 : \ 2261 is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_1 : \ 2262 /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_1) 2263 2264 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8 2265 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8 2266 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9d8 2267 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 ( \ 2268 is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_1_32 : \ 2269 is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_1_32 : \ 2270 /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_1_32) 2271 2272 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0 2273 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL 2274 2275 2276 union uvh_lb_bau_sb_activation_status_1_u { 2277 unsigned long v; 2278 struct uvh_lb_bau_sb_activation_status_1_s { 2279 unsigned long status:64; /* RW */ 2280 } s; 2281 }; 2282 2283 /* ========================================================================= */ 2284 /* UVH_LB_BAU_SB_DESCRIPTOR_BASE */ 2285 /* ========================================================================= */ 2286 #define UV2H_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL 2287 #define UV3H_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL 2288 #define UV4H_LB_BAU_SB_DESCRIPTOR_BASE 0xc8010UL 2289 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE ( \ 2290 is_uv2_hub() ? UV2H_LB_BAU_SB_DESCRIPTOR_BASE : \ 2291 is_uv3_hub() ? UV3H_LB_BAU_SB_DESCRIPTOR_BASE : \ 2292 /*is_uv4_hub*/ UV4H_LB_BAU_SB_DESCRIPTOR_BASE) 2293 2294 #define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0 2295 #define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0 2296 #define UV4H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9c0 2297 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 ( \ 2298 is_uv2_hub() ? UV2H_LB_BAU_SB_DESCRIPTOR_BASE_32 : \ 2299 is_uv3_hub() ? UV3H_LB_BAU_SB_DESCRIPTOR_BASE_32 : \ 2300 /*is_uv4_hub*/ UV4H_LB_BAU_SB_DESCRIPTOR_BASE_32) 2301 2302 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12 2303 2304 #define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49 2305 #define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL 2306 #define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL 2307 2308 #define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49 2309 #define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL 2310 #define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL 2311 2312 #define UV4H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49 2313 #define UV4H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x00003ffffffff000UL 2314 #define UV4H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL 2315 2316 #define UV4AH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 53 2317 #define UV4AH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000ffffffffff000UL 2318 #define UV4AH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0xffe0000000000000UL 2319 2320 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT ( \ 2321 is_uv2_hub() ? UV2H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT : \ 2322 is_uv3_hub() ? UV3H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT : \ 2323 is_uv4a_hub() ? UV4AH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT : \ 2324 /*is_uv4_hub*/ UV4H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT) 2325 2326 #define UVH_LB_BAU_SB_DESCRIPTOR_PAGE_ADDRESS_MASK ( \ 2327 is_uv2_hub() ? UV2H_LB_BAU_SB_DESCRIPTOR_PAGE_ADDRESS_MASK : \ 2328 is_uv3_hub() ? UV3H_LB_BAU_SB_DESCRIPTOR_PAGE_ADDRESS_MASK : \ 2329 is_uv4a_hub() ? UV4AH_LB_BAU_SB_DESCRIPTOR_PAGE_ADDRESS_MASK : \ 2330 /*is_uv4_hub*/ UV4H_LB_BAU_SB_DESCRIPTOR_PAGE_ADDRESS_MASK) 2331 2332 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK ( \ 2333 is_uv2_hub() ? UV2H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK : \ 2334 is_uv3_hub() ? UV3H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK : \ 2335 is_uv4a_hub() ? UV4AH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK : \ 2336 /*is_uv4_hub*/ UV4H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK) 2337 2338 /* ========================================================================= */ 2339 /* UVH_NODE_ID */ 2340 /* ========================================================================= */ 2341 #define UVH_NODE_ID 0x0UL 2342 #define UV2H_NODE_ID 0x0UL 2343 #define UV3H_NODE_ID 0x0UL 2344 #define UV4H_NODE_ID 0x0UL 2345 2346 #define UVH_NODE_ID_FORCE1_SHFT 0 2347 #define UVH_NODE_ID_MANUFACTURER_SHFT 1 2348 #define UVH_NODE_ID_PART_NUMBER_SHFT 12 2349 #define UVH_NODE_ID_REVISION_SHFT 28 2350 #define UVH_NODE_ID_NODE_ID_SHFT 32 2351 #define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL 2352 #define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL 2353 #define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL 2354 #define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL 2355 #define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 2356 2357 #define UVXH_NODE_ID_FORCE1_SHFT 0 2358 #define UVXH_NODE_ID_MANUFACTURER_SHFT 1 2359 #define UVXH_NODE_ID_PART_NUMBER_SHFT 12 2360 #define UVXH_NODE_ID_REVISION_SHFT 28 2361 #define UVXH_NODE_ID_NODE_ID_SHFT 32 2362 #define UVXH_NODE_ID_NODES_PER_BIT_SHFT 50 2363 #define UVXH_NODE_ID_NI_PORT_SHFT 57 2364 #define UVXH_NODE_ID_FORCE1_MASK 0x0000000000000001UL 2365 #define UVXH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL 2366 #define UVXH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL 2367 #define UVXH_NODE_ID_REVISION_MASK 0x00000000f0000000UL 2368 #define UVXH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 2369 #define UVXH_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL 2370 #define UVXH_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL 2371 2372 #define UV2H_NODE_ID_FORCE1_SHFT 0 2373 #define UV2H_NODE_ID_MANUFACTURER_SHFT 1 2374 #define UV2H_NODE_ID_PART_NUMBER_SHFT 12 2375 #define UV2H_NODE_ID_REVISION_SHFT 28 2376 #define UV2H_NODE_ID_NODE_ID_SHFT 32 2377 #define UV2H_NODE_ID_NODES_PER_BIT_SHFT 50 2378 #define UV2H_NODE_ID_NI_PORT_SHFT 57 2379 #define UV2H_NODE_ID_FORCE1_MASK 0x0000000000000001UL 2380 #define UV2H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL 2381 #define UV2H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL 2382 #define UV2H_NODE_ID_REVISION_MASK 0x00000000f0000000UL 2383 #define UV2H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 2384 #define UV2H_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL 2385 #define UV2H_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL 2386 2387 #define UV3H_NODE_ID_FORCE1_SHFT 0 2388 #define UV3H_NODE_ID_MANUFACTURER_SHFT 1 2389 #define UV3H_NODE_ID_PART_NUMBER_SHFT 12 2390 #define UV3H_NODE_ID_REVISION_SHFT 28 2391 #define UV3H_NODE_ID_NODE_ID_SHFT 32 2392 #define UV3H_NODE_ID_ROUTER_SELECT_SHFT 48 2393 #define UV3H_NODE_ID_RESERVED_2_SHFT 49 2394 #define UV3H_NODE_ID_NODES_PER_BIT_SHFT 50 2395 #define UV3H_NODE_ID_NI_PORT_SHFT 57 2396 #define UV3H_NODE_ID_FORCE1_MASK 0x0000000000000001UL 2397 #define UV3H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL 2398 #define UV3H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL 2399 #define UV3H_NODE_ID_REVISION_MASK 0x00000000f0000000UL 2400 #define UV3H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 2401 #define UV3H_NODE_ID_ROUTER_SELECT_MASK 0x0001000000000000UL 2402 #define UV3H_NODE_ID_RESERVED_2_MASK 0x0002000000000000UL 2403 #define UV3H_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL 2404 #define UV3H_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL 2405 2406 #define UV4H_NODE_ID_FORCE1_SHFT 0 2407 #define UV4H_NODE_ID_MANUFACTURER_SHFT 1 2408 #define UV4H_NODE_ID_PART_NUMBER_SHFT 12 2409 #define UV4H_NODE_ID_REVISION_SHFT 28 2410 #define UV4H_NODE_ID_NODE_ID_SHFT 32 2411 #define UV4H_NODE_ID_ROUTER_SELECT_SHFT 48 2412 #define UV4H_NODE_ID_RESERVED_2_SHFT 49 2413 #define UV4H_NODE_ID_NODES_PER_BIT_SHFT 50 2414 #define UV4H_NODE_ID_NI_PORT_SHFT 57 2415 #define UV4H_NODE_ID_FORCE1_MASK 0x0000000000000001UL 2416 #define UV4H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL 2417 #define UV4H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL 2418 #define UV4H_NODE_ID_REVISION_MASK 0x00000000f0000000UL 2419 #define UV4H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 2420 #define UV4H_NODE_ID_ROUTER_SELECT_MASK 0x0001000000000000UL 2421 #define UV4H_NODE_ID_RESERVED_2_MASK 0x0002000000000000UL 2422 #define UV4H_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL 2423 #define UV4H_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL 2424 2425 2426 union uvh_node_id_u { 2427 unsigned long v; 2428 struct uvh_node_id_s { 2429 unsigned long force1:1; /* RO */ 2430 unsigned long manufacturer:11; /* RO */ 2431 unsigned long part_number:16; /* RO */ 2432 unsigned long revision:4; /* RO */ 2433 unsigned long node_id:15; /* RW */ 2434 unsigned long rsvd_47_63:17; 2435 } s; 2436 struct uvxh_node_id_s { 2437 unsigned long force1:1; /* RO */ 2438 unsigned long manufacturer:11; /* RO */ 2439 unsigned long part_number:16; /* RO */ 2440 unsigned long revision:4; /* RO */ 2441 unsigned long node_id:15; /* RW */ 2442 unsigned long rsvd_47_49:3; 2443 unsigned long nodes_per_bit:7; /* RO */ 2444 unsigned long ni_port:5; /* RO */ 2445 unsigned long rsvd_62_63:2; 2446 } sx; 2447 struct uv2h_node_id_s { 2448 unsigned long force1:1; /* RO */ 2449 unsigned long manufacturer:11; /* RO */ 2450 unsigned long part_number:16; /* RO */ 2451 unsigned long revision:4; /* RO */ 2452 unsigned long node_id:15; /* RW */ 2453 unsigned long rsvd_47_49:3; 2454 unsigned long nodes_per_bit:7; /* RO */ 2455 unsigned long ni_port:5; /* RO */ 2456 unsigned long rsvd_62_63:2; 2457 } s2; 2458 struct uv3h_node_id_s { 2459 unsigned long force1:1; /* RO */ 2460 unsigned long manufacturer:11; /* RO */ 2461 unsigned long part_number:16; /* RO */ 2462 unsigned long revision:4; /* RO */ 2463 unsigned long node_id:15; /* RW */ 2464 unsigned long rsvd_47:1; 2465 unsigned long router_select:1; /* RO */ 2466 unsigned long rsvd_49:1; 2467 unsigned long nodes_per_bit:7; /* RO */ 2468 unsigned long ni_port:5; /* RO */ 2469 unsigned long rsvd_62_63:2; 2470 } s3; 2471 struct uv4h_node_id_s { 2472 unsigned long force1:1; /* RO */ 2473 unsigned long manufacturer:11; /* RO */ 2474 unsigned long part_number:16; /* RO */ 2475 unsigned long revision:4; /* RO */ 2476 unsigned long node_id:15; /* RW */ 2477 unsigned long rsvd_47:1; 2478 unsigned long router_select:1; /* RO */ 2479 unsigned long rsvd_49:1; 2480 unsigned long nodes_per_bit:7; /* RO */ 2481 unsigned long ni_port:5; /* RO */ 2482 unsigned long rsvd_62_63:2; 2483 } s4; 2484 }; 2485 2486 /* ========================================================================= */ 2487 /* UVH_NODE_PRESENT_TABLE */ 2488 /* ========================================================================= */ 2489 #define UVH_NODE_PRESENT_TABLE 0x1400UL 2490 2491 #define UV2H_NODE_PRESENT_TABLE_DEPTH 16 2492 #define UV3H_NODE_PRESENT_TABLE_DEPTH 16 2493 #define UV4H_NODE_PRESENT_TABLE_DEPTH 4 2494 #define UVH_NODE_PRESENT_TABLE_DEPTH ( \ 2495 is_uv2_hub() ? UV2H_NODE_PRESENT_TABLE_DEPTH : \ 2496 is_uv3_hub() ? UV3H_NODE_PRESENT_TABLE_DEPTH : \ 2497 /*is_uv4_hub*/ UV4H_NODE_PRESENT_TABLE_DEPTH) 2498 2499 #define UVH_NODE_PRESENT_TABLE_NODES_SHFT 0 2500 #define UVH_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL 2501 2502 2503 union uvh_node_present_table_u { 2504 unsigned long v; 2505 struct uvh_node_present_table_s { 2506 unsigned long nodes:64; /* RW */ 2507 } s; 2508 }; 2509 2510 /* ========================================================================= */ 2511 /* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR */ 2512 /* ========================================================================= */ 2513 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL 2514 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL 2515 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x4800c8UL 2516 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR ( \ 2517 is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR : \ 2518 is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR : \ 2519 /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR) 2520 2521 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24 2522 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48 2523 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63 2524 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL 2525 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL 2526 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL 2527 2528 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24 2529 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48 2530 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63 2531 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL 2532 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL 2533 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL 2534 2535 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24 2536 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48 2537 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63 2538 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL 2539 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL 2540 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL 2541 2542 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24 2543 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48 2544 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63 2545 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL 2546 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL 2547 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL 2548 2549 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24 2550 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48 2551 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63 2552 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL 2553 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL 2554 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL 2555 2556 2557 union uvh_rh_gam_alias210_overlay_config_0_mmr_u { 2558 unsigned long v; 2559 struct uvh_rh_gam_alias210_overlay_config_0_mmr_s { 2560 unsigned long rsvd_0_23:24; 2561 unsigned long base:8; /* RW */ 2562 unsigned long rsvd_32_47:16; 2563 unsigned long m_alias:5; /* RW */ 2564 unsigned long rsvd_53_62:10; 2565 unsigned long enable:1; /* RW */ 2566 } s; 2567 struct uvxh_rh_gam_alias210_overlay_config_0_mmr_s { 2568 unsigned long rsvd_0_23:24; 2569 unsigned long base:8; /* RW */ 2570 unsigned long rsvd_32_47:16; 2571 unsigned long m_alias:5; /* RW */ 2572 unsigned long rsvd_53_62:10; 2573 unsigned long enable:1; /* RW */ 2574 } sx; 2575 struct uv2h_rh_gam_alias210_overlay_config_0_mmr_s { 2576 unsigned long rsvd_0_23:24; 2577 unsigned long base:8; /* RW */ 2578 unsigned long rsvd_32_47:16; 2579 unsigned long m_alias:5; /* RW */ 2580 unsigned long rsvd_53_62:10; 2581 unsigned long enable:1; /* RW */ 2582 } s2; 2583 struct uv3h_rh_gam_alias210_overlay_config_0_mmr_s { 2584 unsigned long rsvd_0_23:24; 2585 unsigned long base:8; /* RW */ 2586 unsigned long rsvd_32_47:16; 2587 unsigned long m_alias:5; /* RW */ 2588 unsigned long rsvd_53_62:10; 2589 unsigned long enable:1; /* RW */ 2590 } s3; 2591 struct uv4h_rh_gam_alias210_overlay_config_0_mmr_s { 2592 unsigned long rsvd_0_23:24; 2593 unsigned long base:8; /* RW */ 2594 unsigned long rsvd_32_47:16; 2595 unsigned long m_alias:5; /* RW */ 2596 unsigned long rsvd_53_62:10; 2597 unsigned long enable:1; /* RW */ 2598 } s4; 2599 }; 2600 2601 /* ========================================================================= */ 2602 /* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR */ 2603 /* ========================================================================= */ 2604 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL 2605 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL 2606 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x4800d8UL 2607 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR ( \ 2608 is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR : \ 2609 is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR : \ 2610 /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR) 2611 2612 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24 2613 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48 2614 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63 2615 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL 2616 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL 2617 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL 2618 2619 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24 2620 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48 2621 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63 2622 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL 2623 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL 2624 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL 2625 2626 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24 2627 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48 2628 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63 2629 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL 2630 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL 2631 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL 2632 2633 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24 2634 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48 2635 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63 2636 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL 2637 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL 2638 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL 2639 2640 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24 2641 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48 2642 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63 2643 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL 2644 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL 2645 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL 2646 2647 2648 union uvh_rh_gam_alias210_overlay_config_1_mmr_u { 2649 unsigned long v; 2650 struct uvh_rh_gam_alias210_overlay_config_1_mmr_s { 2651 unsigned long rsvd_0_23:24; 2652 unsigned long base:8; /* RW */ 2653 unsigned long rsvd_32_47:16; 2654 unsigned long m_alias:5; /* RW */ 2655 unsigned long rsvd_53_62:10; 2656 unsigned long enable:1; /* RW */ 2657 } s; 2658 struct uvxh_rh_gam_alias210_overlay_config_1_mmr_s { 2659 unsigned long rsvd_0_23:24; 2660 unsigned long base:8; /* RW */ 2661 unsigned long rsvd_32_47:16; 2662 unsigned long m_alias:5; /* RW */ 2663 unsigned long rsvd_53_62:10; 2664 unsigned long enable:1; /* RW */ 2665 } sx; 2666 struct uv2h_rh_gam_alias210_overlay_config_1_mmr_s { 2667 unsigned long rsvd_0_23:24; 2668 unsigned long base:8; /* RW */ 2669 unsigned long rsvd_32_47:16; 2670 unsigned long m_alias:5; /* RW */ 2671 unsigned long rsvd_53_62:10; 2672 unsigned long enable:1; /* RW */ 2673 } s2; 2674 struct uv3h_rh_gam_alias210_overlay_config_1_mmr_s { 2675 unsigned long rsvd_0_23:24; 2676 unsigned long base:8; /* RW */ 2677 unsigned long rsvd_32_47:16; 2678 unsigned long m_alias:5; /* RW */ 2679 unsigned long rsvd_53_62:10; 2680 unsigned long enable:1; /* RW */ 2681 } s3; 2682 struct uv4h_rh_gam_alias210_overlay_config_1_mmr_s { 2683 unsigned long rsvd_0_23:24; 2684 unsigned long base:8; /* RW */ 2685 unsigned long rsvd_32_47:16; 2686 unsigned long m_alias:5; /* RW */ 2687 unsigned long rsvd_53_62:10; 2688 unsigned long enable:1; /* RW */ 2689 } s4; 2690 }; 2691 2692 /* ========================================================================= */ 2693 /* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR */ 2694 /* ========================================================================= */ 2695 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL 2696 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL 2697 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x4800e8UL 2698 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR ( \ 2699 is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR : \ 2700 is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR : \ 2701 /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR) 2702 2703 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24 2704 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48 2705 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63 2706 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL 2707 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL 2708 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL 2709 2710 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24 2711 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48 2712 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63 2713 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL 2714 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL 2715 #define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL 2716 2717 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24 2718 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48 2719 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63 2720 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL 2721 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL 2722 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL 2723 2724 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24 2725 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48 2726 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63 2727 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL 2728 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL 2729 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL 2730 2731 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24 2732 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48 2733 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63 2734 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL 2735 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL 2736 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL 2737 2738 2739 union uvh_rh_gam_alias210_overlay_config_2_mmr_u { 2740 unsigned long v; 2741 struct uvh_rh_gam_alias210_overlay_config_2_mmr_s { 2742 unsigned long rsvd_0_23:24; 2743 unsigned long base:8; /* RW */ 2744 unsigned long rsvd_32_47:16; 2745 unsigned long m_alias:5; /* RW */ 2746 unsigned long rsvd_53_62:10; 2747 unsigned long enable:1; /* RW */ 2748 } s; 2749 struct uvxh_rh_gam_alias210_overlay_config_2_mmr_s { 2750 unsigned long rsvd_0_23:24; 2751 unsigned long base:8; /* RW */ 2752 unsigned long rsvd_32_47:16; 2753 unsigned long m_alias:5; /* RW */ 2754 unsigned long rsvd_53_62:10; 2755 unsigned long enable:1; /* RW */ 2756 } sx; 2757 struct uv2h_rh_gam_alias210_overlay_config_2_mmr_s { 2758 unsigned long rsvd_0_23:24; 2759 unsigned long base:8; /* RW */ 2760 unsigned long rsvd_32_47:16; 2761 unsigned long m_alias:5; /* RW */ 2762 unsigned long rsvd_53_62:10; 2763 unsigned long enable:1; /* RW */ 2764 } s2; 2765 struct uv3h_rh_gam_alias210_overlay_config_2_mmr_s { 2766 unsigned long rsvd_0_23:24; 2767 unsigned long base:8; /* RW */ 2768 unsigned long rsvd_32_47:16; 2769 unsigned long m_alias:5; /* RW */ 2770 unsigned long rsvd_53_62:10; 2771 unsigned long enable:1; /* RW */ 2772 } s3; 2773 struct uv4h_rh_gam_alias210_overlay_config_2_mmr_s { 2774 unsigned long rsvd_0_23:24; 2775 unsigned long base:8; /* RW */ 2776 unsigned long rsvd_32_47:16; 2777 unsigned long m_alias:5; /* RW */ 2778 unsigned long rsvd_53_62:10; 2779 unsigned long enable:1; /* RW */ 2780 } s4; 2781 }; 2782 2783 /* ========================================================================= */ 2784 /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */ 2785 /* ========================================================================= */ 2786 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL 2787 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL 2788 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x4800d0UL 2789 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR ( \ 2790 is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR : \ 2791 is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR : \ 2792 /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR) 2793 2794 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 2795 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL 2796 2797 #define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 2798 #define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL 2799 2800 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 2801 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL 2802 2803 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 2804 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL 2805 2806 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 2807 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL 2808 2809 2810 union uvh_rh_gam_alias210_redirect_config_0_mmr_u { 2811 unsigned long v; 2812 struct uvh_rh_gam_alias210_redirect_config_0_mmr_s { 2813 unsigned long rsvd_0_23:24; 2814 unsigned long dest_base:22; /* RW */ 2815 unsigned long rsvd_46_63:18; 2816 } s; 2817 struct uvxh_rh_gam_alias210_redirect_config_0_mmr_s { 2818 unsigned long rsvd_0_23:24; 2819 unsigned long dest_base:22; /* RW */ 2820 unsigned long rsvd_46_63:18; 2821 } sx; 2822 struct uv2h_rh_gam_alias210_redirect_config_0_mmr_s { 2823 unsigned long rsvd_0_23:24; 2824 unsigned long dest_base:22; /* RW */ 2825 unsigned long rsvd_46_63:18; 2826 } s2; 2827 struct uv3h_rh_gam_alias210_redirect_config_0_mmr_s { 2828 unsigned long rsvd_0_23:24; 2829 unsigned long dest_base:22; /* RW */ 2830 unsigned long rsvd_46_63:18; 2831 } s3; 2832 struct uv4h_rh_gam_alias210_redirect_config_0_mmr_s { 2833 unsigned long rsvd_0_23:24; 2834 unsigned long dest_base:22; /* RW */ 2835 unsigned long rsvd_46_63:18; 2836 } s4; 2837 }; 2838 2839 /* ========================================================================= */ 2840 /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */ 2841 /* ========================================================================= */ 2842 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL 2843 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL 2844 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x4800e0UL 2845 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR ( \ 2846 is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR : \ 2847 is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR : \ 2848 /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR) 2849 2850 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 2851 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL 2852 2853 #define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 2854 #define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL 2855 2856 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 2857 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL 2858 2859 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 2860 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL 2861 2862 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 2863 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL 2864 2865 2866 union uvh_rh_gam_alias210_redirect_config_1_mmr_u { 2867 unsigned long v; 2868 struct uvh_rh_gam_alias210_redirect_config_1_mmr_s { 2869 unsigned long rsvd_0_23:24; 2870 unsigned long dest_base:22; /* RW */ 2871 unsigned long rsvd_46_63:18; 2872 } s; 2873 struct uvxh_rh_gam_alias210_redirect_config_1_mmr_s { 2874 unsigned long rsvd_0_23:24; 2875 unsigned long dest_base:22; /* RW */ 2876 unsigned long rsvd_46_63:18; 2877 } sx; 2878 struct uv2h_rh_gam_alias210_redirect_config_1_mmr_s { 2879 unsigned long rsvd_0_23:24; 2880 unsigned long dest_base:22; /* RW */ 2881 unsigned long rsvd_46_63:18; 2882 } s2; 2883 struct uv3h_rh_gam_alias210_redirect_config_1_mmr_s { 2884 unsigned long rsvd_0_23:24; 2885 unsigned long dest_base:22; /* RW */ 2886 unsigned long rsvd_46_63:18; 2887 } s3; 2888 struct uv4h_rh_gam_alias210_redirect_config_1_mmr_s { 2889 unsigned long rsvd_0_23:24; 2890 unsigned long dest_base:22; /* RW */ 2891 unsigned long rsvd_46_63:18; 2892 } s4; 2893 }; 2894 2895 /* ========================================================================= */ 2896 /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */ 2897 /* ========================================================================= */ 2898 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL 2899 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL 2900 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x4800f0UL 2901 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR ( \ 2902 is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR : \ 2903 is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR : \ 2904 /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR) 2905 2906 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 2907 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL 2908 2909 #define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 2910 #define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL 2911 2912 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 2913 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL 2914 2915 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 2916 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL 2917 2918 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 2919 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL 2920 2921 2922 union uvh_rh_gam_alias210_redirect_config_2_mmr_u { 2923 unsigned long v; 2924 struct uvh_rh_gam_alias210_redirect_config_2_mmr_s { 2925 unsigned long rsvd_0_23:24; 2926 unsigned long dest_base:22; /* RW */ 2927 unsigned long rsvd_46_63:18; 2928 } s; 2929 struct uvxh_rh_gam_alias210_redirect_config_2_mmr_s { 2930 unsigned long rsvd_0_23:24; 2931 unsigned long dest_base:22; /* RW */ 2932 unsigned long rsvd_46_63:18; 2933 } sx; 2934 struct uv2h_rh_gam_alias210_redirect_config_2_mmr_s { 2935 unsigned long rsvd_0_23:24; 2936 unsigned long dest_base:22; /* RW */ 2937 unsigned long rsvd_46_63:18; 2938 } s2; 2939 struct uv3h_rh_gam_alias210_redirect_config_2_mmr_s { 2940 unsigned long rsvd_0_23:24; 2941 unsigned long dest_base:22; /* RW */ 2942 unsigned long rsvd_46_63:18; 2943 } s3; 2944 struct uv4h_rh_gam_alias210_redirect_config_2_mmr_s { 2945 unsigned long rsvd_0_23:24; 2946 unsigned long dest_base:22; /* RW */ 2947 unsigned long rsvd_46_63:18; 2948 } s4; 2949 }; 2950 2951 /* ========================================================================= */ 2952 /* UVH_RH_GAM_CONFIG_MMR */ 2953 /* ========================================================================= */ 2954 #define UV2H_RH_GAM_CONFIG_MMR 0x1600000UL 2955 #define UV3H_RH_GAM_CONFIG_MMR 0x1600000UL 2956 #define UV4H_RH_GAM_CONFIG_MMR 0x480000UL 2957 #define UVH_RH_GAM_CONFIG_MMR ( \ 2958 is_uv2_hub() ? UV2H_RH_GAM_CONFIG_MMR : \ 2959 is_uv3_hub() ? UV3H_RH_GAM_CONFIG_MMR : \ 2960 /*is_uv4_hub*/ UV4H_RH_GAM_CONFIG_MMR) 2961 2962 #define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 2963 #define UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 2964 2965 #define UVXH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 2966 #define UVXH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 2967 2968 #define UV2H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 2969 #define UV2H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 2970 #define UV2H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL 2971 #define UV2H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 2972 2973 #define UV3H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 2974 #define UV3H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 2975 #define UV3H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL 2976 #define UV3H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 2977 2978 #define UV4H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 2979 #define UV4H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 2980 2981 2982 union uvh_rh_gam_config_mmr_u { 2983 unsigned long v; 2984 struct uvh_rh_gam_config_mmr_s { 2985 unsigned long rsvd_0_5:6; 2986 unsigned long n_skt:4; /* RW */ 2987 unsigned long rsvd_10_63:54; 2988 } s; 2989 struct uvxh_rh_gam_config_mmr_s { 2990 unsigned long rsvd_0_5:6; 2991 unsigned long n_skt:4; /* RW */ 2992 unsigned long rsvd_10_63:54; 2993 } sx; 2994 struct uv2h_rh_gam_config_mmr_s { 2995 unsigned long m_skt:6; /* RW */ 2996 unsigned long n_skt:4; /* RW */ 2997 unsigned long rsvd_10_63:54; 2998 } s2; 2999 struct uv3h_rh_gam_config_mmr_s { 3000 unsigned long m_skt:6; /* RW */ 3001 unsigned long n_skt:4; /* RW */ 3002 unsigned long rsvd_10_63:54; 3003 } s3; 3004 struct uv4h_rh_gam_config_mmr_s { 3005 unsigned long rsvd_0_5:6; 3006 unsigned long n_skt:4; /* RW */ 3007 unsigned long rsvd_10_63:54; 3008 } s4; 3009 }; 3010 3011 /* ========================================================================= */ 3012 /* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */ 3013 /* ========================================================================= */ 3014 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL 3015 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL 3016 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x480010UL 3017 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR ( \ 3018 is_uv2_hub() ? UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR : \ 3019 is_uv3_hub() ? UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR : \ 3020 /*is_uv4_hub*/ UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR) 3021 3022 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 3023 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3024 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 3025 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3026 3027 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 3028 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3029 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 3030 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3031 3032 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 3033 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 3034 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3035 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL 3036 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 3037 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3038 3039 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 3040 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 3041 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_MODE_SHFT 62 3042 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3043 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL 3044 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 3045 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_MODE_MASK 0x4000000000000000UL 3046 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3047 3048 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 26 3049 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 3050 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3051 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 3052 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 3053 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3054 3055 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK ( \ 3056 is_uv2_hub() ? UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK : \ 3057 is_uv3_hub() ? UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK : \ 3058 /*is_uv4_hub*/ UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK) 3059 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT ( \ 3060 is_uv2_hub() ? UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT : \ 3061 is_uv3_hub() ? UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT : \ 3062 /*is_uv4_hub*/ UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT) 3063 3064 union uvh_rh_gam_gru_overlay_config_mmr_u { 3065 unsigned long v; 3066 struct uvh_rh_gam_gru_overlay_config_mmr_s { 3067 unsigned long rsvd_0_51:52; 3068 unsigned long n_gru:4; /* RW */ 3069 unsigned long rsvd_56_62:7; 3070 unsigned long enable:1; /* RW */ 3071 } s; 3072 struct uvxh_rh_gam_gru_overlay_config_mmr_s { 3073 unsigned long rsvd_0_45:46; 3074 unsigned long rsvd_46_51:6; 3075 unsigned long n_gru:4; /* RW */ 3076 unsigned long rsvd_56_62:7; 3077 unsigned long enable:1; /* RW */ 3078 } sx; 3079 struct uv2h_rh_gam_gru_overlay_config_mmr_s { 3080 unsigned long rsvd_0_27:28; 3081 unsigned long base:18; /* RW */ 3082 unsigned long rsvd_46_51:6; 3083 unsigned long n_gru:4; /* RW */ 3084 unsigned long rsvd_56_62:7; 3085 unsigned long enable:1; /* RW */ 3086 } s2; 3087 struct uv3h_rh_gam_gru_overlay_config_mmr_s { 3088 unsigned long rsvd_0_27:28; 3089 unsigned long base:18; /* RW */ 3090 unsigned long rsvd_46_51:6; 3091 unsigned long n_gru:4; /* RW */ 3092 unsigned long rsvd_56_61:6; 3093 unsigned long mode:1; /* RW */ 3094 unsigned long enable:1; /* RW */ 3095 } s3; 3096 struct uv4h_rh_gam_gru_overlay_config_mmr_s { 3097 unsigned long rsvd_0_24:25; 3098 unsigned long undef_25:1; /* Undefined */ 3099 unsigned long base:20; /* RW */ 3100 unsigned long rsvd_46_51:6; 3101 unsigned long n_gru:4; /* RW */ 3102 unsigned long rsvd_56_62:7; 3103 unsigned long enable:1; /* RW */ 3104 } s4; 3105 }; 3106 3107 /* ========================================================================= */ 3108 /* UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR */ 3109 /* ========================================================================= */ 3110 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR uv_undefined("UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR") 3111 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR 0x1603000UL 3112 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR 0x483000UL 3113 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR ( \ 3114 is_uv2_hub() ? UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR : \ 3115 is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR : \ 3116 /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR) 3117 3118 3119 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT 26 3120 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT 46 3121 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_SHFT 63 3122 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK 0x00003ffffc000000UL 3123 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK 0x000fc00000000000UL 3124 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK 0x8000000000000000UL 3125 3126 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT 26 3127 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT 46 3128 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_SHFT 63 3129 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK 0x00003ffffc000000UL 3130 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK 0x000fc00000000000UL 3131 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK 0x8000000000000000UL 3132 3133 #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT 52 3134 #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK 0x000ffffffc000000UL 3135 #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK 0x03f0000000000000UL 3136 #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK 0x8000000000000000UL 3137 3138 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT ( \ 3139 is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT : \ 3140 is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT : \ 3141 /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT) 3142 3143 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK ( \ 3144 is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK : \ 3145 is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK : \ 3146 /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK) 3147 3148 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK ( \ 3149 is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK : \ 3150 is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK : \ 3151 /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK) 3152 3153 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK ( \ 3154 is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK : \ 3155 is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK : \ 3156 /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK) 3157 3158 union uvh_rh_gam_mmioh_overlay_config0_mmr_u { 3159 unsigned long v; 3160 struct uv3h_rh_gam_mmioh_overlay_config0_mmr_s { 3161 unsigned long rsvd_0_25:26; 3162 unsigned long base:20; /* RW */ 3163 unsigned long m_io:6; /* RW */ 3164 unsigned long n_io:4; 3165 unsigned long rsvd_56_62:7; 3166 unsigned long enable:1; /* RW */ 3167 } s3; 3168 struct uv4h_rh_gam_mmioh_overlay_config0_mmr_s { 3169 unsigned long rsvd_0_25:26; 3170 unsigned long base:20; /* RW */ 3171 unsigned long m_io:6; /* RW */ 3172 unsigned long n_io:4; 3173 unsigned long rsvd_56_62:7; 3174 unsigned long enable:1; /* RW */ 3175 } s4; 3176 struct uv4ah_rh_gam_mmioh_overlay_config0_mmr_s { 3177 unsigned long rsvd_0_25:26; 3178 unsigned long base:26; /* RW */ 3179 unsigned long m_io:6; /* RW */ 3180 unsigned long n_io:4; 3181 unsigned long undef_62:1; /* Undefined */ 3182 unsigned long enable:1; /* RW */ 3183 } s4a; 3184 }; 3185 3186 /* ========================================================================= */ 3187 /* UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR */ 3188 /* ========================================================================= */ 3189 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR uv_undefined("UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR") 3190 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR 0x1603000UL 3191 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR 0x484000UL 3192 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR ( \ 3193 is_uv2_hub() ? UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR : \ 3194 is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR : \ 3195 /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR) 3196 3197 3198 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_SHFT 26 3199 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT 46 3200 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_SHFT 63 3201 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK 0x00003ffffc000000UL 3202 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK 0x000fc00000000000UL 3203 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_MASK 0x8000000000000000UL 3204 3205 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_SHFT 26 3206 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT 46 3207 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_SHFT 63 3208 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK 0x00003ffffc000000UL 3209 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK 0x000fc00000000000UL 3210 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_MASK 0x8000000000000000UL 3211 3212 #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT 52 3213 #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK 0x000ffffffc000000UL 3214 #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK 0x03f0000000000000UL 3215 3216 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT ( \ 3217 is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT : \ 3218 is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT : \ 3219 /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT) 3220 3221 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK ( \ 3222 is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK : \ 3223 is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK : \ 3224 /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK) 3225 3226 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK ( \ 3227 is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK : \ 3228 is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK : \ 3229 /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK) 3230 3231 union uvh_rh_gam_mmioh_overlay_config1_mmr_u { 3232 unsigned long v; 3233 struct uv3h_rh_gam_mmioh_overlay_config1_mmr_s { 3234 unsigned long rsvd_0_25:26; 3235 unsigned long base:20; /* RW */ 3236 unsigned long m_io:6; /* RW */ 3237 unsigned long n_io:4; 3238 unsigned long rsvd_56_62:7; 3239 unsigned long enable:1; /* RW */ 3240 } s3; 3241 struct uv4h_rh_gam_mmioh_overlay_config1_mmr_s { 3242 unsigned long rsvd_0_25:26; 3243 unsigned long base:20; /* RW */ 3244 unsigned long m_io:6; /* RW */ 3245 unsigned long n_io:4; 3246 unsigned long rsvd_56_62:7; 3247 unsigned long enable:1; /* RW */ 3248 } s4; 3249 struct uv4ah_rh_gam_mmioh_overlay_config1_mmr_s { 3250 unsigned long rsvd_0_25:26; 3251 unsigned long base:26; /* RW */ 3252 unsigned long m_io:6; /* RW */ 3253 unsigned long n_io:4; 3254 unsigned long undef_62:1; /* Undefined */ 3255 unsigned long enable:1; /* RW */ 3256 } s4a; 3257 }; 3258 3259 /* ========================================================================= */ 3260 /* UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR */ 3261 /* ========================================================================= */ 3262 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL 3263 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR uv_undefined("UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR") 3264 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR uv_undefined("UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR") 3265 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR ( \ 3266 is_uv2_hub() ? UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR : \ 3267 is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR : \ 3268 /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR) 3269 3270 3271 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 27 3272 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46 3273 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52 3274 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3275 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff8000000UL 3276 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL 3277 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL 3278 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3279 3280 3281 union uvh_rh_gam_mmioh_overlay_config_mmr_u { 3282 unsigned long v; 3283 struct uv2h_rh_gam_mmioh_overlay_config_mmr_s { 3284 unsigned long rsvd_0_26:27; 3285 unsigned long base:19; /* RW */ 3286 unsigned long m_io:6; /* RW */ 3287 unsigned long n_io:4; /* RW */ 3288 unsigned long rsvd_56_62:7; 3289 unsigned long enable:1; /* RW */ 3290 } s2; 3291 }; 3292 3293 /* ========================================================================= */ 3294 /* UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR */ 3295 /* ========================================================================= */ 3296 #define UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR uv_undefined("UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR") 3297 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR 0x1603800UL 3298 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR 0x483800UL 3299 #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR ( \ 3300 is_uv2_hub() ? UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR : \ 3301 is_uv3_hub() ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR : \ 3302 /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR) 3303 3304 #define UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH uv_undefined("UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH") 3305 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH 128 3306 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH 128 3307 #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH ( \ 3308 is_uv2_hub() ? UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH : \ 3309 is_uv3_hub() ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH : \ 3310 /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH) 3311 3312 3313 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_SHFT 0 3314 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK 0x0000000000007fffUL 3315 3316 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_SHFT 0 3317 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK 0x0000000000007fffUL 3318 3319 #define UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK 0x0000000000000fffUL 3320 3321 #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK ( \ 3322 is_uv3_hub() ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK : \ 3323 is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK : \ 3324 /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK) 3325 3326 union uvh_rh_gam_mmioh_redirect_config0_mmr_u { 3327 unsigned long v; 3328 struct uv3h_rh_gam_mmioh_redirect_config0_mmr_s { 3329 unsigned long nasid:15; /* RW */ 3330 unsigned long rsvd_15_63:49; 3331 } s3; 3332 struct uv4h_rh_gam_mmioh_redirect_config0_mmr_s { 3333 unsigned long nasid:15; /* RW */ 3334 unsigned long rsvd_15_63:49; 3335 } s4; 3336 struct uv4ah_rh_gam_mmioh_redirect_config0_mmr_s { 3337 unsigned long nasid:12; /* RW */ 3338 unsigned long rsvd_12_63:52; 3339 } s4a; 3340 }; 3341 3342 /* ========================================================================= */ 3343 /* UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR */ 3344 /* ========================================================================= */ 3345 #define UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR uv_undefined("UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR") 3346 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR 0x1604800UL 3347 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR 0x484800UL 3348 #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR ( \ 3349 is_uv2_hub() ? UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR : \ 3350 is_uv3_hub() ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR : \ 3351 /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR) 3352 3353 #define UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH uv_undefined("UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH") 3354 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH 128 3355 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH 128 3356 #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH ( \ 3357 is_uv2_hub() ? UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH : \ 3358 is_uv3_hub() ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH : \ 3359 /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH) 3360 3361 3362 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_SHFT 0 3363 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK 0x0000000000007fffUL 3364 3365 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_SHFT 0 3366 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK 0x0000000000007fffUL 3367 3368 #define UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK 0x0000000000000fffUL 3369 3370 #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK ( \ 3371 is_uv3_hub() ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK : \ 3372 is_uv4a_hub() ? UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK : \ 3373 /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK) 3374 3375 union uvh_rh_gam_mmioh_redirect_config1_mmr_u { 3376 unsigned long v; 3377 struct uv3h_rh_gam_mmioh_redirect_config1_mmr_s { 3378 unsigned long nasid:15; /* RW */ 3379 unsigned long rsvd_15_63:49; 3380 } s3; 3381 struct uv4h_rh_gam_mmioh_redirect_config1_mmr_s { 3382 unsigned long nasid:15; /* RW */ 3383 unsigned long rsvd_15_63:49; 3384 } s4; 3385 struct uv4ah_rh_gam_mmioh_redirect_config1_mmr_s { 3386 unsigned long nasid:12; /* RW */ 3387 unsigned long rsvd_12_63:52; 3388 } s4a; 3389 }; 3390 3391 /* ========================================================================= */ 3392 /* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */ 3393 /* ========================================================================= */ 3394 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL 3395 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL 3396 #define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x480028UL 3397 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR ( \ 3398 is_uv2_hub() ? UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR : \ 3399 is_uv3_hub() ? UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR : \ 3400 /*is_uv4_hub*/ UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR) 3401 3402 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 3403 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3404 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 3405 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3406 3407 #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 3408 #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3409 #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 3410 #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3411 3412 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 3413 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3414 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 3415 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3416 3417 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 3418 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3419 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 3420 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3421 3422 #define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 3423 #define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3424 #define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 3425 #define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3426 3427 3428 union uvh_rh_gam_mmr_overlay_config_mmr_u { 3429 unsigned long v; 3430 struct uvh_rh_gam_mmr_overlay_config_mmr_s { 3431 unsigned long rsvd_0_25:26; 3432 unsigned long base:20; /* RW */ 3433 unsigned long rsvd_46_62:17; 3434 unsigned long enable:1; /* RW */ 3435 } s; 3436 struct uvxh_rh_gam_mmr_overlay_config_mmr_s { 3437 unsigned long rsvd_0_25:26; 3438 unsigned long base:20; /* RW */ 3439 unsigned long rsvd_46_62:17; 3440 unsigned long enable:1; /* RW */ 3441 } sx; 3442 struct uv2h_rh_gam_mmr_overlay_config_mmr_s { 3443 unsigned long rsvd_0_25:26; 3444 unsigned long base:20; /* RW */ 3445 unsigned long rsvd_46_62:17; 3446 unsigned long enable:1; /* RW */ 3447 } s2; 3448 struct uv3h_rh_gam_mmr_overlay_config_mmr_s { 3449 unsigned long rsvd_0_25:26; 3450 unsigned long base:20; /* RW */ 3451 unsigned long rsvd_46_62:17; 3452 unsigned long enable:1; /* RW */ 3453 } s3; 3454 struct uv4h_rh_gam_mmr_overlay_config_mmr_s { 3455 unsigned long rsvd_0_25:26; 3456 unsigned long base:20; /* RW */ 3457 unsigned long rsvd_46_62:17; 3458 unsigned long enable:1; /* RW */ 3459 } s4; 3460 }; 3461 3462 /* ========================================================================= */ 3463 /* UVH_RTC */ 3464 /* ========================================================================= */ 3465 #define UV2H_RTC 0x340000UL 3466 #define UV3H_RTC 0x340000UL 3467 #define UV4H_RTC 0xe0000UL 3468 #define UVH_RTC ( \ 3469 is_uv2_hub() ? UV2H_RTC : \ 3470 is_uv3_hub() ? UV3H_RTC : \ 3471 /*is_uv4_hub*/ UV4H_RTC) 3472 3473 #define UVH_RTC_REAL_TIME_CLOCK_SHFT 0 3474 #define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL 3475 3476 3477 union uvh_rtc_u { 3478 unsigned long v; 3479 struct uvh_rtc_s { 3480 unsigned long real_time_clock:56; /* RW */ 3481 unsigned long rsvd_56_63:8; 3482 } s; 3483 }; 3484 3485 /* ========================================================================= */ 3486 /* UVH_RTC1_INT_CONFIG */ 3487 /* ========================================================================= */ 3488 #define UVH_RTC1_INT_CONFIG 0x615c0UL 3489 3490 #define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0 3491 #define UVH_RTC1_INT_CONFIG_DM_SHFT 8 3492 #define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT 11 3493 #define UVH_RTC1_INT_CONFIG_STATUS_SHFT 12 3494 #define UVH_RTC1_INT_CONFIG_P_SHFT 13 3495 #define UVH_RTC1_INT_CONFIG_T_SHFT 15 3496 #define UVH_RTC1_INT_CONFIG_M_SHFT 16 3497 #define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT 32 3498 #define UVH_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL 3499 #define UVH_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL 3500 #define UVH_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL 3501 #define UVH_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL 3502 #define UVH_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL 3503 #define UVH_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL 3504 #define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL 3505 #define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 3506 3507 3508 union uvh_rtc1_int_config_u { 3509 unsigned long v; 3510 struct uvh_rtc1_int_config_s { 3511 unsigned long vector_:8; /* RW */ 3512 unsigned long dm:3; /* RW */ 3513 unsigned long destmode:1; /* RW */ 3514 unsigned long status:1; /* RO */ 3515 unsigned long p:1; /* RO */ 3516 unsigned long rsvd_14:1; 3517 unsigned long t:1; /* RO */ 3518 unsigned long m:1; /* RW */ 3519 unsigned long rsvd_17_31:15; 3520 unsigned long apic_id:32; /* RW */ 3521 } s; 3522 }; 3523 3524 /* ========================================================================= */ 3525 /* UVH_SCRATCH5 */ 3526 /* ========================================================================= */ 3527 #define UV2H_SCRATCH5 0x2d0200UL 3528 #define UV3H_SCRATCH5 0x2d0200UL 3529 #define UV4H_SCRATCH5 0xb0200UL 3530 #define UVH_SCRATCH5 ( \ 3531 is_uv2_hub() ? UV2H_SCRATCH5 : \ 3532 is_uv3_hub() ? UV3H_SCRATCH5 : \ 3533 /*is_uv4_hub*/ UV4H_SCRATCH5) 3534 3535 #define UV2H_SCRATCH5_32 0x778 3536 #define UV3H_SCRATCH5_32 0x778 3537 #define UV4H_SCRATCH5_32 0x798 3538 #define UVH_SCRATCH5_32 ( \ 3539 is_uv2_hub() ? UV2H_SCRATCH5_32 : \ 3540 is_uv3_hub() ? UV3H_SCRATCH5_32 : \ 3541 /*is_uv4_hub*/ UV4H_SCRATCH5_32) 3542 3543 #define UVH_SCRATCH5_SCRATCH5_SHFT 0 3544 #define UVH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL 3545 3546 3547 union uvh_scratch5_u { 3548 unsigned long v; 3549 struct uvh_scratch5_s { 3550 unsigned long scratch5:64; /* RW, W1CS */ 3551 } s; 3552 }; 3553 3554 /* ========================================================================= */ 3555 /* UVH_SCRATCH5_ALIAS */ 3556 /* ========================================================================= */ 3557 #define UV2H_SCRATCH5_ALIAS 0x2d0208UL 3558 #define UV3H_SCRATCH5_ALIAS 0x2d0208UL 3559 #define UV4H_SCRATCH5_ALIAS 0xb0208UL 3560 #define UVH_SCRATCH5_ALIAS ( \ 3561 is_uv2_hub() ? UV2H_SCRATCH5_ALIAS : \ 3562 is_uv3_hub() ? UV3H_SCRATCH5_ALIAS : \ 3563 /*is_uv4_hub*/ UV4H_SCRATCH5_ALIAS) 3564 3565 #define UV2H_SCRATCH5_ALIAS_32 0x780 3566 #define UV3H_SCRATCH5_ALIAS_32 0x780 3567 #define UV4H_SCRATCH5_ALIAS_32 0x7a0 3568 #define UVH_SCRATCH5_ALIAS_32 ( \ 3569 is_uv2_hub() ? UV2H_SCRATCH5_ALIAS_32 : \ 3570 is_uv3_hub() ? UV3H_SCRATCH5_ALIAS_32 : \ 3571 /*is_uv4_hub*/ UV4H_SCRATCH5_ALIAS_32) 3572 3573 3574 /* ========================================================================= */ 3575 /* UVH_SCRATCH5_ALIAS_2 */ 3576 /* ========================================================================= */ 3577 #define UV2H_SCRATCH5_ALIAS_2 0x2d0210UL 3578 #define UV3H_SCRATCH5_ALIAS_2 0x2d0210UL 3579 #define UV4H_SCRATCH5_ALIAS_2 0xb0210UL 3580 #define UVH_SCRATCH5_ALIAS_2 ( \ 3581 is_uv2_hub() ? UV2H_SCRATCH5_ALIAS_2 : \ 3582 is_uv3_hub() ? UV3H_SCRATCH5_ALIAS_2 : \ 3583 /*is_uv4_hub*/ UV4H_SCRATCH5_ALIAS_2) 3584 #define UVH_SCRATCH5_ALIAS_2_32 0x788 3585 3586 3587 /* ========================================================================= */ 3588 /* UVXH_EVENT_OCCURRED2 */ 3589 /* ========================================================================= */ 3590 #define UVXH_EVENT_OCCURRED2 0x70100UL 3591 3592 #define UV2H_EVENT_OCCURRED2_32 0xb68 3593 #define UV3H_EVENT_OCCURRED2_32 0xb68 3594 #define UV4H_EVENT_OCCURRED2_32 0x608 3595 #define UVH_EVENT_OCCURRED2_32 ( \ 3596 is_uv2_hub() ? UV2H_EVENT_OCCURRED2_32 : \ 3597 is_uv3_hub() ? UV3H_EVENT_OCCURRED2_32 : \ 3598 /*is_uv4_hub*/ UV4H_EVENT_OCCURRED2_32) 3599 3600 3601 #define UV2H_EVENT_OCCURRED2_RTC_0_SHFT 0 3602 #define UV2H_EVENT_OCCURRED2_RTC_1_SHFT 1 3603 #define UV2H_EVENT_OCCURRED2_RTC_2_SHFT 2 3604 #define UV2H_EVENT_OCCURRED2_RTC_3_SHFT 3 3605 #define UV2H_EVENT_OCCURRED2_RTC_4_SHFT 4 3606 #define UV2H_EVENT_OCCURRED2_RTC_5_SHFT 5 3607 #define UV2H_EVENT_OCCURRED2_RTC_6_SHFT 6 3608 #define UV2H_EVENT_OCCURRED2_RTC_7_SHFT 7 3609 #define UV2H_EVENT_OCCURRED2_RTC_8_SHFT 8 3610 #define UV2H_EVENT_OCCURRED2_RTC_9_SHFT 9 3611 #define UV2H_EVENT_OCCURRED2_RTC_10_SHFT 10 3612 #define UV2H_EVENT_OCCURRED2_RTC_11_SHFT 11 3613 #define UV2H_EVENT_OCCURRED2_RTC_12_SHFT 12 3614 #define UV2H_EVENT_OCCURRED2_RTC_13_SHFT 13 3615 #define UV2H_EVENT_OCCURRED2_RTC_14_SHFT 14 3616 #define UV2H_EVENT_OCCURRED2_RTC_15_SHFT 15 3617 #define UV2H_EVENT_OCCURRED2_RTC_16_SHFT 16 3618 #define UV2H_EVENT_OCCURRED2_RTC_17_SHFT 17 3619 #define UV2H_EVENT_OCCURRED2_RTC_18_SHFT 18 3620 #define UV2H_EVENT_OCCURRED2_RTC_19_SHFT 19 3621 #define UV2H_EVENT_OCCURRED2_RTC_20_SHFT 20 3622 #define UV2H_EVENT_OCCURRED2_RTC_21_SHFT 21 3623 #define UV2H_EVENT_OCCURRED2_RTC_22_SHFT 22 3624 #define UV2H_EVENT_OCCURRED2_RTC_23_SHFT 23 3625 #define UV2H_EVENT_OCCURRED2_RTC_24_SHFT 24 3626 #define UV2H_EVENT_OCCURRED2_RTC_25_SHFT 25 3627 #define UV2H_EVENT_OCCURRED2_RTC_26_SHFT 26 3628 #define UV2H_EVENT_OCCURRED2_RTC_27_SHFT 27 3629 #define UV2H_EVENT_OCCURRED2_RTC_28_SHFT 28 3630 #define UV2H_EVENT_OCCURRED2_RTC_29_SHFT 29 3631 #define UV2H_EVENT_OCCURRED2_RTC_30_SHFT 30 3632 #define UV2H_EVENT_OCCURRED2_RTC_31_SHFT 31 3633 #define UV2H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL 3634 #define UV2H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL 3635 #define UV2H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL 3636 #define UV2H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL 3637 #define UV2H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL 3638 #define UV2H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL 3639 #define UV2H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL 3640 #define UV2H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL 3641 #define UV2H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL 3642 #define UV2H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL 3643 #define UV2H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL 3644 #define UV2H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL 3645 #define UV2H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL 3646 #define UV2H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL 3647 #define UV2H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL 3648 #define UV2H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL 3649 #define UV2H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL 3650 #define UV2H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL 3651 #define UV2H_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL 3652 #define UV2H_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL 3653 #define UV2H_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL 3654 #define UV2H_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL 3655 #define UV2H_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL 3656 #define UV2H_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL 3657 #define UV2H_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL 3658 #define UV2H_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL 3659 #define UV2H_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL 3660 #define UV2H_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL 3661 #define UV2H_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL 3662 #define UV2H_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL 3663 #define UV2H_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL 3664 #define UV2H_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL 3665 3666 #define UV3H_EVENT_OCCURRED2_RTC_0_SHFT 0 3667 #define UV3H_EVENT_OCCURRED2_RTC_1_SHFT 1 3668 #define UV3H_EVENT_OCCURRED2_RTC_2_SHFT 2 3669 #define UV3H_EVENT_OCCURRED2_RTC_3_SHFT 3 3670 #define UV3H_EVENT_OCCURRED2_RTC_4_SHFT 4 3671 #define UV3H_EVENT_OCCURRED2_RTC_5_SHFT 5 3672 #define UV3H_EVENT_OCCURRED2_RTC_6_SHFT 6 3673 #define UV3H_EVENT_OCCURRED2_RTC_7_SHFT 7 3674 #define UV3H_EVENT_OCCURRED2_RTC_8_SHFT 8 3675 #define UV3H_EVENT_OCCURRED2_RTC_9_SHFT 9 3676 #define UV3H_EVENT_OCCURRED2_RTC_10_SHFT 10 3677 #define UV3H_EVENT_OCCURRED2_RTC_11_SHFT 11 3678 #define UV3H_EVENT_OCCURRED2_RTC_12_SHFT 12 3679 #define UV3H_EVENT_OCCURRED2_RTC_13_SHFT 13 3680 #define UV3H_EVENT_OCCURRED2_RTC_14_SHFT 14 3681 #define UV3H_EVENT_OCCURRED2_RTC_15_SHFT 15 3682 #define UV3H_EVENT_OCCURRED2_RTC_16_SHFT 16 3683 #define UV3H_EVENT_OCCURRED2_RTC_17_SHFT 17 3684 #define UV3H_EVENT_OCCURRED2_RTC_18_SHFT 18 3685 #define UV3H_EVENT_OCCURRED2_RTC_19_SHFT 19 3686 #define UV3H_EVENT_OCCURRED2_RTC_20_SHFT 20 3687 #define UV3H_EVENT_OCCURRED2_RTC_21_SHFT 21 3688 #define UV3H_EVENT_OCCURRED2_RTC_22_SHFT 22 3689 #define UV3H_EVENT_OCCURRED2_RTC_23_SHFT 23 3690 #define UV3H_EVENT_OCCURRED2_RTC_24_SHFT 24 3691 #define UV3H_EVENT_OCCURRED2_RTC_25_SHFT 25 3692 #define UV3H_EVENT_OCCURRED2_RTC_26_SHFT 26 3693 #define UV3H_EVENT_OCCURRED2_RTC_27_SHFT 27 3694 #define UV3H_EVENT_OCCURRED2_RTC_28_SHFT 28 3695 #define UV3H_EVENT_OCCURRED2_RTC_29_SHFT 29 3696 #define UV3H_EVENT_OCCURRED2_RTC_30_SHFT 30 3697 #define UV3H_EVENT_OCCURRED2_RTC_31_SHFT 31 3698 #define UV3H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL 3699 #define UV3H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL 3700 #define UV3H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL 3701 #define UV3H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL 3702 #define UV3H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL 3703 #define UV3H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL 3704 #define UV3H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL 3705 #define UV3H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL 3706 #define UV3H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL 3707 #define UV3H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL 3708 #define UV3H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL 3709 #define UV3H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL 3710 #define UV3H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL 3711 #define UV3H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL 3712 #define UV3H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL 3713 #define UV3H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL 3714 #define UV3H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL 3715 #define UV3H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL 3716 #define UV3H_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL 3717 #define UV3H_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL 3718 #define UV3H_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL 3719 #define UV3H_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL 3720 #define UV3H_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL 3721 #define UV3H_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL 3722 #define UV3H_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL 3723 #define UV3H_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL 3724 #define UV3H_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL 3725 #define UV3H_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL 3726 #define UV3H_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL 3727 #define UV3H_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL 3728 #define UV3H_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL 3729 #define UV3H_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL 3730 3731 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT0_SHFT 0 3732 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT1_SHFT 1 3733 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT2_SHFT 2 3734 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT3_SHFT 3 3735 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT4_SHFT 4 3736 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT5_SHFT 5 3737 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT6_SHFT 6 3738 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT7_SHFT 7 3739 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT8_SHFT 8 3740 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT9_SHFT 9 3741 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT10_SHFT 10 3742 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT11_SHFT 11 3743 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT12_SHFT 12 3744 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT13_SHFT 13 3745 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT14_SHFT 14 3746 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT15_SHFT 15 3747 #define UV4H_EVENT_OCCURRED2_RTC_INTERVAL_INT_SHFT 16 3748 #define UV4H_EVENT_OCCURRED2_BAU_DASHBOARD_INT_SHFT 17 3749 #define UV4H_EVENT_OCCURRED2_RTC_0_SHFT 18 3750 #define UV4H_EVENT_OCCURRED2_RTC_1_SHFT 19 3751 #define UV4H_EVENT_OCCURRED2_RTC_2_SHFT 20 3752 #define UV4H_EVENT_OCCURRED2_RTC_3_SHFT 21 3753 #define UV4H_EVENT_OCCURRED2_RTC_4_SHFT 22 3754 #define UV4H_EVENT_OCCURRED2_RTC_5_SHFT 23 3755 #define UV4H_EVENT_OCCURRED2_RTC_6_SHFT 24 3756 #define UV4H_EVENT_OCCURRED2_RTC_7_SHFT 25 3757 #define UV4H_EVENT_OCCURRED2_RTC_8_SHFT 26 3758 #define UV4H_EVENT_OCCURRED2_RTC_9_SHFT 27 3759 #define UV4H_EVENT_OCCURRED2_RTC_10_SHFT 28 3760 #define UV4H_EVENT_OCCURRED2_RTC_11_SHFT 29 3761 #define UV4H_EVENT_OCCURRED2_RTC_12_SHFT 30 3762 #define UV4H_EVENT_OCCURRED2_RTC_13_SHFT 31 3763 #define UV4H_EVENT_OCCURRED2_RTC_14_SHFT 32 3764 #define UV4H_EVENT_OCCURRED2_RTC_15_SHFT 33 3765 #define UV4H_EVENT_OCCURRED2_RTC_16_SHFT 34 3766 #define UV4H_EVENT_OCCURRED2_RTC_17_SHFT 35 3767 #define UV4H_EVENT_OCCURRED2_RTC_18_SHFT 36 3768 #define UV4H_EVENT_OCCURRED2_RTC_19_SHFT 37 3769 #define UV4H_EVENT_OCCURRED2_RTC_20_SHFT 38 3770 #define UV4H_EVENT_OCCURRED2_RTC_21_SHFT 39 3771 #define UV4H_EVENT_OCCURRED2_RTC_22_SHFT 40 3772 #define UV4H_EVENT_OCCURRED2_RTC_23_SHFT 41 3773 #define UV4H_EVENT_OCCURRED2_RTC_24_SHFT 42 3774 #define UV4H_EVENT_OCCURRED2_RTC_25_SHFT 43 3775 #define UV4H_EVENT_OCCURRED2_RTC_26_SHFT 44 3776 #define UV4H_EVENT_OCCURRED2_RTC_27_SHFT 45 3777 #define UV4H_EVENT_OCCURRED2_RTC_28_SHFT 46 3778 #define UV4H_EVENT_OCCURRED2_RTC_29_SHFT 47 3779 #define UV4H_EVENT_OCCURRED2_RTC_30_SHFT 48 3780 #define UV4H_EVENT_OCCURRED2_RTC_31_SHFT 49 3781 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT0_MASK 0x0000000000000001UL 3782 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT1_MASK 0x0000000000000002UL 3783 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT2_MASK 0x0000000000000004UL 3784 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT3_MASK 0x0000000000000008UL 3785 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT4_MASK 0x0000000000000010UL 3786 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT5_MASK 0x0000000000000020UL 3787 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT6_MASK 0x0000000000000040UL 3788 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT7_MASK 0x0000000000000080UL 3789 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT8_MASK 0x0000000000000100UL 3790 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT9_MASK 0x0000000000000200UL 3791 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT10_MASK 0x0000000000000400UL 3792 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT11_MASK 0x0000000000000800UL 3793 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT12_MASK 0x0000000000001000UL 3794 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT13_MASK 0x0000000000002000UL 3795 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT14_MASK 0x0000000000004000UL 3796 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT15_MASK 0x0000000000008000UL 3797 #define UV4H_EVENT_OCCURRED2_RTC_INTERVAL_INT_MASK 0x0000000000010000UL 3798 #define UV4H_EVENT_OCCURRED2_BAU_DASHBOARD_INT_MASK 0x0000000000020000UL 3799 #define UV4H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000040000UL 3800 #define UV4H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000080000UL 3801 #define UV4H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000100000UL 3802 #define UV4H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000200000UL 3803 #define UV4H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000400000UL 3804 #define UV4H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000800000UL 3805 #define UV4H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000001000000UL 3806 #define UV4H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000002000000UL 3807 #define UV4H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000004000000UL 3808 #define UV4H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000008000000UL 3809 #define UV4H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000010000000UL 3810 #define UV4H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000020000000UL 3811 #define UV4H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000040000000UL 3812 #define UV4H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000080000000UL 3813 #define UV4H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000100000000UL 3814 #define UV4H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000200000000UL 3815 #define UV4H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000400000000UL 3816 #define UV4H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000800000000UL 3817 #define UV4H_EVENT_OCCURRED2_RTC_18_MASK 0x0000001000000000UL 3818 #define UV4H_EVENT_OCCURRED2_RTC_19_MASK 0x0000002000000000UL 3819 #define UV4H_EVENT_OCCURRED2_RTC_20_MASK 0x0000004000000000UL 3820 #define UV4H_EVENT_OCCURRED2_RTC_21_MASK 0x0000008000000000UL 3821 #define UV4H_EVENT_OCCURRED2_RTC_22_MASK 0x0000010000000000UL 3822 #define UV4H_EVENT_OCCURRED2_RTC_23_MASK 0x0000020000000000UL 3823 #define UV4H_EVENT_OCCURRED2_RTC_24_MASK 0x0000040000000000UL 3824 #define UV4H_EVENT_OCCURRED2_RTC_25_MASK 0x0000080000000000UL 3825 #define UV4H_EVENT_OCCURRED2_RTC_26_MASK 0x0000100000000000UL 3826 #define UV4H_EVENT_OCCURRED2_RTC_27_MASK 0x0000200000000000UL 3827 #define UV4H_EVENT_OCCURRED2_RTC_28_MASK 0x0000400000000000UL 3828 #define UV4H_EVENT_OCCURRED2_RTC_29_MASK 0x0000800000000000UL 3829 #define UV4H_EVENT_OCCURRED2_RTC_30_MASK 0x0001000000000000UL 3830 #define UV4H_EVENT_OCCURRED2_RTC_31_MASK 0x0002000000000000UL 3831 3832 #define UVXH_EVENT_OCCURRED2_RTC_1_MASK ( \ 3833 is_uv2_hub() ? UV2H_EVENT_OCCURRED2_RTC_1_MASK : \ 3834 is_uv3_hub() ? UV3H_EVENT_OCCURRED2_RTC_1_MASK : \ 3835 /*is_uv4_hub*/ UV4H_EVENT_OCCURRED2_RTC_1_MASK) 3836 3837 union uvh_event_occurred2_u { 3838 unsigned long v; 3839 struct uv2h_event_occurred2_s { 3840 unsigned long rtc_0:1; /* RW */ 3841 unsigned long rtc_1:1; /* RW */ 3842 unsigned long rtc_2:1; /* RW */ 3843 unsigned long rtc_3:1; /* RW */ 3844 unsigned long rtc_4:1; /* RW */ 3845 unsigned long rtc_5:1; /* RW */ 3846 unsigned long rtc_6:1; /* RW */ 3847 unsigned long rtc_7:1; /* RW */ 3848 unsigned long rtc_8:1; /* RW */ 3849 unsigned long rtc_9:1; /* RW */ 3850 unsigned long rtc_10:1; /* RW */ 3851 unsigned long rtc_11:1; /* RW */ 3852 unsigned long rtc_12:1; /* RW */ 3853 unsigned long rtc_13:1; /* RW */ 3854 unsigned long rtc_14:1; /* RW */ 3855 unsigned long rtc_15:1; /* RW */ 3856 unsigned long rtc_16:1; /* RW */ 3857 unsigned long rtc_17:1; /* RW */ 3858 unsigned long rtc_18:1; /* RW */ 3859 unsigned long rtc_19:1; /* RW */ 3860 unsigned long rtc_20:1; /* RW */ 3861 unsigned long rtc_21:1; /* RW */ 3862 unsigned long rtc_22:1; /* RW */ 3863 unsigned long rtc_23:1; /* RW */ 3864 unsigned long rtc_24:1; /* RW */ 3865 unsigned long rtc_25:1; /* RW */ 3866 unsigned long rtc_26:1; /* RW */ 3867 unsigned long rtc_27:1; /* RW */ 3868 unsigned long rtc_28:1; /* RW */ 3869 unsigned long rtc_29:1; /* RW */ 3870 unsigned long rtc_30:1; /* RW */ 3871 unsigned long rtc_31:1; /* RW */ 3872 unsigned long rsvd_32_63:32; 3873 } s2; 3874 struct uv3h_event_occurred2_s { 3875 unsigned long rtc_0:1; /* RW */ 3876 unsigned long rtc_1:1; /* RW */ 3877 unsigned long rtc_2:1; /* RW */ 3878 unsigned long rtc_3:1; /* RW */ 3879 unsigned long rtc_4:1; /* RW */ 3880 unsigned long rtc_5:1; /* RW */ 3881 unsigned long rtc_6:1; /* RW */ 3882 unsigned long rtc_7:1; /* RW */ 3883 unsigned long rtc_8:1; /* RW */ 3884 unsigned long rtc_9:1; /* RW */ 3885 unsigned long rtc_10:1; /* RW */ 3886 unsigned long rtc_11:1; /* RW */ 3887 unsigned long rtc_12:1; /* RW */ 3888 unsigned long rtc_13:1; /* RW */ 3889 unsigned long rtc_14:1; /* RW */ 3890 unsigned long rtc_15:1; /* RW */ 3891 unsigned long rtc_16:1; /* RW */ 3892 unsigned long rtc_17:1; /* RW */ 3893 unsigned long rtc_18:1; /* RW */ 3894 unsigned long rtc_19:1; /* RW */ 3895 unsigned long rtc_20:1; /* RW */ 3896 unsigned long rtc_21:1; /* RW */ 3897 unsigned long rtc_22:1; /* RW */ 3898 unsigned long rtc_23:1; /* RW */ 3899 unsigned long rtc_24:1; /* RW */ 3900 unsigned long rtc_25:1; /* RW */ 3901 unsigned long rtc_26:1; /* RW */ 3902 unsigned long rtc_27:1; /* RW */ 3903 unsigned long rtc_28:1; /* RW */ 3904 unsigned long rtc_29:1; /* RW */ 3905 unsigned long rtc_30:1; /* RW */ 3906 unsigned long rtc_31:1; /* RW */ 3907 unsigned long rsvd_32_63:32; 3908 } s3; 3909 struct uv4h_event_occurred2_s { 3910 unsigned long message_accelerator_int0:1; /* RW */ 3911 unsigned long message_accelerator_int1:1; /* RW */ 3912 unsigned long message_accelerator_int2:1; /* RW */ 3913 unsigned long message_accelerator_int3:1; /* RW */ 3914 unsigned long message_accelerator_int4:1; /* RW */ 3915 unsigned long message_accelerator_int5:1; /* RW */ 3916 unsigned long message_accelerator_int6:1; /* RW */ 3917 unsigned long message_accelerator_int7:1; /* RW */ 3918 unsigned long message_accelerator_int8:1; /* RW */ 3919 unsigned long message_accelerator_int9:1; /* RW */ 3920 unsigned long message_accelerator_int10:1; /* RW */ 3921 unsigned long message_accelerator_int11:1; /* RW */ 3922 unsigned long message_accelerator_int12:1; /* RW */ 3923 unsigned long message_accelerator_int13:1; /* RW */ 3924 unsigned long message_accelerator_int14:1; /* RW */ 3925 unsigned long message_accelerator_int15:1; /* RW */ 3926 unsigned long rtc_interval_int:1; /* RW */ 3927 unsigned long bau_dashboard_int:1; /* RW */ 3928 unsigned long rtc_0:1; /* RW */ 3929 unsigned long rtc_1:1; /* RW */ 3930 unsigned long rtc_2:1; /* RW */ 3931 unsigned long rtc_3:1; /* RW */ 3932 unsigned long rtc_4:1; /* RW */ 3933 unsigned long rtc_5:1; /* RW */ 3934 unsigned long rtc_6:1; /* RW */ 3935 unsigned long rtc_7:1; /* RW */ 3936 unsigned long rtc_8:1; /* RW */ 3937 unsigned long rtc_9:1; /* RW */ 3938 unsigned long rtc_10:1; /* RW */ 3939 unsigned long rtc_11:1; /* RW */ 3940 unsigned long rtc_12:1; /* RW */ 3941 unsigned long rtc_13:1; /* RW */ 3942 unsigned long rtc_14:1; /* RW */ 3943 unsigned long rtc_15:1; /* RW */ 3944 unsigned long rtc_16:1; /* RW */ 3945 unsigned long rtc_17:1; /* RW */ 3946 unsigned long rtc_18:1; /* RW */ 3947 unsigned long rtc_19:1; /* RW */ 3948 unsigned long rtc_20:1; /* RW */ 3949 unsigned long rtc_21:1; /* RW */ 3950 unsigned long rtc_22:1; /* RW */ 3951 unsigned long rtc_23:1; /* RW */ 3952 unsigned long rtc_24:1; /* RW */ 3953 unsigned long rtc_25:1; /* RW */ 3954 unsigned long rtc_26:1; /* RW */ 3955 unsigned long rtc_27:1; /* RW */ 3956 unsigned long rtc_28:1; /* RW */ 3957 unsigned long rtc_29:1; /* RW */ 3958 unsigned long rtc_30:1; /* RW */ 3959 unsigned long rtc_31:1; /* RW */ 3960 unsigned long rsvd_50_63:14; 3961 } s4; 3962 }; 3963 3964 /* ========================================================================= */ 3965 /* UVXH_EVENT_OCCURRED2_ALIAS */ 3966 /* ========================================================================= */ 3967 #define UVXH_EVENT_OCCURRED2_ALIAS 0x70108UL 3968 3969 #define UV2H_EVENT_OCCURRED2_ALIAS_32 0xb70 3970 #define UV3H_EVENT_OCCURRED2_ALIAS_32 0xb70 3971 #define UV4H_EVENT_OCCURRED2_ALIAS_32 0x610 3972 #define UVH_EVENT_OCCURRED2_ALIAS_32 ( \ 3973 is_uv2_hub() ? UV2H_EVENT_OCCURRED2_ALIAS_32 : \ 3974 is_uv3_hub() ? UV3H_EVENT_OCCURRED2_ALIAS_32 : \ 3975 /*is_uv4_hub*/ UV4H_EVENT_OCCURRED2_ALIAS_32) 3976 3977 3978 /* ========================================================================= */ 3979 /* UVXH_LB_BAU_SB_ACTIVATION_STATUS_2 */ 3980 /* ========================================================================= */ 3981 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL 3982 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL 3983 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2 0xc8130UL 3984 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_2 ( \ 3985 is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 : \ 3986 is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_2 : \ 3987 /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_2) 3988 3989 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0 3990 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0 3991 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0xa10 3992 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_2_32 ( \ 3993 is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 : \ 3994 is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_32 : \ 3995 /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_32) 3996 3997 #define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0 3998 #define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL 3999 4000 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0 4001 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL 4002 4003 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0 4004 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL 4005 4006 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0 4007 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL 4008 4009 4010 union uvxh_lb_bau_sb_activation_status_2_u { 4011 unsigned long v; 4012 struct uvxh_lb_bau_sb_activation_status_2_s { 4013 unsigned long aux_error:64; /* RW */ 4014 } sx; 4015 struct uv2h_lb_bau_sb_activation_status_2_s { 4016 unsigned long aux_error:64; /* RW */ 4017 } s2; 4018 struct uv3h_lb_bau_sb_activation_status_2_s { 4019 unsigned long aux_error:64; /* RW */ 4020 } s3; 4021 struct uv4h_lb_bau_sb_activation_status_2_s { 4022 unsigned long aux_error:64; /* RW */ 4023 } s4; 4024 }; 4025 4026 /* ========================================================================= */ 4027 /* UV3H_GR0_GAM_GR_CONFIG */ 4028 /* ========================================================================= */ 4029 #define UV3H_GR0_GAM_GR_CONFIG 0xc00028UL 4030 4031 #define UV3H_GR0_GAM_GR_CONFIG_M_SKT_SHFT 0 4032 #define UV3H_GR0_GAM_GR_CONFIG_SUBSPACE_SHFT 10 4033 #define UV3H_GR0_GAM_GR_CONFIG_M_SKT_MASK 0x000000000000003fUL 4034 #define UV3H_GR0_GAM_GR_CONFIG_SUBSPACE_MASK 0x0000000000000400UL 4035 4036 union uv3h_gr0_gam_gr_config_u { 4037 unsigned long v; 4038 struct uv3h_gr0_gam_gr_config_s { 4039 unsigned long m_skt:6; /* RW */ 4040 unsigned long undef_6_9:4; /* Undefined */ 4041 unsigned long subspace:1; /* RW */ 4042 unsigned long reserved:53; 4043 } s3; 4044 }; 4045 4046 /* ========================================================================= */ 4047 /* UV4H_LB_PROC_INTD_QUEUE_FIRST */ 4048 /* ========================================================================= */ 4049 #define UV4H_LB_PROC_INTD_QUEUE_FIRST 0xa4100UL 4050 4051 #define UV4H_LB_PROC_INTD_QUEUE_FIRST_FIRST_PAYLOAD_ADDRESS_SHFT 6 4052 #define UV4H_LB_PROC_INTD_QUEUE_FIRST_FIRST_PAYLOAD_ADDRESS_MASK 0x00003fffffffffc0UL 4053 4054 union uv4h_lb_proc_intd_queue_first_u { 4055 unsigned long v; 4056 struct uv4h_lb_proc_intd_queue_first_s { 4057 unsigned long undef_0_5:6; /* Undefined */ 4058 unsigned long first_payload_address:40; /* RW */ 4059 } s4; 4060 }; 4061 4062 /* ========================================================================= */ 4063 /* UV4H_LB_PROC_INTD_QUEUE_LAST */ 4064 /* ========================================================================= */ 4065 #define UV4H_LB_PROC_INTD_QUEUE_LAST 0xa4108UL 4066 4067 #define UV4H_LB_PROC_INTD_QUEUE_LAST_LAST_PAYLOAD_ADDRESS_SHFT 5 4068 #define UV4H_LB_PROC_INTD_QUEUE_LAST_LAST_PAYLOAD_ADDRESS_MASK 0x00003fffffffffe0UL 4069 4070 union uv4h_lb_proc_intd_queue_last_u { 4071 unsigned long v; 4072 struct uv4h_lb_proc_intd_queue_last_s { 4073 unsigned long undef_0_4:5; /* Undefined */ 4074 unsigned long last_payload_address:41; /* RW */ 4075 } s4; 4076 }; 4077 4078 /* ========================================================================= */ 4079 /* UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR */ 4080 /* ========================================================================= */ 4081 #define UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR 0xa4118UL 4082 4083 #define UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR_SOFT_ACK_PENDING_FLAGS_SHFT 0 4084 #define UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR_SOFT_ACK_PENDING_FLAGS_MASK 0x00000000000000ffUL 4085 4086 union uv4h_lb_proc_intd_soft_ack_clear_u { 4087 unsigned long v; 4088 struct uv4h_lb_proc_intd_soft_ack_clear_s { 4089 unsigned long soft_ack_pending_flags:8; /* WP */ 4090 } s4; 4091 }; 4092 4093 /* ========================================================================= */ 4094 /* UV4H_LB_PROC_INTD_SOFT_ACK_PENDING */ 4095 /* ========================================================================= */ 4096 #define UV4H_LB_PROC_INTD_SOFT_ACK_PENDING 0xa4110UL 4097 4098 #define UV4H_LB_PROC_INTD_SOFT_ACK_PENDING_SOFT_ACK_FLAGS_SHFT 0 4099 #define UV4H_LB_PROC_INTD_SOFT_ACK_PENDING_SOFT_ACK_FLAGS_MASK 0x00000000000000ffUL 4100 4101 union uv4h_lb_proc_intd_soft_ack_pending_u { 4102 unsigned long v; 4103 struct uv4h_lb_proc_intd_soft_ack_pending_s { 4104 unsigned long soft_ack_flags:8; /* RW */ 4105 } s4; 4106 }; 4107 4108 4109 #endif /* _ASM_X86_UV_UV_MMRS_H */ 4110