1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * SGI UV MMR definitions 7 * 8 * Copyright (C) 2007-2016 Silicon Graphics, Inc. All rights reserved. 9 */ 10 11 #ifndef _ASM_X86_UV_UV_MMRS_H 12 #define _ASM_X86_UV_UV_MMRS_H 13 14 /* 15 * This file contains MMR definitions for all UV hubs types. 16 * 17 * To minimize coding differences between hub types, the symbols are 18 * grouped by architecture types. 19 * 20 * UVH - definitions common to all UV hub types. 21 * UVXH - definitions common to all UV eXtended hub types (currently 2, 3, 4). 22 * UV1H - definitions specific to UV type 1 hub. 23 * UV2H - definitions specific to UV type 2 hub. 24 * UV3H - definitions specific to UV type 3 hub. 25 * UV4H - definitions specific to UV type 4 hub. 26 * 27 * So in general, MMR addresses and structures are identical on all hubs types. 28 * These MMRs are identified as: 29 * #define UVH_xxx <address> 30 * union uvh_xxx { 31 * unsigned long v; 32 * struct uvh_int_cmpd_s { 33 * } s; 34 * }; 35 * 36 * If the MMR exists on all hub types but have different addresses, 37 * use a conditional operator to define the value at runtime. 38 * #define UV1Hxxx a 39 * #define UV2Hxxx b 40 * #define UV3Hxxx c 41 * #define UV4Hxxx d 42 * #define UVHxxx (is_uv1_hub() ? UV1Hxxx : 43 * (is_uv2_hub() ? UV2Hxxx : 44 * (is_uv3_hub() ? UV3Hxxx : 45 * UV4Hxxx)) 46 * 47 * If the MMR exists on all hub types > 1 but have different addresses, the 48 * variation using "UVX" as the prefix exists. 49 * #define UV2Hxxx b 50 * #define UV3Hxxx c 51 * #define UV4Hxxx d 52 * #define UVHxxx (is_uv2_hub() ? UV2Hxxx : 53 * (is_uv3_hub() ? UV3Hxxx : 54 * UV4Hxxx)) 55 * 56 * union uvh_xxx { 57 * unsigned long v; 58 * struct uvh_xxx_s { # Common fields only 59 * } s; 60 * struct uv1h_xxx_s { # Full UV1 definition (*) 61 * } s1; 62 * struct uv2h_xxx_s { # Full UV2 definition (*) 63 * } s2; 64 * struct uv3h_xxx_s { # Full UV3 definition (*) 65 * } s3; 66 * struct uv4h_xxx_s { # Full UV4 definition (*) 67 * } s4; 68 * }; 69 * (* - if present and different than the common struct) 70 * 71 * Only essential differences are enumerated. For example, if the address is 72 * the same for all UV's, only a single #define is generated. Likewise, 73 * if the contents is the same for all hubs, only the "s" structure is 74 * generated. 75 * 76 * If the MMR exists on ONLY 1 type of hub, no generic definition is 77 * generated: 78 * #define UVnH_xxx <uvn address> 79 * union uvnh_xxx { 80 * unsigned long v; 81 * struct uvh_int_cmpd_s { 82 * } sn; 83 * }; 84 * 85 * (GEN Flags: mflags_opt= undefs=function UV234=UVXH) 86 */ 87 88 #define UV_MMR_ENABLE (1UL << 63) 89 90 #define UV1_HUB_PART_NUMBER 0x88a5 91 #define UV2_HUB_PART_NUMBER 0x8eb8 92 #define UV2_HUB_PART_NUMBER_X 0x1111 93 #define UV3_HUB_PART_NUMBER 0x9578 94 #define UV3_HUB_PART_NUMBER_X 0x4321 95 #define UV4_HUB_PART_NUMBER 0x99a1 96 97 /* Compat: Indicate which UV Hubs are supported. */ 98 #define UV1_HUB_IS_SUPPORTED 1 99 #define UV2_HUB_IS_SUPPORTED 1 100 #define UV3_HUB_IS_SUPPORTED 1 101 #define UV4_HUB_IS_SUPPORTED 1 102 103 /* Error function to catch undefined references */ 104 extern unsigned long uv_undefined(char *str); 105 106 /* ========================================================================= */ 107 /* UVH_BAU_DATA_BROADCAST */ 108 /* ========================================================================= */ 109 #define UVH_BAU_DATA_BROADCAST 0x61688UL 110 111 #define UV1H_BAU_DATA_BROADCAST_32 0x440 112 #define UV2H_BAU_DATA_BROADCAST_32 0x440 113 #define UV3H_BAU_DATA_BROADCAST_32 0x440 114 #define UV4H_BAU_DATA_BROADCAST_32 0x360 115 #define UVH_BAU_DATA_BROADCAST_32 ( \ 116 is_uv1_hub() ? UV1H_BAU_DATA_BROADCAST_32 : \ 117 is_uv2_hub() ? UV2H_BAU_DATA_BROADCAST_32 : \ 118 is_uv3_hub() ? UV3H_BAU_DATA_BROADCAST_32 : \ 119 /*is_uv4_hub*/ UV4H_BAU_DATA_BROADCAST_32) 120 121 #define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT 0 122 #define UVH_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL 123 124 125 union uvh_bau_data_broadcast_u { 126 unsigned long v; 127 struct uvh_bau_data_broadcast_s { 128 unsigned long enable:1; /* RW */ 129 unsigned long rsvd_1_63:63; 130 } s; 131 }; 132 133 /* ========================================================================= */ 134 /* UVH_BAU_DATA_CONFIG */ 135 /* ========================================================================= */ 136 #define UVH_BAU_DATA_CONFIG 0x61680UL 137 138 #define UV1H_BAU_DATA_CONFIG_32 0x438 139 #define UV2H_BAU_DATA_CONFIG_32 0x438 140 #define UV3H_BAU_DATA_CONFIG_32 0x438 141 #define UV4H_BAU_DATA_CONFIG_32 0x358 142 #define UVH_BAU_DATA_CONFIG_32 ( \ 143 is_uv1_hub() ? UV1H_BAU_DATA_CONFIG_32 : \ 144 is_uv2_hub() ? UV2H_BAU_DATA_CONFIG_32 : \ 145 is_uv3_hub() ? UV3H_BAU_DATA_CONFIG_32 : \ 146 /*is_uv4_hub*/ UV4H_BAU_DATA_CONFIG_32) 147 148 #define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0 149 #define UVH_BAU_DATA_CONFIG_DM_SHFT 8 150 #define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT 11 151 #define UVH_BAU_DATA_CONFIG_STATUS_SHFT 12 152 #define UVH_BAU_DATA_CONFIG_P_SHFT 13 153 #define UVH_BAU_DATA_CONFIG_T_SHFT 15 154 #define UVH_BAU_DATA_CONFIG_M_SHFT 16 155 #define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT 32 156 #define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL 157 #define UVH_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL 158 #define UVH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL 159 #define UVH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL 160 #define UVH_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL 161 #define UVH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL 162 #define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL 163 #define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 164 165 166 union uvh_bau_data_config_u { 167 unsigned long v; 168 struct uvh_bau_data_config_s { 169 unsigned long vector_:8; /* RW */ 170 unsigned long dm:3; /* RW */ 171 unsigned long destmode:1; /* RW */ 172 unsigned long status:1; /* RO */ 173 unsigned long p:1; /* RO */ 174 unsigned long rsvd_14:1; 175 unsigned long t:1; /* RO */ 176 unsigned long m:1; /* RW */ 177 unsigned long rsvd_17_31:15; 178 unsigned long apic_id:32; /* RW */ 179 } s; 180 }; 181 182 /* ========================================================================= */ 183 /* UVH_EVENT_OCCURRED0 */ 184 /* ========================================================================= */ 185 #define UVH_EVENT_OCCURRED0 0x70000UL 186 #define UVH_EVENT_OCCURRED0_32 0x5e8 187 188 #define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT 0 189 #define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT 11 190 #define UVH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL 191 #define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL 192 193 #define UV1H_EVENT_OCCURRED0_GR0_HCERR_SHFT 1 194 #define UV1H_EVENT_OCCURRED0_GR1_HCERR_SHFT 2 195 #define UV1H_EVENT_OCCURRED0_LH_HCERR_SHFT 3 196 #define UV1H_EVENT_OCCURRED0_RH_HCERR_SHFT 4 197 #define UV1H_EVENT_OCCURRED0_XN_HCERR_SHFT 5 198 #define UV1H_EVENT_OCCURRED0_SI_HCERR_SHFT 6 199 #define UV1H_EVENT_OCCURRED0_LB_AOERR0_SHFT 7 200 #define UV1H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8 201 #define UV1H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9 202 #define UV1H_EVENT_OCCURRED0_LH_AOERR0_SHFT 10 203 #define UV1H_EVENT_OCCURRED0_XN_AOERR0_SHFT 12 204 #define UV1H_EVENT_OCCURRED0_SI_AOERR0_SHFT 13 205 #define UV1H_EVENT_OCCURRED0_LB_AOERR1_SHFT 14 206 #define UV1H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15 207 #define UV1H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16 208 #define UV1H_EVENT_OCCURRED0_LH_AOERR1_SHFT 17 209 #define UV1H_EVENT_OCCURRED0_RH_AOERR1_SHFT 18 210 #define UV1H_EVENT_OCCURRED0_XN_AOERR1_SHFT 19 211 #define UV1H_EVENT_OCCURRED0_SI_AOERR1_SHFT 20 212 #define UV1H_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21 213 #define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22 214 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23 215 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24 216 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25 217 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26 218 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27 219 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28 220 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29 221 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30 222 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31 223 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32 224 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33 225 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34 226 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35 227 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36 228 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37 229 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38 230 #define UV1H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39 231 #define UV1H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40 232 #define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41 233 #define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42 234 #define UV1H_EVENT_OCCURRED0_LTC_INT_SHFT 43 235 #define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44 236 #define UV1H_EVENT_OCCURRED0_IPI_INT_SHFT 45 237 #define UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46 238 #define UV1H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47 239 #define UV1H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48 240 #define UV1H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49 241 #define UV1H_EVENT_OCCURRED0_PROFILE_INT_SHFT 50 242 #define UV1H_EVENT_OCCURRED0_RTC0_SHFT 51 243 #define UV1H_EVENT_OCCURRED0_RTC1_SHFT 52 244 #define UV1H_EVENT_OCCURRED0_RTC2_SHFT 53 245 #define UV1H_EVENT_OCCURRED0_RTC3_SHFT 54 246 #define UV1H_EVENT_OCCURRED0_BAU_DATA_SHFT 55 247 #define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56 248 #define UV1H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL 249 #define UV1H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL 250 #define UV1H_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL 251 #define UV1H_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL 252 #define UV1H_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL 253 #define UV1H_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL 254 #define UV1H_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL 255 #define UV1H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL 256 #define UV1H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL 257 #define UV1H_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL 258 #define UV1H_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL 259 #define UV1H_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL 260 #define UV1H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL 261 #define UV1H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL 262 #define UV1H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL 263 #define UV1H_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL 264 #define UV1H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL 265 #define UV1H_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL 266 #define UV1H_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL 267 #define UV1H_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL 268 #define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL 269 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL 270 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL 271 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL 272 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL 273 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL 274 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL 275 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL 276 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL 277 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL 278 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL 279 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL 280 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL 281 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL 282 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL 283 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL 284 #define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL 285 #define UV1H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL 286 #define UV1H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL 287 #define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL 288 #define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL 289 #define UV1H_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL 290 #define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL 291 #define UV1H_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL 292 #define UV1H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL 293 #define UV1H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL 294 #define UV1H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL 295 #define UV1H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL 296 #define UV1H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL 297 #define UV1H_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL 298 #define UV1H_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL 299 #define UV1H_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL 300 #define UV1H_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL 301 #define UV1H_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL 302 #define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL 303 304 #define UVXH_EVENT_OCCURRED0_RH_HCERR_SHFT 2 305 #define UVXH_EVENT_OCCURRED0_LH0_HCERR_SHFT 3 306 #define UVXH_EVENT_OCCURRED0_LH1_HCERR_SHFT 4 307 #define UVXH_EVENT_OCCURRED0_GR0_HCERR_SHFT 5 308 #define UVXH_EVENT_OCCURRED0_GR1_HCERR_SHFT 6 309 #define UVXH_EVENT_OCCURRED0_NI0_HCERR_SHFT 7 310 #define UVXH_EVENT_OCCURRED0_NI1_HCERR_SHFT 8 311 #define UVXH_EVENT_OCCURRED0_LB_AOERR0_SHFT 9 312 #define UVXH_EVENT_OCCURRED0_LH0_AOERR0_SHFT 12 313 #define UVXH_EVENT_OCCURRED0_LH1_AOERR0_SHFT 13 314 #define UVXH_EVENT_OCCURRED0_GR0_AOERR0_SHFT 14 315 #define UVXH_EVENT_OCCURRED0_GR1_AOERR0_SHFT 15 316 #define UVXH_EVENT_OCCURRED0_XB_AOERR0_SHFT 16 317 #define UVXH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000004UL 318 #define UVXH_EVENT_OCCURRED0_LH0_HCERR_MASK 0x0000000000000008UL 319 #define UVXH_EVENT_OCCURRED0_LH1_HCERR_MASK 0x0000000000000010UL 320 #define UVXH_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000020UL 321 #define UVXH_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000040UL 322 #define UVXH_EVENT_OCCURRED0_NI0_HCERR_MASK 0x0000000000000080UL 323 #define UVXH_EVENT_OCCURRED0_NI1_HCERR_MASK 0x0000000000000100UL 324 #define UVXH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000200UL 325 #define UVXH_EVENT_OCCURRED0_LH0_AOERR0_MASK 0x0000000000001000UL 326 #define UVXH_EVENT_OCCURRED0_LH1_AOERR0_MASK 0x0000000000002000UL 327 #define UVXH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000004000UL 328 #define UVXH_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000008000UL 329 #define UVXH_EVENT_OCCURRED0_XB_AOERR0_MASK 0x0000000000010000UL 330 331 #define UV2H_EVENT_OCCURRED0_QP_HCERR_SHFT 1 332 #define UV2H_EVENT_OCCURRED0_QP_AOERR0_SHFT 10 333 #define UV2H_EVENT_OCCURRED0_RT_AOERR0_SHFT 17 334 #define UV2H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18 335 #define UV2H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19 336 #define UV2H_EVENT_OCCURRED0_LB_AOERR1_SHFT 20 337 #define UV2H_EVENT_OCCURRED0_QP_AOERR1_SHFT 21 338 #define UV2H_EVENT_OCCURRED0_RH_AOERR1_SHFT 22 339 #define UV2H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23 340 #define UV2H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24 341 #define UV2H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25 342 #define UV2H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26 343 #define UV2H_EVENT_OCCURRED0_XB_AOERR1_SHFT 27 344 #define UV2H_EVENT_OCCURRED0_RT_AOERR1_SHFT 28 345 #define UV2H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29 346 #define UV2H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30 347 #define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31 348 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32 349 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33 350 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34 351 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35 352 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36 353 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37 354 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38 355 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39 356 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40 357 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41 358 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42 359 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43 360 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44 361 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45 362 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46 363 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47 364 #define UV2H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48 365 #define UV2H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49 366 #define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50 367 #define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51 368 #define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52 369 #define UV2H_EVENT_OCCURRED0_IPI_INT_SHFT 53 370 #define UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54 371 #define UV2H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55 372 #define UV2H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56 373 #define UV2H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57 374 #define UV2H_EVENT_OCCURRED0_PROFILE_INT_SHFT 58 375 #define UV2H_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL 376 #define UV2H_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL 377 #define UV2H_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL 378 #define UV2H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL 379 #define UV2H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL 380 #define UV2H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL 381 #define UV2H_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL 382 #define UV2H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL 383 #define UV2H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL 384 #define UV2H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL 385 #define UV2H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL 386 #define UV2H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL 387 #define UV2H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL 388 #define UV2H_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL 389 #define UV2H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL 390 #define UV2H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL 391 #define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL 392 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL 393 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL 394 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL 395 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL 396 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL 397 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL 398 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL 399 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL 400 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL 401 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL 402 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL 403 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL 404 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL 405 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL 406 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL 407 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL 408 #define UV2H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL 409 #define UV2H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL 410 #define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL 411 #define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL 412 #define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL 413 #define UV2H_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL 414 #define UV2H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL 415 #define UV2H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL 416 #define UV2H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL 417 #define UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL 418 #define UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL 419 420 #define UV3H_EVENT_OCCURRED0_QP_HCERR_SHFT 1 421 #define UV3H_EVENT_OCCURRED0_QP_AOERR0_SHFT 10 422 #define UV3H_EVENT_OCCURRED0_RT_AOERR0_SHFT 17 423 #define UV3H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18 424 #define UV3H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19 425 #define UV3H_EVENT_OCCURRED0_LB_AOERR1_SHFT 20 426 #define UV3H_EVENT_OCCURRED0_QP_AOERR1_SHFT 21 427 #define UV3H_EVENT_OCCURRED0_RH_AOERR1_SHFT 22 428 #define UV3H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23 429 #define UV3H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24 430 #define UV3H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25 431 #define UV3H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26 432 #define UV3H_EVENT_OCCURRED0_XB_AOERR1_SHFT 27 433 #define UV3H_EVENT_OCCURRED0_RT_AOERR1_SHFT 28 434 #define UV3H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29 435 #define UV3H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30 436 #define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31 437 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32 438 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33 439 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34 440 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35 441 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36 442 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37 443 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38 444 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39 445 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40 446 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41 447 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42 448 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43 449 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44 450 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45 451 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46 452 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47 453 #define UV3H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48 454 #define UV3H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49 455 #define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50 456 #define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51 457 #define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52 458 #define UV3H_EVENT_OCCURRED0_IPI_INT_SHFT 53 459 #define UV3H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54 460 #define UV3H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55 461 #define UV3H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56 462 #define UV3H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57 463 #define UV3H_EVENT_OCCURRED0_PROFILE_INT_SHFT 58 464 #define UV3H_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL 465 #define UV3H_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL 466 #define UV3H_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL 467 #define UV3H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL 468 #define UV3H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL 469 #define UV3H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL 470 #define UV3H_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL 471 #define UV3H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL 472 #define UV3H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL 473 #define UV3H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL 474 #define UV3H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL 475 #define UV3H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL 476 #define UV3H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL 477 #define UV3H_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL 478 #define UV3H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL 479 #define UV3H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL 480 #define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL 481 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL 482 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL 483 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL 484 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL 485 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL 486 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL 487 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL 488 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL 489 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL 490 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL 491 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL 492 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL 493 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL 494 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL 495 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL 496 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL 497 #define UV3H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL 498 #define UV3H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL 499 #define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL 500 #define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL 501 #define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL 502 #define UV3H_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL 503 #define UV3H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL 504 #define UV3H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL 505 #define UV3H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL 506 #define UV3H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL 507 #define UV3H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL 508 509 #define UV4H_EVENT_OCCURRED0_KT_HCERR_SHFT 1 510 #define UV4H_EVENT_OCCURRED0_KT_AOERR0_SHFT 10 511 #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR0_SHFT 17 512 #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR0_SHFT 18 513 #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR0_SHFT 19 514 #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR0_SHFT 20 515 #define UV4H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 21 516 #define UV4H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 22 517 #define UV4H_EVENT_OCCURRED0_LB_AOERR1_SHFT 23 518 #define UV4H_EVENT_OCCURRED0_KT_AOERR1_SHFT 24 519 #define UV4H_EVENT_OCCURRED0_RH_AOERR1_SHFT 25 520 #define UV4H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 26 521 #define UV4H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 27 522 #define UV4H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 28 523 #define UV4H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 29 524 #define UV4H_EVENT_OCCURRED0_XB_AOERR1_SHFT 30 525 #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR1_SHFT 31 526 #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR1_SHFT 32 527 #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR1_SHFT 33 528 #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR1_SHFT 34 529 #define UV4H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 35 530 #define UV4H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 36 531 #define UV4H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 37 532 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 38 533 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 39 534 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 40 535 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 41 536 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 42 537 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 43 538 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 44 539 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 45 540 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 46 541 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 47 542 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 48 543 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 49 544 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 50 545 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 51 546 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 52 547 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 53 548 #define UV4H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 54 549 #define UV4H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 55 550 #define UV4H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 56 551 #define UV4H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 57 552 #define UV4H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 58 553 #define UV4H_EVENT_OCCURRED0_IPI_INT_SHFT 59 554 #define UV4H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 60 555 #define UV4H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 61 556 #define UV4H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 62 557 #define UV4H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 63 558 #define UV4H_EVENT_OCCURRED0_KT_HCERR_MASK 0x0000000000000002UL 559 #define UV4H_EVENT_OCCURRED0_KT_AOERR0_MASK 0x0000000000000400UL 560 #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR0_MASK 0x0000000000020000UL 561 #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR0_MASK 0x0000000000040000UL 562 #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR0_MASK 0x0000000000080000UL 563 #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR0_MASK 0x0000000000100000UL 564 #define UV4H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000200000UL 565 #define UV4H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000400000UL 566 #define UV4H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000800000UL 567 #define UV4H_EVENT_OCCURRED0_KT_AOERR1_MASK 0x0000000001000000UL 568 #define UV4H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000002000000UL 569 #define UV4H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000004000000UL 570 #define UV4H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000008000000UL 571 #define UV4H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000010000000UL 572 #define UV4H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000020000000UL 573 #define UV4H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000040000000UL 574 #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR1_MASK 0x0000000080000000UL 575 #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR1_MASK 0x0000000100000000UL 576 #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR1_MASK 0x0000000200000000UL 577 #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR1_MASK 0x0000000400000000UL 578 #define UV4H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000800000000UL 579 #define UV4H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000001000000000UL 580 #define UV4H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000002000000000UL 581 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000004000000000UL 582 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000008000000000UL 583 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000010000000000UL 584 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000020000000000UL 585 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000040000000000UL 586 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000080000000000UL 587 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000100000000000UL 588 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000200000000000UL 589 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000400000000000UL 590 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000800000000000UL 591 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0001000000000000UL 592 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0002000000000000UL 593 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0004000000000000UL 594 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0008000000000000UL 595 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0010000000000000UL 596 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0020000000000000UL 597 #define UV4H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0040000000000000UL 598 #define UV4H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0080000000000000UL 599 #define UV4H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0100000000000000UL 600 #define UV4H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0200000000000000UL 601 #define UV4H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0400000000000000UL 602 #define UV4H_EVENT_OCCURRED0_IPI_INT_MASK 0x0800000000000000UL 603 #define UV4H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x1000000000000000UL 604 #define UV4H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x2000000000000000UL 605 #define UV4H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x4000000000000000UL 606 #define UV4H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x8000000000000000UL 607 608 #define UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT ( \ 609 is_uv1_hub() ? UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT : \ 610 is_uv2_hub() ? UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT : \ 611 is_uv3_hub() ? UV3H_EVENT_OCCURRED0_EXTIO_INT0_SHFT : \ 612 /*is_uv4_hub*/ UV4H_EVENT_OCCURRED0_EXTIO_INT0_SHFT) 613 614 union uvh_event_occurred0_u { 615 unsigned long v; 616 struct uvh_event_occurred0_s { 617 unsigned long lb_hcerr:1; /* RW, W1C */ 618 unsigned long rsvd_1_10:10; 619 unsigned long rh_aoerr0:1; /* RW, W1C */ 620 unsigned long rsvd_12_63:52; 621 } s; 622 struct uvxh_event_occurred0_s { 623 unsigned long lb_hcerr:1; /* RW */ 624 unsigned long rsvd_1:1; 625 unsigned long rh_hcerr:1; /* RW */ 626 unsigned long lh0_hcerr:1; /* RW */ 627 unsigned long lh1_hcerr:1; /* RW */ 628 unsigned long gr0_hcerr:1; /* RW */ 629 unsigned long gr1_hcerr:1; /* RW */ 630 unsigned long ni0_hcerr:1; /* RW */ 631 unsigned long ni1_hcerr:1; /* RW */ 632 unsigned long lb_aoerr0:1; /* RW */ 633 unsigned long rsvd_10:1; 634 unsigned long rh_aoerr0:1; /* RW */ 635 unsigned long lh0_aoerr0:1; /* RW */ 636 unsigned long lh1_aoerr0:1; /* RW */ 637 unsigned long gr0_aoerr0:1; /* RW */ 638 unsigned long gr1_aoerr0:1; /* RW */ 639 unsigned long xb_aoerr0:1; /* RW */ 640 unsigned long rsvd_17_63:47; 641 } sx; 642 struct uv4h_event_occurred0_s { 643 unsigned long lb_hcerr:1; /* RW */ 644 unsigned long kt_hcerr:1; /* RW */ 645 unsigned long rh_hcerr:1; /* RW */ 646 unsigned long lh0_hcerr:1; /* RW */ 647 unsigned long lh1_hcerr:1; /* RW */ 648 unsigned long gr0_hcerr:1; /* RW */ 649 unsigned long gr1_hcerr:1; /* RW */ 650 unsigned long ni0_hcerr:1; /* RW */ 651 unsigned long ni1_hcerr:1; /* RW */ 652 unsigned long lb_aoerr0:1; /* RW */ 653 unsigned long kt_aoerr0:1; /* RW */ 654 unsigned long rh_aoerr0:1; /* RW */ 655 unsigned long lh0_aoerr0:1; /* RW */ 656 unsigned long lh1_aoerr0:1; /* RW */ 657 unsigned long gr0_aoerr0:1; /* RW */ 658 unsigned long gr1_aoerr0:1; /* RW */ 659 unsigned long xb_aoerr0:1; /* RW */ 660 unsigned long rtq0_aoerr0:1; /* RW */ 661 unsigned long rtq1_aoerr0:1; /* RW */ 662 unsigned long rtq2_aoerr0:1; /* RW */ 663 unsigned long rtq3_aoerr0:1; /* RW */ 664 unsigned long ni0_aoerr0:1; /* RW */ 665 unsigned long ni1_aoerr0:1; /* RW */ 666 unsigned long lb_aoerr1:1; /* RW */ 667 unsigned long kt_aoerr1:1; /* RW */ 668 unsigned long rh_aoerr1:1; /* RW */ 669 unsigned long lh0_aoerr1:1; /* RW */ 670 unsigned long lh1_aoerr1:1; /* RW */ 671 unsigned long gr0_aoerr1:1; /* RW */ 672 unsigned long gr1_aoerr1:1; /* RW */ 673 unsigned long xb_aoerr1:1; /* RW */ 674 unsigned long rtq0_aoerr1:1; /* RW */ 675 unsigned long rtq1_aoerr1:1; /* RW */ 676 unsigned long rtq2_aoerr1:1; /* RW */ 677 unsigned long rtq3_aoerr1:1; /* RW */ 678 unsigned long ni0_aoerr1:1; /* RW */ 679 unsigned long ni1_aoerr1:1; /* RW */ 680 unsigned long system_shutdown_int:1; /* RW */ 681 unsigned long lb_irq_int_0:1; /* RW */ 682 unsigned long lb_irq_int_1:1; /* RW */ 683 unsigned long lb_irq_int_2:1; /* RW */ 684 unsigned long lb_irq_int_3:1; /* RW */ 685 unsigned long lb_irq_int_4:1; /* RW */ 686 unsigned long lb_irq_int_5:1; /* RW */ 687 unsigned long lb_irq_int_6:1; /* RW */ 688 unsigned long lb_irq_int_7:1; /* RW */ 689 unsigned long lb_irq_int_8:1; /* RW */ 690 unsigned long lb_irq_int_9:1; /* RW */ 691 unsigned long lb_irq_int_10:1; /* RW */ 692 unsigned long lb_irq_int_11:1; /* RW */ 693 unsigned long lb_irq_int_12:1; /* RW */ 694 unsigned long lb_irq_int_13:1; /* RW */ 695 unsigned long lb_irq_int_14:1; /* RW */ 696 unsigned long lb_irq_int_15:1; /* RW */ 697 unsigned long l1_nmi_int:1; /* RW */ 698 unsigned long stop_clock:1; /* RW */ 699 unsigned long asic_to_l1:1; /* RW */ 700 unsigned long l1_to_asic:1; /* RW */ 701 unsigned long la_seq_trigger:1; /* RW */ 702 unsigned long ipi_int:1; /* RW */ 703 unsigned long extio_int0:1; /* RW */ 704 unsigned long extio_int1:1; /* RW */ 705 unsigned long extio_int2:1; /* RW */ 706 unsigned long extio_int3:1; /* RW */ 707 } s4; 708 }; 709 710 /* ========================================================================= */ 711 /* UVH_EVENT_OCCURRED0_ALIAS */ 712 /* ========================================================================= */ 713 #define UVH_EVENT_OCCURRED0_ALIAS 0x70008UL 714 #define UVH_EVENT_OCCURRED0_ALIAS_32 0x5f0 715 716 717 /* ========================================================================= */ 718 /* UVH_EXTIO_INT0_BROADCAST */ 719 /* ========================================================================= */ 720 #define UVH_EXTIO_INT0_BROADCAST 0x61448UL 721 722 #define UV1H_EXTIO_INT0_BROADCAST_32 0x3f0 723 #define UV2H_EXTIO_INT0_BROADCAST_32 0x3f0 724 #define UV3H_EXTIO_INT0_BROADCAST_32 0x3f0 725 #define UV4H_EXTIO_INT0_BROADCAST_32 0x310 726 #define UVH_EXTIO_INT0_BROADCAST_32 ( \ 727 is_uv1_hub() ? UV1H_EXTIO_INT0_BROADCAST_32 : \ 728 is_uv2_hub() ? UV2H_EXTIO_INT0_BROADCAST_32 : \ 729 is_uv3_hub() ? UV3H_EXTIO_INT0_BROADCAST_32 : \ 730 /*is_uv4_hub*/ UV4H_EXTIO_INT0_BROADCAST_32) 731 732 #define UVH_EXTIO_INT0_BROADCAST_ENABLE_SHFT 0 733 #define UVH_EXTIO_INT0_BROADCAST_ENABLE_MASK 0x0000000000000001UL 734 735 736 union uvh_extio_int0_broadcast_u { 737 unsigned long v; 738 struct uvh_extio_int0_broadcast_s { 739 unsigned long enable:1; /* RW */ 740 unsigned long rsvd_1_63:63; 741 } s; 742 }; 743 744 /* ========================================================================= */ 745 /* UVH_GR0_TLB_INT0_CONFIG */ 746 /* ========================================================================= */ 747 #define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL 748 749 #define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0 750 #define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT 8 751 #define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11 752 #define UVH_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12 753 #define UVH_GR0_TLB_INT0_CONFIG_P_SHFT 13 754 #define UVH_GR0_TLB_INT0_CONFIG_T_SHFT 15 755 #define UVH_GR0_TLB_INT0_CONFIG_M_SHFT 16 756 #define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32 757 #define UVH_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL 758 #define UVH_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL 759 #define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL 760 #define UVH_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL 761 #define UVH_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL 762 #define UVH_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL 763 #define UVH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL 764 #define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 765 766 767 union uvh_gr0_tlb_int0_config_u { 768 unsigned long v; 769 struct uvh_gr0_tlb_int0_config_s { 770 unsigned long vector_:8; /* RW */ 771 unsigned long dm:3; /* RW */ 772 unsigned long destmode:1; /* RW */ 773 unsigned long status:1; /* RO */ 774 unsigned long p:1; /* RO */ 775 unsigned long rsvd_14:1; 776 unsigned long t:1; /* RO */ 777 unsigned long m:1; /* RW */ 778 unsigned long rsvd_17_31:15; 779 unsigned long apic_id:32; /* RW */ 780 } s; 781 }; 782 783 /* ========================================================================= */ 784 /* UVH_GR0_TLB_INT1_CONFIG */ 785 /* ========================================================================= */ 786 #define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL 787 788 #define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0 789 #define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT 8 790 #define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT 11 791 #define UVH_GR0_TLB_INT1_CONFIG_STATUS_SHFT 12 792 #define UVH_GR0_TLB_INT1_CONFIG_P_SHFT 13 793 #define UVH_GR0_TLB_INT1_CONFIG_T_SHFT 15 794 #define UVH_GR0_TLB_INT1_CONFIG_M_SHFT 16 795 #define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT 32 796 #define UVH_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL 797 #define UVH_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL 798 #define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL 799 #define UVH_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL 800 #define UVH_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL 801 #define UVH_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL 802 #define UVH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL 803 #define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 804 805 806 union uvh_gr0_tlb_int1_config_u { 807 unsigned long v; 808 struct uvh_gr0_tlb_int1_config_s { 809 unsigned long vector_:8; /* RW */ 810 unsigned long dm:3; /* RW */ 811 unsigned long destmode:1; /* RW */ 812 unsigned long status:1; /* RO */ 813 unsigned long p:1; /* RO */ 814 unsigned long rsvd_14:1; 815 unsigned long t:1; /* RO */ 816 unsigned long m:1; /* RW */ 817 unsigned long rsvd_17_31:15; 818 unsigned long apic_id:32; /* RW */ 819 } s; 820 }; 821 822 /* ========================================================================= */ 823 /* UVH_GR0_TLB_MMR_CONTROL */ 824 /* ========================================================================= */ 825 #define UV1H_GR0_TLB_MMR_CONTROL 0x401080UL 826 #define UV2H_GR0_TLB_MMR_CONTROL 0xc01080UL 827 #define UV3H_GR0_TLB_MMR_CONTROL 0xc01080UL 828 #define UV4H_GR0_TLB_MMR_CONTROL 0x601080UL 829 #define UVH_GR0_TLB_MMR_CONTROL ( \ 830 is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL : \ 831 is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL : \ 832 is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL : \ 833 /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL) 834 835 #define UVH_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 836 #define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 837 #define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 838 #define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 839 #define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31 840 #define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 841 #define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 842 #define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 843 #define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 844 845 #define UV1H_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 846 #define UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 847 #define UV1H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 848 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 849 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 850 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31 851 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT 48 852 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT 52 853 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_SHFT 54 854 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_SHFT 56 855 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_SHFT 60 856 #define UV1H_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL 857 #define UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL 858 #define UV1H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 859 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 860 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 861 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 862 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL 863 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL 864 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_MASK 0x0040000000000000UL 865 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK 0x0100000000000000UL 866 #define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK 0x1000000000000000UL 867 868 #define UVXH_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 869 #define UVXH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 870 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 871 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 872 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31 873 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 874 #define UVXH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 875 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 876 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 877 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 878 #define UVXH_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 879 880 #define UV2H_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 881 #define UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 882 #define UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 883 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 884 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 885 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31 886 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 887 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT 48 888 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT 52 889 #define UV2H_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL 890 #define UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL 891 #define UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 892 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 893 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 894 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 895 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 896 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL 897 #define UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL 898 899 #define UV3H_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 900 #define UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 901 #define UV3H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 902 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 903 #define UV3H_GR0_TLB_MMR_CONTROL_ECC_SEL_SHFT 21 904 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 905 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31 906 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 907 #define UV3H_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL 908 #define UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL 909 #define UV3H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 910 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 911 #define UV3H_GR0_TLB_MMR_CONTROL_ECC_SEL_MASK 0x0000000000200000UL 912 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 913 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 914 #define UV3H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 915 916 #define UV4H_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 917 #define UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 13 918 #define UV4H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 919 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 920 #define UV4H_GR0_TLB_MMR_CONTROL_ECC_SEL_SHFT 21 921 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 922 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31 923 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 924 #define UV4H_GR0_TLB_MMR_CONTROL_PAGE_SIZE_SHFT 59 925 #define UV4H_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000001fffUL 926 #define UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000006000UL 927 #define UV4H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 928 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 929 #define UV4H_GR0_TLB_MMR_CONTROL_ECC_SEL_MASK 0x0000000000200000UL 930 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 931 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 932 #define UV4H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 933 #define UV4H_GR0_TLB_MMR_CONTROL_PAGE_SIZE_MASK 0xf800000000000000UL 934 935 #define UVH_GR0_TLB_MMR_CONTROL_INDEX_MASK ( \ 936 is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL_INDEX_MASK : \ 937 is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL_INDEX_MASK : \ 938 is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL_INDEX_MASK : \ 939 /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL_INDEX_MASK) 940 #define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK ( \ 941 is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK : \ 942 is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK : \ 943 is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK : \ 944 /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK) 945 #define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT ( \ 946 is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT : \ 947 is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT : \ 948 is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT : \ 949 /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT) 950 951 union uvh_gr0_tlb_mmr_control_u { 952 unsigned long v; 953 struct uvh_gr0_tlb_mmr_control_s { 954 unsigned long rsvd_0_15:16; 955 unsigned long auto_valid_en:1; /* RW */ 956 unsigned long rsvd_17_19:3; 957 unsigned long mmr_hash_index_en:1; /* RW */ 958 unsigned long rsvd_21_29:9; 959 unsigned long mmr_write:1; /* WP */ 960 unsigned long mmr_read:1; /* WP */ 961 unsigned long rsvd_32_48:17; 962 unsigned long rsvd_49_51:3; 963 unsigned long rsvd_52_63:12; 964 } s; 965 struct uv1h_gr0_tlb_mmr_control_s { 966 unsigned long index:12; /* RW */ 967 unsigned long mem_sel:2; /* RW */ 968 unsigned long rsvd_14_15:2; 969 unsigned long auto_valid_en:1; /* RW */ 970 unsigned long rsvd_17_19:3; 971 unsigned long mmr_hash_index_en:1; /* RW */ 972 unsigned long rsvd_21_29:9; 973 unsigned long mmr_write:1; /* WP */ 974 unsigned long mmr_read:1; /* WP */ 975 unsigned long rsvd_32_47:16; 976 unsigned long mmr_inj_con:1; /* RW */ 977 unsigned long rsvd_49_51:3; 978 unsigned long mmr_inj_tlbram:1; /* RW */ 979 unsigned long rsvd_53:1; 980 unsigned long mmr_inj_tlbpgsize:1; /* RW */ 981 unsigned long rsvd_55:1; 982 unsigned long mmr_inj_tlbrreg:1; /* RW */ 983 unsigned long rsvd_57_59:3; 984 unsigned long mmr_inj_tlblruv:1; /* RW */ 985 unsigned long rsvd_61_63:3; 986 } s1; 987 struct uvxh_gr0_tlb_mmr_control_s { 988 unsigned long rsvd_0_15:16; 989 unsigned long auto_valid_en:1; /* RW */ 990 unsigned long rsvd_17_19:3; 991 unsigned long mmr_hash_index_en:1; /* RW */ 992 unsigned long rsvd_21_29:9; 993 unsigned long mmr_write:1; /* WP */ 994 unsigned long mmr_read:1; /* WP */ 995 unsigned long mmr_op_done:1; /* RW */ 996 unsigned long rsvd_33_47:15; 997 unsigned long rsvd_48:1; 998 unsigned long rsvd_49_51:3; 999 unsigned long rsvd_52_63:12; 1000 } sx; 1001 struct uv2h_gr0_tlb_mmr_control_s { 1002 unsigned long index:12; /* RW */ 1003 unsigned long mem_sel:2; /* RW */ 1004 unsigned long rsvd_14_15:2; 1005 unsigned long auto_valid_en:1; /* RW */ 1006 unsigned long rsvd_17_19:3; 1007 unsigned long mmr_hash_index_en:1; /* RW */ 1008 unsigned long rsvd_21_29:9; 1009 unsigned long mmr_write:1; /* WP */ 1010 unsigned long mmr_read:1; /* WP */ 1011 unsigned long mmr_op_done:1; /* RW */ 1012 unsigned long rsvd_33_47:15; 1013 unsigned long mmr_inj_con:1; /* RW */ 1014 unsigned long rsvd_49_51:3; 1015 unsigned long mmr_inj_tlbram:1; /* RW */ 1016 unsigned long rsvd_53_63:11; 1017 } s2; 1018 struct uv3h_gr0_tlb_mmr_control_s { 1019 unsigned long index:12; /* RW */ 1020 unsigned long mem_sel:2; /* RW */ 1021 unsigned long rsvd_14_15:2; 1022 unsigned long auto_valid_en:1; /* RW */ 1023 unsigned long rsvd_17_19:3; 1024 unsigned long mmr_hash_index_en:1; /* RW */ 1025 unsigned long ecc_sel:1; /* RW */ 1026 unsigned long rsvd_22_29:8; 1027 unsigned long mmr_write:1; /* WP */ 1028 unsigned long mmr_read:1; /* WP */ 1029 unsigned long mmr_op_done:1; /* RW */ 1030 unsigned long rsvd_33_47:15; 1031 unsigned long undef_48:1; /* Undefined */ 1032 unsigned long rsvd_49_51:3; 1033 unsigned long undef_52:1; /* Undefined */ 1034 unsigned long rsvd_53_63:11; 1035 } s3; 1036 struct uv4h_gr0_tlb_mmr_control_s { 1037 unsigned long index:13; /* RW */ 1038 unsigned long mem_sel:2; /* RW */ 1039 unsigned long rsvd_15:1; 1040 unsigned long auto_valid_en:1; /* RW */ 1041 unsigned long rsvd_17_19:3; 1042 unsigned long mmr_hash_index_en:1; /* RW */ 1043 unsigned long ecc_sel:1; /* RW */ 1044 unsigned long rsvd_22_29:8; 1045 unsigned long mmr_write:1; /* WP */ 1046 unsigned long mmr_read:1; /* WP */ 1047 unsigned long mmr_op_done:1; /* RW */ 1048 unsigned long rsvd_33_47:15; 1049 unsigned long undef_48:1; /* Undefined */ 1050 unsigned long rsvd_49_51:3; 1051 unsigned long rsvd_52_58:7; 1052 unsigned long page_size:5; /* RW */ 1053 } s4; 1054 }; 1055 1056 /* ========================================================================= */ 1057 /* UVH_GR0_TLB_MMR_READ_DATA_HI */ 1058 /* ========================================================================= */ 1059 #define UV1H_GR0_TLB_MMR_READ_DATA_HI 0x4010a0UL 1060 #define UV2H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL 1061 #define UV3H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL 1062 #define UV4H_GR0_TLB_MMR_READ_DATA_HI 0x6010a0UL 1063 #define UVH_GR0_TLB_MMR_READ_DATA_HI ( \ 1064 is_uv1_hub() ? UV1H_GR0_TLB_MMR_READ_DATA_HI : \ 1065 is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_HI : \ 1066 is_uv3_hub() ? UV3H_GR0_TLB_MMR_READ_DATA_HI : \ 1067 /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_READ_DATA_HI) 1068 1069 #define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1070 1071 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1072 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 1073 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 1074 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 1075 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL 1076 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL 1077 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL 1078 #define UV1H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 1079 1080 #define UVXH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1081 1082 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1083 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 1084 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 1085 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 1086 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL 1087 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL 1088 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL 1089 #define UV2H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 1090 1091 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1092 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 1093 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 1094 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 1095 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT 45 1096 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT 55 1097 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL 1098 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL 1099 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL 1100 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 1101 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_MASK 0x0000200000000000UL 1102 #define UV3H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK 0xff80000000000000UL 1103 1104 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1105 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_PNID_SHFT 34 1106 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 49 1107 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 51 1108 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT 52 1109 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT 53 1110 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT 55 1111 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK 0x00000003ffffffffUL 1112 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_PNID_MASK 0x0001fffc00000000UL 1113 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0006000000000000UL 1114 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0008000000000000UL 1115 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0010000000000000UL 1116 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_MASK 0x0020000000000000UL 1117 #define UV4H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK 0xff80000000000000UL 1118 1119 1120 union uvh_gr0_tlb_mmr_read_data_hi_u { 1121 unsigned long v; 1122 struct uv1h_gr0_tlb_mmr_read_data_hi_s { 1123 unsigned long pfn:41; /* RO */ 1124 unsigned long gaa:2; /* RO */ 1125 unsigned long dirty:1; /* RO */ 1126 unsigned long larger:1; /* RO */ 1127 unsigned long rsvd_45_63:19; 1128 } s1; 1129 struct uv2h_gr0_tlb_mmr_read_data_hi_s { 1130 unsigned long pfn:41; /* RO */ 1131 unsigned long gaa:2; /* RO */ 1132 unsigned long dirty:1; /* RO */ 1133 unsigned long larger:1; /* RO */ 1134 unsigned long rsvd_45_63:19; 1135 } s2; 1136 struct uv3h_gr0_tlb_mmr_read_data_hi_s { 1137 unsigned long pfn:41; /* RO */ 1138 unsigned long gaa:2; /* RO */ 1139 unsigned long dirty:1; /* RO */ 1140 unsigned long larger:1; /* RO */ 1141 unsigned long aa_ext:1; /* RO */ 1142 unsigned long undef_46_54:9; /* Undefined */ 1143 unsigned long way_ecc:9; /* RO */ 1144 } s3; 1145 struct uv4h_gr0_tlb_mmr_read_data_hi_s { 1146 unsigned long pfn:34; /* RO */ 1147 unsigned long pnid:15; /* RO */ 1148 unsigned long gaa:2; /* RO */ 1149 unsigned long dirty:1; /* RO */ 1150 unsigned long larger:1; /* RO */ 1151 unsigned long aa_ext:1; /* RO */ 1152 unsigned long undef_54:1; /* Undefined */ 1153 unsigned long way_ecc:9; /* RO */ 1154 } s4; 1155 }; 1156 1157 /* ========================================================================= */ 1158 /* UVH_GR0_TLB_MMR_READ_DATA_LO */ 1159 /* ========================================================================= */ 1160 #define UV1H_GR0_TLB_MMR_READ_DATA_LO 0x4010a8UL 1161 #define UV2H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL 1162 #define UV3H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL 1163 #define UV4H_GR0_TLB_MMR_READ_DATA_LO 0x6010a8UL 1164 #define UVH_GR0_TLB_MMR_READ_DATA_LO ( \ 1165 is_uv1_hub() ? UV1H_GR0_TLB_MMR_READ_DATA_LO : \ 1166 is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_LO : \ 1167 is_uv3_hub() ? UV3H_GR0_TLB_MMR_READ_DATA_LO : \ 1168 /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_READ_DATA_LO) 1169 1170 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1171 #define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1172 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1173 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1174 #define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1175 #define UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1176 1177 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1178 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1179 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1180 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1181 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1182 #define UV1H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1183 1184 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1185 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1186 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1187 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1188 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1189 #define UVXH_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1190 1191 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1192 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1193 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1194 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1195 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1196 #define UV2H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1197 1198 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1199 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1200 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1201 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1202 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1203 #define UV3H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1204 1205 #define UV4H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1206 #define UV4H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1207 #define UV4H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1208 #define UV4H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1209 #define UV4H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1210 #define UV4H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1211 1212 1213 union uvh_gr0_tlb_mmr_read_data_lo_u { 1214 unsigned long v; 1215 struct uvh_gr0_tlb_mmr_read_data_lo_s { 1216 unsigned long vpn:39; /* RO */ 1217 unsigned long asid:24; /* RO */ 1218 unsigned long valid:1; /* RO */ 1219 } s; 1220 struct uv1h_gr0_tlb_mmr_read_data_lo_s { 1221 unsigned long vpn:39; /* RO */ 1222 unsigned long asid:24; /* RO */ 1223 unsigned long valid:1; /* RO */ 1224 } s1; 1225 struct uvxh_gr0_tlb_mmr_read_data_lo_s { 1226 unsigned long vpn:39; /* RO */ 1227 unsigned long asid:24; /* RO */ 1228 unsigned long valid:1; /* RO */ 1229 } sx; 1230 struct uv2h_gr0_tlb_mmr_read_data_lo_s { 1231 unsigned long vpn:39; /* RO */ 1232 unsigned long asid:24; /* RO */ 1233 unsigned long valid:1; /* RO */ 1234 } s2; 1235 struct uv3h_gr0_tlb_mmr_read_data_lo_s { 1236 unsigned long vpn:39; /* RO */ 1237 unsigned long asid:24; /* RO */ 1238 unsigned long valid:1; /* RO */ 1239 } s3; 1240 struct uv4h_gr0_tlb_mmr_read_data_lo_s { 1241 unsigned long vpn:39; /* RO */ 1242 unsigned long asid:24; /* RO */ 1243 unsigned long valid:1; /* RO */ 1244 } s4; 1245 }; 1246 1247 /* ========================================================================= */ 1248 /* UVH_GR1_TLB_INT0_CONFIG */ 1249 /* ========================================================================= */ 1250 #define UV1H_GR1_TLB_INT0_CONFIG 0x61f00UL 1251 #define UV2H_GR1_TLB_INT0_CONFIG 0x61f00UL 1252 #define UV3H_GR1_TLB_INT0_CONFIG 0x61f00UL 1253 #define UV4H_GR1_TLB_INT0_CONFIG 0x62100UL 1254 #define UVH_GR1_TLB_INT0_CONFIG ( \ 1255 is_uv1_hub() ? UV1H_GR1_TLB_INT0_CONFIG : \ 1256 is_uv2_hub() ? UV2H_GR1_TLB_INT0_CONFIG : \ 1257 is_uv3_hub() ? UV3H_GR1_TLB_INT0_CONFIG : \ 1258 /*is_uv4_hub*/ UV4H_GR1_TLB_INT0_CONFIG) 1259 1260 #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0 1261 #define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT 8 1262 #define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT 11 1263 #define UVH_GR1_TLB_INT0_CONFIG_STATUS_SHFT 12 1264 #define UVH_GR1_TLB_INT0_CONFIG_P_SHFT 13 1265 #define UVH_GR1_TLB_INT0_CONFIG_T_SHFT 15 1266 #define UVH_GR1_TLB_INT0_CONFIG_M_SHFT 16 1267 #define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT 32 1268 #define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL 1269 #define UVH_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL 1270 #define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL 1271 #define UVH_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL 1272 #define UVH_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL 1273 #define UVH_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL 1274 #define UVH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL 1275 #define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 1276 1277 1278 union uvh_gr1_tlb_int0_config_u { 1279 unsigned long v; 1280 struct uvh_gr1_tlb_int0_config_s { 1281 unsigned long vector_:8; /* RW */ 1282 unsigned long dm:3; /* RW */ 1283 unsigned long destmode:1; /* RW */ 1284 unsigned long status:1; /* RO */ 1285 unsigned long p:1; /* RO */ 1286 unsigned long rsvd_14:1; 1287 unsigned long t:1; /* RO */ 1288 unsigned long m:1; /* RW */ 1289 unsigned long rsvd_17_31:15; 1290 unsigned long apic_id:32; /* RW */ 1291 } s; 1292 }; 1293 1294 /* ========================================================================= */ 1295 /* UVH_GR1_TLB_INT1_CONFIG */ 1296 /* ========================================================================= */ 1297 #define UV1H_GR1_TLB_INT1_CONFIG 0x61f40UL 1298 #define UV2H_GR1_TLB_INT1_CONFIG 0x61f40UL 1299 #define UV3H_GR1_TLB_INT1_CONFIG 0x61f40UL 1300 #define UV4H_GR1_TLB_INT1_CONFIG 0x62140UL 1301 #define UVH_GR1_TLB_INT1_CONFIG ( \ 1302 is_uv1_hub() ? UV1H_GR1_TLB_INT1_CONFIG : \ 1303 is_uv2_hub() ? UV2H_GR1_TLB_INT1_CONFIG : \ 1304 is_uv3_hub() ? UV3H_GR1_TLB_INT1_CONFIG : \ 1305 /*is_uv4_hub*/ UV4H_GR1_TLB_INT1_CONFIG) 1306 1307 #define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0 1308 #define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT 8 1309 #define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT 11 1310 #define UVH_GR1_TLB_INT1_CONFIG_STATUS_SHFT 12 1311 #define UVH_GR1_TLB_INT1_CONFIG_P_SHFT 13 1312 #define UVH_GR1_TLB_INT1_CONFIG_T_SHFT 15 1313 #define UVH_GR1_TLB_INT1_CONFIG_M_SHFT 16 1314 #define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT 32 1315 #define UVH_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL 1316 #define UVH_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL 1317 #define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL 1318 #define UVH_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL 1319 #define UVH_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL 1320 #define UVH_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL 1321 #define UVH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL 1322 #define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 1323 1324 1325 union uvh_gr1_tlb_int1_config_u { 1326 unsigned long v; 1327 struct uvh_gr1_tlb_int1_config_s { 1328 unsigned long vector_:8; /* RW */ 1329 unsigned long dm:3; /* RW */ 1330 unsigned long destmode:1; /* RW */ 1331 unsigned long status:1; /* RO */ 1332 unsigned long p:1; /* RO */ 1333 unsigned long rsvd_14:1; 1334 unsigned long t:1; /* RO */ 1335 unsigned long m:1; /* RW */ 1336 unsigned long rsvd_17_31:15; 1337 unsigned long apic_id:32; /* RW */ 1338 } s; 1339 }; 1340 1341 /* ========================================================================= */ 1342 /* UVH_GR1_TLB_MMR_CONTROL */ 1343 /* ========================================================================= */ 1344 #define UV1H_GR1_TLB_MMR_CONTROL 0x801080UL 1345 #define UV2H_GR1_TLB_MMR_CONTROL 0x1001080UL 1346 #define UV3H_GR1_TLB_MMR_CONTROL 0x1001080UL 1347 #define UV4H_GR1_TLB_MMR_CONTROL 0x701080UL 1348 #define UVH_GR1_TLB_MMR_CONTROL ( \ 1349 is_uv1_hub() ? UV1H_GR1_TLB_MMR_CONTROL : \ 1350 is_uv2_hub() ? UV2H_GR1_TLB_MMR_CONTROL : \ 1351 is_uv3_hub() ? UV3H_GR1_TLB_MMR_CONTROL : \ 1352 /*is_uv4_hub*/ UV4H_GR1_TLB_MMR_CONTROL) 1353 1354 #define UVH_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 1355 #define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 1356 #define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 1357 #define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 1358 #define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31 1359 #define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 1360 #define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 1361 #define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 1362 #define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 1363 1364 #define UV1H_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 1365 #define UV1H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 1366 #define UV1H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 1367 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 1368 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 1369 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31 1370 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT 48 1371 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT 52 1372 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_SHFT 54 1373 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_SHFT 56 1374 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_SHFT 60 1375 #define UV1H_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL 1376 #define UV1H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL 1377 #define UV1H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 1378 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 1379 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 1380 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 1381 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL 1382 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL 1383 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_MASK 0x0040000000000000UL 1384 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK 0x0100000000000000UL 1385 #define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK 0x1000000000000000UL 1386 1387 #define UVXH_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 1388 #define UVXH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 1389 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 1390 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 1391 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31 1392 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 1393 #define UVXH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 1394 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 1395 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 1396 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 1397 #define UVXH_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 1398 1399 #define UV2H_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 1400 #define UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 1401 #define UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 1402 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 1403 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 1404 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31 1405 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 1406 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT 48 1407 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT 52 1408 #define UV2H_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL 1409 #define UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL 1410 #define UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 1411 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 1412 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 1413 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 1414 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 1415 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK 0x0001000000000000UL 1416 #define UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK 0x0010000000000000UL 1417 1418 #define UV3H_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 1419 #define UV3H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12 1420 #define UV3H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 1421 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 1422 #define UV3H_GR1_TLB_MMR_CONTROL_ECC_SEL_SHFT 21 1423 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 1424 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31 1425 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 1426 #define UV3H_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL 1427 #define UV3H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL 1428 #define UV3H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 1429 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 1430 #define UV3H_GR1_TLB_MMR_CONTROL_ECC_SEL_MASK 0x0000000000200000UL 1431 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 1432 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 1433 #define UV3H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 1434 1435 #define UV4H_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 1436 #define UV4H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 13 1437 #define UV4H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 1438 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 1439 #define UV4H_GR1_TLB_MMR_CONTROL_ECC_SEL_SHFT 21 1440 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 1441 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31 1442 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 1443 #define UV4H_GR1_TLB_MMR_CONTROL_PAGE_SIZE_SHFT 59 1444 #define UV4H_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000001fffUL 1445 #define UV4H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000006000UL 1446 #define UV4H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 1447 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 1448 #define UV4H_GR1_TLB_MMR_CONTROL_ECC_SEL_MASK 0x0000000000200000UL 1449 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 1450 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 1451 #define UV4H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 1452 #define UV4H_GR1_TLB_MMR_CONTROL_PAGE_SIZE_MASK 0xf800000000000000UL 1453 1454 1455 union uvh_gr1_tlb_mmr_control_u { 1456 unsigned long v; 1457 struct uvh_gr1_tlb_mmr_control_s { 1458 unsigned long rsvd_0_15:16; 1459 unsigned long auto_valid_en:1; /* RW */ 1460 unsigned long rsvd_17_19:3; 1461 unsigned long mmr_hash_index_en:1; /* RW */ 1462 unsigned long rsvd_21_29:9; 1463 unsigned long mmr_write:1; /* WP */ 1464 unsigned long mmr_read:1; /* WP */ 1465 unsigned long rsvd_32_48:17; 1466 unsigned long rsvd_49_51:3; 1467 unsigned long rsvd_52_63:12; 1468 } s; 1469 struct uv1h_gr1_tlb_mmr_control_s { 1470 unsigned long index:12; /* RW */ 1471 unsigned long mem_sel:2; /* RW */ 1472 unsigned long rsvd_14_15:2; 1473 unsigned long auto_valid_en:1; /* RW */ 1474 unsigned long rsvd_17_19:3; 1475 unsigned long mmr_hash_index_en:1; /* RW */ 1476 unsigned long rsvd_21_29:9; 1477 unsigned long mmr_write:1; /* WP */ 1478 unsigned long mmr_read:1; /* WP */ 1479 unsigned long rsvd_32_47:16; 1480 unsigned long mmr_inj_con:1; /* RW */ 1481 unsigned long rsvd_49_51:3; 1482 unsigned long mmr_inj_tlbram:1; /* RW */ 1483 unsigned long rsvd_53:1; 1484 unsigned long mmr_inj_tlbpgsize:1; /* RW */ 1485 unsigned long rsvd_55:1; 1486 unsigned long mmr_inj_tlbrreg:1; /* RW */ 1487 unsigned long rsvd_57_59:3; 1488 unsigned long mmr_inj_tlblruv:1; /* RW */ 1489 unsigned long rsvd_61_63:3; 1490 } s1; 1491 struct uvxh_gr1_tlb_mmr_control_s { 1492 unsigned long rsvd_0_15:16; 1493 unsigned long auto_valid_en:1; /* RW */ 1494 unsigned long rsvd_17_19:3; 1495 unsigned long mmr_hash_index_en:1; /* RW */ 1496 unsigned long rsvd_21_29:9; 1497 unsigned long mmr_write:1; /* WP */ 1498 unsigned long mmr_read:1; /* WP */ 1499 unsigned long mmr_op_done:1; /* RW */ 1500 unsigned long rsvd_33_47:15; 1501 unsigned long rsvd_48:1; 1502 unsigned long rsvd_49_51:3; 1503 unsigned long rsvd_52_63:12; 1504 } sx; 1505 struct uv2h_gr1_tlb_mmr_control_s { 1506 unsigned long index:12; /* RW */ 1507 unsigned long mem_sel:2; /* RW */ 1508 unsigned long rsvd_14_15:2; 1509 unsigned long auto_valid_en:1; /* RW */ 1510 unsigned long rsvd_17_19:3; 1511 unsigned long mmr_hash_index_en:1; /* RW */ 1512 unsigned long rsvd_21_29:9; 1513 unsigned long mmr_write:1; /* WP */ 1514 unsigned long mmr_read:1; /* WP */ 1515 unsigned long mmr_op_done:1; /* RW */ 1516 unsigned long rsvd_33_47:15; 1517 unsigned long mmr_inj_con:1; /* RW */ 1518 unsigned long rsvd_49_51:3; 1519 unsigned long mmr_inj_tlbram:1; /* RW */ 1520 unsigned long rsvd_53_63:11; 1521 } s2; 1522 struct uv3h_gr1_tlb_mmr_control_s { 1523 unsigned long index:12; /* RW */ 1524 unsigned long mem_sel:2; /* RW */ 1525 unsigned long rsvd_14_15:2; 1526 unsigned long auto_valid_en:1; /* RW */ 1527 unsigned long rsvd_17_19:3; 1528 unsigned long mmr_hash_index_en:1; /* RW */ 1529 unsigned long ecc_sel:1; /* RW */ 1530 unsigned long rsvd_22_29:8; 1531 unsigned long mmr_write:1; /* WP */ 1532 unsigned long mmr_read:1; /* WP */ 1533 unsigned long mmr_op_done:1; /* RW */ 1534 unsigned long rsvd_33_47:15; 1535 unsigned long undef_48:1; /* Undefined */ 1536 unsigned long rsvd_49_51:3; 1537 unsigned long undef_52:1; /* Undefined */ 1538 unsigned long rsvd_53_63:11; 1539 } s3; 1540 struct uv4h_gr1_tlb_mmr_control_s { 1541 unsigned long index:13; /* RW */ 1542 unsigned long mem_sel:2; /* RW */ 1543 unsigned long rsvd_15:1; 1544 unsigned long auto_valid_en:1; /* RW */ 1545 unsigned long rsvd_17_19:3; 1546 unsigned long mmr_hash_index_en:1; /* RW */ 1547 unsigned long ecc_sel:1; /* RW */ 1548 unsigned long rsvd_22_29:8; 1549 unsigned long mmr_write:1; /* WP */ 1550 unsigned long mmr_read:1; /* WP */ 1551 unsigned long mmr_op_done:1; /* RW */ 1552 unsigned long rsvd_33_47:15; 1553 unsigned long undef_48:1; /* Undefined */ 1554 unsigned long rsvd_49_51:3; 1555 unsigned long rsvd_52_58:7; 1556 unsigned long page_size:5; /* RW */ 1557 } s4; 1558 }; 1559 1560 /* ========================================================================= */ 1561 /* UVH_GR1_TLB_MMR_READ_DATA_HI */ 1562 /* ========================================================================= */ 1563 #define UV1H_GR1_TLB_MMR_READ_DATA_HI 0x8010a0UL 1564 #define UV2H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL 1565 #define UV3H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL 1566 #define UV4H_GR1_TLB_MMR_READ_DATA_HI 0x7010a0UL 1567 #define UVH_GR1_TLB_MMR_READ_DATA_HI ( \ 1568 is_uv1_hub() ? UV1H_GR1_TLB_MMR_READ_DATA_HI : \ 1569 is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_HI : \ 1570 is_uv3_hub() ? UV3H_GR1_TLB_MMR_READ_DATA_HI : \ 1571 /*is_uv4_hub*/ UV4H_GR1_TLB_MMR_READ_DATA_HI) 1572 1573 #define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1574 1575 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1576 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 1577 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 1578 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 1579 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL 1580 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL 1581 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL 1582 #define UV1H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 1583 1584 #define UVXH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1585 1586 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1587 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 1588 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 1589 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 1590 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL 1591 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL 1592 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL 1593 #define UV2H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 1594 1595 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1596 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 1597 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43 1598 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44 1599 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT 45 1600 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT 55 1601 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL 1602 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL 1603 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL 1604 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 1605 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_MASK 0x0000200000000000UL 1606 #define UV3H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK 0xff80000000000000UL 1607 1608 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1609 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_PNID_SHFT 34 1610 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 49 1611 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 51 1612 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT 52 1613 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT 53 1614 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT 55 1615 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK 0x00000003ffffffffUL 1616 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_PNID_MASK 0x0001fffc00000000UL 1617 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0006000000000000UL 1618 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0008000000000000UL 1619 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0010000000000000UL 1620 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_MASK 0x0020000000000000UL 1621 #define UV4H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK 0xff80000000000000UL 1622 1623 1624 union uvh_gr1_tlb_mmr_read_data_hi_u { 1625 unsigned long v; 1626 struct uv1h_gr1_tlb_mmr_read_data_hi_s { 1627 unsigned long pfn:41; /* RO */ 1628 unsigned long gaa:2; /* RO */ 1629 unsigned long dirty:1; /* RO */ 1630 unsigned long larger:1; /* RO */ 1631 unsigned long rsvd_45_63:19; 1632 } s1; 1633 struct uv2h_gr1_tlb_mmr_read_data_hi_s { 1634 unsigned long pfn:41; /* RO */ 1635 unsigned long gaa:2; /* RO */ 1636 unsigned long dirty:1; /* RO */ 1637 unsigned long larger:1; /* RO */ 1638 unsigned long rsvd_45_63:19; 1639 } s2; 1640 struct uv3h_gr1_tlb_mmr_read_data_hi_s { 1641 unsigned long pfn:41; /* RO */ 1642 unsigned long gaa:2; /* RO */ 1643 unsigned long dirty:1; /* RO */ 1644 unsigned long larger:1; /* RO */ 1645 unsigned long aa_ext:1; /* RO */ 1646 unsigned long undef_46_54:9; /* Undefined */ 1647 unsigned long way_ecc:9; /* RO */ 1648 } s3; 1649 struct uv4h_gr1_tlb_mmr_read_data_hi_s { 1650 unsigned long pfn:34; /* RO */ 1651 unsigned long pnid:15; /* RO */ 1652 unsigned long gaa:2; /* RO */ 1653 unsigned long dirty:1; /* RO */ 1654 unsigned long larger:1; /* RO */ 1655 unsigned long aa_ext:1; /* RO */ 1656 unsigned long undef_54:1; /* Undefined */ 1657 unsigned long way_ecc:9; /* RO */ 1658 } s4; 1659 }; 1660 1661 /* ========================================================================= */ 1662 /* UVH_GR1_TLB_MMR_READ_DATA_LO */ 1663 /* ========================================================================= */ 1664 #define UV1H_GR1_TLB_MMR_READ_DATA_LO 0x8010a8UL 1665 #define UV2H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL 1666 #define UV3H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL 1667 #define UV4H_GR1_TLB_MMR_READ_DATA_LO 0x7010a8UL 1668 #define UVH_GR1_TLB_MMR_READ_DATA_LO ( \ 1669 is_uv1_hub() ? UV1H_GR1_TLB_MMR_READ_DATA_LO : \ 1670 is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_LO : \ 1671 is_uv3_hub() ? UV3H_GR1_TLB_MMR_READ_DATA_LO : \ 1672 /*is_uv4_hub*/ UV4H_GR1_TLB_MMR_READ_DATA_LO) 1673 1674 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1675 #define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1676 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1677 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1678 #define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1679 #define UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1680 1681 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1682 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1683 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1684 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1685 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1686 #define UV1H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1687 1688 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1689 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1690 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1691 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1692 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1693 #define UVXH_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1694 1695 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1696 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1697 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1698 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1699 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1700 #define UV2H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1701 1702 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1703 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1704 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1705 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1706 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1707 #define UV3H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1708 1709 #define UV4H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1710 #define UV4H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1711 #define UV4H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT 63 1712 #define UV4H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL 1713 #define UV4H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1714 #define UV4H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1715 1716 1717 union uvh_gr1_tlb_mmr_read_data_lo_u { 1718 unsigned long v; 1719 struct uvh_gr1_tlb_mmr_read_data_lo_s { 1720 unsigned long vpn:39; /* RO */ 1721 unsigned long asid:24; /* RO */ 1722 unsigned long valid:1; /* RO */ 1723 } s; 1724 struct uv1h_gr1_tlb_mmr_read_data_lo_s { 1725 unsigned long vpn:39; /* RO */ 1726 unsigned long asid:24; /* RO */ 1727 unsigned long valid:1; /* RO */ 1728 } s1; 1729 struct uvxh_gr1_tlb_mmr_read_data_lo_s { 1730 unsigned long vpn:39; /* RO */ 1731 unsigned long asid:24; /* RO */ 1732 unsigned long valid:1; /* RO */ 1733 } sx; 1734 struct uv2h_gr1_tlb_mmr_read_data_lo_s { 1735 unsigned long vpn:39; /* RO */ 1736 unsigned long asid:24; /* RO */ 1737 unsigned long valid:1; /* RO */ 1738 } s2; 1739 struct uv3h_gr1_tlb_mmr_read_data_lo_s { 1740 unsigned long vpn:39; /* RO */ 1741 unsigned long asid:24; /* RO */ 1742 unsigned long valid:1; /* RO */ 1743 } s3; 1744 struct uv4h_gr1_tlb_mmr_read_data_lo_s { 1745 unsigned long vpn:39; /* RO */ 1746 unsigned long asid:24; /* RO */ 1747 unsigned long valid:1; /* RO */ 1748 } s4; 1749 }; 1750 1751 /* ========================================================================= */ 1752 /* UVH_INT_CMPB */ 1753 /* ========================================================================= */ 1754 #define UVH_INT_CMPB 0x22080UL 1755 1756 #define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0 1757 #define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL 1758 1759 1760 union uvh_int_cmpb_u { 1761 unsigned long v; 1762 struct uvh_int_cmpb_s { 1763 unsigned long real_time_cmpb:56; /* RW */ 1764 unsigned long rsvd_56_63:8; 1765 } s; 1766 }; 1767 1768 /* ========================================================================= */ 1769 /* UVH_INT_CMPC */ 1770 /* ========================================================================= */ 1771 #define UVH_INT_CMPC 0x22100UL 1772 1773 1774 #define UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT 0 1775 #define UV1H_INT_CMPC_REAL_TIME_CMPC_MASK 0x00ffffffffffffffUL 1776 1777 #define UVXH_INT_CMPC_REAL_TIME_CMP_2_SHFT 0 1778 #define UVXH_INT_CMPC_REAL_TIME_CMP_2_MASK 0x00ffffffffffffffUL 1779 1780 1781 union uvh_int_cmpc_u { 1782 unsigned long v; 1783 struct uvh_int_cmpc_s { 1784 unsigned long real_time_cmpc:56; /* RW */ 1785 unsigned long rsvd_56_63:8; 1786 } s; 1787 }; 1788 1789 /* ========================================================================= */ 1790 /* UVH_INT_CMPD */ 1791 /* ========================================================================= */ 1792 #define UVH_INT_CMPD 0x22180UL 1793 1794 1795 #define UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT 0 1796 #define UV1H_INT_CMPD_REAL_TIME_CMPD_MASK 0x00ffffffffffffffUL 1797 1798 #define UVXH_INT_CMPD_REAL_TIME_CMP_3_SHFT 0 1799 #define UVXH_INT_CMPD_REAL_TIME_CMP_3_MASK 0x00ffffffffffffffUL 1800 1801 1802 union uvh_int_cmpd_u { 1803 unsigned long v; 1804 struct uvh_int_cmpd_s { 1805 unsigned long real_time_cmpd:56; /* RW */ 1806 unsigned long rsvd_56_63:8; 1807 } s; 1808 }; 1809 1810 /* ========================================================================= */ 1811 /* UVH_IPI_INT */ 1812 /* ========================================================================= */ 1813 #define UVH_IPI_INT 0x60500UL 1814 1815 #define UV1H_IPI_INT_32 0x348 1816 #define UV2H_IPI_INT_32 0x348 1817 #define UV3H_IPI_INT_32 0x348 1818 #define UV4H_IPI_INT_32 0x268 1819 #define UVH_IPI_INT_32 ( \ 1820 is_uv1_hub() ? UV1H_IPI_INT_32 : \ 1821 is_uv2_hub() ? UV2H_IPI_INT_32 : \ 1822 is_uv3_hub() ? UV3H_IPI_INT_32 : \ 1823 /*is_uv4_hub*/ UV4H_IPI_INT_32) 1824 1825 #define UVH_IPI_INT_VECTOR_SHFT 0 1826 #define UVH_IPI_INT_DELIVERY_MODE_SHFT 8 1827 #define UVH_IPI_INT_DESTMODE_SHFT 11 1828 #define UVH_IPI_INT_APIC_ID_SHFT 16 1829 #define UVH_IPI_INT_SEND_SHFT 63 1830 #define UVH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL 1831 #define UVH_IPI_INT_DELIVERY_MODE_MASK 0x0000000000000700UL 1832 #define UVH_IPI_INT_DESTMODE_MASK 0x0000000000000800UL 1833 #define UVH_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL 1834 #define UVH_IPI_INT_SEND_MASK 0x8000000000000000UL 1835 1836 1837 union uvh_ipi_int_u { 1838 unsigned long v; 1839 struct uvh_ipi_int_s { 1840 unsigned long vector_:8; /* RW */ 1841 unsigned long delivery_mode:3; /* RW */ 1842 unsigned long destmode:1; /* RW */ 1843 unsigned long rsvd_12_15:4; 1844 unsigned long apic_id:32; /* RW */ 1845 unsigned long rsvd_48_62:15; 1846 unsigned long send:1; /* WP */ 1847 } s; 1848 }; 1849 1850 /* ========================================================================= */ 1851 /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST */ 1852 /* ========================================================================= */ 1853 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL 1854 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL 1855 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL 1856 #define UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST uv_undefined("UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST") 1857 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST ( \ 1858 is_uv1_hub() ? UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST : \ 1859 is_uv2_hub() ? UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST : \ 1860 is_uv3_hub() ? UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST : \ 1861 /*is_uv4_hub*/ UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST) 1862 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x9c0 1863 1864 1865 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4 1866 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49 1867 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL 1868 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL 1869 1870 1871 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4 1872 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49 1873 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL 1874 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL 1875 1876 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4 1877 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49 1878 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL 1879 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL 1880 1881 1882 union uvh_lb_bau_intd_payload_queue_first_u { 1883 unsigned long v; 1884 struct uv1h_lb_bau_intd_payload_queue_first_s { 1885 unsigned long rsvd_0_3:4; 1886 unsigned long address:39; /* RW */ 1887 unsigned long rsvd_43_48:6; 1888 unsigned long node_id:14; /* RW */ 1889 unsigned long rsvd_63:1; 1890 } s1; 1891 struct uv2h_lb_bau_intd_payload_queue_first_s { 1892 unsigned long rsvd_0_3:4; 1893 unsigned long address:39; /* RW */ 1894 unsigned long rsvd_43_48:6; 1895 unsigned long node_id:14; /* RW */ 1896 unsigned long rsvd_63:1; 1897 } s2; 1898 struct uv3h_lb_bau_intd_payload_queue_first_s { 1899 unsigned long rsvd_0_3:4; 1900 unsigned long address:39; /* RW */ 1901 unsigned long rsvd_43_48:6; 1902 unsigned long node_id:14; /* RW */ 1903 unsigned long rsvd_63:1; 1904 } s3; 1905 }; 1906 1907 /* ========================================================================= */ 1908 /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST */ 1909 /* ========================================================================= */ 1910 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL 1911 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL 1912 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL 1913 #define UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST uv_undefined("UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST") 1914 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST ( \ 1915 is_uv1_hub() ? UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST : \ 1916 is_uv2_hub() ? UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST : \ 1917 is_uv3_hub() ? UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST : \ 1918 /*is_uv4_hub*/ UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST) 1919 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x9c8 1920 1921 1922 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4 1923 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL 1924 1925 1926 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4 1927 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL 1928 1929 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4 1930 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL 1931 1932 1933 union uvh_lb_bau_intd_payload_queue_last_u { 1934 unsigned long v; 1935 struct uv1h_lb_bau_intd_payload_queue_last_s { 1936 unsigned long rsvd_0_3:4; 1937 unsigned long address:39; /* RW */ 1938 unsigned long rsvd_43_63:21; 1939 } s1; 1940 struct uv2h_lb_bau_intd_payload_queue_last_s { 1941 unsigned long rsvd_0_3:4; 1942 unsigned long address:39; /* RW */ 1943 unsigned long rsvd_43_63:21; 1944 } s2; 1945 struct uv3h_lb_bau_intd_payload_queue_last_s { 1946 unsigned long rsvd_0_3:4; 1947 unsigned long address:39; /* RW */ 1948 unsigned long rsvd_43_63:21; 1949 } s3; 1950 }; 1951 1952 /* ========================================================================= */ 1953 /* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL */ 1954 /* ========================================================================= */ 1955 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL 1956 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL 1957 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL 1958 #define UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL uv_undefined("UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL") 1959 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL ( \ 1960 is_uv1_hub() ? UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL : \ 1961 is_uv2_hub() ? UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL : \ 1962 is_uv3_hub() ? UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL : \ 1963 /*is_uv4_hub*/ UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL) 1964 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x9d0 1965 1966 1967 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4 1968 #define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL 1969 1970 1971 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4 1972 #define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL 1973 1974 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4 1975 #define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL 1976 1977 1978 union uvh_lb_bau_intd_payload_queue_tail_u { 1979 unsigned long v; 1980 struct uv1h_lb_bau_intd_payload_queue_tail_s { 1981 unsigned long rsvd_0_3:4; 1982 unsigned long address:39; /* RW */ 1983 unsigned long rsvd_43_63:21; 1984 } s1; 1985 struct uv2h_lb_bau_intd_payload_queue_tail_s { 1986 unsigned long rsvd_0_3:4; 1987 unsigned long address:39; /* RW */ 1988 unsigned long rsvd_43_63:21; 1989 } s2; 1990 struct uv3h_lb_bau_intd_payload_queue_tail_s { 1991 unsigned long rsvd_0_3:4; 1992 unsigned long address:39; /* RW */ 1993 unsigned long rsvd_43_63:21; 1994 } s3; 1995 }; 1996 1997 /* ========================================================================= */ 1998 /* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE */ 1999 /* ========================================================================= */ 2000 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL 2001 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL 2002 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL 2003 #define UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE uv_undefined("UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE") 2004 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE ( \ 2005 is_uv1_hub() ? UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE : \ 2006 is_uv2_hub() ? UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE : \ 2007 is_uv3_hub() ? UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE : \ 2008 /*is_uv4_hub*/ UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE) 2009 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0xa68 2010 2011 2012 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 2013 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1 2014 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2 2015 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3 2016 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4 2017 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5 2018 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6 2019 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7 2020 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8 2021 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9 2022 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10 2023 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11 2024 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12 2025 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13 2026 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14 2027 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15 2028 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL 2029 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL 2030 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL 2031 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL 2032 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL 2033 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL 2034 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL 2035 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL 2036 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL 2037 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL 2038 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL 2039 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL 2040 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL 2041 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL 2042 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL 2043 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL 2044 2045 2046 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 2047 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1 2048 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2 2049 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3 2050 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4 2051 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5 2052 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6 2053 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7 2054 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8 2055 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9 2056 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10 2057 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11 2058 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12 2059 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13 2060 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14 2061 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15 2062 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL 2063 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL 2064 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL 2065 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL 2066 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL 2067 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL 2068 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL 2069 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL 2070 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL 2071 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL 2072 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL 2073 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL 2074 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL 2075 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL 2076 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL 2077 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL 2078 2079 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 2080 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1 2081 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2 2082 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3 2083 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4 2084 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5 2085 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6 2086 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7 2087 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8 2088 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9 2089 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10 2090 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11 2091 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12 2092 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13 2093 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14 2094 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15 2095 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL 2096 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL 2097 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL 2098 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL 2099 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL 2100 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL 2101 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL 2102 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL 2103 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL 2104 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL 2105 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL 2106 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL 2107 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL 2108 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL 2109 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL 2110 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL 2111 2112 2113 union uvh_lb_bau_intd_software_acknowledge_u { 2114 unsigned long v; 2115 struct uv1h_lb_bau_intd_software_acknowledge_s { 2116 unsigned long pending_0:1; /* RW, W1C */ 2117 unsigned long pending_1:1; /* RW, W1C */ 2118 unsigned long pending_2:1; /* RW, W1C */ 2119 unsigned long pending_3:1; /* RW, W1C */ 2120 unsigned long pending_4:1; /* RW, W1C */ 2121 unsigned long pending_5:1; /* RW, W1C */ 2122 unsigned long pending_6:1; /* RW, W1C */ 2123 unsigned long pending_7:1; /* RW, W1C */ 2124 unsigned long timeout_0:1; /* RW, W1C */ 2125 unsigned long timeout_1:1; /* RW, W1C */ 2126 unsigned long timeout_2:1; /* RW, W1C */ 2127 unsigned long timeout_3:1; /* RW, W1C */ 2128 unsigned long timeout_4:1; /* RW, W1C */ 2129 unsigned long timeout_5:1; /* RW, W1C */ 2130 unsigned long timeout_6:1; /* RW, W1C */ 2131 unsigned long timeout_7:1; /* RW, W1C */ 2132 unsigned long rsvd_16_63:48; 2133 } s1; 2134 struct uv2h_lb_bau_intd_software_acknowledge_s { 2135 unsigned long pending_0:1; /* RW */ 2136 unsigned long pending_1:1; /* RW */ 2137 unsigned long pending_2:1; /* RW */ 2138 unsigned long pending_3:1; /* RW */ 2139 unsigned long pending_4:1; /* RW */ 2140 unsigned long pending_5:1; /* RW */ 2141 unsigned long pending_6:1; /* RW */ 2142 unsigned long pending_7:1; /* RW */ 2143 unsigned long timeout_0:1; /* RW */ 2144 unsigned long timeout_1:1; /* RW */ 2145 unsigned long timeout_2:1; /* RW */ 2146 unsigned long timeout_3:1; /* RW */ 2147 unsigned long timeout_4:1; /* RW */ 2148 unsigned long timeout_5:1; /* RW */ 2149 unsigned long timeout_6:1; /* RW */ 2150 unsigned long timeout_7:1; /* RW */ 2151 unsigned long rsvd_16_63:48; 2152 } s2; 2153 struct uv3h_lb_bau_intd_software_acknowledge_s { 2154 unsigned long pending_0:1; /* RW */ 2155 unsigned long pending_1:1; /* RW */ 2156 unsigned long pending_2:1; /* RW */ 2157 unsigned long pending_3:1; /* RW */ 2158 unsigned long pending_4:1; /* RW */ 2159 unsigned long pending_5:1; /* RW */ 2160 unsigned long pending_6:1; /* RW */ 2161 unsigned long pending_7:1; /* RW */ 2162 unsigned long timeout_0:1; /* RW */ 2163 unsigned long timeout_1:1; /* RW */ 2164 unsigned long timeout_2:1; /* RW */ 2165 unsigned long timeout_3:1; /* RW */ 2166 unsigned long timeout_4:1; /* RW */ 2167 unsigned long timeout_5:1; /* RW */ 2168 unsigned long timeout_6:1; /* RW */ 2169 unsigned long timeout_7:1; /* RW */ 2170 unsigned long rsvd_16_63:48; 2171 } s3; 2172 }; 2173 2174 /* ========================================================================= */ 2175 /* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS */ 2176 /* ========================================================================= */ 2177 #define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL 2178 #define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL 2179 #define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL 2180 #define UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS uv_undefined("UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS") 2181 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS ( \ 2182 is_uv1_hub() ? UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS : \ 2183 is_uv2_hub() ? UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS : \ 2184 is_uv3_hub() ? UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS : \ 2185 /*is_uv4_hub*/ UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS) 2186 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0xa70 2187 2188 2189 /* ========================================================================= */ 2190 /* UVH_LB_BAU_MISC_CONTROL */ 2191 /* ========================================================================= */ 2192 #define UV1H_LB_BAU_MISC_CONTROL 0x320170UL 2193 #define UV2H_LB_BAU_MISC_CONTROL 0x320170UL 2194 #define UV3H_LB_BAU_MISC_CONTROL 0x320170UL 2195 #define UV4H_LB_BAU_MISC_CONTROL 0xc8170UL 2196 #define UVH_LB_BAU_MISC_CONTROL ( \ 2197 is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL : \ 2198 is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL : \ 2199 is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL : \ 2200 /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL) 2201 2202 #define UV1H_LB_BAU_MISC_CONTROL_32 0xa10 2203 #define UV2H_LB_BAU_MISC_CONTROL_32 0xa10 2204 #define UV3H_LB_BAU_MISC_CONTROL_32 0xa10 2205 #define UV4H_LB_BAU_MISC_CONTROL_32 0xa18 2206 #define UVH_LB_BAU_MISC_CONTROL_32 ( \ 2207 is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_32 : \ 2208 is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_32 : \ 2209 is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_32 : \ 2210 /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_32) 2211 2212 #define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 2213 #define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 2214 #define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 2215 #define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 2216 #define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 2217 #define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 2218 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 2219 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 2220 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 2221 #define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 2222 #define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 2223 #define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 2224 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 2225 #define UVH_LB_BAU_MISC_CONTROL_FUN_SHFT 48 2226 #define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 2227 #define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL 2228 #define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL 2229 #define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 2230 #define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 2231 #define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 2232 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL 2233 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL 2234 #define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL 2235 #define UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL 2236 #define UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL 2237 #define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL 2238 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 2239 #define UVH_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 2240 2241 #define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 2242 #define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 2243 #define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 2244 #define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 2245 #define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 2246 #define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 2247 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15 2248 #define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16 2249 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 2250 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 2251 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 2252 #define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 2253 #define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 2254 #define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 2255 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 2256 #define UV1H_LB_BAU_MISC_CONTROL_FUN_SHFT 48 2257 #define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 2258 #define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL 2259 #define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL 2260 #define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 2261 #define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 2262 #define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 2263 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL 2264 #define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL 2265 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL 2266 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL 2267 #define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL 2268 #define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL 2269 #define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL 2270 #define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL 2271 #define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 2272 #define UV1H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 2273 2274 #define UVXH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 2275 #define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 2276 #define UVXH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 2277 #define UVXH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 2278 #define UVXH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 2279 #define UVXH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 2280 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 2281 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 2282 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 2283 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 2284 #define UVXH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 2285 #define UVXH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 2286 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 2287 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29 2288 #define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT 30 2289 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31 2290 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32 2291 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33 2292 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34 2293 #define UVXH_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35 2294 #define UVXH_LB_BAU_MISC_CONTROL_FUN_SHFT 48 2295 #define UVXH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 2296 #define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL 2297 #define UVXH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL 2298 #define UVXH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 2299 #define UVXH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 2300 #define UVXH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 2301 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL 2302 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL 2303 #define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL 2304 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL 2305 #define UVXH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL 2306 #define UVXH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL 2307 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 2308 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL 2309 #define UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK 0x0000000040000000UL 2310 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL 2311 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL 2312 #define UVXH_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL 2313 #define UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL 2314 #define UVXH_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL 2315 #define UVXH_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 2316 2317 #define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 2318 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 2319 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 2320 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 2321 #define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 2322 #define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 2323 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15 2324 #define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16 2325 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 2326 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 2327 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 2328 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 2329 #define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 2330 #define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 2331 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 2332 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29 2333 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT 30 2334 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31 2335 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32 2336 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33 2337 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34 2338 #define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35 2339 #define UV2H_LB_BAU_MISC_CONTROL_FUN_SHFT 48 2340 #define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 2341 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL 2342 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL 2343 #define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 2344 #define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 2345 #define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 2346 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL 2347 #define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL 2348 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL 2349 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL 2350 #define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL 2351 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL 2352 #define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL 2353 #define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL 2354 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 2355 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL 2356 #define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK 0x0000000040000000UL 2357 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL 2358 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL 2359 #define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL 2360 #define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL 2361 #define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL 2362 #define UV2H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 2363 2364 #define UV3H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 2365 #define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 2366 #define UV3H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 2367 #define UV3H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 2368 #define UV3H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 2369 #define UV3H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 2370 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15 2371 #define UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16 2372 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 2373 #define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 2374 #define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 2375 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 2376 #define UV3H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 2377 #define UV3H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 2378 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 2379 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29 2380 #define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT 30 2381 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31 2382 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32 2383 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33 2384 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34 2385 #define UV3H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35 2386 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_SHFT 36 2387 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_PREFETCH_HINT_SHFT 37 2388 #define UV3H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_SHFT 38 2389 #define UV3H_LB_BAU_MISC_CONTROL_FUN_SHFT 48 2390 #define UV3H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 2391 #define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL 2392 #define UV3H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL 2393 #define UV3H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 2394 #define UV3H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 2395 #define UV3H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 2396 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL 2397 #define UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL 2398 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL 2399 #define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL 2400 #define UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL 2401 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL 2402 #define UV3H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL 2403 #define UV3H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL 2404 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 2405 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL 2406 #define UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK 0x0000000040000000UL 2407 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL 2408 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL 2409 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL 2410 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL 2411 #define UV3H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL 2412 #define UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_MASK 0x0000001000000000UL 2413 #define UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_PREFETCH_HINT_MASK 0x0000002000000000UL 2414 #define UV3H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_MASK 0x00003fc000000000UL 2415 #define UV3H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 2416 2417 #define UV4H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 2418 #define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 2419 #define UV4H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9 2420 #define UV4H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 2421 #define UV4H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 2422 #define UV4H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 2423 #define UV4H_LB_BAU_MISC_CONTROL_RESERVED_15_19_SHFT 15 2424 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 2425 #define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 2426 #define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 2427 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23 2428 #define UV4H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24 2429 #define UV4H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27 2430 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28 2431 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29 2432 #define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT 30 2433 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31 2434 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32 2435 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33 2436 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34 2437 #define UV4H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35 2438 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_SHFT 36 2439 #define UV4H_LB_BAU_MISC_CONTROL_RESERVED_37_SHFT 37 2440 #define UV4H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_SHFT 38 2441 #define UV4H_LB_BAU_MISC_CONTROL_ADDRESS_INTERLEAVE_SELECT_SHFT 46 2442 #define UV4H_LB_BAU_MISC_CONTROL_FUN_SHFT 48 2443 #define UV4H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL 2444 #define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL 2445 #define UV4H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL 2446 #define UV4H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 2447 #define UV4H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 2448 #define UV4H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 2449 #define UV4H_LB_BAU_MISC_CONTROL_RESERVED_15_19_MASK 0x00000000000f8000UL 2450 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL 2451 #define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL 2452 #define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL 2453 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL 2454 #define UV4H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL 2455 #define UV4H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL 2456 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL 2457 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL 2458 #define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK 0x0000000040000000UL 2459 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL 2460 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL 2461 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL 2462 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL 2463 #define UV4H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL 2464 #define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_MASK 0x0000001000000000UL 2465 #define UV4H_LB_BAU_MISC_CONTROL_RESERVED_37_MASK 0x0000002000000000UL 2466 #define UV4H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_MASK 0x00003fc000000000UL 2467 #define UV4H_LB_BAU_MISC_CONTROL_ADDRESS_INTERLEAVE_SELECT_MASK 0x0000400000000000UL 2468 #define UV4H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 2469 2470 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK \ 2471 uv_undefined("UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK") 2472 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK ( \ 2473 is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK : \ 2474 is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK : \ 2475 is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK : \ 2476 /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK) 2477 #define UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT \ 2478 uv_undefined("UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT") 2479 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT ( \ 2480 is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT : \ 2481 is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT : \ 2482 is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT : \ 2483 /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT) 2484 #define UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK \ 2485 uv_undefined("UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK") 2486 #define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK ( \ 2487 is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK : \ 2488 is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK : \ 2489 is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK : \ 2490 /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK) 2491 #define UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT \ 2492 uv_undefined("UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT") 2493 #define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT ( \ 2494 is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT : \ 2495 is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT : \ 2496 is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT : \ 2497 /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT) 2498 2499 union uvh_lb_bau_misc_control_u { 2500 unsigned long v; 2501 struct uvh_lb_bau_misc_control_s { 2502 unsigned long rejection_delay:8; /* RW */ 2503 unsigned long apic_mode:1; /* RW */ 2504 unsigned long force_broadcast:1; /* RW */ 2505 unsigned long force_lock_nop:1; /* RW */ 2506 unsigned long qpi_agent_presence_vector:3; /* RW */ 2507 unsigned long descriptor_fetch_mode:1; /* RW */ 2508 unsigned long rsvd_15_19:5; 2509 unsigned long enable_dual_mapping_mode:1; /* RW */ 2510 unsigned long vga_io_port_decode_enable:1; /* RW */ 2511 unsigned long vga_io_port_16_bit_decode:1; /* RW */ 2512 unsigned long suppress_dest_registration:1; /* RW */ 2513 unsigned long programmed_initial_priority:3; /* RW */ 2514 unsigned long use_incoming_priority:1; /* RW */ 2515 unsigned long enable_programmed_initial_priority:1;/* RW */ 2516 unsigned long rsvd_29_47:19; 2517 unsigned long fun:16; /* RW */ 2518 } s; 2519 struct uv1h_lb_bau_misc_control_s { 2520 unsigned long rejection_delay:8; /* RW */ 2521 unsigned long apic_mode:1; /* RW */ 2522 unsigned long force_broadcast:1; /* RW */ 2523 unsigned long force_lock_nop:1; /* RW */ 2524 unsigned long qpi_agent_presence_vector:3; /* RW */ 2525 unsigned long descriptor_fetch_mode:1; /* RW */ 2526 unsigned long enable_intd_soft_ack_mode:1; /* RW */ 2527 unsigned long intd_soft_ack_timeout_period:4; /* RW */ 2528 unsigned long enable_dual_mapping_mode:1; /* RW */ 2529 unsigned long vga_io_port_decode_enable:1; /* RW */ 2530 unsigned long vga_io_port_16_bit_decode:1; /* RW */ 2531 unsigned long suppress_dest_registration:1; /* RW */ 2532 unsigned long programmed_initial_priority:3; /* RW */ 2533 unsigned long use_incoming_priority:1; /* RW */ 2534 unsigned long enable_programmed_initial_priority:1;/* RW */ 2535 unsigned long rsvd_29_47:19; 2536 unsigned long fun:16; /* RW */ 2537 } s1; 2538 struct uvxh_lb_bau_misc_control_s { 2539 unsigned long rejection_delay:8; /* RW */ 2540 unsigned long apic_mode:1; /* RW */ 2541 unsigned long force_broadcast:1; /* RW */ 2542 unsigned long force_lock_nop:1; /* RW */ 2543 unsigned long qpi_agent_presence_vector:3; /* RW */ 2544 unsigned long descriptor_fetch_mode:1; /* RW */ 2545 unsigned long rsvd_15_19:5; 2546 unsigned long enable_dual_mapping_mode:1; /* RW */ 2547 unsigned long vga_io_port_decode_enable:1; /* RW */ 2548 unsigned long vga_io_port_16_bit_decode:1; /* RW */ 2549 unsigned long suppress_dest_registration:1; /* RW */ 2550 unsigned long programmed_initial_priority:3; /* RW */ 2551 unsigned long use_incoming_priority:1; /* RW */ 2552 unsigned long enable_programmed_initial_priority:1;/* RW */ 2553 unsigned long enable_automatic_apic_mode_selection:1;/* RW */ 2554 unsigned long apic_mode_status:1; /* RO */ 2555 unsigned long suppress_interrupts_to_self:1; /* RW */ 2556 unsigned long enable_lock_based_system_flush:1;/* RW */ 2557 unsigned long enable_extended_sb_status:1; /* RW */ 2558 unsigned long suppress_int_prio_udt_to_self:1;/* RW */ 2559 unsigned long use_legacy_descriptor_formats:1;/* RW */ 2560 unsigned long rsvd_36_47:12; 2561 unsigned long fun:16; /* RW */ 2562 } sx; 2563 struct uv2h_lb_bau_misc_control_s { 2564 unsigned long rejection_delay:8; /* RW */ 2565 unsigned long apic_mode:1; /* RW */ 2566 unsigned long force_broadcast:1; /* RW */ 2567 unsigned long force_lock_nop:1; /* RW */ 2568 unsigned long qpi_agent_presence_vector:3; /* RW */ 2569 unsigned long descriptor_fetch_mode:1; /* RW */ 2570 unsigned long enable_intd_soft_ack_mode:1; /* RW */ 2571 unsigned long intd_soft_ack_timeout_period:4; /* RW */ 2572 unsigned long enable_dual_mapping_mode:1; /* RW */ 2573 unsigned long vga_io_port_decode_enable:1; /* RW */ 2574 unsigned long vga_io_port_16_bit_decode:1; /* RW */ 2575 unsigned long suppress_dest_registration:1; /* RW */ 2576 unsigned long programmed_initial_priority:3; /* RW */ 2577 unsigned long use_incoming_priority:1; /* RW */ 2578 unsigned long enable_programmed_initial_priority:1;/* RW */ 2579 unsigned long enable_automatic_apic_mode_selection:1;/* RW */ 2580 unsigned long apic_mode_status:1; /* RO */ 2581 unsigned long suppress_interrupts_to_self:1; /* RW */ 2582 unsigned long enable_lock_based_system_flush:1;/* RW */ 2583 unsigned long enable_extended_sb_status:1; /* RW */ 2584 unsigned long suppress_int_prio_udt_to_self:1;/* RW */ 2585 unsigned long use_legacy_descriptor_formats:1;/* RW */ 2586 unsigned long rsvd_36_47:12; 2587 unsigned long fun:16; /* RW */ 2588 } s2; 2589 struct uv3h_lb_bau_misc_control_s { 2590 unsigned long rejection_delay:8; /* RW */ 2591 unsigned long apic_mode:1; /* RW */ 2592 unsigned long force_broadcast:1; /* RW */ 2593 unsigned long force_lock_nop:1; /* RW */ 2594 unsigned long qpi_agent_presence_vector:3; /* RW */ 2595 unsigned long descriptor_fetch_mode:1; /* RW */ 2596 unsigned long enable_intd_soft_ack_mode:1; /* RW */ 2597 unsigned long intd_soft_ack_timeout_period:4; /* RW */ 2598 unsigned long enable_dual_mapping_mode:1; /* RW */ 2599 unsigned long vga_io_port_decode_enable:1; /* RW */ 2600 unsigned long vga_io_port_16_bit_decode:1; /* RW */ 2601 unsigned long suppress_dest_registration:1; /* RW */ 2602 unsigned long programmed_initial_priority:3; /* RW */ 2603 unsigned long use_incoming_priority:1; /* RW */ 2604 unsigned long enable_programmed_initial_priority:1;/* RW */ 2605 unsigned long enable_automatic_apic_mode_selection:1;/* RW */ 2606 unsigned long apic_mode_status:1; /* RO */ 2607 unsigned long suppress_interrupts_to_self:1; /* RW */ 2608 unsigned long enable_lock_based_system_flush:1;/* RW */ 2609 unsigned long enable_extended_sb_status:1; /* RW */ 2610 unsigned long suppress_int_prio_udt_to_self:1;/* RW */ 2611 unsigned long use_legacy_descriptor_formats:1;/* RW */ 2612 unsigned long suppress_quiesce_msgs_to_qpi:1; /* RW */ 2613 unsigned long enable_intd_prefetch_hint:1; /* RW */ 2614 unsigned long thread_kill_timebase:8; /* RW */ 2615 unsigned long rsvd_46_47:2; 2616 unsigned long fun:16; /* RW */ 2617 } s3; 2618 struct uv4h_lb_bau_misc_control_s { 2619 unsigned long rejection_delay:8; /* RW */ 2620 unsigned long apic_mode:1; /* RW */ 2621 unsigned long force_broadcast:1; /* RW */ 2622 unsigned long force_lock_nop:1; /* RW */ 2623 unsigned long qpi_agent_presence_vector:3; /* RW */ 2624 unsigned long descriptor_fetch_mode:1; /* RW */ 2625 unsigned long rsvd_15_19:5; 2626 unsigned long enable_dual_mapping_mode:1; /* RW */ 2627 unsigned long vga_io_port_decode_enable:1; /* RW */ 2628 unsigned long vga_io_port_16_bit_decode:1; /* RW */ 2629 unsigned long suppress_dest_registration:1; /* RW */ 2630 unsigned long programmed_initial_priority:3; /* RW */ 2631 unsigned long use_incoming_priority:1; /* RW */ 2632 unsigned long enable_programmed_initial_priority:1;/* RW */ 2633 unsigned long enable_automatic_apic_mode_selection:1;/* RW */ 2634 unsigned long apic_mode_status:1; /* RO */ 2635 unsigned long suppress_interrupts_to_self:1; /* RW */ 2636 unsigned long enable_lock_based_system_flush:1;/* RW */ 2637 unsigned long enable_extended_sb_status:1; /* RW */ 2638 unsigned long suppress_int_prio_udt_to_self:1;/* RW */ 2639 unsigned long use_legacy_descriptor_formats:1;/* RW */ 2640 unsigned long suppress_quiesce_msgs_to_qpi:1; /* RW */ 2641 unsigned long rsvd_37:1; 2642 unsigned long thread_kill_timebase:8; /* RW */ 2643 unsigned long address_interleave_select:1; /* RW */ 2644 unsigned long rsvd_47:1; 2645 unsigned long fun:16; /* RW */ 2646 } s4; 2647 }; 2648 2649 /* ========================================================================= */ 2650 /* UVH_LB_BAU_SB_ACTIVATION_CONTROL */ 2651 /* ========================================================================= */ 2652 #define UV1H_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL 2653 #define UV2H_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL 2654 #define UV3H_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL 2655 #define UV4H_LB_BAU_SB_ACTIVATION_CONTROL 0xc8020UL 2656 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL ( \ 2657 is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_CONTROL : \ 2658 is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_CONTROL : \ 2659 is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_CONTROL : \ 2660 /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_CONTROL) 2661 2662 #define UV1H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8 2663 #define UV2H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8 2664 #define UV3H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8 2665 #define UV4H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9c8 2666 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 ( \ 2667 is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_CONTROL_32 : \ 2668 is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_CONTROL_32 : \ 2669 is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_CONTROL_32 : \ 2670 /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_CONTROL_32) 2671 2672 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0 2673 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62 2674 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT 63 2675 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL 2676 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL 2677 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL 2678 2679 2680 union uvh_lb_bau_sb_activation_control_u { 2681 unsigned long v; 2682 struct uvh_lb_bau_sb_activation_control_s { 2683 unsigned long index:6; /* RW */ 2684 unsigned long rsvd_6_61:56; 2685 unsigned long push:1; /* WP */ 2686 unsigned long init:1; /* WP */ 2687 } s; 2688 }; 2689 2690 /* ========================================================================= */ 2691 /* UVH_LB_BAU_SB_ACTIVATION_STATUS_0 */ 2692 /* ========================================================================= */ 2693 #define UV1H_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL 2694 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL 2695 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL 2696 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_0 0xc8030UL 2697 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 ( \ 2698 is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_STATUS_0 : \ 2699 is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_0 : \ 2700 is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_0 : \ 2701 /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_0) 2702 2703 #define UV1H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0 2704 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0 2705 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0 2706 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9d0 2707 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 ( \ 2708 is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_STATUS_0_32 : \ 2709 is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_0_32 : \ 2710 is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_0_32 : \ 2711 /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_0_32) 2712 2713 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0 2714 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL 2715 2716 2717 union uvh_lb_bau_sb_activation_status_0_u { 2718 unsigned long v; 2719 struct uvh_lb_bau_sb_activation_status_0_s { 2720 unsigned long status:64; /* RW */ 2721 } s; 2722 }; 2723 2724 /* ========================================================================= */ 2725 /* UVH_LB_BAU_SB_ACTIVATION_STATUS_1 */ 2726 /* ========================================================================= */ 2727 #define UV1H_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL 2728 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL 2729 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL 2730 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_1 0xc8040UL 2731 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 ( \ 2732 is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_STATUS_1 : \ 2733 is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_1 : \ 2734 is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_1 : \ 2735 /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_1) 2736 2737 #define UV1H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8 2738 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8 2739 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8 2740 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9d8 2741 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 ( \ 2742 is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_STATUS_1_32 : \ 2743 is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_1_32 : \ 2744 is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_1_32 : \ 2745 /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_1_32) 2746 2747 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0 2748 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL 2749 2750 2751 union uvh_lb_bau_sb_activation_status_1_u { 2752 unsigned long v; 2753 struct uvh_lb_bau_sb_activation_status_1_s { 2754 unsigned long status:64; /* RW */ 2755 } s; 2756 }; 2757 2758 /* ========================================================================= */ 2759 /* UVH_LB_BAU_SB_DESCRIPTOR_BASE */ 2760 /* ========================================================================= */ 2761 #define UV1H_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL 2762 #define UV2H_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL 2763 #define UV3H_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL 2764 #define UV4H_LB_BAU_SB_DESCRIPTOR_BASE 0xc8010UL 2765 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE ( \ 2766 is_uv1_hub() ? UV1H_LB_BAU_SB_DESCRIPTOR_BASE : \ 2767 is_uv2_hub() ? UV2H_LB_BAU_SB_DESCRIPTOR_BASE : \ 2768 is_uv3_hub() ? UV3H_LB_BAU_SB_DESCRIPTOR_BASE : \ 2769 /*is_uv4_hub*/ UV4H_LB_BAU_SB_DESCRIPTOR_BASE) 2770 2771 #define UV1H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0 2772 #define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0 2773 #define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0 2774 #define UV4H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9c0 2775 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 ( \ 2776 is_uv1_hub() ? UV1H_LB_BAU_SB_DESCRIPTOR_BASE_32 : \ 2777 is_uv2_hub() ? UV2H_LB_BAU_SB_DESCRIPTOR_BASE_32 : \ 2778 is_uv3_hub() ? UV3H_LB_BAU_SB_DESCRIPTOR_BASE_32 : \ 2779 /*is_uv4_hub*/ UV4H_LB_BAU_SB_DESCRIPTOR_BASE_32) 2780 2781 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12 2782 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49 2783 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL 2784 2785 #define UV1H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL 2786 2787 2788 #define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL 2789 2790 #define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL 2791 2792 #define UV4H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x00003ffffffff000UL 2793 2794 2795 union uvh_lb_bau_sb_descriptor_base_u { 2796 unsigned long v; 2797 struct uvh_lb_bau_sb_descriptor_base_s { 2798 unsigned long rsvd_0_11:12; 2799 unsigned long rsvd_12_48:37; 2800 unsigned long node_id:14; /* RW */ 2801 unsigned long rsvd_63:1; 2802 } s; 2803 struct uv4h_lb_bau_sb_descriptor_base_s { 2804 unsigned long rsvd_0_11:12; 2805 unsigned long page_address:34; /* RW */ 2806 unsigned long rsvd_46_48:3; 2807 unsigned long node_id:14; /* RW */ 2808 unsigned long rsvd_63:1; 2809 } s4; 2810 }; 2811 2812 /* ========================================================================= */ 2813 /* UVH_NODE_ID */ 2814 /* ========================================================================= */ 2815 #define UVH_NODE_ID 0x0UL 2816 #define UV1H_NODE_ID 0x0UL 2817 #define UV2H_NODE_ID 0x0UL 2818 #define UV3H_NODE_ID 0x0UL 2819 #define UV4H_NODE_ID 0x0UL 2820 2821 #define UVH_NODE_ID_FORCE1_SHFT 0 2822 #define UVH_NODE_ID_MANUFACTURER_SHFT 1 2823 #define UVH_NODE_ID_PART_NUMBER_SHFT 12 2824 #define UVH_NODE_ID_REVISION_SHFT 28 2825 #define UVH_NODE_ID_NODE_ID_SHFT 32 2826 #define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL 2827 #define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL 2828 #define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL 2829 #define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL 2830 #define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 2831 2832 #define UV1H_NODE_ID_FORCE1_SHFT 0 2833 #define UV1H_NODE_ID_MANUFACTURER_SHFT 1 2834 #define UV1H_NODE_ID_PART_NUMBER_SHFT 12 2835 #define UV1H_NODE_ID_REVISION_SHFT 28 2836 #define UV1H_NODE_ID_NODE_ID_SHFT 32 2837 #define UV1H_NODE_ID_NODES_PER_BIT_SHFT 48 2838 #define UV1H_NODE_ID_NI_PORT_SHFT 56 2839 #define UV1H_NODE_ID_FORCE1_MASK 0x0000000000000001UL 2840 #define UV1H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL 2841 #define UV1H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL 2842 #define UV1H_NODE_ID_REVISION_MASK 0x00000000f0000000UL 2843 #define UV1H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 2844 #define UV1H_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL 2845 #define UV1H_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL 2846 2847 #define UVXH_NODE_ID_FORCE1_SHFT 0 2848 #define UVXH_NODE_ID_MANUFACTURER_SHFT 1 2849 #define UVXH_NODE_ID_PART_NUMBER_SHFT 12 2850 #define UVXH_NODE_ID_REVISION_SHFT 28 2851 #define UVXH_NODE_ID_NODE_ID_SHFT 32 2852 #define UVXH_NODE_ID_NODES_PER_BIT_SHFT 50 2853 #define UVXH_NODE_ID_NI_PORT_SHFT 57 2854 #define UVXH_NODE_ID_FORCE1_MASK 0x0000000000000001UL 2855 #define UVXH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL 2856 #define UVXH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL 2857 #define UVXH_NODE_ID_REVISION_MASK 0x00000000f0000000UL 2858 #define UVXH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 2859 #define UVXH_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL 2860 #define UVXH_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL 2861 2862 #define UV2H_NODE_ID_FORCE1_SHFT 0 2863 #define UV2H_NODE_ID_MANUFACTURER_SHFT 1 2864 #define UV2H_NODE_ID_PART_NUMBER_SHFT 12 2865 #define UV2H_NODE_ID_REVISION_SHFT 28 2866 #define UV2H_NODE_ID_NODE_ID_SHFT 32 2867 #define UV2H_NODE_ID_NODES_PER_BIT_SHFT 50 2868 #define UV2H_NODE_ID_NI_PORT_SHFT 57 2869 #define UV2H_NODE_ID_FORCE1_MASK 0x0000000000000001UL 2870 #define UV2H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL 2871 #define UV2H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL 2872 #define UV2H_NODE_ID_REVISION_MASK 0x00000000f0000000UL 2873 #define UV2H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 2874 #define UV2H_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL 2875 #define UV2H_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL 2876 2877 #define UV3H_NODE_ID_FORCE1_SHFT 0 2878 #define UV3H_NODE_ID_MANUFACTURER_SHFT 1 2879 #define UV3H_NODE_ID_PART_NUMBER_SHFT 12 2880 #define UV3H_NODE_ID_REVISION_SHFT 28 2881 #define UV3H_NODE_ID_NODE_ID_SHFT 32 2882 #define UV3H_NODE_ID_ROUTER_SELECT_SHFT 48 2883 #define UV3H_NODE_ID_RESERVED_2_SHFT 49 2884 #define UV3H_NODE_ID_NODES_PER_BIT_SHFT 50 2885 #define UV3H_NODE_ID_NI_PORT_SHFT 57 2886 #define UV3H_NODE_ID_FORCE1_MASK 0x0000000000000001UL 2887 #define UV3H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL 2888 #define UV3H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL 2889 #define UV3H_NODE_ID_REVISION_MASK 0x00000000f0000000UL 2890 #define UV3H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 2891 #define UV3H_NODE_ID_ROUTER_SELECT_MASK 0x0001000000000000UL 2892 #define UV3H_NODE_ID_RESERVED_2_MASK 0x0002000000000000UL 2893 #define UV3H_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL 2894 #define UV3H_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL 2895 2896 #define UV4H_NODE_ID_FORCE1_SHFT 0 2897 #define UV4H_NODE_ID_MANUFACTURER_SHFT 1 2898 #define UV4H_NODE_ID_PART_NUMBER_SHFT 12 2899 #define UV4H_NODE_ID_REVISION_SHFT 28 2900 #define UV4H_NODE_ID_NODE_ID_SHFT 32 2901 #define UV4H_NODE_ID_ROUTER_SELECT_SHFT 48 2902 #define UV4H_NODE_ID_RESERVED_2_SHFT 49 2903 #define UV4H_NODE_ID_NODES_PER_BIT_SHFT 50 2904 #define UV4H_NODE_ID_NI_PORT_SHFT 57 2905 #define UV4H_NODE_ID_FORCE1_MASK 0x0000000000000001UL 2906 #define UV4H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL 2907 #define UV4H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL 2908 #define UV4H_NODE_ID_REVISION_MASK 0x00000000f0000000UL 2909 #define UV4H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL 2910 #define UV4H_NODE_ID_ROUTER_SELECT_MASK 0x0001000000000000UL 2911 #define UV4H_NODE_ID_RESERVED_2_MASK 0x0002000000000000UL 2912 #define UV4H_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL 2913 #define UV4H_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL 2914 2915 2916 union uvh_node_id_u { 2917 unsigned long v; 2918 struct uvh_node_id_s { 2919 unsigned long force1:1; /* RO */ 2920 unsigned long manufacturer:11; /* RO */ 2921 unsigned long part_number:16; /* RO */ 2922 unsigned long revision:4; /* RO */ 2923 unsigned long node_id:15; /* RW */ 2924 unsigned long rsvd_47_63:17; 2925 } s; 2926 struct uv1h_node_id_s { 2927 unsigned long force1:1; /* RO */ 2928 unsigned long manufacturer:11; /* RO */ 2929 unsigned long part_number:16; /* RO */ 2930 unsigned long revision:4; /* RO */ 2931 unsigned long node_id:15; /* RW */ 2932 unsigned long rsvd_47:1; 2933 unsigned long nodes_per_bit:7; /* RW */ 2934 unsigned long rsvd_55:1; 2935 unsigned long ni_port:4; /* RO */ 2936 unsigned long rsvd_60_63:4; 2937 } s1; 2938 struct uvxh_node_id_s { 2939 unsigned long force1:1; /* RO */ 2940 unsigned long manufacturer:11; /* RO */ 2941 unsigned long part_number:16; /* RO */ 2942 unsigned long revision:4; /* RO */ 2943 unsigned long node_id:15; /* RW */ 2944 unsigned long rsvd_47_49:3; 2945 unsigned long nodes_per_bit:7; /* RO */ 2946 unsigned long ni_port:5; /* RO */ 2947 unsigned long rsvd_62_63:2; 2948 } sx; 2949 struct uv2h_node_id_s { 2950 unsigned long force1:1; /* RO */ 2951 unsigned long manufacturer:11; /* RO */ 2952 unsigned long part_number:16; /* RO */ 2953 unsigned long revision:4; /* RO */ 2954 unsigned long node_id:15; /* RW */ 2955 unsigned long rsvd_47_49:3; 2956 unsigned long nodes_per_bit:7; /* RO */ 2957 unsigned long ni_port:5; /* RO */ 2958 unsigned long rsvd_62_63:2; 2959 } s2; 2960 struct uv3h_node_id_s { 2961 unsigned long force1:1; /* RO */ 2962 unsigned long manufacturer:11; /* RO */ 2963 unsigned long part_number:16; /* RO */ 2964 unsigned long revision:4; /* RO */ 2965 unsigned long node_id:15; /* RW */ 2966 unsigned long rsvd_47:1; 2967 unsigned long router_select:1; /* RO */ 2968 unsigned long rsvd_49:1; 2969 unsigned long nodes_per_bit:7; /* RO */ 2970 unsigned long ni_port:5; /* RO */ 2971 unsigned long rsvd_62_63:2; 2972 } s3; 2973 struct uv4h_node_id_s { 2974 unsigned long force1:1; /* RO */ 2975 unsigned long manufacturer:11; /* RO */ 2976 unsigned long part_number:16; /* RO */ 2977 unsigned long revision:4; /* RO */ 2978 unsigned long node_id:15; /* RW */ 2979 unsigned long rsvd_47:1; 2980 unsigned long router_select:1; /* RO */ 2981 unsigned long rsvd_49:1; 2982 unsigned long nodes_per_bit:7; /* RO */ 2983 unsigned long ni_port:5; /* RO */ 2984 unsigned long rsvd_62_63:2; 2985 } s4; 2986 }; 2987 2988 /* ========================================================================= */ 2989 /* UVH_NODE_PRESENT_TABLE */ 2990 /* ========================================================================= */ 2991 #define UVH_NODE_PRESENT_TABLE 0x1400UL 2992 2993 #define UV1H_NODE_PRESENT_TABLE_DEPTH 16 2994 #define UV2H_NODE_PRESENT_TABLE_DEPTH 16 2995 #define UV3H_NODE_PRESENT_TABLE_DEPTH 16 2996 #define UV4H_NODE_PRESENT_TABLE_DEPTH 4 2997 #define UVH_NODE_PRESENT_TABLE_DEPTH ( \ 2998 is_uv1_hub() ? UV1H_NODE_PRESENT_TABLE_DEPTH : \ 2999 is_uv2_hub() ? UV2H_NODE_PRESENT_TABLE_DEPTH : \ 3000 is_uv3_hub() ? UV3H_NODE_PRESENT_TABLE_DEPTH : \ 3001 /*is_uv4_hub*/ UV4H_NODE_PRESENT_TABLE_DEPTH) 3002 3003 #define UVH_NODE_PRESENT_TABLE_NODES_SHFT 0 3004 #define UVH_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL 3005 3006 3007 union uvh_node_present_table_u { 3008 unsigned long v; 3009 struct uvh_node_present_table_s { 3010 unsigned long nodes:64; /* RW */ 3011 } s; 3012 }; 3013 3014 /* ========================================================================= */ 3015 /* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR */ 3016 /* ========================================================================= */ 3017 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL 3018 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL 3019 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL 3020 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x4800c8UL 3021 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR ( \ 3022 is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR : \ 3023 is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR : \ 3024 is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR : \ 3025 /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR) 3026 3027 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24 3028 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48 3029 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63 3030 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL 3031 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL 3032 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL 3033 3034 3035 union uvh_rh_gam_alias210_overlay_config_0_mmr_u { 3036 unsigned long v; 3037 struct uvh_rh_gam_alias210_overlay_config_0_mmr_s { 3038 unsigned long rsvd_0_23:24; 3039 unsigned long base:8; /* RW */ 3040 unsigned long rsvd_32_47:16; 3041 unsigned long m_alias:5; /* RW */ 3042 unsigned long rsvd_53_62:10; 3043 unsigned long enable:1; /* RW */ 3044 } s; 3045 }; 3046 3047 /* ========================================================================= */ 3048 /* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR */ 3049 /* ========================================================================= */ 3050 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL 3051 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL 3052 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL 3053 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x4800d8UL 3054 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR ( \ 3055 is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR : \ 3056 is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR : \ 3057 is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR : \ 3058 /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR) 3059 3060 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24 3061 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48 3062 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63 3063 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL 3064 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL 3065 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL 3066 3067 3068 union uvh_rh_gam_alias210_overlay_config_1_mmr_u { 3069 unsigned long v; 3070 struct uvh_rh_gam_alias210_overlay_config_1_mmr_s { 3071 unsigned long rsvd_0_23:24; 3072 unsigned long base:8; /* RW */ 3073 unsigned long rsvd_32_47:16; 3074 unsigned long m_alias:5; /* RW */ 3075 unsigned long rsvd_53_62:10; 3076 unsigned long enable:1; /* RW */ 3077 } s; 3078 }; 3079 3080 /* ========================================================================= */ 3081 /* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR */ 3082 /* ========================================================================= */ 3083 #define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL 3084 #define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL 3085 #define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL 3086 #define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x4800e8UL 3087 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR ( \ 3088 is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR : \ 3089 is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR : \ 3090 is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR : \ 3091 /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR) 3092 3093 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24 3094 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48 3095 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63 3096 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL 3097 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL 3098 #define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL 3099 3100 3101 union uvh_rh_gam_alias210_overlay_config_2_mmr_u { 3102 unsigned long v; 3103 struct uvh_rh_gam_alias210_overlay_config_2_mmr_s { 3104 unsigned long rsvd_0_23:24; 3105 unsigned long base:8; /* RW */ 3106 unsigned long rsvd_32_47:16; 3107 unsigned long m_alias:5; /* RW */ 3108 unsigned long rsvd_53_62:10; 3109 unsigned long enable:1; /* RW */ 3110 } s; 3111 }; 3112 3113 /* ========================================================================= */ 3114 /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */ 3115 /* ========================================================================= */ 3116 #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL 3117 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL 3118 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL 3119 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x4800d0UL 3120 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR ( \ 3121 is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR : \ 3122 is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR : \ 3123 is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR : \ 3124 /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR) 3125 3126 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 3127 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL 3128 3129 3130 union uvh_rh_gam_alias210_redirect_config_0_mmr_u { 3131 unsigned long v; 3132 struct uvh_rh_gam_alias210_redirect_config_0_mmr_s { 3133 unsigned long rsvd_0_23:24; 3134 unsigned long dest_base:22; /* RW */ 3135 unsigned long rsvd_46_63:18; 3136 } s; 3137 }; 3138 3139 /* ========================================================================= */ 3140 /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */ 3141 /* ========================================================================= */ 3142 #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL 3143 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL 3144 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL 3145 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x4800e0UL 3146 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR ( \ 3147 is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR : \ 3148 is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR : \ 3149 is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR : \ 3150 /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR) 3151 3152 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 3153 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL 3154 3155 3156 union uvh_rh_gam_alias210_redirect_config_1_mmr_u { 3157 unsigned long v; 3158 struct uvh_rh_gam_alias210_redirect_config_1_mmr_s { 3159 unsigned long rsvd_0_23:24; 3160 unsigned long dest_base:22; /* RW */ 3161 unsigned long rsvd_46_63:18; 3162 } s; 3163 }; 3164 3165 /* ========================================================================= */ 3166 /* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */ 3167 /* ========================================================================= */ 3168 #define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL 3169 #define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL 3170 #define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL 3171 #define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x4800f0UL 3172 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR ( \ 3173 is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR : \ 3174 is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR : \ 3175 is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR : \ 3176 /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR) 3177 3178 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 3179 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL 3180 3181 3182 union uvh_rh_gam_alias210_redirect_config_2_mmr_u { 3183 unsigned long v; 3184 struct uvh_rh_gam_alias210_redirect_config_2_mmr_s { 3185 unsigned long rsvd_0_23:24; 3186 unsigned long dest_base:22; /* RW */ 3187 unsigned long rsvd_46_63:18; 3188 } s; 3189 }; 3190 3191 /* ========================================================================= */ 3192 /* UVH_RH_GAM_CONFIG_MMR */ 3193 /* ========================================================================= */ 3194 #define UV1H_RH_GAM_CONFIG_MMR 0x1600000UL 3195 #define UV2H_RH_GAM_CONFIG_MMR 0x1600000UL 3196 #define UV3H_RH_GAM_CONFIG_MMR 0x1600000UL 3197 #define UV4H_RH_GAM_CONFIG_MMR 0x480000UL 3198 #define UVH_RH_GAM_CONFIG_MMR ( \ 3199 is_uv1_hub() ? UV1H_RH_GAM_CONFIG_MMR : \ 3200 is_uv2_hub() ? UV2H_RH_GAM_CONFIG_MMR : \ 3201 is_uv3_hub() ? UV3H_RH_GAM_CONFIG_MMR : \ 3202 /*is_uv4_hub*/ UV4H_RH_GAM_CONFIG_MMR) 3203 3204 #define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 3205 #define UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 3206 3207 #define UV1H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 3208 #define UV1H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 3209 #define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_SHFT 12 3210 #define UV1H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL 3211 #define UV1H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 3212 #define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK 0x0000000000001000UL 3213 3214 #define UVXH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 3215 #define UVXH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 3216 3217 #define UV2H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 3218 #define UV2H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 3219 #define UV2H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL 3220 #define UV2H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 3221 3222 #define UV3H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 3223 #define UV3H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 3224 #define UV3H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL 3225 #define UV3H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 3226 3227 #define UV4H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 3228 #define UV4H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 3229 3230 3231 union uvh_rh_gam_config_mmr_u { 3232 unsigned long v; 3233 struct uvh_rh_gam_config_mmr_s { 3234 unsigned long rsvd_0_5:6; 3235 unsigned long n_skt:4; /* RW */ 3236 unsigned long rsvd_10_63:54; 3237 } s; 3238 struct uv1h_rh_gam_config_mmr_s { 3239 unsigned long m_skt:6; /* RW */ 3240 unsigned long n_skt:4; /* RW */ 3241 unsigned long rsvd_10_11:2; 3242 unsigned long mmiol_cfg:1; /* RW */ 3243 unsigned long rsvd_13_63:51; 3244 } s1; 3245 struct uvxh_rh_gam_config_mmr_s { 3246 unsigned long rsvd_0_5:6; 3247 unsigned long n_skt:4; /* RW */ 3248 unsigned long rsvd_10_63:54; 3249 } sx; 3250 struct uv2h_rh_gam_config_mmr_s { 3251 unsigned long m_skt:6; /* RW */ 3252 unsigned long n_skt:4; /* RW */ 3253 unsigned long rsvd_10_63:54; 3254 } s2; 3255 struct uv3h_rh_gam_config_mmr_s { 3256 unsigned long m_skt:6; /* RW */ 3257 unsigned long n_skt:4; /* RW */ 3258 unsigned long rsvd_10_63:54; 3259 } s3; 3260 struct uv4h_rh_gam_config_mmr_s { 3261 unsigned long rsvd_0_5:6; 3262 unsigned long n_skt:4; /* RW */ 3263 unsigned long rsvd_10_63:54; 3264 } s4; 3265 }; 3266 3267 /* ========================================================================= */ 3268 /* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */ 3269 /* ========================================================================= */ 3270 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL 3271 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL 3272 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL 3273 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x480010UL 3274 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR ( \ 3275 is_uv1_hub() ? UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR : \ 3276 is_uv2_hub() ? UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR : \ 3277 is_uv3_hub() ? UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR : \ 3278 /*is_uv4_hub*/ UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR) 3279 3280 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 3281 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3282 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 3283 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3284 3285 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 3286 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48 3287 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 3288 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3289 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL 3290 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL 3291 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 3292 #define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3293 3294 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 3295 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3296 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 3297 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3298 3299 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 3300 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 3301 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3302 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL 3303 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 3304 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3305 3306 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 3307 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 3308 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_MODE_SHFT 62 3309 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3310 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL 3311 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 3312 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_MODE_MASK 0x4000000000000000UL 3313 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3314 3315 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 26 3316 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 3317 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3318 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 3319 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 3320 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3321 3322 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK ( \ 3323 is_uv1_hub() ? UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK : \ 3324 is_uv2_hub() ? UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK : \ 3325 is_uv3_hub() ? UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK : \ 3326 /*is_uv4_hub*/ UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK) 3327 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT ( \ 3328 is_uv1_hub() ? UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT : \ 3329 is_uv2_hub() ? UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT : \ 3330 is_uv3_hub() ? UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT : \ 3331 /*is_uv4_hub*/ UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT) 3332 3333 union uvh_rh_gam_gru_overlay_config_mmr_u { 3334 unsigned long v; 3335 struct uvh_rh_gam_gru_overlay_config_mmr_s { 3336 unsigned long rsvd_0_51:52; 3337 unsigned long n_gru:4; /* RW */ 3338 unsigned long rsvd_56_62:7; 3339 unsigned long enable:1; /* RW */ 3340 } s; 3341 struct uv1h_rh_gam_gru_overlay_config_mmr_s { 3342 unsigned long rsvd_0_27:28; 3343 unsigned long base:18; /* RW */ 3344 unsigned long rsvd_46_47:2; 3345 unsigned long gr4:1; /* RW */ 3346 unsigned long rsvd_49_51:3; 3347 unsigned long n_gru:4; /* RW */ 3348 unsigned long rsvd_56_62:7; 3349 unsigned long enable:1; /* RW */ 3350 } s1; 3351 struct uvxh_rh_gam_gru_overlay_config_mmr_s { 3352 unsigned long rsvd_0_45:46; 3353 unsigned long rsvd_46_51:6; 3354 unsigned long n_gru:4; /* RW */ 3355 unsigned long rsvd_56_62:7; 3356 unsigned long enable:1; /* RW */ 3357 } sx; 3358 struct uv2h_rh_gam_gru_overlay_config_mmr_s { 3359 unsigned long rsvd_0_27:28; 3360 unsigned long base:18; /* RW */ 3361 unsigned long rsvd_46_51:6; 3362 unsigned long n_gru:4; /* RW */ 3363 unsigned long rsvd_56_62:7; 3364 unsigned long enable:1; /* RW */ 3365 } s2; 3366 struct uv3h_rh_gam_gru_overlay_config_mmr_s { 3367 unsigned long rsvd_0_27:28; 3368 unsigned long base:18; /* RW */ 3369 unsigned long rsvd_46_51:6; 3370 unsigned long n_gru:4; /* RW */ 3371 unsigned long rsvd_56_61:6; 3372 unsigned long mode:1; /* RW */ 3373 unsigned long enable:1; /* RW */ 3374 } s3; 3375 struct uv4h_rh_gam_gru_overlay_config_mmr_s { 3376 unsigned long rsvd_0_24:25; 3377 unsigned long undef_25:1; /* Undefined */ 3378 unsigned long base:20; /* RW */ 3379 unsigned long rsvd_46_51:6; 3380 unsigned long n_gru:4; /* RW */ 3381 unsigned long rsvd_56_62:7; 3382 unsigned long enable:1; /* RW */ 3383 } s4; 3384 }; 3385 3386 /* ========================================================================= */ 3387 /* UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR */ 3388 /* ========================================================================= */ 3389 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL 3390 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL 3391 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR uv_undefined("UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR") 3392 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR uv_undefined("UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR") 3393 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR ( \ 3394 is_uv1_hub() ? UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR : \ 3395 is_uv2_hub() ? UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR : \ 3396 is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR : \ 3397 /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR) 3398 3399 3400 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30 3401 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46 3402 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52 3403 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3404 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003fffc0000000UL 3405 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL 3406 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL 3407 #define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3408 3409 3410 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 27 3411 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46 3412 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52 3413 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3414 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff8000000UL 3415 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL 3416 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL 3417 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3418 3419 3420 union uvh_rh_gam_mmioh_overlay_config_mmr_u { 3421 unsigned long v; 3422 struct uv1h_rh_gam_mmioh_overlay_config_mmr_s { 3423 unsigned long rsvd_0_29:30; 3424 unsigned long base:16; /* RW */ 3425 unsigned long m_io:6; /* RW */ 3426 unsigned long n_io:4; /* RW */ 3427 unsigned long rsvd_56_62:7; 3428 unsigned long enable:1; /* RW */ 3429 } s1; 3430 struct uv2h_rh_gam_mmioh_overlay_config_mmr_s { 3431 unsigned long rsvd_0_26:27; 3432 unsigned long base:19; /* RW */ 3433 unsigned long m_io:6; /* RW */ 3434 unsigned long n_io:4; /* RW */ 3435 unsigned long rsvd_56_62:7; 3436 unsigned long enable:1; /* RW */ 3437 } s2; 3438 }; 3439 3440 /* ========================================================================= */ 3441 /* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */ 3442 /* ========================================================================= */ 3443 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL 3444 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL 3445 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL 3446 #define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x480028UL 3447 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR ( \ 3448 is_uv1_hub() ? UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR : \ 3449 is_uv2_hub() ? UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR : \ 3450 is_uv3_hub() ? UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR : \ 3451 /*is_uv4_hub*/ UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR) 3452 3453 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 3454 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3455 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 3456 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3457 3458 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 3459 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46 3460 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3461 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 3462 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL 3463 #define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3464 3465 #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 3466 #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3467 #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 3468 #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3469 3470 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 3471 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3472 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 3473 #define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3474 3475 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 3476 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3477 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 3478 #define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3479 3480 #define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 3481 #define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3482 #define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 3483 #define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3484 3485 3486 union uvh_rh_gam_mmr_overlay_config_mmr_u { 3487 unsigned long v; 3488 struct uvh_rh_gam_mmr_overlay_config_mmr_s { 3489 unsigned long rsvd_0_25:26; 3490 unsigned long base:20; /* RW */ 3491 unsigned long rsvd_46_62:17; 3492 unsigned long enable:1; /* RW */ 3493 } s; 3494 struct uv1h_rh_gam_mmr_overlay_config_mmr_s { 3495 unsigned long rsvd_0_25:26; 3496 unsigned long base:20; /* RW */ 3497 unsigned long dual_hub:1; /* RW */ 3498 unsigned long rsvd_47_62:16; 3499 unsigned long enable:1; /* RW */ 3500 } s1; 3501 struct uvxh_rh_gam_mmr_overlay_config_mmr_s { 3502 unsigned long rsvd_0_25:26; 3503 unsigned long base:20; /* RW */ 3504 unsigned long rsvd_46_62:17; 3505 unsigned long enable:1; /* RW */ 3506 } sx; 3507 struct uv2h_rh_gam_mmr_overlay_config_mmr_s { 3508 unsigned long rsvd_0_25:26; 3509 unsigned long base:20; /* RW */ 3510 unsigned long rsvd_46_62:17; 3511 unsigned long enable:1; /* RW */ 3512 } s2; 3513 struct uv3h_rh_gam_mmr_overlay_config_mmr_s { 3514 unsigned long rsvd_0_25:26; 3515 unsigned long base:20; /* RW */ 3516 unsigned long rsvd_46_62:17; 3517 unsigned long enable:1; /* RW */ 3518 } s3; 3519 struct uv4h_rh_gam_mmr_overlay_config_mmr_s { 3520 unsigned long rsvd_0_25:26; 3521 unsigned long base:20; /* RW */ 3522 unsigned long rsvd_46_62:17; 3523 unsigned long enable:1; /* RW */ 3524 } s4; 3525 }; 3526 3527 /* ========================================================================= */ 3528 /* UVH_RTC */ 3529 /* ========================================================================= */ 3530 #define UV1H_RTC 0x340000UL 3531 #define UV2H_RTC 0x340000UL 3532 #define UV3H_RTC 0x340000UL 3533 #define UV4H_RTC 0xe0000UL 3534 #define UVH_RTC ( \ 3535 is_uv1_hub() ? UV1H_RTC : \ 3536 is_uv2_hub() ? UV2H_RTC : \ 3537 is_uv3_hub() ? UV3H_RTC : \ 3538 /*is_uv4_hub*/ UV4H_RTC) 3539 3540 #define UVH_RTC_REAL_TIME_CLOCK_SHFT 0 3541 #define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL 3542 3543 3544 union uvh_rtc_u { 3545 unsigned long v; 3546 struct uvh_rtc_s { 3547 unsigned long real_time_clock:56; /* RW */ 3548 unsigned long rsvd_56_63:8; 3549 } s; 3550 }; 3551 3552 /* ========================================================================= */ 3553 /* UVH_RTC1_INT_CONFIG */ 3554 /* ========================================================================= */ 3555 #define UVH_RTC1_INT_CONFIG 0x615c0UL 3556 3557 #define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0 3558 #define UVH_RTC1_INT_CONFIG_DM_SHFT 8 3559 #define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT 11 3560 #define UVH_RTC1_INT_CONFIG_STATUS_SHFT 12 3561 #define UVH_RTC1_INT_CONFIG_P_SHFT 13 3562 #define UVH_RTC1_INT_CONFIG_T_SHFT 15 3563 #define UVH_RTC1_INT_CONFIG_M_SHFT 16 3564 #define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT 32 3565 #define UVH_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL 3566 #define UVH_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL 3567 #define UVH_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL 3568 #define UVH_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL 3569 #define UVH_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL 3570 #define UVH_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL 3571 #define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL 3572 #define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 3573 3574 3575 union uvh_rtc1_int_config_u { 3576 unsigned long v; 3577 struct uvh_rtc1_int_config_s { 3578 unsigned long vector_:8; /* RW */ 3579 unsigned long dm:3; /* RW */ 3580 unsigned long destmode:1; /* RW */ 3581 unsigned long status:1; /* RO */ 3582 unsigned long p:1; /* RO */ 3583 unsigned long rsvd_14:1; 3584 unsigned long t:1; /* RO */ 3585 unsigned long m:1; /* RW */ 3586 unsigned long rsvd_17_31:15; 3587 unsigned long apic_id:32; /* RW */ 3588 } s; 3589 }; 3590 3591 /* ========================================================================= */ 3592 /* UVH_SCRATCH5 */ 3593 /* ========================================================================= */ 3594 #define UV1H_SCRATCH5 0x2d0200UL 3595 #define UV2H_SCRATCH5 0x2d0200UL 3596 #define UV3H_SCRATCH5 0x2d0200UL 3597 #define UV4H_SCRATCH5 0xb0200UL 3598 #define UVH_SCRATCH5 ( \ 3599 is_uv1_hub() ? UV1H_SCRATCH5 : \ 3600 is_uv2_hub() ? UV2H_SCRATCH5 : \ 3601 is_uv3_hub() ? UV3H_SCRATCH5 : \ 3602 /*is_uv4_hub*/ UV4H_SCRATCH5) 3603 3604 #define UV1H_SCRATCH5_32 0x778 3605 #define UV2H_SCRATCH5_32 0x778 3606 #define UV3H_SCRATCH5_32 0x778 3607 #define UV4H_SCRATCH5_32 0x798 3608 #define UVH_SCRATCH5_32 ( \ 3609 is_uv1_hub() ? UV1H_SCRATCH5_32 : \ 3610 is_uv2_hub() ? UV2H_SCRATCH5_32 : \ 3611 is_uv3_hub() ? UV3H_SCRATCH5_32 : \ 3612 /*is_uv4_hub*/ UV4H_SCRATCH5_32) 3613 3614 #define UVH_SCRATCH5_SCRATCH5_SHFT 0 3615 #define UVH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL 3616 3617 3618 union uvh_scratch5_u { 3619 unsigned long v; 3620 struct uvh_scratch5_s { 3621 unsigned long scratch5:64; /* RW, W1CS */ 3622 } s; 3623 }; 3624 3625 /* ========================================================================= */ 3626 /* UVH_SCRATCH5_ALIAS */ 3627 /* ========================================================================= */ 3628 #define UV1H_SCRATCH5_ALIAS 0x2d0208UL 3629 #define UV2H_SCRATCH5_ALIAS 0x2d0208UL 3630 #define UV3H_SCRATCH5_ALIAS 0x2d0208UL 3631 #define UV4H_SCRATCH5_ALIAS 0xb0208UL 3632 #define UVH_SCRATCH5_ALIAS ( \ 3633 is_uv1_hub() ? UV1H_SCRATCH5_ALIAS : \ 3634 is_uv2_hub() ? UV2H_SCRATCH5_ALIAS : \ 3635 is_uv3_hub() ? UV3H_SCRATCH5_ALIAS : \ 3636 /*is_uv4_hub*/ UV4H_SCRATCH5_ALIAS) 3637 3638 #define UV1H_SCRATCH5_ALIAS_32 0x780 3639 #define UV2H_SCRATCH5_ALIAS_32 0x780 3640 #define UV3H_SCRATCH5_ALIAS_32 0x780 3641 #define UV4H_SCRATCH5_ALIAS_32 0x7a0 3642 #define UVH_SCRATCH5_ALIAS_32 ( \ 3643 is_uv1_hub() ? UV1H_SCRATCH5_ALIAS_32 : \ 3644 is_uv2_hub() ? UV2H_SCRATCH5_ALIAS_32 : \ 3645 is_uv3_hub() ? UV3H_SCRATCH5_ALIAS_32 : \ 3646 /*is_uv4_hub*/ UV4H_SCRATCH5_ALIAS_32) 3647 3648 3649 /* ========================================================================= */ 3650 /* UVH_SCRATCH5_ALIAS_2 */ 3651 /* ========================================================================= */ 3652 #define UV1H_SCRATCH5_ALIAS_2 0x2d0210UL 3653 #define UV2H_SCRATCH5_ALIAS_2 0x2d0210UL 3654 #define UV3H_SCRATCH5_ALIAS_2 0x2d0210UL 3655 #define UV4H_SCRATCH5_ALIAS_2 0xb0210UL 3656 #define UVH_SCRATCH5_ALIAS_2 ( \ 3657 is_uv1_hub() ? UV1H_SCRATCH5_ALIAS_2 : \ 3658 is_uv2_hub() ? UV2H_SCRATCH5_ALIAS_2 : \ 3659 is_uv3_hub() ? UV3H_SCRATCH5_ALIAS_2 : \ 3660 /*is_uv4_hub*/ UV4H_SCRATCH5_ALIAS_2) 3661 #define UVH_SCRATCH5_ALIAS_2_32 0x788 3662 3663 3664 /* ========================================================================= */ 3665 /* UVXH_EVENT_OCCURRED2 */ 3666 /* ========================================================================= */ 3667 #define UVXH_EVENT_OCCURRED2 0x70100UL 3668 3669 #define UV2H_EVENT_OCCURRED2_32 0xb68 3670 #define UV3H_EVENT_OCCURRED2_32 0xb68 3671 #define UV4H_EVENT_OCCURRED2_32 0x608 3672 #define UVH_EVENT_OCCURRED2_32 ( \ 3673 is_uv2_hub() ? UV2H_EVENT_OCCURRED2_32 : \ 3674 is_uv3_hub() ? UV3H_EVENT_OCCURRED2_32 : \ 3675 /*is_uv4_hub*/ UV4H_EVENT_OCCURRED2_32) 3676 3677 3678 #define UV2H_EVENT_OCCURRED2_RTC_0_SHFT 0 3679 #define UV2H_EVENT_OCCURRED2_RTC_1_SHFT 1 3680 #define UV2H_EVENT_OCCURRED2_RTC_2_SHFT 2 3681 #define UV2H_EVENT_OCCURRED2_RTC_3_SHFT 3 3682 #define UV2H_EVENT_OCCURRED2_RTC_4_SHFT 4 3683 #define UV2H_EVENT_OCCURRED2_RTC_5_SHFT 5 3684 #define UV2H_EVENT_OCCURRED2_RTC_6_SHFT 6 3685 #define UV2H_EVENT_OCCURRED2_RTC_7_SHFT 7 3686 #define UV2H_EVENT_OCCURRED2_RTC_8_SHFT 8 3687 #define UV2H_EVENT_OCCURRED2_RTC_9_SHFT 9 3688 #define UV2H_EVENT_OCCURRED2_RTC_10_SHFT 10 3689 #define UV2H_EVENT_OCCURRED2_RTC_11_SHFT 11 3690 #define UV2H_EVENT_OCCURRED2_RTC_12_SHFT 12 3691 #define UV2H_EVENT_OCCURRED2_RTC_13_SHFT 13 3692 #define UV2H_EVENT_OCCURRED2_RTC_14_SHFT 14 3693 #define UV2H_EVENT_OCCURRED2_RTC_15_SHFT 15 3694 #define UV2H_EVENT_OCCURRED2_RTC_16_SHFT 16 3695 #define UV2H_EVENT_OCCURRED2_RTC_17_SHFT 17 3696 #define UV2H_EVENT_OCCURRED2_RTC_18_SHFT 18 3697 #define UV2H_EVENT_OCCURRED2_RTC_19_SHFT 19 3698 #define UV2H_EVENT_OCCURRED2_RTC_20_SHFT 20 3699 #define UV2H_EVENT_OCCURRED2_RTC_21_SHFT 21 3700 #define UV2H_EVENT_OCCURRED2_RTC_22_SHFT 22 3701 #define UV2H_EVENT_OCCURRED2_RTC_23_SHFT 23 3702 #define UV2H_EVENT_OCCURRED2_RTC_24_SHFT 24 3703 #define UV2H_EVENT_OCCURRED2_RTC_25_SHFT 25 3704 #define UV2H_EVENT_OCCURRED2_RTC_26_SHFT 26 3705 #define UV2H_EVENT_OCCURRED2_RTC_27_SHFT 27 3706 #define UV2H_EVENT_OCCURRED2_RTC_28_SHFT 28 3707 #define UV2H_EVENT_OCCURRED2_RTC_29_SHFT 29 3708 #define UV2H_EVENT_OCCURRED2_RTC_30_SHFT 30 3709 #define UV2H_EVENT_OCCURRED2_RTC_31_SHFT 31 3710 #define UV2H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL 3711 #define UV2H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL 3712 #define UV2H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL 3713 #define UV2H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL 3714 #define UV2H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL 3715 #define UV2H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL 3716 #define UV2H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL 3717 #define UV2H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL 3718 #define UV2H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL 3719 #define UV2H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL 3720 #define UV2H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL 3721 #define UV2H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL 3722 #define UV2H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL 3723 #define UV2H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL 3724 #define UV2H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL 3725 #define UV2H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL 3726 #define UV2H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL 3727 #define UV2H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL 3728 #define UV2H_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL 3729 #define UV2H_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL 3730 #define UV2H_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL 3731 #define UV2H_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL 3732 #define UV2H_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL 3733 #define UV2H_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL 3734 #define UV2H_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL 3735 #define UV2H_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL 3736 #define UV2H_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL 3737 #define UV2H_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL 3738 #define UV2H_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL 3739 #define UV2H_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL 3740 #define UV2H_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL 3741 #define UV2H_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL 3742 3743 #define UV3H_EVENT_OCCURRED2_RTC_0_SHFT 0 3744 #define UV3H_EVENT_OCCURRED2_RTC_1_SHFT 1 3745 #define UV3H_EVENT_OCCURRED2_RTC_2_SHFT 2 3746 #define UV3H_EVENT_OCCURRED2_RTC_3_SHFT 3 3747 #define UV3H_EVENT_OCCURRED2_RTC_4_SHFT 4 3748 #define UV3H_EVENT_OCCURRED2_RTC_5_SHFT 5 3749 #define UV3H_EVENT_OCCURRED2_RTC_6_SHFT 6 3750 #define UV3H_EVENT_OCCURRED2_RTC_7_SHFT 7 3751 #define UV3H_EVENT_OCCURRED2_RTC_8_SHFT 8 3752 #define UV3H_EVENT_OCCURRED2_RTC_9_SHFT 9 3753 #define UV3H_EVENT_OCCURRED2_RTC_10_SHFT 10 3754 #define UV3H_EVENT_OCCURRED2_RTC_11_SHFT 11 3755 #define UV3H_EVENT_OCCURRED2_RTC_12_SHFT 12 3756 #define UV3H_EVENT_OCCURRED2_RTC_13_SHFT 13 3757 #define UV3H_EVENT_OCCURRED2_RTC_14_SHFT 14 3758 #define UV3H_EVENT_OCCURRED2_RTC_15_SHFT 15 3759 #define UV3H_EVENT_OCCURRED2_RTC_16_SHFT 16 3760 #define UV3H_EVENT_OCCURRED2_RTC_17_SHFT 17 3761 #define UV3H_EVENT_OCCURRED2_RTC_18_SHFT 18 3762 #define UV3H_EVENT_OCCURRED2_RTC_19_SHFT 19 3763 #define UV3H_EVENT_OCCURRED2_RTC_20_SHFT 20 3764 #define UV3H_EVENT_OCCURRED2_RTC_21_SHFT 21 3765 #define UV3H_EVENT_OCCURRED2_RTC_22_SHFT 22 3766 #define UV3H_EVENT_OCCURRED2_RTC_23_SHFT 23 3767 #define UV3H_EVENT_OCCURRED2_RTC_24_SHFT 24 3768 #define UV3H_EVENT_OCCURRED2_RTC_25_SHFT 25 3769 #define UV3H_EVENT_OCCURRED2_RTC_26_SHFT 26 3770 #define UV3H_EVENT_OCCURRED2_RTC_27_SHFT 27 3771 #define UV3H_EVENT_OCCURRED2_RTC_28_SHFT 28 3772 #define UV3H_EVENT_OCCURRED2_RTC_29_SHFT 29 3773 #define UV3H_EVENT_OCCURRED2_RTC_30_SHFT 30 3774 #define UV3H_EVENT_OCCURRED2_RTC_31_SHFT 31 3775 #define UV3H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL 3776 #define UV3H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL 3777 #define UV3H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL 3778 #define UV3H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL 3779 #define UV3H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL 3780 #define UV3H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL 3781 #define UV3H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL 3782 #define UV3H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL 3783 #define UV3H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL 3784 #define UV3H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL 3785 #define UV3H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL 3786 #define UV3H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL 3787 #define UV3H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL 3788 #define UV3H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL 3789 #define UV3H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL 3790 #define UV3H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL 3791 #define UV3H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL 3792 #define UV3H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL 3793 #define UV3H_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL 3794 #define UV3H_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL 3795 #define UV3H_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL 3796 #define UV3H_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL 3797 #define UV3H_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL 3798 #define UV3H_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL 3799 #define UV3H_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL 3800 #define UV3H_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL 3801 #define UV3H_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL 3802 #define UV3H_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL 3803 #define UV3H_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL 3804 #define UV3H_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL 3805 #define UV3H_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL 3806 #define UV3H_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL 3807 3808 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT0_SHFT 0 3809 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT1_SHFT 1 3810 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT2_SHFT 2 3811 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT3_SHFT 3 3812 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT4_SHFT 4 3813 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT5_SHFT 5 3814 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT6_SHFT 6 3815 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT7_SHFT 7 3816 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT8_SHFT 8 3817 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT9_SHFT 9 3818 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT10_SHFT 10 3819 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT11_SHFT 11 3820 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT12_SHFT 12 3821 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT13_SHFT 13 3822 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT14_SHFT 14 3823 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT15_SHFT 15 3824 #define UV4H_EVENT_OCCURRED2_RTC_INTERVAL_INT_SHFT 16 3825 #define UV4H_EVENT_OCCURRED2_BAU_DASHBOARD_INT_SHFT 17 3826 #define UV4H_EVENT_OCCURRED2_RTC_0_SHFT 18 3827 #define UV4H_EVENT_OCCURRED2_RTC_1_SHFT 19 3828 #define UV4H_EVENT_OCCURRED2_RTC_2_SHFT 20 3829 #define UV4H_EVENT_OCCURRED2_RTC_3_SHFT 21 3830 #define UV4H_EVENT_OCCURRED2_RTC_4_SHFT 22 3831 #define UV4H_EVENT_OCCURRED2_RTC_5_SHFT 23 3832 #define UV4H_EVENT_OCCURRED2_RTC_6_SHFT 24 3833 #define UV4H_EVENT_OCCURRED2_RTC_7_SHFT 25 3834 #define UV4H_EVENT_OCCURRED2_RTC_8_SHFT 26 3835 #define UV4H_EVENT_OCCURRED2_RTC_9_SHFT 27 3836 #define UV4H_EVENT_OCCURRED2_RTC_10_SHFT 28 3837 #define UV4H_EVENT_OCCURRED2_RTC_11_SHFT 29 3838 #define UV4H_EVENT_OCCURRED2_RTC_12_SHFT 30 3839 #define UV4H_EVENT_OCCURRED2_RTC_13_SHFT 31 3840 #define UV4H_EVENT_OCCURRED2_RTC_14_SHFT 32 3841 #define UV4H_EVENT_OCCURRED2_RTC_15_SHFT 33 3842 #define UV4H_EVENT_OCCURRED2_RTC_16_SHFT 34 3843 #define UV4H_EVENT_OCCURRED2_RTC_17_SHFT 35 3844 #define UV4H_EVENT_OCCURRED2_RTC_18_SHFT 36 3845 #define UV4H_EVENT_OCCURRED2_RTC_19_SHFT 37 3846 #define UV4H_EVENT_OCCURRED2_RTC_20_SHFT 38 3847 #define UV4H_EVENT_OCCURRED2_RTC_21_SHFT 39 3848 #define UV4H_EVENT_OCCURRED2_RTC_22_SHFT 40 3849 #define UV4H_EVENT_OCCURRED2_RTC_23_SHFT 41 3850 #define UV4H_EVENT_OCCURRED2_RTC_24_SHFT 42 3851 #define UV4H_EVENT_OCCURRED2_RTC_25_SHFT 43 3852 #define UV4H_EVENT_OCCURRED2_RTC_26_SHFT 44 3853 #define UV4H_EVENT_OCCURRED2_RTC_27_SHFT 45 3854 #define UV4H_EVENT_OCCURRED2_RTC_28_SHFT 46 3855 #define UV4H_EVENT_OCCURRED2_RTC_29_SHFT 47 3856 #define UV4H_EVENT_OCCURRED2_RTC_30_SHFT 48 3857 #define UV4H_EVENT_OCCURRED2_RTC_31_SHFT 49 3858 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT0_MASK 0x0000000000000001UL 3859 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT1_MASK 0x0000000000000002UL 3860 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT2_MASK 0x0000000000000004UL 3861 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT3_MASK 0x0000000000000008UL 3862 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT4_MASK 0x0000000000000010UL 3863 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT5_MASK 0x0000000000000020UL 3864 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT6_MASK 0x0000000000000040UL 3865 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT7_MASK 0x0000000000000080UL 3866 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT8_MASK 0x0000000000000100UL 3867 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT9_MASK 0x0000000000000200UL 3868 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT10_MASK 0x0000000000000400UL 3869 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT11_MASK 0x0000000000000800UL 3870 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT12_MASK 0x0000000000001000UL 3871 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT13_MASK 0x0000000000002000UL 3872 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT14_MASK 0x0000000000004000UL 3873 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT15_MASK 0x0000000000008000UL 3874 #define UV4H_EVENT_OCCURRED2_RTC_INTERVAL_INT_MASK 0x0000000000010000UL 3875 #define UV4H_EVENT_OCCURRED2_BAU_DASHBOARD_INT_MASK 0x0000000000020000UL 3876 #define UV4H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000040000UL 3877 #define UV4H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000080000UL 3878 #define UV4H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000100000UL 3879 #define UV4H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000200000UL 3880 #define UV4H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000400000UL 3881 #define UV4H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000800000UL 3882 #define UV4H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000001000000UL 3883 #define UV4H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000002000000UL 3884 #define UV4H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000004000000UL 3885 #define UV4H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000008000000UL 3886 #define UV4H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000010000000UL 3887 #define UV4H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000020000000UL 3888 #define UV4H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000040000000UL 3889 #define UV4H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000080000000UL 3890 #define UV4H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000100000000UL 3891 #define UV4H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000200000000UL 3892 #define UV4H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000400000000UL 3893 #define UV4H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000800000000UL 3894 #define UV4H_EVENT_OCCURRED2_RTC_18_MASK 0x0000001000000000UL 3895 #define UV4H_EVENT_OCCURRED2_RTC_19_MASK 0x0000002000000000UL 3896 #define UV4H_EVENT_OCCURRED2_RTC_20_MASK 0x0000004000000000UL 3897 #define UV4H_EVENT_OCCURRED2_RTC_21_MASK 0x0000008000000000UL 3898 #define UV4H_EVENT_OCCURRED2_RTC_22_MASK 0x0000010000000000UL 3899 #define UV4H_EVENT_OCCURRED2_RTC_23_MASK 0x0000020000000000UL 3900 #define UV4H_EVENT_OCCURRED2_RTC_24_MASK 0x0000040000000000UL 3901 #define UV4H_EVENT_OCCURRED2_RTC_25_MASK 0x0000080000000000UL 3902 #define UV4H_EVENT_OCCURRED2_RTC_26_MASK 0x0000100000000000UL 3903 #define UV4H_EVENT_OCCURRED2_RTC_27_MASK 0x0000200000000000UL 3904 #define UV4H_EVENT_OCCURRED2_RTC_28_MASK 0x0000400000000000UL 3905 #define UV4H_EVENT_OCCURRED2_RTC_29_MASK 0x0000800000000000UL 3906 #define UV4H_EVENT_OCCURRED2_RTC_30_MASK 0x0001000000000000UL 3907 #define UV4H_EVENT_OCCURRED2_RTC_31_MASK 0x0002000000000000UL 3908 3909 #define UVXH_EVENT_OCCURRED2_RTC_1_MASK ( \ 3910 is_uv2_hub() ? UV2H_EVENT_OCCURRED2_RTC_1_MASK : \ 3911 is_uv3_hub() ? UV3H_EVENT_OCCURRED2_RTC_1_MASK : \ 3912 /*is_uv4_hub*/ UV4H_EVENT_OCCURRED2_RTC_1_MASK) 3913 3914 union uvh_event_occurred2_u { 3915 unsigned long v; 3916 struct uv2h_event_occurred2_s { 3917 unsigned long rtc_0:1; /* RW */ 3918 unsigned long rtc_1:1; /* RW */ 3919 unsigned long rtc_2:1; /* RW */ 3920 unsigned long rtc_3:1; /* RW */ 3921 unsigned long rtc_4:1; /* RW */ 3922 unsigned long rtc_5:1; /* RW */ 3923 unsigned long rtc_6:1; /* RW */ 3924 unsigned long rtc_7:1; /* RW */ 3925 unsigned long rtc_8:1; /* RW */ 3926 unsigned long rtc_9:1; /* RW */ 3927 unsigned long rtc_10:1; /* RW */ 3928 unsigned long rtc_11:1; /* RW */ 3929 unsigned long rtc_12:1; /* RW */ 3930 unsigned long rtc_13:1; /* RW */ 3931 unsigned long rtc_14:1; /* RW */ 3932 unsigned long rtc_15:1; /* RW */ 3933 unsigned long rtc_16:1; /* RW */ 3934 unsigned long rtc_17:1; /* RW */ 3935 unsigned long rtc_18:1; /* RW */ 3936 unsigned long rtc_19:1; /* RW */ 3937 unsigned long rtc_20:1; /* RW */ 3938 unsigned long rtc_21:1; /* RW */ 3939 unsigned long rtc_22:1; /* RW */ 3940 unsigned long rtc_23:1; /* RW */ 3941 unsigned long rtc_24:1; /* RW */ 3942 unsigned long rtc_25:1; /* RW */ 3943 unsigned long rtc_26:1; /* RW */ 3944 unsigned long rtc_27:1; /* RW */ 3945 unsigned long rtc_28:1; /* RW */ 3946 unsigned long rtc_29:1; /* RW */ 3947 unsigned long rtc_30:1; /* RW */ 3948 unsigned long rtc_31:1; /* RW */ 3949 unsigned long rsvd_32_63:32; 3950 } s2; 3951 struct uv3h_event_occurred2_s { 3952 unsigned long rtc_0:1; /* RW */ 3953 unsigned long rtc_1:1; /* RW */ 3954 unsigned long rtc_2:1; /* RW */ 3955 unsigned long rtc_3:1; /* RW */ 3956 unsigned long rtc_4:1; /* RW */ 3957 unsigned long rtc_5:1; /* RW */ 3958 unsigned long rtc_6:1; /* RW */ 3959 unsigned long rtc_7:1; /* RW */ 3960 unsigned long rtc_8:1; /* RW */ 3961 unsigned long rtc_9:1; /* RW */ 3962 unsigned long rtc_10:1; /* RW */ 3963 unsigned long rtc_11:1; /* RW */ 3964 unsigned long rtc_12:1; /* RW */ 3965 unsigned long rtc_13:1; /* RW */ 3966 unsigned long rtc_14:1; /* RW */ 3967 unsigned long rtc_15:1; /* RW */ 3968 unsigned long rtc_16:1; /* RW */ 3969 unsigned long rtc_17:1; /* RW */ 3970 unsigned long rtc_18:1; /* RW */ 3971 unsigned long rtc_19:1; /* RW */ 3972 unsigned long rtc_20:1; /* RW */ 3973 unsigned long rtc_21:1; /* RW */ 3974 unsigned long rtc_22:1; /* RW */ 3975 unsigned long rtc_23:1; /* RW */ 3976 unsigned long rtc_24:1; /* RW */ 3977 unsigned long rtc_25:1; /* RW */ 3978 unsigned long rtc_26:1; /* RW */ 3979 unsigned long rtc_27:1; /* RW */ 3980 unsigned long rtc_28:1; /* RW */ 3981 unsigned long rtc_29:1; /* RW */ 3982 unsigned long rtc_30:1; /* RW */ 3983 unsigned long rtc_31:1; /* RW */ 3984 unsigned long rsvd_32_63:32; 3985 } s3; 3986 struct uv4h_event_occurred2_s { 3987 unsigned long message_accelerator_int0:1; /* RW */ 3988 unsigned long message_accelerator_int1:1; /* RW */ 3989 unsigned long message_accelerator_int2:1; /* RW */ 3990 unsigned long message_accelerator_int3:1; /* RW */ 3991 unsigned long message_accelerator_int4:1; /* RW */ 3992 unsigned long message_accelerator_int5:1; /* RW */ 3993 unsigned long message_accelerator_int6:1; /* RW */ 3994 unsigned long message_accelerator_int7:1; /* RW */ 3995 unsigned long message_accelerator_int8:1; /* RW */ 3996 unsigned long message_accelerator_int9:1; /* RW */ 3997 unsigned long message_accelerator_int10:1; /* RW */ 3998 unsigned long message_accelerator_int11:1; /* RW */ 3999 unsigned long message_accelerator_int12:1; /* RW */ 4000 unsigned long message_accelerator_int13:1; /* RW */ 4001 unsigned long message_accelerator_int14:1; /* RW */ 4002 unsigned long message_accelerator_int15:1; /* RW */ 4003 unsigned long rtc_interval_int:1; /* RW */ 4004 unsigned long bau_dashboard_int:1; /* RW */ 4005 unsigned long rtc_0:1; /* RW */ 4006 unsigned long rtc_1:1; /* RW */ 4007 unsigned long rtc_2:1; /* RW */ 4008 unsigned long rtc_3:1; /* RW */ 4009 unsigned long rtc_4:1; /* RW */ 4010 unsigned long rtc_5:1; /* RW */ 4011 unsigned long rtc_6:1; /* RW */ 4012 unsigned long rtc_7:1; /* RW */ 4013 unsigned long rtc_8:1; /* RW */ 4014 unsigned long rtc_9:1; /* RW */ 4015 unsigned long rtc_10:1; /* RW */ 4016 unsigned long rtc_11:1; /* RW */ 4017 unsigned long rtc_12:1; /* RW */ 4018 unsigned long rtc_13:1; /* RW */ 4019 unsigned long rtc_14:1; /* RW */ 4020 unsigned long rtc_15:1; /* RW */ 4021 unsigned long rtc_16:1; /* RW */ 4022 unsigned long rtc_17:1; /* RW */ 4023 unsigned long rtc_18:1; /* RW */ 4024 unsigned long rtc_19:1; /* RW */ 4025 unsigned long rtc_20:1; /* RW */ 4026 unsigned long rtc_21:1; /* RW */ 4027 unsigned long rtc_22:1; /* RW */ 4028 unsigned long rtc_23:1; /* RW */ 4029 unsigned long rtc_24:1; /* RW */ 4030 unsigned long rtc_25:1; /* RW */ 4031 unsigned long rtc_26:1; /* RW */ 4032 unsigned long rtc_27:1; /* RW */ 4033 unsigned long rtc_28:1; /* RW */ 4034 unsigned long rtc_29:1; /* RW */ 4035 unsigned long rtc_30:1; /* RW */ 4036 unsigned long rtc_31:1; /* RW */ 4037 unsigned long rsvd_50_63:14; 4038 } s4; 4039 }; 4040 4041 /* ========================================================================= */ 4042 /* UVXH_EVENT_OCCURRED2_ALIAS */ 4043 /* ========================================================================= */ 4044 #define UVXH_EVENT_OCCURRED2_ALIAS 0x70108UL 4045 4046 #define UV2H_EVENT_OCCURRED2_ALIAS_32 0xb70 4047 #define UV3H_EVENT_OCCURRED2_ALIAS_32 0xb70 4048 #define UV4H_EVENT_OCCURRED2_ALIAS_32 0x610 4049 #define UVH_EVENT_OCCURRED2_ALIAS_32 ( \ 4050 is_uv2_hub() ? UV2H_EVENT_OCCURRED2_ALIAS_32 : \ 4051 is_uv3_hub() ? UV3H_EVENT_OCCURRED2_ALIAS_32 : \ 4052 /*is_uv4_hub*/ UV4H_EVENT_OCCURRED2_ALIAS_32) 4053 4054 4055 /* ========================================================================= */ 4056 /* UVXH_LB_BAU_SB_ACTIVATION_STATUS_2 */ 4057 /* ========================================================================= */ 4058 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL 4059 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL 4060 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2 0xc8130UL 4061 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_2 ( \ 4062 is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 : \ 4063 is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_2 : \ 4064 /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_2) 4065 4066 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0 4067 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0 4068 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0xa10 4069 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_2_32 ( \ 4070 is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 : \ 4071 is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_32 : \ 4072 /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_32) 4073 4074 #define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0 4075 #define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL 4076 4077 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0 4078 #define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL 4079 4080 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0 4081 #define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL 4082 4083 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0 4084 #define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL 4085 4086 4087 union uvxh_lb_bau_sb_activation_status_2_u { 4088 unsigned long v; 4089 struct uvxh_lb_bau_sb_activation_status_2_s { 4090 unsigned long aux_error:64; /* RW */ 4091 } sx; 4092 struct uv2h_lb_bau_sb_activation_status_2_s { 4093 unsigned long aux_error:64; /* RW */ 4094 } s2; 4095 struct uv3h_lb_bau_sb_activation_status_2_s { 4096 unsigned long aux_error:64; /* RW */ 4097 } s3; 4098 struct uv4h_lb_bau_sb_activation_status_2_s { 4099 unsigned long aux_error:64; /* RW */ 4100 } s4; 4101 }; 4102 4103 /* ========================================================================= */ 4104 /* UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK */ 4105 /* ========================================================================= */ 4106 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK 0x320130UL 4107 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_32 0x9f0 4108 4109 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_SHFT 0 4110 #define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_MASK 0x00000000ffffffffUL 4111 4112 union uv1h_lb_target_physical_apic_id_mask_u { 4113 unsigned long v; 4114 struct uv1h_lb_target_physical_apic_id_mask_s { 4115 unsigned long bit_enables:32; /* RW */ 4116 unsigned long rsvd_32_63:32; 4117 } s1; 4118 }; 4119 4120 /* ========================================================================= */ 4121 /* UV3H_GR0_GAM_GR_CONFIG */ 4122 /* ========================================================================= */ 4123 #define UV3H_GR0_GAM_GR_CONFIG 0xc00028UL 4124 4125 #define UV3H_GR0_GAM_GR_CONFIG_M_SKT_SHFT 0 4126 #define UV3H_GR0_GAM_GR_CONFIG_SUBSPACE_SHFT 10 4127 #define UV3H_GR0_GAM_GR_CONFIG_M_SKT_MASK 0x000000000000003fUL 4128 #define UV3H_GR0_GAM_GR_CONFIG_SUBSPACE_MASK 0x0000000000000400UL 4129 4130 union uv3h_gr0_gam_gr_config_u { 4131 unsigned long v; 4132 struct uv3h_gr0_gam_gr_config_s { 4133 unsigned long m_skt:6; /* RW */ 4134 unsigned long undef_6_9:4; /* Undefined */ 4135 unsigned long subspace:1; /* RW */ 4136 unsigned long reserved:53; 4137 } s3; 4138 }; 4139 4140 /* ========================================================================= */ 4141 /* UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR */ 4142 /* ========================================================================= */ 4143 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR 0x1603000UL 4144 4145 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT 26 4146 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT 46 4147 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_SHFT 63 4148 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK 0x00003ffffc000000UL 4149 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK 0x000fc00000000000UL 4150 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK 0x8000000000000000UL 4151 4152 union uv3h_rh_gam_mmioh_overlay_config0_mmr_u { 4153 unsigned long v; 4154 struct uv3h_rh_gam_mmioh_overlay_config0_mmr_s { 4155 unsigned long rsvd_0_25:26; 4156 unsigned long base:20; /* RW */ 4157 unsigned long m_io:6; /* RW */ 4158 unsigned long n_io:4; 4159 unsigned long rsvd_56_62:7; 4160 unsigned long enable:1; /* RW */ 4161 } s3; 4162 }; 4163 4164 /* ========================================================================= */ 4165 /* UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR */ 4166 /* ========================================================================= */ 4167 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR 0x1604000UL 4168 4169 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_SHFT 26 4170 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT 46 4171 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_SHFT 63 4172 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK 0x00003ffffc000000UL 4173 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK 0x000fc00000000000UL 4174 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_MASK 0x8000000000000000UL 4175 4176 union uv3h_rh_gam_mmioh_overlay_config1_mmr_u { 4177 unsigned long v; 4178 struct uv3h_rh_gam_mmioh_overlay_config1_mmr_s { 4179 unsigned long rsvd_0_25:26; 4180 unsigned long base:20; /* RW */ 4181 unsigned long m_io:6; /* RW */ 4182 unsigned long n_io:4; 4183 unsigned long rsvd_56_62:7; 4184 unsigned long enable:1; /* RW */ 4185 } s3; 4186 }; 4187 4188 /* ========================================================================= */ 4189 /* UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR */ 4190 /* ========================================================================= */ 4191 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR 0x1603800UL 4192 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH 128 4193 4194 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_SHFT 0 4195 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK 0x0000000000007fffUL 4196 4197 union uv3h_rh_gam_mmioh_redirect_config0_mmr_u { 4198 unsigned long v; 4199 struct uv3h_rh_gam_mmioh_redirect_config0_mmr_s { 4200 unsigned long nasid:15; /* RW */ 4201 unsigned long rsvd_15_63:49; 4202 } s3; 4203 }; 4204 4205 /* ========================================================================= */ 4206 /* UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR */ 4207 /* ========================================================================= */ 4208 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR 0x1604800UL 4209 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH 128 4210 4211 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_SHFT 0 4212 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK 0x0000000000007fffUL 4213 4214 union uv3h_rh_gam_mmioh_redirect_config1_mmr_u { 4215 unsigned long v; 4216 struct uv3h_rh_gam_mmioh_redirect_config1_mmr_s { 4217 unsigned long nasid:15; /* RW */ 4218 unsigned long rsvd_15_63:49; 4219 } s3; 4220 }; 4221 4222 /* ========================================================================= */ 4223 /* UV4H_LB_PROC_INTD_QUEUE_FIRST */ 4224 /* ========================================================================= */ 4225 #define UV4H_LB_PROC_INTD_QUEUE_FIRST 0xa4100UL 4226 4227 #define UV4H_LB_PROC_INTD_QUEUE_FIRST_FIRST_PAYLOAD_ADDRESS_SHFT 6 4228 #define UV4H_LB_PROC_INTD_QUEUE_FIRST_FIRST_PAYLOAD_ADDRESS_MASK 0x00003fffffffffc0UL 4229 4230 union uv4h_lb_proc_intd_queue_first_u { 4231 unsigned long v; 4232 struct uv4h_lb_proc_intd_queue_first_s { 4233 unsigned long undef_0_5:6; /* Undefined */ 4234 unsigned long first_payload_address:40; /* RW */ 4235 } s4; 4236 }; 4237 4238 /* ========================================================================= */ 4239 /* UV4H_LB_PROC_INTD_QUEUE_LAST */ 4240 /* ========================================================================= */ 4241 #define UV4H_LB_PROC_INTD_QUEUE_LAST 0xa4108UL 4242 4243 #define UV4H_LB_PROC_INTD_QUEUE_LAST_LAST_PAYLOAD_ADDRESS_SHFT 5 4244 #define UV4H_LB_PROC_INTD_QUEUE_LAST_LAST_PAYLOAD_ADDRESS_MASK 0x00003fffffffffe0UL 4245 4246 union uv4h_lb_proc_intd_queue_last_u { 4247 unsigned long v; 4248 struct uv4h_lb_proc_intd_queue_last_s { 4249 unsigned long undef_0_4:5; /* Undefined */ 4250 unsigned long last_payload_address:41; /* RW */ 4251 } s4; 4252 }; 4253 4254 /* ========================================================================= */ 4255 /* UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR */ 4256 /* ========================================================================= */ 4257 #define UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR 0xa4118UL 4258 4259 #define UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR_SOFT_ACK_PENDING_FLAGS_SHFT 0 4260 #define UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR_SOFT_ACK_PENDING_FLAGS_MASK 0x00000000000000ffUL 4261 4262 union uv4h_lb_proc_intd_soft_ack_clear_u { 4263 unsigned long v; 4264 struct uv4h_lb_proc_intd_soft_ack_clear_s { 4265 unsigned long soft_ack_pending_flags:8; /* WP */ 4266 } s4; 4267 }; 4268 4269 /* ========================================================================= */ 4270 /* UV4H_LB_PROC_INTD_SOFT_ACK_PENDING */ 4271 /* ========================================================================= */ 4272 #define UV4H_LB_PROC_INTD_SOFT_ACK_PENDING 0xa4110UL 4273 4274 #define UV4H_LB_PROC_INTD_SOFT_ACK_PENDING_SOFT_ACK_FLAGS_SHFT 0 4275 #define UV4H_LB_PROC_INTD_SOFT_ACK_PENDING_SOFT_ACK_FLAGS_MASK 0x00000000000000ffUL 4276 4277 union uv4h_lb_proc_intd_soft_ack_pending_u { 4278 unsigned long v; 4279 struct uv4h_lb_proc_intd_soft_ack_pending_s { 4280 unsigned long soft_ack_flags:8; /* RW */ 4281 } s4; 4282 }; 4283 4284 4285 #endif /* _ASM_X86_UV_UV_MMRS_H */ 4286