1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * SGI UV architectural definitions 7 * 8 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved. 9 */ 10 11 #ifndef _ASM_X86_UV_UV_HUB_H 12 #define _ASM_X86_UV_UV_HUB_H 13 14 #ifdef CONFIG_X86_64 15 #include <linux/numa.h> 16 #include <linux/percpu.h> 17 #include <linux/timer.h> 18 #include <linux/io.h> 19 #include <linux/topology.h> 20 #include <asm/types.h> 21 #include <asm/percpu.h> 22 #include <asm/uv/uv.h> 23 #include <asm/uv/uv_mmrs.h> 24 #include <asm/uv/bios.h> 25 #include <asm/irq_vectors.h> 26 #include <asm/io_apic.h> 27 28 29 /* 30 * Addressing Terminology 31 * 32 * M - The low M bits of a physical address represent the offset 33 * into the blade local memory. RAM memory on a blade is physically 34 * contiguous (although various IO spaces may punch holes in 35 * it).. 36 * 37 * N - Number of bits in the node portion of a socket physical 38 * address. 39 * 40 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of 41 * routers always have low bit of 1, C/MBricks have low bit 42 * equal to 0. Most addressing macros that target UV hub chips 43 * right shift the NASID by 1 to exclude the always-zero bit. 44 * NASIDs contain up to 15 bits. 45 * 46 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead 47 * of nasids. 48 * 49 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant 50 * of the nasid for socket usage. 51 * 52 * GPA - (global physical address) a socket physical address converted 53 * so that it can be used by the GRU as a global address. Socket 54 * physical addresses 1) need additional NASID (node) bits added 55 * to the high end of the address, and 2) unaliased if the 56 * partition does not have a physical address 0. In addition, on 57 * UV2 rev 1, GPAs need the gnode left shifted to bits 39 or 40. 58 * 59 * 60 * NumaLink Global Physical Address Format: 61 * +--------------------------------+---------------------+ 62 * |00..000| GNODE | NodeOffset | 63 * +--------------------------------+---------------------+ 64 * |<-------53 - M bits --->|<--------M bits -----> 65 * 66 * M - number of node offset bits (35 .. 40) 67 * 68 * 69 * Memory/UV-HUB Processor Socket Address Format: 70 * +----------------+---------------+---------------------+ 71 * |00..000000000000| PNODE | NodeOffset | 72 * +----------------+---------------+---------------------+ 73 * <--- N bits --->|<--------M bits -----> 74 * 75 * M - number of node offset bits (35 .. 40) 76 * N - number of PNODE bits (0 .. 10) 77 * 78 * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64). 79 * The actual values are configuration dependent and are set at 80 * boot time. M & N values are set by the hardware/BIOS at boot. 81 * 82 * 83 * APICID format 84 * NOTE!!!!!! This is the current format of the APICID. However, code 85 * should assume that this will change in the future. Use functions 86 * in this file for all APICID bit manipulations and conversion. 87 * 88 * 1111110000000000 89 * 5432109876543210 90 * pppppppppplc0cch Nehalem-EX (12 bits in hdw reg) 91 * ppppppppplcc0cch Westmere-EX (12 bits in hdw reg) 92 * pppppppppppcccch SandyBridge (15 bits in hdw reg) 93 * sssssssssss 94 * 95 * p = pnode bits 96 * l = socket number on board 97 * c = core 98 * h = hyperthread 99 * s = bits that are in the SOCKET_ID CSR 100 * 101 * Note: Processor may support fewer bits in the APICID register. The ACPI 102 * tables hold all 16 bits. Software needs to be aware of this. 103 * 104 * Unless otherwise specified, all references to APICID refer to 105 * the FULL value contained in ACPI tables, not the subset in the 106 * processor APICID register. 107 */ 108 109 /* 110 * Maximum number of bricks in all partitions and in all coherency domains. 111 * This is the total number of bricks accessible in the numalink fabric. It 112 * includes all C & M bricks. Routers are NOT included. 113 * 114 * This value is also the value of the maximum number of non-router NASIDs 115 * in the numalink fabric. 116 * 117 * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused. 118 */ 119 #define UV_MAX_NUMALINK_BLADES 16384 120 121 /* 122 * Maximum number of C/Mbricks within a software SSI (hardware may support 123 * more). 124 */ 125 #define UV_MAX_SSI_BLADES 256 126 127 /* 128 * The largest possible NASID of a C or M brick (+ 2) 129 */ 130 #define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_BLADES * 2) 131 132 /* System Controller Interface Reg info */ 133 struct uv_scir_s { 134 struct timer_list timer; 135 unsigned long offset; 136 unsigned long last; 137 unsigned long idle_on; 138 unsigned long idle_off; 139 unsigned char state; 140 unsigned char enabled; 141 }; 142 143 /* GAM (globally addressed memory) range table */ 144 struct uv_gam_range_s { 145 u32 limit; /* PA bits 56:26 (GAM_RANGE_SHFT) */ 146 u16 nasid; /* node's global physical address */ 147 s8 base; /* entry index of node's base addr */ 148 u8 reserved; 149 }; 150 151 /* 152 * The following defines attributes of the HUB chip. These attributes are 153 * frequently referenced and are kept in a common per hub struct. 154 * After setup, the struct is read only, so it should be readily 155 * available in the L3 cache on the cpu socket for the node. 156 */ 157 struct uv_hub_info_s { 158 unsigned long global_mmr_base; 159 unsigned long global_mmr_shift; 160 unsigned long gpa_mask; 161 unsigned short *socket_to_node; 162 unsigned short *socket_to_pnode; 163 unsigned short *pnode_to_socket; 164 struct uv_gam_range_s *gr_table; 165 unsigned short min_socket; 166 unsigned short min_pnode; 167 unsigned char m_val; 168 unsigned char n_val; 169 unsigned char gr_table_len; 170 unsigned char hub_revision; 171 unsigned char apic_pnode_shift; 172 unsigned char gpa_shift; 173 unsigned char m_shift; 174 unsigned char n_lshift; 175 unsigned int gnode_extra; 176 unsigned long gnode_upper; 177 unsigned long lowmem_remap_top; 178 unsigned long lowmem_remap_base; 179 unsigned long global_gru_base; 180 unsigned long global_gru_shift; 181 unsigned short pnode; 182 unsigned short pnode_mask; 183 unsigned short coherency_domain_number; 184 unsigned short numa_blade_id; 185 unsigned short nr_possible_cpus; 186 unsigned short nr_online_cpus; 187 short memory_nid; 188 }; 189 190 /* CPU specific info with a pointer to the hub common info struct */ 191 struct uv_cpu_info_s { 192 void *p_uv_hub_info; 193 unsigned char blade_cpu_id; 194 struct uv_scir_s scir; 195 }; 196 DECLARE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info); 197 198 #define uv_cpu_info this_cpu_ptr(&__uv_cpu_info) 199 #define uv_cpu_info_per(cpu) (&per_cpu(__uv_cpu_info, cpu)) 200 201 #define uv_scir_info (&uv_cpu_info->scir) 202 #define uv_cpu_scir_info(cpu) (&uv_cpu_info_per(cpu)->scir) 203 204 /* Node specific hub common info struct */ 205 extern void **__uv_hub_info_list; 206 static inline struct uv_hub_info_s *uv_hub_info_list(int node) 207 { 208 return (struct uv_hub_info_s *)__uv_hub_info_list[node]; 209 } 210 211 static inline struct uv_hub_info_s *_uv_hub_info(void) 212 { 213 return (struct uv_hub_info_s *)uv_cpu_info->p_uv_hub_info; 214 } 215 #define uv_hub_info _uv_hub_info() 216 217 static inline struct uv_hub_info_s *uv_cpu_hub_info(int cpu) 218 { 219 return (struct uv_hub_info_s *)uv_cpu_info_per(cpu)->p_uv_hub_info; 220 } 221 222 /* 223 * HUB revision ranges for each UV HUB architecture. 224 * This is a software convention - NOT the hardware revision numbers in 225 * the hub chip. 226 */ 227 #define UV1_HUB_REVISION_BASE 1 228 #define UV2_HUB_REVISION_BASE 3 229 #define UV3_HUB_REVISION_BASE 5 230 #define UV4_HUB_REVISION_BASE 7 231 #define UV4A_HUB_REVISION_BASE 8 /* UV4 (fixed) rev 2 */ 232 233 static inline int is_uv1_hub(void) 234 { 235 return is_uv_hubbed(uv(1)); 236 } 237 238 static inline int is_uv2_hub(void) 239 { 240 return is_uv_hubbed(uv(2)); 241 } 242 243 static inline int is_uv3_hub(void) 244 { 245 return is_uv_hubbed(uv(3)); 246 } 247 248 /* First test "is UV4A", then "is UV4" */ 249 static inline int is_uv4a_hub(void) 250 { 251 if (is_uv_hubbed(uv(4))) 252 return (uv_hub_info->hub_revision == UV4A_HUB_REVISION_BASE); 253 return 0; 254 } 255 256 static inline int is_uv4_hub(void) 257 { 258 return is_uv_hubbed(uv(4)); 259 } 260 261 static inline int is_uvx_hub(void) 262 { 263 return (is_uv_hubbed(-2) >= uv(2)); 264 } 265 266 static inline int is_uv_hub(void) 267 { 268 return is_uv1_hub() || is_uvx_hub(); 269 } 270 271 union uvh_apicid { 272 unsigned long v; 273 struct uvh_apicid_s { 274 unsigned long local_apic_mask : 24; 275 unsigned long local_apic_shift : 5; 276 unsigned long unused1 : 3; 277 unsigned long pnode_mask : 24; 278 unsigned long pnode_shift : 5; 279 unsigned long unused2 : 3; 280 } s; 281 }; 282 283 /* 284 * Local & Global MMR space macros. 285 * Note: macros are intended to be used ONLY by inline functions 286 * in this file - not by other kernel code. 287 * n - NASID (full 15-bit global nasid) 288 * g - GNODE (full 15-bit global nasid, right shifted 1) 289 * p - PNODE (local part of nsids, right shifted 1) 290 */ 291 #define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask) 292 #define UV_PNODE_TO_GNODE(p) ((p) |uv_hub_info->gnode_extra) 293 #define UV_PNODE_TO_NASID(p) (UV_PNODE_TO_GNODE(p) << 1) 294 295 #define UV1_LOCAL_MMR_BASE 0xf4000000UL 296 #define UV1_GLOBAL_MMR32_BASE 0xf8000000UL 297 #define UV1_LOCAL_MMR_SIZE (64UL * 1024 * 1024) 298 #define UV1_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024) 299 300 #define UV2_LOCAL_MMR_BASE 0xfa000000UL 301 #define UV2_GLOBAL_MMR32_BASE 0xfc000000UL 302 #define UV2_LOCAL_MMR_SIZE (32UL * 1024 * 1024) 303 #define UV2_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024) 304 305 #define UV3_LOCAL_MMR_BASE 0xfa000000UL 306 #define UV3_GLOBAL_MMR32_BASE 0xfc000000UL 307 #define UV3_LOCAL_MMR_SIZE (32UL * 1024 * 1024) 308 #define UV3_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024) 309 310 #define UV4_LOCAL_MMR_BASE 0xfa000000UL 311 #define UV4_GLOBAL_MMR32_BASE 0xfc000000UL 312 #define UV4_LOCAL_MMR_SIZE (32UL * 1024 * 1024) 313 #define UV4_GLOBAL_MMR32_SIZE (16UL * 1024 * 1024) 314 315 #define UV_LOCAL_MMR_BASE ( \ 316 is_uv1_hub() ? UV1_LOCAL_MMR_BASE : \ 317 is_uv2_hub() ? UV2_LOCAL_MMR_BASE : \ 318 is_uv3_hub() ? UV3_LOCAL_MMR_BASE : \ 319 /*is_uv4_hub*/ UV4_LOCAL_MMR_BASE) 320 321 #define UV_GLOBAL_MMR32_BASE ( \ 322 is_uv1_hub() ? UV1_GLOBAL_MMR32_BASE : \ 323 is_uv2_hub() ? UV2_GLOBAL_MMR32_BASE : \ 324 is_uv3_hub() ? UV3_GLOBAL_MMR32_BASE : \ 325 /*is_uv4_hub*/ UV4_GLOBAL_MMR32_BASE) 326 327 #define UV_LOCAL_MMR_SIZE ( \ 328 is_uv1_hub() ? UV1_LOCAL_MMR_SIZE : \ 329 is_uv2_hub() ? UV2_LOCAL_MMR_SIZE : \ 330 is_uv3_hub() ? UV3_LOCAL_MMR_SIZE : \ 331 /*is_uv4_hub*/ UV4_LOCAL_MMR_SIZE) 332 333 #define UV_GLOBAL_MMR32_SIZE ( \ 334 is_uv1_hub() ? UV1_GLOBAL_MMR32_SIZE : \ 335 is_uv2_hub() ? UV2_GLOBAL_MMR32_SIZE : \ 336 is_uv3_hub() ? UV3_GLOBAL_MMR32_SIZE : \ 337 /*is_uv4_hub*/ UV4_GLOBAL_MMR32_SIZE) 338 339 #define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base) 340 341 #define UV_GLOBAL_GRU_MMR_BASE 0x4000000 342 343 #define UV_GLOBAL_MMR32_PNODE_SHIFT 15 344 #define _UV_GLOBAL_MMR64_PNODE_SHIFT 26 345 #define UV_GLOBAL_MMR64_PNODE_SHIFT (uv_hub_info->global_mmr_shift) 346 347 #define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT)) 348 349 #define UV_GLOBAL_MMR64_PNODE_BITS(p) \ 350 (((unsigned long)(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT) 351 352 #define UVH_APICID 0x002D0E00L 353 #define UV_APIC_PNODE_SHIFT 6 354 355 #define UV_APICID_HIBIT_MASK 0xffff0000 356 357 /* Local Bus from cpu's perspective */ 358 #define LOCAL_BUS_BASE 0x1c00000 359 #define LOCAL_BUS_SIZE (4 * 1024 * 1024) 360 361 /* 362 * System Controller Interface Reg 363 * 364 * Note there are NO leds on a UV system. This register is only 365 * used by the system controller to monitor system-wide operation. 366 * There are 64 regs per node. With Nahelem cpus (2 cores per node, 367 * 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on 368 * a node. 369 * 370 * The window is located at top of ACPI MMR space 371 */ 372 #define SCIR_WINDOW_COUNT 64 373 #define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \ 374 LOCAL_BUS_SIZE - \ 375 SCIR_WINDOW_COUNT) 376 377 #define SCIR_CPU_HEARTBEAT 0x01 /* timer interrupt */ 378 #define SCIR_CPU_ACTIVITY 0x02 /* not idle */ 379 #define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */ 380 381 /* Loop through all installed blades */ 382 #define for_each_possible_blade(bid) \ 383 for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++) 384 385 /* 386 * Macros for converting between kernel virtual addresses, socket local physical 387 * addresses, and UV global physical addresses. 388 * Note: use the standard __pa() & __va() macros for converting 389 * between socket virtual and socket physical addresses. 390 */ 391 392 /* global bits offset - number of local address bits in gpa for this UV arch */ 393 static inline unsigned int uv_gpa_shift(void) 394 { 395 return uv_hub_info->gpa_shift; 396 } 397 #define _uv_gpa_shift 398 399 /* Find node that has the address range that contains global address */ 400 static inline struct uv_gam_range_s *uv_gam_range(unsigned long pa) 401 { 402 struct uv_gam_range_s *gr = uv_hub_info->gr_table; 403 unsigned long pal = (pa & uv_hub_info->gpa_mask) >> UV_GAM_RANGE_SHFT; 404 int i, num = uv_hub_info->gr_table_len; 405 406 if (gr) { 407 for (i = 0; i < num; i++, gr++) { 408 if (pal < gr->limit) 409 return gr; 410 } 411 } 412 pr_crit("UV: GAM Range for 0x%lx not found at %p!\n", pa, gr); 413 BUG(); 414 } 415 416 /* Return base address of node that contains global address */ 417 static inline unsigned long uv_gam_range_base(unsigned long pa) 418 { 419 struct uv_gam_range_s *gr = uv_gam_range(pa); 420 int base = gr->base; 421 422 if (base < 0) 423 return 0UL; 424 425 return uv_hub_info->gr_table[base].limit; 426 } 427 428 /* socket phys RAM --> UV global NASID (UV4+) */ 429 static inline unsigned long uv_soc_phys_ram_to_nasid(unsigned long paddr) 430 { 431 return uv_gam_range(paddr)->nasid; 432 } 433 #define _uv_soc_phys_ram_to_nasid 434 435 /* socket virtual --> UV global NASID (UV4+) */ 436 static inline unsigned long uv_gpa_nasid(void *v) 437 { 438 return uv_soc_phys_ram_to_nasid(__pa(v)); 439 } 440 441 /* socket phys RAM --> UV global physical address */ 442 static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr) 443 { 444 unsigned int m_val = uv_hub_info->m_val; 445 446 if (paddr < uv_hub_info->lowmem_remap_top) 447 paddr |= uv_hub_info->lowmem_remap_base; 448 449 if (m_val) { 450 paddr |= uv_hub_info->gnode_upper; 451 paddr = ((paddr << uv_hub_info->m_shift) 452 >> uv_hub_info->m_shift) | 453 ((paddr >> uv_hub_info->m_val) 454 << uv_hub_info->n_lshift); 455 } else { 456 paddr |= uv_soc_phys_ram_to_nasid(paddr) 457 << uv_hub_info->gpa_shift; 458 } 459 return paddr; 460 } 461 462 /* socket virtual --> UV global physical address */ 463 static inline unsigned long uv_gpa(void *v) 464 { 465 return uv_soc_phys_ram_to_gpa(__pa(v)); 466 } 467 468 /* Top two bits indicate the requested address is in MMR space. */ 469 static inline int 470 uv_gpa_in_mmr_space(unsigned long gpa) 471 { 472 return (gpa >> 62) == 0x3UL; 473 } 474 475 /* UV global physical address --> socket phys RAM */ 476 static inline unsigned long uv_gpa_to_soc_phys_ram(unsigned long gpa) 477 { 478 unsigned long paddr; 479 unsigned long remap_base = uv_hub_info->lowmem_remap_base; 480 unsigned long remap_top = uv_hub_info->lowmem_remap_top; 481 unsigned int m_val = uv_hub_info->m_val; 482 483 if (m_val) 484 gpa = ((gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift) | 485 ((gpa >> uv_hub_info->n_lshift) << uv_hub_info->m_val); 486 487 paddr = gpa & uv_hub_info->gpa_mask; 488 if (paddr >= remap_base && paddr < remap_base + remap_top) 489 paddr -= remap_base; 490 return paddr; 491 } 492 493 /* gpa -> gnode */ 494 static inline unsigned long uv_gpa_to_gnode(unsigned long gpa) 495 { 496 unsigned int n_lshift = uv_hub_info->n_lshift; 497 498 if (n_lshift) 499 return gpa >> n_lshift; 500 501 return uv_gam_range(gpa)->nasid >> 1; 502 } 503 504 /* gpa -> pnode */ 505 static inline int uv_gpa_to_pnode(unsigned long gpa) 506 { 507 return uv_gpa_to_gnode(gpa) & uv_hub_info->pnode_mask; 508 } 509 510 /* gpa -> node offset */ 511 static inline unsigned long uv_gpa_to_offset(unsigned long gpa) 512 { 513 unsigned int m_shift = uv_hub_info->m_shift; 514 515 if (m_shift) 516 return (gpa << m_shift) >> m_shift; 517 518 return (gpa & uv_hub_info->gpa_mask) - uv_gam_range_base(gpa); 519 } 520 521 /* Convert socket to node */ 522 static inline int _uv_socket_to_node(int socket, unsigned short *s2nid) 523 { 524 return s2nid ? s2nid[socket - uv_hub_info->min_socket] : socket; 525 } 526 527 static inline int uv_socket_to_node(int socket) 528 { 529 return _uv_socket_to_node(socket, uv_hub_info->socket_to_node); 530 } 531 532 /* pnode, offset --> socket virtual */ 533 static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset) 534 { 535 unsigned int m_val = uv_hub_info->m_val; 536 unsigned long base; 537 unsigned short sockid, node, *p2s; 538 539 if (m_val) 540 return __va(((unsigned long)pnode << m_val) | offset); 541 542 p2s = uv_hub_info->pnode_to_socket; 543 sockid = p2s ? p2s[pnode - uv_hub_info->min_pnode] : pnode; 544 node = uv_socket_to_node(sockid); 545 546 /* limit address of previous socket is our base, except node 0 is 0 */ 547 if (!node) 548 return __va((unsigned long)offset); 549 550 base = (unsigned long)(uv_hub_info->gr_table[node - 1].limit); 551 return __va(base << UV_GAM_RANGE_SHFT | offset); 552 } 553 554 /* Extract/Convert a PNODE from an APICID (full apicid, not processor subset) */ 555 static inline int uv_apicid_to_pnode(int apicid) 556 { 557 int pnode = apicid >> uv_hub_info->apic_pnode_shift; 558 unsigned short *s2pn = uv_hub_info->socket_to_pnode; 559 560 return s2pn ? s2pn[pnode - uv_hub_info->min_socket] : pnode; 561 } 562 563 /* Convert an apicid to the socket number on the blade */ 564 static inline int uv_apicid_to_socket(int apicid) 565 { 566 if (is_uv1_hub()) 567 return (apicid >> (uv_hub_info->apic_pnode_shift - 1)) & 1; 568 else 569 return 0; 570 } 571 572 /* 573 * Access global MMRs using the low memory MMR32 space. This region supports 574 * faster MMR access but not all MMRs are accessible in this space. 575 */ 576 static inline unsigned long *uv_global_mmr32_address(int pnode, unsigned long offset) 577 { 578 return __va(UV_GLOBAL_MMR32_BASE | 579 UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset); 580 } 581 582 static inline void uv_write_global_mmr32(int pnode, unsigned long offset, unsigned long val) 583 { 584 writeq(val, uv_global_mmr32_address(pnode, offset)); 585 } 586 587 static inline unsigned long uv_read_global_mmr32(int pnode, unsigned long offset) 588 { 589 return readq(uv_global_mmr32_address(pnode, offset)); 590 } 591 592 /* 593 * Access Global MMR space using the MMR space located at the top of physical 594 * memory. 595 */ 596 static inline volatile void __iomem *uv_global_mmr64_address(int pnode, unsigned long offset) 597 { 598 return __va(UV_GLOBAL_MMR64_BASE | 599 UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset); 600 } 601 602 static inline void uv_write_global_mmr64(int pnode, unsigned long offset, unsigned long val) 603 { 604 writeq(val, uv_global_mmr64_address(pnode, offset)); 605 } 606 607 static inline unsigned long uv_read_global_mmr64(int pnode, unsigned long offset) 608 { 609 return readq(uv_global_mmr64_address(pnode, offset)); 610 } 611 612 static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val) 613 { 614 writeb(val, uv_global_mmr64_address(pnode, offset)); 615 } 616 617 static inline unsigned char uv_read_global_mmr8(int pnode, unsigned long offset) 618 { 619 return readb(uv_global_mmr64_address(pnode, offset)); 620 } 621 622 /* 623 * Access hub local MMRs. Faster than using global space but only local MMRs 624 * are accessible. 625 */ 626 static inline unsigned long *uv_local_mmr_address(unsigned long offset) 627 { 628 return __va(UV_LOCAL_MMR_BASE | offset); 629 } 630 631 static inline unsigned long uv_read_local_mmr(unsigned long offset) 632 { 633 return readq(uv_local_mmr_address(offset)); 634 } 635 636 static inline void uv_write_local_mmr(unsigned long offset, unsigned long val) 637 { 638 writeq(val, uv_local_mmr_address(offset)); 639 } 640 641 static inline unsigned char uv_read_local_mmr8(unsigned long offset) 642 { 643 return readb(uv_local_mmr_address(offset)); 644 } 645 646 static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val) 647 { 648 writeb(val, uv_local_mmr_address(offset)); 649 } 650 651 /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */ 652 static inline int uv_blade_processor_id(void) 653 { 654 return uv_cpu_info->blade_cpu_id; 655 } 656 657 /* Blade-local cpu number of cpu N. Numbered 0 .. <# cpus on the blade> */ 658 static inline int uv_cpu_blade_processor_id(int cpu) 659 { 660 return uv_cpu_info_per(cpu)->blade_cpu_id; 661 } 662 #define _uv_cpu_blade_processor_id 1 /* indicate function available */ 663 664 /* Blade number to Node number (UV1..UV4 is 1:1) */ 665 static inline int uv_blade_to_node(int blade) 666 { 667 return blade; 668 } 669 670 /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */ 671 static inline int uv_numa_blade_id(void) 672 { 673 return uv_hub_info->numa_blade_id; 674 } 675 676 /* 677 * Convert linux node number to the UV blade number. 678 * .. Currently for UV1 thru UV4 the node and the blade are identical. 679 * .. If this changes then you MUST check references to this function! 680 */ 681 static inline int uv_node_to_blade_id(int nid) 682 { 683 return nid; 684 } 685 686 /* Convert a cpu number to the the UV blade number */ 687 static inline int uv_cpu_to_blade_id(int cpu) 688 { 689 return uv_node_to_blade_id(cpu_to_node(cpu)); 690 } 691 692 /* Convert a blade id to the PNODE of the blade */ 693 static inline int uv_blade_to_pnode(int bid) 694 { 695 return uv_hub_info_list(uv_blade_to_node(bid))->pnode; 696 } 697 698 /* Nid of memory node on blade. -1 if no blade-local memory */ 699 static inline int uv_blade_to_memory_nid(int bid) 700 { 701 return uv_hub_info_list(uv_blade_to_node(bid))->memory_nid; 702 } 703 704 /* Determine the number of possible cpus on a blade */ 705 static inline int uv_blade_nr_possible_cpus(int bid) 706 { 707 return uv_hub_info_list(uv_blade_to_node(bid))->nr_possible_cpus; 708 } 709 710 /* Determine the number of online cpus on a blade */ 711 static inline int uv_blade_nr_online_cpus(int bid) 712 { 713 return uv_hub_info_list(uv_blade_to_node(bid))->nr_online_cpus; 714 } 715 716 /* Convert a cpu id to the PNODE of the blade containing the cpu */ 717 static inline int uv_cpu_to_pnode(int cpu) 718 { 719 return uv_cpu_hub_info(cpu)->pnode; 720 } 721 722 /* Convert a linux node number to the PNODE of the blade */ 723 static inline int uv_node_to_pnode(int nid) 724 { 725 return uv_hub_info_list(nid)->pnode; 726 } 727 728 /* Maximum possible number of blades */ 729 extern short uv_possible_blades; 730 static inline int uv_num_possible_blades(void) 731 { 732 return uv_possible_blades; 733 } 734 735 /* Per Hub NMI support */ 736 extern void uv_nmi_setup(void); 737 extern void uv_nmi_setup_hubless(void); 738 739 /* BIOS/Kernel flags exchange MMR */ 740 #define UVH_BIOS_KERNEL_MMR UVH_SCRATCH5 741 #define UVH_BIOS_KERNEL_MMR_ALIAS UVH_SCRATCH5_ALIAS 742 #define UVH_BIOS_KERNEL_MMR_ALIAS_2 UVH_SCRATCH5_ALIAS_2 743 744 /* TSC sync valid, set by BIOS */ 745 #define UVH_TSC_SYNC_MMR UVH_BIOS_KERNEL_MMR 746 #define UVH_TSC_SYNC_SHIFT 10 747 #define UVH_TSC_SYNC_SHIFT_UV2K 16 /* UV2/3k have different bits */ 748 #define UVH_TSC_SYNC_MASK 3 /* 0011 */ 749 #define UVH_TSC_SYNC_VALID 3 /* 0011 */ 750 #define UVH_TSC_SYNC_INVALID 2 /* 0010 */ 751 752 /* BMC sets a bit this MMR non-zero before sending an NMI */ 753 #define UVH_NMI_MMR UVH_BIOS_KERNEL_MMR 754 #define UVH_NMI_MMR_CLEAR UVH_BIOS_KERNEL_MMR_ALIAS 755 #define UVH_NMI_MMR_SHIFT 63 756 #define UVH_NMI_MMR_TYPE "SCRATCH5" 757 758 /* Newer SMM NMI handler, not present in all systems */ 759 #define UVH_NMI_MMRX UVH_EVENT_OCCURRED0 760 #define UVH_NMI_MMRX_CLEAR UVH_EVENT_OCCURRED0_ALIAS 761 #define UVH_NMI_MMRX_SHIFT UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT 762 #define UVH_NMI_MMRX_TYPE "EXTIO_INT0" 763 764 /* Non-zero indicates newer SMM NMI handler present */ 765 #define UVH_NMI_MMRX_SUPPORTED UVH_EXTIO_INT0_BROADCAST 766 767 /* Indicates to BIOS that we want to use the newer SMM NMI handler */ 768 #define UVH_NMI_MMRX_REQ UVH_BIOS_KERNEL_MMR_ALIAS_2 769 #define UVH_NMI_MMRX_REQ_SHIFT 62 770 771 struct uv_hub_nmi_s { 772 raw_spinlock_t nmi_lock; 773 atomic_t in_nmi; /* flag this node in UV NMI IRQ */ 774 atomic_t cpu_owner; /* last locker of this struct */ 775 atomic_t read_mmr_count; /* count of MMR reads */ 776 atomic_t nmi_count; /* count of true UV NMIs */ 777 unsigned long nmi_value; /* last value read from NMI MMR */ 778 bool hub_present; /* false means UV hubless system */ 779 bool pch_owner; /* indicates this hub owns PCH */ 780 }; 781 782 struct uv_cpu_nmi_s { 783 struct uv_hub_nmi_s *hub; 784 int state; 785 int pinging; 786 int queries; 787 int pings; 788 }; 789 790 DECLARE_PER_CPU(struct uv_cpu_nmi_s, uv_cpu_nmi); 791 792 #define uv_hub_nmi this_cpu_read(uv_cpu_nmi.hub) 793 #define uv_cpu_nmi_per(cpu) (per_cpu(uv_cpu_nmi, cpu)) 794 #define uv_hub_nmi_per(cpu) (uv_cpu_nmi_per(cpu).hub) 795 796 /* uv_cpu_nmi_states */ 797 #define UV_NMI_STATE_OUT 0 798 #define UV_NMI_STATE_IN 1 799 #define UV_NMI_STATE_DUMP 2 800 #define UV_NMI_STATE_DUMP_DONE 3 801 802 /* Update SCIR state */ 803 static inline void uv_set_scir_bits(unsigned char value) 804 { 805 if (uv_scir_info->state != value) { 806 uv_scir_info->state = value; 807 uv_write_local_mmr8(uv_scir_info->offset, value); 808 } 809 } 810 811 static inline unsigned long uv_scir_offset(int apicid) 812 { 813 return SCIR_LOCAL_MMR_BASE | (apicid & 0x3f); 814 } 815 816 static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value) 817 { 818 if (uv_cpu_scir_info(cpu)->state != value) { 819 uv_write_global_mmr8(uv_cpu_to_pnode(cpu), 820 uv_cpu_scir_info(cpu)->offset, value); 821 uv_cpu_scir_info(cpu)->state = value; 822 } 823 } 824 825 extern unsigned int uv_apicid_hibits; 826 827 /* 828 * Get the minimum revision number of the hub chips within the partition. 829 * (See UVx_HUB_REVISION_BASE above for specific values.) 830 */ 831 static inline int uv_get_min_hub_revision_id(void) 832 { 833 return uv_hub_info->hub_revision; 834 } 835 836 #endif /* CONFIG_X86_64 */ 837 #endif /* _ASM_X86_UV_UV_HUB_H */ 838