1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * SGI UV architectural definitions 7 * 8 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved. 9 */ 10 11 #ifndef _ASM_X86_UV_UV_HUB_H 12 #define _ASM_X86_UV_UV_HUB_H 13 14 #ifdef CONFIG_X86_64 15 #include <linux/numa.h> 16 #include <linux/percpu.h> 17 #include <linux/timer.h> 18 #include <linux/io.h> 19 #include <asm/types.h> 20 #include <asm/percpu.h> 21 #include <asm/uv/uv_mmrs.h> 22 23 24 /* 25 * Addressing Terminology 26 * 27 * M - The low M bits of a physical address represent the offset 28 * into the blade local memory. RAM memory on a blade is physically 29 * contiguous (although various IO spaces may punch holes in 30 * it).. 31 * 32 * N - Number of bits in the node portion of a socket physical 33 * address. 34 * 35 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of 36 * routers always have low bit of 1, C/MBricks have low bit 37 * equal to 0. Most addressing macros that target UV hub chips 38 * right shift the NASID by 1 to exclude the always-zero bit. 39 * NASIDs contain up to 15 bits. 40 * 41 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead 42 * of nasids. 43 * 44 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant 45 * of the nasid for socket usage. 46 * 47 * 48 * NumaLink Global Physical Address Format: 49 * +--------------------------------+---------------------+ 50 * |00..000| GNODE | NodeOffset | 51 * +--------------------------------+---------------------+ 52 * |<-------53 - M bits --->|<--------M bits -----> 53 * 54 * M - number of node offset bits (35 .. 40) 55 * 56 * 57 * Memory/UV-HUB Processor Socket Address Format: 58 * +----------------+---------------+---------------------+ 59 * |00..000000000000| PNODE | NodeOffset | 60 * +----------------+---------------+---------------------+ 61 * <--- N bits --->|<--------M bits -----> 62 * 63 * M - number of node offset bits (35 .. 40) 64 * N - number of PNODE bits (0 .. 10) 65 * 66 * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64). 67 * The actual values are configuration dependent and are set at 68 * boot time. M & N values are set by the hardware/BIOS at boot. 69 * 70 * 71 * APICID format 72 * NOTE!!!!!! This is the current format of the APICID. However, code 73 * should assume that this will change in the future. Use functions 74 * in this file for all APICID bit manipulations and conversion. 75 * 76 * 1111110000000000 77 * 5432109876543210 78 * pppppppppplc0cch 79 * sssssssssss 80 * 81 * p = pnode bits 82 * l = socket number on board 83 * c = core 84 * h = hyperthread 85 * s = bits that are in the SOCKET_ID CSR 86 * 87 * Note: Processor only supports 12 bits in the APICID register. The ACPI 88 * tables hold all 16 bits. Software needs to be aware of this. 89 * 90 * Unless otherwise specified, all references to APICID refer to 91 * the FULL value contained in ACPI tables, not the subset in the 92 * processor APICID register. 93 */ 94 95 96 /* 97 * Maximum number of bricks in all partitions and in all coherency domains. 98 * This is the total number of bricks accessible in the numalink fabric. It 99 * includes all C & M bricks. Routers are NOT included. 100 * 101 * This value is also the value of the maximum number of non-router NASIDs 102 * in the numalink fabric. 103 * 104 * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused. 105 */ 106 #define UV_MAX_NUMALINK_BLADES 16384 107 108 /* 109 * Maximum number of C/Mbricks within a software SSI (hardware may support 110 * more). 111 */ 112 #define UV_MAX_SSI_BLADES 256 113 114 /* 115 * The largest possible NASID of a C or M brick (+ 2) 116 */ 117 #define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_NODES * 2) 118 119 struct uv_scir_s { 120 struct timer_list timer; 121 unsigned long offset; 122 unsigned long last; 123 unsigned long idle_on; 124 unsigned long idle_off; 125 unsigned char state; 126 unsigned char enabled; 127 }; 128 129 /* 130 * The following defines attributes of the HUB chip. These attributes are 131 * frequently referenced and are kept in the per-cpu data areas of each cpu. 132 * They are kept together in a struct to minimize cache misses. 133 */ 134 struct uv_hub_info_s { 135 unsigned long global_mmr_base; 136 unsigned long gpa_mask; 137 unsigned int gnode_extra; 138 unsigned long gnode_upper; 139 unsigned long lowmem_remap_top; 140 unsigned long lowmem_remap_base; 141 unsigned short pnode; 142 unsigned short pnode_mask; 143 unsigned short coherency_domain_number; 144 unsigned short numa_blade_id; 145 unsigned char blade_processor_id; 146 unsigned char m_val; 147 unsigned char n_val; 148 struct uv_scir_s scir; 149 }; 150 151 DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); 152 #define uv_hub_info (&__get_cpu_var(__uv_hub_info)) 153 #define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu)) 154 155 /* 156 * Local & Global MMR space macros. 157 * Note: macros are intended to be used ONLY by inline functions 158 * in this file - not by other kernel code. 159 * n - NASID (full 15-bit global nasid) 160 * g - GNODE (full 15-bit global nasid, right shifted 1) 161 * p - PNODE (local part of nsids, right shifted 1) 162 */ 163 #define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask) 164 #define UV_PNODE_TO_GNODE(p) ((p) |uv_hub_info->gnode_extra) 165 #define UV_PNODE_TO_NASID(p) (UV_PNODE_TO_GNODE(p) << 1) 166 167 #define UV_LOCAL_MMR_BASE 0xf4000000UL 168 #define UV_GLOBAL_MMR32_BASE 0xf8000000UL 169 #define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base) 170 #define UV_LOCAL_MMR_SIZE (64UL * 1024 * 1024) 171 #define UV_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024) 172 173 #define UV_GLOBAL_MMR32_PNODE_SHIFT 15 174 #define UV_GLOBAL_MMR64_PNODE_SHIFT 26 175 176 #define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT)) 177 178 #define UV_GLOBAL_MMR64_PNODE_BITS(p) \ 179 (((unsigned long)(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT) 180 181 #define UV_APIC_PNODE_SHIFT 6 182 183 /* Local Bus from cpu's perspective */ 184 #define LOCAL_BUS_BASE 0x1c00000 185 #define LOCAL_BUS_SIZE (4 * 1024 * 1024) 186 187 /* 188 * System Controller Interface Reg 189 * 190 * Note there are NO leds on a UV system. This register is only 191 * used by the system controller to monitor system-wide operation. 192 * There are 64 regs per node. With Nahelem cpus (2 cores per node, 193 * 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on 194 * a node. 195 * 196 * The window is located at top of ACPI MMR space 197 */ 198 #define SCIR_WINDOW_COUNT 64 199 #define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \ 200 LOCAL_BUS_SIZE - \ 201 SCIR_WINDOW_COUNT) 202 203 #define SCIR_CPU_HEARTBEAT 0x01 /* timer interrupt */ 204 #define SCIR_CPU_ACTIVITY 0x02 /* not idle */ 205 #define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */ 206 207 /* Loop through all installed blades */ 208 #define for_each_possible_blade(bid) \ 209 for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++) 210 211 /* 212 * Macros for converting between kernel virtual addresses, socket local physical 213 * addresses, and UV global physical addresses. 214 * Note: use the standard __pa() & __va() macros for converting 215 * between socket virtual and socket physical addresses. 216 */ 217 218 /* socket phys RAM --> UV global physical address */ 219 static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr) 220 { 221 if (paddr < uv_hub_info->lowmem_remap_top) 222 paddr |= uv_hub_info->lowmem_remap_base; 223 return paddr | uv_hub_info->gnode_upper; 224 } 225 226 227 /* socket virtual --> UV global physical address */ 228 static inline unsigned long uv_gpa(void *v) 229 { 230 return uv_soc_phys_ram_to_gpa(__pa(v)); 231 } 232 233 /* pnode, offset --> socket virtual */ 234 static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset) 235 { 236 return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset); 237 } 238 239 240 /* 241 * Extract a PNODE from an APICID (full apicid, not processor subset) 242 */ 243 static inline int uv_apicid_to_pnode(int apicid) 244 { 245 return (apicid >> UV_APIC_PNODE_SHIFT); 246 } 247 248 /* 249 * Access global MMRs using the low memory MMR32 space. This region supports 250 * faster MMR access but not all MMRs are accessible in this space. 251 */ 252 static inline unsigned long *uv_global_mmr32_address(int pnode, 253 unsigned long offset) 254 { 255 return __va(UV_GLOBAL_MMR32_BASE | 256 UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset); 257 } 258 259 static inline void uv_write_global_mmr32(int pnode, unsigned long offset, 260 unsigned long val) 261 { 262 writeq(val, uv_global_mmr32_address(pnode, offset)); 263 } 264 265 static inline unsigned long uv_read_global_mmr32(int pnode, 266 unsigned long offset) 267 { 268 return readq(uv_global_mmr32_address(pnode, offset)); 269 } 270 271 /* 272 * Access Global MMR space using the MMR space located at the top of physical 273 * memory. 274 */ 275 static inline unsigned long *uv_global_mmr64_address(int pnode, 276 unsigned long offset) 277 { 278 return __va(UV_GLOBAL_MMR64_BASE | 279 UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset); 280 } 281 282 static inline void uv_write_global_mmr64(int pnode, unsigned long offset, 283 unsigned long val) 284 { 285 writeq(val, uv_global_mmr64_address(pnode, offset)); 286 } 287 288 static inline unsigned long uv_read_global_mmr64(int pnode, 289 unsigned long offset) 290 { 291 return readq(uv_global_mmr64_address(pnode, offset)); 292 } 293 294 /* 295 * Access hub local MMRs. Faster than using global space but only local MMRs 296 * are accessible. 297 */ 298 static inline unsigned long *uv_local_mmr_address(unsigned long offset) 299 { 300 return __va(UV_LOCAL_MMR_BASE | offset); 301 } 302 303 static inline unsigned long uv_read_local_mmr(unsigned long offset) 304 { 305 return readq(uv_local_mmr_address(offset)); 306 } 307 308 static inline void uv_write_local_mmr(unsigned long offset, unsigned long val) 309 { 310 writeq(val, uv_local_mmr_address(offset)); 311 } 312 313 static inline unsigned char uv_read_local_mmr8(unsigned long offset) 314 { 315 return readb(uv_local_mmr_address(offset)); 316 } 317 318 static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val) 319 { 320 writeb(val, uv_local_mmr_address(offset)); 321 } 322 323 /* 324 * Structures and definitions for converting between cpu, node, pnode, and blade 325 * numbers. 326 */ 327 struct uv_blade_info { 328 unsigned short nr_possible_cpus; 329 unsigned short nr_online_cpus; 330 unsigned short pnode; 331 short memory_nid; 332 }; 333 extern struct uv_blade_info *uv_blade_info; 334 extern short *uv_node_to_blade; 335 extern short *uv_cpu_to_blade; 336 extern short uv_possible_blades; 337 338 /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */ 339 static inline int uv_blade_processor_id(void) 340 { 341 return uv_hub_info->blade_processor_id; 342 } 343 344 /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */ 345 static inline int uv_numa_blade_id(void) 346 { 347 return uv_hub_info->numa_blade_id; 348 } 349 350 /* Convert a cpu number to the the UV blade number */ 351 static inline int uv_cpu_to_blade_id(int cpu) 352 { 353 return uv_cpu_to_blade[cpu]; 354 } 355 356 /* Convert linux node number to the UV blade number */ 357 static inline int uv_node_to_blade_id(int nid) 358 { 359 return uv_node_to_blade[nid]; 360 } 361 362 /* Convert a blade id to the PNODE of the blade */ 363 static inline int uv_blade_to_pnode(int bid) 364 { 365 return uv_blade_info[bid].pnode; 366 } 367 368 /* Nid of memory node on blade. -1 if no blade-local memory */ 369 static inline int uv_blade_to_memory_nid(int bid) 370 { 371 return uv_blade_info[bid].memory_nid; 372 } 373 374 /* Determine the number of possible cpus on a blade */ 375 static inline int uv_blade_nr_possible_cpus(int bid) 376 { 377 return uv_blade_info[bid].nr_possible_cpus; 378 } 379 380 /* Determine the number of online cpus on a blade */ 381 static inline int uv_blade_nr_online_cpus(int bid) 382 { 383 return uv_blade_info[bid].nr_online_cpus; 384 } 385 386 /* Convert a cpu id to the PNODE of the blade containing the cpu */ 387 static inline int uv_cpu_to_pnode(int cpu) 388 { 389 return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode; 390 } 391 392 /* Convert a linux node number to the PNODE of the blade */ 393 static inline int uv_node_to_pnode(int nid) 394 { 395 return uv_blade_info[uv_node_to_blade_id(nid)].pnode; 396 } 397 398 /* Maximum possible number of blades */ 399 static inline int uv_num_possible_blades(void) 400 { 401 return uv_possible_blades; 402 } 403 404 /* Update SCIR state */ 405 static inline void uv_set_scir_bits(unsigned char value) 406 { 407 if (uv_hub_info->scir.state != value) { 408 uv_hub_info->scir.state = value; 409 uv_write_local_mmr8(uv_hub_info->scir.offset, value); 410 } 411 } 412 413 static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value) 414 { 415 if (uv_cpu_hub_info(cpu)->scir.state != value) { 416 uv_cpu_hub_info(cpu)->scir.state = value; 417 uv_write_local_mmr8(uv_cpu_hub_info(cpu)->scir.offset, value); 418 } 419 } 420 421 static inline void uv_hub_send_ipi(int pnode, int apicid, int vector) 422 { 423 unsigned long val; 424 425 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 426 ((apicid) << UVH_IPI_INT_APIC_ID_SHFT) | 427 (vector << UVH_IPI_INT_VECTOR_SHFT); 428 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 429 } 430 431 #endif /* CONFIG_X86_64 */ 432 #endif /* _ASM_X86_UV_UV_HUB_H */ 433