1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * SGI UV architectural definitions 7 * 8 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved. 9 */ 10 11 #ifndef _ASM_X86_UV_UV_HUB_H 12 #define _ASM_X86_UV_UV_HUB_H 13 14 #include <linux/numa.h> 15 #include <linux/percpu.h> 16 #include <linux/timer.h> 17 #include <asm/types.h> 18 #include <asm/percpu.h> 19 20 21 /* 22 * Addressing Terminology 23 * 24 * M - The low M bits of a physical address represent the offset 25 * into the blade local memory. RAM memory on a blade is physically 26 * contiguous (although various IO spaces may punch holes in 27 * it).. 28 * 29 * N - Number of bits in the node portion of a socket physical 30 * address. 31 * 32 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of 33 * routers always have low bit of 1, C/MBricks have low bit 34 * equal to 0. Most addressing macros that target UV hub chips 35 * right shift the NASID by 1 to exclude the always-zero bit. 36 * NASIDs contain up to 15 bits. 37 * 38 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead 39 * of nasids. 40 * 41 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant 42 * of the nasid for socket usage. 43 * 44 * 45 * NumaLink Global Physical Address Format: 46 * +--------------------------------+---------------------+ 47 * |00..000| GNODE | NodeOffset | 48 * +--------------------------------+---------------------+ 49 * |<-------53 - M bits --->|<--------M bits -----> 50 * 51 * M - number of node offset bits (35 .. 40) 52 * 53 * 54 * Memory/UV-HUB Processor Socket Address Format: 55 * +----------------+---------------+---------------------+ 56 * |00..000000000000| PNODE | NodeOffset | 57 * +----------------+---------------+---------------------+ 58 * <--- N bits --->|<--------M bits -----> 59 * 60 * M - number of node offset bits (35 .. 40) 61 * N - number of PNODE bits (0 .. 10) 62 * 63 * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64). 64 * The actual values are configuration dependent and are set at 65 * boot time. M & N values are set by the hardware/BIOS at boot. 66 * 67 * 68 * APICID format 69 * NOTE!!!!!! This is the current format of the APICID. However, code 70 * should assume that this will change in the future. Use functions 71 * in this file for all APICID bit manipulations and conversion. 72 * 73 * 1111110000000000 74 * 5432109876543210 75 * pppppppppplc0cch 76 * sssssssssss 77 * 78 * p = pnode bits 79 * l = socket number on board 80 * c = core 81 * h = hyperthread 82 * s = bits that are in the SOCKET_ID CSR 83 * 84 * Note: Processor only supports 12 bits in the APICID register. The ACPI 85 * tables hold all 16 bits. Software needs to be aware of this. 86 * 87 * Unless otherwise specified, all references to APICID refer to 88 * the FULL value contained in ACPI tables, not the subset in the 89 * processor APICID register. 90 */ 91 92 93 /* 94 * Maximum number of bricks in all partitions and in all coherency domains. 95 * This is the total number of bricks accessible in the numalink fabric. It 96 * includes all C & M bricks. Routers are NOT included. 97 * 98 * This value is also the value of the maximum number of non-router NASIDs 99 * in the numalink fabric. 100 * 101 * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused. 102 */ 103 #define UV_MAX_NUMALINK_BLADES 16384 104 105 /* 106 * Maximum number of C/Mbricks within a software SSI (hardware may support 107 * more). 108 */ 109 #define UV_MAX_SSI_BLADES 256 110 111 /* 112 * The largest possible NASID of a C or M brick (+ 2) 113 */ 114 #define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_NODES * 2) 115 116 struct uv_scir_s { 117 struct timer_list timer; 118 unsigned long offset; 119 unsigned long last; 120 unsigned long idle_on; 121 unsigned long idle_off; 122 unsigned char state; 123 unsigned char enabled; 124 }; 125 126 /* 127 * The following defines attributes of the HUB chip. These attributes are 128 * frequently referenced and are kept in the per-cpu data areas of each cpu. 129 * They are kept together in a struct to minimize cache misses. 130 */ 131 struct uv_hub_info_s { 132 unsigned long global_mmr_base; 133 unsigned long gpa_mask; 134 unsigned long gnode_upper; 135 unsigned long lowmem_remap_top; 136 unsigned long lowmem_remap_base; 137 unsigned short pnode; 138 unsigned short pnode_mask; 139 unsigned short coherency_domain_number; 140 unsigned short numa_blade_id; 141 unsigned char blade_processor_id; 142 unsigned char m_val; 143 unsigned char n_val; 144 struct uv_scir_s scir; 145 }; 146 147 DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); 148 #define uv_hub_info (&__get_cpu_var(__uv_hub_info)) 149 #define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu)) 150 151 /* 152 * Local & Global MMR space macros. 153 * Note: macros are intended to be used ONLY by inline functions 154 * in this file - not by other kernel code. 155 * n - NASID (full 15-bit global nasid) 156 * g - GNODE (full 15-bit global nasid, right shifted 1) 157 * p - PNODE (local part of nsids, right shifted 1) 158 */ 159 #define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask) 160 #define UV_PNODE_TO_NASID(p) (((p) << 1) | uv_hub_info->gnode_upper) 161 162 #define UV_LOCAL_MMR_BASE 0xf4000000UL 163 #define UV_GLOBAL_MMR32_BASE 0xf8000000UL 164 #define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base) 165 #define UV_LOCAL_MMR_SIZE (64UL * 1024 * 1024) 166 #define UV_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024) 167 168 #define UV_GLOBAL_MMR32_PNODE_SHIFT 15 169 #define UV_GLOBAL_MMR64_PNODE_SHIFT 26 170 171 #define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT)) 172 173 #define UV_GLOBAL_MMR64_PNODE_BITS(p) \ 174 ((unsigned long)(p) << UV_GLOBAL_MMR64_PNODE_SHIFT) 175 176 #define UV_APIC_PNODE_SHIFT 6 177 178 /* Local Bus from cpu's perspective */ 179 #define LOCAL_BUS_BASE 0x1c00000 180 #define LOCAL_BUS_SIZE (4 * 1024 * 1024) 181 182 /* 183 * System Controller Interface Reg 184 * 185 * Note there are NO leds on a UV system. This register is only 186 * used by the system controller to monitor system-wide operation. 187 * There are 64 regs per node. With Nahelem cpus (2 cores per node, 188 * 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on 189 * a node. 190 * 191 * The window is located at top of ACPI MMR space 192 */ 193 #define SCIR_WINDOW_COUNT 64 194 #define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \ 195 LOCAL_BUS_SIZE - \ 196 SCIR_WINDOW_COUNT) 197 198 #define SCIR_CPU_HEARTBEAT 0x01 /* timer interrupt */ 199 #define SCIR_CPU_ACTIVITY 0x02 /* not idle */ 200 #define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */ 201 202 /* Loop through all installed blades */ 203 #define for_each_possible_blade(bid) \ 204 for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++) 205 206 /* 207 * Macros for converting between kernel virtual addresses, socket local physical 208 * addresses, and UV global physical addresses. 209 * Note: use the standard __pa() & __va() macros for converting 210 * between socket virtual and socket physical addresses. 211 */ 212 213 /* socket phys RAM --> UV global physical address */ 214 static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr) 215 { 216 if (paddr < uv_hub_info->lowmem_remap_top) 217 paddr |= uv_hub_info->lowmem_remap_base; 218 return paddr | uv_hub_info->gnode_upper; 219 } 220 221 222 /* socket virtual --> UV global physical address */ 223 static inline unsigned long uv_gpa(void *v) 224 { 225 return uv_soc_phys_ram_to_gpa(__pa(v)); 226 } 227 228 /* pnode, offset --> socket virtual */ 229 static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset) 230 { 231 return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset); 232 } 233 234 235 /* 236 * Extract a PNODE from an APICID (full apicid, not processor subset) 237 */ 238 static inline int uv_apicid_to_pnode(int apicid) 239 { 240 return (apicid >> UV_APIC_PNODE_SHIFT); 241 } 242 243 /* 244 * Access global MMRs using the low memory MMR32 space. This region supports 245 * faster MMR access but not all MMRs are accessible in this space. 246 */ 247 static inline unsigned long *uv_global_mmr32_address(int pnode, 248 unsigned long offset) 249 { 250 return __va(UV_GLOBAL_MMR32_BASE | 251 UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset); 252 } 253 254 static inline void uv_write_global_mmr32(int pnode, unsigned long offset, 255 unsigned long val) 256 { 257 *uv_global_mmr32_address(pnode, offset) = val; 258 } 259 260 static inline unsigned long uv_read_global_mmr32(int pnode, 261 unsigned long offset) 262 { 263 return *uv_global_mmr32_address(pnode, offset); 264 } 265 266 /* 267 * Access Global MMR space using the MMR space located at the top of physical 268 * memory. 269 */ 270 static inline unsigned long *uv_global_mmr64_address(int pnode, 271 unsigned long offset) 272 { 273 return __va(UV_GLOBAL_MMR64_BASE | 274 UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset); 275 } 276 277 static inline void uv_write_global_mmr64(int pnode, unsigned long offset, 278 unsigned long val) 279 { 280 *uv_global_mmr64_address(pnode, offset) = val; 281 } 282 283 static inline unsigned long uv_read_global_mmr64(int pnode, 284 unsigned long offset) 285 { 286 return *uv_global_mmr64_address(pnode, offset); 287 } 288 289 /* 290 * Access hub local MMRs. Faster than using global space but only local MMRs 291 * are accessible. 292 */ 293 static inline unsigned long *uv_local_mmr_address(unsigned long offset) 294 { 295 return __va(UV_LOCAL_MMR_BASE | offset); 296 } 297 298 static inline unsigned long uv_read_local_mmr(unsigned long offset) 299 { 300 return *uv_local_mmr_address(offset); 301 } 302 303 static inline void uv_write_local_mmr(unsigned long offset, unsigned long val) 304 { 305 *uv_local_mmr_address(offset) = val; 306 } 307 308 static inline unsigned char uv_read_local_mmr8(unsigned long offset) 309 { 310 return *((unsigned char *)uv_local_mmr_address(offset)); 311 } 312 313 static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val) 314 { 315 *((unsigned char *)uv_local_mmr_address(offset)) = val; 316 } 317 318 /* 319 * Structures and definitions for converting between cpu, node, pnode, and blade 320 * numbers. 321 */ 322 struct uv_blade_info { 323 unsigned short nr_possible_cpus; 324 unsigned short nr_online_cpus; 325 unsigned short pnode; 326 }; 327 extern struct uv_blade_info *uv_blade_info; 328 extern short *uv_node_to_blade; 329 extern short *uv_cpu_to_blade; 330 extern short uv_possible_blades; 331 332 /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */ 333 static inline int uv_blade_processor_id(void) 334 { 335 return uv_hub_info->blade_processor_id; 336 } 337 338 /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */ 339 static inline int uv_numa_blade_id(void) 340 { 341 return uv_hub_info->numa_blade_id; 342 } 343 344 /* Convert a cpu number to the the UV blade number */ 345 static inline int uv_cpu_to_blade_id(int cpu) 346 { 347 return uv_cpu_to_blade[cpu]; 348 } 349 350 /* Convert linux node number to the UV blade number */ 351 static inline int uv_node_to_blade_id(int nid) 352 { 353 return uv_node_to_blade[nid]; 354 } 355 356 /* Convert a blade id to the PNODE of the blade */ 357 static inline int uv_blade_to_pnode(int bid) 358 { 359 return uv_blade_info[bid].pnode; 360 } 361 362 /* Determine the number of possible cpus on a blade */ 363 static inline int uv_blade_nr_possible_cpus(int bid) 364 { 365 return uv_blade_info[bid].nr_possible_cpus; 366 } 367 368 /* Determine the number of online cpus on a blade */ 369 static inline int uv_blade_nr_online_cpus(int bid) 370 { 371 return uv_blade_info[bid].nr_online_cpus; 372 } 373 374 /* Convert a cpu id to the PNODE of the blade containing the cpu */ 375 static inline int uv_cpu_to_pnode(int cpu) 376 { 377 return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode; 378 } 379 380 /* Convert a linux node number to the PNODE of the blade */ 381 static inline int uv_node_to_pnode(int nid) 382 { 383 return uv_blade_info[uv_node_to_blade_id(nid)].pnode; 384 } 385 386 /* Maximum possible number of blades */ 387 static inline int uv_num_possible_blades(void) 388 { 389 return uv_possible_blades; 390 } 391 392 /* Update SCIR state */ 393 static inline void uv_set_scir_bits(unsigned char value) 394 { 395 if (uv_hub_info->scir.state != value) { 396 uv_hub_info->scir.state = value; 397 uv_write_local_mmr8(uv_hub_info->scir.offset, value); 398 } 399 } 400 static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value) 401 { 402 if (uv_cpu_hub_info(cpu)->scir.state != value) { 403 uv_cpu_hub_info(cpu)->scir.state = value; 404 uv_write_local_mmr8(uv_cpu_hub_info(cpu)->scir.offset, value); 405 } 406 } 407 408 #endif /* _ASM_X86_UV_UV_HUB_H */ 409