1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * SGI UV architectural definitions 7 * 8 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved. 9 */ 10 11 #ifndef _ASM_X86_UV_UV_HUB_H 12 #define _ASM_X86_UV_UV_HUB_H 13 14 #ifdef CONFIG_X86_64 15 #include <linux/numa.h> 16 #include <linux/percpu.h> 17 #include <linux/timer.h> 18 #include <asm/types.h> 19 #include <asm/percpu.h> 20 #include <asm/uv/uv_mmrs.h> 21 22 23 /* 24 * Addressing Terminology 25 * 26 * M - The low M bits of a physical address represent the offset 27 * into the blade local memory. RAM memory on a blade is physically 28 * contiguous (although various IO spaces may punch holes in 29 * it).. 30 * 31 * N - Number of bits in the node portion of a socket physical 32 * address. 33 * 34 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of 35 * routers always have low bit of 1, C/MBricks have low bit 36 * equal to 0. Most addressing macros that target UV hub chips 37 * right shift the NASID by 1 to exclude the always-zero bit. 38 * NASIDs contain up to 15 bits. 39 * 40 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead 41 * of nasids. 42 * 43 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant 44 * of the nasid for socket usage. 45 * 46 * 47 * NumaLink Global Physical Address Format: 48 * +--------------------------------+---------------------+ 49 * |00..000| GNODE | NodeOffset | 50 * +--------------------------------+---------------------+ 51 * |<-------53 - M bits --->|<--------M bits -----> 52 * 53 * M - number of node offset bits (35 .. 40) 54 * 55 * 56 * Memory/UV-HUB Processor Socket Address Format: 57 * +----------------+---------------+---------------------+ 58 * |00..000000000000| PNODE | NodeOffset | 59 * +----------------+---------------+---------------------+ 60 * <--- N bits --->|<--------M bits -----> 61 * 62 * M - number of node offset bits (35 .. 40) 63 * N - number of PNODE bits (0 .. 10) 64 * 65 * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64). 66 * The actual values are configuration dependent and are set at 67 * boot time. M & N values are set by the hardware/BIOS at boot. 68 * 69 * 70 * APICID format 71 * NOTE!!!!!! This is the current format of the APICID. However, code 72 * should assume that this will change in the future. Use functions 73 * in this file for all APICID bit manipulations and conversion. 74 * 75 * 1111110000000000 76 * 5432109876543210 77 * pppppppppplc0cch 78 * sssssssssss 79 * 80 * p = pnode bits 81 * l = socket number on board 82 * c = core 83 * h = hyperthread 84 * s = bits that are in the SOCKET_ID CSR 85 * 86 * Note: Processor only supports 12 bits in the APICID register. The ACPI 87 * tables hold all 16 bits. Software needs to be aware of this. 88 * 89 * Unless otherwise specified, all references to APICID refer to 90 * the FULL value contained in ACPI tables, not the subset in the 91 * processor APICID register. 92 */ 93 94 95 /* 96 * Maximum number of bricks in all partitions and in all coherency domains. 97 * This is the total number of bricks accessible in the numalink fabric. It 98 * includes all C & M bricks. Routers are NOT included. 99 * 100 * This value is also the value of the maximum number of non-router NASIDs 101 * in the numalink fabric. 102 * 103 * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused. 104 */ 105 #define UV_MAX_NUMALINK_BLADES 16384 106 107 /* 108 * Maximum number of C/Mbricks within a software SSI (hardware may support 109 * more). 110 */ 111 #define UV_MAX_SSI_BLADES 256 112 113 /* 114 * The largest possible NASID of a C or M brick (+ 2) 115 */ 116 #define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_NODES * 2) 117 118 struct uv_scir_s { 119 struct timer_list timer; 120 unsigned long offset; 121 unsigned long last; 122 unsigned long idle_on; 123 unsigned long idle_off; 124 unsigned char state; 125 unsigned char enabled; 126 }; 127 128 /* 129 * The following defines attributes of the HUB chip. These attributes are 130 * frequently referenced and are kept in the per-cpu data areas of each cpu. 131 * They are kept together in a struct to minimize cache misses. 132 */ 133 struct uv_hub_info_s { 134 unsigned long global_mmr_base; 135 unsigned long gpa_mask; 136 unsigned long gnode_upper; 137 unsigned long lowmem_remap_top; 138 unsigned long lowmem_remap_base; 139 unsigned short pnode; 140 unsigned short pnode_mask; 141 unsigned short coherency_domain_number; 142 unsigned short numa_blade_id; 143 unsigned char blade_processor_id; 144 unsigned char m_val; 145 unsigned char n_val; 146 struct uv_scir_s scir; 147 }; 148 149 DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); 150 #define uv_hub_info (&__get_cpu_var(__uv_hub_info)) 151 #define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu)) 152 153 /* 154 * Local & Global MMR space macros. 155 * Note: macros are intended to be used ONLY by inline functions 156 * in this file - not by other kernel code. 157 * n - NASID (full 15-bit global nasid) 158 * g - GNODE (full 15-bit global nasid, right shifted 1) 159 * p - PNODE (local part of nsids, right shifted 1) 160 */ 161 #define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask) 162 #define UV_PNODE_TO_NASID(p) (((p) << 1) | uv_hub_info->gnode_upper) 163 164 #define UV_LOCAL_MMR_BASE 0xf4000000UL 165 #define UV_GLOBAL_MMR32_BASE 0xf8000000UL 166 #define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base) 167 #define UV_LOCAL_MMR_SIZE (64UL * 1024 * 1024) 168 #define UV_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024) 169 170 #define UV_GLOBAL_MMR32_PNODE_SHIFT 15 171 #define UV_GLOBAL_MMR64_PNODE_SHIFT 26 172 173 #define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT)) 174 175 #define UV_GLOBAL_MMR64_PNODE_BITS(p) \ 176 ((unsigned long)(p) << UV_GLOBAL_MMR64_PNODE_SHIFT) 177 178 #define UV_APIC_PNODE_SHIFT 6 179 180 /* Local Bus from cpu's perspective */ 181 #define LOCAL_BUS_BASE 0x1c00000 182 #define LOCAL_BUS_SIZE (4 * 1024 * 1024) 183 184 /* 185 * System Controller Interface Reg 186 * 187 * Note there are NO leds on a UV system. This register is only 188 * used by the system controller to monitor system-wide operation. 189 * There are 64 regs per node. With Nahelem cpus (2 cores per node, 190 * 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on 191 * a node. 192 * 193 * The window is located at top of ACPI MMR space 194 */ 195 #define SCIR_WINDOW_COUNT 64 196 #define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \ 197 LOCAL_BUS_SIZE - \ 198 SCIR_WINDOW_COUNT) 199 200 #define SCIR_CPU_HEARTBEAT 0x01 /* timer interrupt */ 201 #define SCIR_CPU_ACTIVITY 0x02 /* not idle */ 202 #define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */ 203 204 /* Loop through all installed blades */ 205 #define for_each_possible_blade(bid) \ 206 for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++) 207 208 /* 209 * Macros for converting between kernel virtual addresses, socket local physical 210 * addresses, and UV global physical addresses. 211 * Note: use the standard __pa() & __va() macros for converting 212 * between socket virtual and socket physical addresses. 213 */ 214 215 /* socket phys RAM --> UV global physical address */ 216 static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr) 217 { 218 if (paddr < uv_hub_info->lowmem_remap_top) 219 paddr |= uv_hub_info->lowmem_remap_base; 220 return paddr | uv_hub_info->gnode_upper; 221 } 222 223 224 /* socket virtual --> UV global physical address */ 225 static inline unsigned long uv_gpa(void *v) 226 { 227 return uv_soc_phys_ram_to_gpa(__pa(v)); 228 } 229 230 /* pnode, offset --> socket virtual */ 231 static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset) 232 { 233 return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset); 234 } 235 236 237 /* 238 * Extract a PNODE from an APICID (full apicid, not processor subset) 239 */ 240 static inline int uv_apicid_to_pnode(int apicid) 241 { 242 return (apicid >> UV_APIC_PNODE_SHIFT); 243 } 244 245 /* 246 * Access global MMRs using the low memory MMR32 space. This region supports 247 * faster MMR access but not all MMRs are accessible in this space. 248 */ 249 static inline unsigned long *uv_global_mmr32_address(int pnode, 250 unsigned long offset) 251 { 252 return __va(UV_GLOBAL_MMR32_BASE | 253 UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset); 254 } 255 256 static inline void uv_write_global_mmr32(int pnode, unsigned long offset, 257 unsigned long val) 258 { 259 *uv_global_mmr32_address(pnode, offset) = val; 260 } 261 262 static inline unsigned long uv_read_global_mmr32(int pnode, 263 unsigned long offset) 264 { 265 return *uv_global_mmr32_address(pnode, offset); 266 } 267 268 /* 269 * Access Global MMR space using the MMR space located at the top of physical 270 * memory. 271 */ 272 static inline unsigned long *uv_global_mmr64_address(int pnode, 273 unsigned long offset) 274 { 275 return __va(UV_GLOBAL_MMR64_BASE | 276 UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset); 277 } 278 279 static inline void uv_write_global_mmr64(int pnode, unsigned long offset, 280 unsigned long val) 281 { 282 *uv_global_mmr64_address(pnode, offset) = val; 283 } 284 285 static inline unsigned long uv_read_global_mmr64(int pnode, 286 unsigned long offset) 287 { 288 return *uv_global_mmr64_address(pnode, offset); 289 } 290 291 /* 292 * Access hub local MMRs. Faster than using global space but only local MMRs 293 * are accessible. 294 */ 295 static inline unsigned long *uv_local_mmr_address(unsigned long offset) 296 { 297 return __va(UV_LOCAL_MMR_BASE | offset); 298 } 299 300 static inline unsigned long uv_read_local_mmr(unsigned long offset) 301 { 302 return *uv_local_mmr_address(offset); 303 } 304 305 static inline void uv_write_local_mmr(unsigned long offset, unsigned long val) 306 { 307 *uv_local_mmr_address(offset) = val; 308 } 309 310 static inline unsigned char uv_read_local_mmr8(unsigned long offset) 311 { 312 return *((unsigned char *)uv_local_mmr_address(offset)); 313 } 314 315 static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val) 316 { 317 *((unsigned char *)uv_local_mmr_address(offset)) = val; 318 } 319 320 /* 321 * Structures and definitions for converting between cpu, node, pnode, and blade 322 * numbers. 323 */ 324 struct uv_blade_info { 325 unsigned short nr_possible_cpus; 326 unsigned short nr_online_cpus; 327 unsigned short pnode; 328 }; 329 extern struct uv_blade_info *uv_blade_info; 330 extern short *uv_node_to_blade; 331 extern short *uv_cpu_to_blade; 332 extern short uv_possible_blades; 333 334 /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */ 335 static inline int uv_blade_processor_id(void) 336 { 337 return uv_hub_info->blade_processor_id; 338 } 339 340 /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */ 341 static inline int uv_numa_blade_id(void) 342 { 343 return uv_hub_info->numa_blade_id; 344 } 345 346 /* Convert a cpu number to the the UV blade number */ 347 static inline int uv_cpu_to_blade_id(int cpu) 348 { 349 return uv_cpu_to_blade[cpu]; 350 } 351 352 /* Convert linux node number to the UV blade number */ 353 static inline int uv_node_to_blade_id(int nid) 354 { 355 return uv_node_to_blade[nid]; 356 } 357 358 /* Convert a blade id to the PNODE of the blade */ 359 static inline int uv_blade_to_pnode(int bid) 360 { 361 return uv_blade_info[bid].pnode; 362 } 363 364 /* Determine the number of possible cpus on a blade */ 365 static inline int uv_blade_nr_possible_cpus(int bid) 366 { 367 return uv_blade_info[bid].nr_possible_cpus; 368 } 369 370 /* Determine the number of online cpus on a blade */ 371 static inline int uv_blade_nr_online_cpus(int bid) 372 { 373 return uv_blade_info[bid].nr_online_cpus; 374 } 375 376 /* Convert a cpu id to the PNODE of the blade containing the cpu */ 377 static inline int uv_cpu_to_pnode(int cpu) 378 { 379 return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode; 380 } 381 382 /* Convert a linux node number to the PNODE of the blade */ 383 static inline int uv_node_to_pnode(int nid) 384 { 385 return uv_blade_info[uv_node_to_blade_id(nid)].pnode; 386 } 387 388 /* Maximum possible number of blades */ 389 static inline int uv_num_possible_blades(void) 390 { 391 return uv_possible_blades; 392 } 393 394 /* Update SCIR state */ 395 static inline void uv_set_scir_bits(unsigned char value) 396 { 397 if (uv_hub_info->scir.state != value) { 398 uv_hub_info->scir.state = value; 399 uv_write_local_mmr8(uv_hub_info->scir.offset, value); 400 } 401 } 402 403 static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value) 404 { 405 if (uv_cpu_hub_info(cpu)->scir.state != value) { 406 uv_cpu_hub_info(cpu)->scir.state = value; 407 uv_write_local_mmr8(uv_cpu_hub_info(cpu)->scir.offset, value); 408 } 409 } 410 411 static inline void uv_hub_send_ipi(int pnode, int apicid, int vector) 412 { 413 unsigned long val; 414 415 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 416 ((apicid & 0x3f) << UVH_IPI_INT_APIC_ID_SHFT) | 417 (vector << UVH_IPI_INT_VECTOR_SHFT); 418 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 419 } 420 421 #endif /* CONFIG_X86_64 */ 422 #endif /* _ASM_X86_UV_UV_HUB_H */ 423