1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * SGI UV architectural definitions 7 * 8 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved. 9 */ 10 11 #ifndef _ASM_X86_UV_UV_HUB_H 12 #define _ASM_X86_UV_UV_HUB_H 13 14 #ifdef CONFIG_X86_64 15 #include <linux/numa.h> 16 #include <linux/percpu.h> 17 #include <linux/timer.h> 18 #include <linux/io.h> 19 #include <asm/types.h> 20 #include <asm/percpu.h> 21 #include <asm/uv/uv_mmrs.h> 22 #include <asm/irq_vectors.h> 23 #include <asm/io_apic.h> 24 25 26 /* 27 * Addressing Terminology 28 * 29 * M - The low M bits of a physical address represent the offset 30 * into the blade local memory. RAM memory on a blade is physically 31 * contiguous (although various IO spaces may punch holes in 32 * it).. 33 * 34 * N - Number of bits in the node portion of a socket physical 35 * address. 36 * 37 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of 38 * routers always have low bit of 1, C/MBricks have low bit 39 * equal to 0. Most addressing macros that target UV hub chips 40 * right shift the NASID by 1 to exclude the always-zero bit. 41 * NASIDs contain up to 15 bits. 42 * 43 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead 44 * of nasids. 45 * 46 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant 47 * of the nasid for socket usage. 48 * 49 * 50 * NumaLink Global Physical Address Format: 51 * +--------------------------------+---------------------+ 52 * |00..000| GNODE | NodeOffset | 53 * +--------------------------------+---------------------+ 54 * |<-------53 - M bits --->|<--------M bits -----> 55 * 56 * M - number of node offset bits (35 .. 40) 57 * 58 * 59 * Memory/UV-HUB Processor Socket Address Format: 60 * +----------------+---------------+---------------------+ 61 * |00..000000000000| PNODE | NodeOffset | 62 * +----------------+---------------+---------------------+ 63 * <--- N bits --->|<--------M bits -----> 64 * 65 * M - number of node offset bits (35 .. 40) 66 * N - number of PNODE bits (0 .. 10) 67 * 68 * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64). 69 * The actual values are configuration dependent and are set at 70 * boot time. M & N values are set by the hardware/BIOS at boot. 71 * 72 * 73 * APICID format 74 * NOTE!!!!!! This is the current format of the APICID. However, code 75 * should assume that this will change in the future. Use functions 76 * in this file for all APICID bit manipulations and conversion. 77 * 78 * 1111110000000000 79 * 5432109876543210 80 * pppppppppplc0cch 81 * sssssssssss 82 * 83 * p = pnode bits 84 * l = socket number on board 85 * c = core 86 * h = hyperthread 87 * s = bits that are in the SOCKET_ID CSR 88 * 89 * Note: Processor only supports 12 bits in the APICID register. The ACPI 90 * tables hold all 16 bits. Software needs to be aware of this. 91 * 92 * Unless otherwise specified, all references to APICID refer to 93 * the FULL value contained in ACPI tables, not the subset in the 94 * processor APICID register. 95 */ 96 97 98 /* 99 * Maximum number of bricks in all partitions and in all coherency domains. 100 * This is the total number of bricks accessible in the numalink fabric. It 101 * includes all C & M bricks. Routers are NOT included. 102 * 103 * This value is also the value of the maximum number of non-router NASIDs 104 * in the numalink fabric. 105 * 106 * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused. 107 */ 108 #define UV_MAX_NUMALINK_BLADES 16384 109 110 /* 111 * Maximum number of C/Mbricks within a software SSI (hardware may support 112 * more). 113 */ 114 #define UV_MAX_SSI_BLADES 256 115 116 /* 117 * The largest possible NASID of a C or M brick (+ 2) 118 */ 119 #define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_BLADES * 2) 120 121 struct uv_scir_s { 122 struct timer_list timer; 123 unsigned long offset; 124 unsigned long last; 125 unsigned long idle_on; 126 unsigned long idle_off; 127 unsigned char state; 128 unsigned char enabled; 129 }; 130 131 /* 132 * The following defines attributes of the HUB chip. These attributes are 133 * frequently referenced and are kept in the per-cpu data areas of each cpu. 134 * They are kept together in a struct to minimize cache misses. 135 */ 136 struct uv_hub_info_s { 137 unsigned long global_mmr_base; 138 unsigned long gpa_mask; 139 unsigned int gnode_extra; 140 unsigned long gnode_upper; 141 unsigned long lowmem_remap_top; 142 unsigned long lowmem_remap_base; 143 unsigned short pnode; 144 unsigned short pnode_mask; 145 unsigned short coherency_domain_number; 146 unsigned short numa_blade_id; 147 unsigned char blade_processor_id; 148 unsigned char m_val; 149 unsigned char n_val; 150 struct uv_scir_s scir; 151 }; 152 153 DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); 154 #define uv_hub_info (&__get_cpu_var(__uv_hub_info)) 155 #define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu)) 156 157 /* 158 * Local & Global MMR space macros. 159 * Note: macros are intended to be used ONLY by inline functions 160 * in this file - not by other kernel code. 161 * n - NASID (full 15-bit global nasid) 162 * g - GNODE (full 15-bit global nasid, right shifted 1) 163 * p - PNODE (local part of nsids, right shifted 1) 164 */ 165 #define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask) 166 #define UV_PNODE_TO_GNODE(p) ((p) |uv_hub_info->gnode_extra) 167 #define UV_PNODE_TO_NASID(p) (UV_PNODE_TO_GNODE(p) << 1) 168 169 #define UV_LOCAL_MMR_BASE 0xf4000000UL 170 #define UV_GLOBAL_MMR32_BASE 0xf8000000UL 171 #define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base) 172 #define UV_LOCAL_MMR_SIZE (64UL * 1024 * 1024) 173 #define UV_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024) 174 175 #define UV_GLOBAL_GRU_MMR_BASE 0x4000000 176 177 #define UV_GLOBAL_MMR32_PNODE_SHIFT 15 178 #define UV_GLOBAL_MMR64_PNODE_SHIFT 26 179 180 #define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT)) 181 182 #define UV_GLOBAL_MMR64_PNODE_BITS(p) \ 183 (((unsigned long)(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT) 184 185 #define UV_APIC_PNODE_SHIFT 6 186 187 /* Local Bus from cpu's perspective */ 188 #define LOCAL_BUS_BASE 0x1c00000 189 #define LOCAL_BUS_SIZE (4 * 1024 * 1024) 190 191 /* 192 * System Controller Interface Reg 193 * 194 * Note there are NO leds on a UV system. This register is only 195 * used by the system controller to monitor system-wide operation. 196 * There are 64 regs per node. With Nahelem cpus (2 cores per node, 197 * 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on 198 * a node. 199 * 200 * The window is located at top of ACPI MMR space 201 */ 202 #define SCIR_WINDOW_COUNT 64 203 #define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \ 204 LOCAL_BUS_SIZE - \ 205 SCIR_WINDOW_COUNT) 206 207 #define SCIR_CPU_HEARTBEAT 0x01 /* timer interrupt */ 208 #define SCIR_CPU_ACTIVITY 0x02 /* not idle */ 209 #define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */ 210 211 /* Loop through all installed blades */ 212 #define for_each_possible_blade(bid) \ 213 for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++) 214 215 /* 216 * Macros for converting between kernel virtual addresses, socket local physical 217 * addresses, and UV global physical addresses. 218 * Note: use the standard __pa() & __va() macros for converting 219 * between socket virtual and socket physical addresses. 220 */ 221 222 /* socket phys RAM --> UV global physical address */ 223 static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr) 224 { 225 if (paddr < uv_hub_info->lowmem_remap_top) 226 paddr |= uv_hub_info->lowmem_remap_base; 227 return paddr | uv_hub_info->gnode_upper; 228 } 229 230 231 /* socket virtual --> UV global physical address */ 232 static inline unsigned long uv_gpa(void *v) 233 { 234 return uv_soc_phys_ram_to_gpa(__pa(v)); 235 } 236 237 /* Top two bits indicate the requested address is in MMR space. */ 238 static inline int 239 uv_gpa_in_mmr_space(unsigned long gpa) 240 { 241 return (gpa >> 62) == 0x3UL; 242 } 243 244 /* UV global physical address --> socket phys RAM */ 245 static inline unsigned long uv_gpa_to_soc_phys_ram(unsigned long gpa) 246 { 247 unsigned long paddr = gpa & uv_hub_info->gpa_mask; 248 unsigned long remap_base = uv_hub_info->lowmem_remap_base; 249 unsigned long remap_top = uv_hub_info->lowmem_remap_top; 250 251 if (paddr >= remap_base && paddr < remap_base + remap_top) 252 paddr -= remap_base; 253 return paddr; 254 } 255 256 257 /* gnode -> pnode */ 258 static inline unsigned long uv_gpa_to_gnode(unsigned long gpa) 259 { 260 return gpa >> uv_hub_info->m_val; 261 } 262 263 /* gpa -> pnode */ 264 static inline int uv_gpa_to_pnode(unsigned long gpa) 265 { 266 unsigned long n_mask = (1UL << uv_hub_info->n_val) - 1; 267 268 return uv_gpa_to_gnode(gpa) & n_mask; 269 } 270 271 /* pnode, offset --> socket virtual */ 272 static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset) 273 { 274 return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset); 275 } 276 277 278 /* 279 * Extract a PNODE from an APICID (full apicid, not processor subset) 280 */ 281 static inline int uv_apicid_to_pnode(int apicid) 282 { 283 return (apicid >> UV_APIC_PNODE_SHIFT); 284 } 285 286 /* 287 * Access global MMRs using the low memory MMR32 space. This region supports 288 * faster MMR access but not all MMRs are accessible in this space. 289 */ 290 static inline unsigned long *uv_global_mmr32_address(int pnode, unsigned long offset) 291 { 292 return __va(UV_GLOBAL_MMR32_BASE | 293 UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset); 294 } 295 296 static inline void uv_write_global_mmr32(int pnode, unsigned long offset, unsigned long val) 297 { 298 writeq(val, uv_global_mmr32_address(pnode, offset)); 299 } 300 301 static inline unsigned long uv_read_global_mmr32(int pnode, unsigned long offset) 302 { 303 return readq(uv_global_mmr32_address(pnode, offset)); 304 } 305 306 /* 307 * Access Global MMR space using the MMR space located at the top of physical 308 * memory. 309 */ 310 static inline unsigned long *uv_global_mmr64_address(int pnode, unsigned long offset) 311 { 312 return __va(UV_GLOBAL_MMR64_BASE | 313 UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset); 314 } 315 316 static inline void uv_write_global_mmr64(int pnode, unsigned long offset, unsigned long val) 317 { 318 writeq(val, uv_global_mmr64_address(pnode, offset)); 319 } 320 321 static inline unsigned long uv_read_global_mmr64(int pnode, unsigned long offset) 322 { 323 return readq(uv_global_mmr64_address(pnode, offset)); 324 } 325 326 /* 327 * Global MMR space addresses when referenced by the GRU. (GRU does 328 * NOT use socket addressing). 329 */ 330 static inline unsigned long uv_global_gru_mmr_address(int pnode, unsigned long offset) 331 { 332 return UV_GLOBAL_GRU_MMR_BASE | offset | 333 ((unsigned long)pnode << uv_hub_info->m_val); 334 } 335 336 static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val) 337 { 338 writeb(val, uv_global_mmr64_address(pnode, offset)); 339 } 340 341 static inline unsigned char uv_read_global_mmr8(int pnode, unsigned long offset) 342 { 343 return readb(uv_global_mmr64_address(pnode, offset)); 344 } 345 346 /* 347 * Access hub local MMRs. Faster than using global space but only local MMRs 348 * are accessible. 349 */ 350 static inline unsigned long *uv_local_mmr_address(unsigned long offset) 351 { 352 return __va(UV_LOCAL_MMR_BASE | offset); 353 } 354 355 static inline unsigned long uv_read_local_mmr(unsigned long offset) 356 { 357 return readq(uv_local_mmr_address(offset)); 358 } 359 360 static inline void uv_write_local_mmr(unsigned long offset, unsigned long val) 361 { 362 writeq(val, uv_local_mmr_address(offset)); 363 } 364 365 static inline unsigned char uv_read_local_mmr8(unsigned long offset) 366 { 367 return readb(uv_local_mmr_address(offset)); 368 } 369 370 static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val) 371 { 372 writeb(val, uv_local_mmr_address(offset)); 373 } 374 375 /* 376 * Structures and definitions for converting between cpu, node, pnode, and blade 377 * numbers. 378 */ 379 struct uv_blade_info { 380 unsigned short nr_possible_cpus; 381 unsigned short nr_online_cpus; 382 unsigned short pnode; 383 short memory_nid; 384 }; 385 extern struct uv_blade_info *uv_blade_info; 386 extern short *uv_node_to_blade; 387 extern short *uv_cpu_to_blade; 388 extern short uv_possible_blades; 389 390 /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */ 391 static inline int uv_blade_processor_id(void) 392 { 393 return uv_hub_info->blade_processor_id; 394 } 395 396 /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */ 397 static inline int uv_numa_blade_id(void) 398 { 399 return uv_hub_info->numa_blade_id; 400 } 401 402 /* Convert a cpu number to the the UV blade number */ 403 static inline int uv_cpu_to_blade_id(int cpu) 404 { 405 return uv_cpu_to_blade[cpu]; 406 } 407 408 /* Convert linux node number to the UV blade number */ 409 static inline int uv_node_to_blade_id(int nid) 410 { 411 return uv_node_to_blade[nid]; 412 } 413 414 /* Convert a blade id to the PNODE of the blade */ 415 static inline int uv_blade_to_pnode(int bid) 416 { 417 return uv_blade_info[bid].pnode; 418 } 419 420 /* Nid of memory node on blade. -1 if no blade-local memory */ 421 static inline int uv_blade_to_memory_nid(int bid) 422 { 423 return uv_blade_info[bid].memory_nid; 424 } 425 426 /* Determine the number of possible cpus on a blade */ 427 static inline int uv_blade_nr_possible_cpus(int bid) 428 { 429 return uv_blade_info[bid].nr_possible_cpus; 430 } 431 432 /* Determine the number of online cpus on a blade */ 433 static inline int uv_blade_nr_online_cpus(int bid) 434 { 435 return uv_blade_info[bid].nr_online_cpus; 436 } 437 438 /* Convert a cpu id to the PNODE of the blade containing the cpu */ 439 static inline int uv_cpu_to_pnode(int cpu) 440 { 441 return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode; 442 } 443 444 /* Convert a linux node number to the PNODE of the blade */ 445 static inline int uv_node_to_pnode(int nid) 446 { 447 return uv_blade_info[uv_node_to_blade_id(nid)].pnode; 448 } 449 450 /* Maximum possible number of blades */ 451 static inline int uv_num_possible_blades(void) 452 { 453 return uv_possible_blades; 454 } 455 456 /* Update SCIR state */ 457 static inline void uv_set_scir_bits(unsigned char value) 458 { 459 if (uv_hub_info->scir.state != value) { 460 uv_hub_info->scir.state = value; 461 uv_write_local_mmr8(uv_hub_info->scir.offset, value); 462 } 463 } 464 465 static inline unsigned long uv_scir_offset(int apicid) 466 { 467 return SCIR_LOCAL_MMR_BASE | (apicid & 0x3f); 468 } 469 470 static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value) 471 { 472 if (uv_cpu_hub_info(cpu)->scir.state != value) { 473 uv_write_global_mmr8(uv_cpu_to_pnode(cpu), 474 uv_cpu_hub_info(cpu)->scir.offset, value); 475 uv_cpu_hub_info(cpu)->scir.state = value; 476 } 477 } 478 479 static unsigned long uv_hub_ipi_value(int apicid, int vector, int mode) 480 { 481 return (1UL << UVH_IPI_INT_SEND_SHFT) | 482 ((apicid) << UVH_IPI_INT_APIC_ID_SHFT) | 483 (mode << UVH_IPI_INT_DELIVERY_MODE_SHFT) | 484 (vector << UVH_IPI_INT_VECTOR_SHFT); 485 } 486 487 static inline void uv_hub_send_ipi(int pnode, int apicid, int vector) 488 { 489 unsigned long val; 490 unsigned long dmode = dest_Fixed; 491 492 if (vector == NMI_VECTOR) 493 dmode = dest_NMI; 494 495 val = uv_hub_ipi_value(apicid, vector, dmode); 496 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 497 } 498 499 /* 500 * Get the minimum revision number of the hub chips within the partition. 501 * 1 - initial rev 1.0 silicon 502 * 2 - rev 2.0 production silicon 503 */ 504 static inline int uv_get_min_hub_revision_id(void) 505 { 506 extern int uv_min_hub_revision_id; 507 508 return uv_min_hub_revision_id; 509 } 510 511 #endif /* CONFIG_X86_64 */ 512 #endif /* _ASM_X86_UV_UV_HUB_H */ 513