1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * SGI UV architectural definitions 7 * 8 * Copyright (C) 2007-2010 Silicon Graphics, Inc. All rights reserved. 9 */ 10 11 #ifndef _ASM_X86_UV_UV_HUB_H 12 #define _ASM_X86_UV_UV_HUB_H 13 14 #ifdef CONFIG_X86_64 15 #include <linux/numa.h> 16 #include <linux/percpu.h> 17 #include <linux/timer.h> 18 #include <linux/io.h> 19 #include <asm/types.h> 20 #include <asm/percpu.h> 21 #include <asm/uv/uv_mmrs.h> 22 #include <asm/irq_vectors.h> 23 #include <asm/io_apic.h> 24 25 26 /* 27 * Addressing Terminology 28 * 29 * M - The low M bits of a physical address represent the offset 30 * into the blade local memory. RAM memory on a blade is physically 31 * contiguous (although various IO spaces may punch holes in 32 * it).. 33 * 34 * N - Number of bits in the node portion of a socket physical 35 * address. 36 * 37 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of 38 * routers always have low bit of 1, C/MBricks have low bit 39 * equal to 0. Most addressing macros that target UV hub chips 40 * right shift the NASID by 1 to exclude the always-zero bit. 41 * NASIDs contain up to 15 bits. 42 * 43 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead 44 * of nasids. 45 * 46 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant 47 * of the nasid for socket usage. 48 * 49 * 50 * NumaLink Global Physical Address Format: 51 * +--------------------------------+---------------------+ 52 * |00..000| GNODE | NodeOffset | 53 * +--------------------------------+---------------------+ 54 * |<-------53 - M bits --->|<--------M bits -----> 55 * 56 * M - number of node offset bits (35 .. 40) 57 * 58 * 59 * Memory/UV-HUB Processor Socket Address Format: 60 * +----------------+---------------+---------------------+ 61 * |00..000000000000| PNODE | NodeOffset | 62 * +----------------+---------------+---------------------+ 63 * <--- N bits --->|<--------M bits -----> 64 * 65 * M - number of node offset bits (35 .. 40) 66 * N - number of PNODE bits (0 .. 10) 67 * 68 * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64). 69 * The actual values are configuration dependent and are set at 70 * boot time. M & N values are set by the hardware/BIOS at boot. 71 * 72 * 73 * APICID format 74 * NOTE!!!!!! This is the current format of the APICID. However, code 75 * should assume that this will change in the future. Use functions 76 * in this file for all APICID bit manipulations and conversion. 77 * 78 * 1111110000000000 79 * 5432109876543210 80 * pppppppppplc0cch Nehalem-EX (12 bits in hdw reg) 81 * ppppppppplcc0cch Westmere-EX (12 bits in hdw reg) 82 * pppppppppppcccch SandyBridge (15 bits in hdw reg) 83 * sssssssssss 84 * 85 * p = pnode bits 86 * l = socket number on board 87 * c = core 88 * h = hyperthread 89 * s = bits that are in the SOCKET_ID CSR 90 * 91 * Note: Processor may support fewer bits in the APICID register. The ACPI 92 * tables hold all 16 bits. Software needs to be aware of this. 93 * 94 * Unless otherwise specified, all references to APICID refer to 95 * the FULL value contained in ACPI tables, not the subset in the 96 * processor APICID register. 97 */ 98 99 100 /* 101 * Maximum number of bricks in all partitions and in all coherency domains. 102 * This is the total number of bricks accessible in the numalink fabric. It 103 * includes all C & M bricks. Routers are NOT included. 104 * 105 * This value is also the value of the maximum number of non-router NASIDs 106 * in the numalink fabric. 107 * 108 * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused. 109 */ 110 #define UV_MAX_NUMALINK_BLADES 16384 111 112 /* 113 * Maximum number of C/Mbricks within a software SSI (hardware may support 114 * more). 115 */ 116 #define UV_MAX_SSI_BLADES 256 117 118 /* 119 * The largest possible NASID of a C or M brick (+ 2) 120 */ 121 #define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_BLADES * 2) 122 123 struct uv_scir_s { 124 struct timer_list timer; 125 unsigned long offset; 126 unsigned long last; 127 unsigned long idle_on; 128 unsigned long idle_off; 129 unsigned char state; 130 unsigned char enabled; 131 }; 132 133 /* 134 * The following defines attributes of the HUB chip. These attributes are 135 * frequently referenced and are kept in the per-cpu data areas of each cpu. 136 * They are kept together in a struct to minimize cache misses. 137 */ 138 struct uv_hub_info_s { 139 unsigned long global_mmr_base; 140 unsigned long gpa_mask; 141 unsigned int gnode_extra; 142 unsigned char hub_revision; 143 unsigned char apic_pnode_shift; 144 unsigned long gnode_upper; 145 unsigned long lowmem_remap_top; 146 unsigned long lowmem_remap_base; 147 unsigned short pnode; 148 unsigned short pnode_mask; 149 unsigned short coherency_domain_number; 150 unsigned short numa_blade_id; 151 unsigned char blade_processor_id; 152 unsigned char m_val; 153 unsigned char n_val; 154 struct uv_scir_s scir; 155 }; 156 157 DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); 158 #define uv_hub_info (&__get_cpu_var(__uv_hub_info)) 159 #define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu)) 160 161 /* 162 * Hub revisions less than UV2_HUB_REVISION_BASE are UV1 hubs. All UV2 163 * hubs have revision numbers greater than or equal to UV2_HUB_REVISION_BASE. 164 * This is a software convention - NOT the hardware revision numbers in 165 * the hub chip. 166 */ 167 #define UV1_HUB_REVISION_BASE 1 168 #define UV2_HUB_REVISION_BASE 3 169 170 static inline int is_uv1_hub(void) 171 { 172 return uv_hub_info->hub_revision < UV2_HUB_REVISION_BASE; 173 } 174 175 static inline int is_uv2_hub(void) 176 { 177 return uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE; 178 } 179 180 union uvh_apicid { 181 unsigned long v; 182 struct uvh_apicid_s { 183 unsigned long local_apic_mask : 24; 184 unsigned long local_apic_shift : 5; 185 unsigned long unused1 : 3; 186 unsigned long pnode_mask : 24; 187 unsigned long pnode_shift : 5; 188 unsigned long unused2 : 3; 189 } s; 190 }; 191 192 /* 193 * Local & Global MMR space macros. 194 * Note: macros are intended to be used ONLY by inline functions 195 * in this file - not by other kernel code. 196 * n - NASID (full 15-bit global nasid) 197 * g - GNODE (full 15-bit global nasid, right shifted 1) 198 * p - PNODE (local part of nsids, right shifted 1) 199 */ 200 #define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask) 201 #define UV_PNODE_TO_GNODE(p) ((p) |uv_hub_info->gnode_extra) 202 #define UV_PNODE_TO_NASID(p) (UV_PNODE_TO_GNODE(p) << 1) 203 204 #define UV1_LOCAL_MMR_BASE 0xf4000000UL 205 #define UV1_GLOBAL_MMR32_BASE 0xf8000000UL 206 #define UV1_LOCAL_MMR_SIZE (64UL * 1024 * 1024) 207 #define UV1_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024) 208 209 #define UV2_LOCAL_MMR_BASE 0xfa000000UL 210 #define UV2_GLOBAL_MMR32_BASE 0xfc000000UL 211 #define UV2_LOCAL_MMR_SIZE (32UL * 1024 * 1024) 212 #define UV2_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024) 213 214 #define UV_LOCAL_MMR_BASE (is_uv1_hub() ? UV1_LOCAL_MMR_BASE \ 215 : UV2_LOCAL_MMR_BASE) 216 #define UV_GLOBAL_MMR32_BASE (is_uv1_hub() ? UV1_GLOBAL_MMR32_BASE \ 217 : UV2_GLOBAL_MMR32_BASE) 218 #define UV_LOCAL_MMR_SIZE (is_uv1_hub() ? UV1_LOCAL_MMR_SIZE : \ 219 UV2_LOCAL_MMR_SIZE) 220 #define UV_GLOBAL_MMR32_SIZE (is_uv1_hub() ? UV1_GLOBAL_MMR32_SIZE :\ 221 UV2_GLOBAL_MMR32_SIZE) 222 #define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base) 223 224 #define UV_GLOBAL_GRU_MMR_BASE 0x4000000 225 226 #define UV_GLOBAL_MMR32_PNODE_SHIFT 15 227 #define UV_GLOBAL_MMR64_PNODE_SHIFT 26 228 229 #define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT)) 230 231 #define UV_GLOBAL_MMR64_PNODE_BITS(p) \ 232 (((unsigned long)(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT) 233 234 #define UVH_APICID 0x002D0E00L 235 #define UV_APIC_PNODE_SHIFT 6 236 237 #define UV_APICID_HIBIT_MASK 0xffff0000 238 239 /* Local Bus from cpu's perspective */ 240 #define LOCAL_BUS_BASE 0x1c00000 241 #define LOCAL_BUS_SIZE (4 * 1024 * 1024) 242 243 /* 244 * System Controller Interface Reg 245 * 246 * Note there are NO leds on a UV system. This register is only 247 * used by the system controller to monitor system-wide operation. 248 * There are 64 regs per node. With Nahelem cpus (2 cores per node, 249 * 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on 250 * a node. 251 * 252 * The window is located at top of ACPI MMR space 253 */ 254 #define SCIR_WINDOW_COUNT 64 255 #define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \ 256 LOCAL_BUS_SIZE - \ 257 SCIR_WINDOW_COUNT) 258 259 #define SCIR_CPU_HEARTBEAT 0x01 /* timer interrupt */ 260 #define SCIR_CPU_ACTIVITY 0x02 /* not idle */ 261 #define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */ 262 263 /* Loop through all installed blades */ 264 #define for_each_possible_blade(bid) \ 265 for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++) 266 267 /* 268 * Macros for converting between kernel virtual addresses, socket local physical 269 * addresses, and UV global physical addresses. 270 * Note: use the standard __pa() & __va() macros for converting 271 * between socket virtual and socket physical addresses. 272 */ 273 274 /* socket phys RAM --> UV global physical address */ 275 static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr) 276 { 277 if (paddr < uv_hub_info->lowmem_remap_top) 278 paddr |= uv_hub_info->lowmem_remap_base; 279 return paddr | uv_hub_info->gnode_upper; 280 } 281 282 283 /* socket virtual --> UV global physical address */ 284 static inline unsigned long uv_gpa(void *v) 285 { 286 return uv_soc_phys_ram_to_gpa(__pa(v)); 287 } 288 289 /* Top two bits indicate the requested address is in MMR space. */ 290 static inline int 291 uv_gpa_in_mmr_space(unsigned long gpa) 292 { 293 return (gpa >> 62) == 0x3UL; 294 } 295 296 /* UV global physical address --> socket phys RAM */ 297 static inline unsigned long uv_gpa_to_soc_phys_ram(unsigned long gpa) 298 { 299 unsigned long paddr = gpa & uv_hub_info->gpa_mask; 300 unsigned long remap_base = uv_hub_info->lowmem_remap_base; 301 unsigned long remap_top = uv_hub_info->lowmem_remap_top; 302 303 if (paddr >= remap_base && paddr < remap_base + remap_top) 304 paddr -= remap_base; 305 return paddr; 306 } 307 308 309 /* gnode -> pnode */ 310 static inline unsigned long uv_gpa_to_gnode(unsigned long gpa) 311 { 312 return gpa >> uv_hub_info->m_val; 313 } 314 315 /* gpa -> pnode */ 316 static inline int uv_gpa_to_pnode(unsigned long gpa) 317 { 318 unsigned long n_mask = (1UL << uv_hub_info->n_val) - 1; 319 320 return uv_gpa_to_gnode(gpa) & n_mask; 321 } 322 323 /* pnode, offset --> socket virtual */ 324 static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset) 325 { 326 return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset); 327 } 328 329 330 /* 331 * Extract a PNODE from an APICID (full apicid, not processor subset) 332 */ 333 static inline int uv_apicid_to_pnode(int apicid) 334 { 335 return (apicid >> uv_hub_info->apic_pnode_shift); 336 } 337 338 /* 339 * Convert an apicid to the socket number on the blade 340 */ 341 static inline int uv_apicid_to_socket(int apicid) 342 { 343 if (is_uv1_hub()) 344 return (apicid >> (uv_hub_info->apic_pnode_shift - 1)) & 1; 345 else 346 return 0; 347 } 348 349 /* 350 * Access global MMRs using the low memory MMR32 space. This region supports 351 * faster MMR access but not all MMRs are accessible in this space. 352 */ 353 static inline unsigned long *uv_global_mmr32_address(int pnode, unsigned long offset) 354 { 355 return __va(UV_GLOBAL_MMR32_BASE | 356 UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset); 357 } 358 359 static inline void uv_write_global_mmr32(int pnode, unsigned long offset, unsigned long val) 360 { 361 writeq(val, uv_global_mmr32_address(pnode, offset)); 362 } 363 364 static inline unsigned long uv_read_global_mmr32(int pnode, unsigned long offset) 365 { 366 return readq(uv_global_mmr32_address(pnode, offset)); 367 } 368 369 /* 370 * Access Global MMR space using the MMR space located at the top of physical 371 * memory. 372 */ 373 static inline volatile void __iomem *uv_global_mmr64_address(int pnode, unsigned long offset) 374 { 375 return __va(UV_GLOBAL_MMR64_BASE | 376 UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset); 377 } 378 379 static inline void uv_write_global_mmr64(int pnode, unsigned long offset, unsigned long val) 380 { 381 writeq(val, uv_global_mmr64_address(pnode, offset)); 382 } 383 384 static inline unsigned long uv_read_global_mmr64(int pnode, unsigned long offset) 385 { 386 return readq(uv_global_mmr64_address(pnode, offset)); 387 } 388 389 /* 390 * Global MMR space addresses when referenced by the GRU. (GRU does 391 * NOT use socket addressing). 392 */ 393 static inline unsigned long uv_global_gru_mmr_address(int pnode, unsigned long offset) 394 { 395 return UV_GLOBAL_GRU_MMR_BASE | offset | 396 ((unsigned long)pnode << uv_hub_info->m_val); 397 } 398 399 static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val) 400 { 401 writeb(val, uv_global_mmr64_address(pnode, offset)); 402 } 403 404 static inline unsigned char uv_read_global_mmr8(int pnode, unsigned long offset) 405 { 406 return readb(uv_global_mmr64_address(pnode, offset)); 407 } 408 409 /* 410 * Access hub local MMRs. Faster than using global space but only local MMRs 411 * are accessible. 412 */ 413 static inline unsigned long *uv_local_mmr_address(unsigned long offset) 414 { 415 return __va(UV_LOCAL_MMR_BASE | offset); 416 } 417 418 static inline unsigned long uv_read_local_mmr(unsigned long offset) 419 { 420 return readq(uv_local_mmr_address(offset)); 421 } 422 423 static inline void uv_write_local_mmr(unsigned long offset, unsigned long val) 424 { 425 writeq(val, uv_local_mmr_address(offset)); 426 } 427 428 static inline unsigned char uv_read_local_mmr8(unsigned long offset) 429 { 430 return readb(uv_local_mmr_address(offset)); 431 } 432 433 static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val) 434 { 435 writeb(val, uv_local_mmr_address(offset)); 436 } 437 438 /* 439 * Structures and definitions for converting between cpu, node, pnode, and blade 440 * numbers. 441 */ 442 struct uv_blade_info { 443 unsigned short nr_possible_cpus; 444 unsigned short nr_online_cpus; 445 unsigned short pnode; 446 short memory_nid; 447 spinlock_t nmi_lock; 448 unsigned long nmi_count; 449 }; 450 extern struct uv_blade_info *uv_blade_info; 451 extern short *uv_node_to_blade; 452 extern short *uv_cpu_to_blade; 453 extern short uv_possible_blades; 454 455 /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */ 456 static inline int uv_blade_processor_id(void) 457 { 458 return uv_hub_info->blade_processor_id; 459 } 460 461 /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */ 462 static inline int uv_numa_blade_id(void) 463 { 464 return uv_hub_info->numa_blade_id; 465 } 466 467 /* Convert a cpu number to the the UV blade number */ 468 static inline int uv_cpu_to_blade_id(int cpu) 469 { 470 return uv_cpu_to_blade[cpu]; 471 } 472 473 /* Convert linux node number to the UV blade number */ 474 static inline int uv_node_to_blade_id(int nid) 475 { 476 return uv_node_to_blade[nid]; 477 } 478 479 /* Convert a blade id to the PNODE of the blade */ 480 static inline int uv_blade_to_pnode(int bid) 481 { 482 return uv_blade_info[bid].pnode; 483 } 484 485 /* Nid of memory node on blade. -1 if no blade-local memory */ 486 static inline int uv_blade_to_memory_nid(int bid) 487 { 488 return uv_blade_info[bid].memory_nid; 489 } 490 491 /* Determine the number of possible cpus on a blade */ 492 static inline int uv_blade_nr_possible_cpus(int bid) 493 { 494 return uv_blade_info[bid].nr_possible_cpus; 495 } 496 497 /* Determine the number of online cpus on a blade */ 498 static inline int uv_blade_nr_online_cpus(int bid) 499 { 500 return uv_blade_info[bid].nr_online_cpus; 501 } 502 503 /* Convert a cpu id to the PNODE of the blade containing the cpu */ 504 static inline int uv_cpu_to_pnode(int cpu) 505 { 506 return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode; 507 } 508 509 /* Convert a linux node number to the PNODE of the blade */ 510 static inline int uv_node_to_pnode(int nid) 511 { 512 return uv_blade_info[uv_node_to_blade_id(nid)].pnode; 513 } 514 515 /* Maximum possible number of blades */ 516 static inline int uv_num_possible_blades(void) 517 { 518 return uv_possible_blades; 519 } 520 521 /* Update SCIR state */ 522 static inline void uv_set_scir_bits(unsigned char value) 523 { 524 if (uv_hub_info->scir.state != value) { 525 uv_hub_info->scir.state = value; 526 uv_write_local_mmr8(uv_hub_info->scir.offset, value); 527 } 528 } 529 530 static inline unsigned long uv_scir_offset(int apicid) 531 { 532 return SCIR_LOCAL_MMR_BASE | (apicid & 0x3f); 533 } 534 535 static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value) 536 { 537 if (uv_cpu_hub_info(cpu)->scir.state != value) { 538 uv_write_global_mmr8(uv_cpu_to_pnode(cpu), 539 uv_cpu_hub_info(cpu)->scir.offset, value); 540 uv_cpu_hub_info(cpu)->scir.state = value; 541 } 542 } 543 544 extern unsigned int uv_apicid_hibits; 545 static unsigned long uv_hub_ipi_value(int apicid, int vector, int mode) 546 { 547 apicid |= uv_apicid_hibits; 548 return (1UL << UVH_IPI_INT_SEND_SHFT) | 549 ((apicid) << UVH_IPI_INT_APIC_ID_SHFT) | 550 (mode << UVH_IPI_INT_DELIVERY_MODE_SHFT) | 551 (vector << UVH_IPI_INT_VECTOR_SHFT); 552 } 553 554 static inline void uv_hub_send_ipi(int pnode, int apicid, int vector) 555 { 556 unsigned long val; 557 unsigned long dmode = dest_Fixed; 558 559 if (vector == NMI_VECTOR) 560 dmode = dest_NMI; 561 562 val = uv_hub_ipi_value(apicid, vector, dmode); 563 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 564 } 565 566 /* 567 * Get the minimum revision number of the hub chips within the partition. 568 * 1 - UV1 rev 1.0 initial silicon 569 * 2 - UV1 rev 2.0 production silicon 570 * 3 - UV2 rev 1.0 initial silicon 571 */ 572 static inline int uv_get_min_hub_revision_id(void) 573 { 574 return uv_hub_info->hub_revision; 575 } 576 577 #endif /* CONFIG_X86_64 */ 578 #endif /* _ASM_X86_UV_UV_HUB_H */ 579