1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * SGI UV architectural definitions 7 * 8 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved. 9 */ 10 11 #ifndef _ASM_X86_UV_UV_HUB_H 12 #define _ASM_X86_UV_UV_HUB_H 13 14 #ifdef CONFIG_X86_64 15 #include <linux/numa.h> 16 #include <linux/percpu.h> 17 #include <linux/timer.h> 18 #include <linux/io.h> 19 #include <linux/topology.h> 20 #include <asm/types.h> 21 #include <asm/percpu.h> 22 #include <asm/uv/uv.h> 23 #include <asm/uv/uv_mmrs.h> 24 #include <asm/uv/bios.h> 25 #include <asm/irq_vectors.h> 26 #include <asm/io_apic.h> 27 28 29 /* 30 * Addressing Terminology 31 * 32 * M - The low M bits of a physical address represent the offset 33 * into the blade local memory. RAM memory on a blade is physically 34 * contiguous (although various IO spaces may punch holes in 35 * it).. 36 * 37 * N - Number of bits in the node portion of a socket physical 38 * address. 39 * 40 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of 41 * routers always have low bit of 1, C/MBricks have low bit 42 * equal to 0. Most addressing macros that target UV hub chips 43 * right shift the NASID by 1 to exclude the always-zero bit. 44 * NASIDs contain up to 15 bits. 45 * 46 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead 47 * of nasids. 48 * 49 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant 50 * of the nasid for socket usage. 51 * 52 * GPA - (global physical address) a socket physical address converted 53 * so that it can be used by the GRU as a global address. Socket 54 * physical addresses 1) need additional NASID (node) bits added 55 * to the high end of the address, and 2) unaliased if the 56 * partition does not have a physical address 0. In addition, on 57 * UV2 rev 1, GPAs need the gnode left shifted to bits 39 or 40. 58 * 59 * 60 * NumaLink Global Physical Address Format: 61 * +--------------------------------+---------------------+ 62 * |00..000| GNODE | NodeOffset | 63 * +--------------------------------+---------------------+ 64 * |<-------53 - M bits --->|<--------M bits -----> 65 * 66 * M - number of node offset bits (35 .. 40) 67 * 68 * 69 * Memory/UV-HUB Processor Socket Address Format: 70 * +----------------+---------------+---------------------+ 71 * |00..000000000000| PNODE | NodeOffset | 72 * +----------------+---------------+---------------------+ 73 * <--- N bits --->|<--------M bits -----> 74 * 75 * M - number of node offset bits (35 .. 40) 76 * N - number of PNODE bits (0 .. 10) 77 * 78 * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64). 79 * The actual values are configuration dependent and are set at 80 * boot time. M & N values are set by the hardware/BIOS at boot. 81 * 82 * 83 * APICID format 84 * NOTE!!!!!! This is the current format of the APICID. However, code 85 * should assume that this will change in the future. Use functions 86 * in this file for all APICID bit manipulations and conversion. 87 * 88 * 1111110000000000 89 * 5432109876543210 90 * pppppppppplc0cch Nehalem-EX (12 bits in hdw reg) 91 * ppppppppplcc0cch Westmere-EX (12 bits in hdw reg) 92 * pppppppppppcccch SandyBridge (15 bits in hdw reg) 93 * sssssssssss 94 * 95 * p = pnode bits 96 * l = socket number on board 97 * c = core 98 * h = hyperthread 99 * s = bits that are in the SOCKET_ID CSR 100 * 101 * Note: Processor may support fewer bits in the APICID register. The ACPI 102 * tables hold all 16 bits. Software needs to be aware of this. 103 * 104 * Unless otherwise specified, all references to APICID refer to 105 * the FULL value contained in ACPI tables, not the subset in the 106 * processor APICID register. 107 */ 108 109 /* 110 * Maximum number of bricks in all partitions and in all coherency domains. 111 * This is the total number of bricks accessible in the numalink fabric. It 112 * includes all C & M bricks. Routers are NOT included. 113 * 114 * This value is also the value of the maximum number of non-router NASIDs 115 * in the numalink fabric. 116 * 117 * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused. 118 */ 119 #define UV_MAX_NUMALINK_BLADES 16384 120 121 /* 122 * Maximum number of C/Mbricks within a software SSI (hardware may support 123 * more). 124 */ 125 #define UV_MAX_SSI_BLADES 256 126 127 /* 128 * The largest possible NASID of a C or M brick (+ 2) 129 */ 130 #define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_BLADES * 2) 131 132 /* System Controller Interface Reg info */ 133 struct uv_scir_s { 134 struct timer_list timer; 135 unsigned long offset; 136 unsigned long last; 137 unsigned long idle_on; 138 unsigned long idle_off; 139 unsigned char state; 140 unsigned char enabled; 141 }; 142 143 /* GAM (globally addressed memory) range table */ 144 struct uv_gam_range_s { 145 u32 limit; /* PA bits 56:26 (GAM_RANGE_SHFT) */ 146 u16 nasid; /* node's global physical address */ 147 s8 base; /* entry index of node's base addr */ 148 u8 reserved; 149 }; 150 151 /* 152 * The following defines attributes of the HUB chip. These attributes are 153 * frequently referenced and are kept in a common per hub struct. 154 * After setup, the struct is read only, so it should be readily 155 * available in the L3 cache on the cpu socket for the node. 156 */ 157 struct uv_hub_info_s { 158 unsigned long global_mmr_base; 159 unsigned long global_mmr_shift; 160 unsigned long gpa_mask; 161 unsigned short *socket_to_node; 162 unsigned short *socket_to_pnode; 163 unsigned short *pnode_to_socket; 164 struct uv_gam_range_s *gr_table; 165 unsigned short min_socket; 166 unsigned short min_pnode; 167 unsigned char m_val; 168 unsigned char n_val; 169 unsigned char gr_table_len; 170 unsigned char hub_revision; 171 unsigned char apic_pnode_shift; 172 unsigned char gpa_shift; 173 unsigned char m_shift; 174 unsigned char n_lshift; 175 unsigned int gnode_extra; 176 unsigned long gnode_upper; 177 unsigned long lowmem_remap_top; 178 unsigned long lowmem_remap_base; 179 unsigned long global_gru_base; 180 unsigned long global_gru_shift; 181 unsigned short pnode; 182 unsigned short pnode_mask; 183 unsigned short coherency_domain_number; 184 unsigned short numa_blade_id; 185 unsigned short nr_possible_cpus; 186 unsigned short nr_online_cpus; 187 short memory_nid; 188 }; 189 190 /* CPU specific info with a pointer to the hub common info struct */ 191 struct uv_cpu_info_s { 192 void *p_uv_hub_info; 193 unsigned char blade_cpu_id; 194 struct uv_scir_s scir; 195 }; 196 DECLARE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info); 197 198 #define uv_cpu_info this_cpu_ptr(&__uv_cpu_info) 199 #define uv_cpu_info_per(cpu) (&per_cpu(__uv_cpu_info, cpu)) 200 201 #define uv_scir_info (&uv_cpu_info->scir) 202 #define uv_cpu_scir_info(cpu) (&uv_cpu_info_per(cpu)->scir) 203 204 /* Node specific hub common info struct */ 205 extern void **__uv_hub_info_list; 206 static inline struct uv_hub_info_s *uv_hub_info_list(int node) 207 { 208 return (struct uv_hub_info_s *)__uv_hub_info_list[node]; 209 } 210 211 static inline struct uv_hub_info_s *_uv_hub_info(void) 212 { 213 return (struct uv_hub_info_s *)uv_cpu_info->p_uv_hub_info; 214 } 215 #define uv_hub_info _uv_hub_info() 216 217 static inline struct uv_hub_info_s *uv_cpu_hub_info(int cpu) 218 { 219 return (struct uv_hub_info_s *)uv_cpu_info_per(cpu)->p_uv_hub_info; 220 } 221 222 #define UV_HUB_INFO_VERSION 0x7150 223 extern int uv_hub_info_version(void); 224 static inline int uv_hub_info_check(int version) 225 { 226 if (uv_hub_info_version() == version) 227 return 0; 228 229 pr_crit("UV: uv_hub_info version(%x) mismatch, expecting(%x)\n", 230 uv_hub_info_version(), version); 231 232 BUG(); /* Catastrophic - cannot continue on unknown UV system */ 233 } 234 #define _uv_hub_info_check() uv_hub_info_check(UV_HUB_INFO_VERSION) 235 236 /* 237 * HUB revision ranges for each UV HUB architecture. 238 * This is a software convention - NOT the hardware revision numbers in 239 * the hub chip. 240 */ 241 #define UV1_HUB_REVISION_BASE 1 242 #define UV2_HUB_REVISION_BASE 3 243 #define UV3_HUB_REVISION_BASE 5 244 #define UV4_HUB_REVISION_BASE 7 245 #define UV4A_HUB_REVISION_BASE 8 /* UV4 (fixed) rev 2 */ 246 247 /* WARNING: UVx_HUB_IS_SUPPORTED defines are deprecated and will be removed */ 248 static inline int is_uv1_hub(void) 249 { 250 #ifdef UV1_HUB_IS_SUPPORTED 251 return is_uv_hubbed(uv(1)); 252 #else 253 return 0; 254 #endif 255 } 256 257 static inline int is_uv2_hub(void) 258 { 259 #ifdef UV2_HUB_IS_SUPPORTED 260 return is_uv_hubbed(uv(2)); 261 #else 262 return 0; 263 #endif 264 } 265 266 static inline int is_uv3_hub(void) 267 { 268 #ifdef UV3_HUB_IS_SUPPORTED 269 return is_uv_hubbed(uv(3)); 270 #else 271 return 0; 272 #endif 273 } 274 275 /* First test "is UV4A", then "is UV4" */ 276 static inline int is_uv4a_hub(void) 277 { 278 #ifdef UV4A_HUB_IS_SUPPORTED 279 if (is_uv_hubbed(uv(4))) 280 return (uv_hub_info->hub_revision == UV4A_HUB_REVISION_BASE); 281 #endif 282 return 0; 283 } 284 285 static inline int is_uv4_hub(void) 286 { 287 #ifdef UV4_HUB_IS_SUPPORTED 288 return is_uv_hubbed(uv(4)); 289 #else 290 return 0; 291 #endif 292 } 293 294 static inline int is_uvx_hub(void) 295 { 296 return (is_uv_hubbed(-2) >= uv(2)); 297 } 298 299 static inline int is_uv_hub(void) 300 { 301 return is_uv1_hub() || is_uvx_hub(); 302 } 303 304 union uvh_apicid { 305 unsigned long v; 306 struct uvh_apicid_s { 307 unsigned long local_apic_mask : 24; 308 unsigned long local_apic_shift : 5; 309 unsigned long unused1 : 3; 310 unsigned long pnode_mask : 24; 311 unsigned long pnode_shift : 5; 312 unsigned long unused2 : 3; 313 } s; 314 }; 315 316 /* 317 * Local & Global MMR space macros. 318 * Note: macros are intended to be used ONLY by inline functions 319 * in this file - not by other kernel code. 320 * n - NASID (full 15-bit global nasid) 321 * g - GNODE (full 15-bit global nasid, right shifted 1) 322 * p - PNODE (local part of nsids, right shifted 1) 323 */ 324 #define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask) 325 #define UV_PNODE_TO_GNODE(p) ((p) |uv_hub_info->gnode_extra) 326 #define UV_PNODE_TO_NASID(p) (UV_PNODE_TO_GNODE(p) << 1) 327 328 #define UV1_LOCAL_MMR_BASE 0xf4000000UL 329 #define UV1_GLOBAL_MMR32_BASE 0xf8000000UL 330 #define UV1_LOCAL_MMR_SIZE (64UL * 1024 * 1024) 331 #define UV1_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024) 332 333 #define UV2_LOCAL_MMR_BASE 0xfa000000UL 334 #define UV2_GLOBAL_MMR32_BASE 0xfc000000UL 335 #define UV2_LOCAL_MMR_SIZE (32UL * 1024 * 1024) 336 #define UV2_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024) 337 338 #define UV3_LOCAL_MMR_BASE 0xfa000000UL 339 #define UV3_GLOBAL_MMR32_BASE 0xfc000000UL 340 #define UV3_LOCAL_MMR_SIZE (32UL * 1024 * 1024) 341 #define UV3_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024) 342 343 #define UV4_LOCAL_MMR_BASE 0xfa000000UL 344 #define UV4_GLOBAL_MMR32_BASE 0xfc000000UL 345 #define UV4_LOCAL_MMR_SIZE (32UL * 1024 * 1024) 346 #define UV4_GLOBAL_MMR32_SIZE (16UL * 1024 * 1024) 347 348 #define UV_LOCAL_MMR_BASE ( \ 349 is_uv1_hub() ? UV1_LOCAL_MMR_BASE : \ 350 is_uv2_hub() ? UV2_LOCAL_MMR_BASE : \ 351 is_uv3_hub() ? UV3_LOCAL_MMR_BASE : \ 352 /*is_uv4_hub*/ UV4_LOCAL_MMR_BASE) 353 354 #define UV_GLOBAL_MMR32_BASE ( \ 355 is_uv1_hub() ? UV1_GLOBAL_MMR32_BASE : \ 356 is_uv2_hub() ? UV2_GLOBAL_MMR32_BASE : \ 357 is_uv3_hub() ? UV3_GLOBAL_MMR32_BASE : \ 358 /*is_uv4_hub*/ UV4_GLOBAL_MMR32_BASE) 359 360 #define UV_LOCAL_MMR_SIZE ( \ 361 is_uv1_hub() ? UV1_LOCAL_MMR_SIZE : \ 362 is_uv2_hub() ? UV2_LOCAL_MMR_SIZE : \ 363 is_uv3_hub() ? UV3_LOCAL_MMR_SIZE : \ 364 /*is_uv4_hub*/ UV4_LOCAL_MMR_SIZE) 365 366 #define UV_GLOBAL_MMR32_SIZE ( \ 367 is_uv1_hub() ? UV1_GLOBAL_MMR32_SIZE : \ 368 is_uv2_hub() ? UV2_GLOBAL_MMR32_SIZE : \ 369 is_uv3_hub() ? UV3_GLOBAL_MMR32_SIZE : \ 370 /*is_uv4_hub*/ UV4_GLOBAL_MMR32_SIZE) 371 372 #define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base) 373 374 #define UV_GLOBAL_GRU_MMR_BASE 0x4000000 375 376 #define UV_GLOBAL_MMR32_PNODE_SHIFT 15 377 #define _UV_GLOBAL_MMR64_PNODE_SHIFT 26 378 #define UV_GLOBAL_MMR64_PNODE_SHIFT (uv_hub_info->global_mmr_shift) 379 380 #define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT)) 381 382 #define UV_GLOBAL_MMR64_PNODE_BITS(p) \ 383 (((unsigned long)(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT) 384 385 #define UVH_APICID 0x002D0E00L 386 #define UV_APIC_PNODE_SHIFT 6 387 388 #define UV_APICID_HIBIT_MASK 0xffff0000 389 390 /* Local Bus from cpu's perspective */ 391 #define LOCAL_BUS_BASE 0x1c00000 392 #define LOCAL_BUS_SIZE (4 * 1024 * 1024) 393 394 /* 395 * System Controller Interface Reg 396 * 397 * Note there are NO leds on a UV system. This register is only 398 * used by the system controller to monitor system-wide operation. 399 * There are 64 regs per node. With Nahelem cpus (2 cores per node, 400 * 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on 401 * a node. 402 * 403 * The window is located at top of ACPI MMR space 404 */ 405 #define SCIR_WINDOW_COUNT 64 406 #define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \ 407 LOCAL_BUS_SIZE - \ 408 SCIR_WINDOW_COUNT) 409 410 #define SCIR_CPU_HEARTBEAT 0x01 /* timer interrupt */ 411 #define SCIR_CPU_ACTIVITY 0x02 /* not idle */ 412 #define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */ 413 414 /* Loop through all installed blades */ 415 #define for_each_possible_blade(bid) \ 416 for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++) 417 418 /* 419 * Macros for converting between kernel virtual addresses, socket local physical 420 * addresses, and UV global physical addresses. 421 * Note: use the standard __pa() & __va() macros for converting 422 * between socket virtual and socket physical addresses. 423 */ 424 425 /* global bits offset - number of local address bits in gpa for this UV arch */ 426 static inline unsigned int uv_gpa_shift(void) 427 { 428 return uv_hub_info->gpa_shift; 429 } 430 #define _uv_gpa_shift 431 432 /* Find node that has the address range that contains global address */ 433 static inline struct uv_gam_range_s *uv_gam_range(unsigned long pa) 434 { 435 struct uv_gam_range_s *gr = uv_hub_info->gr_table; 436 unsigned long pal = (pa & uv_hub_info->gpa_mask) >> UV_GAM_RANGE_SHFT; 437 int i, num = uv_hub_info->gr_table_len; 438 439 if (gr) { 440 for (i = 0; i < num; i++, gr++) { 441 if (pal < gr->limit) 442 return gr; 443 } 444 } 445 pr_crit("UV: GAM Range for 0x%lx not found at %p!\n", pa, gr); 446 BUG(); 447 } 448 449 /* Return base address of node that contains global address */ 450 static inline unsigned long uv_gam_range_base(unsigned long pa) 451 { 452 struct uv_gam_range_s *gr = uv_gam_range(pa); 453 int base = gr->base; 454 455 if (base < 0) 456 return 0UL; 457 458 return uv_hub_info->gr_table[base].limit; 459 } 460 461 /* socket phys RAM --> UV global NASID (UV4+) */ 462 static inline unsigned long uv_soc_phys_ram_to_nasid(unsigned long paddr) 463 { 464 return uv_gam_range(paddr)->nasid; 465 } 466 #define _uv_soc_phys_ram_to_nasid 467 468 /* socket virtual --> UV global NASID (UV4+) */ 469 static inline unsigned long uv_gpa_nasid(void *v) 470 { 471 return uv_soc_phys_ram_to_nasid(__pa(v)); 472 } 473 474 /* socket phys RAM --> UV global physical address */ 475 static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr) 476 { 477 unsigned int m_val = uv_hub_info->m_val; 478 479 if (paddr < uv_hub_info->lowmem_remap_top) 480 paddr |= uv_hub_info->lowmem_remap_base; 481 482 if (m_val) { 483 paddr |= uv_hub_info->gnode_upper; 484 paddr = ((paddr << uv_hub_info->m_shift) 485 >> uv_hub_info->m_shift) | 486 ((paddr >> uv_hub_info->m_val) 487 << uv_hub_info->n_lshift); 488 } else { 489 paddr |= uv_soc_phys_ram_to_nasid(paddr) 490 << uv_hub_info->gpa_shift; 491 } 492 return paddr; 493 } 494 495 /* socket virtual --> UV global physical address */ 496 static inline unsigned long uv_gpa(void *v) 497 { 498 return uv_soc_phys_ram_to_gpa(__pa(v)); 499 } 500 501 /* Top two bits indicate the requested address is in MMR space. */ 502 static inline int 503 uv_gpa_in_mmr_space(unsigned long gpa) 504 { 505 return (gpa >> 62) == 0x3UL; 506 } 507 508 /* UV global physical address --> socket phys RAM */ 509 static inline unsigned long uv_gpa_to_soc_phys_ram(unsigned long gpa) 510 { 511 unsigned long paddr; 512 unsigned long remap_base = uv_hub_info->lowmem_remap_base; 513 unsigned long remap_top = uv_hub_info->lowmem_remap_top; 514 unsigned int m_val = uv_hub_info->m_val; 515 516 if (m_val) 517 gpa = ((gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift) | 518 ((gpa >> uv_hub_info->n_lshift) << uv_hub_info->m_val); 519 520 paddr = gpa & uv_hub_info->gpa_mask; 521 if (paddr >= remap_base && paddr < remap_base + remap_top) 522 paddr -= remap_base; 523 return paddr; 524 } 525 526 /* gpa -> gnode */ 527 static inline unsigned long uv_gpa_to_gnode(unsigned long gpa) 528 { 529 unsigned int n_lshift = uv_hub_info->n_lshift; 530 531 if (n_lshift) 532 return gpa >> n_lshift; 533 534 return uv_gam_range(gpa)->nasid >> 1; 535 } 536 537 /* gpa -> pnode */ 538 static inline int uv_gpa_to_pnode(unsigned long gpa) 539 { 540 return uv_gpa_to_gnode(gpa) & uv_hub_info->pnode_mask; 541 } 542 543 /* gpa -> node offset */ 544 static inline unsigned long uv_gpa_to_offset(unsigned long gpa) 545 { 546 unsigned int m_shift = uv_hub_info->m_shift; 547 548 if (m_shift) 549 return (gpa << m_shift) >> m_shift; 550 551 return (gpa & uv_hub_info->gpa_mask) - uv_gam_range_base(gpa); 552 } 553 554 /* Convert socket to node */ 555 static inline int _uv_socket_to_node(int socket, unsigned short *s2nid) 556 { 557 return s2nid ? s2nid[socket - uv_hub_info->min_socket] : socket; 558 } 559 560 static inline int uv_socket_to_node(int socket) 561 { 562 return _uv_socket_to_node(socket, uv_hub_info->socket_to_node); 563 } 564 565 /* pnode, offset --> socket virtual */ 566 static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset) 567 { 568 unsigned int m_val = uv_hub_info->m_val; 569 unsigned long base; 570 unsigned short sockid, node, *p2s; 571 572 if (m_val) 573 return __va(((unsigned long)pnode << m_val) | offset); 574 575 p2s = uv_hub_info->pnode_to_socket; 576 sockid = p2s ? p2s[pnode - uv_hub_info->min_pnode] : pnode; 577 node = uv_socket_to_node(sockid); 578 579 /* limit address of previous socket is our base, except node 0 is 0 */ 580 if (!node) 581 return __va((unsigned long)offset); 582 583 base = (unsigned long)(uv_hub_info->gr_table[node - 1].limit); 584 return __va(base << UV_GAM_RANGE_SHFT | offset); 585 } 586 587 /* Extract/Convert a PNODE from an APICID (full apicid, not processor subset) */ 588 static inline int uv_apicid_to_pnode(int apicid) 589 { 590 int pnode = apicid >> uv_hub_info->apic_pnode_shift; 591 unsigned short *s2pn = uv_hub_info->socket_to_pnode; 592 593 return s2pn ? s2pn[pnode - uv_hub_info->min_socket] : pnode; 594 } 595 596 /* Convert an apicid to the socket number on the blade */ 597 static inline int uv_apicid_to_socket(int apicid) 598 { 599 if (is_uv1_hub()) 600 return (apicid >> (uv_hub_info->apic_pnode_shift - 1)) & 1; 601 else 602 return 0; 603 } 604 605 /* 606 * Access global MMRs using the low memory MMR32 space. This region supports 607 * faster MMR access but not all MMRs are accessible in this space. 608 */ 609 static inline unsigned long *uv_global_mmr32_address(int pnode, unsigned long offset) 610 { 611 return __va(UV_GLOBAL_MMR32_BASE | 612 UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset); 613 } 614 615 static inline void uv_write_global_mmr32(int pnode, unsigned long offset, unsigned long val) 616 { 617 writeq(val, uv_global_mmr32_address(pnode, offset)); 618 } 619 620 static inline unsigned long uv_read_global_mmr32(int pnode, unsigned long offset) 621 { 622 return readq(uv_global_mmr32_address(pnode, offset)); 623 } 624 625 /* 626 * Access Global MMR space using the MMR space located at the top of physical 627 * memory. 628 */ 629 static inline volatile void __iomem *uv_global_mmr64_address(int pnode, unsigned long offset) 630 { 631 return __va(UV_GLOBAL_MMR64_BASE | 632 UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset); 633 } 634 635 static inline void uv_write_global_mmr64(int pnode, unsigned long offset, unsigned long val) 636 { 637 writeq(val, uv_global_mmr64_address(pnode, offset)); 638 } 639 640 static inline unsigned long uv_read_global_mmr64(int pnode, unsigned long offset) 641 { 642 return readq(uv_global_mmr64_address(pnode, offset)); 643 } 644 645 static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val) 646 { 647 writeb(val, uv_global_mmr64_address(pnode, offset)); 648 } 649 650 static inline unsigned char uv_read_global_mmr8(int pnode, unsigned long offset) 651 { 652 return readb(uv_global_mmr64_address(pnode, offset)); 653 } 654 655 /* 656 * Access hub local MMRs. Faster than using global space but only local MMRs 657 * are accessible. 658 */ 659 static inline unsigned long *uv_local_mmr_address(unsigned long offset) 660 { 661 return __va(UV_LOCAL_MMR_BASE | offset); 662 } 663 664 static inline unsigned long uv_read_local_mmr(unsigned long offset) 665 { 666 return readq(uv_local_mmr_address(offset)); 667 } 668 669 static inline void uv_write_local_mmr(unsigned long offset, unsigned long val) 670 { 671 writeq(val, uv_local_mmr_address(offset)); 672 } 673 674 static inline unsigned char uv_read_local_mmr8(unsigned long offset) 675 { 676 return readb(uv_local_mmr_address(offset)); 677 } 678 679 static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val) 680 { 681 writeb(val, uv_local_mmr_address(offset)); 682 } 683 684 /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */ 685 static inline int uv_blade_processor_id(void) 686 { 687 return uv_cpu_info->blade_cpu_id; 688 } 689 690 /* Blade-local cpu number of cpu N. Numbered 0 .. <# cpus on the blade> */ 691 static inline int uv_cpu_blade_processor_id(int cpu) 692 { 693 return uv_cpu_info_per(cpu)->blade_cpu_id; 694 } 695 #define _uv_cpu_blade_processor_id 1 /* indicate function available */ 696 697 /* Blade number to Node number (UV1..UV4 is 1:1) */ 698 static inline int uv_blade_to_node(int blade) 699 { 700 return blade; 701 } 702 703 /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */ 704 static inline int uv_numa_blade_id(void) 705 { 706 return uv_hub_info->numa_blade_id; 707 } 708 709 /* 710 * Convert linux node number to the UV blade number. 711 * .. Currently for UV1 thru UV4 the node and the blade are identical. 712 * .. If this changes then you MUST check references to this function! 713 */ 714 static inline int uv_node_to_blade_id(int nid) 715 { 716 return nid; 717 } 718 719 /* Convert a cpu number to the the UV blade number */ 720 static inline int uv_cpu_to_blade_id(int cpu) 721 { 722 return uv_node_to_blade_id(cpu_to_node(cpu)); 723 } 724 725 /* Convert a blade id to the PNODE of the blade */ 726 static inline int uv_blade_to_pnode(int bid) 727 { 728 return uv_hub_info_list(uv_blade_to_node(bid))->pnode; 729 } 730 731 /* Nid of memory node on blade. -1 if no blade-local memory */ 732 static inline int uv_blade_to_memory_nid(int bid) 733 { 734 return uv_hub_info_list(uv_blade_to_node(bid))->memory_nid; 735 } 736 737 /* Determine the number of possible cpus on a blade */ 738 static inline int uv_blade_nr_possible_cpus(int bid) 739 { 740 return uv_hub_info_list(uv_blade_to_node(bid))->nr_possible_cpus; 741 } 742 743 /* Determine the number of online cpus on a blade */ 744 static inline int uv_blade_nr_online_cpus(int bid) 745 { 746 return uv_hub_info_list(uv_blade_to_node(bid))->nr_online_cpus; 747 } 748 749 /* Convert a cpu id to the PNODE of the blade containing the cpu */ 750 static inline int uv_cpu_to_pnode(int cpu) 751 { 752 return uv_cpu_hub_info(cpu)->pnode; 753 } 754 755 /* Convert a linux node number to the PNODE of the blade */ 756 static inline int uv_node_to_pnode(int nid) 757 { 758 return uv_hub_info_list(nid)->pnode; 759 } 760 761 /* Maximum possible number of blades */ 762 extern short uv_possible_blades; 763 static inline int uv_num_possible_blades(void) 764 { 765 return uv_possible_blades; 766 } 767 768 /* Per Hub NMI support */ 769 extern void uv_nmi_setup(void); 770 extern void uv_nmi_setup_hubless(void); 771 772 /* BIOS/Kernel flags exchange MMR */ 773 #define UVH_BIOS_KERNEL_MMR UVH_SCRATCH5 774 #define UVH_BIOS_KERNEL_MMR_ALIAS UVH_SCRATCH5_ALIAS 775 #define UVH_BIOS_KERNEL_MMR_ALIAS_2 UVH_SCRATCH5_ALIAS_2 776 777 /* TSC sync valid, set by BIOS */ 778 #define UVH_TSC_SYNC_MMR UVH_BIOS_KERNEL_MMR 779 #define UVH_TSC_SYNC_SHIFT 10 780 #define UVH_TSC_SYNC_SHIFT_UV2K 16 /* UV2/3k have different bits */ 781 #define UVH_TSC_SYNC_MASK 3 /* 0011 */ 782 #define UVH_TSC_SYNC_VALID 3 /* 0011 */ 783 #define UVH_TSC_SYNC_INVALID 2 /* 0010 */ 784 785 /* BMC sets a bit this MMR non-zero before sending an NMI */ 786 #define UVH_NMI_MMR UVH_BIOS_KERNEL_MMR 787 #define UVH_NMI_MMR_CLEAR UVH_BIOS_KERNEL_MMR_ALIAS 788 #define UVH_NMI_MMR_SHIFT 63 789 #define UVH_NMI_MMR_TYPE "SCRATCH5" 790 791 /* Newer SMM NMI handler, not present in all systems */ 792 #define UVH_NMI_MMRX UVH_EVENT_OCCURRED0 793 #define UVH_NMI_MMRX_CLEAR UVH_EVENT_OCCURRED0_ALIAS 794 #define UVH_NMI_MMRX_SHIFT UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT 795 #define UVH_NMI_MMRX_TYPE "EXTIO_INT0" 796 797 /* Non-zero indicates newer SMM NMI handler present */ 798 #define UVH_NMI_MMRX_SUPPORTED UVH_EXTIO_INT0_BROADCAST 799 800 /* Indicates to BIOS that we want to use the newer SMM NMI handler */ 801 #define UVH_NMI_MMRX_REQ UVH_BIOS_KERNEL_MMR_ALIAS_2 802 #define UVH_NMI_MMRX_REQ_SHIFT 62 803 804 struct uv_hub_nmi_s { 805 raw_spinlock_t nmi_lock; 806 atomic_t in_nmi; /* flag this node in UV NMI IRQ */ 807 atomic_t cpu_owner; /* last locker of this struct */ 808 atomic_t read_mmr_count; /* count of MMR reads */ 809 atomic_t nmi_count; /* count of true UV NMIs */ 810 unsigned long nmi_value; /* last value read from NMI MMR */ 811 bool hub_present; /* false means UV hubless system */ 812 bool pch_owner; /* indicates this hub owns PCH */ 813 }; 814 815 struct uv_cpu_nmi_s { 816 struct uv_hub_nmi_s *hub; 817 int state; 818 int pinging; 819 int queries; 820 int pings; 821 }; 822 823 DECLARE_PER_CPU(struct uv_cpu_nmi_s, uv_cpu_nmi); 824 825 #define uv_hub_nmi this_cpu_read(uv_cpu_nmi.hub) 826 #define uv_cpu_nmi_per(cpu) (per_cpu(uv_cpu_nmi, cpu)) 827 #define uv_hub_nmi_per(cpu) (uv_cpu_nmi_per(cpu).hub) 828 829 /* uv_cpu_nmi_states */ 830 #define UV_NMI_STATE_OUT 0 831 #define UV_NMI_STATE_IN 1 832 #define UV_NMI_STATE_DUMP 2 833 #define UV_NMI_STATE_DUMP_DONE 3 834 835 /* Update SCIR state */ 836 static inline void uv_set_scir_bits(unsigned char value) 837 { 838 if (uv_scir_info->state != value) { 839 uv_scir_info->state = value; 840 uv_write_local_mmr8(uv_scir_info->offset, value); 841 } 842 } 843 844 static inline unsigned long uv_scir_offset(int apicid) 845 { 846 return SCIR_LOCAL_MMR_BASE | (apicid & 0x3f); 847 } 848 849 static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value) 850 { 851 if (uv_cpu_scir_info(cpu)->state != value) { 852 uv_write_global_mmr8(uv_cpu_to_pnode(cpu), 853 uv_cpu_scir_info(cpu)->offset, value); 854 uv_cpu_scir_info(cpu)->state = value; 855 } 856 } 857 858 extern unsigned int uv_apicid_hibits; 859 static unsigned long uv_hub_ipi_value(int apicid, int vector, int mode) 860 { 861 apicid |= uv_apicid_hibits; 862 return (1UL << UVH_IPI_INT_SEND_SHFT) | 863 ((apicid) << UVH_IPI_INT_APIC_ID_SHFT) | 864 (mode << UVH_IPI_INT_DELIVERY_MODE_SHFT) | 865 (vector << UVH_IPI_INT_VECTOR_SHFT); 866 } 867 868 static inline void uv_hub_send_ipi(int pnode, int apicid, int vector) 869 { 870 unsigned long val; 871 unsigned long dmode = dest_Fixed; 872 873 if (vector == NMI_VECTOR) 874 dmode = dest_NMI; 875 876 val = uv_hub_ipi_value(apicid, vector, dmode); 877 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 878 } 879 880 /* 881 * Get the minimum revision number of the hub chips within the partition. 882 * (See UVx_HUB_REVISION_BASE above for specific values.) 883 */ 884 static inline int uv_get_min_hub_revision_id(void) 885 { 886 return uv_hub_info->hub_revision; 887 } 888 889 #endif /* CONFIG_X86_64 */ 890 #endif /* _ASM_X86_UV_UV_HUB_H */ 891