1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * SGI UV architectural definitions 7 * 8 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved. 9 */ 10 11 #ifndef _ASM_X86_UV_UV_HUB_H 12 #define _ASM_X86_UV_UV_HUB_H 13 14 #ifdef CONFIG_X86_64 15 #include <linux/numa.h> 16 #include <linux/percpu.h> 17 #include <linux/timer.h> 18 #include <linux/io.h> 19 #include <linux/topology.h> 20 #include <asm/types.h> 21 #include <asm/percpu.h> 22 #include <asm/uv/uv_mmrs.h> 23 #include <asm/irq_vectors.h> 24 #include <asm/io_apic.h> 25 26 27 /* 28 * Addressing Terminology 29 * 30 * M - The low M bits of a physical address represent the offset 31 * into the blade local memory. RAM memory on a blade is physically 32 * contiguous (although various IO spaces may punch holes in 33 * it).. 34 * 35 * N - Number of bits in the node portion of a socket physical 36 * address. 37 * 38 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of 39 * routers always have low bit of 1, C/MBricks have low bit 40 * equal to 0. Most addressing macros that target UV hub chips 41 * right shift the NASID by 1 to exclude the always-zero bit. 42 * NASIDs contain up to 15 bits. 43 * 44 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead 45 * of nasids. 46 * 47 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant 48 * of the nasid for socket usage. 49 * 50 * GPA - (global physical address) a socket physical address converted 51 * so that it can be used by the GRU as a global address. Socket 52 * physical addresses 1) need additional NASID (node) bits added 53 * to the high end of the address, and 2) unaliased if the 54 * partition does not have a physical address 0. In addition, on 55 * UV2 rev 1, GPAs need the gnode left shifted to bits 39 or 40. 56 * 57 * 58 * NumaLink Global Physical Address Format: 59 * +--------------------------------+---------------------+ 60 * |00..000| GNODE | NodeOffset | 61 * +--------------------------------+---------------------+ 62 * |<-------53 - M bits --->|<--------M bits -----> 63 * 64 * M - number of node offset bits (35 .. 40) 65 * 66 * 67 * Memory/UV-HUB Processor Socket Address Format: 68 * +----------------+---------------+---------------------+ 69 * |00..000000000000| PNODE | NodeOffset | 70 * +----------------+---------------+---------------------+ 71 * <--- N bits --->|<--------M bits -----> 72 * 73 * M - number of node offset bits (35 .. 40) 74 * N - number of PNODE bits (0 .. 10) 75 * 76 * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64). 77 * The actual values are configuration dependent and are set at 78 * boot time. M & N values are set by the hardware/BIOS at boot. 79 * 80 * 81 * APICID format 82 * NOTE!!!!!! This is the current format of the APICID. However, code 83 * should assume that this will change in the future. Use functions 84 * in this file for all APICID bit manipulations and conversion. 85 * 86 * 1111110000000000 87 * 5432109876543210 88 * pppppppppplc0cch Nehalem-EX (12 bits in hdw reg) 89 * ppppppppplcc0cch Westmere-EX (12 bits in hdw reg) 90 * pppppppppppcccch SandyBridge (15 bits in hdw reg) 91 * sssssssssss 92 * 93 * p = pnode bits 94 * l = socket number on board 95 * c = core 96 * h = hyperthread 97 * s = bits that are in the SOCKET_ID CSR 98 * 99 * Note: Processor may support fewer bits in the APICID register. The ACPI 100 * tables hold all 16 bits. Software needs to be aware of this. 101 * 102 * Unless otherwise specified, all references to APICID refer to 103 * the FULL value contained in ACPI tables, not the subset in the 104 * processor APICID register. 105 */ 106 107 108 /* 109 * Maximum number of bricks in all partitions and in all coherency domains. 110 * This is the total number of bricks accessible in the numalink fabric. It 111 * includes all C & M bricks. Routers are NOT included. 112 * 113 * This value is also the value of the maximum number of non-router NASIDs 114 * in the numalink fabric. 115 * 116 * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused. 117 */ 118 #define UV_MAX_NUMALINK_BLADES 16384 119 120 /* 121 * Maximum number of C/Mbricks within a software SSI (hardware may support 122 * more). 123 */ 124 #define UV_MAX_SSI_BLADES 256 125 126 /* 127 * The largest possible NASID of a C or M brick (+ 2) 128 */ 129 #define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_BLADES * 2) 130 131 /* System Controller Interface Reg info */ 132 struct uv_scir_s { 133 struct timer_list timer; 134 unsigned long offset; 135 unsigned long last; 136 unsigned long idle_on; 137 unsigned long idle_off; 138 unsigned char state; 139 unsigned char enabled; 140 }; 141 142 /* 143 * The following defines attributes of the HUB chip. These attributes are 144 * frequently referenced and are kept in a common per hub struct. 145 * After setup, the struct is read only, so it should be readily 146 * available in the L3 cache on the cpu socket for the node. 147 */ 148 struct uv_hub_info_s { 149 unsigned long global_mmr_base; 150 unsigned long global_mmr_shift; 151 unsigned long gpa_mask; 152 unsigned short *socket_to_node; 153 unsigned short *socket_to_pnode; 154 unsigned short *pnode_to_socket; 155 unsigned short min_socket; 156 unsigned short min_pnode; 157 unsigned char hub_revision; 158 unsigned char apic_pnode_shift; 159 unsigned char gpa_shift; 160 unsigned char m_shift; 161 unsigned char n_lshift; 162 unsigned int gnode_extra; 163 unsigned long gnode_upper; 164 unsigned long lowmem_remap_top; 165 unsigned long lowmem_remap_base; 166 unsigned long global_gru_base; 167 unsigned long global_gru_shift; 168 unsigned short pnode; 169 unsigned short pnode_mask; 170 unsigned short coherency_domain_number; 171 unsigned short numa_blade_id; 172 unsigned char m_val; 173 unsigned char n_val; 174 unsigned short nr_possible_cpus; 175 unsigned short nr_online_cpus; 176 short memory_nid; 177 }; 178 179 /* CPU specific info with a pointer to the hub common info struct */ 180 struct uv_cpu_info_s { 181 void *p_uv_hub_info; 182 unsigned char blade_cpu_id; 183 struct uv_scir_s scir; 184 }; 185 DECLARE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info); 186 187 #define uv_cpu_info this_cpu_ptr(&__uv_cpu_info) 188 #define uv_cpu_info_per(cpu) (&per_cpu(__uv_cpu_info, cpu)) 189 190 #define uv_scir_info (&uv_cpu_info->scir) 191 #define uv_cpu_scir_info(cpu) (&uv_cpu_info_per(cpu)->scir) 192 193 /* Node specific hub common info struct */ 194 extern void **__uv_hub_info_list; 195 static inline struct uv_hub_info_s *uv_hub_info_list(int node) 196 { 197 return (struct uv_hub_info_s *)__uv_hub_info_list[node]; 198 } 199 200 static inline struct uv_hub_info_s *_uv_hub_info(void) 201 { 202 return (struct uv_hub_info_s *)uv_cpu_info->p_uv_hub_info; 203 } 204 #define uv_hub_info _uv_hub_info() 205 206 static inline struct uv_hub_info_s *uv_cpu_hub_info(int cpu) 207 { 208 return (struct uv_hub_info_s *)uv_cpu_info_per(cpu)->p_uv_hub_info; 209 } 210 211 #define UV_HUB_INFO_VERSION 0x7150 212 extern int uv_hub_info_version(void); 213 static inline int uv_hub_info_check(int version) 214 { 215 if (uv_hub_info_version() == version) 216 return 0; 217 218 pr_crit("UV: uv_hub_info version(%x) mismatch, expecting(%x)\n", 219 uv_hub_info_version(), version); 220 221 BUG(); /* Catastrophic - cannot continue on unknown UV system */ 222 } 223 #define _uv_hub_info_check() uv_hub_info_check(UV_HUB_INFO_VERSION) 224 225 /* 226 * HUB revision ranges for each UV HUB architecture. 227 * This is a software convention - NOT the hardware revision numbers in 228 * the hub chip. 229 */ 230 #define UV1_HUB_REVISION_BASE 1 231 #define UV2_HUB_REVISION_BASE 3 232 #define UV3_HUB_REVISION_BASE 5 233 #define UV4_HUB_REVISION_BASE 7 234 235 #ifdef UV1_HUB_IS_SUPPORTED 236 static inline int is_uv1_hub(void) 237 { 238 return uv_hub_info->hub_revision < UV2_HUB_REVISION_BASE; 239 } 240 #else 241 static inline int is_uv1_hub(void) 242 { 243 return 0; 244 } 245 #endif 246 247 #ifdef UV2_HUB_IS_SUPPORTED 248 static inline int is_uv2_hub(void) 249 { 250 return ((uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE) && 251 (uv_hub_info->hub_revision < UV3_HUB_REVISION_BASE)); 252 } 253 #else 254 static inline int is_uv2_hub(void) 255 { 256 return 0; 257 } 258 #endif 259 260 #ifdef UV3_HUB_IS_SUPPORTED 261 static inline int is_uv3_hub(void) 262 { 263 return ((uv_hub_info->hub_revision >= UV3_HUB_REVISION_BASE) && 264 (uv_hub_info->hub_revision < UV4_HUB_REVISION_BASE)); 265 } 266 #else 267 static inline int is_uv3_hub(void) 268 { 269 return 0; 270 } 271 #endif 272 273 #ifdef UV4_HUB_IS_SUPPORTED 274 static inline int is_uv4_hub(void) 275 { 276 return uv_hub_info->hub_revision >= UV4_HUB_REVISION_BASE; 277 } 278 #else 279 static inline int is_uv4_hub(void) 280 { 281 return 0; 282 } 283 #endif 284 285 static inline int is_uvx_hub(void) 286 { 287 if (uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE) 288 return uv_hub_info->hub_revision; 289 290 return 0; 291 } 292 293 static inline int is_uv_hub(void) 294 { 295 #ifdef UV1_HUB_IS_SUPPORTED 296 return uv_hub_info->hub_revision; 297 #endif 298 return is_uvx_hub(); 299 } 300 301 union uvh_apicid { 302 unsigned long v; 303 struct uvh_apicid_s { 304 unsigned long local_apic_mask : 24; 305 unsigned long local_apic_shift : 5; 306 unsigned long unused1 : 3; 307 unsigned long pnode_mask : 24; 308 unsigned long pnode_shift : 5; 309 unsigned long unused2 : 3; 310 } s; 311 }; 312 313 /* 314 * Local & Global MMR space macros. 315 * Note: macros are intended to be used ONLY by inline functions 316 * in this file - not by other kernel code. 317 * n - NASID (full 15-bit global nasid) 318 * g - GNODE (full 15-bit global nasid, right shifted 1) 319 * p - PNODE (local part of nsids, right shifted 1) 320 */ 321 #define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask) 322 #define UV_PNODE_TO_GNODE(p) ((p) |uv_hub_info->gnode_extra) 323 #define UV_PNODE_TO_NASID(p) (UV_PNODE_TO_GNODE(p) << 1) 324 325 #define UV1_LOCAL_MMR_BASE 0xf4000000UL 326 #define UV1_GLOBAL_MMR32_BASE 0xf8000000UL 327 #define UV1_LOCAL_MMR_SIZE (64UL * 1024 * 1024) 328 #define UV1_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024) 329 330 #define UV2_LOCAL_MMR_BASE 0xfa000000UL 331 #define UV2_GLOBAL_MMR32_BASE 0xfc000000UL 332 #define UV2_LOCAL_MMR_SIZE (32UL * 1024 * 1024) 333 #define UV2_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024) 334 335 #define UV3_LOCAL_MMR_BASE 0xfa000000UL 336 #define UV3_GLOBAL_MMR32_BASE 0xfc000000UL 337 #define UV3_LOCAL_MMR_SIZE (32UL * 1024 * 1024) 338 #define UV3_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024) 339 340 #define UV4_LOCAL_MMR_BASE 0xfa000000UL 341 #define UV4_GLOBAL_MMR32_BASE 0xfc000000UL 342 #define UV4_LOCAL_MMR_SIZE (32UL * 1024 * 1024) 343 #define UV4_GLOBAL_MMR32_SIZE (16UL * 1024 * 1024) 344 345 #define UV_LOCAL_MMR_BASE ( \ 346 is_uv1_hub() ? UV1_LOCAL_MMR_BASE : \ 347 is_uv2_hub() ? UV2_LOCAL_MMR_BASE : \ 348 is_uv3_hub() ? UV3_LOCAL_MMR_BASE : \ 349 /*is_uv4_hub*/ UV4_LOCAL_MMR_BASE) 350 351 #define UV_GLOBAL_MMR32_BASE ( \ 352 is_uv1_hub() ? UV1_GLOBAL_MMR32_BASE : \ 353 is_uv2_hub() ? UV2_GLOBAL_MMR32_BASE : \ 354 is_uv3_hub() ? UV3_GLOBAL_MMR32_BASE : \ 355 /*is_uv4_hub*/ UV4_GLOBAL_MMR32_BASE) 356 357 #define UV_LOCAL_MMR_SIZE ( \ 358 is_uv1_hub() ? UV1_LOCAL_MMR_SIZE : \ 359 is_uv2_hub() ? UV2_LOCAL_MMR_SIZE : \ 360 is_uv3_hub() ? UV3_LOCAL_MMR_SIZE : \ 361 /*is_uv4_hub*/ UV4_LOCAL_MMR_SIZE) 362 363 #define UV_GLOBAL_MMR32_SIZE ( \ 364 is_uv1_hub() ? UV1_GLOBAL_MMR32_SIZE : \ 365 is_uv2_hub() ? UV2_GLOBAL_MMR32_SIZE : \ 366 is_uv3_hub() ? UV3_GLOBAL_MMR32_SIZE : \ 367 /*is_uv4_hub*/ UV4_GLOBAL_MMR32_SIZE) 368 369 #define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base) 370 371 #define UV_GLOBAL_GRU_MMR_BASE 0x4000000 372 373 #define UV_GLOBAL_MMR32_PNODE_SHIFT 15 374 #define _UV_GLOBAL_MMR64_PNODE_SHIFT 26 375 #define UV_GLOBAL_MMR64_PNODE_SHIFT (uv_hub_info->global_mmr_shift) 376 377 #define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT)) 378 379 #define UV_GLOBAL_MMR64_PNODE_BITS(p) \ 380 (((unsigned long)(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT) 381 382 #define UVH_APICID 0x002D0E00L 383 #define UV_APIC_PNODE_SHIFT 6 384 385 #define UV_APICID_HIBIT_MASK 0xffff0000 386 387 /* Local Bus from cpu's perspective */ 388 #define LOCAL_BUS_BASE 0x1c00000 389 #define LOCAL_BUS_SIZE (4 * 1024 * 1024) 390 391 /* 392 * System Controller Interface Reg 393 * 394 * Note there are NO leds on a UV system. This register is only 395 * used by the system controller to monitor system-wide operation. 396 * There are 64 regs per node. With Nahelem cpus (2 cores per node, 397 * 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on 398 * a node. 399 * 400 * The window is located at top of ACPI MMR space 401 */ 402 #define SCIR_WINDOW_COUNT 64 403 #define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \ 404 LOCAL_BUS_SIZE - \ 405 SCIR_WINDOW_COUNT) 406 407 #define SCIR_CPU_HEARTBEAT 0x01 /* timer interrupt */ 408 #define SCIR_CPU_ACTIVITY 0x02 /* not idle */ 409 #define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */ 410 411 /* Loop through all installed blades */ 412 #define for_each_possible_blade(bid) \ 413 for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++) 414 415 /* 416 * Macros for converting between kernel virtual addresses, socket local physical 417 * addresses, and UV global physical addresses. 418 * Note: use the standard __pa() & __va() macros for converting 419 * between socket virtual and socket physical addresses. 420 */ 421 422 /* socket phys RAM --> UV global physical address */ 423 static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr) 424 { 425 if (paddr < uv_hub_info->lowmem_remap_top) 426 paddr |= uv_hub_info->lowmem_remap_base; 427 paddr |= uv_hub_info->gnode_upper; 428 paddr = ((paddr << uv_hub_info->m_shift) >> uv_hub_info->m_shift) | 429 ((paddr >> uv_hub_info->m_val) << uv_hub_info->n_lshift); 430 return paddr; 431 } 432 433 434 /* socket virtual --> UV global physical address */ 435 static inline unsigned long uv_gpa(void *v) 436 { 437 return uv_soc_phys_ram_to_gpa(__pa(v)); 438 } 439 440 /* Top two bits indicate the requested address is in MMR space. */ 441 static inline int 442 uv_gpa_in_mmr_space(unsigned long gpa) 443 { 444 return (gpa >> 62) == 0x3UL; 445 } 446 447 /* UV global physical address --> socket phys RAM */ 448 static inline unsigned long uv_gpa_to_soc_phys_ram(unsigned long gpa) 449 { 450 unsigned long paddr; 451 unsigned long remap_base = uv_hub_info->lowmem_remap_base; 452 unsigned long remap_top = uv_hub_info->lowmem_remap_top; 453 454 gpa = ((gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift) | 455 ((gpa >> uv_hub_info->n_lshift) << uv_hub_info->m_val); 456 paddr = gpa & uv_hub_info->gpa_mask; 457 if (paddr >= remap_base && paddr < remap_base + remap_top) 458 paddr -= remap_base; 459 return paddr; 460 } 461 462 463 /* gpa -> gnode */ 464 static inline unsigned long uv_gpa_to_gnode(unsigned long gpa) 465 { 466 return gpa >> uv_hub_info->n_lshift; 467 } 468 469 /* gpa -> pnode */ 470 static inline int uv_gpa_to_pnode(unsigned long gpa) 471 { 472 return uv_gpa_to_gnode(gpa) & uv_hub_info->pnode_mask; 473 } 474 475 /* gpa -> node offset */ 476 static inline unsigned long uv_gpa_to_offset(unsigned long gpa) 477 { 478 return (gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift; 479 } 480 481 /* pnode, offset --> socket virtual */ 482 static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset) 483 { 484 return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset); 485 } 486 487 /* Convert socket to node */ 488 static inline int uv_socket_to_node(int socket) 489 { 490 unsigned short *s2nid = uv_hub_info->socket_to_node; 491 492 return s2nid ? s2nid[socket - uv_hub_info->min_socket] : socket; 493 } 494 495 /* Extract/Convert a PNODE from an APICID (full apicid, not processor subset) */ 496 static inline int uv_apicid_to_pnode(int apicid) 497 { 498 int pnode = apicid >> uv_hub_info->apic_pnode_shift; 499 unsigned short *s2pn = uv_hub_info->socket_to_pnode; 500 501 return s2pn ? s2pn[pnode - uv_hub_info->min_socket] : pnode; 502 } 503 504 /* Convert an apicid to the socket number on the blade */ 505 static inline int uv_apicid_to_socket(int apicid) 506 { 507 if (is_uv1_hub()) 508 return (apicid >> (uv_hub_info->apic_pnode_shift - 1)) & 1; 509 else 510 return 0; 511 } 512 513 /* 514 * Access global MMRs using the low memory MMR32 space. This region supports 515 * faster MMR access but not all MMRs are accessible in this space. 516 */ 517 static inline unsigned long *uv_global_mmr32_address(int pnode, unsigned long offset) 518 { 519 return __va(UV_GLOBAL_MMR32_BASE | 520 UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset); 521 } 522 523 static inline void uv_write_global_mmr32(int pnode, unsigned long offset, unsigned long val) 524 { 525 writeq(val, uv_global_mmr32_address(pnode, offset)); 526 } 527 528 static inline unsigned long uv_read_global_mmr32(int pnode, unsigned long offset) 529 { 530 return readq(uv_global_mmr32_address(pnode, offset)); 531 } 532 533 /* 534 * Access Global MMR space using the MMR space located at the top of physical 535 * memory. 536 */ 537 static inline volatile void __iomem *uv_global_mmr64_address(int pnode, unsigned long offset) 538 { 539 return __va(UV_GLOBAL_MMR64_BASE | 540 UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset); 541 } 542 543 static inline void uv_write_global_mmr64(int pnode, unsigned long offset, unsigned long val) 544 { 545 writeq(val, uv_global_mmr64_address(pnode, offset)); 546 } 547 548 static inline unsigned long uv_read_global_mmr64(int pnode, unsigned long offset) 549 { 550 return readq(uv_global_mmr64_address(pnode, offset)); 551 } 552 553 /* 554 * Global MMR space addresses when referenced by the GRU. (GRU does 555 * NOT use socket addressing). 556 */ 557 static inline unsigned long uv_global_gru_mmr_address(int pnode, unsigned long offset) 558 { 559 return UV_GLOBAL_GRU_MMR_BASE | offset | 560 ((unsigned long)pnode << uv_hub_info->m_val); 561 } 562 563 static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val) 564 { 565 writeb(val, uv_global_mmr64_address(pnode, offset)); 566 } 567 568 static inline unsigned char uv_read_global_mmr8(int pnode, unsigned long offset) 569 { 570 return readb(uv_global_mmr64_address(pnode, offset)); 571 } 572 573 /* 574 * Access hub local MMRs. Faster than using global space but only local MMRs 575 * are accessible. 576 */ 577 static inline unsigned long *uv_local_mmr_address(unsigned long offset) 578 { 579 return __va(UV_LOCAL_MMR_BASE | offset); 580 } 581 582 static inline unsigned long uv_read_local_mmr(unsigned long offset) 583 { 584 return readq(uv_local_mmr_address(offset)); 585 } 586 587 static inline void uv_write_local_mmr(unsigned long offset, unsigned long val) 588 { 589 writeq(val, uv_local_mmr_address(offset)); 590 } 591 592 static inline unsigned char uv_read_local_mmr8(unsigned long offset) 593 { 594 return readb(uv_local_mmr_address(offset)); 595 } 596 597 static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val) 598 { 599 writeb(val, uv_local_mmr_address(offset)); 600 } 601 602 /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */ 603 static inline int uv_blade_processor_id(void) 604 { 605 return uv_cpu_info->blade_cpu_id; 606 } 607 608 /* Blade-local cpu number of cpu N. Numbered 0 .. <# cpus on the blade> */ 609 static inline int uv_cpu_blade_processor_id(int cpu) 610 { 611 return uv_cpu_info_per(cpu)->blade_cpu_id; 612 } 613 #define _uv_cpu_blade_processor_id 1 /* indicate function available */ 614 615 /* Blade number to Node number (UV1..UV4 is 1:1) */ 616 static inline int uv_blade_to_node(int blade) 617 { 618 return blade; 619 } 620 621 /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */ 622 static inline int uv_numa_blade_id(void) 623 { 624 return uv_hub_info->numa_blade_id; 625 } 626 627 /* 628 * Convert linux node number to the UV blade number. 629 * .. Currently for UV1 thru UV4 the node and the blade are identical. 630 * .. If this changes then you MUST check references to this function! 631 */ 632 static inline int uv_node_to_blade_id(int nid) 633 { 634 return nid; 635 } 636 637 /* Convert a cpu number to the the UV blade number */ 638 static inline int uv_cpu_to_blade_id(int cpu) 639 { 640 return uv_node_to_blade_id(cpu_to_node(cpu)); 641 } 642 643 /* Convert a blade id to the PNODE of the blade */ 644 static inline int uv_blade_to_pnode(int bid) 645 { 646 return uv_hub_info_list(uv_blade_to_node(bid))->pnode; 647 } 648 649 /* Nid of memory node on blade. -1 if no blade-local memory */ 650 static inline int uv_blade_to_memory_nid(int bid) 651 { 652 return uv_hub_info_list(uv_blade_to_node(bid))->memory_nid; 653 } 654 655 /* Determine the number of possible cpus on a blade */ 656 static inline int uv_blade_nr_possible_cpus(int bid) 657 { 658 return uv_hub_info_list(uv_blade_to_node(bid))->nr_possible_cpus; 659 } 660 661 /* Determine the number of online cpus on a blade */ 662 static inline int uv_blade_nr_online_cpus(int bid) 663 { 664 return uv_hub_info_list(uv_blade_to_node(bid))->nr_online_cpus; 665 } 666 667 /* Convert a cpu id to the PNODE of the blade containing the cpu */ 668 static inline int uv_cpu_to_pnode(int cpu) 669 { 670 return uv_cpu_hub_info(cpu)->pnode; 671 } 672 673 /* Convert a linux node number to the PNODE of the blade */ 674 static inline int uv_node_to_pnode(int nid) 675 { 676 return uv_hub_info_list(nid)->pnode; 677 } 678 679 /* Maximum possible number of blades */ 680 extern short uv_possible_blades; 681 static inline int uv_num_possible_blades(void) 682 { 683 return uv_possible_blades; 684 } 685 686 /* Per Hub NMI support */ 687 extern void uv_nmi_setup(void); 688 689 /* BMC sets a bit this MMR non-zero before sending an NMI */ 690 #define UVH_NMI_MMR UVH_SCRATCH5 691 #define UVH_NMI_MMR_CLEAR UVH_SCRATCH5_ALIAS 692 #define UVH_NMI_MMR_SHIFT 63 693 #define UVH_NMI_MMR_TYPE "SCRATCH5" 694 695 /* Newer SMM NMI handler, not present in all systems */ 696 #define UVH_NMI_MMRX UVH_EVENT_OCCURRED0 697 #define UVH_NMI_MMRX_CLEAR UVH_EVENT_OCCURRED0_ALIAS 698 #define UVH_NMI_MMRX_SHIFT UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT 699 #define UVH_NMI_MMRX_TYPE "EXTIO_INT0" 700 701 /* Non-zero indicates newer SMM NMI handler present */ 702 #define UVH_NMI_MMRX_SUPPORTED UVH_EXTIO_INT0_BROADCAST 703 704 /* Indicates to BIOS that we want to use the newer SMM NMI handler */ 705 #define UVH_NMI_MMRX_REQ UVH_SCRATCH5_ALIAS_2 706 #define UVH_NMI_MMRX_REQ_SHIFT 62 707 708 struct uv_hub_nmi_s { 709 raw_spinlock_t nmi_lock; 710 atomic_t in_nmi; /* flag this node in UV NMI IRQ */ 711 atomic_t cpu_owner; /* last locker of this struct */ 712 atomic_t read_mmr_count; /* count of MMR reads */ 713 atomic_t nmi_count; /* count of true UV NMIs */ 714 unsigned long nmi_value; /* last value read from NMI MMR */ 715 }; 716 717 struct uv_cpu_nmi_s { 718 struct uv_hub_nmi_s *hub; 719 int state; 720 int pinging; 721 int queries; 722 int pings; 723 }; 724 725 DECLARE_PER_CPU(struct uv_cpu_nmi_s, uv_cpu_nmi); 726 727 #define uv_hub_nmi this_cpu_read(uv_cpu_nmi.hub) 728 #define uv_cpu_nmi_per(cpu) (per_cpu(uv_cpu_nmi, cpu)) 729 #define uv_hub_nmi_per(cpu) (uv_cpu_nmi_per(cpu).hub) 730 731 /* uv_cpu_nmi_states */ 732 #define UV_NMI_STATE_OUT 0 733 #define UV_NMI_STATE_IN 1 734 #define UV_NMI_STATE_DUMP 2 735 #define UV_NMI_STATE_DUMP_DONE 3 736 737 /* Update SCIR state */ 738 static inline void uv_set_scir_bits(unsigned char value) 739 { 740 if (uv_scir_info->state != value) { 741 uv_scir_info->state = value; 742 uv_write_local_mmr8(uv_scir_info->offset, value); 743 } 744 } 745 746 static inline unsigned long uv_scir_offset(int apicid) 747 { 748 return SCIR_LOCAL_MMR_BASE | (apicid & 0x3f); 749 } 750 751 static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value) 752 { 753 if (uv_cpu_scir_info(cpu)->state != value) { 754 uv_write_global_mmr8(uv_cpu_to_pnode(cpu), 755 uv_cpu_scir_info(cpu)->offset, value); 756 uv_cpu_scir_info(cpu)->state = value; 757 } 758 } 759 760 extern unsigned int uv_apicid_hibits; 761 static unsigned long uv_hub_ipi_value(int apicid, int vector, int mode) 762 { 763 apicid |= uv_apicid_hibits; 764 return (1UL << UVH_IPI_INT_SEND_SHFT) | 765 ((apicid) << UVH_IPI_INT_APIC_ID_SHFT) | 766 (mode << UVH_IPI_INT_DELIVERY_MODE_SHFT) | 767 (vector << UVH_IPI_INT_VECTOR_SHFT); 768 } 769 770 static inline void uv_hub_send_ipi(int pnode, int apicid, int vector) 771 { 772 unsigned long val; 773 unsigned long dmode = dest_Fixed; 774 775 if (vector == NMI_VECTOR) 776 dmode = dest_NMI; 777 778 val = uv_hub_ipi_value(apicid, vector, dmode); 779 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 780 } 781 782 /* 783 * Get the minimum revision number of the hub chips within the partition. 784 * (See UVx_HUB_REVISION_BASE above for specific values.) 785 */ 786 static inline int uv_get_min_hub_revision_id(void) 787 { 788 return uv_hub_info->hub_revision; 789 } 790 791 #endif /* CONFIG_X86_64 */ 792 #endif /* _ASM_X86_UV_UV_HUB_H */ 793