1bb898558SAl Viro /* 2bb898558SAl Viro * This file is subject to the terms and conditions of the GNU General Public 3bb898558SAl Viro * License. See the file "COPYING" in the main directory of this archive 4bb898558SAl Viro * for more details. 5bb898558SAl Viro * 6bb898558SAl Viro * SGI UV architectural definitions 7bb898558SAl Viro * 85f40f7d9SDimitri Sivanich * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved. 9bb898558SAl Viro */ 10bb898558SAl Viro 1105e4d316SH. Peter Anvin #ifndef _ASM_X86_UV_UV_HUB_H 1205e4d316SH. Peter Anvin #define _ASM_X86_UV_UV_HUB_H 13bb898558SAl Viro 14bc5d9940SJack Steiner #ifdef CONFIG_X86_64 15bb898558SAl Viro #include <linux/numa.h> 16bb898558SAl Viro #include <linux/percpu.h> 17c08b6accSMike Travis #include <linux/timer.h> 188dc579e8SJack Steiner #include <linux/io.h> 19bb898558SAl Viro #include <asm/types.h> 20bb898558SAl Viro #include <asm/percpu.h> 2166666e50SJack Steiner #include <asm/uv/uv_mmrs.h> 2202dd0a06SRobin Holt #include <asm/irq_vectors.h> 2302dd0a06SRobin Holt #include <asm/io_apic.h> 24bb898558SAl Viro 25bb898558SAl Viro 26bb898558SAl Viro /* 27bb898558SAl Viro * Addressing Terminology 28bb898558SAl Viro * 29bb898558SAl Viro * M - The low M bits of a physical address represent the offset 30bb898558SAl Viro * into the blade local memory. RAM memory on a blade is physically 31bb898558SAl Viro * contiguous (although various IO spaces may punch holes in 32bb898558SAl Viro * it).. 33bb898558SAl Viro * 34bb898558SAl Viro * N - Number of bits in the node portion of a socket physical 35bb898558SAl Viro * address. 36bb898558SAl Viro * 37bb898558SAl Viro * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of 38bb898558SAl Viro * routers always have low bit of 1, C/MBricks have low bit 39bb898558SAl Viro * equal to 0. Most addressing macros that target UV hub chips 40bb898558SAl Viro * right shift the NASID by 1 to exclude the always-zero bit. 41bb898558SAl Viro * NASIDs contain up to 15 bits. 42bb898558SAl Viro * 43bb898558SAl Viro * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead 44bb898558SAl Viro * of nasids. 45bb898558SAl Viro * 46bb898558SAl Viro * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant 47bb898558SAl Viro * of the nasid for socket usage. 48bb898558SAl Viro * 496a469e46SJack Steiner * GPA - (global physical address) a socket physical address converted 506a469e46SJack Steiner * so that it can be used by the GRU as a global address. Socket 516a469e46SJack Steiner * physical addresses 1) need additional NASID (node) bits added 526a469e46SJack Steiner * to the high end of the address, and 2) unaliased if the 536a469e46SJack Steiner * partition does not have a physical address 0. In addition, on 546a469e46SJack Steiner * UV2 rev 1, GPAs need the gnode left shifted to bits 39 or 40. 556a469e46SJack Steiner * 56bb898558SAl Viro * 57bb898558SAl Viro * NumaLink Global Physical Address Format: 58bb898558SAl Viro * +--------------------------------+---------------------+ 59bb898558SAl Viro * |00..000| GNODE | NodeOffset | 60bb898558SAl Viro * +--------------------------------+---------------------+ 61bb898558SAl Viro * |<-------53 - M bits --->|<--------M bits -----> 62bb898558SAl Viro * 63bb898558SAl Viro * M - number of node offset bits (35 .. 40) 64bb898558SAl Viro * 65bb898558SAl Viro * 66bb898558SAl Viro * Memory/UV-HUB Processor Socket Address Format: 67bb898558SAl Viro * +----------------+---------------+---------------------+ 68bb898558SAl Viro * |00..000000000000| PNODE | NodeOffset | 69bb898558SAl Viro * +----------------+---------------+---------------------+ 70bb898558SAl Viro * <--- N bits --->|<--------M bits -----> 71bb898558SAl Viro * 72bb898558SAl Viro * M - number of node offset bits (35 .. 40) 73bb898558SAl Viro * N - number of PNODE bits (0 .. 10) 74bb898558SAl Viro * 75bb898558SAl Viro * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64). 76bb898558SAl Viro * The actual values are configuration dependent and are set at 77bb898558SAl Viro * boot time. M & N values are set by the hardware/BIOS at boot. 78bb898558SAl Viro * 79bb898558SAl Viro * 80bb898558SAl Viro * APICID format 81bb898558SAl Viro * NOTE!!!!!! This is the current format of the APICID. However, code 82bb898558SAl Viro * should assume that this will change in the future. Use functions 83bb898558SAl Viro * in this file for all APICID bit manipulations and conversion. 84bb898558SAl Viro * 85bb898558SAl Viro * 1111110000000000 86bb898558SAl Viro * 5432109876543210 872a919596SJack Steiner * pppppppppplc0cch Nehalem-EX (12 bits in hdw reg) 882a919596SJack Steiner * ppppppppplcc0cch Westmere-EX (12 bits in hdw reg) 892a919596SJack Steiner * pppppppppppcccch SandyBridge (15 bits in hdw reg) 90bb898558SAl Viro * sssssssssss 91bb898558SAl Viro * 92bb898558SAl Viro * p = pnode bits 93bb898558SAl Viro * l = socket number on board 94bb898558SAl Viro * c = core 95bb898558SAl Viro * h = hyperthread 96bb898558SAl Viro * s = bits that are in the SOCKET_ID CSR 97bb898558SAl Viro * 982a919596SJack Steiner * Note: Processor may support fewer bits in the APICID register. The ACPI 99bb898558SAl Viro * tables hold all 16 bits. Software needs to be aware of this. 100bb898558SAl Viro * 101bb898558SAl Viro * Unless otherwise specified, all references to APICID refer to 102bb898558SAl Viro * the FULL value contained in ACPI tables, not the subset in the 103bb898558SAl Viro * processor APICID register. 104bb898558SAl Viro */ 105bb898558SAl Viro 106bb898558SAl Viro 107bb898558SAl Viro /* 108bb898558SAl Viro * Maximum number of bricks in all partitions and in all coherency domains. 109bb898558SAl Viro * This is the total number of bricks accessible in the numalink fabric. It 110bb898558SAl Viro * includes all C & M bricks. Routers are NOT included. 111bb898558SAl Viro * 112bb898558SAl Viro * This value is also the value of the maximum number of non-router NASIDs 113bb898558SAl Viro * in the numalink fabric. 114bb898558SAl Viro * 115bb898558SAl Viro * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused. 116bb898558SAl Viro */ 117bb898558SAl Viro #define UV_MAX_NUMALINK_BLADES 16384 118bb898558SAl Viro 119bb898558SAl Viro /* 120bb898558SAl Viro * Maximum number of C/Mbricks within a software SSI (hardware may support 121bb898558SAl Viro * more). 122bb898558SAl Viro */ 123bb898558SAl Viro #define UV_MAX_SSI_BLADES 256 124bb898558SAl Viro 125bb898558SAl Viro /* 126bb898558SAl Viro * The largest possible NASID of a C or M brick (+ 2) 127bb898558SAl Viro */ 1281d21e6e3SRobin Holt #define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_BLADES * 2) 129bb898558SAl Viro 1307f1baa06SMike Travis struct uv_scir_s { 1317f1baa06SMike Travis struct timer_list timer; 1327f1baa06SMike Travis unsigned long offset; 1337f1baa06SMike Travis unsigned long last; 1347f1baa06SMike Travis unsigned long idle_on; 1357f1baa06SMike Travis unsigned long idle_off; 1367f1baa06SMike Travis unsigned char state; 1377f1baa06SMike Travis unsigned char enabled; 1387f1baa06SMike Travis }; 1397f1baa06SMike Travis 140bb898558SAl Viro /* 141bb898558SAl Viro * The following defines attributes of the HUB chip. These attributes are 142bb898558SAl Viro * frequently referenced and are kept in the per-cpu data areas of each cpu. 143bb898558SAl Viro * They are kept together in a struct to minimize cache misses. 144bb898558SAl Viro */ 145bb898558SAl Viro struct uv_hub_info_s { 146bb898558SAl Viro unsigned long global_mmr_base; 147bb898558SAl Viro unsigned long gpa_mask; 148c4ed3f04SJack Steiner unsigned int gnode_extra; 1492a919596SJack Steiner unsigned char hub_revision; 1502a919596SJack Steiner unsigned char apic_pnode_shift; 1516a469e46SJack Steiner unsigned char m_shift; 1526a469e46SJack Steiner unsigned char n_lshift; 153bb898558SAl Viro unsigned long gnode_upper; 154bb898558SAl Viro unsigned long lowmem_remap_top; 155bb898558SAl Viro unsigned long lowmem_remap_base; 156bb898558SAl Viro unsigned short pnode; 157bb898558SAl Viro unsigned short pnode_mask; 158bb898558SAl Viro unsigned short coherency_domain_number; 159bb898558SAl Viro unsigned short numa_blade_id; 160bb898558SAl Viro unsigned char blade_processor_id; 161bb898558SAl Viro unsigned char m_val; 162bb898558SAl Viro unsigned char n_val; 1637f1baa06SMike Travis struct uv_scir_s scir; 164bb898558SAl Viro }; 1657f1baa06SMike Travis 166bb898558SAl Viro DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); 16789cbc767SChristoph Lameter #define uv_hub_info this_cpu_ptr(&__uv_hub_info) 168bb898558SAl Viro #define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu)) 169bb898558SAl Viro 1702a919596SJack Steiner /* 1712a919596SJack Steiner * Hub revisions less than UV2_HUB_REVISION_BASE are UV1 hubs. All UV2 1722a919596SJack Steiner * hubs have revision numbers greater than or equal to UV2_HUB_REVISION_BASE. 1732a919596SJack Steiner * This is a software convention - NOT the hardware revision numbers in 1742a919596SJack Steiner * the hub chip. 1752a919596SJack Steiner */ 1762a919596SJack Steiner #define UV1_HUB_REVISION_BASE 1 1772a919596SJack Steiner #define UV2_HUB_REVISION_BASE 3 1786edbd471SMike Travis #define UV3_HUB_REVISION_BASE 5 179eb1e3461SMike Travis #define UV4_HUB_REVISION_BASE 7 1802a919596SJack Steiner 1812a919596SJack Steiner static inline int is_uv1_hub(void) 1822a919596SJack Steiner { 1832a919596SJack Steiner return uv_hub_info->hub_revision < UV2_HUB_REVISION_BASE; 1842a919596SJack Steiner } 1852a919596SJack Steiner 1862a919596SJack Steiner static inline int is_uv2_hub(void) 1872a919596SJack Steiner { 1886edbd471SMike Travis return ((uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE) && 1896edbd471SMike Travis (uv_hub_info->hub_revision < UV3_HUB_REVISION_BASE)); 1906edbd471SMike Travis } 1916edbd471SMike Travis 1926edbd471SMike Travis static inline int is_uv3_hub(void) 1936edbd471SMike Travis { 194eb1e3461SMike Travis return ((uv_hub_info->hub_revision >= UV3_HUB_REVISION_BASE) && 195eb1e3461SMike Travis (uv_hub_info->hub_revision < UV4_HUB_REVISION_BASE)); 1966edbd471SMike Travis } 1976edbd471SMike Travis 198eb1e3461SMike Travis #ifdef UV4_HUB_IS_SUPPORTED 199eb1e3461SMike Travis static inline int is_uv4_hub(void) 200eb1e3461SMike Travis { 201eb1e3461SMike Travis return uv_hub_info->hub_revision >= UV4_HUB_REVISION_BASE; 202eb1e3461SMike Travis } 203eb1e3461SMike Travis #else 204eb1e3461SMike Travis static inline int is_uv4_hub(void) 205eb1e3461SMike Travis { 206eb1e3461SMike Travis return 0; 207eb1e3461SMike Travis } 208eb1e3461SMike Travis #endif 209eb1e3461SMike Travis 2106edbd471SMike Travis static inline int is_uv_hub(void) 2116edbd471SMike Travis { 2126edbd471SMike Travis return uv_hub_info->hub_revision; 2136edbd471SMike Travis } 2146edbd471SMike Travis 215eb1e3461SMike Travis /* code common to uv2/3/4 only */ 2166edbd471SMike Travis static inline int is_uvx_hub(void) 2176edbd471SMike Travis { 2182a919596SJack Steiner return uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE; 2192a919596SJack Steiner } 2202a919596SJack Steiner 221c8f730b1SRuss Anderson union uvh_apicid { 222c8f730b1SRuss Anderson unsigned long v; 223c8f730b1SRuss Anderson struct uvh_apicid_s { 224c8f730b1SRuss Anderson unsigned long local_apic_mask : 24; 225c8f730b1SRuss Anderson unsigned long local_apic_shift : 5; 226c8f730b1SRuss Anderson unsigned long unused1 : 3; 227c8f730b1SRuss Anderson unsigned long pnode_mask : 24; 228c8f730b1SRuss Anderson unsigned long pnode_shift : 5; 229c8f730b1SRuss Anderson unsigned long unused2 : 3; 230c8f730b1SRuss Anderson } s; 231c8f730b1SRuss Anderson }; 232c8f730b1SRuss Anderson 233bb898558SAl Viro /* 234bb898558SAl Viro * Local & Global MMR space macros. 235bb898558SAl Viro * Note: macros are intended to be used ONLY by inline functions 236bb898558SAl Viro * in this file - not by other kernel code. 237bb898558SAl Viro * n - NASID (full 15-bit global nasid) 238bb898558SAl Viro * g - GNODE (full 15-bit global nasid, right shifted 1) 239bb898558SAl Viro * p - PNODE (local part of nsids, right shifted 1) 240bb898558SAl Viro */ 241bb898558SAl Viro #define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask) 242c4ed3f04SJack Steiner #define UV_PNODE_TO_GNODE(p) ((p) |uv_hub_info->gnode_extra) 243c4ed3f04SJack Steiner #define UV_PNODE_TO_NASID(p) (UV_PNODE_TO_GNODE(p) << 1) 244bb898558SAl Viro 2452a919596SJack Steiner #define UV1_LOCAL_MMR_BASE 0xf4000000UL 2462a919596SJack Steiner #define UV1_GLOBAL_MMR32_BASE 0xf8000000UL 2472a919596SJack Steiner #define UV1_LOCAL_MMR_SIZE (64UL * 1024 * 1024) 2482a919596SJack Steiner #define UV1_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024) 2492a919596SJack Steiner 2502a919596SJack Steiner #define UV2_LOCAL_MMR_BASE 0xfa000000UL 2512a919596SJack Steiner #define UV2_GLOBAL_MMR32_BASE 0xfc000000UL 2522a919596SJack Steiner #define UV2_LOCAL_MMR_SIZE (32UL * 1024 * 1024) 2532a919596SJack Steiner #define UV2_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024) 2542a919596SJack Steiner 2556edbd471SMike Travis #define UV3_LOCAL_MMR_BASE 0xfa000000UL 2566edbd471SMike Travis #define UV3_GLOBAL_MMR32_BASE 0xfc000000UL 2576edbd471SMike Travis #define UV3_LOCAL_MMR_SIZE (32UL * 1024 * 1024) 2586edbd471SMike Travis #define UV3_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024) 2596edbd471SMike Travis 260eb1e3461SMike Travis #define UV4_LOCAL_MMR_BASE 0xfa000000UL 261eb1e3461SMike Travis #define UV4_GLOBAL_MMR32_BASE 0xfc000000UL 262eb1e3461SMike Travis #define UV4_LOCAL_MMR_SIZE (32UL * 1024 * 1024) 263eb1e3461SMike Travis #define UV4_GLOBAL_MMR32_SIZE (16UL * 1024 * 1024) 264eb1e3461SMike Travis 265eb1e3461SMike Travis #define UV_LOCAL_MMR_BASE ( \ 266eb1e3461SMike Travis is_uv1_hub() ? UV1_LOCAL_MMR_BASE : \ 267eb1e3461SMike Travis is_uv2_hub() ? UV2_LOCAL_MMR_BASE : \ 268eb1e3461SMike Travis is_uv3_hub() ? UV3_LOCAL_MMR_BASE : \ 269eb1e3461SMike Travis /*is_uv4_hub*/ UV4_LOCAL_MMR_BASE) 270eb1e3461SMike Travis 271eb1e3461SMike Travis #define UV_GLOBAL_MMR32_BASE ( \ 272eb1e3461SMike Travis is_uv1_hub() ? UV1_GLOBAL_MMR32_BASE : \ 273eb1e3461SMike Travis is_uv2_hub() ? UV2_GLOBAL_MMR32_BASE : \ 274eb1e3461SMike Travis is_uv3_hub() ? UV3_GLOBAL_MMR32_BASE : \ 275eb1e3461SMike Travis /*is_uv4_hub*/ UV4_GLOBAL_MMR32_BASE) 276eb1e3461SMike Travis 277eb1e3461SMike Travis #define UV_LOCAL_MMR_SIZE ( \ 278eb1e3461SMike Travis is_uv1_hub() ? UV1_LOCAL_MMR_SIZE : \ 279eb1e3461SMike Travis is_uv2_hub() ? UV2_LOCAL_MMR_SIZE : \ 280eb1e3461SMike Travis is_uv3_hub() ? UV3_LOCAL_MMR_SIZE : \ 281eb1e3461SMike Travis /*is_uv4_hub*/ UV4_LOCAL_MMR_SIZE) 282eb1e3461SMike Travis 283eb1e3461SMike Travis #define UV_GLOBAL_MMR32_SIZE ( \ 284eb1e3461SMike Travis is_uv1_hub() ? UV1_GLOBAL_MMR32_SIZE : \ 285eb1e3461SMike Travis is_uv2_hub() ? UV2_GLOBAL_MMR32_SIZE : \ 286eb1e3461SMike Travis is_uv3_hub() ? UV3_GLOBAL_MMR32_SIZE : \ 287eb1e3461SMike Travis /*is_uv4_hub*/ UV4_GLOBAL_MMR32_SIZE) 288eb1e3461SMike Travis 289bb898558SAl Viro #define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base) 290bb898558SAl Viro 29156abcf24SJack Steiner #define UV_GLOBAL_GRU_MMR_BASE 0x4000000 29256abcf24SJack Steiner 293bb898558SAl Viro #define UV_GLOBAL_MMR32_PNODE_SHIFT 15 294bb898558SAl Viro #define UV_GLOBAL_MMR64_PNODE_SHIFT 26 295bb898558SAl Viro 296bb898558SAl Viro #define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT)) 297bb898558SAl Viro 298bb898558SAl Viro #define UV_GLOBAL_MMR64_PNODE_BITS(p) \ 29967e83f30SJack Steiner (((unsigned long)(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT) 300bb898558SAl Viro 301c8f730b1SRuss Anderson #define UVH_APICID 0x002D0E00L 302bb898558SAl Viro #define UV_APIC_PNODE_SHIFT 6 303bb898558SAl Viro 3048191c9f6SDimitri Sivanich #define UV_APICID_HIBIT_MASK 0xffff0000 3058191c9f6SDimitri Sivanich 3067f1baa06SMike Travis /* Local Bus from cpu's perspective */ 3077f1baa06SMike Travis #define LOCAL_BUS_BASE 0x1c00000 3087f1baa06SMike Travis #define LOCAL_BUS_SIZE (4 * 1024 * 1024) 3097f1baa06SMike Travis 3107f1baa06SMike Travis /* 3117f1baa06SMike Travis * System Controller Interface Reg 3127f1baa06SMike Travis * 3137f1baa06SMike Travis * Note there are NO leds on a UV system. This register is only 3147f1baa06SMike Travis * used by the system controller to monitor system-wide operation. 3157f1baa06SMike Travis * There are 64 regs per node. With Nahelem cpus (2 cores per node, 3167f1baa06SMike Travis * 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on 3177f1baa06SMike Travis * a node. 3187f1baa06SMike Travis * 3197f1baa06SMike Travis * The window is located at top of ACPI MMR space 3207f1baa06SMike Travis */ 3217f1baa06SMike Travis #define SCIR_WINDOW_COUNT 64 3227f1baa06SMike Travis #define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \ 3237f1baa06SMike Travis LOCAL_BUS_SIZE - \ 3247f1baa06SMike Travis SCIR_WINDOW_COUNT) 3257f1baa06SMike Travis 3267f1baa06SMike Travis #define SCIR_CPU_HEARTBEAT 0x01 /* timer interrupt */ 3277f1baa06SMike Travis #define SCIR_CPU_ACTIVITY 0x02 /* not idle */ 3287f1baa06SMike Travis #define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */ 3297f1baa06SMike Travis 3308661984fSDimitri Sivanich /* Loop through all installed blades */ 3318661984fSDimitri Sivanich #define for_each_possible_blade(bid) \ 3328661984fSDimitri Sivanich for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++) 3338661984fSDimitri Sivanich 334bb898558SAl Viro /* 335bb898558SAl Viro * Macros for converting between kernel virtual addresses, socket local physical 336bb898558SAl Viro * addresses, and UV global physical addresses. 337bb898558SAl Viro * Note: use the standard __pa() & __va() macros for converting 338bb898558SAl Viro * between socket virtual and socket physical addresses. 339bb898558SAl Viro */ 340bb898558SAl Viro 341bb898558SAl Viro /* socket phys RAM --> UV global physical address */ 342bb898558SAl Viro static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr) 343bb898558SAl Viro { 344bb898558SAl Viro if (paddr < uv_hub_info->lowmem_remap_top) 345189f67c4SJack Steiner paddr |= uv_hub_info->lowmem_remap_base; 3466a469e46SJack Steiner paddr |= uv_hub_info->gnode_upper; 3476a469e46SJack Steiner paddr = ((paddr << uv_hub_info->m_shift) >> uv_hub_info->m_shift) | 3486a469e46SJack Steiner ((paddr >> uv_hub_info->m_val) << uv_hub_info->n_lshift); 3496a469e46SJack Steiner return paddr; 350bb898558SAl Viro } 351bb898558SAl Viro 352bb898558SAl Viro 353bb898558SAl Viro /* socket virtual --> UV global physical address */ 354bb898558SAl Viro static inline unsigned long uv_gpa(void *v) 355bb898558SAl Viro { 356189f67c4SJack Steiner return uv_soc_phys_ram_to_gpa(__pa(v)); 357bb898558SAl Viro } 358bb898558SAl Viro 359fae419f2SRobin Holt /* Top two bits indicate the requested address is in MMR space. */ 360fae419f2SRobin Holt static inline int 361fae419f2SRobin Holt uv_gpa_in_mmr_space(unsigned long gpa) 362fae419f2SRobin Holt { 363fae419f2SRobin Holt return (gpa >> 62) == 0x3UL; 364fae419f2SRobin Holt } 365fae419f2SRobin Holt 366729d69e6SRobin Holt /* UV global physical address --> socket phys RAM */ 367729d69e6SRobin Holt static inline unsigned long uv_gpa_to_soc_phys_ram(unsigned long gpa) 368729d69e6SRobin Holt { 3695a51467bSRuss Anderson unsigned long paddr; 370729d69e6SRobin Holt unsigned long remap_base = uv_hub_info->lowmem_remap_base; 371729d69e6SRobin Holt unsigned long remap_top = uv_hub_info->lowmem_remap_top; 372729d69e6SRobin Holt 3736a469e46SJack Steiner gpa = ((gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift) | 3746a469e46SJack Steiner ((gpa >> uv_hub_info->n_lshift) << uv_hub_info->m_val); 3755a51467bSRuss Anderson paddr = gpa & uv_hub_info->gpa_mask; 376729d69e6SRobin Holt if (paddr >= remap_base && paddr < remap_base + remap_top) 377729d69e6SRobin Holt paddr -= remap_base; 378729d69e6SRobin Holt return paddr; 379729d69e6SRobin Holt } 380729d69e6SRobin Holt 381729d69e6SRobin Holt 3826a469e46SJack Steiner /* gpa -> pnode */ 3831d21e6e3SRobin Holt static inline unsigned long uv_gpa_to_gnode(unsigned long gpa) 3841d21e6e3SRobin Holt { 3856a469e46SJack Steiner return gpa >> uv_hub_info->n_lshift; 3861d21e6e3SRobin Holt } 3871d21e6e3SRobin Holt 3881d21e6e3SRobin Holt /* gpa -> pnode */ 3891d21e6e3SRobin Holt static inline int uv_gpa_to_pnode(unsigned long gpa) 3901d21e6e3SRobin Holt { 3911d21e6e3SRobin Holt unsigned long n_mask = (1UL << uv_hub_info->n_val) - 1; 3921d21e6e3SRobin Holt 3931d21e6e3SRobin Holt return uv_gpa_to_gnode(gpa) & n_mask; 3941d21e6e3SRobin Holt } 3951d21e6e3SRobin Holt 3966a469e46SJack Steiner /* gpa -> node offset*/ 3976a469e46SJack Steiner static inline unsigned long uv_gpa_to_offset(unsigned long gpa) 3986a469e46SJack Steiner { 3996a469e46SJack Steiner return (gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift; 4006a469e46SJack Steiner } 4016a469e46SJack Steiner 402bb898558SAl Viro /* pnode, offset --> socket virtual */ 403bb898558SAl Viro static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset) 404bb898558SAl Viro { 405bb898558SAl Viro return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset); 406bb898558SAl Viro } 407bb898558SAl Viro 408bb898558SAl Viro 409bb898558SAl Viro /* 410bb898558SAl Viro * Extract a PNODE from an APICID (full apicid, not processor subset) 411bb898558SAl Viro */ 412bb898558SAl Viro static inline int uv_apicid_to_pnode(int apicid) 413bb898558SAl Viro { 414c8f730b1SRuss Anderson return (apicid >> uv_hub_info->apic_pnode_shift); 415bb898558SAl Viro } 416bb898558SAl Viro 417bb898558SAl Viro /* 4182a919596SJack Steiner * Convert an apicid to the socket number on the blade 4192a919596SJack Steiner */ 4202a919596SJack Steiner static inline int uv_apicid_to_socket(int apicid) 4212a919596SJack Steiner { 4222a919596SJack Steiner if (is_uv1_hub()) 4232a919596SJack Steiner return (apicid >> (uv_hub_info->apic_pnode_shift - 1)) & 1; 4242a919596SJack Steiner else 4252a919596SJack Steiner return 0; 4262a919596SJack Steiner } 4272a919596SJack Steiner 4282a919596SJack Steiner /* 429bb898558SAl Viro * Access global MMRs using the low memory MMR32 space. This region supports 430bb898558SAl Viro * faster MMR access but not all MMRs are accessible in this space. 431bb898558SAl Viro */ 43239d30770SMike Travis static inline unsigned long *uv_global_mmr32_address(int pnode, unsigned long offset) 433bb898558SAl Viro { 434bb898558SAl Viro return __va(UV_GLOBAL_MMR32_BASE | 435bb898558SAl Viro UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset); 436bb898558SAl Viro } 437bb898558SAl Viro 43839d30770SMike Travis static inline void uv_write_global_mmr32(int pnode, unsigned long offset, unsigned long val) 439bb898558SAl Viro { 4408dc579e8SJack Steiner writeq(val, uv_global_mmr32_address(pnode, offset)); 441bb898558SAl Viro } 442bb898558SAl Viro 44339d30770SMike Travis static inline unsigned long uv_read_global_mmr32(int pnode, unsigned long offset) 444bb898558SAl Viro { 4458dc579e8SJack Steiner return readq(uv_global_mmr32_address(pnode, offset)); 446bb898558SAl Viro } 447bb898558SAl Viro 448bb898558SAl Viro /* 449bb898558SAl Viro * Access Global MMR space using the MMR space located at the top of physical 450bb898558SAl Viro * memory. 451bb898558SAl Viro */ 452a289cc7cSRandy Dunlap static inline volatile void __iomem *uv_global_mmr64_address(int pnode, unsigned long offset) 453bb898558SAl Viro { 454bb898558SAl Viro return __va(UV_GLOBAL_MMR64_BASE | 455bb898558SAl Viro UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset); 456bb898558SAl Viro } 457bb898558SAl Viro 45839d30770SMike Travis static inline void uv_write_global_mmr64(int pnode, unsigned long offset, unsigned long val) 459bb898558SAl Viro { 4608dc579e8SJack Steiner writeq(val, uv_global_mmr64_address(pnode, offset)); 461bb898558SAl Viro } 462bb898558SAl Viro 46339d30770SMike Travis static inline unsigned long uv_read_global_mmr64(int pnode, unsigned long offset) 464bb898558SAl Viro { 4658dc579e8SJack Steiner return readq(uv_global_mmr64_address(pnode, offset)); 466bb898558SAl Viro } 467bb898558SAl Viro 468bb898558SAl Viro /* 46956abcf24SJack Steiner * Global MMR space addresses when referenced by the GRU. (GRU does 47056abcf24SJack Steiner * NOT use socket addressing). 47156abcf24SJack Steiner */ 47256abcf24SJack Steiner static inline unsigned long uv_global_gru_mmr_address(int pnode, unsigned long offset) 47356abcf24SJack Steiner { 474e1e0138dSJack Steiner return UV_GLOBAL_GRU_MMR_BASE | offset | 475e1e0138dSJack Steiner ((unsigned long)pnode << uv_hub_info->m_val); 47656abcf24SJack Steiner } 47756abcf24SJack Steiner 47839d30770SMike Travis static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val) 47939d30770SMike Travis { 48039d30770SMike Travis writeb(val, uv_global_mmr64_address(pnode, offset)); 48139d30770SMike Travis } 48239d30770SMike Travis 48339d30770SMike Travis static inline unsigned char uv_read_global_mmr8(int pnode, unsigned long offset) 48439d30770SMike Travis { 48539d30770SMike Travis return readb(uv_global_mmr64_address(pnode, offset)); 48639d30770SMike Travis } 48739d30770SMike Travis 48856abcf24SJack Steiner /* 489bb898558SAl Viro * Access hub local MMRs. Faster than using global space but only local MMRs 490bb898558SAl Viro * are accessible. 491bb898558SAl Viro */ 492bb898558SAl Viro static inline unsigned long *uv_local_mmr_address(unsigned long offset) 493bb898558SAl Viro { 494bb898558SAl Viro return __va(UV_LOCAL_MMR_BASE | offset); 495bb898558SAl Viro } 496bb898558SAl Viro 497bb898558SAl Viro static inline unsigned long uv_read_local_mmr(unsigned long offset) 498bb898558SAl Viro { 4998dc579e8SJack Steiner return readq(uv_local_mmr_address(offset)); 500bb898558SAl Viro } 501bb898558SAl Viro 502bb898558SAl Viro static inline void uv_write_local_mmr(unsigned long offset, unsigned long val) 503bb898558SAl Viro { 5048dc579e8SJack Steiner writeq(val, uv_local_mmr_address(offset)); 505bb898558SAl Viro } 506bb898558SAl Viro 5077f1baa06SMike Travis static inline unsigned char uv_read_local_mmr8(unsigned long offset) 5087f1baa06SMike Travis { 5098dc579e8SJack Steiner return readb(uv_local_mmr_address(offset)); 5107f1baa06SMike Travis } 5117f1baa06SMike Travis 5127f1baa06SMike Travis static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val) 5137f1baa06SMike Travis { 5148dc579e8SJack Steiner writeb(val, uv_local_mmr_address(offset)); 5157f1baa06SMike Travis } 5167f1baa06SMike Travis 517bb898558SAl Viro /* 518bb898558SAl Viro * Structures and definitions for converting between cpu, node, pnode, and blade 519bb898558SAl Viro * numbers. 520bb898558SAl Viro */ 521bb898558SAl Viro struct uv_blade_info { 522bb898558SAl Viro unsigned short nr_possible_cpus; 523bb898558SAl Viro unsigned short nr_online_cpus; 524bb898558SAl Viro unsigned short pnode; 5256c7184b7SJack Steiner short memory_nid; 5260d12ef0cSMike Travis spinlock_t nmi_lock; /* obsolete, see uv_hub_nmi */ 5270d12ef0cSMike Travis unsigned long nmi_count; /* obsolete, see uv_hub_nmi */ 528bb898558SAl Viro }; 529bb898558SAl Viro extern struct uv_blade_info *uv_blade_info; 530bb898558SAl Viro extern short *uv_node_to_blade; 531bb898558SAl Viro extern short *uv_cpu_to_blade; 532bb898558SAl Viro extern short uv_possible_blades; 533bb898558SAl Viro 534bb898558SAl Viro /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */ 535bb898558SAl Viro static inline int uv_blade_processor_id(void) 536bb898558SAl Viro { 537bb898558SAl Viro return uv_hub_info->blade_processor_id; 538bb898558SAl Viro } 539bb898558SAl Viro 540bb898558SAl Viro /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */ 541bb898558SAl Viro static inline int uv_numa_blade_id(void) 542bb898558SAl Viro { 543bb898558SAl Viro return uv_hub_info->numa_blade_id; 544bb898558SAl Viro } 545bb898558SAl Viro 546bb898558SAl Viro /* Convert a cpu number to the the UV blade number */ 547bb898558SAl Viro static inline int uv_cpu_to_blade_id(int cpu) 548bb898558SAl Viro { 549bb898558SAl Viro return uv_cpu_to_blade[cpu]; 550bb898558SAl Viro } 551bb898558SAl Viro 552bb898558SAl Viro /* Convert linux node number to the UV blade number */ 553bb898558SAl Viro static inline int uv_node_to_blade_id(int nid) 554bb898558SAl Viro { 555bb898558SAl Viro return uv_node_to_blade[nid]; 556bb898558SAl Viro } 557bb898558SAl Viro 558bb898558SAl Viro /* Convert a blade id to the PNODE of the blade */ 559bb898558SAl Viro static inline int uv_blade_to_pnode(int bid) 560bb898558SAl Viro { 561bb898558SAl Viro return uv_blade_info[bid].pnode; 562bb898558SAl Viro } 563bb898558SAl Viro 5646c7184b7SJack Steiner /* Nid of memory node on blade. -1 if no blade-local memory */ 5656c7184b7SJack Steiner static inline int uv_blade_to_memory_nid(int bid) 5666c7184b7SJack Steiner { 5676c7184b7SJack Steiner return uv_blade_info[bid].memory_nid; 5686c7184b7SJack Steiner } 5696c7184b7SJack Steiner 570bb898558SAl Viro /* Determine the number of possible cpus on a blade */ 571bb898558SAl Viro static inline int uv_blade_nr_possible_cpus(int bid) 572bb898558SAl Viro { 573bb898558SAl Viro return uv_blade_info[bid].nr_possible_cpus; 574bb898558SAl Viro } 575bb898558SAl Viro 576bb898558SAl Viro /* Determine the number of online cpus on a blade */ 577bb898558SAl Viro static inline int uv_blade_nr_online_cpus(int bid) 578bb898558SAl Viro { 579bb898558SAl Viro return uv_blade_info[bid].nr_online_cpus; 580bb898558SAl Viro } 581bb898558SAl Viro 582bb898558SAl Viro /* Convert a cpu id to the PNODE of the blade containing the cpu */ 583bb898558SAl Viro static inline int uv_cpu_to_pnode(int cpu) 584bb898558SAl Viro { 585bb898558SAl Viro return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode; 586bb898558SAl Viro } 587bb898558SAl Viro 588bb898558SAl Viro /* Convert a linux node number to the PNODE of the blade */ 589bb898558SAl Viro static inline int uv_node_to_pnode(int nid) 590bb898558SAl Viro { 591bb898558SAl Viro return uv_blade_info[uv_node_to_blade_id(nid)].pnode; 592bb898558SAl Viro } 593bb898558SAl Viro 594bb898558SAl Viro /* Maximum possible number of blades */ 595bb898558SAl Viro static inline int uv_num_possible_blades(void) 596bb898558SAl Viro { 597bb898558SAl Viro return uv_possible_blades; 598bb898558SAl Viro } 599bb898558SAl Viro 6000d12ef0cSMike Travis /* Per Hub NMI support */ 6010d12ef0cSMike Travis extern void uv_nmi_setup(void); 6020d12ef0cSMike Travis 6030d12ef0cSMike Travis /* BMC sets a bit this MMR non-zero before sending an NMI */ 6040d12ef0cSMike Travis #define UVH_NMI_MMR UVH_SCRATCH5 6050d12ef0cSMike Travis #define UVH_NMI_MMR_CLEAR UVH_SCRATCH5_ALIAS 6060d12ef0cSMike Travis #define UVH_NMI_MMR_SHIFT 63 6070d12ef0cSMike Travis #define UVH_NMI_MMR_TYPE "SCRATCH5" 6080d12ef0cSMike Travis 6090d12ef0cSMike Travis /* Newer SMM NMI handler, not present in all systems */ 6100d12ef0cSMike Travis #define UVH_NMI_MMRX UVH_EVENT_OCCURRED0 6110d12ef0cSMike Travis #define UVH_NMI_MMRX_CLEAR UVH_EVENT_OCCURRED0_ALIAS 6120d12ef0cSMike Travis #define UVH_NMI_MMRX_SHIFT (is_uv1_hub() ? \ 6130d12ef0cSMike Travis UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT :\ 6140d12ef0cSMike Travis UVXH_EVENT_OCCURRED0_EXTIO_INT0_SHFT) 6150d12ef0cSMike Travis #define UVH_NMI_MMRX_TYPE "EXTIO_INT0" 6160d12ef0cSMike Travis 6170d12ef0cSMike Travis /* Non-zero indicates newer SMM NMI handler present */ 6180d12ef0cSMike Travis #define UVH_NMI_MMRX_SUPPORTED UVH_EXTIO_INT0_BROADCAST 6190d12ef0cSMike Travis 6200d12ef0cSMike Travis /* Indicates to BIOS that we want to use the newer SMM NMI handler */ 6210d12ef0cSMike Travis #define UVH_NMI_MMRX_REQ UVH_SCRATCH5_ALIAS_2 6220d12ef0cSMike Travis #define UVH_NMI_MMRX_REQ_SHIFT 62 6230d12ef0cSMike Travis 6240d12ef0cSMike Travis struct uv_hub_nmi_s { 6250d12ef0cSMike Travis raw_spinlock_t nmi_lock; 6260d12ef0cSMike Travis atomic_t in_nmi; /* flag this node in UV NMI IRQ */ 6270d12ef0cSMike Travis atomic_t cpu_owner; /* last locker of this struct */ 6280d12ef0cSMike Travis atomic_t read_mmr_count; /* count of MMR reads */ 6290d12ef0cSMike Travis atomic_t nmi_count; /* count of true UV NMIs */ 6300d12ef0cSMike Travis unsigned long nmi_value; /* last value read from NMI MMR */ 6310d12ef0cSMike Travis }; 6320d12ef0cSMike Travis 6330d12ef0cSMike Travis struct uv_cpu_nmi_s { 6340d12ef0cSMike Travis struct uv_hub_nmi_s *hub; 635e1632170SChristoph Lameter int state; 636e1632170SChristoph Lameter int pinging; 6370d12ef0cSMike Travis int queries; 6380d12ef0cSMike Travis int pings; 6390d12ef0cSMike Travis }; 6400d12ef0cSMike Travis 641e1632170SChristoph Lameter DECLARE_PER_CPU(struct uv_cpu_nmi_s, uv_cpu_nmi); 642e1632170SChristoph Lameter 6437c52198bSGeorge Beshers #define uv_hub_nmi this_cpu_read(uv_cpu_nmi.hub) 644e1632170SChristoph Lameter #define uv_cpu_nmi_per(cpu) (per_cpu(uv_cpu_nmi, cpu)) 6450d12ef0cSMike Travis #define uv_hub_nmi_per(cpu) (uv_cpu_nmi_per(cpu).hub) 6460d12ef0cSMike Travis 6470d12ef0cSMike Travis /* uv_cpu_nmi_states */ 6480d12ef0cSMike Travis #define UV_NMI_STATE_OUT 0 6490d12ef0cSMike Travis #define UV_NMI_STATE_IN 1 6500d12ef0cSMike Travis #define UV_NMI_STATE_DUMP 2 6510d12ef0cSMike Travis #define UV_NMI_STATE_DUMP_DONE 3 6520d12ef0cSMike Travis 6537f1baa06SMike Travis /* Update SCIR state */ 6547f1baa06SMike Travis static inline void uv_set_scir_bits(unsigned char value) 6557f1baa06SMike Travis { 6567f1baa06SMike Travis if (uv_hub_info->scir.state != value) { 6577f1baa06SMike Travis uv_hub_info->scir.state = value; 6587f1baa06SMike Travis uv_write_local_mmr8(uv_hub_info->scir.offset, value); 6597f1baa06SMike Travis } 6607f1baa06SMike Travis } 66166666e50SJack Steiner 66239d30770SMike Travis static inline unsigned long uv_scir_offset(int apicid) 66339d30770SMike Travis { 66439d30770SMike Travis return SCIR_LOCAL_MMR_BASE | (apicid & 0x3f); 66539d30770SMike Travis } 66639d30770SMike Travis 6677f1baa06SMike Travis static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value) 6687f1baa06SMike Travis { 6697f1baa06SMike Travis if (uv_cpu_hub_info(cpu)->scir.state != value) { 67039d30770SMike Travis uv_write_global_mmr8(uv_cpu_to_pnode(cpu), 67139d30770SMike Travis uv_cpu_hub_info(cpu)->scir.offset, value); 6727f1baa06SMike Travis uv_cpu_hub_info(cpu)->scir.state = value; 6737f1baa06SMike Travis } 6747f1baa06SMike Travis } 675bb898558SAl Viro 6768191c9f6SDimitri Sivanich extern unsigned int uv_apicid_hibits; 67756abcf24SJack Steiner static unsigned long uv_hub_ipi_value(int apicid, int vector, int mode) 67856abcf24SJack Steiner { 6798191c9f6SDimitri Sivanich apicid |= uv_apicid_hibits; 68056abcf24SJack Steiner return (1UL << UVH_IPI_INT_SEND_SHFT) | 68156abcf24SJack Steiner ((apicid) << UVH_IPI_INT_APIC_ID_SHFT) | 68256abcf24SJack Steiner (mode << UVH_IPI_INT_DELIVERY_MODE_SHFT) | 68356abcf24SJack Steiner (vector << UVH_IPI_INT_VECTOR_SHFT); 68456abcf24SJack Steiner } 68556abcf24SJack Steiner 68666666e50SJack Steiner static inline void uv_hub_send_ipi(int pnode, int apicid, int vector) 68766666e50SJack Steiner { 68866666e50SJack Steiner unsigned long val; 68902dd0a06SRobin Holt unsigned long dmode = dest_Fixed; 69002dd0a06SRobin Holt 69102dd0a06SRobin Holt if (vector == NMI_VECTOR) 69202dd0a06SRobin Holt dmode = dest_NMI; 69366666e50SJack Steiner 69456abcf24SJack Steiner val = uv_hub_ipi_value(apicid, vector, dmode); 69566666e50SJack Steiner uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 69666666e50SJack Steiner } 69766666e50SJack Steiner 6987a1110e8SJack Steiner /* 6997a1110e8SJack Steiner * Get the minimum revision number of the hub chips within the partition. 700eb1e3461SMike Travis * (See UVx_HUB_REVISION_BASE above for specific values.) 7017a1110e8SJack Steiner */ 7027a1110e8SJack Steiner static inline int uv_get_min_hub_revision_id(void) 7037a1110e8SJack Steiner { 7042a919596SJack Steiner return uv_hub_info->hub_revision; 7057a1110e8SJack Steiner } 7067a1110e8SJack Steiner 707bc5d9940SJack Steiner #endif /* CONFIG_X86_64 */ 7087f1baa06SMike Travis #endif /* _ASM_X86_UV_UV_HUB_H */ 709