1bb898558SAl Viro /* 2bb898558SAl Viro * This file is subject to the terms and conditions of the GNU General Public 3bb898558SAl Viro * License. See the file "COPYING" in the main directory of this archive 4bb898558SAl Viro * for more details. 5bb898558SAl Viro * 6bb898558SAl Viro * SGI UV architectural definitions 7bb898558SAl Viro * 8c8f730b1SRuss Anderson * Copyright (C) 2007-2010 Silicon Graphics, Inc. All rights reserved. 9bb898558SAl Viro */ 10bb898558SAl Viro 1105e4d316SH. Peter Anvin #ifndef _ASM_X86_UV_UV_HUB_H 1205e4d316SH. Peter Anvin #define _ASM_X86_UV_UV_HUB_H 13bb898558SAl Viro 14bc5d9940SJack Steiner #ifdef CONFIG_X86_64 15bb898558SAl Viro #include <linux/numa.h> 16bb898558SAl Viro #include <linux/percpu.h> 17c08b6accSMike Travis #include <linux/timer.h> 188dc579e8SJack Steiner #include <linux/io.h> 19bb898558SAl Viro #include <asm/types.h> 20bb898558SAl Viro #include <asm/percpu.h> 2166666e50SJack Steiner #include <asm/uv/uv_mmrs.h> 2202dd0a06SRobin Holt #include <asm/irq_vectors.h> 2302dd0a06SRobin Holt #include <asm/io_apic.h> 24bb898558SAl Viro 25bb898558SAl Viro 26bb898558SAl Viro /* 27bb898558SAl Viro * Addressing Terminology 28bb898558SAl Viro * 29bb898558SAl Viro * M - The low M bits of a physical address represent the offset 30bb898558SAl Viro * into the blade local memory. RAM memory on a blade is physically 31bb898558SAl Viro * contiguous (although various IO spaces may punch holes in 32bb898558SAl Viro * it).. 33bb898558SAl Viro * 34bb898558SAl Viro * N - Number of bits in the node portion of a socket physical 35bb898558SAl Viro * address. 36bb898558SAl Viro * 37bb898558SAl Viro * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of 38bb898558SAl Viro * routers always have low bit of 1, C/MBricks have low bit 39bb898558SAl Viro * equal to 0. Most addressing macros that target UV hub chips 40bb898558SAl Viro * right shift the NASID by 1 to exclude the always-zero bit. 41bb898558SAl Viro * NASIDs contain up to 15 bits. 42bb898558SAl Viro * 43bb898558SAl Viro * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead 44bb898558SAl Viro * of nasids. 45bb898558SAl Viro * 46bb898558SAl Viro * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant 47bb898558SAl Viro * of the nasid for socket usage. 48bb898558SAl Viro * 496a469e46SJack Steiner * GPA - (global physical address) a socket physical address converted 506a469e46SJack Steiner * so that it can be used by the GRU as a global address. Socket 516a469e46SJack Steiner * physical addresses 1) need additional NASID (node) bits added 526a469e46SJack Steiner * to the high end of the address, and 2) unaliased if the 536a469e46SJack Steiner * partition does not have a physical address 0. In addition, on 546a469e46SJack Steiner * UV2 rev 1, GPAs need the gnode left shifted to bits 39 or 40. 556a469e46SJack Steiner * 56bb898558SAl Viro * 57bb898558SAl Viro * NumaLink Global Physical Address Format: 58bb898558SAl Viro * +--------------------------------+---------------------+ 59bb898558SAl Viro * |00..000| GNODE | NodeOffset | 60bb898558SAl Viro * +--------------------------------+---------------------+ 61bb898558SAl Viro * |<-------53 - M bits --->|<--------M bits -----> 62bb898558SAl Viro * 63bb898558SAl Viro * M - number of node offset bits (35 .. 40) 64bb898558SAl Viro * 65bb898558SAl Viro * 66bb898558SAl Viro * Memory/UV-HUB Processor Socket Address Format: 67bb898558SAl Viro * +----------------+---------------+---------------------+ 68bb898558SAl Viro * |00..000000000000| PNODE | NodeOffset | 69bb898558SAl Viro * +----------------+---------------+---------------------+ 70bb898558SAl Viro * <--- N bits --->|<--------M bits -----> 71bb898558SAl Viro * 72bb898558SAl Viro * M - number of node offset bits (35 .. 40) 73bb898558SAl Viro * N - number of PNODE bits (0 .. 10) 74bb898558SAl Viro * 75bb898558SAl Viro * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64). 76bb898558SAl Viro * The actual values are configuration dependent and are set at 77bb898558SAl Viro * boot time. M & N values are set by the hardware/BIOS at boot. 78bb898558SAl Viro * 79bb898558SAl Viro * 80bb898558SAl Viro * APICID format 81bb898558SAl Viro * NOTE!!!!!! This is the current format of the APICID. However, code 82bb898558SAl Viro * should assume that this will change in the future. Use functions 83bb898558SAl Viro * in this file for all APICID bit manipulations and conversion. 84bb898558SAl Viro * 85bb898558SAl Viro * 1111110000000000 86bb898558SAl Viro * 5432109876543210 872a919596SJack Steiner * pppppppppplc0cch Nehalem-EX (12 bits in hdw reg) 882a919596SJack Steiner * ppppppppplcc0cch Westmere-EX (12 bits in hdw reg) 892a919596SJack Steiner * pppppppppppcccch SandyBridge (15 bits in hdw reg) 90bb898558SAl Viro * sssssssssss 91bb898558SAl Viro * 92bb898558SAl Viro * p = pnode bits 93bb898558SAl Viro * l = socket number on board 94bb898558SAl Viro * c = core 95bb898558SAl Viro * h = hyperthread 96bb898558SAl Viro * s = bits that are in the SOCKET_ID CSR 97bb898558SAl Viro * 982a919596SJack Steiner * Note: Processor may support fewer bits in the APICID register. The ACPI 99bb898558SAl Viro * tables hold all 16 bits. Software needs to be aware of this. 100bb898558SAl Viro * 101bb898558SAl Viro * Unless otherwise specified, all references to APICID refer to 102bb898558SAl Viro * the FULL value contained in ACPI tables, not the subset in the 103bb898558SAl Viro * processor APICID register. 104bb898558SAl Viro */ 105bb898558SAl Viro 106bb898558SAl Viro 107bb898558SAl Viro /* 108bb898558SAl Viro * Maximum number of bricks in all partitions and in all coherency domains. 109bb898558SAl Viro * This is the total number of bricks accessible in the numalink fabric. It 110bb898558SAl Viro * includes all C & M bricks. Routers are NOT included. 111bb898558SAl Viro * 112bb898558SAl Viro * This value is also the value of the maximum number of non-router NASIDs 113bb898558SAl Viro * in the numalink fabric. 114bb898558SAl Viro * 115bb898558SAl Viro * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused. 116bb898558SAl Viro */ 117bb898558SAl Viro #define UV_MAX_NUMALINK_BLADES 16384 118bb898558SAl Viro 119bb898558SAl Viro /* 120bb898558SAl Viro * Maximum number of C/Mbricks within a software SSI (hardware may support 121bb898558SAl Viro * more). 122bb898558SAl Viro */ 123bb898558SAl Viro #define UV_MAX_SSI_BLADES 256 124bb898558SAl Viro 125bb898558SAl Viro /* 126bb898558SAl Viro * The largest possible NASID of a C or M brick (+ 2) 127bb898558SAl Viro */ 1281d21e6e3SRobin Holt #define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_BLADES * 2) 129bb898558SAl Viro 1307f1baa06SMike Travis struct uv_scir_s { 1317f1baa06SMike Travis struct timer_list timer; 1327f1baa06SMike Travis unsigned long offset; 1337f1baa06SMike Travis unsigned long last; 1347f1baa06SMike Travis unsigned long idle_on; 1357f1baa06SMike Travis unsigned long idle_off; 1367f1baa06SMike Travis unsigned char state; 1377f1baa06SMike Travis unsigned char enabled; 1387f1baa06SMike Travis }; 1397f1baa06SMike Travis 140bb898558SAl Viro /* 141bb898558SAl Viro * The following defines attributes of the HUB chip. These attributes are 142bb898558SAl Viro * frequently referenced and are kept in the per-cpu data areas of each cpu. 143bb898558SAl Viro * They are kept together in a struct to minimize cache misses. 144bb898558SAl Viro */ 145bb898558SAl Viro struct uv_hub_info_s { 146bb898558SAl Viro unsigned long global_mmr_base; 147bb898558SAl Viro unsigned long gpa_mask; 148c4ed3f04SJack Steiner unsigned int gnode_extra; 1492a919596SJack Steiner unsigned char hub_revision; 1502a919596SJack Steiner unsigned char apic_pnode_shift; 1516a469e46SJack Steiner unsigned char m_shift; 1526a469e46SJack Steiner unsigned char n_lshift; 153bb898558SAl Viro unsigned long gnode_upper; 154bb898558SAl Viro unsigned long lowmem_remap_top; 155bb898558SAl Viro unsigned long lowmem_remap_base; 156bb898558SAl Viro unsigned short pnode; 157bb898558SAl Viro unsigned short pnode_mask; 158bb898558SAl Viro unsigned short coherency_domain_number; 159bb898558SAl Viro unsigned short numa_blade_id; 160bb898558SAl Viro unsigned char blade_processor_id; 161bb898558SAl Viro unsigned char m_val; 162bb898558SAl Viro unsigned char n_val; 1637f1baa06SMike Travis struct uv_scir_s scir; 164bb898558SAl Viro }; 1657f1baa06SMike Travis 166bb898558SAl Viro DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); 167bb898558SAl Viro #define uv_hub_info (&__get_cpu_var(__uv_hub_info)) 168bb898558SAl Viro #define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu)) 169bb898558SAl Viro 1702a919596SJack Steiner /* 1712a919596SJack Steiner * Hub revisions less than UV2_HUB_REVISION_BASE are UV1 hubs. All UV2 1722a919596SJack Steiner * hubs have revision numbers greater than or equal to UV2_HUB_REVISION_BASE. 1732a919596SJack Steiner * This is a software convention - NOT the hardware revision numbers in 1742a919596SJack Steiner * the hub chip. 1752a919596SJack Steiner */ 1762a919596SJack Steiner #define UV1_HUB_REVISION_BASE 1 1772a919596SJack Steiner #define UV2_HUB_REVISION_BASE 3 1782a919596SJack Steiner 1792a919596SJack Steiner static inline int is_uv1_hub(void) 1802a919596SJack Steiner { 1812a919596SJack Steiner return uv_hub_info->hub_revision < UV2_HUB_REVISION_BASE; 1822a919596SJack Steiner } 1832a919596SJack Steiner 1842a919596SJack Steiner static inline int is_uv2_hub(void) 1852a919596SJack Steiner { 1862a919596SJack Steiner return uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE; 1872a919596SJack Steiner } 1882a919596SJack Steiner 1896a469e46SJack Steiner static inline int is_uv2_1_hub(void) 1906a469e46SJack Steiner { 1916a469e46SJack Steiner return uv_hub_info->hub_revision == UV2_HUB_REVISION_BASE; 1926a469e46SJack Steiner } 1936a469e46SJack Steiner 1946a469e46SJack Steiner static inline int is_uv2_2_hub(void) 1956a469e46SJack Steiner { 1966a469e46SJack Steiner return uv_hub_info->hub_revision == UV2_HUB_REVISION_BASE + 1; 1976a469e46SJack Steiner } 1986a469e46SJack Steiner 199c8f730b1SRuss Anderson union uvh_apicid { 200c8f730b1SRuss Anderson unsigned long v; 201c8f730b1SRuss Anderson struct uvh_apicid_s { 202c8f730b1SRuss Anderson unsigned long local_apic_mask : 24; 203c8f730b1SRuss Anderson unsigned long local_apic_shift : 5; 204c8f730b1SRuss Anderson unsigned long unused1 : 3; 205c8f730b1SRuss Anderson unsigned long pnode_mask : 24; 206c8f730b1SRuss Anderson unsigned long pnode_shift : 5; 207c8f730b1SRuss Anderson unsigned long unused2 : 3; 208c8f730b1SRuss Anderson } s; 209c8f730b1SRuss Anderson }; 210c8f730b1SRuss Anderson 211bb898558SAl Viro /* 212bb898558SAl Viro * Local & Global MMR space macros. 213bb898558SAl Viro * Note: macros are intended to be used ONLY by inline functions 214bb898558SAl Viro * in this file - not by other kernel code. 215bb898558SAl Viro * n - NASID (full 15-bit global nasid) 216bb898558SAl Viro * g - GNODE (full 15-bit global nasid, right shifted 1) 217bb898558SAl Viro * p - PNODE (local part of nsids, right shifted 1) 218bb898558SAl Viro */ 219bb898558SAl Viro #define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask) 220c4ed3f04SJack Steiner #define UV_PNODE_TO_GNODE(p) ((p) |uv_hub_info->gnode_extra) 221c4ed3f04SJack Steiner #define UV_PNODE_TO_NASID(p) (UV_PNODE_TO_GNODE(p) << 1) 222bb898558SAl Viro 2232a919596SJack Steiner #define UV1_LOCAL_MMR_BASE 0xf4000000UL 2242a919596SJack Steiner #define UV1_GLOBAL_MMR32_BASE 0xf8000000UL 2252a919596SJack Steiner #define UV1_LOCAL_MMR_SIZE (64UL * 1024 * 1024) 2262a919596SJack Steiner #define UV1_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024) 2272a919596SJack Steiner 2282a919596SJack Steiner #define UV2_LOCAL_MMR_BASE 0xfa000000UL 2292a919596SJack Steiner #define UV2_GLOBAL_MMR32_BASE 0xfc000000UL 2302a919596SJack Steiner #define UV2_LOCAL_MMR_SIZE (32UL * 1024 * 1024) 2312a919596SJack Steiner #define UV2_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024) 2322a919596SJack Steiner 2332a919596SJack Steiner #define UV_LOCAL_MMR_BASE (is_uv1_hub() ? UV1_LOCAL_MMR_BASE \ 2342a919596SJack Steiner : UV2_LOCAL_MMR_BASE) 2352a919596SJack Steiner #define UV_GLOBAL_MMR32_BASE (is_uv1_hub() ? UV1_GLOBAL_MMR32_BASE \ 2362a919596SJack Steiner : UV2_GLOBAL_MMR32_BASE) 2372a919596SJack Steiner #define UV_LOCAL_MMR_SIZE (is_uv1_hub() ? UV1_LOCAL_MMR_SIZE : \ 2382a919596SJack Steiner UV2_LOCAL_MMR_SIZE) 2392a919596SJack Steiner #define UV_GLOBAL_MMR32_SIZE (is_uv1_hub() ? UV1_GLOBAL_MMR32_SIZE :\ 2402a919596SJack Steiner UV2_GLOBAL_MMR32_SIZE) 241bb898558SAl Viro #define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base) 242bb898558SAl Viro 24356abcf24SJack Steiner #define UV_GLOBAL_GRU_MMR_BASE 0x4000000 24456abcf24SJack Steiner 245bb898558SAl Viro #define UV_GLOBAL_MMR32_PNODE_SHIFT 15 246bb898558SAl Viro #define UV_GLOBAL_MMR64_PNODE_SHIFT 26 247bb898558SAl Viro 248bb898558SAl Viro #define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT)) 249bb898558SAl Viro 250bb898558SAl Viro #define UV_GLOBAL_MMR64_PNODE_BITS(p) \ 25167e83f30SJack Steiner (((unsigned long)(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT) 252bb898558SAl Viro 253c8f730b1SRuss Anderson #define UVH_APICID 0x002D0E00L 254bb898558SAl Viro #define UV_APIC_PNODE_SHIFT 6 255bb898558SAl Viro 2568191c9f6SDimitri Sivanich #define UV_APICID_HIBIT_MASK 0xffff0000 2578191c9f6SDimitri Sivanich 2587f1baa06SMike Travis /* Local Bus from cpu's perspective */ 2597f1baa06SMike Travis #define LOCAL_BUS_BASE 0x1c00000 2607f1baa06SMike Travis #define LOCAL_BUS_SIZE (4 * 1024 * 1024) 2617f1baa06SMike Travis 2627f1baa06SMike Travis /* 2637f1baa06SMike Travis * System Controller Interface Reg 2647f1baa06SMike Travis * 2657f1baa06SMike Travis * Note there are NO leds on a UV system. This register is only 2667f1baa06SMike Travis * used by the system controller to monitor system-wide operation. 2677f1baa06SMike Travis * There are 64 regs per node. With Nahelem cpus (2 cores per node, 2687f1baa06SMike Travis * 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on 2697f1baa06SMike Travis * a node. 2707f1baa06SMike Travis * 2717f1baa06SMike Travis * The window is located at top of ACPI MMR space 2727f1baa06SMike Travis */ 2737f1baa06SMike Travis #define SCIR_WINDOW_COUNT 64 2747f1baa06SMike Travis #define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \ 2757f1baa06SMike Travis LOCAL_BUS_SIZE - \ 2767f1baa06SMike Travis SCIR_WINDOW_COUNT) 2777f1baa06SMike Travis 2787f1baa06SMike Travis #define SCIR_CPU_HEARTBEAT 0x01 /* timer interrupt */ 2797f1baa06SMike Travis #define SCIR_CPU_ACTIVITY 0x02 /* not idle */ 2807f1baa06SMike Travis #define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */ 2817f1baa06SMike Travis 2828661984fSDimitri Sivanich /* Loop through all installed blades */ 2838661984fSDimitri Sivanich #define for_each_possible_blade(bid) \ 2848661984fSDimitri Sivanich for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++) 2858661984fSDimitri Sivanich 286bb898558SAl Viro /* 287bb898558SAl Viro * Macros for converting between kernel virtual addresses, socket local physical 288bb898558SAl Viro * addresses, and UV global physical addresses. 289bb898558SAl Viro * Note: use the standard __pa() & __va() macros for converting 290bb898558SAl Viro * between socket virtual and socket physical addresses. 291bb898558SAl Viro */ 292bb898558SAl Viro 293bb898558SAl Viro /* socket phys RAM --> UV global physical address */ 294bb898558SAl Viro static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr) 295bb898558SAl Viro { 296bb898558SAl Viro if (paddr < uv_hub_info->lowmem_remap_top) 297189f67c4SJack Steiner paddr |= uv_hub_info->lowmem_remap_base; 2986a469e46SJack Steiner paddr |= uv_hub_info->gnode_upper; 2996a469e46SJack Steiner paddr = ((paddr << uv_hub_info->m_shift) >> uv_hub_info->m_shift) | 3006a469e46SJack Steiner ((paddr >> uv_hub_info->m_val) << uv_hub_info->n_lshift); 3016a469e46SJack Steiner return paddr; 302bb898558SAl Viro } 303bb898558SAl Viro 304bb898558SAl Viro 305bb898558SAl Viro /* socket virtual --> UV global physical address */ 306bb898558SAl Viro static inline unsigned long uv_gpa(void *v) 307bb898558SAl Viro { 308189f67c4SJack Steiner return uv_soc_phys_ram_to_gpa(__pa(v)); 309bb898558SAl Viro } 310bb898558SAl Viro 311fae419f2SRobin Holt /* Top two bits indicate the requested address is in MMR space. */ 312fae419f2SRobin Holt static inline int 313fae419f2SRobin Holt uv_gpa_in_mmr_space(unsigned long gpa) 314fae419f2SRobin Holt { 315fae419f2SRobin Holt return (gpa >> 62) == 0x3UL; 316fae419f2SRobin Holt } 317fae419f2SRobin Holt 318729d69e6SRobin Holt /* UV global physical address --> socket phys RAM */ 319729d69e6SRobin Holt static inline unsigned long uv_gpa_to_soc_phys_ram(unsigned long gpa) 320729d69e6SRobin Holt { 3215a51467bSRuss Anderson unsigned long paddr; 322729d69e6SRobin Holt unsigned long remap_base = uv_hub_info->lowmem_remap_base; 323729d69e6SRobin Holt unsigned long remap_top = uv_hub_info->lowmem_remap_top; 324729d69e6SRobin Holt 3256a469e46SJack Steiner gpa = ((gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift) | 3266a469e46SJack Steiner ((gpa >> uv_hub_info->n_lshift) << uv_hub_info->m_val); 3275a51467bSRuss Anderson paddr = gpa & uv_hub_info->gpa_mask; 328729d69e6SRobin Holt if (paddr >= remap_base && paddr < remap_base + remap_top) 329729d69e6SRobin Holt paddr -= remap_base; 330729d69e6SRobin Holt return paddr; 331729d69e6SRobin Holt } 332729d69e6SRobin Holt 333729d69e6SRobin Holt 3346a469e46SJack Steiner /* gpa -> pnode */ 3351d21e6e3SRobin Holt static inline unsigned long uv_gpa_to_gnode(unsigned long gpa) 3361d21e6e3SRobin Holt { 3376a469e46SJack Steiner return gpa >> uv_hub_info->n_lshift; 3381d21e6e3SRobin Holt } 3391d21e6e3SRobin Holt 3401d21e6e3SRobin Holt /* gpa -> pnode */ 3411d21e6e3SRobin Holt static inline int uv_gpa_to_pnode(unsigned long gpa) 3421d21e6e3SRobin Holt { 3431d21e6e3SRobin Holt unsigned long n_mask = (1UL << uv_hub_info->n_val) - 1; 3441d21e6e3SRobin Holt 3451d21e6e3SRobin Holt return uv_gpa_to_gnode(gpa) & n_mask; 3461d21e6e3SRobin Holt } 3471d21e6e3SRobin Holt 3486a469e46SJack Steiner /* gpa -> node offset*/ 3496a469e46SJack Steiner static inline unsigned long uv_gpa_to_offset(unsigned long gpa) 3506a469e46SJack Steiner { 3516a469e46SJack Steiner return (gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift; 3526a469e46SJack Steiner } 3536a469e46SJack Steiner 354bb898558SAl Viro /* pnode, offset --> socket virtual */ 355bb898558SAl Viro static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset) 356bb898558SAl Viro { 357bb898558SAl Viro return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset); 358bb898558SAl Viro } 359bb898558SAl Viro 360bb898558SAl Viro 361bb898558SAl Viro /* 362bb898558SAl Viro * Extract a PNODE from an APICID (full apicid, not processor subset) 363bb898558SAl Viro */ 364bb898558SAl Viro static inline int uv_apicid_to_pnode(int apicid) 365bb898558SAl Viro { 366c8f730b1SRuss Anderson return (apicid >> uv_hub_info->apic_pnode_shift); 367bb898558SAl Viro } 368bb898558SAl Viro 369bb898558SAl Viro /* 3702a919596SJack Steiner * Convert an apicid to the socket number on the blade 3712a919596SJack Steiner */ 3722a919596SJack Steiner static inline int uv_apicid_to_socket(int apicid) 3732a919596SJack Steiner { 3742a919596SJack Steiner if (is_uv1_hub()) 3752a919596SJack Steiner return (apicid >> (uv_hub_info->apic_pnode_shift - 1)) & 1; 3762a919596SJack Steiner else 3772a919596SJack Steiner return 0; 3782a919596SJack Steiner } 3792a919596SJack Steiner 3802a919596SJack Steiner /* 381bb898558SAl Viro * Access global MMRs using the low memory MMR32 space. This region supports 382bb898558SAl Viro * faster MMR access but not all MMRs are accessible in this space. 383bb898558SAl Viro */ 38439d30770SMike Travis static inline unsigned long *uv_global_mmr32_address(int pnode, unsigned long offset) 385bb898558SAl Viro { 386bb898558SAl Viro return __va(UV_GLOBAL_MMR32_BASE | 387bb898558SAl Viro UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset); 388bb898558SAl Viro } 389bb898558SAl Viro 39039d30770SMike Travis static inline void uv_write_global_mmr32(int pnode, unsigned long offset, unsigned long val) 391bb898558SAl Viro { 3928dc579e8SJack Steiner writeq(val, uv_global_mmr32_address(pnode, offset)); 393bb898558SAl Viro } 394bb898558SAl Viro 39539d30770SMike Travis static inline unsigned long uv_read_global_mmr32(int pnode, unsigned long offset) 396bb898558SAl Viro { 3978dc579e8SJack Steiner return readq(uv_global_mmr32_address(pnode, offset)); 398bb898558SAl Viro } 399bb898558SAl Viro 400bb898558SAl Viro /* 401bb898558SAl Viro * Access Global MMR space using the MMR space located at the top of physical 402bb898558SAl Viro * memory. 403bb898558SAl Viro */ 404a289cc7cSRandy Dunlap static inline volatile void __iomem *uv_global_mmr64_address(int pnode, unsigned long offset) 405bb898558SAl Viro { 406bb898558SAl Viro return __va(UV_GLOBAL_MMR64_BASE | 407bb898558SAl Viro UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset); 408bb898558SAl Viro } 409bb898558SAl Viro 41039d30770SMike Travis static inline void uv_write_global_mmr64(int pnode, unsigned long offset, unsigned long val) 411bb898558SAl Viro { 4128dc579e8SJack Steiner writeq(val, uv_global_mmr64_address(pnode, offset)); 413bb898558SAl Viro } 414bb898558SAl Viro 41539d30770SMike Travis static inline unsigned long uv_read_global_mmr64(int pnode, unsigned long offset) 416bb898558SAl Viro { 4178dc579e8SJack Steiner return readq(uv_global_mmr64_address(pnode, offset)); 418bb898558SAl Viro } 419bb898558SAl Viro 420bb898558SAl Viro /* 42156abcf24SJack Steiner * Global MMR space addresses when referenced by the GRU. (GRU does 42256abcf24SJack Steiner * NOT use socket addressing). 42356abcf24SJack Steiner */ 42456abcf24SJack Steiner static inline unsigned long uv_global_gru_mmr_address(int pnode, unsigned long offset) 42556abcf24SJack Steiner { 426e1e0138dSJack Steiner return UV_GLOBAL_GRU_MMR_BASE | offset | 427e1e0138dSJack Steiner ((unsigned long)pnode << uv_hub_info->m_val); 42856abcf24SJack Steiner } 42956abcf24SJack Steiner 43039d30770SMike Travis static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val) 43139d30770SMike Travis { 43239d30770SMike Travis writeb(val, uv_global_mmr64_address(pnode, offset)); 43339d30770SMike Travis } 43439d30770SMike Travis 43539d30770SMike Travis static inline unsigned char uv_read_global_mmr8(int pnode, unsigned long offset) 43639d30770SMike Travis { 43739d30770SMike Travis return readb(uv_global_mmr64_address(pnode, offset)); 43839d30770SMike Travis } 43939d30770SMike Travis 44056abcf24SJack Steiner /* 441bb898558SAl Viro * Access hub local MMRs. Faster than using global space but only local MMRs 442bb898558SAl Viro * are accessible. 443bb898558SAl Viro */ 444bb898558SAl Viro static inline unsigned long *uv_local_mmr_address(unsigned long offset) 445bb898558SAl Viro { 446bb898558SAl Viro return __va(UV_LOCAL_MMR_BASE | offset); 447bb898558SAl Viro } 448bb898558SAl Viro 449bb898558SAl Viro static inline unsigned long uv_read_local_mmr(unsigned long offset) 450bb898558SAl Viro { 4518dc579e8SJack Steiner return readq(uv_local_mmr_address(offset)); 452bb898558SAl Viro } 453bb898558SAl Viro 454bb898558SAl Viro static inline void uv_write_local_mmr(unsigned long offset, unsigned long val) 455bb898558SAl Viro { 4568dc579e8SJack Steiner writeq(val, uv_local_mmr_address(offset)); 457bb898558SAl Viro } 458bb898558SAl Viro 4597f1baa06SMike Travis static inline unsigned char uv_read_local_mmr8(unsigned long offset) 4607f1baa06SMike Travis { 4618dc579e8SJack Steiner return readb(uv_local_mmr_address(offset)); 4627f1baa06SMike Travis } 4637f1baa06SMike Travis 4647f1baa06SMike Travis static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val) 4657f1baa06SMike Travis { 4668dc579e8SJack Steiner writeb(val, uv_local_mmr_address(offset)); 4677f1baa06SMike Travis } 4687f1baa06SMike Travis 469bb898558SAl Viro /* 470bb898558SAl Viro * Structures and definitions for converting between cpu, node, pnode, and blade 471bb898558SAl Viro * numbers. 472bb898558SAl Viro */ 473bb898558SAl Viro struct uv_blade_info { 474bb898558SAl Viro unsigned short nr_possible_cpus; 475bb898558SAl Viro unsigned short nr_online_cpus; 476bb898558SAl Viro unsigned short pnode; 4776c7184b7SJack Steiner short memory_nid; 4781d44e828SJack Steiner spinlock_t nmi_lock; 4791d44e828SJack Steiner unsigned long nmi_count; 480bb898558SAl Viro }; 481bb898558SAl Viro extern struct uv_blade_info *uv_blade_info; 482bb898558SAl Viro extern short *uv_node_to_blade; 483bb898558SAl Viro extern short *uv_cpu_to_blade; 484bb898558SAl Viro extern short uv_possible_blades; 485bb898558SAl Viro 486bb898558SAl Viro /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */ 487bb898558SAl Viro static inline int uv_blade_processor_id(void) 488bb898558SAl Viro { 489bb898558SAl Viro return uv_hub_info->blade_processor_id; 490bb898558SAl Viro } 491bb898558SAl Viro 492bb898558SAl Viro /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */ 493bb898558SAl Viro static inline int uv_numa_blade_id(void) 494bb898558SAl Viro { 495bb898558SAl Viro return uv_hub_info->numa_blade_id; 496bb898558SAl Viro } 497bb898558SAl Viro 498bb898558SAl Viro /* Convert a cpu number to the the UV blade number */ 499bb898558SAl Viro static inline int uv_cpu_to_blade_id(int cpu) 500bb898558SAl Viro { 501bb898558SAl Viro return uv_cpu_to_blade[cpu]; 502bb898558SAl Viro } 503bb898558SAl Viro 504bb898558SAl Viro /* Convert linux node number to the UV blade number */ 505bb898558SAl Viro static inline int uv_node_to_blade_id(int nid) 506bb898558SAl Viro { 507bb898558SAl Viro return uv_node_to_blade[nid]; 508bb898558SAl Viro } 509bb898558SAl Viro 510bb898558SAl Viro /* Convert a blade id to the PNODE of the blade */ 511bb898558SAl Viro static inline int uv_blade_to_pnode(int bid) 512bb898558SAl Viro { 513bb898558SAl Viro return uv_blade_info[bid].pnode; 514bb898558SAl Viro } 515bb898558SAl Viro 5166c7184b7SJack Steiner /* Nid of memory node on blade. -1 if no blade-local memory */ 5176c7184b7SJack Steiner static inline int uv_blade_to_memory_nid(int bid) 5186c7184b7SJack Steiner { 5196c7184b7SJack Steiner return uv_blade_info[bid].memory_nid; 5206c7184b7SJack Steiner } 5216c7184b7SJack Steiner 522bb898558SAl Viro /* Determine the number of possible cpus on a blade */ 523bb898558SAl Viro static inline int uv_blade_nr_possible_cpus(int bid) 524bb898558SAl Viro { 525bb898558SAl Viro return uv_blade_info[bid].nr_possible_cpus; 526bb898558SAl Viro } 527bb898558SAl Viro 528bb898558SAl Viro /* Determine the number of online cpus on a blade */ 529bb898558SAl Viro static inline int uv_blade_nr_online_cpus(int bid) 530bb898558SAl Viro { 531bb898558SAl Viro return uv_blade_info[bid].nr_online_cpus; 532bb898558SAl Viro } 533bb898558SAl Viro 534bb898558SAl Viro /* Convert a cpu id to the PNODE of the blade containing the cpu */ 535bb898558SAl Viro static inline int uv_cpu_to_pnode(int cpu) 536bb898558SAl Viro { 537bb898558SAl Viro return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode; 538bb898558SAl Viro } 539bb898558SAl Viro 540bb898558SAl Viro /* Convert a linux node number to the PNODE of the blade */ 541bb898558SAl Viro static inline int uv_node_to_pnode(int nid) 542bb898558SAl Viro { 543bb898558SAl Viro return uv_blade_info[uv_node_to_blade_id(nid)].pnode; 544bb898558SAl Viro } 545bb898558SAl Viro 546bb898558SAl Viro /* Maximum possible number of blades */ 547bb898558SAl Viro static inline int uv_num_possible_blades(void) 548bb898558SAl Viro { 549bb898558SAl Viro return uv_possible_blades; 550bb898558SAl Viro } 551bb898558SAl Viro 5527f1baa06SMike Travis /* Update SCIR state */ 5537f1baa06SMike Travis static inline void uv_set_scir_bits(unsigned char value) 5547f1baa06SMike Travis { 5557f1baa06SMike Travis if (uv_hub_info->scir.state != value) { 5567f1baa06SMike Travis uv_hub_info->scir.state = value; 5577f1baa06SMike Travis uv_write_local_mmr8(uv_hub_info->scir.offset, value); 5587f1baa06SMike Travis } 5597f1baa06SMike Travis } 56066666e50SJack Steiner 56139d30770SMike Travis static inline unsigned long uv_scir_offset(int apicid) 56239d30770SMike Travis { 56339d30770SMike Travis return SCIR_LOCAL_MMR_BASE | (apicid & 0x3f); 56439d30770SMike Travis } 56539d30770SMike Travis 5667f1baa06SMike Travis static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value) 5677f1baa06SMike Travis { 5687f1baa06SMike Travis if (uv_cpu_hub_info(cpu)->scir.state != value) { 56939d30770SMike Travis uv_write_global_mmr8(uv_cpu_to_pnode(cpu), 57039d30770SMike Travis uv_cpu_hub_info(cpu)->scir.offset, value); 5717f1baa06SMike Travis uv_cpu_hub_info(cpu)->scir.state = value; 5727f1baa06SMike Travis } 5737f1baa06SMike Travis } 574bb898558SAl Viro 5758191c9f6SDimitri Sivanich extern unsigned int uv_apicid_hibits; 57656abcf24SJack Steiner static unsigned long uv_hub_ipi_value(int apicid, int vector, int mode) 57756abcf24SJack Steiner { 5788191c9f6SDimitri Sivanich apicid |= uv_apicid_hibits; 57956abcf24SJack Steiner return (1UL << UVH_IPI_INT_SEND_SHFT) | 58056abcf24SJack Steiner ((apicid) << UVH_IPI_INT_APIC_ID_SHFT) | 58156abcf24SJack Steiner (mode << UVH_IPI_INT_DELIVERY_MODE_SHFT) | 58256abcf24SJack Steiner (vector << UVH_IPI_INT_VECTOR_SHFT); 58356abcf24SJack Steiner } 58456abcf24SJack Steiner 58566666e50SJack Steiner static inline void uv_hub_send_ipi(int pnode, int apicid, int vector) 58666666e50SJack Steiner { 58766666e50SJack Steiner unsigned long val; 58802dd0a06SRobin Holt unsigned long dmode = dest_Fixed; 58902dd0a06SRobin Holt 59002dd0a06SRobin Holt if (vector == NMI_VECTOR) 59102dd0a06SRobin Holt dmode = dest_NMI; 59266666e50SJack Steiner 59356abcf24SJack Steiner val = uv_hub_ipi_value(apicid, vector, dmode); 59466666e50SJack Steiner uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 59566666e50SJack Steiner } 59666666e50SJack Steiner 5977a1110e8SJack Steiner /* 5987a1110e8SJack Steiner * Get the minimum revision number of the hub chips within the partition. 5992a919596SJack Steiner * 1 - UV1 rev 1.0 initial silicon 6002a919596SJack Steiner * 2 - UV1 rev 2.0 production silicon 6012a919596SJack Steiner * 3 - UV2 rev 1.0 initial silicon 6027a1110e8SJack Steiner */ 6037a1110e8SJack Steiner static inline int uv_get_min_hub_revision_id(void) 6047a1110e8SJack Steiner { 6052a919596SJack Steiner return uv_hub_info->hub_revision; 6067a1110e8SJack Steiner } 6077a1110e8SJack Steiner 608bc5d9940SJack Steiner #endif /* CONFIG_X86_64 */ 6097f1baa06SMike Travis #endif /* _ASM_X86_UV_UV_HUB_H */ 610