1bb898558SAl Viro /* 2bb898558SAl Viro * This file is subject to the terms and conditions of the GNU General Public 3bb898558SAl Viro * License. See the file "COPYING" in the main directory of this archive 4bb898558SAl Viro * for more details. 5bb898558SAl Viro * 6bb898558SAl Viro * SGI UV architectural definitions 7bb898558SAl Viro * 85f40f7d9SDimitri Sivanich * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved. 9bb898558SAl Viro */ 10bb898558SAl Viro 1105e4d316SH. Peter Anvin #ifndef _ASM_X86_UV_UV_HUB_H 1205e4d316SH. Peter Anvin #define _ASM_X86_UV_UV_HUB_H 13bb898558SAl Viro 14bc5d9940SJack Steiner #ifdef CONFIG_X86_64 15bb898558SAl Viro #include <linux/numa.h> 16bb898558SAl Viro #include <linux/percpu.h> 17c08b6accSMike Travis #include <linux/timer.h> 188dc579e8SJack Steiner #include <linux/io.h> 19bb898558SAl Viro #include <asm/types.h> 20bb898558SAl Viro #include <asm/percpu.h> 2166666e50SJack Steiner #include <asm/uv/uv_mmrs.h> 2202dd0a06SRobin Holt #include <asm/irq_vectors.h> 2302dd0a06SRobin Holt #include <asm/io_apic.h> 24bb898558SAl Viro 25bb898558SAl Viro 26bb898558SAl Viro /* 27bb898558SAl Viro * Addressing Terminology 28bb898558SAl Viro * 29bb898558SAl Viro * M - The low M bits of a physical address represent the offset 30bb898558SAl Viro * into the blade local memory. RAM memory on a blade is physically 31bb898558SAl Viro * contiguous (although various IO spaces may punch holes in 32bb898558SAl Viro * it).. 33bb898558SAl Viro * 34bb898558SAl Viro * N - Number of bits in the node portion of a socket physical 35bb898558SAl Viro * address. 36bb898558SAl Viro * 37bb898558SAl Viro * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of 38bb898558SAl Viro * routers always have low bit of 1, C/MBricks have low bit 39bb898558SAl Viro * equal to 0. Most addressing macros that target UV hub chips 40bb898558SAl Viro * right shift the NASID by 1 to exclude the always-zero bit. 41bb898558SAl Viro * NASIDs contain up to 15 bits. 42bb898558SAl Viro * 43bb898558SAl Viro * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead 44bb898558SAl Viro * of nasids. 45bb898558SAl Viro * 46bb898558SAl Viro * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant 47bb898558SAl Viro * of the nasid for socket usage. 48bb898558SAl Viro * 496a469e46SJack Steiner * GPA - (global physical address) a socket physical address converted 506a469e46SJack Steiner * so that it can be used by the GRU as a global address. Socket 516a469e46SJack Steiner * physical addresses 1) need additional NASID (node) bits added 526a469e46SJack Steiner * to the high end of the address, and 2) unaliased if the 536a469e46SJack Steiner * partition does not have a physical address 0. In addition, on 546a469e46SJack Steiner * UV2 rev 1, GPAs need the gnode left shifted to bits 39 or 40. 556a469e46SJack Steiner * 56bb898558SAl Viro * 57bb898558SAl Viro * NumaLink Global Physical Address Format: 58bb898558SAl Viro * +--------------------------------+---------------------+ 59bb898558SAl Viro * |00..000| GNODE | NodeOffset | 60bb898558SAl Viro * +--------------------------------+---------------------+ 61bb898558SAl Viro * |<-------53 - M bits --->|<--------M bits -----> 62bb898558SAl Viro * 63bb898558SAl Viro * M - number of node offset bits (35 .. 40) 64bb898558SAl Viro * 65bb898558SAl Viro * 66bb898558SAl Viro * Memory/UV-HUB Processor Socket Address Format: 67bb898558SAl Viro * +----------------+---------------+---------------------+ 68bb898558SAl Viro * |00..000000000000| PNODE | NodeOffset | 69bb898558SAl Viro * +----------------+---------------+---------------------+ 70bb898558SAl Viro * <--- N bits --->|<--------M bits -----> 71bb898558SAl Viro * 72bb898558SAl Viro * M - number of node offset bits (35 .. 40) 73bb898558SAl Viro * N - number of PNODE bits (0 .. 10) 74bb898558SAl Viro * 75bb898558SAl Viro * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64). 76bb898558SAl Viro * The actual values are configuration dependent and are set at 77bb898558SAl Viro * boot time. M & N values are set by the hardware/BIOS at boot. 78bb898558SAl Viro * 79bb898558SAl Viro * 80bb898558SAl Viro * APICID format 81bb898558SAl Viro * NOTE!!!!!! This is the current format of the APICID. However, code 82bb898558SAl Viro * should assume that this will change in the future. Use functions 83bb898558SAl Viro * in this file for all APICID bit manipulations and conversion. 84bb898558SAl Viro * 85bb898558SAl Viro * 1111110000000000 86bb898558SAl Viro * 5432109876543210 872a919596SJack Steiner * pppppppppplc0cch Nehalem-EX (12 bits in hdw reg) 882a919596SJack Steiner * ppppppppplcc0cch Westmere-EX (12 bits in hdw reg) 892a919596SJack Steiner * pppppppppppcccch SandyBridge (15 bits in hdw reg) 90bb898558SAl Viro * sssssssssss 91bb898558SAl Viro * 92bb898558SAl Viro * p = pnode bits 93bb898558SAl Viro * l = socket number on board 94bb898558SAl Viro * c = core 95bb898558SAl Viro * h = hyperthread 96bb898558SAl Viro * s = bits that are in the SOCKET_ID CSR 97bb898558SAl Viro * 982a919596SJack Steiner * Note: Processor may support fewer bits in the APICID register. The ACPI 99bb898558SAl Viro * tables hold all 16 bits. Software needs to be aware of this. 100bb898558SAl Viro * 101bb898558SAl Viro * Unless otherwise specified, all references to APICID refer to 102bb898558SAl Viro * the FULL value contained in ACPI tables, not the subset in the 103bb898558SAl Viro * processor APICID register. 104bb898558SAl Viro */ 105bb898558SAl Viro 106bb898558SAl Viro 107bb898558SAl Viro /* 108bb898558SAl Viro * Maximum number of bricks in all partitions and in all coherency domains. 109bb898558SAl Viro * This is the total number of bricks accessible in the numalink fabric. It 110bb898558SAl Viro * includes all C & M bricks. Routers are NOT included. 111bb898558SAl Viro * 112bb898558SAl Viro * This value is also the value of the maximum number of non-router NASIDs 113bb898558SAl Viro * in the numalink fabric. 114bb898558SAl Viro * 115bb898558SAl Viro * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused. 116bb898558SAl Viro */ 117bb898558SAl Viro #define UV_MAX_NUMALINK_BLADES 16384 118bb898558SAl Viro 119bb898558SAl Viro /* 120bb898558SAl Viro * Maximum number of C/Mbricks within a software SSI (hardware may support 121bb898558SAl Viro * more). 122bb898558SAl Viro */ 123bb898558SAl Viro #define UV_MAX_SSI_BLADES 256 124bb898558SAl Viro 125bb898558SAl Viro /* 126bb898558SAl Viro * The largest possible NASID of a C or M brick (+ 2) 127bb898558SAl Viro */ 1281d21e6e3SRobin Holt #define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_BLADES * 2) 129bb898558SAl Viro 130d38bb135SMike Travis /* System Controller Interface Reg info */ 1317f1baa06SMike Travis struct uv_scir_s { 1327f1baa06SMike Travis struct timer_list timer; 1337f1baa06SMike Travis unsigned long offset; 1347f1baa06SMike Travis unsigned long last; 1357f1baa06SMike Travis unsigned long idle_on; 1367f1baa06SMike Travis unsigned long idle_off; 1377f1baa06SMike Travis unsigned char state; 1387f1baa06SMike Travis unsigned char enabled; 1397f1baa06SMike Travis }; 1407f1baa06SMike Travis 141bb898558SAl Viro /* 142bb898558SAl Viro * The following defines attributes of the HUB chip. These attributes are 1430045ddd2SMike Travis * frequently referenced and are kept in a common per hub struct. 1440045ddd2SMike Travis * After setup, the struct is read only, so it should be readily 1450045ddd2SMike Travis * available in the L3 cache on the cpu socket for the node. 146bb898558SAl Viro */ 147bb898558SAl Viro struct uv_hub_info_s { 148bb898558SAl Viro unsigned long global_mmr_base; 149bb898558SAl Viro unsigned long gpa_mask; 150c4ed3f04SJack Steiner unsigned int gnode_extra; 1512a919596SJack Steiner unsigned char hub_revision; 1522a919596SJack Steiner unsigned char apic_pnode_shift; 1536a469e46SJack Steiner unsigned char m_shift; 1546a469e46SJack Steiner unsigned char n_lshift; 155bb898558SAl Viro unsigned long gnode_upper; 156bb898558SAl Viro unsigned long lowmem_remap_top; 157bb898558SAl Viro unsigned long lowmem_remap_base; 158bb898558SAl Viro unsigned short pnode; 159bb898558SAl Viro unsigned short pnode_mask; 160bb898558SAl Viro unsigned short coherency_domain_number; 161bb898558SAl Viro unsigned short numa_blade_id; 162bb898558SAl Viro unsigned char m_val; 163bb898558SAl Viro unsigned char n_val; 164bb898558SAl Viro }; 1657f1baa06SMike Travis 166bb898558SAl Viro DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); 16789cbc767SChristoph Lameter #define uv_hub_info this_cpu_ptr(&__uv_hub_info) 168bb898558SAl Viro #define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu)) 169bb898558SAl Viro 1700045ddd2SMike Travis /* CPU specific info with a pointer to the hub common info struct */ 1710045ddd2SMike Travis struct uv_cpu_info_s { 1720045ddd2SMike Travis void *p_uv_hub_info; 1730045ddd2SMike Travis unsigned char blade_cpu_id; 1740045ddd2SMike Travis struct uv_scir_s scir; 1750045ddd2SMike Travis }; 1760045ddd2SMike Travis DECLARE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info); 1770045ddd2SMike Travis 1780045ddd2SMike Travis #define uv_cpu_info this_cpu_ptr(&__uv_cpu_info) 1790045ddd2SMike Travis #define uv_cpu_info_per(cpu) (&per_cpu(__uv_cpu_info, cpu)) 1800045ddd2SMike Travis 181d38bb135SMike Travis #define uv_scir_info (&uv_cpu_info->scir) 182d38bb135SMike Travis #define uv_cpu_scir_info(cpu) (&uv_cpu_info_per(cpu)->scir) 183d38bb135SMike Travis 1842a919596SJack Steiner /* 1850045ddd2SMike Travis * HUB revision ranges for each UV HUB architecture. 1862a919596SJack Steiner * This is a software convention - NOT the hardware revision numbers in 1872a919596SJack Steiner * the hub chip. 1882a919596SJack Steiner */ 1892a919596SJack Steiner #define UV1_HUB_REVISION_BASE 1 1902a919596SJack Steiner #define UV2_HUB_REVISION_BASE 3 1916edbd471SMike Travis #define UV3_HUB_REVISION_BASE 5 192eb1e3461SMike Travis #define UV4_HUB_REVISION_BASE 7 1932a919596SJack Steiner 194e0ee1c97SMike Travis #ifdef UV1_HUB_IS_SUPPORTED 1952a919596SJack Steiner static inline int is_uv1_hub(void) 1962a919596SJack Steiner { 1972a919596SJack Steiner return uv_hub_info->hub_revision < UV2_HUB_REVISION_BASE; 1982a919596SJack Steiner } 199e0ee1c97SMike Travis #else 200e0ee1c97SMike Travis static inline int is_uv1_hub(void) 201e0ee1c97SMike Travis { 202e0ee1c97SMike Travis return 0; 203e0ee1c97SMike Travis } 204e0ee1c97SMike Travis #endif 2052a919596SJack Steiner 206e0ee1c97SMike Travis #ifdef UV2_HUB_IS_SUPPORTED 2072a919596SJack Steiner static inline int is_uv2_hub(void) 2082a919596SJack Steiner { 2096edbd471SMike Travis return ((uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE) && 2106edbd471SMike Travis (uv_hub_info->hub_revision < UV3_HUB_REVISION_BASE)); 2116edbd471SMike Travis } 212e0ee1c97SMike Travis #else 213e0ee1c97SMike Travis static inline int is_uv2_hub(void) 214e0ee1c97SMike Travis { 215e0ee1c97SMike Travis return 0; 216e0ee1c97SMike Travis } 217e0ee1c97SMike Travis #endif 2186edbd471SMike Travis 219e0ee1c97SMike Travis #ifdef UV3_HUB_IS_SUPPORTED 2206edbd471SMike Travis static inline int is_uv3_hub(void) 2216edbd471SMike Travis { 222eb1e3461SMike Travis return ((uv_hub_info->hub_revision >= UV3_HUB_REVISION_BASE) && 223eb1e3461SMike Travis (uv_hub_info->hub_revision < UV4_HUB_REVISION_BASE)); 2246edbd471SMike Travis } 225e0ee1c97SMike Travis #else 226e0ee1c97SMike Travis static inline int is_uv3_hub(void) 227e0ee1c97SMike Travis { 228e0ee1c97SMike Travis return 0; 229e0ee1c97SMike Travis } 230e0ee1c97SMike Travis #endif 2316edbd471SMike Travis 232eb1e3461SMike Travis #ifdef UV4_HUB_IS_SUPPORTED 233eb1e3461SMike Travis static inline int is_uv4_hub(void) 234eb1e3461SMike Travis { 235eb1e3461SMike Travis return uv_hub_info->hub_revision >= UV4_HUB_REVISION_BASE; 236eb1e3461SMike Travis } 237eb1e3461SMike Travis #else 238eb1e3461SMike Travis static inline int is_uv4_hub(void) 239eb1e3461SMike Travis { 240eb1e3461SMike Travis return 0; 241eb1e3461SMike Travis } 242eb1e3461SMike Travis #endif 243eb1e3461SMike Travis 2446edbd471SMike Travis static inline int is_uvx_hub(void) 2456edbd471SMike Travis { 246e0ee1c97SMike Travis if (uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE) 247e0ee1c97SMike Travis return uv_hub_info->hub_revision; 248e0ee1c97SMike Travis 249e0ee1c97SMike Travis return 0; 250e0ee1c97SMike Travis } 251e0ee1c97SMike Travis 252e0ee1c97SMike Travis static inline int is_uv_hub(void) 253e0ee1c97SMike Travis { 254e0ee1c97SMike Travis #ifdef UV1_HUB_IS_SUPPORTED 255e0ee1c97SMike Travis return uv_hub_info->hub_revision; 256e0ee1c97SMike Travis #endif 257e0ee1c97SMike Travis return is_uvx_hub(); 2582a919596SJack Steiner } 2592a919596SJack Steiner 260c8f730b1SRuss Anderson union uvh_apicid { 261c8f730b1SRuss Anderson unsigned long v; 262c8f730b1SRuss Anderson struct uvh_apicid_s { 263c8f730b1SRuss Anderson unsigned long local_apic_mask : 24; 264c8f730b1SRuss Anderson unsigned long local_apic_shift : 5; 265c8f730b1SRuss Anderson unsigned long unused1 : 3; 266c8f730b1SRuss Anderson unsigned long pnode_mask : 24; 267c8f730b1SRuss Anderson unsigned long pnode_shift : 5; 268c8f730b1SRuss Anderson unsigned long unused2 : 3; 269c8f730b1SRuss Anderson } s; 270c8f730b1SRuss Anderson }; 271c8f730b1SRuss Anderson 272bb898558SAl Viro /* 273bb898558SAl Viro * Local & Global MMR space macros. 274bb898558SAl Viro * Note: macros are intended to be used ONLY by inline functions 275bb898558SAl Viro * in this file - not by other kernel code. 276bb898558SAl Viro * n - NASID (full 15-bit global nasid) 277bb898558SAl Viro * g - GNODE (full 15-bit global nasid, right shifted 1) 278bb898558SAl Viro * p - PNODE (local part of nsids, right shifted 1) 279bb898558SAl Viro */ 280bb898558SAl Viro #define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask) 281c4ed3f04SJack Steiner #define UV_PNODE_TO_GNODE(p) ((p) |uv_hub_info->gnode_extra) 282c4ed3f04SJack Steiner #define UV_PNODE_TO_NASID(p) (UV_PNODE_TO_GNODE(p) << 1) 283bb898558SAl Viro 2842a919596SJack Steiner #define UV1_LOCAL_MMR_BASE 0xf4000000UL 2852a919596SJack Steiner #define UV1_GLOBAL_MMR32_BASE 0xf8000000UL 2862a919596SJack Steiner #define UV1_LOCAL_MMR_SIZE (64UL * 1024 * 1024) 2872a919596SJack Steiner #define UV1_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024) 2882a919596SJack Steiner 2892a919596SJack Steiner #define UV2_LOCAL_MMR_BASE 0xfa000000UL 2902a919596SJack Steiner #define UV2_GLOBAL_MMR32_BASE 0xfc000000UL 2912a919596SJack Steiner #define UV2_LOCAL_MMR_SIZE (32UL * 1024 * 1024) 2922a919596SJack Steiner #define UV2_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024) 2932a919596SJack Steiner 2946edbd471SMike Travis #define UV3_LOCAL_MMR_BASE 0xfa000000UL 2956edbd471SMike Travis #define UV3_GLOBAL_MMR32_BASE 0xfc000000UL 2966edbd471SMike Travis #define UV3_LOCAL_MMR_SIZE (32UL * 1024 * 1024) 2976edbd471SMike Travis #define UV3_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024) 2986edbd471SMike Travis 299eb1e3461SMike Travis #define UV4_LOCAL_MMR_BASE 0xfa000000UL 300eb1e3461SMike Travis #define UV4_GLOBAL_MMR32_BASE 0xfc000000UL 301eb1e3461SMike Travis #define UV4_LOCAL_MMR_SIZE (32UL * 1024 * 1024) 302eb1e3461SMike Travis #define UV4_GLOBAL_MMR32_SIZE (16UL * 1024 * 1024) 303eb1e3461SMike Travis 304eb1e3461SMike Travis #define UV_LOCAL_MMR_BASE ( \ 305eb1e3461SMike Travis is_uv1_hub() ? UV1_LOCAL_MMR_BASE : \ 306eb1e3461SMike Travis is_uv2_hub() ? UV2_LOCAL_MMR_BASE : \ 307eb1e3461SMike Travis is_uv3_hub() ? UV3_LOCAL_MMR_BASE : \ 308eb1e3461SMike Travis /*is_uv4_hub*/ UV4_LOCAL_MMR_BASE) 309eb1e3461SMike Travis 310eb1e3461SMike Travis #define UV_GLOBAL_MMR32_BASE ( \ 311eb1e3461SMike Travis is_uv1_hub() ? UV1_GLOBAL_MMR32_BASE : \ 312eb1e3461SMike Travis is_uv2_hub() ? UV2_GLOBAL_MMR32_BASE : \ 313eb1e3461SMike Travis is_uv3_hub() ? UV3_GLOBAL_MMR32_BASE : \ 314eb1e3461SMike Travis /*is_uv4_hub*/ UV4_GLOBAL_MMR32_BASE) 315eb1e3461SMike Travis 316eb1e3461SMike Travis #define UV_LOCAL_MMR_SIZE ( \ 317eb1e3461SMike Travis is_uv1_hub() ? UV1_LOCAL_MMR_SIZE : \ 318eb1e3461SMike Travis is_uv2_hub() ? UV2_LOCAL_MMR_SIZE : \ 319eb1e3461SMike Travis is_uv3_hub() ? UV3_LOCAL_MMR_SIZE : \ 320eb1e3461SMike Travis /*is_uv4_hub*/ UV4_LOCAL_MMR_SIZE) 321eb1e3461SMike Travis 322eb1e3461SMike Travis #define UV_GLOBAL_MMR32_SIZE ( \ 323eb1e3461SMike Travis is_uv1_hub() ? UV1_GLOBAL_MMR32_SIZE : \ 324eb1e3461SMike Travis is_uv2_hub() ? UV2_GLOBAL_MMR32_SIZE : \ 325eb1e3461SMike Travis is_uv3_hub() ? UV3_GLOBAL_MMR32_SIZE : \ 326eb1e3461SMike Travis /*is_uv4_hub*/ UV4_GLOBAL_MMR32_SIZE) 327eb1e3461SMike Travis 328bb898558SAl Viro #define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base) 329bb898558SAl Viro 33056abcf24SJack Steiner #define UV_GLOBAL_GRU_MMR_BASE 0x4000000 33156abcf24SJack Steiner 332bb898558SAl Viro #define UV_GLOBAL_MMR32_PNODE_SHIFT 15 333bb898558SAl Viro #define UV_GLOBAL_MMR64_PNODE_SHIFT 26 334bb898558SAl Viro 335bb898558SAl Viro #define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT)) 336bb898558SAl Viro 337bb898558SAl Viro #define UV_GLOBAL_MMR64_PNODE_BITS(p) \ 33867e83f30SJack Steiner (((unsigned long)(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT) 339bb898558SAl Viro 340c8f730b1SRuss Anderson #define UVH_APICID 0x002D0E00L 341bb898558SAl Viro #define UV_APIC_PNODE_SHIFT 6 342bb898558SAl Viro 3438191c9f6SDimitri Sivanich #define UV_APICID_HIBIT_MASK 0xffff0000 3448191c9f6SDimitri Sivanich 3457f1baa06SMike Travis /* Local Bus from cpu's perspective */ 3467f1baa06SMike Travis #define LOCAL_BUS_BASE 0x1c00000 3477f1baa06SMike Travis #define LOCAL_BUS_SIZE (4 * 1024 * 1024) 3487f1baa06SMike Travis 3497f1baa06SMike Travis /* 3507f1baa06SMike Travis * System Controller Interface Reg 3517f1baa06SMike Travis * 3527f1baa06SMike Travis * Note there are NO leds on a UV system. This register is only 3537f1baa06SMike Travis * used by the system controller to monitor system-wide operation. 3547f1baa06SMike Travis * There are 64 regs per node. With Nahelem cpus (2 cores per node, 3557f1baa06SMike Travis * 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on 3567f1baa06SMike Travis * a node. 3577f1baa06SMike Travis * 3587f1baa06SMike Travis * The window is located at top of ACPI MMR space 3597f1baa06SMike Travis */ 3607f1baa06SMike Travis #define SCIR_WINDOW_COUNT 64 3617f1baa06SMike Travis #define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \ 3627f1baa06SMike Travis LOCAL_BUS_SIZE - \ 3637f1baa06SMike Travis SCIR_WINDOW_COUNT) 3647f1baa06SMike Travis 3657f1baa06SMike Travis #define SCIR_CPU_HEARTBEAT 0x01 /* timer interrupt */ 3667f1baa06SMike Travis #define SCIR_CPU_ACTIVITY 0x02 /* not idle */ 3677f1baa06SMike Travis #define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */ 3687f1baa06SMike Travis 3698661984fSDimitri Sivanich /* Loop through all installed blades */ 3708661984fSDimitri Sivanich #define for_each_possible_blade(bid) \ 3718661984fSDimitri Sivanich for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++) 3728661984fSDimitri Sivanich 373bb898558SAl Viro /* 374bb898558SAl Viro * Macros for converting between kernel virtual addresses, socket local physical 375bb898558SAl Viro * addresses, and UV global physical addresses. 376bb898558SAl Viro * Note: use the standard __pa() & __va() macros for converting 377bb898558SAl Viro * between socket virtual and socket physical addresses. 378bb898558SAl Viro */ 379bb898558SAl Viro 380bb898558SAl Viro /* socket phys RAM --> UV global physical address */ 381bb898558SAl Viro static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr) 382bb898558SAl Viro { 383bb898558SAl Viro if (paddr < uv_hub_info->lowmem_remap_top) 384189f67c4SJack Steiner paddr |= uv_hub_info->lowmem_remap_base; 3856a469e46SJack Steiner paddr |= uv_hub_info->gnode_upper; 3866a469e46SJack Steiner paddr = ((paddr << uv_hub_info->m_shift) >> uv_hub_info->m_shift) | 3876a469e46SJack Steiner ((paddr >> uv_hub_info->m_val) << uv_hub_info->n_lshift); 3886a469e46SJack Steiner return paddr; 389bb898558SAl Viro } 390bb898558SAl Viro 391bb898558SAl Viro 392bb898558SAl Viro /* socket virtual --> UV global physical address */ 393bb898558SAl Viro static inline unsigned long uv_gpa(void *v) 394bb898558SAl Viro { 395189f67c4SJack Steiner return uv_soc_phys_ram_to_gpa(__pa(v)); 396bb898558SAl Viro } 397bb898558SAl Viro 398fae419f2SRobin Holt /* Top two bits indicate the requested address is in MMR space. */ 399fae419f2SRobin Holt static inline int 400fae419f2SRobin Holt uv_gpa_in_mmr_space(unsigned long gpa) 401fae419f2SRobin Holt { 402fae419f2SRobin Holt return (gpa >> 62) == 0x3UL; 403fae419f2SRobin Holt } 404fae419f2SRobin Holt 405729d69e6SRobin Holt /* UV global physical address --> socket phys RAM */ 406729d69e6SRobin Holt static inline unsigned long uv_gpa_to_soc_phys_ram(unsigned long gpa) 407729d69e6SRobin Holt { 4085a51467bSRuss Anderson unsigned long paddr; 409729d69e6SRobin Holt unsigned long remap_base = uv_hub_info->lowmem_remap_base; 410729d69e6SRobin Holt unsigned long remap_top = uv_hub_info->lowmem_remap_top; 411729d69e6SRobin Holt 4126a469e46SJack Steiner gpa = ((gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift) | 4136a469e46SJack Steiner ((gpa >> uv_hub_info->n_lshift) << uv_hub_info->m_val); 4145a51467bSRuss Anderson paddr = gpa & uv_hub_info->gpa_mask; 415729d69e6SRobin Holt if (paddr >= remap_base && paddr < remap_base + remap_top) 416729d69e6SRobin Holt paddr -= remap_base; 417729d69e6SRobin Holt return paddr; 418729d69e6SRobin Holt } 419729d69e6SRobin Holt 420729d69e6SRobin Holt 4216a469e46SJack Steiner /* gpa -> pnode */ 4221d21e6e3SRobin Holt static inline unsigned long uv_gpa_to_gnode(unsigned long gpa) 4231d21e6e3SRobin Holt { 4246a469e46SJack Steiner return gpa >> uv_hub_info->n_lshift; 4251d21e6e3SRobin Holt } 4261d21e6e3SRobin Holt 4271d21e6e3SRobin Holt /* gpa -> pnode */ 4281d21e6e3SRobin Holt static inline int uv_gpa_to_pnode(unsigned long gpa) 4291d21e6e3SRobin Holt { 4301d21e6e3SRobin Holt unsigned long n_mask = (1UL << uv_hub_info->n_val) - 1; 4311d21e6e3SRobin Holt 4321d21e6e3SRobin Holt return uv_gpa_to_gnode(gpa) & n_mask; 4331d21e6e3SRobin Holt } 4341d21e6e3SRobin Holt 4356a469e46SJack Steiner /* gpa -> node offset*/ 4366a469e46SJack Steiner static inline unsigned long uv_gpa_to_offset(unsigned long gpa) 4376a469e46SJack Steiner { 4386a469e46SJack Steiner return (gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift; 4396a469e46SJack Steiner } 4406a469e46SJack Steiner 441bb898558SAl Viro /* pnode, offset --> socket virtual */ 442bb898558SAl Viro static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset) 443bb898558SAl Viro { 444bb898558SAl Viro return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset); 445bb898558SAl Viro } 446bb898558SAl Viro 447bb898558SAl Viro 448bb898558SAl Viro /* 449bb898558SAl Viro * Extract a PNODE from an APICID (full apicid, not processor subset) 450bb898558SAl Viro */ 451bb898558SAl Viro static inline int uv_apicid_to_pnode(int apicid) 452bb898558SAl Viro { 453c8f730b1SRuss Anderson return (apicid >> uv_hub_info->apic_pnode_shift); 454bb898558SAl Viro } 455bb898558SAl Viro 456bb898558SAl Viro /* 4572a919596SJack Steiner * Convert an apicid to the socket number on the blade 4582a919596SJack Steiner */ 4592a919596SJack Steiner static inline int uv_apicid_to_socket(int apicid) 4602a919596SJack Steiner { 4612a919596SJack Steiner if (is_uv1_hub()) 4622a919596SJack Steiner return (apicid >> (uv_hub_info->apic_pnode_shift - 1)) & 1; 4632a919596SJack Steiner else 4642a919596SJack Steiner return 0; 4652a919596SJack Steiner } 4662a919596SJack Steiner 4672a919596SJack Steiner /* 468bb898558SAl Viro * Access global MMRs using the low memory MMR32 space. This region supports 469bb898558SAl Viro * faster MMR access but not all MMRs are accessible in this space. 470bb898558SAl Viro */ 47139d30770SMike Travis static inline unsigned long *uv_global_mmr32_address(int pnode, unsigned long offset) 472bb898558SAl Viro { 473bb898558SAl Viro return __va(UV_GLOBAL_MMR32_BASE | 474bb898558SAl Viro UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset); 475bb898558SAl Viro } 476bb898558SAl Viro 47739d30770SMike Travis static inline void uv_write_global_mmr32(int pnode, unsigned long offset, unsigned long val) 478bb898558SAl Viro { 4798dc579e8SJack Steiner writeq(val, uv_global_mmr32_address(pnode, offset)); 480bb898558SAl Viro } 481bb898558SAl Viro 48239d30770SMike Travis static inline unsigned long uv_read_global_mmr32(int pnode, unsigned long offset) 483bb898558SAl Viro { 4848dc579e8SJack Steiner return readq(uv_global_mmr32_address(pnode, offset)); 485bb898558SAl Viro } 486bb898558SAl Viro 487bb898558SAl Viro /* 488bb898558SAl Viro * Access Global MMR space using the MMR space located at the top of physical 489bb898558SAl Viro * memory. 490bb898558SAl Viro */ 491a289cc7cSRandy Dunlap static inline volatile void __iomem *uv_global_mmr64_address(int pnode, unsigned long offset) 492bb898558SAl Viro { 493bb898558SAl Viro return __va(UV_GLOBAL_MMR64_BASE | 494bb898558SAl Viro UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset); 495bb898558SAl Viro } 496bb898558SAl Viro 49739d30770SMike Travis static inline void uv_write_global_mmr64(int pnode, unsigned long offset, unsigned long val) 498bb898558SAl Viro { 4998dc579e8SJack Steiner writeq(val, uv_global_mmr64_address(pnode, offset)); 500bb898558SAl Viro } 501bb898558SAl Viro 50239d30770SMike Travis static inline unsigned long uv_read_global_mmr64(int pnode, unsigned long offset) 503bb898558SAl Viro { 5048dc579e8SJack Steiner return readq(uv_global_mmr64_address(pnode, offset)); 505bb898558SAl Viro } 506bb898558SAl Viro 507bb898558SAl Viro /* 50856abcf24SJack Steiner * Global MMR space addresses when referenced by the GRU. (GRU does 50956abcf24SJack Steiner * NOT use socket addressing). 51056abcf24SJack Steiner */ 51156abcf24SJack Steiner static inline unsigned long uv_global_gru_mmr_address(int pnode, unsigned long offset) 51256abcf24SJack Steiner { 513e1e0138dSJack Steiner return UV_GLOBAL_GRU_MMR_BASE | offset | 514e1e0138dSJack Steiner ((unsigned long)pnode << uv_hub_info->m_val); 51556abcf24SJack Steiner } 51656abcf24SJack Steiner 51739d30770SMike Travis static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val) 51839d30770SMike Travis { 51939d30770SMike Travis writeb(val, uv_global_mmr64_address(pnode, offset)); 52039d30770SMike Travis } 52139d30770SMike Travis 52239d30770SMike Travis static inline unsigned char uv_read_global_mmr8(int pnode, unsigned long offset) 52339d30770SMike Travis { 52439d30770SMike Travis return readb(uv_global_mmr64_address(pnode, offset)); 52539d30770SMike Travis } 52639d30770SMike Travis 52756abcf24SJack Steiner /* 528bb898558SAl Viro * Access hub local MMRs. Faster than using global space but only local MMRs 529bb898558SAl Viro * are accessible. 530bb898558SAl Viro */ 531bb898558SAl Viro static inline unsigned long *uv_local_mmr_address(unsigned long offset) 532bb898558SAl Viro { 533bb898558SAl Viro return __va(UV_LOCAL_MMR_BASE | offset); 534bb898558SAl Viro } 535bb898558SAl Viro 536bb898558SAl Viro static inline unsigned long uv_read_local_mmr(unsigned long offset) 537bb898558SAl Viro { 5388dc579e8SJack Steiner return readq(uv_local_mmr_address(offset)); 539bb898558SAl Viro } 540bb898558SAl Viro 541bb898558SAl Viro static inline void uv_write_local_mmr(unsigned long offset, unsigned long val) 542bb898558SAl Viro { 5438dc579e8SJack Steiner writeq(val, uv_local_mmr_address(offset)); 544bb898558SAl Viro } 545bb898558SAl Viro 5467f1baa06SMike Travis static inline unsigned char uv_read_local_mmr8(unsigned long offset) 5477f1baa06SMike Travis { 5488dc579e8SJack Steiner return readb(uv_local_mmr_address(offset)); 5497f1baa06SMike Travis } 5507f1baa06SMike Travis 5517f1baa06SMike Travis static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val) 5527f1baa06SMike Travis { 5538dc579e8SJack Steiner writeb(val, uv_local_mmr_address(offset)); 5547f1baa06SMike Travis } 5557f1baa06SMike Travis 556bb898558SAl Viro /* 557bb898558SAl Viro * Structures and definitions for converting between cpu, node, pnode, and blade 558bb898558SAl Viro * numbers. 559bb898558SAl Viro */ 560bb898558SAl Viro struct uv_blade_info { 561bb898558SAl Viro unsigned short nr_possible_cpus; 562bb898558SAl Viro unsigned short nr_online_cpus; 563bb898558SAl Viro unsigned short pnode; 5646c7184b7SJack Steiner short memory_nid; 565bb898558SAl Viro }; 566bb898558SAl Viro extern struct uv_blade_info *uv_blade_info; 567bb898558SAl Viro extern short *uv_node_to_blade; 568bb898558SAl Viro extern short *uv_cpu_to_blade; 569bb898558SAl Viro extern short uv_possible_blades; 570bb898558SAl Viro 571bb898558SAl Viro /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */ 572bb898558SAl Viro static inline int uv_blade_processor_id(void) 573bb898558SAl Viro { 5745627a825SMike Travis return uv_cpu_info->blade_cpu_id; 575bb898558SAl Viro } 576bb898558SAl Viro 5775627a825SMike Travis /* Blade-local cpu number of cpu N. Numbered 0 .. <# cpus on the blade> */ 5785627a825SMike Travis static inline int uv_cpu_blade_processor_id(int cpu) 5795627a825SMike Travis { 5805627a825SMike Travis return uv_cpu_info_per(cpu)->blade_cpu_id; 5815627a825SMike Travis } 5825627a825SMike Travis #define _uv_cpu_blade_processor_id 1 /* indicate function available */ 5835627a825SMike Travis 584bb898558SAl Viro /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */ 585bb898558SAl Viro static inline int uv_numa_blade_id(void) 586bb898558SAl Viro { 587bb898558SAl Viro return uv_hub_info->numa_blade_id; 588bb898558SAl Viro } 589bb898558SAl Viro 590bb898558SAl Viro /* Convert a cpu number to the the UV blade number */ 591bb898558SAl Viro static inline int uv_cpu_to_blade_id(int cpu) 592bb898558SAl Viro { 593bb898558SAl Viro return uv_cpu_to_blade[cpu]; 594bb898558SAl Viro } 595bb898558SAl Viro 596bb898558SAl Viro /* Convert linux node number to the UV blade number */ 597bb898558SAl Viro static inline int uv_node_to_blade_id(int nid) 598bb898558SAl Viro { 599bb898558SAl Viro return uv_node_to_blade[nid]; 600bb898558SAl Viro } 601bb898558SAl Viro 602bb898558SAl Viro /* Convert a blade id to the PNODE of the blade */ 603bb898558SAl Viro static inline int uv_blade_to_pnode(int bid) 604bb898558SAl Viro { 605bb898558SAl Viro return uv_blade_info[bid].pnode; 606bb898558SAl Viro } 607bb898558SAl Viro 6086c7184b7SJack Steiner /* Nid of memory node on blade. -1 if no blade-local memory */ 6096c7184b7SJack Steiner static inline int uv_blade_to_memory_nid(int bid) 6106c7184b7SJack Steiner { 6116c7184b7SJack Steiner return uv_blade_info[bid].memory_nid; 6126c7184b7SJack Steiner } 6136c7184b7SJack Steiner 614bb898558SAl Viro /* Determine the number of possible cpus on a blade */ 615bb898558SAl Viro static inline int uv_blade_nr_possible_cpus(int bid) 616bb898558SAl Viro { 617bb898558SAl Viro return uv_blade_info[bid].nr_possible_cpus; 618bb898558SAl Viro } 619bb898558SAl Viro 620bb898558SAl Viro /* Determine the number of online cpus on a blade */ 621bb898558SAl Viro static inline int uv_blade_nr_online_cpus(int bid) 622bb898558SAl Viro { 623bb898558SAl Viro return uv_blade_info[bid].nr_online_cpus; 624bb898558SAl Viro } 625bb898558SAl Viro 626bb898558SAl Viro /* Convert a cpu id to the PNODE of the blade containing the cpu */ 627bb898558SAl Viro static inline int uv_cpu_to_pnode(int cpu) 628bb898558SAl Viro { 629bb898558SAl Viro return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode; 630bb898558SAl Viro } 631bb898558SAl Viro 632bb898558SAl Viro /* Convert a linux node number to the PNODE of the blade */ 633bb898558SAl Viro static inline int uv_node_to_pnode(int nid) 634bb898558SAl Viro { 635bb898558SAl Viro return uv_blade_info[uv_node_to_blade_id(nid)].pnode; 636bb898558SAl Viro } 637bb898558SAl Viro 638bb898558SAl Viro /* Maximum possible number of blades */ 639bb898558SAl Viro static inline int uv_num_possible_blades(void) 640bb898558SAl Viro { 641bb898558SAl Viro return uv_possible_blades; 642bb898558SAl Viro } 643bb898558SAl Viro 6440d12ef0cSMike Travis /* Per Hub NMI support */ 6450d12ef0cSMike Travis extern void uv_nmi_setup(void); 6460d12ef0cSMike Travis 6470d12ef0cSMike Travis /* BMC sets a bit this MMR non-zero before sending an NMI */ 6480d12ef0cSMike Travis #define UVH_NMI_MMR UVH_SCRATCH5 6490d12ef0cSMike Travis #define UVH_NMI_MMR_CLEAR UVH_SCRATCH5_ALIAS 6500d12ef0cSMike Travis #define UVH_NMI_MMR_SHIFT 63 6510d12ef0cSMike Travis #define UVH_NMI_MMR_TYPE "SCRATCH5" 6520d12ef0cSMike Travis 6530d12ef0cSMike Travis /* Newer SMM NMI handler, not present in all systems */ 6540d12ef0cSMike Travis #define UVH_NMI_MMRX UVH_EVENT_OCCURRED0 6550d12ef0cSMike Travis #define UVH_NMI_MMRX_CLEAR UVH_EVENT_OCCURRED0_ALIAS 656c443c03dSMike Travis #define UVH_NMI_MMRX_SHIFT UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT 6570d12ef0cSMike Travis #define UVH_NMI_MMRX_TYPE "EXTIO_INT0" 6580d12ef0cSMike Travis 6590d12ef0cSMike Travis /* Non-zero indicates newer SMM NMI handler present */ 6600d12ef0cSMike Travis #define UVH_NMI_MMRX_SUPPORTED UVH_EXTIO_INT0_BROADCAST 6610d12ef0cSMike Travis 6620d12ef0cSMike Travis /* Indicates to BIOS that we want to use the newer SMM NMI handler */ 6630d12ef0cSMike Travis #define UVH_NMI_MMRX_REQ UVH_SCRATCH5_ALIAS_2 6640d12ef0cSMike Travis #define UVH_NMI_MMRX_REQ_SHIFT 62 6650d12ef0cSMike Travis 6660d12ef0cSMike Travis struct uv_hub_nmi_s { 6670d12ef0cSMike Travis raw_spinlock_t nmi_lock; 6680d12ef0cSMike Travis atomic_t in_nmi; /* flag this node in UV NMI IRQ */ 6690d12ef0cSMike Travis atomic_t cpu_owner; /* last locker of this struct */ 6700d12ef0cSMike Travis atomic_t read_mmr_count; /* count of MMR reads */ 6710d12ef0cSMike Travis atomic_t nmi_count; /* count of true UV NMIs */ 6720d12ef0cSMike Travis unsigned long nmi_value; /* last value read from NMI MMR */ 6730d12ef0cSMike Travis }; 6740d12ef0cSMike Travis 6750d12ef0cSMike Travis struct uv_cpu_nmi_s { 6760d12ef0cSMike Travis struct uv_hub_nmi_s *hub; 677e1632170SChristoph Lameter int state; 678e1632170SChristoph Lameter int pinging; 6790d12ef0cSMike Travis int queries; 6800d12ef0cSMike Travis int pings; 6810d12ef0cSMike Travis }; 6820d12ef0cSMike Travis 683e1632170SChristoph Lameter DECLARE_PER_CPU(struct uv_cpu_nmi_s, uv_cpu_nmi); 684e1632170SChristoph Lameter 6857c52198bSGeorge Beshers #define uv_hub_nmi this_cpu_read(uv_cpu_nmi.hub) 686e1632170SChristoph Lameter #define uv_cpu_nmi_per(cpu) (per_cpu(uv_cpu_nmi, cpu)) 6870d12ef0cSMike Travis #define uv_hub_nmi_per(cpu) (uv_cpu_nmi_per(cpu).hub) 6880d12ef0cSMike Travis 6890d12ef0cSMike Travis /* uv_cpu_nmi_states */ 6900d12ef0cSMike Travis #define UV_NMI_STATE_OUT 0 6910d12ef0cSMike Travis #define UV_NMI_STATE_IN 1 6920d12ef0cSMike Travis #define UV_NMI_STATE_DUMP 2 6930d12ef0cSMike Travis #define UV_NMI_STATE_DUMP_DONE 3 6940d12ef0cSMike Travis 6957f1baa06SMike Travis /* Update SCIR state */ 6967f1baa06SMike Travis static inline void uv_set_scir_bits(unsigned char value) 6977f1baa06SMike Travis { 698d38bb135SMike Travis if (uv_scir_info->state != value) { 699d38bb135SMike Travis uv_scir_info->state = value; 700d38bb135SMike Travis uv_write_local_mmr8(uv_scir_info->offset, value); 7017f1baa06SMike Travis } 7027f1baa06SMike Travis } 70366666e50SJack Steiner 70439d30770SMike Travis static inline unsigned long uv_scir_offset(int apicid) 70539d30770SMike Travis { 70639d30770SMike Travis return SCIR_LOCAL_MMR_BASE | (apicid & 0x3f); 70739d30770SMike Travis } 70839d30770SMike Travis 7097f1baa06SMike Travis static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value) 7107f1baa06SMike Travis { 711d38bb135SMike Travis if (uv_cpu_scir_info(cpu)->state != value) { 71239d30770SMike Travis uv_write_global_mmr8(uv_cpu_to_pnode(cpu), 713d38bb135SMike Travis uv_cpu_scir_info(cpu)->offset, value); 714d38bb135SMike Travis uv_cpu_scir_info(cpu)->state = value; 7157f1baa06SMike Travis } 7167f1baa06SMike Travis } 717bb898558SAl Viro 7188191c9f6SDimitri Sivanich extern unsigned int uv_apicid_hibits; 71956abcf24SJack Steiner static unsigned long uv_hub_ipi_value(int apicid, int vector, int mode) 72056abcf24SJack Steiner { 7218191c9f6SDimitri Sivanich apicid |= uv_apicid_hibits; 72256abcf24SJack Steiner return (1UL << UVH_IPI_INT_SEND_SHFT) | 72356abcf24SJack Steiner ((apicid) << UVH_IPI_INT_APIC_ID_SHFT) | 72456abcf24SJack Steiner (mode << UVH_IPI_INT_DELIVERY_MODE_SHFT) | 72556abcf24SJack Steiner (vector << UVH_IPI_INT_VECTOR_SHFT); 72656abcf24SJack Steiner } 72756abcf24SJack Steiner 72866666e50SJack Steiner static inline void uv_hub_send_ipi(int pnode, int apicid, int vector) 72966666e50SJack Steiner { 73066666e50SJack Steiner unsigned long val; 73102dd0a06SRobin Holt unsigned long dmode = dest_Fixed; 73202dd0a06SRobin Holt 73302dd0a06SRobin Holt if (vector == NMI_VECTOR) 73402dd0a06SRobin Holt dmode = dest_NMI; 73566666e50SJack Steiner 73656abcf24SJack Steiner val = uv_hub_ipi_value(apicid, vector, dmode); 73766666e50SJack Steiner uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 73866666e50SJack Steiner } 73966666e50SJack Steiner 7407a1110e8SJack Steiner /* 7417a1110e8SJack Steiner * Get the minimum revision number of the hub chips within the partition. 742eb1e3461SMike Travis * (See UVx_HUB_REVISION_BASE above for specific values.) 7437a1110e8SJack Steiner */ 7447a1110e8SJack Steiner static inline int uv_get_min_hub_revision_id(void) 7457a1110e8SJack Steiner { 7462a919596SJack Steiner return uv_hub_info->hub_revision; 7477a1110e8SJack Steiner } 7487a1110e8SJack Steiner 749bc5d9940SJack Steiner #endif /* CONFIG_X86_64 */ 7507f1baa06SMike Travis #endif /* _ASM_X86_UV_UV_HUB_H */ 751