1bb898558SAl Viro /* 2bb898558SAl Viro * This file is subject to the terms and conditions of the GNU General Public 3bb898558SAl Viro * License. See the file "COPYING" in the main directory of this archive 4bb898558SAl Viro * for more details. 5bb898558SAl Viro * 6bb898558SAl Viro * SGI UV architectural definitions 7bb898558SAl Viro * 85f40f7d9SDimitri Sivanich * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved. 9bb898558SAl Viro */ 10bb898558SAl Viro 1105e4d316SH. Peter Anvin #ifndef _ASM_X86_UV_UV_HUB_H 1205e4d316SH. Peter Anvin #define _ASM_X86_UV_UV_HUB_H 13bb898558SAl Viro 14bc5d9940SJack Steiner #ifdef CONFIG_X86_64 15bb898558SAl Viro #include <linux/numa.h> 16bb898558SAl Viro #include <linux/percpu.h> 17c08b6accSMike Travis #include <linux/timer.h> 188dc579e8SJack Steiner #include <linux/io.h> 19906f3b20SMike Travis #include <linux/topology.h> 20bb898558SAl Viro #include <asm/types.h> 21bb898558SAl Viro #include <asm/percpu.h> 2266666e50SJack Steiner #include <asm/uv/uv_mmrs.h> 2302dd0a06SRobin Holt #include <asm/irq_vectors.h> 2402dd0a06SRobin Holt #include <asm/io_apic.h> 25bb898558SAl Viro 26bb898558SAl Viro 27bb898558SAl Viro /* 28bb898558SAl Viro * Addressing Terminology 29bb898558SAl Viro * 30bb898558SAl Viro * M - The low M bits of a physical address represent the offset 31bb898558SAl Viro * into the blade local memory. RAM memory on a blade is physically 32bb898558SAl Viro * contiguous (although various IO spaces may punch holes in 33bb898558SAl Viro * it).. 34bb898558SAl Viro * 35bb898558SAl Viro * N - Number of bits in the node portion of a socket physical 36bb898558SAl Viro * address. 37bb898558SAl Viro * 38bb898558SAl Viro * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of 39bb898558SAl Viro * routers always have low bit of 1, C/MBricks have low bit 40bb898558SAl Viro * equal to 0. Most addressing macros that target UV hub chips 41bb898558SAl Viro * right shift the NASID by 1 to exclude the always-zero bit. 42bb898558SAl Viro * NASIDs contain up to 15 bits. 43bb898558SAl Viro * 44bb898558SAl Viro * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead 45bb898558SAl Viro * of nasids. 46bb898558SAl Viro * 47bb898558SAl Viro * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant 48bb898558SAl Viro * of the nasid for socket usage. 49bb898558SAl Viro * 506a469e46SJack Steiner * GPA - (global physical address) a socket physical address converted 516a469e46SJack Steiner * so that it can be used by the GRU as a global address. Socket 526a469e46SJack Steiner * physical addresses 1) need additional NASID (node) bits added 536a469e46SJack Steiner * to the high end of the address, and 2) unaliased if the 546a469e46SJack Steiner * partition does not have a physical address 0. In addition, on 556a469e46SJack Steiner * UV2 rev 1, GPAs need the gnode left shifted to bits 39 or 40. 566a469e46SJack Steiner * 57bb898558SAl Viro * 58bb898558SAl Viro * NumaLink Global Physical Address Format: 59bb898558SAl Viro * +--------------------------------+---------------------+ 60bb898558SAl Viro * |00..000| GNODE | NodeOffset | 61bb898558SAl Viro * +--------------------------------+---------------------+ 62bb898558SAl Viro * |<-------53 - M bits --->|<--------M bits -----> 63bb898558SAl Viro * 64bb898558SAl Viro * M - number of node offset bits (35 .. 40) 65bb898558SAl Viro * 66bb898558SAl Viro * 67bb898558SAl Viro * Memory/UV-HUB Processor Socket Address Format: 68bb898558SAl Viro * +----------------+---------------+---------------------+ 69bb898558SAl Viro * |00..000000000000| PNODE | NodeOffset | 70bb898558SAl Viro * +----------------+---------------+---------------------+ 71bb898558SAl Viro * <--- N bits --->|<--------M bits -----> 72bb898558SAl Viro * 73bb898558SAl Viro * M - number of node offset bits (35 .. 40) 74bb898558SAl Viro * N - number of PNODE bits (0 .. 10) 75bb898558SAl Viro * 76bb898558SAl Viro * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64). 77bb898558SAl Viro * The actual values are configuration dependent and are set at 78bb898558SAl Viro * boot time. M & N values are set by the hardware/BIOS at boot. 79bb898558SAl Viro * 80bb898558SAl Viro * 81bb898558SAl Viro * APICID format 82bb898558SAl Viro * NOTE!!!!!! This is the current format of the APICID. However, code 83bb898558SAl Viro * should assume that this will change in the future. Use functions 84bb898558SAl Viro * in this file for all APICID bit manipulations and conversion. 85bb898558SAl Viro * 86bb898558SAl Viro * 1111110000000000 87bb898558SAl Viro * 5432109876543210 882a919596SJack Steiner * pppppppppplc0cch Nehalem-EX (12 bits in hdw reg) 892a919596SJack Steiner * ppppppppplcc0cch Westmere-EX (12 bits in hdw reg) 902a919596SJack Steiner * pppppppppppcccch SandyBridge (15 bits in hdw reg) 91bb898558SAl Viro * sssssssssss 92bb898558SAl Viro * 93bb898558SAl Viro * p = pnode bits 94bb898558SAl Viro * l = socket number on board 95bb898558SAl Viro * c = core 96bb898558SAl Viro * h = hyperthread 97bb898558SAl Viro * s = bits that are in the SOCKET_ID CSR 98bb898558SAl Viro * 992a919596SJack Steiner * Note: Processor may support fewer bits in the APICID register. The ACPI 100bb898558SAl Viro * tables hold all 16 bits. Software needs to be aware of this. 101bb898558SAl Viro * 102bb898558SAl Viro * Unless otherwise specified, all references to APICID refer to 103bb898558SAl Viro * the FULL value contained in ACPI tables, not the subset in the 104bb898558SAl Viro * processor APICID register. 105bb898558SAl Viro */ 106bb898558SAl Viro 107bb898558SAl Viro 108bb898558SAl Viro /* 109bb898558SAl Viro * Maximum number of bricks in all partitions and in all coherency domains. 110bb898558SAl Viro * This is the total number of bricks accessible in the numalink fabric. It 111bb898558SAl Viro * includes all C & M bricks. Routers are NOT included. 112bb898558SAl Viro * 113bb898558SAl Viro * This value is also the value of the maximum number of non-router NASIDs 114bb898558SAl Viro * in the numalink fabric. 115bb898558SAl Viro * 116bb898558SAl Viro * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused. 117bb898558SAl Viro */ 118bb898558SAl Viro #define UV_MAX_NUMALINK_BLADES 16384 119bb898558SAl Viro 120bb898558SAl Viro /* 121bb898558SAl Viro * Maximum number of C/Mbricks within a software SSI (hardware may support 122bb898558SAl Viro * more). 123bb898558SAl Viro */ 124bb898558SAl Viro #define UV_MAX_SSI_BLADES 256 125bb898558SAl Viro 126bb898558SAl Viro /* 127bb898558SAl Viro * The largest possible NASID of a C or M brick (+ 2) 128bb898558SAl Viro */ 1291d21e6e3SRobin Holt #define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_BLADES * 2) 130bb898558SAl Viro 131d38bb135SMike Travis /* System Controller Interface Reg info */ 1327f1baa06SMike Travis struct uv_scir_s { 1337f1baa06SMike Travis struct timer_list timer; 1347f1baa06SMike Travis unsigned long offset; 1357f1baa06SMike Travis unsigned long last; 1367f1baa06SMike Travis unsigned long idle_on; 1377f1baa06SMike Travis unsigned long idle_off; 1387f1baa06SMike Travis unsigned char state; 1397f1baa06SMike Travis unsigned char enabled; 1407f1baa06SMike Travis }; 1417f1baa06SMike Travis 142bb898558SAl Viro /* 143bb898558SAl Viro * The following defines attributes of the HUB chip. These attributes are 1440045ddd2SMike Travis * frequently referenced and are kept in a common per hub struct. 1450045ddd2SMike Travis * After setup, the struct is read only, so it should be readily 1460045ddd2SMike Travis * available in the L3 cache on the cpu socket for the node. 147bb898558SAl Viro */ 148bb898558SAl Viro struct uv_hub_info_s { 149bb898558SAl Viro unsigned long global_mmr_base; 1501de329c1SMike Travis unsigned long global_mmr_shift; 151bb898558SAl Viro unsigned long gpa_mask; 1521de329c1SMike Travis unsigned short min_socket; 1531de329c1SMike Travis unsigned short min_pnode; 1542a919596SJack Steiner unsigned char hub_revision; 1552a919596SJack Steiner unsigned char apic_pnode_shift; 1561de329c1SMike Travis unsigned char gpa_shift; 1576a469e46SJack Steiner unsigned char m_shift; 1586a469e46SJack Steiner unsigned char n_lshift; 1591de329c1SMike Travis unsigned int gnode_extra; 160bb898558SAl Viro unsigned long gnode_upper; 161bb898558SAl Viro unsigned long lowmem_remap_top; 162bb898558SAl Viro unsigned long lowmem_remap_base; 1631de329c1SMike Travis unsigned long global_gru_base; 1641de329c1SMike Travis unsigned long global_gru_shift; 165bb898558SAl Viro unsigned short pnode; 166bb898558SAl Viro unsigned short pnode_mask; 167bb898558SAl Viro unsigned short coherency_domain_number; 168bb898558SAl Viro unsigned short numa_blade_id; 169bb898558SAl Viro unsigned char m_val; 170bb898558SAl Viro unsigned char n_val; 171906f3b20SMike Travis unsigned short nr_possible_cpus; 172906f3b20SMike Travis unsigned short nr_online_cpus; 173906f3b20SMike Travis short memory_nid; 174bb898558SAl Viro }; 1757f1baa06SMike Travis 1760045ddd2SMike Travis /* CPU specific info with a pointer to the hub common info struct */ 1770045ddd2SMike Travis struct uv_cpu_info_s { 1780045ddd2SMike Travis void *p_uv_hub_info; 1790045ddd2SMike Travis unsigned char blade_cpu_id; 1800045ddd2SMike Travis struct uv_scir_s scir; 1810045ddd2SMike Travis }; 1820045ddd2SMike Travis DECLARE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info); 1830045ddd2SMike Travis 1840045ddd2SMike Travis #define uv_cpu_info this_cpu_ptr(&__uv_cpu_info) 1850045ddd2SMike Travis #define uv_cpu_info_per(cpu) (&per_cpu(__uv_cpu_info, cpu)) 1860045ddd2SMike Travis 187d38bb135SMike Travis #define uv_scir_info (&uv_cpu_info->scir) 188d38bb135SMike Travis #define uv_cpu_scir_info(cpu) (&uv_cpu_info_per(cpu)->scir) 189d38bb135SMike Travis 1903edcf2ffSMike Travis /* Node specific hub common info struct */ 1913edcf2ffSMike Travis extern void **__uv_hub_info_list; 1923edcf2ffSMike Travis static inline struct uv_hub_info_s *uv_hub_info_list(int node) 1933edcf2ffSMike Travis { 1943edcf2ffSMike Travis return (struct uv_hub_info_s *)__uv_hub_info_list[node]; 1953edcf2ffSMike Travis } 1963edcf2ffSMike Travis 1973edcf2ffSMike Travis static inline struct uv_hub_info_s *_uv_hub_info(void) 1983edcf2ffSMike Travis { 1993edcf2ffSMike Travis return (struct uv_hub_info_s *)uv_cpu_info->p_uv_hub_info; 2003edcf2ffSMike Travis } 2013edcf2ffSMike Travis #define uv_hub_info _uv_hub_info() 2023edcf2ffSMike Travis 2033edcf2ffSMike Travis static inline struct uv_hub_info_s *uv_cpu_hub_info(int cpu) 2043edcf2ffSMike Travis { 2053edcf2ffSMike Travis return (struct uv_hub_info_s *)uv_cpu_info_per(cpu)->p_uv_hub_info; 2063edcf2ffSMike Travis } 2073edcf2ffSMike Travis 2083edcf2ffSMike Travis #define UV_HUB_INFO_VERSION 0x7150 2093edcf2ffSMike Travis extern int uv_hub_info_version(void); 2103edcf2ffSMike Travis static inline int uv_hub_info_check(int version) 2113edcf2ffSMike Travis { 2123edcf2ffSMike Travis if (uv_hub_info_version() == version) 2133edcf2ffSMike Travis return 0; 2143edcf2ffSMike Travis 2153edcf2ffSMike Travis pr_crit("UV: uv_hub_info version(%x) mismatch, expecting(%x)\n", 2163edcf2ffSMike Travis uv_hub_info_version(), version); 2173edcf2ffSMike Travis 2183edcf2ffSMike Travis BUG(); /* Catastrophic - cannot continue on unknown UV system */ 2193edcf2ffSMike Travis } 2203edcf2ffSMike Travis #define _uv_hub_info_check() uv_hub_info_check(UV_HUB_INFO_VERSION) 2213edcf2ffSMike Travis 2222a919596SJack Steiner /* 2230045ddd2SMike Travis * HUB revision ranges for each UV HUB architecture. 2242a919596SJack Steiner * This is a software convention - NOT the hardware revision numbers in 2252a919596SJack Steiner * the hub chip. 2262a919596SJack Steiner */ 2272a919596SJack Steiner #define UV1_HUB_REVISION_BASE 1 2282a919596SJack Steiner #define UV2_HUB_REVISION_BASE 3 2296edbd471SMike Travis #define UV3_HUB_REVISION_BASE 5 230eb1e3461SMike Travis #define UV4_HUB_REVISION_BASE 7 2312a919596SJack Steiner 232e0ee1c97SMike Travis #ifdef UV1_HUB_IS_SUPPORTED 2332a919596SJack Steiner static inline int is_uv1_hub(void) 2342a919596SJack Steiner { 2352a919596SJack Steiner return uv_hub_info->hub_revision < UV2_HUB_REVISION_BASE; 2362a919596SJack Steiner } 237e0ee1c97SMike Travis #else 238e0ee1c97SMike Travis static inline int is_uv1_hub(void) 239e0ee1c97SMike Travis { 240e0ee1c97SMike Travis return 0; 241e0ee1c97SMike Travis } 242e0ee1c97SMike Travis #endif 2432a919596SJack Steiner 244e0ee1c97SMike Travis #ifdef UV2_HUB_IS_SUPPORTED 2452a919596SJack Steiner static inline int is_uv2_hub(void) 2462a919596SJack Steiner { 2476edbd471SMike Travis return ((uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE) && 2486edbd471SMike Travis (uv_hub_info->hub_revision < UV3_HUB_REVISION_BASE)); 2496edbd471SMike Travis } 250e0ee1c97SMike Travis #else 251e0ee1c97SMike Travis static inline int is_uv2_hub(void) 252e0ee1c97SMike Travis { 253e0ee1c97SMike Travis return 0; 254e0ee1c97SMike Travis } 255e0ee1c97SMike Travis #endif 2566edbd471SMike Travis 257e0ee1c97SMike Travis #ifdef UV3_HUB_IS_SUPPORTED 2586edbd471SMike Travis static inline int is_uv3_hub(void) 2596edbd471SMike Travis { 260eb1e3461SMike Travis return ((uv_hub_info->hub_revision >= UV3_HUB_REVISION_BASE) && 261eb1e3461SMike Travis (uv_hub_info->hub_revision < UV4_HUB_REVISION_BASE)); 2626edbd471SMike Travis } 263e0ee1c97SMike Travis #else 264e0ee1c97SMike Travis static inline int is_uv3_hub(void) 265e0ee1c97SMike Travis { 266e0ee1c97SMike Travis return 0; 267e0ee1c97SMike Travis } 268e0ee1c97SMike Travis #endif 2696edbd471SMike Travis 270eb1e3461SMike Travis #ifdef UV4_HUB_IS_SUPPORTED 271eb1e3461SMike Travis static inline int is_uv4_hub(void) 272eb1e3461SMike Travis { 273eb1e3461SMike Travis return uv_hub_info->hub_revision >= UV4_HUB_REVISION_BASE; 274eb1e3461SMike Travis } 275eb1e3461SMike Travis #else 276eb1e3461SMike Travis static inline int is_uv4_hub(void) 277eb1e3461SMike Travis { 278eb1e3461SMike Travis return 0; 279eb1e3461SMike Travis } 280eb1e3461SMike Travis #endif 281eb1e3461SMike Travis 2826edbd471SMike Travis static inline int is_uvx_hub(void) 2836edbd471SMike Travis { 284e0ee1c97SMike Travis if (uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE) 285e0ee1c97SMike Travis return uv_hub_info->hub_revision; 286e0ee1c97SMike Travis 287e0ee1c97SMike Travis return 0; 288e0ee1c97SMike Travis } 289e0ee1c97SMike Travis 290e0ee1c97SMike Travis static inline int is_uv_hub(void) 291e0ee1c97SMike Travis { 292e0ee1c97SMike Travis #ifdef UV1_HUB_IS_SUPPORTED 293e0ee1c97SMike Travis return uv_hub_info->hub_revision; 294e0ee1c97SMike Travis #endif 295e0ee1c97SMike Travis return is_uvx_hub(); 2962a919596SJack Steiner } 2972a919596SJack Steiner 298c8f730b1SRuss Anderson union uvh_apicid { 299c8f730b1SRuss Anderson unsigned long v; 300c8f730b1SRuss Anderson struct uvh_apicid_s { 301c8f730b1SRuss Anderson unsigned long local_apic_mask : 24; 302c8f730b1SRuss Anderson unsigned long local_apic_shift : 5; 303c8f730b1SRuss Anderson unsigned long unused1 : 3; 304c8f730b1SRuss Anderson unsigned long pnode_mask : 24; 305c8f730b1SRuss Anderson unsigned long pnode_shift : 5; 306c8f730b1SRuss Anderson unsigned long unused2 : 3; 307c8f730b1SRuss Anderson } s; 308c8f730b1SRuss Anderson }; 309c8f730b1SRuss Anderson 310bb898558SAl Viro /* 311bb898558SAl Viro * Local & Global MMR space macros. 312bb898558SAl Viro * Note: macros are intended to be used ONLY by inline functions 313bb898558SAl Viro * in this file - not by other kernel code. 314bb898558SAl Viro * n - NASID (full 15-bit global nasid) 315bb898558SAl Viro * g - GNODE (full 15-bit global nasid, right shifted 1) 316bb898558SAl Viro * p - PNODE (local part of nsids, right shifted 1) 317bb898558SAl Viro */ 318bb898558SAl Viro #define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask) 319c4ed3f04SJack Steiner #define UV_PNODE_TO_GNODE(p) ((p) |uv_hub_info->gnode_extra) 320c4ed3f04SJack Steiner #define UV_PNODE_TO_NASID(p) (UV_PNODE_TO_GNODE(p) << 1) 321bb898558SAl Viro 3222a919596SJack Steiner #define UV1_LOCAL_MMR_BASE 0xf4000000UL 3232a919596SJack Steiner #define UV1_GLOBAL_MMR32_BASE 0xf8000000UL 3242a919596SJack Steiner #define UV1_LOCAL_MMR_SIZE (64UL * 1024 * 1024) 3252a919596SJack Steiner #define UV1_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024) 3262a919596SJack Steiner 3272a919596SJack Steiner #define UV2_LOCAL_MMR_BASE 0xfa000000UL 3282a919596SJack Steiner #define UV2_GLOBAL_MMR32_BASE 0xfc000000UL 3292a919596SJack Steiner #define UV2_LOCAL_MMR_SIZE (32UL * 1024 * 1024) 3302a919596SJack Steiner #define UV2_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024) 3312a919596SJack Steiner 3326edbd471SMike Travis #define UV3_LOCAL_MMR_BASE 0xfa000000UL 3336edbd471SMike Travis #define UV3_GLOBAL_MMR32_BASE 0xfc000000UL 3346edbd471SMike Travis #define UV3_LOCAL_MMR_SIZE (32UL * 1024 * 1024) 3356edbd471SMike Travis #define UV3_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024) 3366edbd471SMike Travis 337eb1e3461SMike Travis #define UV4_LOCAL_MMR_BASE 0xfa000000UL 338eb1e3461SMike Travis #define UV4_GLOBAL_MMR32_BASE 0xfc000000UL 339eb1e3461SMike Travis #define UV4_LOCAL_MMR_SIZE (32UL * 1024 * 1024) 340eb1e3461SMike Travis #define UV4_GLOBAL_MMR32_SIZE (16UL * 1024 * 1024) 341eb1e3461SMike Travis 342eb1e3461SMike Travis #define UV_LOCAL_MMR_BASE ( \ 343eb1e3461SMike Travis is_uv1_hub() ? UV1_LOCAL_MMR_BASE : \ 344eb1e3461SMike Travis is_uv2_hub() ? UV2_LOCAL_MMR_BASE : \ 345eb1e3461SMike Travis is_uv3_hub() ? UV3_LOCAL_MMR_BASE : \ 346eb1e3461SMike Travis /*is_uv4_hub*/ UV4_LOCAL_MMR_BASE) 347eb1e3461SMike Travis 348eb1e3461SMike Travis #define UV_GLOBAL_MMR32_BASE ( \ 349eb1e3461SMike Travis is_uv1_hub() ? UV1_GLOBAL_MMR32_BASE : \ 350eb1e3461SMike Travis is_uv2_hub() ? UV2_GLOBAL_MMR32_BASE : \ 351eb1e3461SMike Travis is_uv3_hub() ? UV3_GLOBAL_MMR32_BASE : \ 352eb1e3461SMike Travis /*is_uv4_hub*/ UV4_GLOBAL_MMR32_BASE) 353eb1e3461SMike Travis 354eb1e3461SMike Travis #define UV_LOCAL_MMR_SIZE ( \ 355eb1e3461SMike Travis is_uv1_hub() ? UV1_LOCAL_MMR_SIZE : \ 356eb1e3461SMike Travis is_uv2_hub() ? UV2_LOCAL_MMR_SIZE : \ 357eb1e3461SMike Travis is_uv3_hub() ? UV3_LOCAL_MMR_SIZE : \ 358eb1e3461SMike Travis /*is_uv4_hub*/ UV4_LOCAL_MMR_SIZE) 359eb1e3461SMike Travis 360eb1e3461SMike Travis #define UV_GLOBAL_MMR32_SIZE ( \ 361eb1e3461SMike Travis is_uv1_hub() ? UV1_GLOBAL_MMR32_SIZE : \ 362eb1e3461SMike Travis is_uv2_hub() ? UV2_GLOBAL_MMR32_SIZE : \ 363eb1e3461SMike Travis is_uv3_hub() ? UV3_GLOBAL_MMR32_SIZE : \ 364eb1e3461SMike Travis /*is_uv4_hub*/ UV4_GLOBAL_MMR32_SIZE) 365eb1e3461SMike Travis 366bb898558SAl Viro #define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base) 367bb898558SAl Viro 36856abcf24SJack Steiner #define UV_GLOBAL_GRU_MMR_BASE 0x4000000 36956abcf24SJack Steiner 370bb898558SAl Viro #define UV_GLOBAL_MMR32_PNODE_SHIFT 15 3711de329c1SMike Travis #define _UV_GLOBAL_MMR64_PNODE_SHIFT 26 3721de329c1SMike Travis #define UV_GLOBAL_MMR64_PNODE_SHIFT (uv_hub_info->global_mmr_shift) 373bb898558SAl Viro 374bb898558SAl Viro #define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT)) 375bb898558SAl Viro 376bb898558SAl Viro #define UV_GLOBAL_MMR64_PNODE_BITS(p) \ 37767e83f30SJack Steiner (((unsigned long)(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT) 378bb898558SAl Viro 379c8f730b1SRuss Anderson #define UVH_APICID 0x002D0E00L 380bb898558SAl Viro #define UV_APIC_PNODE_SHIFT 6 381bb898558SAl Viro 3828191c9f6SDimitri Sivanich #define UV_APICID_HIBIT_MASK 0xffff0000 3838191c9f6SDimitri Sivanich 3847f1baa06SMike Travis /* Local Bus from cpu's perspective */ 3857f1baa06SMike Travis #define LOCAL_BUS_BASE 0x1c00000 3867f1baa06SMike Travis #define LOCAL_BUS_SIZE (4 * 1024 * 1024) 3877f1baa06SMike Travis 3887f1baa06SMike Travis /* 3897f1baa06SMike Travis * System Controller Interface Reg 3907f1baa06SMike Travis * 3917f1baa06SMike Travis * Note there are NO leds on a UV system. This register is only 3927f1baa06SMike Travis * used by the system controller to monitor system-wide operation. 3937f1baa06SMike Travis * There are 64 regs per node. With Nahelem cpus (2 cores per node, 3947f1baa06SMike Travis * 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on 3957f1baa06SMike Travis * a node. 3967f1baa06SMike Travis * 3977f1baa06SMike Travis * The window is located at top of ACPI MMR space 3987f1baa06SMike Travis */ 3997f1baa06SMike Travis #define SCIR_WINDOW_COUNT 64 4007f1baa06SMike Travis #define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \ 4017f1baa06SMike Travis LOCAL_BUS_SIZE - \ 4027f1baa06SMike Travis SCIR_WINDOW_COUNT) 4037f1baa06SMike Travis 4047f1baa06SMike Travis #define SCIR_CPU_HEARTBEAT 0x01 /* timer interrupt */ 4057f1baa06SMike Travis #define SCIR_CPU_ACTIVITY 0x02 /* not idle */ 4067f1baa06SMike Travis #define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */ 4077f1baa06SMike Travis 4088661984fSDimitri Sivanich /* Loop through all installed blades */ 4098661984fSDimitri Sivanich #define for_each_possible_blade(bid) \ 4108661984fSDimitri Sivanich for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++) 4118661984fSDimitri Sivanich 412bb898558SAl Viro /* 413bb898558SAl Viro * Macros for converting between kernel virtual addresses, socket local physical 414bb898558SAl Viro * addresses, and UV global physical addresses. 415bb898558SAl Viro * Note: use the standard __pa() & __va() macros for converting 416bb898558SAl Viro * between socket virtual and socket physical addresses. 417bb898558SAl Viro */ 418bb898558SAl Viro 419bb898558SAl Viro /* socket phys RAM --> UV global physical address */ 420bb898558SAl Viro static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr) 421bb898558SAl Viro { 422bb898558SAl Viro if (paddr < uv_hub_info->lowmem_remap_top) 423189f67c4SJack Steiner paddr |= uv_hub_info->lowmem_remap_base; 4246a469e46SJack Steiner paddr |= uv_hub_info->gnode_upper; 4256a469e46SJack Steiner paddr = ((paddr << uv_hub_info->m_shift) >> uv_hub_info->m_shift) | 4266a469e46SJack Steiner ((paddr >> uv_hub_info->m_val) << uv_hub_info->n_lshift); 4276a469e46SJack Steiner return paddr; 428bb898558SAl Viro } 429bb898558SAl Viro 430bb898558SAl Viro 431bb898558SAl Viro /* socket virtual --> UV global physical address */ 432bb898558SAl Viro static inline unsigned long uv_gpa(void *v) 433bb898558SAl Viro { 434189f67c4SJack Steiner return uv_soc_phys_ram_to_gpa(__pa(v)); 435bb898558SAl Viro } 436bb898558SAl Viro 437fae419f2SRobin Holt /* Top two bits indicate the requested address is in MMR space. */ 438fae419f2SRobin Holt static inline int 439fae419f2SRobin Holt uv_gpa_in_mmr_space(unsigned long gpa) 440fae419f2SRobin Holt { 441fae419f2SRobin Holt return (gpa >> 62) == 0x3UL; 442fae419f2SRobin Holt } 443fae419f2SRobin Holt 444729d69e6SRobin Holt /* UV global physical address --> socket phys RAM */ 445729d69e6SRobin Holt static inline unsigned long uv_gpa_to_soc_phys_ram(unsigned long gpa) 446729d69e6SRobin Holt { 4475a51467bSRuss Anderson unsigned long paddr; 448729d69e6SRobin Holt unsigned long remap_base = uv_hub_info->lowmem_remap_base; 449729d69e6SRobin Holt unsigned long remap_top = uv_hub_info->lowmem_remap_top; 450729d69e6SRobin Holt 4516a469e46SJack Steiner gpa = ((gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift) | 4526a469e46SJack Steiner ((gpa >> uv_hub_info->n_lshift) << uv_hub_info->m_val); 4535a51467bSRuss Anderson paddr = gpa & uv_hub_info->gpa_mask; 454729d69e6SRobin Holt if (paddr >= remap_base && paddr < remap_base + remap_top) 455729d69e6SRobin Holt paddr -= remap_base; 456729d69e6SRobin Holt return paddr; 457729d69e6SRobin Holt } 458729d69e6SRobin Holt 459729d69e6SRobin Holt 460906f3b20SMike Travis /* gpa -> gnode */ 4611d21e6e3SRobin Holt static inline unsigned long uv_gpa_to_gnode(unsigned long gpa) 4621d21e6e3SRobin Holt { 4636a469e46SJack Steiner return gpa >> uv_hub_info->n_lshift; 4641d21e6e3SRobin Holt } 4651d21e6e3SRobin Holt 4661d21e6e3SRobin Holt /* gpa -> pnode */ 4671d21e6e3SRobin Holt static inline int uv_gpa_to_pnode(unsigned long gpa) 4681d21e6e3SRobin Holt { 469906f3b20SMike Travis return uv_gpa_to_gnode(gpa) & uv_hub_info->pnode_mask; 4701d21e6e3SRobin Holt } 4711d21e6e3SRobin Holt 4726a469e46SJack Steiner /* gpa -> node offset */ 4736a469e46SJack Steiner static inline unsigned long uv_gpa_to_offset(unsigned long gpa) 4746a469e46SJack Steiner { 4756a469e46SJack Steiner return (gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift; 4766a469e46SJack Steiner } 4776a469e46SJack Steiner 478bb898558SAl Viro /* pnode, offset --> socket virtual */ 479bb898558SAl Viro static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset) 480bb898558SAl Viro { 481bb898558SAl Viro return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset); 482bb898558SAl Viro } 483bb898558SAl Viro 484906f3b20SMike Travis /* Extract a PNODE from an APICID (full apicid, not processor subset) */ 485bb898558SAl Viro static inline int uv_apicid_to_pnode(int apicid) 486bb898558SAl Viro { 487c8f730b1SRuss Anderson return (apicid >> uv_hub_info->apic_pnode_shift); 488bb898558SAl Viro } 489bb898558SAl Viro 490906f3b20SMike Travis /* Convert an apicid to the socket number on the blade */ 4912a919596SJack Steiner static inline int uv_apicid_to_socket(int apicid) 4922a919596SJack Steiner { 4932a919596SJack Steiner if (is_uv1_hub()) 4942a919596SJack Steiner return (apicid >> (uv_hub_info->apic_pnode_shift - 1)) & 1; 4952a919596SJack Steiner else 4962a919596SJack Steiner return 0; 4972a919596SJack Steiner } 4982a919596SJack Steiner 4992a919596SJack Steiner /* 500bb898558SAl Viro * Access global MMRs using the low memory MMR32 space. This region supports 501bb898558SAl Viro * faster MMR access but not all MMRs are accessible in this space. 502bb898558SAl Viro */ 50339d30770SMike Travis static inline unsigned long *uv_global_mmr32_address(int pnode, unsigned long offset) 504bb898558SAl Viro { 505bb898558SAl Viro return __va(UV_GLOBAL_MMR32_BASE | 506bb898558SAl Viro UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset); 507bb898558SAl Viro } 508bb898558SAl Viro 50939d30770SMike Travis static inline void uv_write_global_mmr32(int pnode, unsigned long offset, unsigned long val) 510bb898558SAl Viro { 5118dc579e8SJack Steiner writeq(val, uv_global_mmr32_address(pnode, offset)); 512bb898558SAl Viro } 513bb898558SAl Viro 51439d30770SMike Travis static inline unsigned long uv_read_global_mmr32(int pnode, unsigned long offset) 515bb898558SAl Viro { 5168dc579e8SJack Steiner return readq(uv_global_mmr32_address(pnode, offset)); 517bb898558SAl Viro } 518bb898558SAl Viro 519bb898558SAl Viro /* 520bb898558SAl Viro * Access Global MMR space using the MMR space located at the top of physical 521bb898558SAl Viro * memory. 522bb898558SAl Viro */ 523a289cc7cSRandy Dunlap static inline volatile void __iomem *uv_global_mmr64_address(int pnode, unsigned long offset) 524bb898558SAl Viro { 525bb898558SAl Viro return __va(UV_GLOBAL_MMR64_BASE | 526bb898558SAl Viro UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset); 527bb898558SAl Viro } 528bb898558SAl Viro 52939d30770SMike Travis static inline void uv_write_global_mmr64(int pnode, unsigned long offset, unsigned long val) 530bb898558SAl Viro { 5318dc579e8SJack Steiner writeq(val, uv_global_mmr64_address(pnode, offset)); 532bb898558SAl Viro } 533bb898558SAl Viro 53439d30770SMike Travis static inline unsigned long uv_read_global_mmr64(int pnode, unsigned long offset) 535bb898558SAl Viro { 5368dc579e8SJack Steiner return readq(uv_global_mmr64_address(pnode, offset)); 537bb898558SAl Viro } 538bb898558SAl Viro 539bb898558SAl Viro /* 54056abcf24SJack Steiner * Global MMR space addresses when referenced by the GRU. (GRU does 54156abcf24SJack Steiner * NOT use socket addressing). 54256abcf24SJack Steiner */ 54356abcf24SJack Steiner static inline unsigned long uv_global_gru_mmr_address(int pnode, unsigned long offset) 54456abcf24SJack Steiner { 545e1e0138dSJack Steiner return UV_GLOBAL_GRU_MMR_BASE | offset | 546e1e0138dSJack Steiner ((unsigned long)pnode << uv_hub_info->m_val); 54756abcf24SJack Steiner } 54856abcf24SJack Steiner 54939d30770SMike Travis static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val) 55039d30770SMike Travis { 55139d30770SMike Travis writeb(val, uv_global_mmr64_address(pnode, offset)); 55239d30770SMike Travis } 55339d30770SMike Travis 55439d30770SMike Travis static inline unsigned char uv_read_global_mmr8(int pnode, unsigned long offset) 55539d30770SMike Travis { 55639d30770SMike Travis return readb(uv_global_mmr64_address(pnode, offset)); 55739d30770SMike Travis } 55839d30770SMike Travis 55956abcf24SJack Steiner /* 560bb898558SAl Viro * Access hub local MMRs. Faster than using global space but only local MMRs 561bb898558SAl Viro * are accessible. 562bb898558SAl Viro */ 563bb898558SAl Viro static inline unsigned long *uv_local_mmr_address(unsigned long offset) 564bb898558SAl Viro { 565bb898558SAl Viro return __va(UV_LOCAL_MMR_BASE | offset); 566bb898558SAl Viro } 567bb898558SAl Viro 568bb898558SAl Viro static inline unsigned long uv_read_local_mmr(unsigned long offset) 569bb898558SAl Viro { 5708dc579e8SJack Steiner return readq(uv_local_mmr_address(offset)); 571bb898558SAl Viro } 572bb898558SAl Viro 573bb898558SAl Viro static inline void uv_write_local_mmr(unsigned long offset, unsigned long val) 574bb898558SAl Viro { 5758dc579e8SJack Steiner writeq(val, uv_local_mmr_address(offset)); 576bb898558SAl Viro } 577bb898558SAl Viro 5787f1baa06SMike Travis static inline unsigned char uv_read_local_mmr8(unsigned long offset) 5797f1baa06SMike Travis { 5808dc579e8SJack Steiner return readb(uv_local_mmr_address(offset)); 5817f1baa06SMike Travis } 5827f1baa06SMike Travis 5837f1baa06SMike Travis static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val) 5847f1baa06SMike Travis { 5858dc579e8SJack Steiner writeb(val, uv_local_mmr_address(offset)); 5867f1baa06SMike Travis } 5877f1baa06SMike Travis 588bb898558SAl Viro /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */ 589bb898558SAl Viro static inline int uv_blade_processor_id(void) 590bb898558SAl Viro { 5915627a825SMike Travis return uv_cpu_info->blade_cpu_id; 592bb898558SAl Viro } 593bb898558SAl Viro 5945627a825SMike Travis /* Blade-local cpu number of cpu N. Numbered 0 .. <# cpus on the blade> */ 5955627a825SMike Travis static inline int uv_cpu_blade_processor_id(int cpu) 5965627a825SMike Travis { 5975627a825SMike Travis return uv_cpu_info_per(cpu)->blade_cpu_id; 5985627a825SMike Travis } 5995627a825SMike Travis #define _uv_cpu_blade_processor_id 1 /* indicate function available */ 6005627a825SMike Travis 601906f3b20SMike Travis /* Blade number to Node number (UV1..UV4 is 1:1) */ 602906f3b20SMike Travis static inline int uv_blade_to_node(int blade) 603906f3b20SMike Travis { 604906f3b20SMike Travis return blade; 605906f3b20SMike Travis } 606906f3b20SMike Travis 607bb898558SAl Viro /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */ 608bb898558SAl Viro static inline int uv_numa_blade_id(void) 609bb898558SAl Viro { 610bb898558SAl Viro return uv_hub_info->numa_blade_id; 611bb898558SAl Viro } 612bb898558SAl Viro 613906f3b20SMike Travis /* 614906f3b20SMike Travis * Convert linux node number to the UV blade number. 615906f3b20SMike Travis * .. Currently for UV1 thru UV4 the node and the blade are identical. 616906f3b20SMike Travis * .. If this changes then you MUST check references to this function! 617906f3b20SMike Travis */ 618906f3b20SMike Travis static inline int uv_node_to_blade_id(int nid) 619906f3b20SMike Travis { 620906f3b20SMike Travis return nid; 621906f3b20SMike Travis } 622906f3b20SMike Travis 623bb898558SAl Viro /* Convert a cpu number to the the UV blade number */ 624bb898558SAl Viro static inline int uv_cpu_to_blade_id(int cpu) 625bb898558SAl Viro { 626906f3b20SMike Travis return uv_node_to_blade_id(cpu_to_node(cpu)); 627bb898558SAl Viro } 628bb898558SAl Viro 629bb898558SAl Viro /* Convert a blade id to the PNODE of the blade */ 630bb898558SAl Viro static inline int uv_blade_to_pnode(int bid) 631bb898558SAl Viro { 632906f3b20SMike Travis return uv_hub_info_list(uv_blade_to_node(bid))->pnode; 633bb898558SAl Viro } 634bb898558SAl Viro 6356c7184b7SJack Steiner /* Nid of memory node on blade. -1 if no blade-local memory */ 6366c7184b7SJack Steiner static inline int uv_blade_to_memory_nid(int bid) 6376c7184b7SJack Steiner { 638906f3b20SMike Travis return uv_hub_info_list(uv_blade_to_node(bid))->memory_nid; 6396c7184b7SJack Steiner } 6406c7184b7SJack Steiner 641bb898558SAl Viro /* Determine the number of possible cpus on a blade */ 642bb898558SAl Viro static inline int uv_blade_nr_possible_cpus(int bid) 643bb898558SAl Viro { 644906f3b20SMike Travis return uv_hub_info_list(uv_blade_to_node(bid))->nr_possible_cpus; 645bb898558SAl Viro } 646bb898558SAl Viro 647bb898558SAl Viro /* Determine the number of online cpus on a blade */ 648bb898558SAl Viro static inline int uv_blade_nr_online_cpus(int bid) 649bb898558SAl Viro { 650906f3b20SMike Travis return uv_hub_info_list(uv_blade_to_node(bid))->nr_online_cpus; 651bb898558SAl Viro } 652bb898558SAl Viro 653bb898558SAl Viro /* Convert a cpu id to the PNODE of the blade containing the cpu */ 654bb898558SAl Viro static inline int uv_cpu_to_pnode(int cpu) 655bb898558SAl Viro { 656906f3b20SMike Travis return uv_cpu_hub_info(cpu)->pnode; 657bb898558SAl Viro } 658bb898558SAl Viro 659bb898558SAl Viro /* Convert a linux node number to the PNODE of the blade */ 660bb898558SAl Viro static inline int uv_node_to_pnode(int nid) 661bb898558SAl Viro { 662906f3b20SMike Travis return uv_hub_info_list(nid)->pnode; 663bb898558SAl Viro } 664bb898558SAl Viro 665bb898558SAl Viro /* Maximum possible number of blades */ 666906f3b20SMike Travis extern short uv_possible_blades; 667bb898558SAl Viro static inline int uv_num_possible_blades(void) 668bb898558SAl Viro { 669bb898558SAl Viro return uv_possible_blades; 670bb898558SAl Viro } 671bb898558SAl Viro 6720d12ef0cSMike Travis /* Per Hub NMI support */ 6730d12ef0cSMike Travis extern void uv_nmi_setup(void); 6740d12ef0cSMike Travis 6750d12ef0cSMike Travis /* BMC sets a bit this MMR non-zero before sending an NMI */ 6760d12ef0cSMike Travis #define UVH_NMI_MMR UVH_SCRATCH5 6770d12ef0cSMike Travis #define UVH_NMI_MMR_CLEAR UVH_SCRATCH5_ALIAS 6780d12ef0cSMike Travis #define UVH_NMI_MMR_SHIFT 63 6790d12ef0cSMike Travis #define UVH_NMI_MMR_TYPE "SCRATCH5" 6800d12ef0cSMike Travis 6810d12ef0cSMike Travis /* Newer SMM NMI handler, not present in all systems */ 6820d12ef0cSMike Travis #define UVH_NMI_MMRX UVH_EVENT_OCCURRED0 6830d12ef0cSMike Travis #define UVH_NMI_MMRX_CLEAR UVH_EVENT_OCCURRED0_ALIAS 684c443c03dSMike Travis #define UVH_NMI_MMRX_SHIFT UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT 6850d12ef0cSMike Travis #define UVH_NMI_MMRX_TYPE "EXTIO_INT0" 6860d12ef0cSMike Travis 6870d12ef0cSMike Travis /* Non-zero indicates newer SMM NMI handler present */ 6880d12ef0cSMike Travis #define UVH_NMI_MMRX_SUPPORTED UVH_EXTIO_INT0_BROADCAST 6890d12ef0cSMike Travis 6900d12ef0cSMike Travis /* Indicates to BIOS that we want to use the newer SMM NMI handler */ 6910d12ef0cSMike Travis #define UVH_NMI_MMRX_REQ UVH_SCRATCH5_ALIAS_2 6920d12ef0cSMike Travis #define UVH_NMI_MMRX_REQ_SHIFT 62 6930d12ef0cSMike Travis 6940d12ef0cSMike Travis struct uv_hub_nmi_s { 6950d12ef0cSMike Travis raw_spinlock_t nmi_lock; 6960d12ef0cSMike Travis atomic_t in_nmi; /* flag this node in UV NMI IRQ */ 6970d12ef0cSMike Travis atomic_t cpu_owner; /* last locker of this struct */ 6980d12ef0cSMike Travis atomic_t read_mmr_count; /* count of MMR reads */ 6990d12ef0cSMike Travis atomic_t nmi_count; /* count of true UV NMIs */ 7000d12ef0cSMike Travis unsigned long nmi_value; /* last value read from NMI MMR */ 7010d12ef0cSMike Travis }; 7020d12ef0cSMike Travis 7030d12ef0cSMike Travis struct uv_cpu_nmi_s { 7040d12ef0cSMike Travis struct uv_hub_nmi_s *hub; 705e1632170SChristoph Lameter int state; 706e1632170SChristoph Lameter int pinging; 7070d12ef0cSMike Travis int queries; 7080d12ef0cSMike Travis int pings; 7090d12ef0cSMike Travis }; 7100d12ef0cSMike Travis 711e1632170SChristoph Lameter DECLARE_PER_CPU(struct uv_cpu_nmi_s, uv_cpu_nmi); 712e1632170SChristoph Lameter 7137c52198bSGeorge Beshers #define uv_hub_nmi this_cpu_read(uv_cpu_nmi.hub) 714e1632170SChristoph Lameter #define uv_cpu_nmi_per(cpu) (per_cpu(uv_cpu_nmi, cpu)) 7150d12ef0cSMike Travis #define uv_hub_nmi_per(cpu) (uv_cpu_nmi_per(cpu).hub) 7160d12ef0cSMike Travis 7170d12ef0cSMike Travis /* uv_cpu_nmi_states */ 7180d12ef0cSMike Travis #define UV_NMI_STATE_OUT 0 7190d12ef0cSMike Travis #define UV_NMI_STATE_IN 1 7200d12ef0cSMike Travis #define UV_NMI_STATE_DUMP 2 7210d12ef0cSMike Travis #define UV_NMI_STATE_DUMP_DONE 3 7220d12ef0cSMike Travis 7237f1baa06SMike Travis /* Update SCIR state */ 7247f1baa06SMike Travis static inline void uv_set_scir_bits(unsigned char value) 7257f1baa06SMike Travis { 726d38bb135SMike Travis if (uv_scir_info->state != value) { 727d38bb135SMike Travis uv_scir_info->state = value; 728d38bb135SMike Travis uv_write_local_mmr8(uv_scir_info->offset, value); 7297f1baa06SMike Travis } 7307f1baa06SMike Travis } 73166666e50SJack Steiner 73239d30770SMike Travis static inline unsigned long uv_scir_offset(int apicid) 73339d30770SMike Travis { 73439d30770SMike Travis return SCIR_LOCAL_MMR_BASE | (apicid & 0x3f); 73539d30770SMike Travis } 73639d30770SMike Travis 7377f1baa06SMike Travis static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value) 7387f1baa06SMike Travis { 739d38bb135SMike Travis if (uv_cpu_scir_info(cpu)->state != value) { 74039d30770SMike Travis uv_write_global_mmr8(uv_cpu_to_pnode(cpu), 741d38bb135SMike Travis uv_cpu_scir_info(cpu)->offset, value); 742d38bb135SMike Travis uv_cpu_scir_info(cpu)->state = value; 7437f1baa06SMike Travis } 7447f1baa06SMike Travis } 745bb898558SAl Viro 7468191c9f6SDimitri Sivanich extern unsigned int uv_apicid_hibits; 74756abcf24SJack Steiner static unsigned long uv_hub_ipi_value(int apicid, int vector, int mode) 74856abcf24SJack Steiner { 7498191c9f6SDimitri Sivanich apicid |= uv_apicid_hibits; 75056abcf24SJack Steiner return (1UL << UVH_IPI_INT_SEND_SHFT) | 75156abcf24SJack Steiner ((apicid) << UVH_IPI_INT_APIC_ID_SHFT) | 75256abcf24SJack Steiner (mode << UVH_IPI_INT_DELIVERY_MODE_SHFT) | 75356abcf24SJack Steiner (vector << UVH_IPI_INT_VECTOR_SHFT); 75456abcf24SJack Steiner } 75556abcf24SJack Steiner 75666666e50SJack Steiner static inline void uv_hub_send_ipi(int pnode, int apicid, int vector) 75766666e50SJack Steiner { 75866666e50SJack Steiner unsigned long val; 75902dd0a06SRobin Holt unsigned long dmode = dest_Fixed; 76002dd0a06SRobin Holt 76102dd0a06SRobin Holt if (vector == NMI_VECTOR) 76202dd0a06SRobin Holt dmode = dest_NMI; 76366666e50SJack Steiner 76456abcf24SJack Steiner val = uv_hub_ipi_value(apicid, vector, dmode); 76566666e50SJack Steiner uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 76666666e50SJack Steiner } 76766666e50SJack Steiner 7687a1110e8SJack Steiner /* 7697a1110e8SJack Steiner * Get the minimum revision number of the hub chips within the partition. 770eb1e3461SMike Travis * (See UVx_HUB_REVISION_BASE above for specific values.) 7717a1110e8SJack Steiner */ 7727a1110e8SJack Steiner static inline int uv_get_min_hub_revision_id(void) 7737a1110e8SJack Steiner { 7742a919596SJack Steiner return uv_hub_info->hub_revision; 7757a1110e8SJack Steiner } 7767a1110e8SJack Steiner 777bc5d9940SJack Steiner #endif /* CONFIG_X86_64 */ 7787f1baa06SMike Travis #endif /* _ASM_X86_UV_UV_HUB_H */ 779