11a59d1b8SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 205e4d316SH. Peter Anvin #ifndef _ASM_X86_UV_BIOS_H 305e4d316SH. Peter Anvin #define _ASM_X86_UV_BIOS_H 4bb898558SAl Viro 5bb898558SAl Viro /* 6bb898558SAl Viro * UV BIOS layer definitions. 7bb898558SAl Viro * 8b76365a1SRuss Anderson * Copyright (c) 2008-2009 Silicon Graphics, Inc. All Rights Reserved. 9b76365a1SRuss Anderson * Copyright (c) Russ Anderson <rja@sgi.com> 10bb898558SAl Viro */ 11bb898558SAl Viro 12bb898558SAl Viro #include <linux/rtc.h> 13bb898558SAl Viro 14bb898558SAl Viro /* 15bb898558SAl Viro * Values for the BIOS calls. It is passed as the first * argument in the 16bb898558SAl Viro * BIOS call. Passing any other value in the first argument will result 17bb898558SAl Viro * in a BIOS_STATUS_UNIMPLEMENTED return status. 18bb898558SAl Viro */ 19bb898558SAl Viro enum uv_bios_cmd { 20bb898558SAl Viro UV_BIOS_COMMON, 21bb898558SAl Viro UV_BIOS_GET_SN_INFO, 2264ccf2f9SRuss Anderson UV_BIOS_FREQ_BASE, 2364ccf2f9SRuss Anderson UV_BIOS_WATCHLIST_ALLOC, 24e8929c8aSRuss Anderson UV_BIOS_WATCHLIST_FREE, 2523c35700SRuss Anderson UV_BIOS_MEMPROTECT, 26841582eaSMike Travis UV_BIOS_GET_PARTITION_ADDR, 27841582eaSMike Travis UV_BIOS_SET_LEGACY_VGA_TARGET 28bb898558SAl Viro }; 29bb898558SAl Viro 30bb898558SAl Viro /* 31bb898558SAl Viro * Status values returned from a BIOS call. 32bb898558SAl Viro */ 33bb898558SAl Viro enum { 3423c35700SRuss Anderson BIOS_STATUS_MORE_PASSES = 1, 35bb898558SAl Viro BIOS_STATUS_SUCCESS = 0, 36bb898558SAl Viro BIOS_STATUS_UNIMPLEMENTED = -ENOSYS, 37bb898558SAl Viro BIOS_STATUS_EINVAL = -EINVAL, 38f331e766SHedi Berriche BIOS_STATUS_UNAVAIL = -EBUSY, 39f331e766SHedi Berriche BIOS_STATUS_ABORT = -EINTR, 40bb898558SAl Viro }; 41bb898558SAl Viro 42ef93bf80SMike Travis /* Address map parameters */ 43ef93bf80SMike Travis struct uv_gam_parameters { 44ef93bf80SMike Travis u64 mmr_base; 45ef93bf80SMike Travis u64 gru_base; 46ef93bf80SMike Travis u8 mmr_shift; /* Convert PNode to MMR space offset */ 47ef93bf80SMike Travis u8 gru_shift; /* Convert PNode to GRU space offset */ 48ef93bf80SMike Travis u8 gpa_shift; /* Size of offset field in GRU phys addr */ 49ef93bf80SMike Travis u8 unused1; 50ef93bf80SMike Travis }; 51ef93bf80SMike Travis 52ef93bf80SMike Travis /* UV_TABLE_GAM_RANGE_ENTRY values */ 53ef93bf80SMike Travis #define UV_GAM_RANGE_TYPE_UNUSED 0 /* End of table */ 54ef93bf80SMike Travis #define UV_GAM_RANGE_TYPE_RAM 1 /* Normal RAM */ 55ef93bf80SMike Travis #define UV_GAM_RANGE_TYPE_NVRAM 2 /* Non-volatile memory */ 56ef93bf80SMike Travis #define UV_GAM_RANGE_TYPE_NV_WINDOW 3 /* NVMDIMM block window */ 57ef93bf80SMike Travis #define UV_GAM_RANGE_TYPE_NV_MAILBOX 4 /* NVMDIMM mailbox */ 58ef93bf80SMike Travis #define UV_GAM_RANGE_TYPE_HOLE 5 /* Unused address range */ 59ef93bf80SMike Travis #define UV_GAM_RANGE_TYPE_MAX 6 60ef93bf80SMike Travis 61ef93bf80SMike Travis /* The structure stores PA bits 56:26, for 64MB granularity */ 62ef93bf80SMike Travis #define UV_GAM_RANGE_SHFT 26 /* 64MB */ 63ef93bf80SMike Travis 64ef93bf80SMike Travis struct uv_gam_range_entry { 65ef93bf80SMike Travis char type; /* Entry type: GAM_RANGE_TYPE_UNUSED, etc. */ 66ef93bf80SMike Travis char unused1; 67ef93bf80SMike Travis u16 nasid; /* HNasid */ 68ef93bf80SMike Travis u16 sockid; /* Socket ID, high bits of APIC ID */ 69ef93bf80SMike Travis u16 pnode; /* Index to MMR and GRU spaces */ 7022ac2bcaSMike Travis u32 unused2; 71ef93bf80SMike Travis u32 limit; /* PA bits 56:26 (UV_GAM_RANGE_SHFT) */ 72ef93bf80SMike Travis }; 73ef93bf80SMike Travis 74ef93bf80SMike Travis #define UV_SYSTAB_SIG "UVST" 755d662537Ssteve.wahl@hpe.com #define UV_SYSTAB_VERSION_1 1 /* UV2/3 BIOS version */ 76ef93bf80SMike Travis #define UV_SYSTAB_VERSION_UV4 0x400 /* UV4 BIOS base version */ 77ef93bf80SMike Travis #define UV_SYSTAB_VERSION_UV4_1 0x401 /* + gpa_shift */ 78ef93bf80SMike Travis #define UV_SYSTAB_VERSION_UV4_2 0x402 /* + TYPE_NVRAM/WINDOW/MBOX */ 7922ac2bcaSMike Travis #define UV_SYSTAB_VERSION_UV4_3 0x403 /* - GAM Range PXM Value */ 8022ac2bcaSMike Travis #define UV_SYSTAB_VERSION_UV4_LATEST UV_SYSTAB_VERSION_UV4_3 81ef93bf80SMike Travis 82ef93bf80SMike Travis #define UV_SYSTAB_TYPE_UNUSED 0 /* End of table (offset == 0) */ 83ef93bf80SMike Travis #define UV_SYSTAB_TYPE_GAM_PARAMS 1 /* GAM PARAM conversions */ 84ef93bf80SMike Travis #define UV_SYSTAB_TYPE_GAM_RNG_TBL 2 /* GAM entry table */ 85ef93bf80SMike Travis #define UV_SYSTAB_TYPE_MAX 3 86ef93bf80SMike Travis 87bb898558SAl Viro /* 88bb898558SAl Viro * The UV system table describes specific firmware 89bb898558SAl Viro * capabilities available to the Linux kernel at runtime. 90bb898558SAl Viro */ 91bb898558SAl Viro struct uv_systab { 92ef93bf80SMike Travis char signature[4]; /* must be UV_SYSTAB_SIG */ 93bb898558SAl Viro u32 revision; /* distinguish different firmware revs */ 94bb898558SAl Viro u64 function; /* BIOS runtime callback function ptr */ 95ef93bf80SMike Travis u32 size; /* systab size (starting with _VERSION_UV4) */ 96ef93bf80SMike Travis struct { 97ef93bf80SMike Travis u32 type:8; /* type of entry */ 98ef93bf80SMike Travis u32 offset:24; /* byte offset from struct start to entry */ 99ef93bf80SMike Travis } entry[1]; /* additional entries follow */ 100bb898558SAl Viro }; 101ef93bf80SMike Travis extern struct uv_systab *uv_systab; 102ef93bf80SMike Travis /* (... end of definitions from UV BIOS ...) */ 103bb898558SAl Viro 104bb898558SAl Viro enum { 105bb898558SAl Viro BIOS_FREQ_BASE_PLATFORM = 0, 106bb898558SAl Viro BIOS_FREQ_BASE_INTERVAL_TIMER = 1, 107bb898558SAl Viro BIOS_FREQ_BASE_REALTIME_CLOCK = 2 108bb898558SAl Viro }; 109bb898558SAl Viro 110bb898558SAl Viro union partition_info_u { 111bb898558SAl Viro u64 val; 112bb898558SAl Viro struct { 113bb898558SAl Viro u64 hub_version : 8, 114bb898558SAl Viro partition_id : 16, 115bb898558SAl Viro coherence_id : 16, 116bb898558SAl Viro region_size : 24; 117bb898558SAl Viro }; 118bb898558SAl Viro }; 119bb898558SAl Viro 120e8929c8aSRuss Anderson enum uv_memprotect { 121e8929c8aSRuss Anderson UV_MEMPROT_RESTRICT_ACCESS, 122e8929c8aSRuss Anderson UV_MEMPROT_ALLOW_AMO, 123e8929c8aSRuss Anderson UV_MEMPROT_ALLOW_RW 124e8929c8aSRuss Anderson }; 125e8929c8aSRuss Anderson 126b76365a1SRuss Anderson extern s64 uv_bios_get_sn_info(int, int *, long *, long *, long *, long *); 127bb898558SAl Viro extern s64 uv_bios_freq_base(u64, u64 *); 128c2c9f115SRobin Holt extern int uv_bios_mq_watchlist_alloc(unsigned long, unsigned int, 12964ccf2f9SRuss Anderson unsigned long *); 13064ccf2f9SRuss Anderson extern int uv_bios_mq_watchlist_free(int, int); 131e8929c8aSRuss Anderson extern s64 uv_bios_change_memprotect(u64, u64, enum uv_memprotect); 13223c35700SRuss Anderson extern s64 uv_bios_reserved_page_pa(u64, u64 *, u64 *, u64 *); 133841582eaSMike Travis extern int uv_bios_set_legacy_vga_target(bool decode, int domain, int bus); 134bb898558SAl Viro 1359743cb68SMike Travis extern int uv_bios_init(void); 136bb898558SAl Viro 13764ccf2f9SRuss Anderson extern unsigned long sn_rtc_cycles_per_second; 138bb898558SAl Viro extern int uv_type; 139bb898558SAl Viro extern long sn_partition_id; 1405292ae11SIngo Molnar extern long sn_coherency_id; 1415292ae11SIngo Molnar extern long sn_region_size; 142b76365a1SRuss Anderson extern long system_serial_number; 143bb898558SAl Viro 144bb898558SAl Viro extern struct kobject *sgi_uv_kobj; /* /sys/firmware/sgi_uv */ 145bb898558SAl Viro 146f331e766SHedi Berriche /* 147f331e766SHedi Berriche * EFI runtime lock; cf. firmware/efi/runtime-wrappers.c for details 148f331e766SHedi Berriche */ 149f331e766SHedi Berriche extern struct semaphore __efi_uv_runtime_lock; 150f331e766SHedi Berriche 15105e4d316SH. Peter Anvin #endif /* _ASM_X86_UV_BIOS_H */ 152