xref: /openbmc/linux/arch/x86/include/asm/tlbflush.h (revision 1b39eacd)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_TLBFLUSH_H
3 #define _ASM_X86_TLBFLUSH_H
4 
5 #include <linux/mm.h>
6 #include <linux/sched.h>
7 
8 #include <asm/processor.h>
9 #include <asm/cpufeature.h>
10 #include <asm/special_insns.h>
11 #include <asm/smp.h>
12 #include <asm/invpcid.h>
13 #include <asm/pti.h>
14 #include <asm/processor-flags.h>
15 
16 /*
17  * The x86 feature is called PCID (Process Context IDentifier). It is similar
18  * to what is traditionally called ASID on the RISC processors.
19  *
20  * We don't use the traditional ASID implementation, where each process/mm gets
21  * its own ASID and flush/restart when we run out of ASID space.
22  *
23  * Instead we have a small per-cpu array of ASIDs and cache the last few mm's
24  * that came by on this CPU, allowing cheaper switch_mm between processes on
25  * this CPU.
26  *
27  * We end up with different spaces for different things. To avoid confusion we
28  * use different names for each of them:
29  *
30  * ASID  - [0, TLB_NR_DYN_ASIDS-1]
31  *         the canonical identifier for an mm
32  *
33  * kPCID - [1, TLB_NR_DYN_ASIDS]
34  *         the value we write into the PCID part of CR3; corresponds to the
35  *         ASID+1, because PCID 0 is special.
36  *
37  * uPCID - [2048 + 1, 2048 + TLB_NR_DYN_ASIDS]
38  *         for KPTI each mm has two address spaces and thus needs two
39  *         PCID values, but we can still do with a single ASID denomination
40  *         for each mm. Corresponds to kPCID + 2048.
41  *
42  */
43 
44 /* There are 12 bits of space for ASIDS in CR3 */
45 #define CR3_HW_ASID_BITS		12
46 
47 /*
48  * When enabled, PAGE_TABLE_ISOLATION consumes a single bit for
49  * user/kernel switches
50  */
51 #ifdef CONFIG_PAGE_TABLE_ISOLATION
52 # define PTI_CONSUMED_PCID_BITS	1
53 #else
54 # define PTI_CONSUMED_PCID_BITS	0
55 #endif
56 
57 #define CR3_AVAIL_PCID_BITS (X86_CR3_PCID_BITS - PTI_CONSUMED_PCID_BITS)
58 
59 /*
60  * ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid.  -1 below to account
61  * for them being zero-based.  Another -1 is because PCID 0 is reserved for
62  * use by non-PCID-aware users.
63  */
64 #define MAX_ASID_AVAILABLE ((1 << CR3_AVAIL_PCID_BITS) - 2)
65 
66 /*
67  * 6 because 6 should be plenty and struct tlb_state will fit in two cache
68  * lines.
69  */
70 #define TLB_NR_DYN_ASIDS	6
71 
72 /*
73  * Given @asid, compute kPCID
74  */
75 static inline u16 kern_pcid(u16 asid)
76 {
77 	VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
78 
79 #ifdef CONFIG_PAGE_TABLE_ISOLATION
80 	/*
81 	 * Make sure that the dynamic ASID space does not confict with the
82 	 * bit we are using to switch between user and kernel ASIDs.
83 	 */
84 	BUILD_BUG_ON(TLB_NR_DYN_ASIDS >= (1 << X86_CR3_PTI_SWITCH_BIT));
85 
86 	/*
87 	 * The ASID being passed in here should have respected the
88 	 * MAX_ASID_AVAILABLE and thus never have the switch bit set.
89 	 */
90 	VM_WARN_ON_ONCE(asid & (1 << X86_CR3_PTI_SWITCH_BIT));
91 #endif
92 	/*
93 	 * The dynamically-assigned ASIDs that get passed in are small
94 	 * (<TLB_NR_DYN_ASIDS).  They never have the high switch bit set,
95 	 * so do not bother to clear it.
96 	 *
97 	 * If PCID is on, ASID-aware code paths put the ASID+1 into the
98 	 * PCID bits.  This serves two purposes.  It prevents a nasty
99 	 * situation in which PCID-unaware code saves CR3, loads some other
100 	 * value (with PCID == 0), and then restores CR3, thus corrupting
101 	 * the TLB for ASID 0 if the saved ASID was nonzero.  It also means
102 	 * that any bugs involving loading a PCID-enabled CR3 with
103 	 * CR4.PCIDE off will trigger deterministically.
104 	 */
105 	return asid + 1;
106 }
107 
108 /*
109  * Given @asid, compute uPCID
110  */
111 static inline u16 user_pcid(u16 asid)
112 {
113 	u16 ret = kern_pcid(asid);
114 #ifdef CONFIG_PAGE_TABLE_ISOLATION
115 	ret |= 1 << X86_CR3_PTI_SWITCH_BIT;
116 #endif
117 	return ret;
118 }
119 
120 struct pgd_t;
121 static inline unsigned long build_cr3(pgd_t *pgd, u16 asid)
122 {
123 	if (static_cpu_has(X86_FEATURE_PCID)) {
124 		return __sme_pa(pgd) | kern_pcid(asid);
125 	} else {
126 		VM_WARN_ON_ONCE(asid != 0);
127 		return __sme_pa(pgd);
128 	}
129 }
130 
131 static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid)
132 {
133 	VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
134 	VM_WARN_ON_ONCE(!this_cpu_has(X86_FEATURE_PCID));
135 	return __sme_pa(pgd) | kern_pcid(asid) | CR3_NOFLUSH;
136 }
137 
138 #ifdef CONFIG_PARAVIRT
139 #include <asm/paravirt.h>
140 #else
141 #define __flush_tlb() __native_flush_tlb()
142 #define __flush_tlb_global() __native_flush_tlb_global()
143 #define __flush_tlb_single(addr) __native_flush_tlb_single(addr)
144 #endif
145 
146 static inline bool tlb_defer_switch_to_init_mm(void)
147 {
148 	/*
149 	 * If we have PCID, then switching to init_mm is reasonably
150 	 * fast.  If we don't have PCID, then switching to init_mm is
151 	 * quite slow, so we try to defer it in the hopes that we can
152 	 * avoid it entirely.  The latter approach runs the risk of
153 	 * receiving otherwise unnecessary IPIs.
154 	 *
155 	 * This choice is just a heuristic.  The tlb code can handle this
156 	 * function returning true or false regardless of whether we have
157 	 * PCID.
158 	 */
159 	return !static_cpu_has(X86_FEATURE_PCID);
160 }
161 
162 struct tlb_context {
163 	u64 ctx_id;
164 	u64 tlb_gen;
165 };
166 
167 struct tlb_state {
168 	/*
169 	 * cpu_tlbstate.loaded_mm should match CR3 whenever interrupts
170 	 * are on.  This means that it may not match current->active_mm,
171 	 * which will contain the previous user mm when we're in lazy TLB
172 	 * mode even if we've already switched back to swapper_pg_dir.
173 	 */
174 	struct mm_struct *loaded_mm;
175 	u16 loaded_mm_asid;
176 	u16 next_asid;
177 
178 	/*
179 	 * We can be in one of several states:
180 	 *
181 	 *  - Actively using an mm.  Our CPU's bit will be set in
182 	 *    mm_cpumask(loaded_mm) and is_lazy == false;
183 	 *
184 	 *  - Not using a real mm.  loaded_mm == &init_mm.  Our CPU's bit
185 	 *    will not be set in mm_cpumask(&init_mm) and is_lazy == false.
186 	 *
187 	 *  - Lazily using a real mm.  loaded_mm != &init_mm, our bit
188 	 *    is set in mm_cpumask(loaded_mm), but is_lazy == true.
189 	 *    We're heuristically guessing that the CR3 load we
190 	 *    skipped more than makes up for the overhead added by
191 	 *    lazy mode.
192 	 */
193 	bool is_lazy;
194 
195 	/*
196 	 * If set we changed the page tables in such a way that we
197 	 * needed an invalidation of all contexts (aka. PCIDs / ASIDs).
198 	 * This tells us to go invalidate all the non-loaded ctxs[]
199 	 * on the next context switch.
200 	 *
201 	 * The current ctx was kept up-to-date as it ran and does not
202 	 * need to be invalidated.
203 	 */
204 	bool invalidate_other;
205 
206 	/*
207 	 * Mask that contains TLB_NR_DYN_ASIDS+1 bits to indicate
208 	 * the corresponding user PCID needs a flush next time we
209 	 * switch to it; see SWITCH_TO_USER_CR3.
210 	 */
211 	unsigned short user_pcid_flush_mask;
212 
213 	/*
214 	 * Access to this CR4 shadow and to H/W CR4 is protected by
215 	 * disabling interrupts when modifying either one.
216 	 */
217 	unsigned long cr4;
218 
219 	/*
220 	 * This is a list of all contexts that might exist in the TLB.
221 	 * There is one per ASID that we use, and the ASID (what the
222 	 * CPU calls PCID) is the index into ctxts.
223 	 *
224 	 * For each context, ctx_id indicates which mm the TLB's user
225 	 * entries came from.  As an invariant, the TLB will never
226 	 * contain entries that are out-of-date as when that mm reached
227 	 * the tlb_gen in the list.
228 	 *
229 	 * To be clear, this means that it's legal for the TLB code to
230 	 * flush the TLB without updating tlb_gen.  This can happen
231 	 * (for now, at least) due to paravirt remote flushes.
232 	 *
233 	 * NB: context 0 is a bit special, since it's also used by
234 	 * various bits of init code.  This is fine -- code that
235 	 * isn't aware of PCID will end up harmlessly flushing
236 	 * context 0.
237 	 */
238 	struct tlb_context ctxs[TLB_NR_DYN_ASIDS];
239 };
240 DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate);
241 
242 /* Initialize cr4 shadow for this CPU. */
243 static inline void cr4_init_shadow(void)
244 {
245 	this_cpu_write(cpu_tlbstate.cr4, __read_cr4());
246 }
247 
248 static inline void __cr4_set(unsigned long cr4)
249 {
250 	lockdep_assert_irqs_disabled();
251 	this_cpu_write(cpu_tlbstate.cr4, cr4);
252 	__write_cr4(cr4);
253 }
254 
255 /* Set in this cpu's CR4. */
256 static inline void cr4_set_bits(unsigned long mask)
257 {
258 	unsigned long cr4, flags;
259 
260 	local_irq_save(flags);
261 	cr4 = this_cpu_read(cpu_tlbstate.cr4);
262 	if ((cr4 | mask) != cr4)
263 		__cr4_set(cr4 | mask);
264 	local_irq_restore(flags);
265 }
266 
267 /* Clear in this cpu's CR4. */
268 static inline void cr4_clear_bits(unsigned long mask)
269 {
270 	unsigned long cr4, flags;
271 
272 	local_irq_save(flags);
273 	cr4 = this_cpu_read(cpu_tlbstate.cr4);
274 	if ((cr4 & ~mask) != cr4)
275 		__cr4_set(cr4 & ~mask);
276 	local_irq_restore(flags);
277 }
278 
279 static inline void cr4_toggle_bits_irqsoff(unsigned long mask)
280 {
281 	unsigned long cr4;
282 
283 	cr4 = this_cpu_read(cpu_tlbstate.cr4);
284 	__cr4_set(cr4 ^ mask);
285 }
286 
287 /* Read the CR4 shadow. */
288 static inline unsigned long cr4_read_shadow(void)
289 {
290 	return this_cpu_read(cpu_tlbstate.cr4);
291 }
292 
293 /*
294  * Mark all other ASIDs as invalid, preserves the current.
295  */
296 static inline void invalidate_other_asid(void)
297 {
298 	this_cpu_write(cpu_tlbstate.invalidate_other, true);
299 }
300 
301 /*
302  * Save some of cr4 feature set we're using (e.g.  Pentium 4MB
303  * enable and PPro Global page enable), so that any CPU's that boot
304  * up after us can get the correct flags.  This should only be used
305  * during boot on the boot cpu.
306  */
307 extern unsigned long mmu_cr4_features;
308 extern u32 *trampoline_cr4_features;
309 
310 static inline void cr4_set_bits_and_update_boot(unsigned long mask)
311 {
312 	mmu_cr4_features |= mask;
313 	if (trampoline_cr4_features)
314 		*trampoline_cr4_features = mmu_cr4_features;
315 	cr4_set_bits(mask);
316 }
317 
318 extern void initialize_tlbstate_and_flush(void);
319 
320 /*
321  * Given an ASID, flush the corresponding user ASID.  We can delay this
322  * until the next time we switch to it.
323  *
324  * See SWITCH_TO_USER_CR3.
325  */
326 static inline void invalidate_user_asid(u16 asid)
327 {
328 	/* There is no user ASID if address space separation is off */
329 	if (!IS_ENABLED(CONFIG_PAGE_TABLE_ISOLATION))
330 		return;
331 
332 	/*
333 	 * We only have a single ASID if PCID is off and the CR3
334 	 * write will have flushed it.
335 	 */
336 	if (!cpu_feature_enabled(X86_FEATURE_PCID))
337 		return;
338 
339 	if (!static_cpu_has(X86_FEATURE_PTI))
340 		return;
341 
342 	__set_bit(kern_pcid(asid),
343 		  (unsigned long *)this_cpu_ptr(&cpu_tlbstate.user_pcid_flush_mask));
344 }
345 
346 /*
347  * flush the entire current user mapping
348  */
349 static inline void __native_flush_tlb(void)
350 {
351 	/*
352 	 * Preemption or interrupts must be disabled to protect the access
353 	 * to the per CPU variable and to prevent being preempted between
354 	 * read_cr3() and write_cr3().
355 	 */
356 	WARN_ON_ONCE(preemptible());
357 
358 	invalidate_user_asid(this_cpu_read(cpu_tlbstate.loaded_mm_asid));
359 
360 	/* If current->mm == NULL then the read_cr3() "borrows" an mm */
361 	native_write_cr3(__native_read_cr3());
362 }
363 
364 /*
365  * flush everything
366  */
367 static inline void __native_flush_tlb_global(void)
368 {
369 	unsigned long cr4, flags;
370 
371 	if (static_cpu_has(X86_FEATURE_INVPCID)) {
372 		/*
373 		 * Using INVPCID is considerably faster than a pair of writes
374 		 * to CR4 sandwiched inside an IRQ flag save/restore.
375 		 *
376 		 * Note, this works with CR4.PCIDE=0 or 1.
377 		 */
378 		invpcid_flush_all();
379 		return;
380 	}
381 
382 	/*
383 	 * Read-modify-write to CR4 - protect it from preemption and
384 	 * from interrupts. (Use the raw variant because this code can
385 	 * be called from deep inside debugging code.)
386 	 */
387 	raw_local_irq_save(flags);
388 
389 	cr4 = this_cpu_read(cpu_tlbstate.cr4);
390 	/* toggle PGE */
391 	native_write_cr4(cr4 ^ X86_CR4_PGE);
392 	/* write old PGE again and flush TLBs */
393 	native_write_cr4(cr4);
394 
395 	raw_local_irq_restore(flags);
396 }
397 
398 /*
399  * flush one page in the user mapping
400  */
401 static inline void __native_flush_tlb_single(unsigned long addr)
402 {
403 	u32 loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);
404 
405 	asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
406 
407 	if (!static_cpu_has(X86_FEATURE_PTI))
408 		return;
409 
410 	/*
411 	 * Some platforms #GP if we call invpcid(type=1/2) before CR4.PCIDE=1.
412 	 * Just use invalidate_user_asid() in case we are called early.
413 	 */
414 	if (!this_cpu_has(X86_FEATURE_INVPCID_SINGLE))
415 		invalidate_user_asid(loaded_mm_asid);
416 	else
417 		invpcid_flush_one(user_pcid(loaded_mm_asid), addr);
418 }
419 
420 /*
421  * flush everything
422  */
423 static inline void __flush_tlb_all(void)
424 {
425 	if (boot_cpu_has(X86_FEATURE_PGE)) {
426 		__flush_tlb_global();
427 	} else {
428 		/*
429 		 * !PGE -> !PCID (setup_pcid()), thus every flush is total.
430 		 */
431 		__flush_tlb();
432 	}
433 }
434 
435 /*
436  * flush one page in the kernel mapping
437  */
438 static inline void __flush_tlb_one(unsigned long addr)
439 {
440 	count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
441 	__flush_tlb_single(addr);
442 
443 	if (!static_cpu_has(X86_FEATURE_PTI))
444 		return;
445 
446 	/*
447 	 * __flush_tlb_single() will have cleared the TLB entry for this ASID,
448 	 * but since kernel space is replicated across all, we must also
449 	 * invalidate all others.
450 	 */
451 	invalidate_other_asid();
452 }
453 
454 #define TLB_FLUSH_ALL	-1UL
455 
456 /*
457  * TLB flushing:
458  *
459  *  - flush_tlb_all() flushes all processes TLBs
460  *  - flush_tlb_mm(mm) flushes the specified mm context TLB's
461  *  - flush_tlb_page(vma, vmaddr) flushes one page
462  *  - flush_tlb_range(vma, start, end) flushes a range of pages
463  *  - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
464  *  - flush_tlb_others(cpumask, info) flushes TLBs on other cpus
465  *
466  * ..but the i386 has somewhat limited tlb flushing capabilities,
467  * and page-granular flushes are available only on i486 and up.
468  */
469 struct flush_tlb_info {
470 	/*
471 	 * We support several kinds of flushes.
472 	 *
473 	 * - Fully flush a single mm.  .mm will be set, .end will be
474 	 *   TLB_FLUSH_ALL, and .new_tlb_gen will be the tlb_gen to
475 	 *   which the IPI sender is trying to catch us up.
476 	 *
477 	 * - Partially flush a single mm.  .mm will be set, .start and
478 	 *   .end will indicate the range, and .new_tlb_gen will be set
479 	 *   such that the changes between generation .new_tlb_gen-1 and
480 	 *   .new_tlb_gen are entirely contained in the indicated range.
481 	 *
482 	 * - Fully flush all mms whose tlb_gens have been updated.  .mm
483 	 *   will be NULL, .end will be TLB_FLUSH_ALL, and .new_tlb_gen
484 	 *   will be zero.
485 	 */
486 	struct mm_struct	*mm;
487 	unsigned long		start;
488 	unsigned long		end;
489 	u64			new_tlb_gen;
490 };
491 
492 #define local_flush_tlb() __flush_tlb()
493 
494 #define flush_tlb_mm(mm)	flush_tlb_mm_range(mm, 0UL, TLB_FLUSH_ALL, 0UL)
495 
496 #define flush_tlb_range(vma, start, end)	\
497 		flush_tlb_mm_range(vma->vm_mm, start, end, vma->vm_flags)
498 
499 extern void flush_tlb_all(void);
500 extern void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
501 				unsigned long end, unsigned long vmflag);
502 extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
503 
504 static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long a)
505 {
506 	flush_tlb_mm_range(vma->vm_mm, a, a + PAGE_SIZE, VM_NONE);
507 }
508 
509 void native_flush_tlb_others(const struct cpumask *cpumask,
510 			     const struct flush_tlb_info *info);
511 
512 static inline u64 inc_mm_tlb_gen(struct mm_struct *mm)
513 {
514 	/*
515 	 * Bump the generation count.  This also serves as a full barrier
516 	 * that synchronizes with switch_mm(): callers are required to order
517 	 * their read of mm_cpumask after their writes to the paging
518 	 * structures.
519 	 */
520 	return atomic64_inc_return(&mm->context.tlb_gen);
521 }
522 
523 static inline void arch_tlbbatch_add_mm(struct arch_tlbflush_unmap_batch *batch,
524 					struct mm_struct *mm)
525 {
526 	inc_mm_tlb_gen(mm);
527 	cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm));
528 }
529 
530 extern void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch);
531 
532 #ifndef CONFIG_PARAVIRT
533 #define flush_tlb_others(mask, info)	\
534 	native_flush_tlb_others(mask, info)
535 #endif
536 
537 #endif /* _ASM_X86_TLBFLUSH_H */
538