1 #ifndef __SVM_H 2 #define __SVM_H 3 4 #include <uapi/asm/svm.h> 5 6 7 enum { 8 INTERCEPT_INTR, 9 INTERCEPT_NMI, 10 INTERCEPT_SMI, 11 INTERCEPT_INIT, 12 INTERCEPT_VINTR, 13 INTERCEPT_SELECTIVE_CR0, 14 INTERCEPT_STORE_IDTR, 15 INTERCEPT_STORE_GDTR, 16 INTERCEPT_STORE_LDTR, 17 INTERCEPT_STORE_TR, 18 INTERCEPT_LOAD_IDTR, 19 INTERCEPT_LOAD_GDTR, 20 INTERCEPT_LOAD_LDTR, 21 INTERCEPT_LOAD_TR, 22 INTERCEPT_RDTSC, 23 INTERCEPT_RDPMC, 24 INTERCEPT_PUSHF, 25 INTERCEPT_POPF, 26 INTERCEPT_CPUID, 27 INTERCEPT_RSM, 28 INTERCEPT_IRET, 29 INTERCEPT_INTn, 30 INTERCEPT_INVD, 31 INTERCEPT_PAUSE, 32 INTERCEPT_HLT, 33 INTERCEPT_INVLPG, 34 INTERCEPT_INVLPGA, 35 INTERCEPT_IOIO_PROT, 36 INTERCEPT_MSR_PROT, 37 INTERCEPT_TASK_SWITCH, 38 INTERCEPT_FERR_FREEZE, 39 INTERCEPT_SHUTDOWN, 40 INTERCEPT_VMRUN, 41 INTERCEPT_VMMCALL, 42 INTERCEPT_VMLOAD, 43 INTERCEPT_VMSAVE, 44 INTERCEPT_STGI, 45 INTERCEPT_CLGI, 46 INTERCEPT_SKINIT, 47 INTERCEPT_RDTSCP, 48 INTERCEPT_ICEBP, 49 INTERCEPT_WBINVD, 50 INTERCEPT_MONITOR, 51 INTERCEPT_MWAIT, 52 INTERCEPT_MWAIT_COND, 53 INTERCEPT_XSETBV, 54 }; 55 56 57 struct __attribute__ ((__packed__)) vmcb_control_area { 58 u32 intercept_cr; 59 u32 intercept_dr; 60 u32 intercept_exceptions; 61 u64 intercept; 62 u8 reserved_1[42]; 63 u16 pause_filter_count; 64 u64 iopm_base_pa; 65 u64 msrpm_base_pa; 66 u64 tsc_offset; 67 u32 asid; 68 u8 tlb_ctl; 69 u8 reserved_2[3]; 70 u32 int_ctl; 71 u32 int_vector; 72 u32 int_state; 73 u8 reserved_3[4]; 74 u32 exit_code; 75 u32 exit_code_hi; 76 u64 exit_info_1; 77 u64 exit_info_2; 78 u32 exit_int_info; 79 u32 exit_int_info_err; 80 u64 nested_ctl; 81 u64 avic_vapic_bar; 82 u8 reserved_4[8]; 83 u32 event_inj; 84 u32 event_inj_err; 85 u64 nested_cr3; 86 u64 virt_ext; 87 u32 clean; 88 u32 reserved_5; 89 u64 next_rip; 90 u8 insn_len; 91 u8 insn_bytes[15]; 92 u64 avic_backing_page; /* Offset 0xe0 */ 93 u8 reserved_6[8]; /* Offset 0xe8 */ 94 u64 avic_logical_id; /* Offset 0xf0 */ 95 u64 avic_physical_id; /* Offset 0xf8 */ 96 u8 reserved_7[768]; 97 }; 98 99 100 #define TLB_CONTROL_DO_NOTHING 0 101 #define TLB_CONTROL_FLUSH_ALL_ASID 1 102 #define TLB_CONTROL_FLUSH_ASID 3 103 #define TLB_CONTROL_FLUSH_ASID_LOCAL 7 104 105 #define V_TPR_MASK 0x0f 106 107 #define V_IRQ_SHIFT 8 108 #define V_IRQ_MASK (1 << V_IRQ_SHIFT) 109 110 #define V_GIF_SHIFT 9 111 #define V_GIF_MASK (1 << V_GIF_SHIFT) 112 113 #define V_INTR_PRIO_SHIFT 16 114 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT) 115 116 #define V_IGN_TPR_SHIFT 20 117 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT) 118 119 #define V_INTR_MASKING_SHIFT 24 120 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT) 121 122 #define V_GIF_ENABLE_SHIFT 25 123 #define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT) 124 125 #define AVIC_ENABLE_SHIFT 31 126 #define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT) 127 128 #define LBR_CTL_ENABLE_MASK BIT_ULL(0) 129 #define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1) 130 131 #define SVM_INTERRUPT_SHADOW_MASK 1 132 133 #define SVM_IOIO_STR_SHIFT 2 134 #define SVM_IOIO_REP_SHIFT 3 135 #define SVM_IOIO_SIZE_SHIFT 4 136 #define SVM_IOIO_ASIZE_SHIFT 7 137 138 #define SVM_IOIO_TYPE_MASK 1 139 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT) 140 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT) 141 #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT) 142 #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT) 143 144 #define SVM_VM_CR_VALID_MASK 0x001fULL 145 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL 146 #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL 147 148 struct __attribute__ ((__packed__)) vmcb_seg { 149 u16 selector; 150 u16 attrib; 151 u32 limit; 152 u64 base; 153 }; 154 155 struct __attribute__ ((__packed__)) vmcb_save_area { 156 struct vmcb_seg es; 157 struct vmcb_seg cs; 158 struct vmcb_seg ss; 159 struct vmcb_seg ds; 160 struct vmcb_seg fs; 161 struct vmcb_seg gs; 162 struct vmcb_seg gdtr; 163 struct vmcb_seg ldtr; 164 struct vmcb_seg idtr; 165 struct vmcb_seg tr; 166 u8 reserved_1[43]; 167 u8 cpl; 168 u8 reserved_2[4]; 169 u64 efer; 170 u8 reserved_3[112]; 171 u64 cr4; 172 u64 cr3; 173 u64 cr0; 174 u64 dr7; 175 u64 dr6; 176 u64 rflags; 177 u64 rip; 178 u8 reserved_4[88]; 179 u64 rsp; 180 u8 reserved_5[24]; 181 u64 rax; 182 u64 star; 183 u64 lstar; 184 u64 cstar; 185 u64 sfmask; 186 u64 kernel_gs_base; 187 u64 sysenter_cs; 188 u64 sysenter_esp; 189 u64 sysenter_eip; 190 u64 cr2; 191 u8 reserved_6[32]; 192 u64 g_pat; 193 u64 dbgctl; 194 u64 br_from; 195 u64 br_to; 196 u64 last_excp_from; 197 u64 last_excp_to; 198 }; 199 200 struct __attribute__ ((__packed__)) vmcb { 201 struct vmcb_control_area control; 202 struct vmcb_save_area save; 203 }; 204 205 #define SVM_CPUID_FUNC 0x8000000a 206 207 #define SVM_VM_CR_SVM_DISABLE 4 208 209 #define SVM_SELECTOR_S_SHIFT 4 210 #define SVM_SELECTOR_DPL_SHIFT 5 211 #define SVM_SELECTOR_P_SHIFT 7 212 #define SVM_SELECTOR_AVL_SHIFT 8 213 #define SVM_SELECTOR_L_SHIFT 9 214 #define SVM_SELECTOR_DB_SHIFT 10 215 #define SVM_SELECTOR_G_SHIFT 11 216 217 #define SVM_SELECTOR_TYPE_MASK (0xf) 218 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT) 219 #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT) 220 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT) 221 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT) 222 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT) 223 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT) 224 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT) 225 226 #define SVM_SELECTOR_WRITE_MASK (1 << 1) 227 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK 228 #define SVM_SELECTOR_CODE_MASK (1 << 3) 229 230 #define INTERCEPT_CR0_READ 0 231 #define INTERCEPT_CR3_READ 3 232 #define INTERCEPT_CR4_READ 4 233 #define INTERCEPT_CR8_READ 8 234 #define INTERCEPT_CR0_WRITE (16 + 0) 235 #define INTERCEPT_CR3_WRITE (16 + 3) 236 #define INTERCEPT_CR4_WRITE (16 + 4) 237 #define INTERCEPT_CR8_WRITE (16 + 8) 238 239 #define INTERCEPT_DR0_READ 0 240 #define INTERCEPT_DR1_READ 1 241 #define INTERCEPT_DR2_READ 2 242 #define INTERCEPT_DR3_READ 3 243 #define INTERCEPT_DR4_READ 4 244 #define INTERCEPT_DR5_READ 5 245 #define INTERCEPT_DR6_READ 6 246 #define INTERCEPT_DR7_READ 7 247 #define INTERCEPT_DR0_WRITE (16 + 0) 248 #define INTERCEPT_DR1_WRITE (16 + 1) 249 #define INTERCEPT_DR2_WRITE (16 + 2) 250 #define INTERCEPT_DR3_WRITE (16 + 3) 251 #define INTERCEPT_DR4_WRITE (16 + 4) 252 #define INTERCEPT_DR5_WRITE (16 + 5) 253 #define INTERCEPT_DR6_WRITE (16 + 6) 254 #define INTERCEPT_DR7_WRITE (16 + 7) 255 256 #define SVM_EVTINJ_VEC_MASK 0xff 257 258 #define SVM_EVTINJ_TYPE_SHIFT 8 259 #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT) 260 261 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT) 262 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT) 263 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT) 264 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT) 265 266 #define SVM_EVTINJ_VALID (1 << 31) 267 #define SVM_EVTINJ_VALID_ERR (1 << 11) 268 269 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK 270 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK 271 272 #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR 273 #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI 274 #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT 275 #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT 276 277 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID 278 #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR 279 280 #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36 281 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38 282 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44 283 284 #define SVM_EXITINFO_REG_MASK 0x0F 285 286 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP) 287 288 #define SVM_VMLOAD ".byte 0x0f, 0x01, 0xda" 289 #define SVM_VMRUN ".byte 0x0f, 0x01, 0xd8" 290 #define SVM_VMSAVE ".byte 0x0f, 0x01, 0xdb" 291 #define SVM_CLGI ".byte 0x0f, 0x01, 0xdd" 292 #define SVM_STGI ".byte 0x0f, 0x01, 0xdc" 293 #define SVM_INVLPGA ".byte 0x0f, 0x01, 0xdf" 294 295 #endif 296