xref: /openbmc/linux/arch/x86/include/asm/svm.h (revision c88773dc) 
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __SVM_H
3 #define __SVM_H
4 
5 #include <uapi/asm/svm.h>
6 
7 
8 enum {
9 	INTERCEPT_INTR,
10 	INTERCEPT_NMI,
11 	INTERCEPT_SMI,
12 	INTERCEPT_INIT,
13 	INTERCEPT_VINTR,
14 	INTERCEPT_SELECTIVE_CR0,
15 	INTERCEPT_STORE_IDTR,
16 	INTERCEPT_STORE_GDTR,
17 	INTERCEPT_STORE_LDTR,
18 	INTERCEPT_STORE_TR,
19 	INTERCEPT_LOAD_IDTR,
20 	INTERCEPT_LOAD_GDTR,
21 	INTERCEPT_LOAD_LDTR,
22 	INTERCEPT_LOAD_TR,
23 	INTERCEPT_RDTSC,
24 	INTERCEPT_RDPMC,
25 	INTERCEPT_PUSHF,
26 	INTERCEPT_POPF,
27 	INTERCEPT_CPUID,
28 	INTERCEPT_RSM,
29 	INTERCEPT_IRET,
30 	INTERCEPT_INTn,
31 	INTERCEPT_INVD,
32 	INTERCEPT_PAUSE,
33 	INTERCEPT_HLT,
34 	INTERCEPT_INVLPG,
35 	INTERCEPT_INVLPGA,
36 	INTERCEPT_IOIO_PROT,
37 	INTERCEPT_MSR_PROT,
38 	INTERCEPT_TASK_SWITCH,
39 	INTERCEPT_FERR_FREEZE,
40 	INTERCEPT_SHUTDOWN,
41 	INTERCEPT_VMRUN,
42 	INTERCEPT_VMMCALL,
43 	INTERCEPT_VMLOAD,
44 	INTERCEPT_VMSAVE,
45 	INTERCEPT_STGI,
46 	INTERCEPT_CLGI,
47 	INTERCEPT_SKINIT,
48 	INTERCEPT_RDTSCP,
49 	INTERCEPT_ICEBP,
50 	INTERCEPT_WBINVD,
51 	INTERCEPT_MONITOR,
52 	INTERCEPT_MWAIT,
53 	INTERCEPT_MWAIT_COND,
54 	INTERCEPT_XSETBV,
55 	INTERCEPT_RDPRU,
56 };
57 
58 
59 struct __attribute__ ((__packed__)) vmcb_control_area {
60 	u32 intercept_cr;
61 	u32 intercept_dr;
62 	u32 intercept_exceptions;
63 	u64 intercept;
64 	u8 reserved_1[40];
65 	u16 pause_filter_thresh;
66 	u16 pause_filter_count;
67 	u64 iopm_base_pa;
68 	u64 msrpm_base_pa;
69 	u64 tsc_offset;
70 	u32 asid;
71 	u8 tlb_ctl;
72 	u8 reserved_2[3];
73 	u32 int_ctl;
74 	u32 int_vector;
75 	u32 int_state;
76 	u8 reserved_3[4];
77 	u32 exit_code;
78 	u32 exit_code_hi;
79 	u64 exit_info_1;
80 	u64 exit_info_2;
81 	u32 exit_int_info;
82 	u32 exit_int_info_err;
83 	u64 nested_ctl;
84 	u64 avic_vapic_bar;
85 	u8 reserved_4[8];
86 	u32 event_inj;
87 	u32 event_inj_err;
88 	u64 nested_cr3;
89 	u64 virt_ext;
90 	u32 clean;
91 	u32 reserved_5;
92 	u64 next_rip;
93 	u8 insn_len;
94 	u8 insn_bytes[15];
95 	u64 avic_backing_page;	/* Offset 0xe0 */
96 	u8 reserved_6[8];	/* Offset 0xe8 */
97 	u64 avic_logical_id;	/* Offset 0xf0 */
98 	u64 avic_physical_id;	/* Offset 0xf8 */
99 };
100 
101 
102 #define TLB_CONTROL_DO_NOTHING 0
103 #define TLB_CONTROL_FLUSH_ALL_ASID 1
104 #define TLB_CONTROL_FLUSH_ASID 3
105 #define TLB_CONTROL_FLUSH_ASID_LOCAL 7
106 
107 #define V_TPR_MASK 0x0f
108 
109 #define V_IRQ_SHIFT 8
110 #define V_IRQ_MASK (1 << V_IRQ_SHIFT)
111 
112 #define V_GIF_SHIFT 9
113 #define V_GIF_MASK (1 << V_GIF_SHIFT)
114 
115 #define V_INTR_PRIO_SHIFT 16
116 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
117 
118 #define V_IGN_TPR_SHIFT 20
119 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
120 
121 #define V_INTR_MASKING_SHIFT 24
122 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
123 
124 #define V_GIF_ENABLE_SHIFT 25
125 #define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT)
126 
127 #define AVIC_ENABLE_SHIFT 31
128 #define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
129 
130 #define LBR_CTL_ENABLE_MASK BIT_ULL(0)
131 #define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
132 
133 #define SVM_INTERRUPT_SHADOW_MASK 1
134 
135 #define SVM_IOIO_STR_SHIFT 2
136 #define SVM_IOIO_REP_SHIFT 3
137 #define SVM_IOIO_SIZE_SHIFT 4
138 #define SVM_IOIO_ASIZE_SHIFT 7
139 
140 #define SVM_IOIO_TYPE_MASK 1
141 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
142 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
143 #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
144 #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
145 
146 #define SVM_VM_CR_VALID_MASK	0x001fULL
147 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
148 #define SVM_VM_CR_SVM_DIS_MASK  0x0010ULL
149 
150 #define SVM_NESTED_CTL_NP_ENABLE	BIT(0)
151 #define SVM_NESTED_CTL_SEV_ENABLE	BIT(1)
152 
153 struct vmcb_seg {
154 	u16 selector;
155 	u16 attrib;
156 	u32 limit;
157 	u64 base;
158 } __packed;
159 
160 struct vmcb_save_area {
161 	struct vmcb_seg es;
162 	struct vmcb_seg cs;
163 	struct vmcb_seg ss;
164 	struct vmcb_seg ds;
165 	struct vmcb_seg fs;
166 	struct vmcb_seg gs;
167 	struct vmcb_seg gdtr;
168 	struct vmcb_seg ldtr;
169 	struct vmcb_seg idtr;
170 	struct vmcb_seg tr;
171 	u8 reserved_1[43];
172 	u8 cpl;
173 	u8 reserved_2[4];
174 	u64 efer;
175 	u8 reserved_3[112];
176 	u64 cr4;
177 	u64 cr3;
178 	u64 cr0;
179 	u64 dr7;
180 	u64 dr6;
181 	u64 rflags;
182 	u64 rip;
183 	u8 reserved_4[88];
184 	u64 rsp;
185 	u8 reserved_5[24];
186 	u64 rax;
187 	u64 star;
188 	u64 lstar;
189 	u64 cstar;
190 	u64 sfmask;
191 	u64 kernel_gs_base;
192 	u64 sysenter_cs;
193 	u64 sysenter_esp;
194 	u64 sysenter_eip;
195 	u64 cr2;
196 	u8 reserved_6[32];
197 	u64 g_pat;
198 	u64 dbgctl;
199 	u64 br_from;
200 	u64 br_to;
201 	u64 last_excp_from;
202 	u64 last_excp_to;
203 
204 	/*
205 	 * The following part of the save area is valid only for
206 	 * SEV-ES guests when referenced through the GHCB.
207 	 */
208 	u8 reserved_7[104];
209 	u64 reserved_8;		/* rax already available at 0x01f8 */
210 	u64 rcx;
211 	u64 rdx;
212 	u64 rbx;
213 	u64 reserved_9;		/* rsp already available at 0x01d8 */
214 	u64 rbp;
215 	u64 rsi;
216 	u64 rdi;
217 	u64 r8;
218 	u64 r9;
219 	u64 r10;
220 	u64 r11;
221 	u64 r12;
222 	u64 r13;
223 	u64 r14;
224 	u64 r15;
225 	u8 reserved_10[16];
226 	u64 sw_exit_code;
227 	u64 sw_exit_info_1;
228 	u64 sw_exit_info_2;
229 	u64 sw_scratch;
230 	u8 reserved_11[56];
231 	u64 xcr0;
232 	u8 valid_bitmap[16];
233 	u64 x87_state_gpa;
234 } __packed;
235 
236 struct ghcb {
237 	struct vmcb_save_area save;
238 	u8 reserved_save[2048 - sizeof(struct vmcb_save_area)];
239 
240 	u8 shared_buffer[2032];
241 
242 	u8 reserved_1[10];
243 	u16 protocol_version;	/* negotiated SEV-ES/GHCB protocol version */
244 	u32 ghcb_usage;
245 } __packed;
246 
247 
248 #define EXPECTED_VMCB_SAVE_AREA_SIZE		1032
249 #define EXPECTED_VMCB_CONTROL_AREA_SIZE		256
250 #define EXPECTED_GHCB_SIZE			PAGE_SIZE
251 
252 static inline void __unused_size_checks(void)
253 {
254 	BUILD_BUG_ON(sizeof(struct vmcb_save_area)	!= EXPECTED_VMCB_SAVE_AREA_SIZE);
255 	BUILD_BUG_ON(sizeof(struct vmcb_control_area)	!= EXPECTED_VMCB_CONTROL_AREA_SIZE);
256 	BUILD_BUG_ON(sizeof(struct ghcb)		!= EXPECTED_GHCB_SIZE);
257 }
258 
259 struct vmcb {
260 	struct vmcb_control_area control;
261 	u8 reserved_control[1024 - sizeof(struct vmcb_control_area)];
262 	struct vmcb_save_area save;
263 } __packed;
264 
265 #define SVM_CPUID_FUNC 0x8000000a
266 
267 #define SVM_VM_CR_SVM_DISABLE 4
268 
269 #define SVM_SELECTOR_S_SHIFT 4
270 #define SVM_SELECTOR_DPL_SHIFT 5
271 #define SVM_SELECTOR_P_SHIFT 7
272 #define SVM_SELECTOR_AVL_SHIFT 8
273 #define SVM_SELECTOR_L_SHIFT 9
274 #define SVM_SELECTOR_DB_SHIFT 10
275 #define SVM_SELECTOR_G_SHIFT 11
276 
277 #define SVM_SELECTOR_TYPE_MASK (0xf)
278 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
279 #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
280 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
281 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
282 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
283 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
284 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
285 
286 #define SVM_SELECTOR_WRITE_MASK (1 << 1)
287 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
288 #define SVM_SELECTOR_CODE_MASK (1 << 3)
289 
290 #define INTERCEPT_CR0_READ	0
291 #define INTERCEPT_CR3_READ	3
292 #define INTERCEPT_CR4_READ	4
293 #define INTERCEPT_CR8_READ	8
294 #define INTERCEPT_CR0_WRITE	(16 + 0)
295 #define INTERCEPT_CR3_WRITE	(16 + 3)
296 #define INTERCEPT_CR4_WRITE	(16 + 4)
297 #define INTERCEPT_CR8_WRITE	(16 + 8)
298 
299 #define INTERCEPT_DR0_READ	0
300 #define INTERCEPT_DR1_READ	1
301 #define INTERCEPT_DR2_READ	2
302 #define INTERCEPT_DR3_READ	3
303 #define INTERCEPT_DR4_READ	4
304 #define INTERCEPT_DR5_READ	5
305 #define INTERCEPT_DR6_READ	6
306 #define INTERCEPT_DR7_READ	7
307 #define INTERCEPT_DR0_WRITE	(16 + 0)
308 #define INTERCEPT_DR1_WRITE	(16 + 1)
309 #define INTERCEPT_DR2_WRITE	(16 + 2)
310 #define INTERCEPT_DR3_WRITE	(16 + 3)
311 #define INTERCEPT_DR4_WRITE	(16 + 4)
312 #define INTERCEPT_DR5_WRITE	(16 + 5)
313 #define INTERCEPT_DR6_WRITE	(16 + 6)
314 #define INTERCEPT_DR7_WRITE	(16 + 7)
315 
316 #define SVM_EVTINJ_VEC_MASK 0xff
317 
318 #define SVM_EVTINJ_TYPE_SHIFT 8
319 #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
320 
321 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
322 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
323 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
324 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
325 
326 #define SVM_EVTINJ_VALID (1 << 31)
327 #define SVM_EVTINJ_VALID_ERR (1 << 11)
328 
329 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
330 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
331 
332 #define	SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
333 #define	SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
334 #define	SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
335 #define	SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
336 
337 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
338 #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
339 
340 #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
341 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
342 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
343 
344 #define SVM_EXITINFO_REG_MASK 0x0F
345 
346 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
347 
348 /* GHCB Accessor functions */
349 
350 #define GHCB_BITMAP_IDX(field)							\
351 	(offsetof(struct vmcb_save_area, field) / sizeof(u64))
352 
353 #define DEFINE_GHCB_ACCESSORS(field)						\
354 	static inline bool ghcb_##field##_is_valid(const struct ghcb *ghcb)	\
355 	{									\
356 		return test_bit(GHCB_BITMAP_IDX(field),				\
357 				(unsigned long *)&ghcb->save.valid_bitmap);	\
358 	}									\
359 										\
360 	static inline void ghcb_set_##field(struct ghcb *ghcb, u64 value)	\
361 	{									\
362 		__set_bit(GHCB_BITMAP_IDX(field),				\
363 			  (unsigned long *)&ghcb->save.valid_bitmap);		\
364 		ghcb->save.field = value;					\
365 	}
366 
367 DEFINE_GHCB_ACCESSORS(cpl)
368 DEFINE_GHCB_ACCESSORS(rip)
369 DEFINE_GHCB_ACCESSORS(rsp)
370 DEFINE_GHCB_ACCESSORS(rax)
371 DEFINE_GHCB_ACCESSORS(rcx)
372 DEFINE_GHCB_ACCESSORS(rdx)
373 DEFINE_GHCB_ACCESSORS(rbx)
374 DEFINE_GHCB_ACCESSORS(rbp)
375 DEFINE_GHCB_ACCESSORS(rsi)
376 DEFINE_GHCB_ACCESSORS(rdi)
377 DEFINE_GHCB_ACCESSORS(r8)
378 DEFINE_GHCB_ACCESSORS(r9)
379 DEFINE_GHCB_ACCESSORS(r10)
380 DEFINE_GHCB_ACCESSORS(r11)
381 DEFINE_GHCB_ACCESSORS(r12)
382 DEFINE_GHCB_ACCESSORS(r13)
383 DEFINE_GHCB_ACCESSORS(r14)
384 DEFINE_GHCB_ACCESSORS(r15)
385 DEFINE_GHCB_ACCESSORS(sw_exit_code)
386 DEFINE_GHCB_ACCESSORS(sw_exit_info_1)
387 DEFINE_GHCB_ACCESSORS(sw_exit_info_2)
388 DEFINE_GHCB_ACCESSORS(sw_scratch)
389 DEFINE_GHCB_ACCESSORS(xcr0)
390 
391 #endif
392