1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __SVM_H 3 #define __SVM_H 4 5 #include <uapi/asm/svm.h> 6 #include <uapi/asm/kvm.h> 7 8 /* 9 * 32-bit intercept words in the VMCB Control Area, starting 10 * at Byte offset 000h. 11 */ 12 13 enum intercept_words { 14 INTERCEPT_CR = 0, 15 INTERCEPT_DR, 16 INTERCEPT_EXCEPTION, 17 INTERCEPT_WORD3, 18 INTERCEPT_WORD4, 19 INTERCEPT_WORD5, 20 MAX_INTERCEPT, 21 }; 22 23 enum { 24 /* Byte offset 000h (word 0) */ 25 INTERCEPT_CR0_READ = 0, 26 INTERCEPT_CR3_READ = 3, 27 INTERCEPT_CR4_READ = 4, 28 INTERCEPT_CR8_READ = 8, 29 INTERCEPT_CR0_WRITE = 16, 30 INTERCEPT_CR3_WRITE = 16 + 3, 31 INTERCEPT_CR4_WRITE = 16 + 4, 32 INTERCEPT_CR8_WRITE = 16 + 8, 33 /* Byte offset 004h (word 1) */ 34 INTERCEPT_DR0_READ = 32, 35 INTERCEPT_DR1_READ, 36 INTERCEPT_DR2_READ, 37 INTERCEPT_DR3_READ, 38 INTERCEPT_DR4_READ, 39 INTERCEPT_DR5_READ, 40 INTERCEPT_DR6_READ, 41 INTERCEPT_DR7_READ, 42 INTERCEPT_DR0_WRITE = 48, 43 INTERCEPT_DR1_WRITE, 44 INTERCEPT_DR2_WRITE, 45 INTERCEPT_DR3_WRITE, 46 INTERCEPT_DR4_WRITE, 47 INTERCEPT_DR5_WRITE, 48 INTERCEPT_DR6_WRITE, 49 INTERCEPT_DR7_WRITE, 50 /* Byte offset 008h (word 2) */ 51 INTERCEPT_EXCEPTION_OFFSET = 64, 52 /* Byte offset 00Ch (word 3) */ 53 INTERCEPT_INTR = 96, 54 INTERCEPT_NMI, 55 INTERCEPT_SMI, 56 INTERCEPT_INIT, 57 INTERCEPT_VINTR, 58 INTERCEPT_SELECTIVE_CR0, 59 INTERCEPT_STORE_IDTR, 60 INTERCEPT_STORE_GDTR, 61 INTERCEPT_STORE_LDTR, 62 INTERCEPT_STORE_TR, 63 INTERCEPT_LOAD_IDTR, 64 INTERCEPT_LOAD_GDTR, 65 INTERCEPT_LOAD_LDTR, 66 INTERCEPT_LOAD_TR, 67 INTERCEPT_RDTSC, 68 INTERCEPT_RDPMC, 69 INTERCEPT_PUSHF, 70 INTERCEPT_POPF, 71 INTERCEPT_CPUID, 72 INTERCEPT_RSM, 73 INTERCEPT_IRET, 74 INTERCEPT_INTn, 75 INTERCEPT_INVD, 76 INTERCEPT_PAUSE, 77 INTERCEPT_HLT, 78 INTERCEPT_INVLPG, 79 INTERCEPT_INVLPGA, 80 INTERCEPT_IOIO_PROT, 81 INTERCEPT_MSR_PROT, 82 INTERCEPT_TASK_SWITCH, 83 INTERCEPT_FERR_FREEZE, 84 INTERCEPT_SHUTDOWN, 85 /* Byte offset 010h (word 4) */ 86 INTERCEPT_VMRUN = 128, 87 INTERCEPT_VMMCALL, 88 INTERCEPT_VMLOAD, 89 INTERCEPT_VMSAVE, 90 INTERCEPT_STGI, 91 INTERCEPT_CLGI, 92 INTERCEPT_SKINIT, 93 INTERCEPT_RDTSCP, 94 INTERCEPT_ICEBP, 95 INTERCEPT_WBINVD, 96 INTERCEPT_MONITOR, 97 INTERCEPT_MWAIT, 98 INTERCEPT_MWAIT_COND, 99 INTERCEPT_XSETBV, 100 INTERCEPT_RDPRU, 101 /* Byte offset 014h (word 5) */ 102 INTERCEPT_INVLPGB = 160, 103 INTERCEPT_INVLPGB_ILLEGAL, 104 INTERCEPT_INVPCID, 105 INTERCEPT_MCOMMIT, 106 INTERCEPT_TLBSYNC, 107 }; 108 109 110 struct __attribute__ ((__packed__)) vmcb_control_area { 111 u32 intercepts[MAX_INTERCEPT]; 112 u32 reserved_1[15 - MAX_INTERCEPT]; 113 u16 pause_filter_thresh; 114 u16 pause_filter_count; 115 u64 iopm_base_pa; 116 u64 msrpm_base_pa; 117 u64 tsc_offset; 118 u32 asid; 119 u8 tlb_ctl; 120 u8 reserved_2[3]; 121 u32 int_ctl; 122 u32 int_vector; 123 u32 int_state; 124 u8 reserved_3[4]; 125 u32 exit_code; 126 u32 exit_code_hi; 127 u64 exit_info_1; 128 u64 exit_info_2; 129 u32 exit_int_info; 130 u32 exit_int_info_err; 131 u64 nested_ctl; 132 u64 avic_vapic_bar; 133 u8 reserved_4[8]; 134 u32 event_inj; 135 u32 event_inj_err; 136 u64 nested_cr3; 137 u64 virt_ext; 138 u32 clean; 139 u32 reserved_5; 140 u64 next_rip; 141 u8 insn_len; 142 u8 insn_bytes[15]; 143 u64 avic_backing_page; /* Offset 0xe0 */ 144 u8 reserved_6[8]; /* Offset 0xe8 */ 145 u64 avic_logical_id; /* Offset 0xf0 */ 146 u64 avic_physical_id; /* Offset 0xf8 */ 147 }; 148 149 150 #define TLB_CONTROL_DO_NOTHING 0 151 #define TLB_CONTROL_FLUSH_ALL_ASID 1 152 #define TLB_CONTROL_FLUSH_ASID 3 153 #define TLB_CONTROL_FLUSH_ASID_LOCAL 7 154 155 #define V_TPR_MASK 0x0f 156 157 #define V_IRQ_SHIFT 8 158 #define V_IRQ_MASK (1 << V_IRQ_SHIFT) 159 160 #define V_GIF_SHIFT 9 161 #define V_GIF_MASK (1 << V_GIF_SHIFT) 162 163 #define V_INTR_PRIO_SHIFT 16 164 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT) 165 166 #define V_IGN_TPR_SHIFT 20 167 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT) 168 169 #define V_INTR_MASKING_SHIFT 24 170 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT) 171 172 #define V_GIF_ENABLE_SHIFT 25 173 #define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT) 174 175 #define AVIC_ENABLE_SHIFT 31 176 #define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT) 177 178 #define LBR_CTL_ENABLE_MASK BIT_ULL(0) 179 #define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1) 180 181 #define SVM_INTERRUPT_SHADOW_MASK 1 182 183 #define SVM_IOIO_STR_SHIFT 2 184 #define SVM_IOIO_REP_SHIFT 3 185 #define SVM_IOIO_SIZE_SHIFT 4 186 #define SVM_IOIO_ASIZE_SHIFT 7 187 188 #define SVM_IOIO_TYPE_MASK 1 189 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT) 190 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT) 191 #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT) 192 #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT) 193 194 #define SVM_VM_CR_VALID_MASK 0x001fULL 195 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL 196 #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL 197 198 #define SVM_NESTED_CTL_NP_ENABLE BIT(0) 199 #define SVM_NESTED_CTL_SEV_ENABLE BIT(1) 200 201 struct vmcb_seg { 202 u16 selector; 203 u16 attrib; 204 u32 limit; 205 u64 base; 206 } __packed; 207 208 struct vmcb_save_area { 209 struct vmcb_seg es; 210 struct vmcb_seg cs; 211 struct vmcb_seg ss; 212 struct vmcb_seg ds; 213 struct vmcb_seg fs; 214 struct vmcb_seg gs; 215 struct vmcb_seg gdtr; 216 struct vmcb_seg ldtr; 217 struct vmcb_seg idtr; 218 struct vmcb_seg tr; 219 u8 reserved_1[43]; 220 u8 cpl; 221 u8 reserved_2[4]; 222 u64 efer; 223 u8 reserved_3[112]; 224 u64 cr4; 225 u64 cr3; 226 u64 cr0; 227 u64 dr7; 228 u64 dr6; 229 u64 rflags; 230 u64 rip; 231 u8 reserved_4[88]; 232 u64 rsp; 233 u8 reserved_5[24]; 234 u64 rax; 235 u64 star; 236 u64 lstar; 237 u64 cstar; 238 u64 sfmask; 239 u64 kernel_gs_base; 240 u64 sysenter_cs; 241 u64 sysenter_esp; 242 u64 sysenter_eip; 243 u64 cr2; 244 u8 reserved_6[32]; 245 u64 g_pat; 246 u64 dbgctl; 247 u64 br_from; 248 u64 br_to; 249 u64 last_excp_from; 250 u64 last_excp_to; 251 252 /* 253 * The following part of the save area is valid only for 254 * SEV-ES guests when referenced through the GHCB. 255 */ 256 u8 reserved_7[104]; 257 u64 reserved_8; /* rax already available at 0x01f8 */ 258 u64 rcx; 259 u64 rdx; 260 u64 rbx; 261 u64 reserved_9; /* rsp already available at 0x01d8 */ 262 u64 rbp; 263 u64 rsi; 264 u64 rdi; 265 u64 r8; 266 u64 r9; 267 u64 r10; 268 u64 r11; 269 u64 r12; 270 u64 r13; 271 u64 r14; 272 u64 r15; 273 u8 reserved_10[16]; 274 u64 sw_exit_code; 275 u64 sw_exit_info_1; 276 u64 sw_exit_info_2; 277 u64 sw_scratch; 278 u8 reserved_11[56]; 279 u64 xcr0; 280 u8 valid_bitmap[16]; 281 u64 x87_state_gpa; 282 } __packed; 283 284 struct ghcb { 285 struct vmcb_save_area save; 286 u8 reserved_save[2048 - sizeof(struct vmcb_save_area)]; 287 288 u8 shared_buffer[2032]; 289 290 u8 reserved_1[10]; 291 u16 protocol_version; /* negotiated SEV-ES/GHCB protocol version */ 292 u32 ghcb_usage; 293 } __packed; 294 295 296 #define EXPECTED_VMCB_SAVE_AREA_SIZE 1032 297 #define EXPECTED_VMCB_CONTROL_AREA_SIZE 256 298 #define EXPECTED_GHCB_SIZE PAGE_SIZE 299 300 static inline void __unused_size_checks(void) 301 { 302 BUILD_BUG_ON(sizeof(struct vmcb_save_area) != EXPECTED_VMCB_SAVE_AREA_SIZE); 303 BUILD_BUG_ON(sizeof(struct vmcb_control_area) != EXPECTED_VMCB_CONTROL_AREA_SIZE); 304 BUILD_BUG_ON(sizeof(struct ghcb) != EXPECTED_GHCB_SIZE); 305 } 306 307 struct vmcb { 308 struct vmcb_control_area control; 309 u8 reserved_control[1024 - sizeof(struct vmcb_control_area)]; 310 struct vmcb_save_area save; 311 } __packed; 312 313 #define SVM_CPUID_FUNC 0x8000000a 314 315 #define SVM_VM_CR_SVM_DISABLE 4 316 317 #define SVM_SELECTOR_S_SHIFT 4 318 #define SVM_SELECTOR_DPL_SHIFT 5 319 #define SVM_SELECTOR_P_SHIFT 7 320 #define SVM_SELECTOR_AVL_SHIFT 8 321 #define SVM_SELECTOR_L_SHIFT 9 322 #define SVM_SELECTOR_DB_SHIFT 10 323 #define SVM_SELECTOR_G_SHIFT 11 324 325 #define SVM_SELECTOR_TYPE_MASK (0xf) 326 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT) 327 #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT) 328 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT) 329 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT) 330 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT) 331 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT) 332 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT) 333 334 #define SVM_SELECTOR_WRITE_MASK (1 << 1) 335 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK 336 #define SVM_SELECTOR_CODE_MASK (1 << 3) 337 338 #define SVM_EVTINJ_VEC_MASK 0xff 339 340 #define SVM_EVTINJ_TYPE_SHIFT 8 341 #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT) 342 343 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT) 344 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT) 345 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT) 346 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT) 347 348 #define SVM_EVTINJ_VALID (1 << 31) 349 #define SVM_EVTINJ_VALID_ERR (1 << 11) 350 351 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK 352 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK 353 354 #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR 355 #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI 356 #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT 357 #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT 358 359 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID 360 #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR 361 362 #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36 363 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38 364 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44 365 366 #define SVM_EXITINFO_REG_MASK 0x0F 367 368 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP) 369 370 /* GHCB Accessor functions */ 371 372 #define GHCB_BITMAP_IDX(field) \ 373 (offsetof(struct vmcb_save_area, field) / sizeof(u64)) 374 375 #define DEFINE_GHCB_ACCESSORS(field) \ 376 static inline bool ghcb_##field##_is_valid(const struct ghcb *ghcb) \ 377 { \ 378 return test_bit(GHCB_BITMAP_IDX(field), \ 379 (unsigned long *)&ghcb->save.valid_bitmap); \ 380 } \ 381 \ 382 static inline void ghcb_set_##field(struct ghcb *ghcb, u64 value) \ 383 { \ 384 __set_bit(GHCB_BITMAP_IDX(field), \ 385 (unsigned long *)&ghcb->save.valid_bitmap); \ 386 ghcb->save.field = value; \ 387 } 388 389 DEFINE_GHCB_ACCESSORS(cpl) 390 DEFINE_GHCB_ACCESSORS(rip) 391 DEFINE_GHCB_ACCESSORS(rsp) 392 DEFINE_GHCB_ACCESSORS(rax) 393 DEFINE_GHCB_ACCESSORS(rcx) 394 DEFINE_GHCB_ACCESSORS(rdx) 395 DEFINE_GHCB_ACCESSORS(rbx) 396 DEFINE_GHCB_ACCESSORS(rbp) 397 DEFINE_GHCB_ACCESSORS(rsi) 398 DEFINE_GHCB_ACCESSORS(rdi) 399 DEFINE_GHCB_ACCESSORS(r8) 400 DEFINE_GHCB_ACCESSORS(r9) 401 DEFINE_GHCB_ACCESSORS(r10) 402 DEFINE_GHCB_ACCESSORS(r11) 403 DEFINE_GHCB_ACCESSORS(r12) 404 DEFINE_GHCB_ACCESSORS(r13) 405 DEFINE_GHCB_ACCESSORS(r14) 406 DEFINE_GHCB_ACCESSORS(r15) 407 DEFINE_GHCB_ACCESSORS(sw_exit_code) 408 DEFINE_GHCB_ACCESSORS(sw_exit_info_1) 409 DEFINE_GHCB_ACCESSORS(sw_exit_info_2) 410 DEFINE_GHCB_ACCESSORS(sw_scratch) 411 DEFINE_GHCB_ACCESSORS(xcr0) 412 413 #endif 414