1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __SVM_H 3 #define __SVM_H 4 5 #include <uapi/asm/svm.h> 6 #include <uapi/asm/kvm.h> 7 8 /* 9 * 32-bit intercept words in the VMCB Control Area, starting 10 * at Byte offset 000h. 11 */ 12 13 enum intercept_words { 14 INTERCEPT_CR = 0, 15 INTERCEPT_DR, 16 INTERCEPT_EXCEPTION, 17 INTERCEPT_WORD3, 18 INTERCEPT_WORD4, 19 INTERCEPT_WORD5, 20 MAX_INTERCEPT, 21 }; 22 23 enum { 24 /* Byte offset 000h (word 0) */ 25 INTERCEPT_CR0_READ = 0, 26 INTERCEPT_CR3_READ = 3, 27 INTERCEPT_CR4_READ = 4, 28 INTERCEPT_CR8_READ = 8, 29 INTERCEPT_CR0_WRITE = 16, 30 INTERCEPT_CR3_WRITE = 16 + 3, 31 INTERCEPT_CR4_WRITE = 16 + 4, 32 INTERCEPT_CR8_WRITE = 16 + 8, 33 /* Byte offset 004h (word 1) */ 34 INTERCEPT_DR0_READ = 32, 35 INTERCEPT_DR1_READ, 36 INTERCEPT_DR2_READ, 37 INTERCEPT_DR3_READ, 38 INTERCEPT_DR4_READ, 39 INTERCEPT_DR5_READ, 40 INTERCEPT_DR6_READ, 41 INTERCEPT_DR7_READ, 42 INTERCEPT_DR0_WRITE = 48, 43 INTERCEPT_DR1_WRITE, 44 INTERCEPT_DR2_WRITE, 45 INTERCEPT_DR3_WRITE, 46 INTERCEPT_DR4_WRITE, 47 INTERCEPT_DR5_WRITE, 48 INTERCEPT_DR6_WRITE, 49 INTERCEPT_DR7_WRITE, 50 /* Byte offset 008h (word 2) */ 51 INTERCEPT_EXCEPTION_OFFSET = 64, 52 /* Byte offset 00Ch (word 3) */ 53 INTERCEPT_INTR = 96, 54 INTERCEPT_NMI, 55 INTERCEPT_SMI, 56 INTERCEPT_INIT, 57 INTERCEPT_VINTR, 58 INTERCEPT_SELECTIVE_CR0, 59 INTERCEPT_STORE_IDTR, 60 INTERCEPT_STORE_GDTR, 61 INTERCEPT_STORE_LDTR, 62 INTERCEPT_STORE_TR, 63 INTERCEPT_LOAD_IDTR, 64 INTERCEPT_LOAD_GDTR, 65 INTERCEPT_LOAD_LDTR, 66 INTERCEPT_LOAD_TR, 67 INTERCEPT_RDTSC, 68 INTERCEPT_RDPMC, 69 INTERCEPT_PUSHF, 70 INTERCEPT_POPF, 71 INTERCEPT_CPUID, 72 INTERCEPT_RSM, 73 INTERCEPT_IRET, 74 INTERCEPT_INTn, 75 INTERCEPT_INVD, 76 INTERCEPT_PAUSE, 77 INTERCEPT_HLT, 78 INTERCEPT_INVLPG, 79 INTERCEPT_INVLPGA, 80 INTERCEPT_IOIO_PROT, 81 INTERCEPT_MSR_PROT, 82 INTERCEPT_TASK_SWITCH, 83 INTERCEPT_FERR_FREEZE, 84 INTERCEPT_SHUTDOWN, 85 /* Byte offset 010h (word 4) */ 86 INTERCEPT_VMRUN = 128, 87 INTERCEPT_VMMCALL, 88 INTERCEPT_VMLOAD, 89 INTERCEPT_VMSAVE, 90 INTERCEPT_STGI, 91 INTERCEPT_CLGI, 92 INTERCEPT_SKINIT, 93 INTERCEPT_RDTSCP, 94 INTERCEPT_ICEBP, 95 INTERCEPT_WBINVD, 96 INTERCEPT_MONITOR, 97 INTERCEPT_MWAIT, 98 INTERCEPT_MWAIT_COND, 99 INTERCEPT_XSETBV, 100 INTERCEPT_RDPRU, 101 TRAP_EFER_WRITE, 102 TRAP_CR0_WRITE, 103 TRAP_CR1_WRITE, 104 TRAP_CR2_WRITE, 105 TRAP_CR3_WRITE, 106 TRAP_CR4_WRITE, 107 TRAP_CR5_WRITE, 108 TRAP_CR6_WRITE, 109 TRAP_CR7_WRITE, 110 TRAP_CR8_WRITE, 111 /* Byte offset 014h (word 5) */ 112 INTERCEPT_INVLPGB = 160, 113 INTERCEPT_INVLPGB_ILLEGAL, 114 INTERCEPT_INVPCID, 115 INTERCEPT_MCOMMIT, 116 INTERCEPT_TLBSYNC, 117 }; 118 119 120 struct __attribute__ ((__packed__)) vmcb_control_area { 121 u32 intercepts[MAX_INTERCEPT]; 122 u32 reserved_1[15 - MAX_INTERCEPT]; 123 u16 pause_filter_thresh; 124 u16 pause_filter_count; 125 u64 iopm_base_pa; 126 u64 msrpm_base_pa; 127 u64 tsc_offset; 128 u32 asid; 129 u8 tlb_ctl; 130 u8 reserved_2[3]; 131 u32 int_ctl; 132 u32 int_vector; 133 u32 int_state; 134 u8 reserved_3[4]; 135 u32 exit_code; 136 u32 exit_code_hi; 137 u64 exit_info_1; 138 u64 exit_info_2; 139 u32 exit_int_info; 140 u32 exit_int_info_err; 141 u64 nested_ctl; 142 u64 avic_vapic_bar; 143 u64 ghcb_gpa; 144 u32 event_inj; 145 u32 event_inj_err; 146 u64 nested_cr3; 147 u64 virt_ext; 148 u32 clean; 149 u32 reserved_5; 150 u64 next_rip; 151 u8 insn_len; 152 u8 insn_bytes[15]; 153 u64 avic_backing_page; /* Offset 0xe0 */ 154 u8 reserved_6[8]; /* Offset 0xe8 */ 155 u64 avic_logical_id; /* Offset 0xf0 */ 156 u64 avic_physical_id; /* Offset 0xf8 */ 157 u8 reserved_7[8]; 158 u64 vmsa_pa; /* Used for an SEV-ES guest */ 159 u8 reserved_8[720]; 160 /* 161 * Offset 0x3e0, 32 bytes reserved 162 * for use by hypervisor/software. 163 */ 164 u8 reserved_sw[32]; 165 }; 166 167 168 #define TLB_CONTROL_DO_NOTHING 0 169 #define TLB_CONTROL_FLUSH_ALL_ASID 1 170 #define TLB_CONTROL_FLUSH_ASID 3 171 #define TLB_CONTROL_FLUSH_ASID_LOCAL 7 172 173 #define V_TPR_MASK 0x0f 174 175 #define V_IRQ_SHIFT 8 176 #define V_IRQ_MASK (1 << V_IRQ_SHIFT) 177 178 #define V_GIF_SHIFT 9 179 #define V_GIF_MASK (1 << V_GIF_SHIFT) 180 181 #define V_INTR_PRIO_SHIFT 16 182 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT) 183 184 #define V_IGN_TPR_SHIFT 20 185 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT) 186 187 #define V_IRQ_INJECTION_BITS_MASK (V_IRQ_MASK | V_INTR_PRIO_MASK | V_IGN_TPR_MASK) 188 189 #define V_INTR_MASKING_SHIFT 24 190 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT) 191 192 #define V_GIF_ENABLE_SHIFT 25 193 #define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT) 194 195 #define AVIC_ENABLE_SHIFT 31 196 #define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT) 197 198 #define X2APIC_MODE_SHIFT 30 199 #define X2APIC_MODE_MASK (1 << X2APIC_MODE_SHIFT) 200 201 #define LBR_CTL_ENABLE_MASK BIT_ULL(0) 202 #define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1) 203 204 #define SVM_INTERRUPT_SHADOW_MASK BIT_ULL(0) 205 #define SVM_GUEST_INTERRUPT_MASK BIT_ULL(1) 206 207 #define SVM_IOIO_STR_SHIFT 2 208 #define SVM_IOIO_REP_SHIFT 3 209 #define SVM_IOIO_SIZE_SHIFT 4 210 #define SVM_IOIO_ASIZE_SHIFT 7 211 212 #define SVM_IOIO_TYPE_MASK 1 213 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT) 214 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT) 215 #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT) 216 #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT) 217 218 #define SVM_VM_CR_VALID_MASK 0x001fULL 219 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL 220 #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL 221 222 #define SVM_NESTED_CTL_NP_ENABLE BIT(0) 223 #define SVM_NESTED_CTL_SEV_ENABLE BIT(1) 224 #define SVM_NESTED_CTL_SEV_ES_ENABLE BIT(2) 225 226 227 #define SVM_TSC_RATIO_RSVD 0xffffff0000000000ULL 228 #define SVM_TSC_RATIO_MIN 0x0000000000000001ULL 229 #define SVM_TSC_RATIO_MAX 0x000000ffffffffffULL 230 #define SVM_TSC_RATIO_DEFAULT 0x0100000000ULL 231 232 233 /* AVIC */ 234 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFFULL) 235 #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31 236 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31) 237 238 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK GENMASK_ULL(11, 0) 239 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12) 240 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62) 241 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63) 242 #define AVIC_PHYSICAL_ID_TABLE_SIZE_MASK (0xFFULL) 243 244 #define AVIC_DOORBELL_PHYSICAL_ID_MASK GENMASK_ULL(11, 0) 245 246 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL 247 248 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1 249 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0 250 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF 251 252 enum avic_ipi_failure_cause { 253 AVIC_IPI_FAILURE_INVALID_INT_TYPE, 254 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING, 255 AVIC_IPI_FAILURE_INVALID_TARGET, 256 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE, 257 }; 258 259 #define AVIC_PHYSICAL_MAX_INDEX_MASK GENMASK_ULL(9, 0) 260 261 /* 262 * For AVIC, the max index allowed for physical APIC ID 263 * table is 0xff (255). 264 */ 265 #define AVIC_MAX_PHYSICAL_ID 0XFEULL 266 267 /* 268 * For x2AVIC, the max index allowed for physical APIC ID 269 * table is 0x1ff (511). 270 */ 271 #define X2AVIC_MAX_PHYSICAL_ID 0x1FFUL 272 273 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF) 274 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL 275 276 277 struct vmcb_seg { 278 u16 selector; 279 u16 attrib; 280 u32 limit; 281 u64 base; 282 } __packed; 283 284 /* Save area definition for legacy and SEV-MEM guests */ 285 struct vmcb_save_area { 286 struct vmcb_seg es; 287 struct vmcb_seg cs; 288 struct vmcb_seg ss; 289 struct vmcb_seg ds; 290 struct vmcb_seg fs; 291 struct vmcb_seg gs; 292 struct vmcb_seg gdtr; 293 struct vmcb_seg ldtr; 294 struct vmcb_seg idtr; 295 struct vmcb_seg tr; 296 u8 reserved_1[42]; 297 u8 vmpl; 298 u8 cpl; 299 u8 reserved_2[4]; 300 u64 efer; 301 u8 reserved_3[112]; 302 u64 cr4; 303 u64 cr3; 304 u64 cr0; 305 u64 dr7; 306 u64 dr6; 307 u64 rflags; 308 u64 rip; 309 u8 reserved_4[88]; 310 u64 rsp; 311 u64 s_cet; 312 u64 ssp; 313 u64 isst_addr; 314 u64 rax; 315 u64 star; 316 u64 lstar; 317 u64 cstar; 318 u64 sfmask; 319 u64 kernel_gs_base; 320 u64 sysenter_cs; 321 u64 sysenter_esp; 322 u64 sysenter_eip; 323 u64 cr2; 324 u8 reserved_5[32]; 325 u64 g_pat; 326 u64 dbgctl; 327 u64 br_from; 328 u64 br_to; 329 u64 last_excp_from; 330 u64 last_excp_to; 331 u8 reserved_6[72]; 332 u32 spec_ctrl; /* Guest version of SPEC_CTRL at 0x2E0 */ 333 } __packed; 334 335 /* Save area definition for SEV-ES and SEV-SNP guests */ 336 struct sev_es_save_area { 337 struct vmcb_seg es; 338 struct vmcb_seg cs; 339 struct vmcb_seg ss; 340 struct vmcb_seg ds; 341 struct vmcb_seg fs; 342 struct vmcb_seg gs; 343 struct vmcb_seg gdtr; 344 struct vmcb_seg ldtr; 345 struct vmcb_seg idtr; 346 struct vmcb_seg tr; 347 u64 vmpl0_ssp; 348 u64 vmpl1_ssp; 349 u64 vmpl2_ssp; 350 u64 vmpl3_ssp; 351 u64 u_cet; 352 u8 reserved_1[2]; 353 u8 vmpl; 354 u8 cpl; 355 u8 reserved_2[4]; 356 u64 efer; 357 u8 reserved_3[104]; 358 u64 xss; 359 u64 cr4; 360 u64 cr3; 361 u64 cr0; 362 u64 dr7; 363 u64 dr6; 364 u64 rflags; 365 u64 rip; 366 u64 dr0; 367 u64 dr1; 368 u64 dr2; 369 u64 dr3; 370 u64 dr0_addr_mask; 371 u64 dr1_addr_mask; 372 u64 dr2_addr_mask; 373 u64 dr3_addr_mask; 374 u8 reserved_4[24]; 375 u64 rsp; 376 u64 s_cet; 377 u64 ssp; 378 u64 isst_addr; 379 u64 rax; 380 u64 star; 381 u64 lstar; 382 u64 cstar; 383 u64 sfmask; 384 u64 kernel_gs_base; 385 u64 sysenter_cs; 386 u64 sysenter_esp; 387 u64 sysenter_eip; 388 u64 cr2; 389 u8 reserved_5[32]; 390 u64 g_pat; 391 u64 dbgctl; 392 u64 br_from; 393 u64 br_to; 394 u64 last_excp_from; 395 u64 last_excp_to; 396 u8 reserved_7[80]; 397 u32 pkru; 398 u8 reserved_8[20]; 399 u64 reserved_9; /* rax already available at 0x01f8 */ 400 u64 rcx; 401 u64 rdx; 402 u64 rbx; 403 u64 reserved_10; /* rsp already available at 0x01d8 */ 404 u64 rbp; 405 u64 rsi; 406 u64 rdi; 407 u64 r8; 408 u64 r9; 409 u64 r10; 410 u64 r11; 411 u64 r12; 412 u64 r13; 413 u64 r14; 414 u64 r15; 415 u8 reserved_11[16]; 416 u64 guest_exit_info_1; 417 u64 guest_exit_info_2; 418 u64 guest_exit_int_info; 419 u64 guest_nrip; 420 u64 sev_features; 421 u64 vintr_ctrl; 422 u64 guest_exit_code; 423 u64 virtual_tom; 424 u64 tlb_id; 425 u64 pcpu_id; 426 u64 event_inj; 427 u64 xcr0; 428 u8 reserved_12[16]; 429 430 /* Floating point area */ 431 u64 x87_dp; 432 u32 mxcsr; 433 u16 x87_ftw; 434 u16 x87_fsw; 435 u16 x87_fcw; 436 u16 x87_fop; 437 u16 x87_ds; 438 u16 x87_cs; 439 u64 x87_rip; 440 u8 fpreg_x87[80]; 441 u8 fpreg_xmm[256]; 442 u8 fpreg_ymm[256]; 443 } __packed; 444 445 struct ghcb_save_area { 446 u8 reserved_1[203]; 447 u8 cpl; 448 u8 reserved_2[116]; 449 u64 xss; 450 u8 reserved_3[24]; 451 u64 dr7; 452 u8 reserved_4[16]; 453 u64 rip; 454 u8 reserved_5[88]; 455 u64 rsp; 456 u8 reserved_6[24]; 457 u64 rax; 458 u8 reserved_7[264]; 459 u64 rcx; 460 u64 rdx; 461 u64 rbx; 462 u8 reserved_8[8]; 463 u64 rbp; 464 u64 rsi; 465 u64 rdi; 466 u64 r8; 467 u64 r9; 468 u64 r10; 469 u64 r11; 470 u64 r12; 471 u64 r13; 472 u64 r14; 473 u64 r15; 474 u8 reserved_9[16]; 475 u64 sw_exit_code; 476 u64 sw_exit_info_1; 477 u64 sw_exit_info_2; 478 u64 sw_scratch; 479 u8 reserved_10[56]; 480 u64 xcr0; 481 u8 valid_bitmap[16]; 482 u64 x87_state_gpa; 483 } __packed; 484 485 #define GHCB_SHARED_BUF_SIZE 2032 486 487 struct ghcb { 488 struct ghcb_save_area save; 489 u8 reserved_save[2048 - sizeof(struct ghcb_save_area)]; 490 491 u8 shared_buffer[GHCB_SHARED_BUF_SIZE]; 492 493 u8 reserved_1[10]; 494 u16 protocol_version; /* negotiated SEV-ES/GHCB protocol version */ 495 u32 ghcb_usage; 496 } __packed; 497 498 499 #define EXPECTED_VMCB_SAVE_AREA_SIZE 740 500 #define EXPECTED_GHCB_SAVE_AREA_SIZE 1032 501 #define EXPECTED_SEV_ES_SAVE_AREA_SIZE 1648 502 #define EXPECTED_VMCB_CONTROL_AREA_SIZE 1024 503 #define EXPECTED_GHCB_SIZE PAGE_SIZE 504 505 static inline void __unused_size_checks(void) 506 { 507 BUILD_BUG_ON(sizeof(struct vmcb_save_area) != EXPECTED_VMCB_SAVE_AREA_SIZE); 508 BUILD_BUG_ON(sizeof(struct ghcb_save_area) != EXPECTED_GHCB_SAVE_AREA_SIZE); 509 BUILD_BUG_ON(sizeof(struct sev_es_save_area) != EXPECTED_SEV_ES_SAVE_AREA_SIZE); 510 BUILD_BUG_ON(sizeof(struct vmcb_control_area) != EXPECTED_VMCB_CONTROL_AREA_SIZE); 511 BUILD_BUG_ON(sizeof(struct ghcb) != EXPECTED_GHCB_SIZE); 512 } 513 514 struct vmcb { 515 struct vmcb_control_area control; 516 struct vmcb_save_area save; 517 } __packed; 518 519 #define SVM_CPUID_FUNC 0x8000000a 520 521 #define SVM_VM_CR_SVM_DISABLE 4 522 523 #define SVM_SELECTOR_S_SHIFT 4 524 #define SVM_SELECTOR_DPL_SHIFT 5 525 #define SVM_SELECTOR_P_SHIFT 7 526 #define SVM_SELECTOR_AVL_SHIFT 8 527 #define SVM_SELECTOR_L_SHIFT 9 528 #define SVM_SELECTOR_DB_SHIFT 10 529 #define SVM_SELECTOR_G_SHIFT 11 530 531 #define SVM_SELECTOR_TYPE_MASK (0xf) 532 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT) 533 #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT) 534 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT) 535 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT) 536 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT) 537 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT) 538 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT) 539 540 #define SVM_SELECTOR_WRITE_MASK (1 << 1) 541 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK 542 #define SVM_SELECTOR_CODE_MASK (1 << 3) 543 544 #define SVM_EVTINJ_VEC_MASK 0xff 545 546 #define SVM_EVTINJ_TYPE_SHIFT 8 547 #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT) 548 549 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT) 550 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT) 551 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT) 552 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT) 553 554 #define SVM_EVTINJ_VALID (1 << 31) 555 #define SVM_EVTINJ_VALID_ERR (1 << 11) 556 557 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK 558 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK 559 560 #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR 561 #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI 562 #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT 563 #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT 564 565 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID 566 #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR 567 568 #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36 569 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38 570 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44 571 572 #define SVM_EXITINFO_REG_MASK 0x0F 573 574 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP) 575 576 /* GHCB Accessor functions */ 577 578 #define GHCB_BITMAP_IDX(field) \ 579 (offsetof(struct ghcb_save_area, field) / sizeof(u64)) 580 581 #define DEFINE_GHCB_ACCESSORS(field) \ 582 static __always_inline bool ghcb_##field##_is_valid(const struct ghcb *ghcb) \ 583 { \ 584 return test_bit(GHCB_BITMAP_IDX(field), \ 585 (unsigned long *)&ghcb->save.valid_bitmap); \ 586 } \ 587 \ 588 static __always_inline u64 ghcb_get_##field(struct ghcb *ghcb) \ 589 { \ 590 return ghcb->save.field; \ 591 } \ 592 \ 593 static __always_inline u64 ghcb_get_##field##_if_valid(struct ghcb *ghcb) \ 594 { \ 595 return ghcb_##field##_is_valid(ghcb) ? ghcb->save.field : 0; \ 596 } \ 597 \ 598 static __always_inline void ghcb_set_##field(struct ghcb *ghcb, u64 value) \ 599 { \ 600 __set_bit(GHCB_BITMAP_IDX(field), \ 601 (unsigned long *)&ghcb->save.valid_bitmap); \ 602 ghcb->save.field = value; \ 603 } 604 605 DEFINE_GHCB_ACCESSORS(cpl) 606 DEFINE_GHCB_ACCESSORS(rip) 607 DEFINE_GHCB_ACCESSORS(rsp) 608 DEFINE_GHCB_ACCESSORS(rax) 609 DEFINE_GHCB_ACCESSORS(rcx) 610 DEFINE_GHCB_ACCESSORS(rdx) 611 DEFINE_GHCB_ACCESSORS(rbx) 612 DEFINE_GHCB_ACCESSORS(rbp) 613 DEFINE_GHCB_ACCESSORS(rsi) 614 DEFINE_GHCB_ACCESSORS(rdi) 615 DEFINE_GHCB_ACCESSORS(r8) 616 DEFINE_GHCB_ACCESSORS(r9) 617 DEFINE_GHCB_ACCESSORS(r10) 618 DEFINE_GHCB_ACCESSORS(r11) 619 DEFINE_GHCB_ACCESSORS(r12) 620 DEFINE_GHCB_ACCESSORS(r13) 621 DEFINE_GHCB_ACCESSORS(r14) 622 DEFINE_GHCB_ACCESSORS(r15) 623 DEFINE_GHCB_ACCESSORS(sw_exit_code) 624 DEFINE_GHCB_ACCESSORS(sw_exit_info_1) 625 DEFINE_GHCB_ACCESSORS(sw_exit_info_2) 626 DEFINE_GHCB_ACCESSORS(sw_scratch) 627 DEFINE_GHCB_ACCESSORS(xcr0) 628 629 #endif 630