xref: /openbmc/linux/arch/x86/include/asm/svm.h (revision 4f6cce39) 
1 #ifndef __SVM_H
2 #define __SVM_H
3 
4 #include <uapi/asm/svm.h>
5 
6 
7 enum {
8 	INTERCEPT_INTR,
9 	INTERCEPT_NMI,
10 	INTERCEPT_SMI,
11 	INTERCEPT_INIT,
12 	INTERCEPT_VINTR,
13 	INTERCEPT_SELECTIVE_CR0,
14 	INTERCEPT_STORE_IDTR,
15 	INTERCEPT_STORE_GDTR,
16 	INTERCEPT_STORE_LDTR,
17 	INTERCEPT_STORE_TR,
18 	INTERCEPT_LOAD_IDTR,
19 	INTERCEPT_LOAD_GDTR,
20 	INTERCEPT_LOAD_LDTR,
21 	INTERCEPT_LOAD_TR,
22 	INTERCEPT_RDTSC,
23 	INTERCEPT_RDPMC,
24 	INTERCEPT_PUSHF,
25 	INTERCEPT_POPF,
26 	INTERCEPT_CPUID,
27 	INTERCEPT_RSM,
28 	INTERCEPT_IRET,
29 	INTERCEPT_INTn,
30 	INTERCEPT_INVD,
31 	INTERCEPT_PAUSE,
32 	INTERCEPT_HLT,
33 	INTERCEPT_INVLPG,
34 	INTERCEPT_INVLPGA,
35 	INTERCEPT_IOIO_PROT,
36 	INTERCEPT_MSR_PROT,
37 	INTERCEPT_TASK_SWITCH,
38 	INTERCEPT_FERR_FREEZE,
39 	INTERCEPT_SHUTDOWN,
40 	INTERCEPT_VMRUN,
41 	INTERCEPT_VMMCALL,
42 	INTERCEPT_VMLOAD,
43 	INTERCEPT_VMSAVE,
44 	INTERCEPT_STGI,
45 	INTERCEPT_CLGI,
46 	INTERCEPT_SKINIT,
47 	INTERCEPT_RDTSCP,
48 	INTERCEPT_ICEBP,
49 	INTERCEPT_WBINVD,
50 	INTERCEPT_MONITOR,
51 	INTERCEPT_MWAIT,
52 	INTERCEPT_MWAIT_COND,
53 	INTERCEPT_XSETBV,
54 };
55 
56 
57 struct __attribute__ ((__packed__)) vmcb_control_area {
58 	u32 intercept_cr;
59 	u32 intercept_dr;
60 	u32 intercept_exceptions;
61 	u64 intercept;
62 	u8 reserved_1[42];
63 	u16 pause_filter_count;
64 	u64 iopm_base_pa;
65 	u64 msrpm_base_pa;
66 	u64 tsc_offset;
67 	u32 asid;
68 	u8 tlb_ctl;
69 	u8 reserved_2[3];
70 	u32 int_ctl;
71 	u32 int_vector;
72 	u32 int_state;
73 	u8 reserved_3[4];
74 	u32 exit_code;
75 	u32 exit_code_hi;
76 	u64 exit_info_1;
77 	u64 exit_info_2;
78 	u32 exit_int_info;
79 	u32 exit_int_info_err;
80 	u64 nested_ctl;
81 	u64 avic_vapic_bar;
82 	u8 reserved_4[8];
83 	u32 event_inj;
84 	u32 event_inj_err;
85 	u64 nested_cr3;
86 	u64 lbr_ctl;
87 	u32 clean;
88 	u32 reserved_5;
89 	u64 next_rip;
90 	u8 insn_len;
91 	u8 insn_bytes[15];
92 	u64 avic_backing_page;	/* Offset 0xe0 */
93 	u8 reserved_6[8];	/* Offset 0xe8 */
94 	u64 avic_logical_id;	/* Offset 0xf0 */
95 	u64 avic_physical_id;	/* Offset 0xf8 */
96 	u8 reserved_7[768];
97 };
98 
99 
100 #define TLB_CONTROL_DO_NOTHING 0
101 #define TLB_CONTROL_FLUSH_ALL_ASID 1
102 #define TLB_CONTROL_FLUSH_ASID 3
103 #define TLB_CONTROL_FLUSH_ASID_LOCAL 7
104 
105 #define V_TPR_MASK 0x0f
106 
107 #define V_IRQ_SHIFT 8
108 #define V_IRQ_MASK (1 << V_IRQ_SHIFT)
109 
110 #define V_INTR_PRIO_SHIFT 16
111 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
112 
113 #define V_IGN_TPR_SHIFT 20
114 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
115 
116 #define V_INTR_MASKING_SHIFT 24
117 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
118 
119 #define AVIC_ENABLE_SHIFT 31
120 #define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
121 
122 #define SVM_INTERRUPT_SHADOW_MASK 1
123 
124 #define SVM_IOIO_STR_SHIFT 2
125 #define SVM_IOIO_REP_SHIFT 3
126 #define SVM_IOIO_SIZE_SHIFT 4
127 #define SVM_IOIO_ASIZE_SHIFT 7
128 
129 #define SVM_IOIO_TYPE_MASK 1
130 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
131 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
132 #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
133 #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
134 
135 #define SVM_VM_CR_VALID_MASK	0x001fULL
136 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
137 #define SVM_VM_CR_SVM_DIS_MASK  0x0010ULL
138 
139 struct __attribute__ ((__packed__)) vmcb_seg {
140 	u16 selector;
141 	u16 attrib;
142 	u32 limit;
143 	u64 base;
144 };
145 
146 struct __attribute__ ((__packed__)) vmcb_save_area {
147 	struct vmcb_seg es;
148 	struct vmcb_seg cs;
149 	struct vmcb_seg ss;
150 	struct vmcb_seg ds;
151 	struct vmcb_seg fs;
152 	struct vmcb_seg gs;
153 	struct vmcb_seg gdtr;
154 	struct vmcb_seg ldtr;
155 	struct vmcb_seg idtr;
156 	struct vmcb_seg tr;
157 	u8 reserved_1[43];
158 	u8 cpl;
159 	u8 reserved_2[4];
160 	u64 efer;
161 	u8 reserved_3[112];
162 	u64 cr4;
163 	u64 cr3;
164 	u64 cr0;
165 	u64 dr7;
166 	u64 dr6;
167 	u64 rflags;
168 	u64 rip;
169 	u8 reserved_4[88];
170 	u64 rsp;
171 	u8 reserved_5[24];
172 	u64 rax;
173 	u64 star;
174 	u64 lstar;
175 	u64 cstar;
176 	u64 sfmask;
177 	u64 kernel_gs_base;
178 	u64 sysenter_cs;
179 	u64 sysenter_esp;
180 	u64 sysenter_eip;
181 	u64 cr2;
182 	u8 reserved_6[32];
183 	u64 g_pat;
184 	u64 dbgctl;
185 	u64 br_from;
186 	u64 br_to;
187 	u64 last_excp_from;
188 	u64 last_excp_to;
189 };
190 
191 struct __attribute__ ((__packed__)) vmcb {
192 	struct vmcb_control_area control;
193 	struct vmcb_save_area save;
194 };
195 
196 #define SVM_CPUID_FUNC 0x8000000a
197 
198 #define SVM_VM_CR_SVM_DISABLE 4
199 
200 #define SVM_SELECTOR_S_SHIFT 4
201 #define SVM_SELECTOR_DPL_SHIFT 5
202 #define SVM_SELECTOR_P_SHIFT 7
203 #define SVM_SELECTOR_AVL_SHIFT 8
204 #define SVM_SELECTOR_L_SHIFT 9
205 #define SVM_SELECTOR_DB_SHIFT 10
206 #define SVM_SELECTOR_G_SHIFT 11
207 
208 #define SVM_SELECTOR_TYPE_MASK (0xf)
209 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
210 #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
211 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
212 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
213 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
214 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
215 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
216 
217 #define SVM_SELECTOR_WRITE_MASK (1 << 1)
218 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
219 #define SVM_SELECTOR_CODE_MASK (1 << 3)
220 
221 #define INTERCEPT_CR0_READ	0
222 #define INTERCEPT_CR3_READ	3
223 #define INTERCEPT_CR4_READ	4
224 #define INTERCEPT_CR8_READ	8
225 #define INTERCEPT_CR0_WRITE	(16 + 0)
226 #define INTERCEPT_CR3_WRITE	(16 + 3)
227 #define INTERCEPT_CR4_WRITE	(16 + 4)
228 #define INTERCEPT_CR8_WRITE	(16 + 8)
229 
230 #define INTERCEPT_DR0_READ	0
231 #define INTERCEPT_DR1_READ	1
232 #define INTERCEPT_DR2_READ	2
233 #define INTERCEPT_DR3_READ	3
234 #define INTERCEPT_DR4_READ	4
235 #define INTERCEPT_DR5_READ	5
236 #define INTERCEPT_DR6_READ	6
237 #define INTERCEPT_DR7_READ	7
238 #define INTERCEPT_DR0_WRITE	(16 + 0)
239 #define INTERCEPT_DR1_WRITE	(16 + 1)
240 #define INTERCEPT_DR2_WRITE	(16 + 2)
241 #define INTERCEPT_DR3_WRITE	(16 + 3)
242 #define INTERCEPT_DR4_WRITE	(16 + 4)
243 #define INTERCEPT_DR5_WRITE	(16 + 5)
244 #define INTERCEPT_DR6_WRITE	(16 + 6)
245 #define INTERCEPT_DR7_WRITE	(16 + 7)
246 
247 #define SVM_EVTINJ_VEC_MASK 0xff
248 
249 #define SVM_EVTINJ_TYPE_SHIFT 8
250 #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
251 
252 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
253 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
254 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
255 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
256 
257 #define SVM_EVTINJ_VALID (1 << 31)
258 #define SVM_EVTINJ_VALID_ERR (1 << 11)
259 
260 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
261 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
262 
263 #define	SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
264 #define	SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
265 #define	SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
266 #define	SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
267 
268 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
269 #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
270 
271 #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
272 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
273 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
274 
275 #define SVM_EXITINFO_REG_MASK 0x0F
276 
277 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
278 
279 #define SVM_VMLOAD ".byte 0x0f, 0x01, 0xda"
280 #define SVM_VMRUN  ".byte 0x0f, 0x01, 0xd8"
281 #define SVM_VMSAVE ".byte 0x0f, 0x01, 0xdb"
282 #define SVM_CLGI   ".byte 0x0f, 0x01, 0xdd"
283 #define SVM_STGI   ".byte 0x0f, 0x01, 0xdc"
284 #define SVM_INVLPGA ".byte 0x0f, 0x01, 0xdf"
285 
286 #endif
287