1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __SVM_H 3 #define __SVM_H 4 5 #include <uapi/asm/svm.h> 6 #include <uapi/asm/kvm.h> 7 8 /* 9 * 32-bit intercept words in the VMCB Control Area, starting 10 * at Byte offset 000h. 11 */ 12 13 enum intercept_words { 14 INTERCEPT_CR = 0, 15 INTERCEPT_DR, 16 INTERCEPT_EXCEPTION, 17 INTERCEPT_WORD3, 18 INTERCEPT_WORD4, 19 INTERCEPT_WORD5, 20 MAX_INTERCEPT, 21 }; 22 23 enum { 24 /* Byte offset 000h (word 0) */ 25 INTERCEPT_CR0_READ = 0, 26 INTERCEPT_CR3_READ = 3, 27 INTERCEPT_CR4_READ = 4, 28 INTERCEPT_CR8_READ = 8, 29 INTERCEPT_CR0_WRITE = 16, 30 INTERCEPT_CR3_WRITE = 16 + 3, 31 INTERCEPT_CR4_WRITE = 16 + 4, 32 INTERCEPT_CR8_WRITE = 16 + 8, 33 /* Byte offset 004h (word 1) */ 34 INTERCEPT_DR0_READ = 32, 35 INTERCEPT_DR1_READ, 36 INTERCEPT_DR2_READ, 37 INTERCEPT_DR3_READ, 38 INTERCEPT_DR4_READ, 39 INTERCEPT_DR5_READ, 40 INTERCEPT_DR6_READ, 41 INTERCEPT_DR7_READ, 42 INTERCEPT_DR0_WRITE = 48, 43 INTERCEPT_DR1_WRITE, 44 INTERCEPT_DR2_WRITE, 45 INTERCEPT_DR3_WRITE, 46 INTERCEPT_DR4_WRITE, 47 INTERCEPT_DR5_WRITE, 48 INTERCEPT_DR6_WRITE, 49 INTERCEPT_DR7_WRITE, 50 /* Byte offset 008h (word 2) */ 51 INTERCEPT_EXCEPTION_OFFSET = 64, 52 /* Byte offset 00Ch (word 3) */ 53 INTERCEPT_INTR = 96, 54 INTERCEPT_NMI, 55 INTERCEPT_SMI, 56 INTERCEPT_INIT, 57 INTERCEPT_VINTR, 58 INTERCEPT_SELECTIVE_CR0, 59 INTERCEPT_STORE_IDTR, 60 INTERCEPT_STORE_GDTR, 61 INTERCEPT_STORE_LDTR, 62 INTERCEPT_STORE_TR, 63 INTERCEPT_LOAD_IDTR, 64 INTERCEPT_LOAD_GDTR, 65 INTERCEPT_LOAD_LDTR, 66 INTERCEPT_LOAD_TR, 67 INTERCEPT_RDTSC, 68 INTERCEPT_RDPMC, 69 INTERCEPT_PUSHF, 70 INTERCEPT_POPF, 71 INTERCEPT_CPUID, 72 INTERCEPT_RSM, 73 INTERCEPT_IRET, 74 INTERCEPT_INTn, 75 INTERCEPT_INVD, 76 INTERCEPT_PAUSE, 77 INTERCEPT_HLT, 78 INTERCEPT_INVLPG, 79 INTERCEPT_INVLPGA, 80 INTERCEPT_IOIO_PROT, 81 INTERCEPT_MSR_PROT, 82 INTERCEPT_TASK_SWITCH, 83 INTERCEPT_FERR_FREEZE, 84 INTERCEPT_SHUTDOWN, 85 /* Byte offset 010h (word 4) */ 86 INTERCEPT_VMRUN = 128, 87 INTERCEPT_VMMCALL, 88 INTERCEPT_VMLOAD, 89 INTERCEPT_VMSAVE, 90 INTERCEPT_STGI, 91 INTERCEPT_CLGI, 92 INTERCEPT_SKINIT, 93 INTERCEPT_RDTSCP, 94 INTERCEPT_ICEBP, 95 INTERCEPT_WBINVD, 96 INTERCEPT_MONITOR, 97 INTERCEPT_MWAIT, 98 INTERCEPT_MWAIT_COND, 99 INTERCEPT_XSETBV, 100 INTERCEPT_RDPRU, 101 TRAP_EFER_WRITE, 102 TRAP_CR0_WRITE, 103 TRAP_CR1_WRITE, 104 TRAP_CR2_WRITE, 105 TRAP_CR3_WRITE, 106 TRAP_CR4_WRITE, 107 TRAP_CR5_WRITE, 108 TRAP_CR6_WRITE, 109 TRAP_CR7_WRITE, 110 TRAP_CR8_WRITE, 111 /* Byte offset 014h (word 5) */ 112 INTERCEPT_INVLPGB = 160, 113 INTERCEPT_INVLPGB_ILLEGAL, 114 INTERCEPT_INVPCID, 115 INTERCEPT_MCOMMIT, 116 INTERCEPT_TLBSYNC, 117 }; 118 119 120 struct __attribute__ ((__packed__)) vmcb_control_area { 121 u32 intercepts[MAX_INTERCEPT]; 122 u32 reserved_1[15 - MAX_INTERCEPT]; 123 u16 pause_filter_thresh; 124 u16 pause_filter_count; 125 u64 iopm_base_pa; 126 u64 msrpm_base_pa; 127 u64 tsc_offset; 128 u32 asid; 129 u8 tlb_ctl; 130 u8 reserved_2[3]; 131 u32 int_ctl; 132 u32 int_vector; 133 u32 int_state; 134 u8 reserved_3[4]; 135 u32 exit_code; 136 u32 exit_code_hi; 137 u64 exit_info_1; 138 u64 exit_info_2; 139 u32 exit_int_info; 140 u32 exit_int_info_err; 141 u64 nested_ctl; 142 u64 avic_vapic_bar; 143 u64 ghcb_gpa; 144 u32 event_inj; 145 u32 event_inj_err; 146 u64 nested_cr3; 147 u64 virt_ext; 148 u32 clean; 149 u32 reserved_5; 150 u64 next_rip; 151 u8 insn_len; 152 u8 insn_bytes[15]; 153 u64 avic_backing_page; /* Offset 0xe0 */ 154 u8 reserved_6[8]; /* Offset 0xe8 */ 155 u64 avic_logical_id; /* Offset 0xf0 */ 156 u64 avic_physical_id; /* Offset 0xf8 */ 157 u8 reserved_7[8]; 158 u64 vmsa_pa; /* Used for an SEV-ES guest */ 159 u8 reserved_8[720]; 160 /* 161 * Offset 0x3e0, 32 bytes reserved 162 * for use by hypervisor/software. 163 */ 164 u8 reserved_sw[32]; 165 }; 166 167 168 #define TLB_CONTROL_DO_NOTHING 0 169 #define TLB_CONTROL_FLUSH_ALL_ASID 1 170 #define TLB_CONTROL_FLUSH_ASID 3 171 #define TLB_CONTROL_FLUSH_ASID_LOCAL 7 172 173 #define V_TPR_MASK 0x0f 174 175 #define V_IRQ_SHIFT 8 176 #define V_IRQ_MASK (1 << V_IRQ_SHIFT) 177 178 #define V_GIF_SHIFT 9 179 #define V_GIF_MASK (1 << V_GIF_SHIFT) 180 181 #define V_INTR_PRIO_SHIFT 16 182 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT) 183 184 #define V_IGN_TPR_SHIFT 20 185 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT) 186 187 #define V_IRQ_INJECTION_BITS_MASK (V_IRQ_MASK | V_INTR_PRIO_MASK | V_IGN_TPR_MASK) 188 189 #define V_INTR_MASKING_SHIFT 24 190 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT) 191 192 #define V_GIF_ENABLE_SHIFT 25 193 #define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT) 194 195 #define AVIC_ENABLE_SHIFT 31 196 #define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT) 197 198 #define LBR_CTL_ENABLE_MASK BIT_ULL(0) 199 #define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1) 200 201 #define SVM_INTERRUPT_SHADOW_MASK BIT_ULL(0) 202 #define SVM_GUEST_INTERRUPT_MASK BIT_ULL(1) 203 204 #define SVM_IOIO_STR_SHIFT 2 205 #define SVM_IOIO_REP_SHIFT 3 206 #define SVM_IOIO_SIZE_SHIFT 4 207 #define SVM_IOIO_ASIZE_SHIFT 7 208 209 #define SVM_IOIO_TYPE_MASK 1 210 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT) 211 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT) 212 #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT) 213 #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT) 214 215 #define SVM_VM_CR_VALID_MASK 0x001fULL 216 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL 217 #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL 218 219 #define SVM_NESTED_CTL_NP_ENABLE BIT(0) 220 #define SVM_NESTED_CTL_SEV_ENABLE BIT(1) 221 #define SVM_NESTED_CTL_SEV_ES_ENABLE BIT(2) 222 223 224 #define SVM_TSC_RATIO_RSVD 0xffffff0000000000ULL 225 #define SVM_TSC_RATIO_MIN 0x0000000000000001ULL 226 #define SVM_TSC_RATIO_MAX 0x000000ffffffffffULL 227 #define SVM_TSC_RATIO_DEFAULT 0x0100000000ULL 228 229 230 /* AVIC */ 231 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFFULL) 232 #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31 233 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31) 234 235 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK GENMASK_ULL(11, 0) 236 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12) 237 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62) 238 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63) 239 #define AVIC_PHYSICAL_ID_TABLE_SIZE_MASK (0xFFULL) 240 241 #define AVIC_DOORBELL_PHYSICAL_ID_MASK GENMASK_ULL(11, 0) 242 243 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL 244 245 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1 246 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0 247 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF 248 249 enum avic_ipi_failure_cause { 250 AVIC_IPI_FAILURE_INVALID_INT_TYPE, 251 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING, 252 AVIC_IPI_FAILURE_INVALID_TARGET, 253 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE, 254 }; 255 256 257 /* 258 * 0xff is broadcast, so the max index allowed for physical APIC ID 259 * table is 0xfe. APIC IDs above 0xff are reserved. 260 */ 261 #define AVIC_MAX_PHYSICAL_ID_COUNT 0xff 262 263 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF) 264 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL 265 266 267 struct vmcb_seg { 268 u16 selector; 269 u16 attrib; 270 u32 limit; 271 u64 base; 272 } __packed; 273 274 struct vmcb_save_area { 275 struct vmcb_seg es; 276 struct vmcb_seg cs; 277 struct vmcb_seg ss; 278 struct vmcb_seg ds; 279 struct vmcb_seg fs; 280 struct vmcb_seg gs; 281 struct vmcb_seg gdtr; 282 struct vmcb_seg ldtr; 283 struct vmcb_seg idtr; 284 struct vmcb_seg tr; 285 u8 reserved_1[43]; 286 u8 cpl; 287 u8 reserved_2[4]; 288 u64 efer; 289 u8 reserved_3[104]; 290 u64 xss; /* Valid for SEV-ES only */ 291 u64 cr4; 292 u64 cr3; 293 u64 cr0; 294 u64 dr7; 295 u64 dr6; 296 u64 rflags; 297 u64 rip; 298 u8 reserved_4[88]; 299 u64 rsp; 300 u8 reserved_5[24]; 301 u64 rax; 302 u64 star; 303 u64 lstar; 304 u64 cstar; 305 u64 sfmask; 306 u64 kernel_gs_base; 307 u64 sysenter_cs; 308 u64 sysenter_esp; 309 u64 sysenter_eip; 310 u64 cr2; 311 u8 reserved_6[32]; 312 u64 g_pat; 313 u64 dbgctl; 314 u64 br_from; 315 u64 br_to; 316 u64 last_excp_from; 317 u64 last_excp_to; 318 319 /* 320 * The following part of the save area is valid only for 321 * SEV-ES guests when referenced through the GHCB or for 322 * saving to the host save area. 323 */ 324 u8 reserved_7[72]; 325 u32 spec_ctrl; /* Guest version of SPEC_CTRL at 0x2E0 */ 326 u8 reserved_7b[4]; 327 u32 pkru; 328 u8 reserved_7a[20]; 329 u64 reserved_8; /* rax already available at 0x01f8 */ 330 u64 rcx; 331 u64 rdx; 332 u64 rbx; 333 u64 reserved_9; /* rsp already available at 0x01d8 */ 334 u64 rbp; 335 u64 rsi; 336 u64 rdi; 337 u64 r8; 338 u64 r9; 339 u64 r10; 340 u64 r11; 341 u64 r12; 342 u64 r13; 343 u64 r14; 344 u64 r15; 345 u8 reserved_10[16]; 346 u64 sw_exit_code; 347 u64 sw_exit_info_1; 348 u64 sw_exit_info_2; 349 u64 sw_scratch; 350 u8 reserved_11[56]; 351 u64 xcr0; 352 u8 valid_bitmap[16]; 353 u64 x87_state_gpa; 354 } __packed; 355 356 struct ghcb { 357 struct vmcb_save_area save; 358 u8 reserved_save[2048 - sizeof(struct vmcb_save_area)]; 359 360 u8 shared_buffer[2032]; 361 362 u8 reserved_1[10]; 363 u16 protocol_version; /* negotiated SEV-ES/GHCB protocol version */ 364 u32 ghcb_usage; 365 } __packed; 366 367 368 #define EXPECTED_VMCB_SAVE_AREA_SIZE 1032 369 #define EXPECTED_VMCB_CONTROL_AREA_SIZE 1024 370 #define EXPECTED_GHCB_SIZE PAGE_SIZE 371 372 static inline void __unused_size_checks(void) 373 { 374 BUILD_BUG_ON(sizeof(struct vmcb_save_area) != EXPECTED_VMCB_SAVE_AREA_SIZE); 375 BUILD_BUG_ON(sizeof(struct vmcb_control_area) != EXPECTED_VMCB_CONTROL_AREA_SIZE); 376 BUILD_BUG_ON(sizeof(struct ghcb) != EXPECTED_GHCB_SIZE); 377 } 378 379 struct vmcb { 380 struct vmcb_control_area control; 381 struct vmcb_save_area save; 382 } __packed; 383 384 #define SVM_CPUID_FUNC 0x8000000a 385 386 #define SVM_VM_CR_SVM_DISABLE 4 387 388 #define SVM_SELECTOR_S_SHIFT 4 389 #define SVM_SELECTOR_DPL_SHIFT 5 390 #define SVM_SELECTOR_P_SHIFT 7 391 #define SVM_SELECTOR_AVL_SHIFT 8 392 #define SVM_SELECTOR_L_SHIFT 9 393 #define SVM_SELECTOR_DB_SHIFT 10 394 #define SVM_SELECTOR_G_SHIFT 11 395 396 #define SVM_SELECTOR_TYPE_MASK (0xf) 397 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT) 398 #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT) 399 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT) 400 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT) 401 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT) 402 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT) 403 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT) 404 405 #define SVM_SELECTOR_WRITE_MASK (1 << 1) 406 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK 407 #define SVM_SELECTOR_CODE_MASK (1 << 3) 408 409 #define SVM_EVTINJ_VEC_MASK 0xff 410 411 #define SVM_EVTINJ_TYPE_SHIFT 8 412 #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT) 413 414 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT) 415 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT) 416 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT) 417 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT) 418 419 #define SVM_EVTINJ_VALID (1 << 31) 420 #define SVM_EVTINJ_VALID_ERR (1 << 11) 421 422 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK 423 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK 424 425 #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR 426 #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI 427 #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT 428 #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT 429 430 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID 431 #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR 432 433 #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36 434 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38 435 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44 436 437 #define SVM_EXITINFO_REG_MASK 0x0F 438 439 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP) 440 441 /* GHCB Accessor functions */ 442 443 #define GHCB_BITMAP_IDX(field) \ 444 (offsetof(struct vmcb_save_area, field) / sizeof(u64)) 445 446 #define DEFINE_GHCB_ACCESSORS(field) \ 447 static inline bool ghcb_##field##_is_valid(const struct ghcb *ghcb) \ 448 { \ 449 return test_bit(GHCB_BITMAP_IDX(field), \ 450 (unsigned long *)&ghcb->save.valid_bitmap); \ 451 } \ 452 \ 453 static inline u64 ghcb_get_##field(struct ghcb *ghcb) \ 454 { \ 455 return ghcb->save.field; \ 456 } \ 457 \ 458 static inline u64 ghcb_get_##field##_if_valid(struct ghcb *ghcb) \ 459 { \ 460 return ghcb_##field##_is_valid(ghcb) ? ghcb->save.field : 0; \ 461 } \ 462 \ 463 static inline void ghcb_set_##field(struct ghcb *ghcb, u64 value) \ 464 { \ 465 __set_bit(GHCB_BITMAP_IDX(field), \ 466 (unsigned long *)&ghcb->save.valid_bitmap); \ 467 ghcb->save.field = value; \ 468 } 469 470 DEFINE_GHCB_ACCESSORS(cpl) 471 DEFINE_GHCB_ACCESSORS(rip) 472 DEFINE_GHCB_ACCESSORS(rsp) 473 DEFINE_GHCB_ACCESSORS(rax) 474 DEFINE_GHCB_ACCESSORS(rcx) 475 DEFINE_GHCB_ACCESSORS(rdx) 476 DEFINE_GHCB_ACCESSORS(rbx) 477 DEFINE_GHCB_ACCESSORS(rbp) 478 DEFINE_GHCB_ACCESSORS(rsi) 479 DEFINE_GHCB_ACCESSORS(rdi) 480 DEFINE_GHCB_ACCESSORS(r8) 481 DEFINE_GHCB_ACCESSORS(r9) 482 DEFINE_GHCB_ACCESSORS(r10) 483 DEFINE_GHCB_ACCESSORS(r11) 484 DEFINE_GHCB_ACCESSORS(r12) 485 DEFINE_GHCB_ACCESSORS(r13) 486 DEFINE_GHCB_ACCESSORS(r14) 487 DEFINE_GHCB_ACCESSORS(r15) 488 DEFINE_GHCB_ACCESSORS(sw_exit_code) 489 DEFINE_GHCB_ACCESSORS(sw_exit_info_1) 490 DEFINE_GHCB_ACCESSORS(sw_exit_info_2) 491 DEFINE_GHCB_ACCESSORS(sw_scratch) 492 DEFINE_GHCB_ACCESSORS(xcr0) 493 494 #endif 495