1 #ifndef _ASM_X86_SPINLOCK_H 2 #define _ASM_X86_SPINLOCK_H 3 4 #include <linux/atomic.h> 5 #include <asm/page.h> 6 #include <asm/processor.h> 7 #include <linux/compiler.h> 8 #include <asm/paravirt.h> 9 /* 10 * Your basic SMP spinlocks, allowing only a single CPU anywhere 11 * 12 * Simple spin lock operations. There are two variants, one clears IRQ's 13 * on the local processor, one does not. 14 * 15 * These are fair FIFO ticket locks, which are currently limited to 256 16 * CPUs. 17 * 18 * (the type definitions are in asm/spinlock_types.h) 19 */ 20 21 #ifdef CONFIG_X86_32 22 # define LOCK_PTR_REG "a" 23 # define REG_PTR_MODE "k" 24 #else 25 # define LOCK_PTR_REG "D" 26 # define REG_PTR_MODE "q" 27 #endif 28 29 #if defined(CONFIG_X86_32) && \ 30 (defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE)) 31 /* 32 * On PPro SMP or if we are using OOSTORE, we use a locked operation to unlock 33 * (PPro errata 66, 92) 34 */ 35 # define UNLOCK_LOCK_PREFIX LOCK_PREFIX 36 #else 37 # define UNLOCK_LOCK_PREFIX 38 #endif 39 40 /* 41 * Ticket locks are conceptually two parts, one indicating the current head of 42 * the queue, and the other indicating the current tail. The lock is acquired 43 * by atomically noting the tail and incrementing it by one (thus adding 44 * ourself to the queue and noting our position), then waiting until the head 45 * becomes equal to the the initial value of the tail. 46 * 47 * We use an xadd covering *both* parts of the lock, to increment the tail and 48 * also load the position of the head, which takes care of memory ordering 49 * issues and should be optimal for the uncontended case. Note the tail must be 50 * in the high part, because a wide xadd increment of the low part would carry 51 * up and contaminate the high part. 52 */ 53 static __always_inline void __ticket_spin_lock(arch_spinlock_t *lock) 54 { 55 register struct __raw_tickets inc = { .tail = 1 }; 56 57 inc = xadd(&lock->tickets, inc); 58 59 for (;;) { 60 if (inc.head == inc.tail) 61 break; 62 cpu_relax(); 63 inc.head = ACCESS_ONCE(lock->tickets.head); 64 } 65 barrier(); /* make sure nothing creeps before the lock is taken */ 66 } 67 68 static __always_inline int __ticket_spin_trylock(arch_spinlock_t *lock) 69 { 70 arch_spinlock_t old, new; 71 72 old.tickets = ACCESS_ONCE(lock->tickets); 73 if (old.tickets.head != old.tickets.tail) 74 return 0; 75 76 new.head_tail = old.head_tail + (1 << TICKET_SHIFT); 77 78 /* cmpxchg is a full barrier, so nothing can move before it */ 79 return cmpxchg(&lock->head_tail, old.head_tail, new.head_tail) == old.head_tail; 80 } 81 82 static __always_inline void __ticket_spin_unlock(arch_spinlock_t *lock) 83 { 84 __add(&lock->tickets.head, 1, UNLOCK_LOCK_PREFIX); 85 } 86 87 static inline int __ticket_spin_is_locked(arch_spinlock_t *lock) 88 { 89 struct __raw_tickets tmp = ACCESS_ONCE(lock->tickets); 90 91 return tmp.tail != tmp.head; 92 } 93 94 static inline int __ticket_spin_is_contended(arch_spinlock_t *lock) 95 { 96 struct __raw_tickets tmp = ACCESS_ONCE(lock->tickets); 97 98 return (__ticket_t)(tmp.tail - tmp.head) > 1; 99 } 100 101 #ifndef CONFIG_PARAVIRT_SPINLOCKS 102 103 static inline int arch_spin_is_locked(arch_spinlock_t *lock) 104 { 105 return __ticket_spin_is_locked(lock); 106 } 107 108 static inline int arch_spin_is_contended(arch_spinlock_t *lock) 109 { 110 return __ticket_spin_is_contended(lock); 111 } 112 #define arch_spin_is_contended arch_spin_is_contended 113 114 static __always_inline void arch_spin_lock(arch_spinlock_t *lock) 115 { 116 __ticket_spin_lock(lock); 117 } 118 119 static __always_inline int arch_spin_trylock(arch_spinlock_t *lock) 120 { 121 return __ticket_spin_trylock(lock); 122 } 123 124 static __always_inline void arch_spin_unlock(arch_spinlock_t *lock) 125 { 126 __ticket_spin_unlock(lock); 127 } 128 129 static __always_inline void arch_spin_lock_flags(arch_spinlock_t *lock, 130 unsigned long flags) 131 { 132 arch_spin_lock(lock); 133 } 134 135 #endif /* CONFIG_PARAVIRT_SPINLOCKS */ 136 137 static inline void arch_spin_unlock_wait(arch_spinlock_t *lock) 138 { 139 while (arch_spin_is_locked(lock)) 140 cpu_relax(); 141 } 142 143 /* 144 * Read-write spinlocks, allowing multiple readers 145 * but only one writer. 146 * 147 * NOTE! it is quite common to have readers in interrupts 148 * but no interrupt writers. For those circumstances we 149 * can "mix" irq-safe locks - any writer needs to get a 150 * irq-safe write-lock, but readers can get non-irqsafe 151 * read-locks. 152 * 153 * On x86, we implement read-write locks as a 32-bit counter 154 * with the high bit (sign) being the "contended" bit. 155 */ 156 157 /** 158 * read_can_lock - would read_trylock() succeed? 159 * @lock: the rwlock in question. 160 */ 161 static inline int arch_read_can_lock(arch_rwlock_t *lock) 162 { 163 return lock->lock > 0; 164 } 165 166 /** 167 * write_can_lock - would write_trylock() succeed? 168 * @lock: the rwlock in question. 169 */ 170 static inline int arch_write_can_lock(arch_rwlock_t *lock) 171 { 172 return lock->write == WRITE_LOCK_CMP; 173 } 174 175 static inline void arch_read_lock(arch_rwlock_t *rw) 176 { 177 asm volatile(LOCK_PREFIX READ_LOCK_SIZE(dec) " (%0)\n\t" 178 "jns 1f\n" 179 "call __read_lock_failed\n\t" 180 "1:\n" 181 ::LOCK_PTR_REG (rw) : "memory"); 182 } 183 184 static inline void arch_write_lock(arch_rwlock_t *rw) 185 { 186 asm volatile(LOCK_PREFIX WRITE_LOCK_SUB(%1) "(%0)\n\t" 187 "jz 1f\n" 188 "call __write_lock_failed\n\t" 189 "1:\n" 190 ::LOCK_PTR_REG (&rw->write), "i" (RW_LOCK_BIAS) 191 : "memory"); 192 } 193 194 static inline int arch_read_trylock(arch_rwlock_t *lock) 195 { 196 READ_LOCK_ATOMIC(t) *count = (READ_LOCK_ATOMIC(t) *)lock; 197 198 if (READ_LOCK_ATOMIC(dec_return)(count) >= 0) 199 return 1; 200 READ_LOCK_ATOMIC(inc)(count); 201 return 0; 202 } 203 204 static inline int arch_write_trylock(arch_rwlock_t *lock) 205 { 206 atomic_t *count = (atomic_t *)&lock->write; 207 208 if (atomic_sub_and_test(WRITE_LOCK_CMP, count)) 209 return 1; 210 atomic_add(WRITE_LOCK_CMP, count); 211 return 0; 212 } 213 214 static inline void arch_read_unlock(arch_rwlock_t *rw) 215 { 216 asm volatile(LOCK_PREFIX READ_LOCK_SIZE(inc) " %0" 217 :"+m" (rw->lock) : : "memory"); 218 } 219 220 static inline void arch_write_unlock(arch_rwlock_t *rw) 221 { 222 asm volatile(LOCK_PREFIX WRITE_LOCK_ADD(%1) "%0" 223 : "+m" (rw->write) : "i" (RW_LOCK_BIAS) : "memory"); 224 } 225 226 #define arch_read_lock_flags(lock, flags) arch_read_lock(lock) 227 #define arch_write_lock_flags(lock, flags) arch_write_lock(lock) 228 229 #undef READ_LOCK_SIZE 230 #undef READ_LOCK_ATOMIC 231 #undef WRITE_LOCK_ADD 232 #undef WRITE_LOCK_SUB 233 #undef WRITE_LOCK_CMP 234 235 #define arch_spin_relax(lock) cpu_relax() 236 #define arch_read_relax(lock) cpu_relax() 237 #define arch_write_relax(lock) cpu_relax() 238 239 /* The {read|write|spin}_lock() on x86 are full memory barriers. */ 240 static inline void smp_mb__after_lock(void) { } 241 #define ARCH_HAS_SMP_MB_AFTER_LOCK 242 243 #endif /* _ASM_X86_SPINLOCK_H */ 244