11965aae3SH. Peter Anvin #ifndef _ASM_X86_SPINLOCK_H 21965aae3SH. Peter Anvin #define _ASM_X86_SPINLOCK_H 3bb898558SAl Viro 4bb898558SAl Viro #include <asm/atomic.h> 5bb898558SAl Viro #include <asm/page.h> 6bb898558SAl Viro #include <asm/processor.h> 7bb898558SAl Viro #include <linux/compiler.h> 8bb898558SAl Viro #include <asm/paravirt.h> 9bb898558SAl Viro /* 10bb898558SAl Viro * Your basic SMP spinlocks, allowing only a single CPU anywhere 11bb898558SAl Viro * 12bb898558SAl Viro * Simple spin lock operations. There are two variants, one clears IRQ's 13bb898558SAl Viro * on the local processor, one does not. 14bb898558SAl Viro * 15bb898558SAl Viro * These are fair FIFO ticket locks, which are currently limited to 256 16bb898558SAl Viro * CPUs. 17bb898558SAl Viro * 18bb898558SAl Viro * (the type definitions are in asm/spinlock_types.h) 19bb898558SAl Viro */ 20bb898558SAl Viro 21bb898558SAl Viro #ifdef CONFIG_X86_32 22bb898558SAl Viro # define LOCK_PTR_REG "a" 23bb898558SAl Viro # define REG_PTR_MODE "k" 24bb898558SAl Viro #else 25bb898558SAl Viro # define LOCK_PTR_REG "D" 26bb898558SAl Viro # define REG_PTR_MODE "q" 27bb898558SAl Viro #endif 28bb898558SAl Viro 29bb898558SAl Viro #if defined(CONFIG_X86_32) && \ 30bb898558SAl Viro (defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE)) 31bb898558SAl Viro /* 32bb898558SAl Viro * On PPro SMP or if we are using OOSTORE, we use a locked operation to unlock 33bb898558SAl Viro * (PPro errata 66, 92) 34bb898558SAl Viro */ 35bb898558SAl Viro # define UNLOCK_LOCK_PREFIX LOCK_PREFIX 36bb898558SAl Viro #else 37bb898558SAl Viro # define UNLOCK_LOCK_PREFIX 38bb898558SAl Viro #endif 39bb898558SAl Viro 40bb898558SAl Viro /* 41bb898558SAl Viro * Ticket locks are conceptually two parts, one indicating the current head of 42bb898558SAl Viro * the queue, and the other indicating the current tail. The lock is acquired 43bb898558SAl Viro * by atomically noting the tail and incrementing it by one (thus adding 44bb898558SAl Viro * ourself to the queue and noting our position), then waiting until the head 45bb898558SAl Viro * becomes equal to the the initial value of the tail. 46bb898558SAl Viro * 47bb898558SAl Viro * We use an xadd covering *both* parts of the lock, to increment the tail and 48bb898558SAl Viro * also load the position of the head, which takes care of memory ordering 49bb898558SAl Viro * issues and should be optimal for the uncontended case. Note the tail must be 50bb898558SAl Viro * in the high part, because a wide xadd increment of the low part would carry 51bb898558SAl Viro * up and contaminate the high part. 52bb898558SAl Viro * 53bb898558SAl Viro * With fewer than 2^8 possible CPUs, we can use x86's partial registers to 54bb898558SAl Viro * save some instructions and make the code more elegant. There really isn't 55bb898558SAl Viro * much between them in performance though, especially as locks are out of line. 56bb898558SAl Viro */ 57bb898558SAl Viro #if (NR_CPUS < 256) 58bb898558SAl Viro #define TICKET_SHIFT 8 59bb898558SAl Viro 60445c8951SThomas Gleixner static __always_inline void __ticket_spin_lock(arch_spinlock_t *lock) 61bb898558SAl Viro { 62bb898558SAl Viro short inc = 0x0100; 63bb898558SAl Viro 64bb898558SAl Viro asm volatile ( 65bb898558SAl Viro LOCK_PREFIX "xaddw %w0, %1\n" 66bb898558SAl Viro "1:\t" 67bb898558SAl Viro "cmpb %h0, %b0\n\t" 68bb898558SAl Viro "je 2f\n\t" 69bb898558SAl Viro "rep ; nop\n\t" 70bb898558SAl Viro "movb %1, %b0\n\t" 71bb898558SAl Viro /* don't need lfence here, because loads are in-order */ 72bb898558SAl Viro "jmp 1b\n" 73bb898558SAl Viro "2:" 74bb898558SAl Viro : "+Q" (inc), "+m" (lock->slock) 75bb898558SAl Viro : 76bb898558SAl Viro : "memory", "cc"); 77bb898558SAl Viro } 78bb898558SAl Viro 79445c8951SThomas Gleixner static __always_inline int __ticket_spin_trylock(arch_spinlock_t *lock) 80bb898558SAl Viro { 81bb898558SAl Viro int tmp, new; 82bb898558SAl Viro 83bb898558SAl Viro asm volatile("movzwl %2, %0\n\t" 84bb898558SAl Viro "cmpb %h0,%b0\n\t" 85bb898558SAl Viro "leal 0x100(%" REG_PTR_MODE "0), %1\n\t" 86bb898558SAl Viro "jne 1f\n\t" 87bb898558SAl Viro LOCK_PREFIX "cmpxchgw %w1,%2\n\t" 88bb898558SAl Viro "1:" 89bb898558SAl Viro "sete %b1\n\t" 90bb898558SAl Viro "movzbl %b1,%0\n\t" 91bb898558SAl Viro : "=&a" (tmp), "=&q" (new), "+m" (lock->slock) 92bb898558SAl Viro : 93bb898558SAl Viro : "memory", "cc"); 94bb898558SAl Viro 95bb898558SAl Viro return tmp; 96bb898558SAl Viro } 97bb898558SAl Viro 98445c8951SThomas Gleixner static __always_inline void __ticket_spin_unlock(arch_spinlock_t *lock) 99bb898558SAl Viro { 100bb898558SAl Viro asm volatile(UNLOCK_LOCK_PREFIX "incb %0" 101bb898558SAl Viro : "+m" (lock->slock) 102bb898558SAl Viro : 103bb898558SAl Viro : "memory", "cc"); 104bb898558SAl Viro } 105bb898558SAl Viro #else 106bb898558SAl Viro #define TICKET_SHIFT 16 107bb898558SAl Viro 108445c8951SThomas Gleixner static __always_inline void __ticket_spin_lock(arch_spinlock_t *lock) 109bb898558SAl Viro { 110bb898558SAl Viro int inc = 0x00010000; 111bb898558SAl Viro int tmp; 112bb898558SAl Viro 113bb898558SAl Viro asm volatile(LOCK_PREFIX "xaddl %0, %1\n" 114bb898558SAl Viro "movzwl %w0, %2\n\t" 115bb898558SAl Viro "shrl $16, %0\n\t" 116bb898558SAl Viro "1:\t" 117bb898558SAl Viro "cmpl %0, %2\n\t" 118bb898558SAl Viro "je 2f\n\t" 119bb898558SAl Viro "rep ; nop\n\t" 120bb898558SAl Viro "movzwl %1, %2\n\t" 121bb898558SAl Viro /* don't need lfence here, because loads are in-order */ 122bb898558SAl Viro "jmp 1b\n" 123bb898558SAl Viro "2:" 124bb898558SAl Viro : "+r" (inc), "+m" (lock->slock), "=&r" (tmp) 125bb898558SAl Viro : 126bb898558SAl Viro : "memory", "cc"); 127bb898558SAl Viro } 128bb898558SAl Viro 129445c8951SThomas Gleixner static __always_inline int __ticket_spin_trylock(arch_spinlock_t *lock) 130bb898558SAl Viro { 131bb898558SAl Viro int tmp; 132bb898558SAl Viro int new; 133bb898558SAl Viro 134bb898558SAl Viro asm volatile("movl %2,%0\n\t" 135bb898558SAl Viro "movl %0,%1\n\t" 136bb898558SAl Viro "roll $16, %0\n\t" 137bb898558SAl Viro "cmpl %0,%1\n\t" 138bb898558SAl Viro "leal 0x00010000(%" REG_PTR_MODE "0), %1\n\t" 139bb898558SAl Viro "jne 1f\n\t" 140bb898558SAl Viro LOCK_PREFIX "cmpxchgl %1,%2\n\t" 141bb898558SAl Viro "1:" 142bb898558SAl Viro "sete %b1\n\t" 143bb898558SAl Viro "movzbl %b1,%0\n\t" 144bb898558SAl Viro : "=&a" (tmp), "=&q" (new), "+m" (lock->slock) 145bb898558SAl Viro : 146bb898558SAl Viro : "memory", "cc"); 147bb898558SAl Viro 148bb898558SAl Viro return tmp; 149bb898558SAl Viro } 150bb898558SAl Viro 151445c8951SThomas Gleixner static __always_inline void __ticket_spin_unlock(arch_spinlock_t *lock) 152bb898558SAl Viro { 153bb898558SAl Viro asm volatile(UNLOCK_LOCK_PREFIX "incw %0" 154bb898558SAl Viro : "+m" (lock->slock) 155bb898558SAl Viro : 156bb898558SAl Viro : "memory", "cc"); 157bb898558SAl Viro } 158bb898558SAl Viro #endif 159bb898558SAl Viro 160445c8951SThomas Gleixner static inline int __ticket_spin_is_locked(arch_spinlock_t *lock) 161bb898558SAl Viro { 162bb898558SAl Viro int tmp = ACCESS_ONCE(lock->slock); 163bb898558SAl Viro 164bb898558SAl Viro return !!(((tmp >> TICKET_SHIFT) ^ tmp) & ((1 << TICKET_SHIFT) - 1)); 165bb898558SAl Viro } 166bb898558SAl Viro 167445c8951SThomas Gleixner static inline int __ticket_spin_is_contended(arch_spinlock_t *lock) 168bb898558SAl Viro { 169bb898558SAl Viro int tmp = ACCESS_ONCE(lock->slock); 170bb898558SAl Viro 171bb898558SAl Viro return (((tmp >> TICKET_SHIFT) - tmp) & ((1 << TICKET_SHIFT) - 1)) > 1; 172bb898558SAl Viro } 173bb898558SAl Viro 174b4ecc126SJeremy Fitzhardinge #ifndef CONFIG_PARAVIRT_SPINLOCKS 175bb898558SAl Viro 1760199c4e6SThomas Gleixner static inline int arch_spin_is_locked(arch_spinlock_t *lock) 177bb898558SAl Viro { 178bb898558SAl Viro return __ticket_spin_is_locked(lock); 179bb898558SAl Viro } 180bb898558SAl Viro 1810199c4e6SThomas Gleixner static inline int arch_spin_is_contended(arch_spinlock_t *lock) 182bb898558SAl Viro { 183bb898558SAl Viro return __ticket_spin_is_contended(lock); 184bb898558SAl Viro } 1850199c4e6SThomas Gleixner #define arch_spin_is_contended arch_spin_is_contended 186bb898558SAl Viro 1870199c4e6SThomas Gleixner static __always_inline void arch_spin_lock(arch_spinlock_t *lock) 188bb898558SAl Viro { 189bb898558SAl Viro __ticket_spin_lock(lock); 190bb898558SAl Viro } 191bb898558SAl Viro 1920199c4e6SThomas Gleixner static __always_inline int arch_spin_trylock(arch_spinlock_t *lock) 193bb898558SAl Viro { 194bb898558SAl Viro return __ticket_spin_trylock(lock); 195bb898558SAl Viro } 196bb898558SAl Viro 1970199c4e6SThomas Gleixner static __always_inline void arch_spin_unlock(arch_spinlock_t *lock) 198bb898558SAl Viro { 199bb898558SAl Viro __ticket_spin_unlock(lock); 200bb898558SAl Viro } 201bb898558SAl Viro 2020199c4e6SThomas Gleixner static __always_inline void arch_spin_lock_flags(arch_spinlock_t *lock, 203bb898558SAl Viro unsigned long flags) 204bb898558SAl Viro { 2050199c4e6SThomas Gleixner arch_spin_lock(lock); 206bb898558SAl Viro } 207bb898558SAl Viro 208b4ecc126SJeremy Fitzhardinge #endif /* CONFIG_PARAVIRT_SPINLOCKS */ 209bb898558SAl Viro 2100199c4e6SThomas Gleixner static inline void arch_spin_unlock_wait(arch_spinlock_t *lock) 211bb898558SAl Viro { 2120199c4e6SThomas Gleixner while (arch_spin_is_locked(lock)) 213bb898558SAl Viro cpu_relax(); 214bb898558SAl Viro } 215bb898558SAl Viro 216bb898558SAl Viro /* 217bb898558SAl Viro * Read-write spinlocks, allowing multiple readers 218bb898558SAl Viro * but only one writer. 219bb898558SAl Viro * 220bb898558SAl Viro * NOTE! it is quite common to have readers in interrupts 221bb898558SAl Viro * but no interrupt writers. For those circumstances we 222bb898558SAl Viro * can "mix" irq-safe locks - any writer needs to get a 223bb898558SAl Viro * irq-safe write-lock, but readers can get non-irqsafe 224bb898558SAl Viro * read-locks. 225bb898558SAl Viro * 226bb898558SAl Viro * On x86, we implement read-write locks as a 32-bit counter 227bb898558SAl Viro * with the high bit (sign) being the "contended" bit. 228bb898558SAl Viro */ 229bb898558SAl Viro 230bb898558SAl Viro /** 231bb898558SAl Viro * read_can_lock - would read_trylock() succeed? 232bb898558SAl Viro * @lock: the rwlock in question. 233bb898558SAl Viro */ 234e5931943SThomas Gleixner static inline int arch_read_can_lock(arch_rwlock_t *lock) 235bb898558SAl Viro { 236a750036fSJan Beulich return lock->lock > 0; 237bb898558SAl Viro } 238bb898558SAl Viro 239bb898558SAl Viro /** 240bb898558SAl Viro * write_can_lock - would write_trylock() succeed? 241bb898558SAl Viro * @lock: the rwlock in question. 242bb898558SAl Viro */ 243e5931943SThomas Gleixner static inline int arch_write_can_lock(arch_rwlock_t *lock) 244bb898558SAl Viro { 245a750036fSJan Beulich return lock->write == WRITE_LOCK_CMP; 246bb898558SAl Viro } 247bb898558SAl Viro 248e5931943SThomas Gleixner static inline void arch_read_lock(arch_rwlock_t *rw) 249bb898558SAl Viro { 250a750036fSJan Beulich asm volatile(LOCK_PREFIX READ_LOCK_SIZE(dec) " (%0)\n\t" 251bb898558SAl Viro "jns 1f\n" 252bb898558SAl Viro "call __read_lock_failed\n\t" 253bb898558SAl Viro "1:\n" 254bb898558SAl Viro ::LOCK_PTR_REG (rw) : "memory"); 255bb898558SAl Viro } 256bb898558SAl Viro 257e5931943SThomas Gleixner static inline void arch_write_lock(arch_rwlock_t *rw) 258bb898558SAl Viro { 259a750036fSJan Beulich asm volatile(LOCK_PREFIX WRITE_LOCK_SUB(%1) "(%0)\n\t" 260bb898558SAl Viro "jz 1f\n" 261bb898558SAl Viro "call __write_lock_failed\n\t" 262bb898558SAl Viro "1:\n" 263a750036fSJan Beulich ::LOCK_PTR_REG (&rw->write), "i" (RW_LOCK_BIAS) 264a750036fSJan Beulich : "memory"); 265bb898558SAl Viro } 266bb898558SAl Viro 267e5931943SThomas Gleixner static inline int arch_read_trylock(arch_rwlock_t *lock) 268bb898558SAl Viro { 269a750036fSJan Beulich READ_LOCK_ATOMIC(t) *count = (READ_LOCK_ATOMIC(t) *)lock; 270bb898558SAl Viro 271a750036fSJan Beulich if (READ_LOCK_ATOMIC(dec_return)(count) >= 0) 272bb898558SAl Viro return 1; 273a750036fSJan Beulich READ_LOCK_ATOMIC(inc)(count); 274bb898558SAl Viro return 0; 275bb898558SAl Viro } 276bb898558SAl Viro 277e5931943SThomas Gleixner static inline int arch_write_trylock(arch_rwlock_t *lock) 278bb898558SAl Viro { 279a750036fSJan Beulich atomic_t *count = (atomic_t *)&lock->write; 280bb898558SAl Viro 281a750036fSJan Beulich if (atomic_sub_and_test(WRITE_LOCK_CMP, count)) 282bb898558SAl Viro return 1; 283a750036fSJan Beulich atomic_add(WRITE_LOCK_CMP, count); 284bb898558SAl Viro return 0; 285bb898558SAl Viro } 286bb898558SAl Viro 287e5931943SThomas Gleixner static inline void arch_read_unlock(arch_rwlock_t *rw) 288bb898558SAl Viro { 289a750036fSJan Beulich asm volatile(LOCK_PREFIX READ_LOCK_SIZE(inc) " %0" 290a750036fSJan Beulich :"+m" (rw->lock) : : "memory"); 291bb898558SAl Viro } 292bb898558SAl Viro 293e5931943SThomas Gleixner static inline void arch_write_unlock(arch_rwlock_t *rw) 294bb898558SAl Viro { 295a750036fSJan Beulich asm volatile(LOCK_PREFIX WRITE_LOCK_ADD(%1) "%0" 296a750036fSJan Beulich : "+m" (rw->write) : "i" (RW_LOCK_BIAS) : "memory"); 297bb898558SAl Viro } 298bb898558SAl Viro 299e5931943SThomas Gleixner #define arch_read_lock_flags(lock, flags) arch_read_lock(lock) 300e5931943SThomas Gleixner #define arch_write_lock_flags(lock, flags) arch_write_lock(lock) 301f5f7eac4SRobin Holt 302a750036fSJan Beulich #undef READ_LOCK_SIZE 303a750036fSJan Beulich #undef READ_LOCK_ATOMIC 304a750036fSJan Beulich #undef WRITE_LOCK_ADD 305a750036fSJan Beulich #undef WRITE_LOCK_SUB 306a750036fSJan Beulich #undef WRITE_LOCK_CMP 307a750036fSJan Beulich 3080199c4e6SThomas Gleixner #define arch_spin_relax(lock) cpu_relax() 3090199c4e6SThomas Gleixner #define arch_read_relax(lock) cpu_relax() 3100199c4e6SThomas Gleixner #define arch_write_relax(lock) cpu_relax() 311bb898558SAl Viro 312ad462769SJiri Olsa /* The {read|write|spin}_lock() on x86 are full memory barriers. */ 313ad462769SJiri Olsa static inline void smp_mb__after_lock(void) { } 314ad462769SJiri Olsa #define ARCH_HAS_SMP_MB_AFTER_LOCK 315ad462769SJiri Olsa 3161965aae3SH. Peter Anvin #endif /* _ASM_X86_SPINLOCK_H */ 317