11965aae3SH. Peter Anvin #ifndef _ASM_X86_SPINLOCK_H 21965aae3SH. Peter Anvin #define _ASM_X86_SPINLOCK_H 3bb898558SAl Viro 4bb898558SAl Viro #include <asm/atomic.h> 5bb898558SAl Viro #include <asm/rwlock.h> 6bb898558SAl Viro #include <asm/page.h> 7bb898558SAl Viro #include <asm/processor.h> 8bb898558SAl Viro #include <linux/compiler.h> 9bb898558SAl Viro #include <asm/paravirt.h> 10bb898558SAl Viro /* 11bb898558SAl Viro * Your basic SMP spinlocks, allowing only a single CPU anywhere 12bb898558SAl Viro * 13bb898558SAl Viro * Simple spin lock operations. There are two variants, one clears IRQ's 14bb898558SAl Viro * on the local processor, one does not. 15bb898558SAl Viro * 16bb898558SAl Viro * These are fair FIFO ticket locks, which are currently limited to 256 17bb898558SAl Viro * CPUs. 18bb898558SAl Viro * 19bb898558SAl Viro * (the type definitions are in asm/spinlock_types.h) 20bb898558SAl Viro */ 21bb898558SAl Viro 22bb898558SAl Viro #ifdef CONFIG_X86_32 23bb898558SAl Viro # define LOCK_PTR_REG "a" 24bb898558SAl Viro # define REG_PTR_MODE "k" 25bb898558SAl Viro #else 26bb898558SAl Viro # define LOCK_PTR_REG "D" 27bb898558SAl Viro # define REG_PTR_MODE "q" 28bb898558SAl Viro #endif 29bb898558SAl Viro 30bb898558SAl Viro #if defined(CONFIG_X86_32) && \ 31bb898558SAl Viro (defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE)) 32bb898558SAl Viro /* 33bb898558SAl Viro * On PPro SMP or if we are using OOSTORE, we use a locked operation to unlock 34bb898558SAl Viro * (PPro errata 66, 92) 35bb898558SAl Viro */ 36bb898558SAl Viro # define UNLOCK_LOCK_PREFIX LOCK_PREFIX 37bb898558SAl Viro #else 38bb898558SAl Viro # define UNLOCK_LOCK_PREFIX 39bb898558SAl Viro #endif 40bb898558SAl Viro 41bb898558SAl Viro /* 42bb898558SAl Viro * Ticket locks are conceptually two parts, one indicating the current head of 43bb898558SAl Viro * the queue, and the other indicating the current tail. The lock is acquired 44bb898558SAl Viro * by atomically noting the tail and incrementing it by one (thus adding 45bb898558SAl Viro * ourself to the queue and noting our position), then waiting until the head 46bb898558SAl Viro * becomes equal to the the initial value of the tail. 47bb898558SAl Viro * 48bb898558SAl Viro * We use an xadd covering *both* parts of the lock, to increment the tail and 49bb898558SAl Viro * also load the position of the head, which takes care of memory ordering 50bb898558SAl Viro * issues and should be optimal for the uncontended case. Note the tail must be 51bb898558SAl Viro * in the high part, because a wide xadd increment of the low part would carry 52bb898558SAl Viro * up and contaminate the high part. 53bb898558SAl Viro * 54bb898558SAl Viro * With fewer than 2^8 possible CPUs, we can use x86's partial registers to 55bb898558SAl Viro * save some instructions and make the code more elegant. There really isn't 56bb898558SAl Viro * much between them in performance though, especially as locks are out of line. 57bb898558SAl Viro */ 58bb898558SAl Viro #if (NR_CPUS < 256) 59bb898558SAl Viro #define TICKET_SHIFT 8 60bb898558SAl Viro 61445c8951SThomas Gleixner static __always_inline void __ticket_spin_lock(arch_spinlock_t *lock) 62bb898558SAl Viro { 63bb898558SAl Viro short inc = 0x0100; 64bb898558SAl Viro 65bb898558SAl Viro asm volatile ( 66bb898558SAl Viro LOCK_PREFIX "xaddw %w0, %1\n" 67bb898558SAl Viro "1:\t" 68bb898558SAl Viro "cmpb %h0, %b0\n\t" 69bb898558SAl Viro "je 2f\n\t" 70bb898558SAl Viro "rep ; nop\n\t" 71bb898558SAl Viro "movb %1, %b0\n\t" 72bb898558SAl Viro /* don't need lfence here, because loads are in-order */ 73bb898558SAl Viro "jmp 1b\n" 74bb898558SAl Viro "2:" 75bb898558SAl Viro : "+Q" (inc), "+m" (lock->slock) 76bb898558SAl Viro : 77bb898558SAl Viro : "memory", "cc"); 78bb898558SAl Viro } 79bb898558SAl Viro 80445c8951SThomas Gleixner static __always_inline int __ticket_spin_trylock(arch_spinlock_t *lock) 81bb898558SAl Viro { 82bb898558SAl Viro int tmp, new; 83bb898558SAl Viro 84bb898558SAl Viro asm volatile("movzwl %2, %0\n\t" 85bb898558SAl Viro "cmpb %h0,%b0\n\t" 86bb898558SAl Viro "leal 0x100(%" REG_PTR_MODE "0), %1\n\t" 87bb898558SAl Viro "jne 1f\n\t" 88bb898558SAl Viro LOCK_PREFIX "cmpxchgw %w1,%2\n\t" 89bb898558SAl Viro "1:" 90bb898558SAl Viro "sete %b1\n\t" 91bb898558SAl Viro "movzbl %b1,%0\n\t" 92bb898558SAl Viro : "=&a" (tmp), "=&q" (new), "+m" (lock->slock) 93bb898558SAl Viro : 94bb898558SAl Viro : "memory", "cc"); 95bb898558SAl Viro 96bb898558SAl Viro return tmp; 97bb898558SAl Viro } 98bb898558SAl Viro 99445c8951SThomas Gleixner static __always_inline void __ticket_spin_unlock(arch_spinlock_t *lock) 100bb898558SAl Viro { 101bb898558SAl Viro asm volatile(UNLOCK_LOCK_PREFIX "incb %0" 102bb898558SAl Viro : "+m" (lock->slock) 103bb898558SAl Viro : 104bb898558SAl Viro : "memory", "cc"); 105bb898558SAl Viro } 106bb898558SAl Viro #else 107bb898558SAl Viro #define TICKET_SHIFT 16 108bb898558SAl Viro 109445c8951SThomas Gleixner static __always_inline void __ticket_spin_lock(arch_spinlock_t *lock) 110bb898558SAl Viro { 111bb898558SAl Viro int inc = 0x00010000; 112bb898558SAl Viro int tmp; 113bb898558SAl Viro 114bb898558SAl Viro asm volatile(LOCK_PREFIX "xaddl %0, %1\n" 115bb898558SAl Viro "movzwl %w0, %2\n\t" 116bb898558SAl Viro "shrl $16, %0\n\t" 117bb898558SAl Viro "1:\t" 118bb898558SAl Viro "cmpl %0, %2\n\t" 119bb898558SAl Viro "je 2f\n\t" 120bb898558SAl Viro "rep ; nop\n\t" 121bb898558SAl Viro "movzwl %1, %2\n\t" 122bb898558SAl Viro /* don't need lfence here, because loads are in-order */ 123bb898558SAl Viro "jmp 1b\n" 124bb898558SAl Viro "2:" 125bb898558SAl Viro : "+r" (inc), "+m" (lock->slock), "=&r" (tmp) 126bb898558SAl Viro : 127bb898558SAl Viro : "memory", "cc"); 128bb898558SAl Viro } 129bb898558SAl Viro 130445c8951SThomas Gleixner static __always_inline int __ticket_spin_trylock(arch_spinlock_t *lock) 131bb898558SAl Viro { 132bb898558SAl Viro int tmp; 133bb898558SAl Viro int new; 134bb898558SAl Viro 135bb898558SAl Viro asm volatile("movl %2,%0\n\t" 136bb898558SAl Viro "movl %0,%1\n\t" 137bb898558SAl Viro "roll $16, %0\n\t" 138bb898558SAl Viro "cmpl %0,%1\n\t" 139bb898558SAl Viro "leal 0x00010000(%" REG_PTR_MODE "0), %1\n\t" 140bb898558SAl Viro "jne 1f\n\t" 141bb898558SAl Viro LOCK_PREFIX "cmpxchgl %1,%2\n\t" 142bb898558SAl Viro "1:" 143bb898558SAl Viro "sete %b1\n\t" 144bb898558SAl Viro "movzbl %b1,%0\n\t" 145bb898558SAl Viro : "=&a" (tmp), "=&q" (new), "+m" (lock->slock) 146bb898558SAl Viro : 147bb898558SAl Viro : "memory", "cc"); 148bb898558SAl Viro 149bb898558SAl Viro return tmp; 150bb898558SAl Viro } 151bb898558SAl Viro 152445c8951SThomas Gleixner static __always_inline void __ticket_spin_unlock(arch_spinlock_t *lock) 153bb898558SAl Viro { 154bb898558SAl Viro asm volatile(UNLOCK_LOCK_PREFIX "incw %0" 155bb898558SAl Viro : "+m" (lock->slock) 156bb898558SAl Viro : 157bb898558SAl Viro : "memory", "cc"); 158bb898558SAl Viro } 159bb898558SAl Viro #endif 160bb898558SAl Viro 161445c8951SThomas Gleixner static inline int __ticket_spin_is_locked(arch_spinlock_t *lock) 162bb898558SAl Viro { 163bb898558SAl Viro int tmp = ACCESS_ONCE(lock->slock); 164bb898558SAl Viro 165bb898558SAl Viro return !!(((tmp >> TICKET_SHIFT) ^ tmp) & ((1 << TICKET_SHIFT) - 1)); 166bb898558SAl Viro } 167bb898558SAl Viro 168445c8951SThomas Gleixner static inline int __ticket_spin_is_contended(arch_spinlock_t *lock) 169bb898558SAl Viro { 170bb898558SAl Viro int tmp = ACCESS_ONCE(lock->slock); 171bb898558SAl Viro 172bb898558SAl Viro return (((tmp >> TICKET_SHIFT) - tmp) & ((1 << TICKET_SHIFT) - 1)) > 1; 173bb898558SAl Viro } 174bb898558SAl Viro 175b4ecc126SJeremy Fitzhardinge #ifndef CONFIG_PARAVIRT_SPINLOCKS 176bb898558SAl Viro 177445c8951SThomas Gleixner static inline int __raw_spin_is_locked(arch_spinlock_t *lock) 178bb898558SAl Viro { 179bb898558SAl Viro return __ticket_spin_is_locked(lock); 180bb898558SAl Viro } 181bb898558SAl Viro 182445c8951SThomas Gleixner static inline int __raw_spin_is_contended(arch_spinlock_t *lock) 183bb898558SAl Viro { 184bb898558SAl Viro return __ticket_spin_is_contended(lock); 185bb898558SAl Viro } 186a5ef7ca0SKyle McMartin #define __raw_spin_is_contended __raw_spin_is_contended 187bb898558SAl Viro 188445c8951SThomas Gleixner static __always_inline void __raw_spin_lock(arch_spinlock_t *lock) 189bb898558SAl Viro { 190bb898558SAl Viro __ticket_spin_lock(lock); 191bb898558SAl Viro } 192bb898558SAl Viro 193445c8951SThomas Gleixner static __always_inline int __raw_spin_trylock(arch_spinlock_t *lock) 194bb898558SAl Viro { 195bb898558SAl Viro return __ticket_spin_trylock(lock); 196bb898558SAl Viro } 197bb898558SAl Viro 198445c8951SThomas Gleixner static __always_inline void __raw_spin_unlock(arch_spinlock_t *lock) 199bb898558SAl Viro { 200bb898558SAl Viro __ticket_spin_unlock(lock); 201bb898558SAl Viro } 202bb898558SAl Viro 203445c8951SThomas Gleixner static __always_inline void __raw_spin_lock_flags(arch_spinlock_t *lock, 204bb898558SAl Viro unsigned long flags) 205bb898558SAl Viro { 206bb898558SAl Viro __raw_spin_lock(lock); 207bb898558SAl Viro } 208bb898558SAl Viro 209b4ecc126SJeremy Fitzhardinge #endif /* CONFIG_PARAVIRT_SPINLOCKS */ 210bb898558SAl Viro 211445c8951SThomas Gleixner static inline void __raw_spin_unlock_wait(arch_spinlock_t *lock) 212bb898558SAl Viro { 213bb898558SAl Viro while (__raw_spin_is_locked(lock)) 214bb898558SAl Viro cpu_relax(); 215bb898558SAl Viro } 216bb898558SAl Viro 217bb898558SAl Viro /* 218bb898558SAl Viro * Read-write spinlocks, allowing multiple readers 219bb898558SAl Viro * but only one writer. 220bb898558SAl Viro * 221bb898558SAl Viro * NOTE! it is quite common to have readers in interrupts 222bb898558SAl Viro * but no interrupt writers. For those circumstances we 223bb898558SAl Viro * can "mix" irq-safe locks - any writer needs to get a 224bb898558SAl Viro * irq-safe write-lock, but readers can get non-irqsafe 225bb898558SAl Viro * read-locks. 226bb898558SAl Viro * 227bb898558SAl Viro * On x86, we implement read-write locks as a 32-bit counter 228bb898558SAl Viro * with the high bit (sign) being the "contended" bit. 229bb898558SAl Viro */ 230bb898558SAl Viro 231bb898558SAl Viro /** 232bb898558SAl Viro * read_can_lock - would read_trylock() succeed? 233bb898558SAl Viro * @lock: the rwlock in question. 234bb898558SAl Viro */ 235bb898558SAl Viro static inline int __raw_read_can_lock(raw_rwlock_t *lock) 236bb898558SAl Viro { 237bb898558SAl Viro return (int)(lock)->lock > 0; 238bb898558SAl Viro } 239bb898558SAl Viro 240bb898558SAl Viro /** 241bb898558SAl Viro * write_can_lock - would write_trylock() succeed? 242bb898558SAl Viro * @lock: the rwlock in question. 243bb898558SAl Viro */ 244bb898558SAl Viro static inline int __raw_write_can_lock(raw_rwlock_t *lock) 245bb898558SAl Viro { 246bb898558SAl Viro return (lock)->lock == RW_LOCK_BIAS; 247bb898558SAl Viro } 248bb898558SAl Viro 249bb898558SAl Viro static inline void __raw_read_lock(raw_rwlock_t *rw) 250bb898558SAl Viro { 251bb898558SAl Viro asm volatile(LOCK_PREFIX " subl $1,(%0)\n\t" 252bb898558SAl Viro "jns 1f\n" 253bb898558SAl Viro "call __read_lock_failed\n\t" 254bb898558SAl Viro "1:\n" 255bb898558SAl Viro ::LOCK_PTR_REG (rw) : "memory"); 256bb898558SAl Viro } 257bb898558SAl Viro 258bb898558SAl Viro static inline void __raw_write_lock(raw_rwlock_t *rw) 259bb898558SAl Viro { 260bb898558SAl Viro asm volatile(LOCK_PREFIX " subl %1,(%0)\n\t" 261bb898558SAl Viro "jz 1f\n" 262bb898558SAl Viro "call __write_lock_failed\n\t" 263bb898558SAl Viro "1:\n" 264bb898558SAl Viro ::LOCK_PTR_REG (rw), "i" (RW_LOCK_BIAS) : "memory"); 265bb898558SAl Viro } 266bb898558SAl Viro 267bb898558SAl Viro static inline int __raw_read_trylock(raw_rwlock_t *lock) 268bb898558SAl Viro { 269bb898558SAl Viro atomic_t *count = (atomic_t *)lock; 270bb898558SAl Viro 2712d4d57dbSFrederic Weisbecker if (atomic_dec_return(count) >= 0) 272bb898558SAl Viro return 1; 273bb898558SAl Viro atomic_inc(count); 274bb898558SAl Viro return 0; 275bb898558SAl Viro } 276bb898558SAl Viro 277bb898558SAl Viro static inline int __raw_write_trylock(raw_rwlock_t *lock) 278bb898558SAl Viro { 279bb898558SAl Viro atomic_t *count = (atomic_t *)lock; 280bb898558SAl Viro 281bb898558SAl Viro if (atomic_sub_and_test(RW_LOCK_BIAS, count)) 282bb898558SAl Viro return 1; 283bb898558SAl Viro atomic_add(RW_LOCK_BIAS, count); 284bb898558SAl Viro return 0; 285bb898558SAl Viro } 286bb898558SAl Viro 287bb898558SAl Viro static inline void __raw_read_unlock(raw_rwlock_t *rw) 288bb898558SAl Viro { 289bb898558SAl Viro asm volatile(LOCK_PREFIX "incl %0" :"+m" (rw->lock) : : "memory"); 290bb898558SAl Viro } 291bb898558SAl Viro 292bb898558SAl Viro static inline void __raw_write_unlock(raw_rwlock_t *rw) 293bb898558SAl Viro { 294bb898558SAl Viro asm volatile(LOCK_PREFIX "addl %1, %0" 295bb898558SAl Viro : "+m" (rw->lock) : "i" (RW_LOCK_BIAS) : "memory"); 296bb898558SAl Viro } 297bb898558SAl Viro 298f5f7eac4SRobin Holt #define __raw_read_lock_flags(lock, flags) __raw_read_lock(lock) 299f5f7eac4SRobin Holt #define __raw_write_lock_flags(lock, flags) __raw_write_lock(lock) 300f5f7eac4SRobin Holt 301bb898558SAl Viro #define _raw_spin_relax(lock) cpu_relax() 302bb898558SAl Viro #define _raw_read_relax(lock) cpu_relax() 303bb898558SAl Viro #define _raw_write_relax(lock) cpu_relax() 304bb898558SAl Viro 305ad462769SJiri Olsa /* The {read|write|spin}_lock() on x86 are full memory barriers. */ 306ad462769SJiri Olsa static inline void smp_mb__after_lock(void) { } 307ad462769SJiri Olsa #define ARCH_HAS_SMP_MB_AFTER_LOCK 308ad462769SJiri Olsa 3091965aae3SH. Peter Anvin #endif /* _ASM_X86_SPINLOCK_H */ 310